1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
526 // There's never any support for operations beyond MVT::f32.
527 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
532 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
537 if (Subtarget->hasPOPCNT()) {
538 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
540 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
547 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
549 if (!Subtarget->hasMOVBE())
550 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
552 // These should be promoted to a larger select which is supported.
553 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554 // X86 wants to expand cmov itself.
555 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567 if (Subtarget->is64Bit()) {
568 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
571 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574 // support continuation, user-level threading, and etc.. As a result, no
575 // other SjLj exception interfaces are implemented and please don't build
576 // your own exception handling based on them.
577 // LLVM/Clang supports zero-cost DWARF exception handling.
578 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
582 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586 if (Subtarget->is64Bit())
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
597 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601 if (Subtarget->is64Bit()) {
602 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
607 if (Subtarget->hasSSE1())
608 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
610 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
612 // Expand certain atomics
613 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
615 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
620 if (Subtarget->hasCmpxchg16b()) {
621 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
624 // FIXME - use subtarget debug flags
625 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
630 if (Subtarget->is64Bit()) {
631 setExceptionPointerRegister(X86::RAX);
632 setExceptionSelectorRegister(X86::RDX);
634 setExceptionPointerRegister(X86::EAX);
635 setExceptionSelectorRegister(X86::EDX);
637 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
640 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
643 setOperationAction(ISD::TRAP, MVT::Other, Legal);
644 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
646 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647 setOperationAction(ISD::VASTART , MVT::Other, Custom);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650 // TargetInfo::X86_64ABIBuiltinVaList
651 setOperationAction(ISD::VAARG , MVT::Other, Custom);
652 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
654 // TargetInfo::CharPtrBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Expand);
656 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
662 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
663 MVT::i64 : MVT::i32, Custom);
665 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
666 // f32 and f64 use SSE.
667 // Set up the FP register classes.
668 addRegisterClass(MVT::f32, &X86::FR32RegClass);
669 addRegisterClass(MVT::f64, &X86::FR64RegClass);
671 // Use ANDPD to simulate FABS.
672 setOperationAction(ISD::FABS , MVT::f64, Custom);
673 setOperationAction(ISD::FABS , MVT::f32, Custom);
675 // Use XORP to simulate FNEG.
676 setOperationAction(ISD::FNEG , MVT::f64, Custom);
677 setOperationAction(ISD::FNEG , MVT::f32, Custom);
679 // Use ANDPD and ORPD to simulate FCOPYSIGN.
680 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
681 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
683 // Lower this to FGETSIGNx86 plus an AND.
684 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
685 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
687 // We don't support sin/cos/fmod
688 setOperationAction(ISD::FSIN , MVT::f64, Expand);
689 setOperationAction(ISD::FCOS , MVT::f64, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
691 setOperationAction(ISD::FSIN , MVT::f32, Expand);
692 setOperationAction(ISD::FCOS , MVT::f32, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
695 // Expand FP immediates into loads from the stack, except for the special
697 addLegalFPImmediate(APFloat(+0.0)); // xorpd
698 addLegalFPImmediate(APFloat(+0.0f)); // xorps
699 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
700 // Use SSE for f32, x87 for f64.
701 // Set up the FP register classes.
702 addRegisterClass(MVT::f32, &X86::FR32RegClass);
703 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
705 // Use ANDPS to simulate FABS.
706 setOperationAction(ISD::FABS , MVT::f32, Custom);
708 // Use XORP to simulate FNEG.
709 setOperationAction(ISD::FNEG , MVT::f32, Custom);
711 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
713 // Use ANDPS and ORPS to simulate FCOPYSIGN.
714 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
715 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
717 // We don't support sin/cos/fmod
718 setOperationAction(ISD::FSIN , MVT::f32, Expand);
719 setOperationAction(ISD::FCOS , MVT::f32, Expand);
720 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
722 // Special cases we handle for FP constants.
723 addLegalFPImmediate(APFloat(+0.0f)); // xorps
724 addLegalFPImmediate(APFloat(+0.0)); // FLD0
725 addLegalFPImmediate(APFloat(+1.0)); // FLD1
726 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
727 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
729 if (!TM.Options.UnsafeFPMath) {
730 setOperationAction(ISD::FSIN , MVT::f64, Expand);
731 setOperationAction(ISD::FCOS , MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
734 } else if (!TM.Options.UseSoftFloat) {
735 // f32 and f64 in x87.
736 // Set up the FP register classes.
737 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
738 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
740 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
741 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
743 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
745 if (!TM.Options.UnsafeFPMath) {
746 setOperationAction(ISD::FSIN , MVT::f64, Expand);
747 setOperationAction(ISD::FSIN , MVT::f32, Expand);
748 setOperationAction(ISD::FCOS , MVT::f64, Expand);
749 setOperationAction(ISD::FCOS , MVT::f32, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
751 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
753 addLegalFPImmediate(APFloat(+0.0)); // FLD0
754 addLegalFPImmediate(APFloat(+1.0)); // FLD1
755 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
756 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
757 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
758 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
759 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
760 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
763 // We don't support FMA.
764 setOperationAction(ISD::FMA, MVT::f64, Expand);
765 setOperationAction(ISD::FMA, MVT::f32, Expand);
767 // Long double always uses X87.
768 if (!TM.Options.UseSoftFloat) {
769 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
770 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
771 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
773 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
774 addLegalFPImmediate(TmpFlt); // FLD0
776 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
779 APFloat TmpFlt2(+1.0);
780 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
782 addLegalFPImmediate(TmpFlt2); // FLD1
783 TmpFlt2.changeSign();
784 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
787 if (!TM.Options.UnsafeFPMath) {
788 setOperationAction(ISD::FSIN , MVT::f80, Expand);
789 setOperationAction(ISD::FCOS , MVT::f80, Expand);
790 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
793 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
794 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
795 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
796 setOperationAction(ISD::FRINT, MVT::f80, Expand);
797 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
798 setOperationAction(ISD::FMA, MVT::f80, Expand);
801 // Always use a library call for pow.
802 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
804 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
806 setOperationAction(ISD::FLOG, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
808 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP, MVT::f80, Expand);
810 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
812 // First set operation action for all vector types to either promote
813 // (for widening) or expand (for scalarization). Then we will selectively
814 // turn on ones that can be effectively codegen'd.
815 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
816 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
817 MVT VT = (MVT::SimpleValueType)i;
818 setOperationAction(ISD::ADD , VT, Expand);
819 setOperationAction(ISD::SUB , VT, Expand);
820 setOperationAction(ISD::FADD, VT, Expand);
821 setOperationAction(ISD::FNEG, VT, Expand);
822 setOperationAction(ISD::FSUB, VT, Expand);
823 setOperationAction(ISD::MUL , VT, Expand);
824 setOperationAction(ISD::FMUL, VT, Expand);
825 setOperationAction(ISD::SDIV, VT, Expand);
826 setOperationAction(ISD::UDIV, VT, Expand);
827 setOperationAction(ISD::FDIV, VT, Expand);
828 setOperationAction(ISD::SREM, VT, Expand);
829 setOperationAction(ISD::UREM, VT, Expand);
830 setOperationAction(ISD::LOAD, VT, Expand);
831 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
834 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
836 setOperationAction(ISD::FABS, VT, Expand);
837 setOperationAction(ISD::FSIN, VT, Expand);
838 setOperationAction(ISD::FSINCOS, VT, Expand);
839 setOperationAction(ISD::FCOS, VT, Expand);
840 setOperationAction(ISD::FSINCOS, VT, Expand);
841 setOperationAction(ISD::FREM, VT, Expand);
842 setOperationAction(ISD::FMA, VT, Expand);
843 setOperationAction(ISD::FPOWI, VT, Expand);
844 setOperationAction(ISD::FSQRT, VT, Expand);
845 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
846 setOperationAction(ISD::FFLOOR, VT, Expand);
847 setOperationAction(ISD::FCEIL, VT, Expand);
848 setOperationAction(ISD::FTRUNC, VT, Expand);
849 setOperationAction(ISD::FRINT, VT, Expand);
850 setOperationAction(ISD::FNEARBYINT, VT, Expand);
851 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
852 setOperationAction(ISD::MULHS, VT, Expand);
853 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
854 setOperationAction(ISD::MULHU, VT, Expand);
855 setOperationAction(ISD::SDIVREM, VT, Expand);
856 setOperationAction(ISD::UDIVREM, VT, Expand);
857 setOperationAction(ISD::FPOW, VT, Expand);
858 setOperationAction(ISD::CTPOP, VT, Expand);
859 setOperationAction(ISD::CTTZ, VT, Expand);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
861 setOperationAction(ISD::CTLZ, VT, Expand);
862 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
863 setOperationAction(ISD::SHL, VT, Expand);
864 setOperationAction(ISD::SRA, VT, Expand);
865 setOperationAction(ISD::SRL, VT, Expand);
866 setOperationAction(ISD::ROTL, VT, Expand);
867 setOperationAction(ISD::ROTR, VT, Expand);
868 setOperationAction(ISD::BSWAP, VT, Expand);
869 setOperationAction(ISD::SETCC, VT, Expand);
870 setOperationAction(ISD::FLOG, VT, Expand);
871 setOperationAction(ISD::FLOG2, VT, Expand);
872 setOperationAction(ISD::FLOG10, VT, Expand);
873 setOperationAction(ISD::FEXP, VT, Expand);
874 setOperationAction(ISD::FEXP2, VT, Expand);
875 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
876 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
877 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
879 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
880 setOperationAction(ISD::TRUNCATE, VT, Expand);
881 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
882 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
883 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
884 setOperationAction(ISD::VSELECT, VT, Expand);
885 setOperationAction(ISD::SELECT_CC, VT, Expand);
886 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
887 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
888 setTruncStoreAction(VT,
889 (MVT::SimpleValueType)InnerVT, Expand);
890 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
891 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
893 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
894 // we have to deal with them whether we ask for Expansion or not. Setting
895 // Expand causes its own optimisation problems though, so leave them legal.
896 if (VT.getVectorElementType() == MVT::i1)
897 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
900 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
901 // with -msoft-float, disable use of MMX as well.
902 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
903 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
904 // No operations on x86mmx supported, everything uses intrinsics.
907 // MMX-sized vectors (other than x86mmx) are expected to be expanded
908 // into smaller operations.
909 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
910 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
911 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
912 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
913 setOperationAction(ISD::AND, MVT::v8i8, Expand);
914 setOperationAction(ISD::AND, MVT::v4i16, Expand);
915 setOperationAction(ISD::AND, MVT::v2i32, Expand);
916 setOperationAction(ISD::AND, MVT::v1i64, Expand);
917 setOperationAction(ISD::OR, MVT::v8i8, Expand);
918 setOperationAction(ISD::OR, MVT::v4i16, Expand);
919 setOperationAction(ISD::OR, MVT::v2i32, Expand);
920 setOperationAction(ISD::OR, MVT::v1i64, Expand);
921 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
922 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
923 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
924 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
930 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
931 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
932 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
933 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
939 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
940 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
942 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
943 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
944 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
945 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
947 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
948 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
949 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
950 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
951 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
952 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
953 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
956 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
957 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
959 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
960 // registers cannot be used even for integer operations.
961 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
962 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
963 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
964 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
966 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
967 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
968 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
969 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
971 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
972 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
974 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
975 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
976 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
977 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
978 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
979 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
980 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
981 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
982 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
983 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
984 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
986 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
987 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
990 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
991 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
992 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
995 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1001 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1002 MVT VT = (MVT::SimpleValueType)i;
1003 // Do not attempt to custom lower non-power-of-2 vectors
1004 if (!isPowerOf2_32(VT.getVectorNumElements()))
1006 // Do not attempt to custom lower non-128-bit vectors
1007 if (!VT.is128BitVector())
1009 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1010 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1014 // We support custom legalizing of sext and anyext loads for specific
1015 // memory vector types which we can load as a scalar (or sequence of
1016 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1017 // loads these must work with a single scalar load.
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1019 if (Subtarget->is64Bit()) {
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1034 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1037 if (Subtarget->is64Bit()) {
1038 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1039 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1042 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1043 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1044 MVT VT = (MVT::SimpleValueType)i;
1046 // Do not attempt to promote non-128-bit vectors
1047 if (!VT.is128BitVector())
1050 setOperationAction(ISD::AND, VT, Promote);
1051 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1052 setOperationAction(ISD::OR, VT, Promote);
1053 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1054 setOperationAction(ISD::XOR, VT, Promote);
1055 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1056 setOperationAction(ISD::LOAD, VT, Promote);
1057 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1058 setOperationAction(ISD::SELECT, VT, Promote);
1059 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1062 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1064 // Custom lower v2i64 and v2f64 selects.
1065 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1066 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1067 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1068 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1070 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1071 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1074 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1075 // As there is no 64-bit GPR available, we need build a special custom
1076 // sequence to convert from v2i32 to v2f32.
1077 if (!Subtarget->is64Bit())
1078 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1081 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1083 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1085 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1087 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1090 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1091 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1092 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1093 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1094 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1099 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1102 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1111 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1113 // FIXME: Do we need to handle scalar-to-vector here?
1114 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1116 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1120 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1121 // There is no BLENDI for byte vectors. We don't need to custom lower
1122 // some vselects for now.
1123 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1125 // SSE41 brings specific instructions for doing vector sign extend even in
1126 // cases where we don't have SRA.
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1129 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1131 // i8 and i16 vectors are custom , because the source register and source
1132 // source memory operand types are not the same width. f32 vectors are
1133 // custom since the immediate controlling the insert encodes additional
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1145 // FIXME: these should be Legal but thats only for the case where
1146 // the index is constant. For now custom expand to deal with that.
1147 if (Subtarget->is64Bit()) {
1148 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1153 if (Subtarget->hasSSE2()) {
1154 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1157 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1158 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1160 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1161 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1163 // In the customized shift lowering, the legal cases in AVX2 will be
1165 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1166 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1168 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1169 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1171 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1174 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1175 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1180 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1182 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1184 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1186 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1197 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1199 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1210 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1212 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1213 // even though v8i16 is a legal type.
1214 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1216 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1219 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1220 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1223 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1225 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1227 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1233 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1234 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1239 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1243 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1248 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1255 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1258 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1261 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1263 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1264 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1266 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1267 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1268 setOperationAction(ISD::FMA, MVT::f32, Legal);
1269 setOperationAction(ISD::FMA, MVT::f64, Legal);
1272 if (Subtarget->hasInt256()) {
1273 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1274 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1275 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1276 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1278 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1279 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1280 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1281 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1283 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1284 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1285 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1286 // Don't lower v32i8 because there is no 128-bit byte mul
1288 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1290 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1291 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1293 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1294 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1296 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1297 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1298 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1299 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1301 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1302 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1303 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1304 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1306 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1307 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1308 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1309 // Don't lower v32i8 because there is no 128-bit byte mul
1312 // In the customized shift lowering, the legal cases in AVX2 will be
1314 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1315 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1317 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1318 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1320 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1322 // Custom lower several nodes for 256-bit types.
1323 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1324 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1325 MVT VT = (MVT::SimpleValueType)i;
1327 // Extract subvector is special because the value type
1328 // (result) is 128-bit but the source is 256-bit wide.
1329 if (VT.is128BitVector())
1330 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1332 // Do not attempt to custom lower other non-256-bit vectors
1333 if (!VT.is256BitVector())
1336 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1337 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1338 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1340 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1341 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1342 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1345 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1346 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1347 MVT VT = (MVT::SimpleValueType)i;
1349 // Do not attempt to promote non-256-bit vectors
1350 if (!VT.is256BitVector())
1353 setOperationAction(ISD::AND, VT, Promote);
1354 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1355 setOperationAction(ISD::OR, VT, Promote);
1356 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1357 setOperationAction(ISD::XOR, VT, Promote);
1358 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1359 setOperationAction(ISD::LOAD, VT, Promote);
1360 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1361 setOperationAction(ISD::SELECT, VT, Promote);
1362 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1366 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1367 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1370 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1372 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1373 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1374 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1376 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1377 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1378 setOperationAction(ISD::XOR, MVT::i1, Legal);
1379 setOperationAction(ISD::OR, MVT::i1, Legal);
1380 setOperationAction(ISD::AND, MVT::i1, Legal);
1381 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1388 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1395 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1401 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1402 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1406 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1407 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1408 if (Subtarget->is64Bit()) {
1409 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1410 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1411 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1412 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1414 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1422 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1425 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1446 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1447 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1449 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1461 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1462 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1464 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1465 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1467 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1470 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1472 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1473 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1475 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1476 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1478 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1479 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1481 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1482 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1483 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1485 if (Subtarget->hasCDI()) {
1486 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1487 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1490 // Custom lower several nodes.
1491 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1492 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1493 MVT VT = (MVT::SimpleValueType)i;
1495 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1496 // Extract subvector is special because the value type
1497 // (result) is 256/128-bit but the source is 512-bit wide.
1498 if (VT.is128BitVector() || VT.is256BitVector())
1499 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1501 if (VT.getVectorElementType() == MVT::i1)
1502 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1504 // Do not attempt to custom lower other non-512-bit vectors
1505 if (!VT.is512BitVector())
1508 if ( EltSize >= 32) {
1509 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1510 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1511 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1512 setOperationAction(ISD::VSELECT, VT, Legal);
1513 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1514 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1515 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1518 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1519 MVT VT = (MVT::SimpleValueType)i;
1521 // Do not attempt to promote non-256-bit vectors
1522 if (!VT.is512BitVector())
1525 setOperationAction(ISD::SELECT, VT, Promote);
1526 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1530 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1531 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1532 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1536 // of this type with custom code.
1537 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1538 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1539 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1543 // We want to custom lower some of our intrinsics.
1544 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1545 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1546 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1547 if (!Subtarget->is64Bit())
1548 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1550 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1551 // handle type legalization for these operations here.
1553 // FIXME: We really should do custom legalization for addition and
1554 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1555 // than generic legalization for 64-bit multiplication-with-overflow, though.
1556 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1557 // Add/Sub/Mul with overflow operations are custom lowered.
1559 setOperationAction(ISD::SADDO, VT, Custom);
1560 setOperationAction(ISD::UADDO, VT, Custom);
1561 setOperationAction(ISD::SSUBO, VT, Custom);
1562 setOperationAction(ISD::USUBO, VT, Custom);
1563 setOperationAction(ISD::SMULO, VT, Custom);
1564 setOperationAction(ISD::UMULO, VT, Custom);
1567 // There are no 8-bit 3-address imul/mul instructions
1568 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1569 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1571 if (!Subtarget->is64Bit()) {
1572 // These libcalls are not available in 32-bit.
1573 setLibcallName(RTLIB::SHL_I128, nullptr);
1574 setLibcallName(RTLIB::SRL_I128, nullptr);
1575 setLibcallName(RTLIB::SRA_I128, nullptr);
1578 // Combine sin / cos into one node or libcall if possible.
1579 if (Subtarget->hasSinCos()) {
1580 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1581 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1582 if (Subtarget->isTargetDarwin()) {
1583 // For MacOSX, we don't want to the normal expansion of a libcall to
1584 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1586 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1587 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1591 if (Subtarget->isTargetWin64()) {
1592 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1593 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1594 setOperationAction(ISD::SREM, MVT::i128, Custom);
1595 setOperationAction(ISD::UREM, MVT::i128, Custom);
1596 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1597 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1600 // We have target-specific dag combine patterns for the following nodes:
1601 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1602 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1603 setTargetDAGCombine(ISD::VSELECT);
1604 setTargetDAGCombine(ISD::SELECT);
1605 setTargetDAGCombine(ISD::SHL);
1606 setTargetDAGCombine(ISD::SRA);
1607 setTargetDAGCombine(ISD::SRL);
1608 setTargetDAGCombine(ISD::OR);
1609 setTargetDAGCombine(ISD::AND);
1610 setTargetDAGCombine(ISD::ADD);
1611 setTargetDAGCombine(ISD::FADD);
1612 setTargetDAGCombine(ISD::FSUB);
1613 setTargetDAGCombine(ISD::FMA);
1614 setTargetDAGCombine(ISD::SUB);
1615 setTargetDAGCombine(ISD::LOAD);
1616 setTargetDAGCombine(ISD::STORE);
1617 setTargetDAGCombine(ISD::ZERO_EXTEND);
1618 setTargetDAGCombine(ISD::ANY_EXTEND);
1619 setTargetDAGCombine(ISD::SIGN_EXTEND);
1620 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1621 setTargetDAGCombine(ISD::TRUNCATE);
1622 setTargetDAGCombine(ISD::SINT_TO_FP);
1623 setTargetDAGCombine(ISD::SETCC);
1624 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1625 setTargetDAGCombine(ISD::BUILD_VECTOR);
1626 if (Subtarget->is64Bit())
1627 setTargetDAGCombine(ISD::MUL);
1628 setTargetDAGCombine(ISD::XOR);
1630 computeRegisterProperties();
1632 // On Darwin, -Os means optimize for size without hurting performance,
1633 // do not reduce the limit.
1634 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1635 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1636 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1637 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1638 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1639 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1640 setPrefLoopAlignment(4); // 2^4 bytes.
1642 // Predictable cmov don't hurt on atom because it's in-order.
1643 PredictableSelectIsExpensive = !Subtarget->isAtom();
1645 setPrefFunctionAlignment(4); // 2^4 bytes.
1648 // This has so far only been implemented for 64-bit MachO.
1649 bool X86TargetLowering::useLoadStackGuardNode() const {
1650 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1651 Subtarget->is64Bit();
1654 TargetLoweringBase::LegalizeTypeAction
1655 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1656 if (ExperimentalVectorWideningLegalization &&
1657 VT.getVectorNumElements() != 1 &&
1658 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1659 return TypeWidenVector;
1661 return TargetLoweringBase::getPreferredVectorAction(VT);
1664 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1666 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1668 if (Subtarget->hasAVX512())
1669 switch(VT.getVectorNumElements()) {
1670 case 8: return MVT::v8i1;
1671 case 16: return MVT::v16i1;
1674 return VT.changeVectorElementTypeToInteger();
1677 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1678 /// the desired ByVal argument alignment.
1679 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1682 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1683 if (VTy->getBitWidth() == 128)
1685 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1686 unsigned EltAlign = 0;
1687 getMaxByValAlign(ATy->getElementType(), EltAlign);
1688 if (EltAlign > MaxAlign)
1689 MaxAlign = EltAlign;
1690 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1691 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1692 unsigned EltAlign = 0;
1693 getMaxByValAlign(STy->getElementType(i), EltAlign);
1694 if (EltAlign > MaxAlign)
1695 MaxAlign = EltAlign;
1702 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1703 /// function arguments in the caller parameter area. For X86, aggregates
1704 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1705 /// are at 4-byte boundaries.
1706 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1707 if (Subtarget->is64Bit()) {
1708 // Max of 8 and alignment of type.
1709 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1716 if (Subtarget->hasSSE1())
1717 getMaxByValAlign(Ty, Align);
1721 /// getOptimalMemOpType - Returns the target specific optimal type for load
1722 /// and store operations as a result of memset, memcpy, and memmove
1723 /// lowering. If DstAlign is zero that means it's safe to destination
1724 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1725 /// means there isn't a need to check it against alignment requirement,
1726 /// probably because the source does not need to be loaded. If 'IsMemset' is
1727 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1728 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1729 /// source is constant so it does not need to be loaded.
1730 /// It returns EVT::Other if the type should be determined using generic
1731 /// target-independent logic.
1733 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1734 unsigned DstAlign, unsigned SrcAlign,
1735 bool IsMemset, bool ZeroMemset,
1737 MachineFunction &MF) const {
1738 const Function *F = MF.getFunction();
1739 if ((!IsMemset || ZeroMemset) &&
1740 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1741 Attribute::NoImplicitFloat)) {
1743 (Subtarget->isUnalignedMemAccessFast() ||
1744 ((DstAlign == 0 || DstAlign >= 16) &&
1745 (SrcAlign == 0 || SrcAlign >= 16)))) {
1747 if (Subtarget->hasInt256())
1749 if (Subtarget->hasFp256())
1752 if (Subtarget->hasSSE2())
1754 if (Subtarget->hasSSE1())
1756 } else if (!MemcpyStrSrc && Size >= 8 &&
1757 !Subtarget->is64Bit() &&
1758 Subtarget->hasSSE2()) {
1759 // Do not use f64 to lower memcpy if source is string constant. It's
1760 // better to use i32 to avoid the loads.
1764 if (Subtarget->is64Bit() && Size >= 8)
1769 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1771 return X86ScalarSSEf32;
1772 else if (VT == MVT::f64)
1773 return X86ScalarSSEf64;
1778 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1783 *Fast = Subtarget->isUnalignedMemAccessFast();
1787 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1788 /// current function. The returned value is a member of the
1789 /// MachineJumpTableInfo::JTEntryKind enum.
1790 unsigned X86TargetLowering::getJumpTableEncoding() const {
1791 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1793 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1794 Subtarget->isPICStyleGOT())
1795 return MachineJumpTableInfo::EK_Custom32;
1797 // Otherwise, use the normal jump table encoding heuristics.
1798 return TargetLowering::getJumpTableEncoding();
1802 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1803 const MachineBasicBlock *MBB,
1804 unsigned uid,MCContext &Ctx) const{
1805 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1806 Subtarget->isPICStyleGOT());
1807 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1809 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1810 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1813 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1815 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1816 SelectionDAG &DAG) const {
1817 if (!Subtarget->is64Bit())
1818 // This doesn't have SDLoc associated with it, but is not really the
1819 // same as a Register.
1820 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1824 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1825 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1827 const MCExpr *X86TargetLowering::
1828 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1829 MCContext &Ctx) const {
1830 // X86-64 uses RIP relative addressing based on the jump table label.
1831 if (Subtarget->isPICStyleRIPRel())
1832 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1834 // Otherwise, the reference is relative to the PIC base.
1835 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1838 // FIXME: Why this routine is here? Move to RegInfo!
1839 std::pair<const TargetRegisterClass*, uint8_t>
1840 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1841 const TargetRegisterClass *RRC = nullptr;
1843 switch (VT.SimpleTy) {
1845 return TargetLowering::findRepresentativeClass(VT);
1846 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1847 RRC = Subtarget->is64Bit() ?
1848 (const TargetRegisterClass*)&X86::GR64RegClass :
1849 (const TargetRegisterClass*)&X86::GR32RegClass;
1852 RRC = &X86::VR64RegClass;
1854 case MVT::f32: case MVT::f64:
1855 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1856 case MVT::v4f32: case MVT::v2f64:
1857 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1859 RRC = &X86::VR128RegClass;
1862 return std::make_pair(RRC, Cost);
1865 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1866 unsigned &Offset) const {
1867 if (!Subtarget->isTargetLinux())
1870 if (Subtarget->is64Bit()) {
1871 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1873 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1885 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1886 unsigned DestAS) const {
1887 assert(SrcAS != DestAS && "Expected different address spaces!");
1889 return SrcAS < 256 && DestAS < 256;
1892 //===----------------------------------------------------------------------===//
1893 // Return Value Calling Convention Implementation
1894 //===----------------------------------------------------------------------===//
1896 #include "X86GenCallingConv.inc"
1899 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1900 MachineFunction &MF, bool isVarArg,
1901 const SmallVectorImpl<ISD::OutputArg> &Outs,
1902 LLVMContext &Context) const {
1903 SmallVector<CCValAssign, 16> RVLocs;
1904 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
1906 return CCInfo.CheckReturn(Outs, RetCC_X86);
1909 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1910 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1915 X86TargetLowering::LowerReturn(SDValue Chain,
1916 CallingConv::ID CallConv, bool isVarArg,
1917 const SmallVectorImpl<ISD::OutputArg> &Outs,
1918 const SmallVectorImpl<SDValue> &OutVals,
1919 SDLoc dl, SelectionDAG &DAG) const {
1920 MachineFunction &MF = DAG.getMachineFunction();
1921 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1923 SmallVector<CCValAssign, 16> RVLocs;
1924 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
1925 RVLocs, *DAG.getContext());
1926 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1929 SmallVector<SDValue, 6> RetOps;
1930 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1931 // Operand #1 = Bytes To Pop
1932 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1935 // Copy the result values into the output registers.
1936 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1937 CCValAssign &VA = RVLocs[i];
1938 assert(VA.isRegLoc() && "Can only return in registers!");
1939 SDValue ValToCopy = OutVals[i];
1940 EVT ValVT = ValToCopy.getValueType();
1942 // Promote values to the appropriate types
1943 if (VA.getLocInfo() == CCValAssign::SExt)
1944 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1945 else if (VA.getLocInfo() == CCValAssign::ZExt)
1946 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1947 else if (VA.getLocInfo() == CCValAssign::AExt)
1948 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1949 else if (VA.getLocInfo() == CCValAssign::BCvt)
1950 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1952 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1953 "Unexpected FP-extend for return value.");
1955 // If this is x86-64, and we disabled SSE, we can't return FP values,
1956 // or SSE or MMX vectors.
1957 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1958 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1959 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1960 report_fatal_error("SSE register return with SSE disabled");
1962 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1963 // llvm-gcc has never done it right and no one has noticed, so this
1964 // should be OK for now.
1965 if (ValVT == MVT::f64 &&
1966 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1967 report_fatal_error("SSE2 register return with SSE2 disabled");
1969 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1970 // the RET instruction and handled by the FP Stackifier.
1971 if (VA.getLocReg() == X86::FP0 ||
1972 VA.getLocReg() == X86::FP1) {
1973 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1974 // change the value to the FP stack register class.
1975 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1976 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1977 RetOps.push_back(ValToCopy);
1978 // Don't emit a copytoreg.
1982 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1983 // which is returned in RAX / RDX.
1984 if (Subtarget->is64Bit()) {
1985 if (ValVT == MVT::x86mmx) {
1986 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1987 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1988 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1990 // If we don't have SSE2 available, convert to v4f32 so the generated
1991 // register is legal.
1992 if (!Subtarget->hasSSE2())
1993 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1998 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1999 Flag = Chain.getValue(1);
2000 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2003 // The x86-64 ABIs require that for returning structs by value we copy
2004 // the sret argument into %rax/%eax (depending on ABI) for the return.
2005 // Win32 requires us to put the sret argument to %eax as well.
2006 // We saved the argument into a virtual register in the entry block,
2007 // so now we copy the value out and into %rax/%eax.
2008 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2009 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2010 MachineFunction &MF = DAG.getMachineFunction();
2011 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2012 unsigned Reg = FuncInfo->getSRetReturnReg();
2014 "SRetReturnReg should have been set in LowerFormalArguments().");
2015 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2018 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2019 X86::RAX : X86::EAX;
2020 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2021 Flag = Chain.getValue(1);
2023 // RAX/EAX now acts like a return value.
2024 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2027 RetOps[0] = Chain; // Update chain.
2029 // Add the flag if we have it.
2031 RetOps.push_back(Flag);
2033 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2036 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2037 if (N->getNumValues() != 1)
2039 if (!N->hasNUsesOfValue(1, 0))
2042 SDValue TCChain = Chain;
2043 SDNode *Copy = *N->use_begin();
2044 if (Copy->getOpcode() == ISD::CopyToReg) {
2045 // If the copy has a glue operand, we conservatively assume it isn't safe to
2046 // perform a tail call.
2047 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2049 TCChain = Copy->getOperand(0);
2050 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2053 bool HasRet = false;
2054 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2056 if (UI->getOpcode() != X86ISD::RET_FLAG)
2069 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
2070 ISD::NodeType ExtendKind) const {
2072 // TODO: Is this also valid on 32-bit?
2073 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2074 ReturnMVT = MVT::i8;
2076 ReturnMVT = MVT::i32;
2078 MVT MinVT = getRegisterType(ReturnMVT);
2079 return VT.bitsLT(MinVT) ? MinVT : VT;
2082 /// LowerCallResult - Lower the result values of a call into the
2083 /// appropriate copies out of appropriate physical registers.
2086 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2087 CallingConv::ID CallConv, bool isVarArg,
2088 const SmallVectorImpl<ISD::InputArg> &Ins,
2089 SDLoc dl, SelectionDAG &DAG,
2090 SmallVectorImpl<SDValue> &InVals) const {
2092 // Assign locations to each value returned by this call.
2093 SmallVector<CCValAssign, 16> RVLocs;
2094 bool Is64Bit = Subtarget->is64Bit();
2095 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2096 DAG.getTarget(), RVLocs, *DAG.getContext());
2097 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2099 // Copy all of the result registers out of their specified physreg.
2100 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2101 CCValAssign &VA = RVLocs[i];
2102 EVT CopyVT = VA.getValVT();
2104 // If this is x86-64, and we disabled SSE, we can't return FP values
2105 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2106 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2107 report_fatal_error("SSE register return with SSE disabled");
2110 // If we prefer to use the value in xmm registers, copy it out as f80 and
2111 // use a truncate to move it from fp stack reg to xmm reg.
2112 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2113 isScalarFPTypeInSSEReg(VA.getValVT()))
2116 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2117 CopyVT, InFlag).getValue(1);
2118 SDValue Val = Chain.getValue(0);
2120 if (CopyVT != VA.getValVT())
2121 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2122 // This truncation won't change the value.
2123 DAG.getIntPtrConstant(1));
2125 InFlag = Chain.getValue(2);
2126 InVals.push_back(Val);
2132 //===----------------------------------------------------------------------===//
2133 // C & StdCall & Fast Calling Convention implementation
2134 //===----------------------------------------------------------------------===//
2135 // StdCall calling convention seems to be standard for many Windows' API
2136 // routines and around. It differs from C calling convention just a little:
2137 // callee should clean up the stack, not caller. Symbols should be also
2138 // decorated in some fancy way :) It doesn't support any vector arguments.
2139 // For info on fast calling convention see Fast Calling Convention (tail call)
2140 // implementation LowerX86_32FastCCCallTo.
2142 /// CallIsStructReturn - Determines whether a call uses struct return
2144 enum StructReturnType {
2149 static StructReturnType
2150 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2152 return NotStructReturn;
2154 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2155 if (!Flags.isSRet())
2156 return NotStructReturn;
2157 if (Flags.isInReg())
2158 return RegStructReturn;
2159 return StackStructReturn;
2162 /// ArgsAreStructReturn - Determines whether a function uses struct
2163 /// return semantics.
2164 static StructReturnType
2165 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2167 return NotStructReturn;
2169 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2170 if (!Flags.isSRet())
2171 return NotStructReturn;
2172 if (Flags.isInReg())
2173 return RegStructReturn;
2174 return StackStructReturn;
2177 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2178 /// by "Src" to address "Dst" with size and alignment information specified by
2179 /// the specific parameter attribute. The copy will be passed as a byval
2180 /// function parameter.
2182 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2183 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2185 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2187 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2188 /*isVolatile*/false, /*AlwaysInline=*/true,
2189 MachinePointerInfo(), MachinePointerInfo());
2192 /// IsTailCallConvention - Return true if the calling convention is one that
2193 /// supports tail call optimization.
2194 static bool IsTailCallConvention(CallingConv::ID CC) {
2195 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2196 CC == CallingConv::HiPE);
2199 /// \brief Return true if the calling convention is a C calling convention.
2200 static bool IsCCallConvention(CallingConv::ID CC) {
2201 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2202 CC == CallingConv::X86_64_SysV);
2205 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2206 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2210 CallingConv::ID CalleeCC = CS.getCallingConv();
2211 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2217 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2218 /// a tailcall target by changing its ABI.
2219 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2220 bool GuaranteedTailCallOpt) {
2221 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2225 X86TargetLowering::LowerMemArgument(SDValue Chain,
2226 CallingConv::ID CallConv,
2227 const SmallVectorImpl<ISD::InputArg> &Ins,
2228 SDLoc dl, SelectionDAG &DAG,
2229 const CCValAssign &VA,
2230 MachineFrameInfo *MFI,
2232 // Create the nodes corresponding to a load from this parameter slot.
2233 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2234 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2235 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2236 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2239 // If value is passed by pointer we have address passed instead of the value
2241 if (VA.getLocInfo() == CCValAssign::Indirect)
2242 ValVT = VA.getLocVT();
2244 ValVT = VA.getValVT();
2246 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2247 // changed with more analysis.
2248 // In case of tail call optimization mark all arguments mutable. Since they
2249 // could be overwritten by lowering of arguments in case of a tail call.
2250 if (Flags.isByVal()) {
2251 unsigned Bytes = Flags.getByValSize();
2252 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2253 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2254 return DAG.getFrameIndex(FI, getPointerTy());
2256 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2257 VA.getLocMemOffset(), isImmutable);
2258 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2259 return DAG.getLoad(ValVT, dl, Chain, FIN,
2260 MachinePointerInfo::getFixedStack(FI),
2261 false, false, false, 0);
2266 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2267 CallingConv::ID CallConv,
2269 const SmallVectorImpl<ISD::InputArg> &Ins,
2272 SmallVectorImpl<SDValue> &InVals)
2274 MachineFunction &MF = DAG.getMachineFunction();
2275 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2277 const Function* Fn = MF.getFunction();
2278 if (Fn->hasExternalLinkage() &&
2279 Subtarget->isTargetCygMing() &&
2280 Fn->getName() == "main")
2281 FuncInfo->setForceFramePointer(true);
2283 MachineFrameInfo *MFI = MF.getFrameInfo();
2284 bool Is64Bit = Subtarget->is64Bit();
2285 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2287 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2288 "Var args not supported with calling convention fastcc, ghc or hipe");
2290 // Assign locations to all of the incoming arguments.
2291 SmallVector<CCValAssign, 16> ArgLocs;
2292 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
2293 ArgLocs, *DAG.getContext());
2295 // Allocate shadow area for Win64
2297 CCInfo.AllocateStack(32, 8);
2299 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2301 unsigned LastVal = ~0U;
2303 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2304 CCValAssign &VA = ArgLocs[i];
2305 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2307 assert(VA.getValNo() != LastVal &&
2308 "Don't support value assigned to multiple locs yet");
2310 LastVal = VA.getValNo();
2312 if (VA.isRegLoc()) {
2313 EVT RegVT = VA.getLocVT();
2314 const TargetRegisterClass *RC;
2315 if (RegVT == MVT::i32)
2316 RC = &X86::GR32RegClass;
2317 else if (Is64Bit && RegVT == MVT::i64)
2318 RC = &X86::GR64RegClass;
2319 else if (RegVT == MVT::f32)
2320 RC = &X86::FR32RegClass;
2321 else if (RegVT == MVT::f64)
2322 RC = &X86::FR64RegClass;
2323 else if (RegVT.is512BitVector())
2324 RC = &X86::VR512RegClass;
2325 else if (RegVT.is256BitVector())
2326 RC = &X86::VR256RegClass;
2327 else if (RegVT.is128BitVector())
2328 RC = &X86::VR128RegClass;
2329 else if (RegVT == MVT::x86mmx)
2330 RC = &X86::VR64RegClass;
2331 else if (RegVT == MVT::i1)
2332 RC = &X86::VK1RegClass;
2333 else if (RegVT == MVT::v8i1)
2334 RC = &X86::VK8RegClass;
2335 else if (RegVT == MVT::v16i1)
2336 RC = &X86::VK16RegClass;
2337 else if (RegVT == MVT::v32i1)
2338 RC = &X86::VK32RegClass;
2339 else if (RegVT == MVT::v64i1)
2340 RC = &X86::VK64RegClass;
2342 llvm_unreachable("Unknown argument type!");
2344 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2345 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2347 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2348 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2350 if (VA.getLocInfo() == CCValAssign::SExt)
2351 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2352 DAG.getValueType(VA.getValVT()));
2353 else if (VA.getLocInfo() == CCValAssign::ZExt)
2354 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2355 DAG.getValueType(VA.getValVT()));
2356 else if (VA.getLocInfo() == CCValAssign::BCvt)
2357 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2359 if (VA.isExtInLoc()) {
2360 // Handle MMX values passed in XMM regs.
2361 if (RegVT.isVector())
2362 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2364 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2367 assert(VA.isMemLoc());
2368 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2371 // If value is passed via pointer - do a load.
2372 if (VA.getLocInfo() == CCValAssign::Indirect)
2373 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2374 MachinePointerInfo(), false, false, false, 0);
2376 InVals.push_back(ArgValue);
2379 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2380 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2381 // The x86-64 ABIs require that for returning structs by value we copy
2382 // the sret argument into %rax/%eax (depending on ABI) for the return.
2383 // Win32 requires us to put the sret argument to %eax as well.
2384 // Save the argument into a virtual register so that we can access it
2385 // from the return points.
2386 if (Ins[i].Flags.isSRet()) {
2387 unsigned Reg = FuncInfo->getSRetReturnReg();
2389 MVT PtrTy = getPointerTy();
2390 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2391 FuncInfo->setSRetReturnReg(Reg);
2393 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2400 unsigned StackSize = CCInfo.getNextStackOffset();
2401 // Align stack specially for tail calls.
2402 if (FuncIsMadeTailCallSafe(CallConv,
2403 MF.getTarget().Options.GuaranteedTailCallOpt))
2404 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2406 // If the function takes variable number of arguments, make a frame index for
2407 // the start of the first vararg value... for expansion of llvm.va_start.
2409 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2410 CallConv != CallingConv::X86_ThisCall)) {
2411 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2414 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2416 // FIXME: We should really autogenerate these arrays
2417 static const MCPhysReg GPR64ArgRegsWin64[] = {
2418 X86::RCX, X86::RDX, X86::R8, X86::R9
2420 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2421 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2423 static const MCPhysReg XMMArgRegs64Bit[] = {
2424 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2425 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2427 const MCPhysReg *GPR64ArgRegs;
2428 unsigned NumXMMRegs = 0;
2431 // The XMM registers which might contain var arg parameters are shadowed
2432 // in their paired GPR. So we only need to save the GPR to their home
2434 TotalNumIntRegs = 4;
2435 GPR64ArgRegs = GPR64ArgRegsWin64;
2437 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2438 GPR64ArgRegs = GPR64ArgRegs64Bit;
2440 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2443 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2446 bool NoImplicitFloatOps = Fn->getAttributes().
2447 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2448 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2449 "SSE register cannot be used when SSE is disabled!");
2450 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2451 NoImplicitFloatOps) &&
2452 "SSE register cannot be used when SSE is disabled!");
2453 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2454 !Subtarget->hasSSE1())
2455 // Kernel mode asks for SSE to be disabled, so don't push them
2457 TotalNumXMMRegs = 0;
2460 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2461 // Get to the caller-allocated home save location. Add 8 to account
2462 // for the return address.
2463 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2464 FuncInfo->setRegSaveFrameIndex(
2465 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2466 // Fixup to set vararg frame on shadow area (4 x i64).
2468 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2470 // For X86-64, if there are vararg parameters that are passed via
2471 // registers, then we must store them to their spots on the stack so
2472 // they may be loaded by deferencing the result of va_next.
2473 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2474 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2475 FuncInfo->setRegSaveFrameIndex(
2476 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2480 // Store the integer parameter registers.
2481 SmallVector<SDValue, 8> MemOps;
2482 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2484 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2485 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2486 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2487 DAG.getIntPtrConstant(Offset));
2488 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2489 &X86::GR64RegClass);
2490 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2492 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2493 MachinePointerInfo::getFixedStack(
2494 FuncInfo->getRegSaveFrameIndex(), Offset),
2496 MemOps.push_back(Store);
2500 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2501 // Now store the XMM (fp + vector) parameter registers.
2502 SmallVector<SDValue, 11> SaveXMMOps;
2503 SaveXMMOps.push_back(Chain);
2505 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2506 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2507 SaveXMMOps.push_back(ALVal);
2509 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2510 FuncInfo->getRegSaveFrameIndex()));
2511 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2512 FuncInfo->getVarArgsFPOffset()));
2514 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2515 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2516 &X86::VR128RegClass);
2517 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2518 SaveXMMOps.push_back(Val);
2520 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2521 MVT::Other, SaveXMMOps));
2524 if (!MemOps.empty())
2525 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2529 // Some CCs need callee pop.
2530 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2531 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2532 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2534 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2535 // If this is an sret function, the return should pop the hidden pointer.
2536 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2537 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2538 argsAreStructReturn(Ins) == StackStructReturn)
2539 FuncInfo->setBytesToPopOnReturn(4);
2543 // RegSaveFrameIndex is X86-64 only.
2544 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2545 if (CallConv == CallingConv::X86_FastCall ||
2546 CallConv == CallingConv::X86_ThisCall)
2547 // fastcc functions can't have varargs.
2548 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2551 FuncInfo->setArgumentStackSize(StackSize);
2557 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2558 SDValue StackPtr, SDValue Arg,
2559 SDLoc dl, SelectionDAG &DAG,
2560 const CCValAssign &VA,
2561 ISD::ArgFlagsTy Flags) const {
2562 unsigned LocMemOffset = VA.getLocMemOffset();
2563 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2564 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2565 if (Flags.isByVal())
2566 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2568 return DAG.getStore(Chain, dl, Arg, PtrOff,
2569 MachinePointerInfo::getStack(LocMemOffset),
2573 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2574 /// optimization is performed and it is required.
2576 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2577 SDValue &OutRetAddr, SDValue Chain,
2578 bool IsTailCall, bool Is64Bit,
2579 int FPDiff, SDLoc dl) const {
2580 // Adjust the Return address stack slot.
2581 EVT VT = getPointerTy();
2582 OutRetAddr = getReturnAddressFrameIndex(DAG);
2584 // Load the "old" Return address.
2585 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2586 false, false, false, 0);
2587 return SDValue(OutRetAddr.getNode(), 1);
2590 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2591 /// optimization is performed and it is required (FPDiff!=0).
2592 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2593 SDValue Chain, SDValue RetAddrFrIdx,
2594 EVT PtrVT, unsigned SlotSize,
2595 int FPDiff, SDLoc dl) {
2596 // Store the return address to the appropriate stack slot.
2597 if (!FPDiff) return Chain;
2598 // Calculate the new stack slot for the return address.
2599 int NewReturnAddrFI =
2600 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2602 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2603 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2604 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2610 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2611 SmallVectorImpl<SDValue> &InVals) const {
2612 SelectionDAG &DAG = CLI.DAG;
2614 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2615 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2616 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2617 SDValue Chain = CLI.Chain;
2618 SDValue Callee = CLI.Callee;
2619 CallingConv::ID CallConv = CLI.CallConv;
2620 bool &isTailCall = CLI.IsTailCall;
2621 bool isVarArg = CLI.IsVarArg;
2623 MachineFunction &MF = DAG.getMachineFunction();
2624 bool Is64Bit = Subtarget->is64Bit();
2625 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2626 StructReturnType SR = callIsStructReturn(Outs);
2627 bool IsSibcall = false;
2629 if (MF.getTarget().Options.DisableTailCalls)
2632 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2634 // Force this to be a tail call. The verifier rules are enough to ensure
2635 // that we can lower this successfully without moving the return address
2638 } else if (isTailCall) {
2639 // Check if it's really possible to do a tail call.
2640 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2641 isVarArg, SR != NotStructReturn,
2642 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2643 Outs, OutVals, Ins, DAG);
2645 // Sibcalls are automatically detected tailcalls which do not require
2647 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2654 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2655 "Var args not supported with calling convention fastcc, ghc or hipe");
2657 // Analyze operands of the call, assigning locations to each operand.
2658 SmallVector<CCValAssign, 16> ArgLocs;
2659 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
2660 ArgLocs, *DAG.getContext());
2662 // Allocate shadow area for Win64
2664 CCInfo.AllocateStack(32, 8);
2666 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2668 // Get a count of how many bytes are to be pushed on the stack.
2669 unsigned NumBytes = CCInfo.getNextStackOffset();
2671 // This is a sibcall. The memory operands are available in caller's
2672 // own caller's stack.
2674 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2675 IsTailCallConvention(CallConv))
2676 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2679 if (isTailCall && !IsSibcall && !IsMustTail) {
2680 // Lower arguments at fp - stackoffset + fpdiff.
2681 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2682 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2684 FPDiff = NumBytesCallerPushed - NumBytes;
2686 // Set the delta of movement of the returnaddr stackslot.
2687 // But only set if delta is greater than previous delta.
2688 if (FPDiff < X86Info->getTCReturnAddrDelta())
2689 X86Info->setTCReturnAddrDelta(FPDiff);
2692 unsigned NumBytesToPush = NumBytes;
2693 unsigned NumBytesToPop = NumBytes;
2695 // If we have an inalloca argument, all stack space has already been allocated
2696 // for us and be right at the top of the stack. We don't support multiple
2697 // arguments passed in memory when using inalloca.
2698 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2700 if (!ArgLocs.back().isMemLoc())
2701 report_fatal_error("cannot use inalloca attribute on a register "
2703 if (ArgLocs.back().getLocMemOffset() != 0)
2704 report_fatal_error("any parameter with the inalloca attribute must be "
2705 "the only memory argument");
2709 Chain = DAG.getCALLSEQ_START(
2710 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2712 SDValue RetAddrFrIdx;
2713 // Load return address for tail calls.
2714 if (isTailCall && FPDiff)
2715 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2716 Is64Bit, FPDiff, dl);
2718 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2719 SmallVector<SDValue, 8> MemOpChains;
2722 // Walk the register/memloc assignments, inserting copies/loads. In the case
2723 // of tail call optimization arguments are handle later.
2724 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2725 DAG.getSubtarget().getRegisterInfo());
2726 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2727 // Skip inalloca arguments, they have already been written.
2728 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2729 if (Flags.isInAlloca())
2732 CCValAssign &VA = ArgLocs[i];
2733 EVT RegVT = VA.getLocVT();
2734 SDValue Arg = OutVals[i];
2735 bool isByVal = Flags.isByVal();
2737 // Promote the value if needed.
2738 switch (VA.getLocInfo()) {
2739 default: llvm_unreachable("Unknown loc info!");
2740 case CCValAssign::Full: break;
2741 case CCValAssign::SExt:
2742 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2744 case CCValAssign::ZExt:
2745 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2747 case CCValAssign::AExt:
2748 if (RegVT.is128BitVector()) {
2749 // Special case: passing MMX values in XMM registers.
2750 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2751 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2752 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2754 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2756 case CCValAssign::BCvt:
2757 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2759 case CCValAssign::Indirect: {
2760 // Store the argument.
2761 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2762 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2763 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2764 MachinePointerInfo::getFixedStack(FI),
2771 if (VA.isRegLoc()) {
2772 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2773 if (isVarArg && IsWin64) {
2774 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2775 // shadow reg if callee is a varargs function.
2776 unsigned ShadowReg = 0;
2777 switch (VA.getLocReg()) {
2778 case X86::XMM0: ShadowReg = X86::RCX; break;
2779 case X86::XMM1: ShadowReg = X86::RDX; break;
2780 case X86::XMM2: ShadowReg = X86::R8; break;
2781 case X86::XMM3: ShadowReg = X86::R9; break;
2784 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2786 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2787 assert(VA.isMemLoc());
2788 if (!StackPtr.getNode())
2789 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2791 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2792 dl, DAG, VA, Flags));
2796 if (!MemOpChains.empty())
2797 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2799 if (Subtarget->isPICStyleGOT()) {
2800 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2803 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2804 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2806 // If we are tail calling and generating PIC/GOT style code load the
2807 // address of the callee into ECX. The value in ecx is used as target of
2808 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2809 // for tail calls on PIC/GOT architectures. Normally we would just put the
2810 // address of GOT into ebx and then call target@PLT. But for tail calls
2811 // ebx would be restored (since ebx is callee saved) before jumping to the
2814 // Note: The actual moving to ECX is done further down.
2815 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2816 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2817 !G->getGlobal()->hasProtectedVisibility())
2818 Callee = LowerGlobalAddress(Callee, DAG);
2819 else if (isa<ExternalSymbolSDNode>(Callee))
2820 Callee = LowerExternalSymbol(Callee, DAG);
2824 if (Is64Bit && isVarArg && !IsWin64) {
2825 // From AMD64 ABI document:
2826 // For calls that may call functions that use varargs or stdargs
2827 // (prototype-less calls or calls to functions containing ellipsis (...) in
2828 // the declaration) %al is used as hidden argument to specify the number
2829 // of SSE registers used. The contents of %al do not need to match exactly
2830 // the number of registers, but must be an ubound on the number of SSE
2831 // registers used and is in the range 0 - 8 inclusive.
2833 // Count the number of XMM registers allocated.
2834 static const MCPhysReg XMMArgRegs[] = {
2835 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2836 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2838 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2839 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2840 && "SSE registers cannot be used when SSE is disabled");
2842 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2843 DAG.getConstant(NumXMMRegs, MVT::i8)));
2846 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2847 // don't need this because the eligibility check rejects calls that require
2848 // shuffling arguments passed in memory.
2849 if (!IsSibcall && isTailCall) {
2850 // Force all the incoming stack arguments to be loaded from the stack
2851 // before any new outgoing arguments are stored to the stack, because the
2852 // outgoing stack slots may alias the incoming argument stack slots, and
2853 // the alias isn't otherwise explicit. This is slightly more conservative
2854 // than necessary, because it means that each store effectively depends
2855 // on every argument instead of just those arguments it would clobber.
2856 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2858 SmallVector<SDValue, 8> MemOpChains2;
2861 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2862 CCValAssign &VA = ArgLocs[i];
2865 assert(VA.isMemLoc());
2866 SDValue Arg = OutVals[i];
2867 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2868 // Skip inalloca arguments. They don't require any work.
2869 if (Flags.isInAlloca())
2871 // Create frame index.
2872 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2873 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2874 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2875 FIN = DAG.getFrameIndex(FI, getPointerTy());
2877 if (Flags.isByVal()) {
2878 // Copy relative to framepointer.
2879 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2880 if (!StackPtr.getNode())
2881 StackPtr = DAG.getCopyFromReg(Chain, dl,
2882 RegInfo->getStackRegister(),
2884 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2886 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2890 // Store relative to framepointer.
2891 MemOpChains2.push_back(
2892 DAG.getStore(ArgChain, dl, Arg, FIN,
2893 MachinePointerInfo::getFixedStack(FI),
2898 if (!MemOpChains2.empty())
2899 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2901 // Store the return address to the appropriate stack slot.
2902 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2903 getPointerTy(), RegInfo->getSlotSize(),
2907 // Build a sequence of copy-to-reg nodes chained together with token chain
2908 // and flag operands which copy the outgoing args into registers.
2910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2911 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2912 RegsToPass[i].second, InFlag);
2913 InFlag = Chain.getValue(1);
2916 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2917 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2918 // In the 64-bit large code model, we have to make all calls
2919 // through a register, since the call instruction's 32-bit
2920 // pc-relative offset may not be large enough to hold the whole
2922 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2923 // If the callee is a GlobalAddress node (quite common, every direct call
2924 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2927 // We should use extra load for direct calls to dllimported functions in
2929 const GlobalValue *GV = G->getGlobal();
2930 if (!GV->hasDLLImportStorageClass()) {
2931 unsigned char OpFlags = 0;
2932 bool ExtraLoad = false;
2933 unsigned WrapperKind = ISD::DELETED_NODE;
2935 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2936 // external symbols most go through the PLT in PIC mode. If the symbol
2937 // has hidden or protected visibility, or if it is static or local, then
2938 // we don't need to use the PLT - we can directly call it.
2939 if (Subtarget->isTargetELF() &&
2940 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2941 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2942 OpFlags = X86II::MO_PLT;
2943 } else if (Subtarget->isPICStyleStubAny() &&
2944 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2945 (!Subtarget->getTargetTriple().isMacOSX() ||
2946 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2947 // PC-relative references to external symbols should go through $stub,
2948 // unless we're building with the leopard linker or later, which
2949 // automatically synthesizes these stubs.
2950 OpFlags = X86II::MO_DARWIN_STUB;
2951 } else if (Subtarget->isPICStyleRIPRel() &&
2952 isa<Function>(GV) &&
2953 cast<Function>(GV)->getAttributes().
2954 hasAttribute(AttributeSet::FunctionIndex,
2955 Attribute::NonLazyBind)) {
2956 // If the function is marked as non-lazy, generate an indirect call
2957 // which loads from the GOT directly. This avoids runtime overhead
2958 // at the cost of eager binding (and one extra byte of encoding).
2959 OpFlags = X86II::MO_GOTPCREL;
2960 WrapperKind = X86ISD::WrapperRIP;
2964 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2965 G->getOffset(), OpFlags);
2967 // Add a wrapper if needed.
2968 if (WrapperKind != ISD::DELETED_NODE)
2969 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2970 // Add extra indirection if needed.
2972 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2973 MachinePointerInfo::getGOT(),
2974 false, false, false, 0);
2976 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2977 unsigned char OpFlags = 0;
2979 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2980 // external symbols should go through the PLT.
2981 if (Subtarget->isTargetELF() &&
2982 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2983 OpFlags = X86II::MO_PLT;
2984 } else if (Subtarget->isPICStyleStubAny() &&
2985 (!Subtarget->getTargetTriple().isMacOSX() ||
2986 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2987 // PC-relative references to external symbols should go through $stub,
2988 // unless we're building with the leopard linker or later, which
2989 // automatically synthesizes these stubs.
2990 OpFlags = X86II::MO_DARWIN_STUB;
2993 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2997 // Returns a chain & a flag for retval copy to use.
2998 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2999 SmallVector<SDValue, 8> Ops;
3001 if (!IsSibcall && isTailCall) {
3002 Chain = DAG.getCALLSEQ_END(Chain,
3003 DAG.getIntPtrConstant(NumBytesToPop, true),
3004 DAG.getIntPtrConstant(0, true), InFlag, dl);
3005 InFlag = Chain.getValue(1);
3008 Ops.push_back(Chain);
3009 Ops.push_back(Callee);
3012 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3014 // Add argument registers to the end of the list so that they are known live
3016 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3017 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3018 RegsToPass[i].second.getValueType()));
3020 // Add a register mask operand representing the call-preserved registers.
3021 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3022 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3023 assert(Mask && "Missing call preserved mask for calling convention");
3024 Ops.push_back(DAG.getRegisterMask(Mask));
3026 if (InFlag.getNode())
3027 Ops.push_back(InFlag);
3031 //// If this is the first return lowered for this function, add the regs
3032 //// to the liveout set for the function.
3033 // This isn't right, although it's probably harmless on x86; liveouts
3034 // should be computed from returns not tail calls. Consider a void
3035 // function making a tail call to a function returning int.
3036 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3039 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3040 InFlag = Chain.getValue(1);
3042 // Create the CALLSEQ_END node.
3043 unsigned NumBytesForCalleeToPop;
3044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3045 DAG.getTarget().Options.GuaranteedTailCallOpt))
3046 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3047 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3048 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3049 SR == StackStructReturn)
3050 // If this is a call to a struct-return function, the callee
3051 // pops the hidden struct pointer, so we have to push it back.
3052 // This is common for Darwin/X86, Linux & Mingw32 targets.
3053 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3054 NumBytesForCalleeToPop = 4;
3056 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3058 // Returns a flag for retval copy to use.
3060 Chain = DAG.getCALLSEQ_END(Chain,
3061 DAG.getIntPtrConstant(NumBytesToPop, true),
3062 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3065 InFlag = Chain.getValue(1);
3068 // Handle result values, copying them out of physregs into vregs that we
3070 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3071 Ins, dl, DAG, InVals);
3074 //===----------------------------------------------------------------------===//
3075 // Fast Calling Convention (tail call) implementation
3076 //===----------------------------------------------------------------------===//
3078 // Like std call, callee cleans arguments, convention except that ECX is
3079 // reserved for storing the tail called function address. Only 2 registers are
3080 // free for argument passing (inreg). Tail call optimization is performed
3082 // * tailcallopt is enabled
3083 // * caller/callee are fastcc
3084 // On X86_64 architecture with GOT-style position independent code only local
3085 // (within module) calls are supported at the moment.
3086 // To keep the stack aligned according to platform abi the function
3087 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3088 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3089 // If a tail called function callee has more arguments than the caller the
3090 // caller needs to make sure that there is room to move the RETADDR to. This is
3091 // achieved by reserving an area the size of the argument delta right after the
3092 // original RETADDR, but before the saved framepointer or the spilled registers
3093 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3105 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3106 /// for a 16 byte align requirement.
3108 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3109 SelectionDAG& DAG) const {
3110 MachineFunction &MF = DAG.getMachineFunction();
3111 const TargetMachine &TM = MF.getTarget();
3112 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3113 TM.getSubtargetImpl()->getRegisterInfo());
3114 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3115 unsigned StackAlignment = TFI.getStackAlignment();
3116 uint64_t AlignMask = StackAlignment - 1;
3117 int64_t Offset = StackSize;
3118 unsigned SlotSize = RegInfo->getSlotSize();
3119 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3120 // Number smaller than 12 so just add the difference.
3121 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3123 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3124 Offset = ((~AlignMask) & Offset) + StackAlignment +
3125 (StackAlignment-SlotSize);
3130 /// MatchingStackOffset - Return true if the given stack call argument is
3131 /// already available in the same position (relatively) of the caller's
3132 /// incoming argument stack.
3134 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3135 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3136 const X86InstrInfo *TII) {
3137 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3139 if (Arg.getOpcode() == ISD::CopyFromReg) {
3140 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3141 if (!TargetRegisterInfo::isVirtualRegister(VR))
3143 MachineInstr *Def = MRI->getVRegDef(VR);
3146 if (!Flags.isByVal()) {
3147 if (!TII->isLoadFromStackSlot(Def, FI))
3150 unsigned Opcode = Def->getOpcode();
3151 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3152 Def->getOperand(1).isFI()) {
3153 FI = Def->getOperand(1).getIndex();
3154 Bytes = Flags.getByValSize();
3158 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3159 if (Flags.isByVal())
3160 // ByVal argument is passed in as a pointer but it's now being
3161 // dereferenced. e.g.
3162 // define @foo(%struct.X* %A) {
3163 // tail call @bar(%struct.X* byval %A)
3166 SDValue Ptr = Ld->getBasePtr();
3167 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3170 FI = FINode->getIndex();
3171 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3172 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3173 FI = FINode->getIndex();
3174 Bytes = Flags.getByValSize();
3178 assert(FI != INT_MAX);
3179 if (!MFI->isFixedObjectIndex(FI))
3181 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3184 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3185 /// for tail call optimization. Targets which want to do tail call
3186 /// optimization should implement this function.
3188 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3189 CallingConv::ID CalleeCC,
3191 bool isCalleeStructRet,
3192 bool isCallerStructRet,
3194 const SmallVectorImpl<ISD::OutputArg> &Outs,
3195 const SmallVectorImpl<SDValue> &OutVals,
3196 const SmallVectorImpl<ISD::InputArg> &Ins,
3197 SelectionDAG &DAG) const {
3198 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3201 // If -tailcallopt is specified, make fastcc functions tail-callable.
3202 const MachineFunction &MF = DAG.getMachineFunction();
3203 const Function *CallerF = MF.getFunction();
3205 // If the function return type is x86_fp80 and the callee return type is not,
3206 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3207 // perform a tailcall optimization here.
3208 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3211 CallingConv::ID CallerCC = CallerF->getCallingConv();
3212 bool CCMatch = CallerCC == CalleeCC;
3213 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3214 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3216 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3217 if (IsTailCallConvention(CalleeCC) && CCMatch)
3222 // Look for obvious safe cases to perform tail call optimization that do not
3223 // require ABI changes. This is what gcc calls sibcall.
3225 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3226 // emit a special epilogue.
3227 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3228 DAG.getSubtarget().getRegisterInfo());
3229 if (RegInfo->needsStackRealignment(MF))
3232 // Also avoid sibcall optimization if either caller or callee uses struct
3233 // return semantics.
3234 if (isCalleeStructRet || isCallerStructRet)
3237 // An stdcall/thiscall caller is expected to clean up its arguments; the
3238 // callee isn't going to do that.
3239 // FIXME: this is more restrictive than needed. We could produce a tailcall
3240 // when the stack adjustment matches. For example, with a thiscall that takes
3241 // only one argument.
3242 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3243 CallerCC == CallingConv::X86_ThisCall))
3246 // Do not sibcall optimize vararg calls unless all arguments are passed via
3248 if (isVarArg && !Outs.empty()) {
3250 // Optimizing for varargs on Win64 is unlikely to be safe without
3251 // additional testing.
3252 if (IsCalleeWin64 || IsCallerWin64)
3255 SmallVector<CCValAssign, 16> ArgLocs;
3256 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3257 DAG.getTarget(), ArgLocs, *DAG.getContext());
3259 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3260 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3261 if (!ArgLocs[i].isRegLoc())
3265 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3266 // stack. Therefore, if it's not used by the call it is not safe to optimize
3267 // this into a sibcall.
3268 bool Unused = false;
3269 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3276 SmallVector<CCValAssign, 16> RVLocs;
3277 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3278 DAG.getTarget(), RVLocs, *DAG.getContext());
3279 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3280 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3281 CCValAssign &VA = RVLocs[i];
3282 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3287 // If the calling conventions do not match, then we'd better make sure the
3288 // results are returned in the same way as what the caller expects.
3290 SmallVector<CCValAssign, 16> RVLocs1;
3291 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3292 DAG.getTarget(), RVLocs1, *DAG.getContext());
3293 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3295 SmallVector<CCValAssign, 16> RVLocs2;
3296 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3297 DAG.getTarget(), RVLocs2, *DAG.getContext());
3298 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3300 if (RVLocs1.size() != RVLocs2.size())
3302 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3303 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3305 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3307 if (RVLocs1[i].isRegLoc()) {
3308 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3311 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3317 // If the callee takes no arguments then go on to check the results of the
3319 if (!Outs.empty()) {
3320 // Check if stack adjustment is needed. For now, do not do this if any
3321 // argument is passed on the stack.
3322 SmallVector<CCValAssign, 16> ArgLocs;
3323 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3324 DAG.getTarget(), ArgLocs, *DAG.getContext());
3326 // Allocate shadow area for Win64
3328 CCInfo.AllocateStack(32, 8);
3330 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3331 if (CCInfo.getNextStackOffset()) {
3332 MachineFunction &MF = DAG.getMachineFunction();
3333 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3336 // Check if the arguments are already laid out in the right way as
3337 // the caller's fixed stack objects.
3338 MachineFrameInfo *MFI = MF.getFrameInfo();
3339 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3340 const X86InstrInfo *TII =
3341 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3342 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3343 CCValAssign &VA = ArgLocs[i];
3344 SDValue Arg = OutVals[i];
3345 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3346 if (VA.getLocInfo() == CCValAssign::Indirect)
3348 if (!VA.isRegLoc()) {
3349 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3356 // If the tailcall address may be in a register, then make sure it's
3357 // possible to register allocate for it. In 32-bit, the call address can
3358 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3359 // callee-saved registers are restored. These happen to be the same
3360 // registers used to pass 'inreg' arguments so watch out for those.
3361 if (!Subtarget->is64Bit() &&
3362 ((!isa<GlobalAddressSDNode>(Callee) &&
3363 !isa<ExternalSymbolSDNode>(Callee)) ||
3364 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3365 unsigned NumInRegs = 0;
3366 // In PIC we need an extra register to formulate the address computation
3368 unsigned MaxInRegs =
3369 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3371 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3372 CCValAssign &VA = ArgLocs[i];
3375 unsigned Reg = VA.getLocReg();
3378 case X86::EAX: case X86::EDX: case X86::ECX:
3379 if (++NumInRegs == MaxInRegs)
3391 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3392 const TargetLibraryInfo *libInfo) const {
3393 return X86::createFastISel(funcInfo, libInfo);
3396 //===----------------------------------------------------------------------===//
3397 // Other Lowering Hooks
3398 //===----------------------------------------------------------------------===//
3400 static bool MayFoldLoad(SDValue Op) {
3401 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3404 static bool MayFoldIntoStore(SDValue Op) {
3405 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3408 static bool isTargetShuffle(unsigned Opcode) {
3410 default: return false;
3411 case X86ISD::PSHUFB:
3412 case X86ISD::PSHUFD:
3413 case X86ISD::PSHUFHW:
3414 case X86ISD::PSHUFLW:
3416 case X86ISD::PALIGNR:
3417 case X86ISD::MOVLHPS:
3418 case X86ISD::MOVLHPD:
3419 case X86ISD::MOVHLPS:
3420 case X86ISD::MOVLPS:
3421 case X86ISD::MOVLPD:
3422 case X86ISD::MOVSHDUP:
3423 case X86ISD::MOVSLDUP:
3424 case X86ISD::MOVDDUP:
3427 case X86ISD::UNPCKL:
3428 case X86ISD::UNPCKH:
3429 case X86ISD::VPERMILP:
3430 case X86ISD::VPERM2X128:
3431 case X86ISD::VPERMI:
3436 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3437 SDValue V1, SelectionDAG &DAG) {
3439 default: llvm_unreachable("Unknown x86 shuffle node");
3440 case X86ISD::MOVSHDUP:
3441 case X86ISD::MOVSLDUP:
3442 case X86ISD::MOVDDUP:
3443 return DAG.getNode(Opc, dl, VT, V1);
3447 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3448 SDValue V1, unsigned TargetMask,
3449 SelectionDAG &DAG) {
3451 default: llvm_unreachable("Unknown x86 shuffle node");
3452 case X86ISD::PSHUFD:
3453 case X86ISD::PSHUFHW:
3454 case X86ISD::PSHUFLW:
3455 case X86ISD::VPERMILP:
3456 case X86ISD::VPERMI:
3457 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3461 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3462 SDValue V1, SDValue V2, unsigned TargetMask,
3463 SelectionDAG &DAG) {
3465 default: llvm_unreachable("Unknown x86 shuffle node");
3466 case X86ISD::PALIGNR:
3468 case X86ISD::VPERM2X128:
3469 return DAG.getNode(Opc, dl, VT, V1, V2,
3470 DAG.getConstant(TargetMask, MVT::i8));
3474 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3475 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3477 default: llvm_unreachable("Unknown x86 shuffle node");
3478 case X86ISD::MOVLHPS:
3479 case X86ISD::MOVLHPD:
3480 case X86ISD::MOVHLPS:
3481 case X86ISD::MOVLPS:
3482 case X86ISD::MOVLPD:
3485 case X86ISD::UNPCKL:
3486 case X86ISD::UNPCKH:
3487 return DAG.getNode(Opc, dl, VT, V1, V2);
3491 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3492 MachineFunction &MF = DAG.getMachineFunction();
3493 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3494 DAG.getSubtarget().getRegisterInfo());
3495 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3496 int ReturnAddrIndex = FuncInfo->getRAIndex();
3498 if (ReturnAddrIndex == 0) {
3499 // Set up a frame object for the return address.
3500 unsigned SlotSize = RegInfo->getSlotSize();
3501 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3504 FuncInfo->setRAIndex(ReturnAddrIndex);
3507 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3510 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3511 bool hasSymbolicDisplacement) {
3512 // Offset should fit into 32 bit immediate field.
3513 if (!isInt<32>(Offset))
3516 // If we don't have a symbolic displacement - we don't have any extra
3518 if (!hasSymbolicDisplacement)
3521 // FIXME: Some tweaks might be needed for medium code model.
3522 if (M != CodeModel::Small && M != CodeModel::Kernel)
3525 // For small code model we assume that latest object is 16MB before end of 31
3526 // bits boundary. We may also accept pretty large negative constants knowing
3527 // that all objects are in the positive half of address space.
3528 if (M == CodeModel::Small && Offset < 16*1024*1024)
3531 // For kernel code model we know that all object resist in the negative half
3532 // of 32bits address space. We may not accept negative offsets, since they may
3533 // be just off and we may accept pretty large positive ones.
3534 if (M == CodeModel::Kernel && Offset > 0)
3540 /// isCalleePop - Determines whether the callee is required to pop its
3541 /// own arguments. Callee pop is necessary to support tail calls.
3542 bool X86::isCalleePop(CallingConv::ID CallingConv,
3543 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3547 switch (CallingConv) {
3550 case CallingConv::X86_StdCall:
3552 case CallingConv::X86_FastCall:
3554 case CallingConv::X86_ThisCall:
3556 case CallingConv::Fast:
3558 case CallingConv::GHC:
3560 case CallingConv::HiPE:
3565 /// \brief Return true if the condition is an unsigned comparison operation.
3566 static bool isX86CCUnsigned(unsigned X86CC) {
3568 default: llvm_unreachable("Invalid integer condition!");
3569 case X86::COND_E: return true;
3570 case X86::COND_G: return false;
3571 case X86::COND_GE: return false;
3572 case X86::COND_L: return false;
3573 case X86::COND_LE: return false;
3574 case X86::COND_NE: return true;
3575 case X86::COND_B: return true;
3576 case X86::COND_A: return true;
3577 case X86::COND_BE: return true;
3578 case X86::COND_AE: return true;
3580 llvm_unreachable("covered switch fell through?!");
3583 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3584 /// specific condition code, returning the condition code and the LHS/RHS of the
3585 /// comparison to make.
3586 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3587 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3589 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3590 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3591 // X > -1 -> X == 0, jump !sign.
3592 RHS = DAG.getConstant(0, RHS.getValueType());
3593 return X86::COND_NS;
3595 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3596 // X < 0 -> X == 0, jump on sign.
3599 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3601 RHS = DAG.getConstant(0, RHS.getValueType());
3602 return X86::COND_LE;
3606 switch (SetCCOpcode) {
3607 default: llvm_unreachable("Invalid integer condition!");
3608 case ISD::SETEQ: return X86::COND_E;
3609 case ISD::SETGT: return X86::COND_G;
3610 case ISD::SETGE: return X86::COND_GE;
3611 case ISD::SETLT: return X86::COND_L;
3612 case ISD::SETLE: return X86::COND_LE;
3613 case ISD::SETNE: return X86::COND_NE;
3614 case ISD::SETULT: return X86::COND_B;
3615 case ISD::SETUGT: return X86::COND_A;
3616 case ISD::SETULE: return X86::COND_BE;
3617 case ISD::SETUGE: return X86::COND_AE;
3621 // First determine if it is required or is profitable to flip the operands.
3623 // If LHS is a foldable load, but RHS is not, flip the condition.
3624 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3625 !ISD::isNON_EXTLoad(RHS.getNode())) {
3626 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3627 std::swap(LHS, RHS);
3630 switch (SetCCOpcode) {
3636 std::swap(LHS, RHS);
3640 // On a floating point condition, the flags are set as follows:
3642 // 0 | 0 | 0 | X > Y
3643 // 0 | 0 | 1 | X < Y
3644 // 1 | 0 | 0 | X == Y
3645 // 1 | 1 | 1 | unordered
3646 switch (SetCCOpcode) {
3647 default: llvm_unreachable("Condcode should be pre-legalized away");
3649 case ISD::SETEQ: return X86::COND_E;
3650 case ISD::SETOLT: // flipped
3652 case ISD::SETGT: return X86::COND_A;
3653 case ISD::SETOLE: // flipped
3655 case ISD::SETGE: return X86::COND_AE;
3656 case ISD::SETUGT: // flipped
3658 case ISD::SETLT: return X86::COND_B;
3659 case ISD::SETUGE: // flipped
3661 case ISD::SETLE: return X86::COND_BE;
3663 case ISD::SETNE: return X86::COND_NE;
3664 case ISD::SETUO: return X86::COND_P;
3665 case ISD::SETO: return X86::COND_NP;
3667 case ISD::SETUNE: return X86::COND_INVALID;
3671 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3672 /// code. Current x86 isa includes the following FP cmov instructions:
3673 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3674 static bool hasFPCMov(unsigned X86CC) {
3690 /// isFPImmLegal - Returns true if the target can instruction select the
3691 /// specified FP immediate natively. If false, the legalizer will
3692 /// materialize the FP immediate as a load from a constant pool.
3693 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3694 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3695 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3701 /// \brief Returns true if it is beneficial to convert a load of a constant
3702 /// to just the constant itself.
3703 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3705 assert(Ty->isIntegerTy());
3707 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3708 if (BitSize == 0 || BitSize > 64)
3713 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3714 /// the specified range (L, H].
3715 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3716 return (Val < 0) || (Val >= Low && Val < Hi);
3719 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3720 /// specified value.
3721 static bool isUndefOrEqual(int Val, int CmpVal) {
3722 return (Val < 0 || Val == CmpVal);
3725 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3726 /// from position Pos and ending in Pos+Size, falls within the specified
3727 /// sequential range (L, L+Pos]. or is undef.
3728 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3729 unsigned Pos, unsigned Size, int Low) {
3730 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3731 if (!isUndefOrEqual(Mask[i], Low))
3736 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3737 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3738 /// the second operand.
3739 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3740 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3741 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3742 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3743 return (Mask[0] < 2 && Mask[1] < 2);
3747 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3748 /// is suitable for input to PSHUFHW.
3749 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3750 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3753 // Lower quadword copied in order or undef.
3754 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3757 // Upper quadword shuffled.
3758 for (unsigned i = 4; i != 8; ++i)
3759 if (!isUndefOrInRange(Mask[i], 4, 8))
3762 if (VT == MVT::v16i16) {
3763 // Lower quadword copied in order or undef.
3764 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3767 // Upper quadword shuffled.
3768 for (unsigned i = 12; i != 16; ++i)
3769 if (!isUndefOrInRange(Mask[i], 12, 16))
3776 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3777 /// is suitable for input to PSHUFLW.
3778 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3779 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3782 // Upper quadword copied in order.
3783 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3786 // Lower quadword shuffled.
3787 for (unsigned i = 0; i != 4; ++i)
3788 if (!isUndefOrInRange(Mask[i], 0, 4))
3791 if (VT == MVT::v16i16) {
3792 // Upper quadword copied in order.
3793 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3796 // Lower quadword shuffled.
3797 for (unsigned i = 8; i != 12; ++i)
3798 if (!isUndefOrInRange(Mask[i], 8, 12))
3805 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3806 /// is suitable for input to PALIGNR.
3807 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3808 const X86Subtarget *Subtarget) {
3809 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3810 (VT.is256BitVector() && !Subtarget->hasInt256()))
3813 unsigned NumElts = VT.getVectorNumElements();
3814 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3815 unsigned NumLaneElts = NumElts/NumLanes;
3817 // Do not handle 64-bit element shuffles with palignr.
3818 if (NumLaneElts == 2)
3821 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3823 for (i = 0; i != NumLaneElts; ++i) {
3828 // Lane is all undef, go to next lane
3829 if (i == NumLaneElts)
3832 int Start = Mask[i+l];
3834 // Make sure its in this lane in one of the sources
3835 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3836 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3839 // If not lane 0, then we must match lane 0
3840 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3843 // Correct second source to be contiguous with first source
3844 if (Start >= (int)NumElts)
3845 Start -= NumElts - NumLaneElts;
3847 // Make sure we're shifting in the right direction.
3848 if (Start <= (int)(i+l))
3853 // Check the rest of the elements to see if they are consecutive.
3854 for (++i; i != NumLaneElts; ++i) {
3855 int Idx = Mask[i+l];
3857 // Make sure its in this lane
3858 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3859 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3862 // If not lane 0, then we must match lane 0
3863 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3866 if (Idx >= (int)NumElts)
3867 Idx -= NumElts - NumLaneElts;
3869 if (!isUndefOrEqual(Idx, Start+i))
3878 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3879 /// the two vector operands have swapped position.
3880 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3881 unsigned NumElems) {
3882 for (unsigned i = 0; i != NumElems; ++i) {
3886 else if (idx < (int)NumElems)
3887 Mask[i] = idx + NumElems;
3889 Mask[i] = idx - NumElems;
3893 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3894 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3895 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3896 /// reverse of what x86 shuffles want.
3897 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3899 unsigned NumElems = VT.getVectorNumElements();
3900 unsigned NumLanes = VT.getSizeInBits()/128;
3901 unsigned NumLaneElems = NumElems/NumLanes;
3903 if (NumLaneElems != 2 && NumLaneElems != 4)
3906 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3907 bool symetricMaskRequired =
3908 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3910 // VSHUFPSY divides the resulting vector into 4 chunks.
3911 // The sources are also splitted into 4 chunks, and each destination
3912 // chunk must come from a different source chunk.
3914 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3915 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3917 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3918 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3920 // VSHUFPDY divides the resulting vector into 4 chunks.
3921 // The sources are also splitted into 4 chunks, and each destination
3922 // chunk must come from a different source chunk.
3924 // SRC1 => X3 X2 X1 X0
3925 // SRC2 => Y3 Y2 Y1 Y0
3927 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3929 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3930 unsigned HalfLaneElems = NumLaneElems/2;
3931 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3932 for (unsigned i = 0; i != NumLaneElems; ++i) {
3933 int Idx = Mask[i+l];
3934 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3935 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3937 // For VSHUFPSY, the mask of the second half must be the same as the
3938 // first but with the appropriate offsets. This works in the same way as
3939 // VPERMILPS works with masks.
3940 if (!symetricMaskRequired || Idx < 0)
3942 if (MaskVal[i] < 0) {
3943 MaskVal[i] = Idx - l;
3946 if ((signed)(Idx - l) != MaskVal[i])
3954 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3955 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3956 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3957 if (!VT.is128BitVector())
3960 unsigned NumElems = VT.getVectorNumElements();
3965 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3966 return isUndefOrEqual(Mask[0], 6) &&
3967 isUndefOrEqual(Mask[1], 7) &&
3968 isUndefOrEqual(Mask[2], 2) &&
3969 isUndefOrEqual(Mask[3], 3);
3972 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3973 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3975 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3976 if (!VT.is128BitVector())
3979 unsigned NumElems = VT.getVectorNumElements();
3984 return isUndefOrEqual(Mask[0], 2) &&
3985 isUndefOrEqual(Mask[1], 3) &&
3986 isUndefOrEqual(Mask[2], 2) &&
3987 isUndefOrEqual(Mask[3], 3);
3990 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3991 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3992 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3993 if (!VT.is128BitVector())
3996 unsigned NumElems = VT.getVectorNumElements();
3998 if (NumElems != 2 && NumElems != 4)
4001 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4002 if (!isUndefOrEqual(Mask[i], i + NumElems))
4005 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4006 if (!isUndefOrEqual(Mask[i], i))
4012 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4013 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4014 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4015 if (!VT.is128BitVector())
4018 unsigned NumElems = VT.getVectorNumElements();
4020 if (NumElems != 2 && NumElems != 4)
4023 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4024 if (!isUndefOrEqual(Mask[i], i))
4027 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4028 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4034 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4035 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4036 /// i. e: If all but one element come from the same vector.
4037 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4038 // TODO: Deal with AVX's VINSERTPS
4039 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4042 unsigned CorrectPosV1 = 0;
4043 unsigned CorrectPosV2 = 0;
4044 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4045 if (Mask[i] == -1) {
4053 else if (Mask[i] == i + 4)
4057 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4058 // We have 3 elements (undefs count as elements from any vector) from one
4059 // vector, and one from another.
4066 // Some special combinations that can be optimized.
4069 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4070 SelectionDAG &DAG) {
4071 MVT VT = SVOp->getSimpleValueType(0);
4074 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4077 ArrayRef<int> Mask = SVOp->getMask();
4079 // These are the special masks that may be optimized.
4080 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4081 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4082 bool MatchEvenMask = true;
4083 bool MatchOddMask = true;
4084 for (int i=0; i<8; ++i) {
4085 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4086 MatchEvenMask = false;
4087 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4088 MatchOddMask = false;
4091 if (!MatchEvenMask && !MatchOddMask)
4094 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4096 SDValue Op0 = SVOp->getOperand(0);
4097 SDValue Op1 = SVOp->getOperand(1);
4099 if (MatchEvenMask) {
4100 // Shift the second operand right to 32 bits.
4101 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4102 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4104 // Shift the first operand left to 32 bits.
4105 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4106 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4108 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4109 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4112 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4113 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4114 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4115 bool HasInt256, bool V2IsSplat = false) {
4117 assert(VT.getSizeInBits() >= 128 &&
4118 "Unsupported vector type for unpckl");
4120 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4122 unsigned NumOf256BitLanes;
4123 unsigned NumElts = VT.getVectorNumElements();
4124 if (VT.is256BitVector()) {
4125 if (NumElts != 4 && NumElts != 8 &&
4126 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4129 NumOf256BitLanes = 1;
4130 } else if (VT.is512BitVector()) {
4131 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4132 "Unsupported vector type for unpckh");
4134 NumOf256BitLanes = 2;
4137 NumOf256BitLanes = 1;
4140 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4141 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4143 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4144 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4145 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4146 int BitI = Mask[l256*NumEltsInStride+l+i];
4147 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4148 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4150 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4152 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4160 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4162 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4163 bool HasInt256, bool V2IsSplat = false) {
4164 assert(VT.getSizeInBits() >= 128 &&
4165 "Unsupported vector type for unpckh");
4167 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4169 unsigned NumOf256BitLanes;
4170 unsigned NumElts = VT.getVectorNumElements();
4171 if (VT.is256BitVector()) {
4172 if (NumElts != 4 && NumElts != 8 &&
4173 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4176 NumOf256BitLanes = 1;
4177 } else if (VT.is512BitVector()) {
4178 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4179 "Unsupported vector type for unpckh");
4181 NumOf256BitLanes = 2;
4184 NumOf256BitLanes = 1;
4187 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4188 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4190 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4191 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4192 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4193 int BitI = Mask[l256*NumEltsInStride+l+i];
4194 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4195 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4197 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4199 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4207 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4208 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4210 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4211 unsigned NumElts = VT.getVectorNumElements();
4212 bool Is256BitVec = VT.is256BitVector();
4214 if (VT.is512BitVector())
4216 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4217 "Unsupported vector type for unpckh");
4219 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4220 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4223 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4224 // FIXME: Need a better way to get rid of this, there's no latency difference
4225 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4226 // the former later. We should also remove the "_undef" special mask.
4227 if (NumElts == 4 && Is256BitVec)
4230 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4231 // independently on 128-bit lanes.
4232 unsigned NumLanes = VT.getSizeInBits()/128;
4233 unsigned NumLaneElts = NumElts/NumLanes;
4235 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4236 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4237 int BitI = Mask[l+i];
4238 int BitI1 = Mask[l+i+1];
4240 if (!isUndefOrEqual(BitI, j))
4242 if (!isUndefOrEqual(BitI1, j))
4250 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4251 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4253 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4254 unsigned NumElts = VT.getVectorNumElements();
4256 if (VT.is512BitVector())
4259 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4260 "Unsupported vector type for unpckh");
4262 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4263 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4266 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4267 // independently on 128-bit lanes.
4268 unsigned NumLanes = VT.getSizeInBits()/128;
4269 unsigned NumLaneElts = NumElts/NumLanes;
4271 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4272 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4273 int BitI = Mask[l+i];
4274 int BitI1 = Mask[l+i+1];
4275 if (!isUndefOrEqual(BitI, j))
4277 if (!isUndefOrEqual(BitI1, j))
4284 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4285 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4286 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4287 if (!VT.is512BitVector())
4290 unsigned NumElts = VT.getVectorNumElements();
4291 unsigned HalfSize = NumElts/2;
4292 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4293 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4298 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4299 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4307 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4308 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4309 /// MOVSD, and MOVD, i.e. setting the lowest element.
4310 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4311 if (VT.getVectorElementType().getSizeInBits() < 32)
4313 if (!VT.is128BitVector())
4316 unsigned NumElts = VT.getVectorNumElements();
4318 if (!isUndefOrEqual(Mask[0], NumElts))
4321 for (unsigned i = 1; i != NumElts; ++i)
4322 if (!isUndefOrEqual(Mask[i], i))
4328 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4329 /// as permutations between 128-bit chunks or halves. As an example: this
4331 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4332 /// The first half comes from the second half of V1 and the second half from the
4333 /// the second half of V2.
4334 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4335 if (!HasFp256 || !VT.is256BitVector())
4338 // The shuffle result is divided into half A and half B. In total the two
4339 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4340 // B must come from C, D, E or F.
4341 unsigned HalfSize = VT.getVectorNumElements()/2;
4342 bool MatchA = false, MatchB = false;
4344 // Check if A comes from one of C, D, E, F.
4345 for (unsigned Half = 0; Half != 4; ++Half) {
4346 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4352 // Check if B comes from one of C, D, E, F.
4353 for (unsigned Half = 0; Half != 4; ++Half) {
4354 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4360 return MatchA && MatchB;
4363 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4364 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4365 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4366 MVT VT = SVOp->getSimpleValueType(0);
4368 unsigned HalfSize = VT.getVectorNumElements()/2;
4370 unsigned FstHalf = 0, SndHalf = 0;
4371 for (unsigned i = 0; i < HalfSize; ++i) {
4372 if (SVOp->getMaskElt(i) > 0) {
4373 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4377 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4378 if (SVOp->getMaskElt(i) > 0) {
4379 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4384 return (FstHalf | (SndHalf << 4));
4387 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4388 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4389 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4393 unsigned NumElts = VT.getVectorNumElements();
4395 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4396 for (unsigned i = 0; i != NumElts; ++i) {
4399 Imm8 |= Mask[i] << (i*2);
4404 unsigned LaneSize = 4;
4405 SmallVector<int, 4> MaskVal(LaneSize, -1);
4407 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4408 for (unsigned i = 0; i != LaneSize; ++i) {
4409 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4413 if (MaskVal[i] < 0) {
4414 MaskVal[i] = Mask[i+l] - l;
4415 Imm8 |= MaskVal[i] << (i*2);
4418 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4425 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4426 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4427 /// Note that VPERMIL mask matching is different depending whether theunderlying
4428 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4429 /// to the same elements of the low, but to the higher half of the source.
4430 /// In VPERMILPD the two lanes could be shuffled independently of each other
4431 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4432 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4433 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4434 if (VT.getSizeInBits() < 256 || EltSize < 32)
4436 bool symetricMaskRequired = (EltSize == 32);
4437 unsigned NumElts = VT.getVectorNumElements();
4439 unsigned NumLanes = VT.getSizeInBits()/128;
4440 unsigned LaneSize = NumElts/NumLanes;
4441 // 2 or 4 elements in one lane
4443 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4444 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4445 for (unsigned i = 0; i != LaneSize; ++i) {
4446 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4448 if (symetricMaskRequired) {
4449 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4450 ExpectedMaskVal[i] = Mask[i+l] - l;
4453 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4461 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4462 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4463 /// element of vector 2 and the other elements to come from vector 1 in order.
4464 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4465 bool V2IsSplat = false, bool V2IsUndef = false) {
4466 if (!VT.is128BitVector())
4469 unsigned NumOps = VT.getVectorNumElements();
4470 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4473 if (!isUndefOrEqual(Mask[0], 0))
4476 for (unsigned i = 1; i != NumOps; ++i)
4477 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4478 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4479 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4485 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4486 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4487 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4488 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4489 const X86Subtarget *Subtarget) {
4490 if (!Subtarget->hasSSE3())
4493 unsigned NumElems = VT.getVectorNumElements();
4495 if ((VT.is128BitVector() && NumElems != 4) ||
4496 (VT.is256BitVector() && NumElems != 8) ||
4497 (VT.is512BitVector() && NumElems != 16))
4500 // "i+1" is the value the indexed mask element must have
4501 for (unsigned i = 0; i != NumElems; i += 2)
4502 if (!isUndefOrEqual(Mask[i], i+1) ||
4503 !isUndefOrEqual(Mask[i+1], i+1))
4509 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4510 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4511 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4512 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4513 const X86Subtarget *Subtarget) {
4514 if (!Subtarget->hasSSE3())
4517 unsigned NumElems = VT.getVectorNumElements();
4519 if ((VT.is128BitVector() && NumElems != 4) ||
4520 (VT.is256BitVector() && NumElems != 8) ||
4521 (VT.is512BitVector() && NumElems != 16))
4524 // "i" is the value the indexed mask element must have
4525 for (unsigned i = 0; i != NumElems; i += 2)
4526 if (!isUndefOrEqual(Mask[i], i) ||
4527 !isUndefOrEqual(Mask[i+1], i))
4533 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4534 /// specifies a shuffle of elements that is suitable for input to 256-bit
4535 /// version of MOVDDUP.
4536 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4537 if (!HasFp256 || !VT.is256BitVector())
4540 unsigned NumElts = VT.getVectorNumElements();
4544 for (unsigned i = 0; i != NumElts/2; ++i)
4545 if (!isUndefOrEqual(Mask[i], 0))
4547 for (unsigned i = NumElts/2; i != NumElts; ++i)
4548 if (!isUndefOrEqual(Mask[i], NumElts/2))
4553 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to 128-bit
4555 /// version of MOVDDUP.
4556 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4557 if (!VT.is128BitVector())
4560 unsigned e = VT.getVectorNumElements() / 2;
4561 for (unsigned i = 0; i != e; ++i)
4562 if (!isUndefOrEqual(Mask[i], i))
4564 for (unsigned i = 0; i != e; ++i)
4565 if (!isUndefOrEqual(Mask[e+i], i))
4570 /// isVEXTRACTIndex - Return true if the specified
4571 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4572 /// suitable for instruction that extract 128 or 256 bit vectors
4573 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4574 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4575 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4578 // The index should be aligned on a vecWidth-bit boundary.
4580 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4582 MVT VT = N->getSimpleValueType(0);
4583 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4584 bool Result = (Index * ElSize) % vecWidth == 0;
4589 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4590 /// operand specifies a subvector insert that is suitable for input to
4591 /// insertion of 128 or 256-bit subvectors
4592 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4593 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4594 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4596 // The index should be aligned on a vecWidth-bit boundary.
4598 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4600 MVT VT = N->getSimpleValueType(0);
4601 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4602 bool Result = (Index * ElSize) % vecWidth == 0;
4607 bool X86::isVINSERT128Index(SDNode *N) {
4608 return isVINSERTIndex(N, 128);
4611 bool X86::isVINSERT256Index(SDNode *N) {
4612 return isVINSERTIndex(N, 256);
4615 bool X86::isVEXTRACT128Index(SDNode *N) {
4616 return isVEXTRACTIndex(N, 128);
4619 bool X86::isVEXTRACT256Index(SDNode *N) {
4620 return isVEXTRACTIndex(N, 256);
4623 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4624 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4625 /// Handles 128-bit and 256-bit.
4626 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4627 MVT VT = N->getSimpleValueType(0);
4629 assert((VT.getSizeInBits() >= 128) &&
4630 "Unsupported vector type for PSHUF/SHUFP");
4632 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4633 // independently on 128-bit lanes.
4634 unsigned NumElts = VT.getVectorNumElements();
4635 unsigned NumLanes = VT.getSizeInBits()/128;
4636 unsigned NumLaneElts = NumElts/NumLanes;
4638 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4639 "Only supports 2, 4 or 8 elements per lane");
4641 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4643 for (unsigned i = 0; i != NumElts; ++i) {
4644 int Elt = N->getMaskElt(i);
4645 if (Elt < 0) continue;
4646 Elt &= NumLaneElts - 1;
4647 unsigned ShAmt = (i << Shift) % 8;
4648 Mask |= Elt << ShAmt;
4654 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4655 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4656 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4657 MVT VT = N->getSimpleValueType(0);
4659 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4660 "Unsupported vector type for PSHUFHW");
4662 unsigned NumElts = VT.getVectorNumElements();
4665 for (unsigned l = 0; l != NumElts; l += 8) {
4666 // 8 nodes per lane, but we only care about the last 4.
4667 for (unsigned i = 0; i < 4; ++i) {
4668 int Elt = N->getMaskElt(l+i+4);
4669 if (Elt < 0) continue;
4670 Elt &= 0x3; // only 2-bits.
4671 Mask |= Elt << (i * 2);
4678 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4679 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4680 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4681 MVT VT = N->getSimpleValueType(0);
4683 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4684 "Unsupported vector type for PSHUFHW");
4686 unsigned NumElts = VT.getVectorNumElements();
4689 for (unsigned l = 0; l != NumElts; l += 8) {
4690 // 8 nodes per lane, but we only care about the first 4.
4691 for (unsigned i = 0; i < 4; ++i) {
4692 int Elt = N->getMaskElt(l+i);
4693 if (Elt < 0) continue;
4694 Elt &= 0x3; // only 2-bits
4695 Mask |= Elt << (i * 2);
4702 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4703 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4704 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4705 MVT VT = SVOp->getSimpleValueType(0);
4706 unsigned EltSize = VT.is512BitVector() ? 1 :
4707 VT.getVectorElementType().getSizeInBits() >> 3;
4709 unsigned NumElts = VT.getVectorNumElements();
4710 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4711 unsigned NumLaneElts = NumElts/NumLanes;
4715 for (i = 0; i != NumElts; ++i) {
4716 Val = SVOp->getMaskElt(i);
4720 if (Val >= (int)NumElts)
4721 Val -= NumElts - NumLaneElts;
4723 assert(Val - i > 0 && "PALIGNR imm should be positive");
4724 return (Val - i) * EltSize;
4727 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4728 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4729 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4730 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4733 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4735 MVT VecVT = N->getOperand(0).getSimpleValueType();
4736 MVT ElVT = VecVT.getVectorElementType();
4738 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4739 return Index / NumElemsPerChunk;
4742 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4743 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4744 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4745 llvm_unreachable("Illegal insert subvector for VINSERT");
4748 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4750 MVT VecVT = N->getSimpleValueType(0);
4751 MVT ElVT = VecVT.getVectorElementType();
4753 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4754 return Index / NumElemsPerChunk;
4757 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4758 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4759 /// and VINSERTI128 instructions.
4760 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4761 return getExtractVEXTRACTImmediate(N, 128);
4764 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4765 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4766 /// and VINSERTI64x4 instructions.
4767 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4768 return getExtractVEXTRACTImmediate(N, 256);
4771 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4772 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4773 /// and VINSERTI128 instructions.
4774 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4775 return getInsertVINSERTImmediate(N, 128);
4778 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4779 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4780 /// and VINSERTI64x4 instructions.
4781 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4782 return getInsertVINSERTImmediate(N, 256);
4785 /// isZero - Returns true if Elt is a constant integer zero
4786 static bool isZero(SDValue V) {
4787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4788 return C && C->isNullValue();
4791 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4793 bool X86::isZeroNode(SDValue Elt) {
4796 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4797 return CFP->getValueAPF().isPosZero();
4801 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4802 /// match movhlps. The lower half elements should come from upper half of
4803 /// V1 (and in order), and the upper half elements should come from the upper
4804 /// half of V2 (and in order).
4805 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4806 if (!VT.is128BitVector())
4808 if (VT.getVectorNumElements() != 4)
4810 for (unsigned i = 0, e = 2; i != e; ++i)
4811 if (!isUndefOrEqual(Mask[i], i+2))
4813 for (unsigned i = 2; i != 4; ++i)
4814 if (!isUndefOrEqual(Mask[i], i+4))
4819 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4820 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4822 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4823 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4825 N = N->getOperand(0).getNode();
4826 if (!ISD::isNON_EXTLoad(N))
4829 *LD = cast<LoadSDNode>(N);
4833 // Test whether the given value is a vector value which will be legalized
4835 static bool WillBeConstantPoolLoad(SDNode *N) {
4836 if (N->getOpcode() != ISD::BUILD_VECTOR)
4839 // Check for any non-constant elements.
4840 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4841 switch (N->getOperand(i).getNode()->getOpcode()) {
4843 case ISD::ConstantFP:
4850 // Vectors of all-zeros and all-ones are materialized with special
4851 // instructions rather than being loaded.
4852 return !ISD::isBuildVectorAllZeros(N) &&
4853 !ISD::isBuildVectorAllOnes(N);
4856 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4857 /// match movlp{s|d}. The lower half elements should come from lower half of
4858 /// V1 (and in order), and the upper half elements should come from the upper
4859 /// half of V2 (and in order). And since V1 will become the source of the
4860 /// MOVLP, it must be either a vector load or a scalar load to vector.
4861 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4862 ArrayRef<int> Mask, MVT VT) {
4863 if (!VT.is128BitVector())
4866 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4868 // Is V2 is a vector load, don't do this transformation. We will try to use
4869 // load folding shufps op.
4870 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4873 unsigned NumElems = VT.getVectorNumElements();
4875 if (NumElems != 2 && NumElems != 4)
4877 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4878 if (!isUndefOrEqual(Mask[i], i))
4880 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4881 if (!isUndefOrEqual(Mask[i], i+NumElems))
4886 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4887 /// to an zero vector.
4888 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4889 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4890 SDValue V1 = N->getOperand(0);
4891 SDValue V2 = N->getOperand(1);
4892 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4893 for (unsigned i = 0; i != NumElems; ++i) {
4894 int Idx = N->getMaskElt(i);
4895 if (Idx >= (int)NumElems) {
4896 unsigned Opc = V2.getOpcode();
4897 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4899 if (Opc != ISD::BUILD_VECTOR ||
4900 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4902 } else if (Idx >= 0) {
4903 unsigned Opc = V1.getOpcode();
4904 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4906 if (Opc != ISD::BUILD_VECTOR ||
4907 !X86::isZeroNode(V1.getOperand(Idx)))
4914 /// getZeroVector - Returns a vector of specified type with all zero elements.
4916 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4917 SelectionDAG &DAG, SDLoc dl) {
4918 assert(VT.isVector() && "Expected a vector type");
4920 // Always build SSE zero vectors as <4 x i32> bitcasted
4921 // to their dest type. This ensures they get CSE'd.
4923 if (VT.is128BitVector()) { // SSE
4924 if (Subtarget->hasSSE2()) { // SSE2
4925 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4926 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4928 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4929 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4931 } else if (VT.is256BitVector()) { // AVX
4932 if (Subtarget->hasInt256()) { // AVX2
4933 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4934 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4935 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4937 // 256-bit logic and arithmetic instructions in AVX are all
4938 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4939 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4940 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4941 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4943 } else if (VT.is512BitVector()) { // AVX-512
4944 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4945 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4946 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4947 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4948 } else if (VT.getScalarType() == MVT::i1) {
4949 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4950 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4951 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4952 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4954 llvm_unreachable("Unexpected vector type");
4956 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4959 /// getOnesVector - Returns a vector of specified type with all bits set.
4960 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4961 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4962 /// Then bitcast to their original type, ensuring they get CSE'd.
4963 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4965 assert(VT.isVector() && "Expected a vector type");
4967 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4969 if (VT.is256BitVector()) {
4970 if (HasInt256) { // AVX2
4971 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4972 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4974 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4975 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4977 } else if (VT.is128BitVector()) {
4978 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4980 llvm_unreachable("Unexpected vector type");
4982 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4985 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4986 /// that point to V2 points to its first element.
4987 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4988 for (unsigned i = 0; i != NumElems; ++i) {
4989 if (Mask[i] > (int)NumElems) {
4995 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4996 /// operation of specified width.
4997 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4999 unsigned NumElems = VT.getVectorNumElements();
5000 SmallVector<int, 8> Mask;
5001 Mask.push_back(NumElems);
5002 for (unsigned i = 1; i != NumElems; ++i)
5004 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5007 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5008 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5010 unsigned NumElems = VT.getVectorNumElements();
5011 SmallVector<int, 8> Mask;
5012 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5014 Mask.push_back(i + NumElems);
5016 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5019 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5020 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5022 unsigned NumElems = VT.getVectorNumElements();
5023 SmallVector<int, 8> Mask;
5024 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5025 Mask.push_back(i + Half);
5026 Mask.push_back(i + NumElems + Half);
5028 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5031 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5032 // a generic shuffle instruction because the target has no such instructions.
5033 // Generate shuffles which repeat i16 and i8 several times until they can be
5034 // represented by v4f32 and then be manipulated by target suported shuffles.
5035 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5036 MVT VT = V.getSimpleValueType();
5037 int NumElems = VT.getVectorNumElements();
5040 while (NumElems > 4) {
5041 if (EltNo < NumElems/2) {
5042 V = getUnpackl(DAG, dl, VT, V, V);
5044 V = getUnpackh(DAG, dl, VT, V, V);
5045 EltNo -= NumElems/2;
5052 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5053 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5054 MVT VT = V.getSimpleValueType();
5057 if (VT.is128BitVector()) {
5058 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5059 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5060 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5062 } else if (VT.is256BitVector()) {
5063 // To use VPERMILPS to splat scalars, the second half of indicies must
5064 // refer to the higher part, which is a duplication of the lower one,
5065 // because VPERMILPS can only handle in-lane permutations.
5066 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5067 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5069 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5070 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5073 llvm_unreachable("Vector size not supported");
5075 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5078 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5079 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5080 MVT SrcVT = SV->getSimpleValueType(0);
5081 SDValue V1 = SV->getOperand(0);
5084 int EltNo = SV->getSplatIndex();
5085 int NumElems = SrcVT.getVectorNumElements();
5086 bool Is256BitVec = SrcVT.is256BitVector();
5088 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5089 "Unknown how to promote splat for type");
5091 // Extract the 128-bit part containing the splat element and update
5092 // the splat element index when it refers to the higher register.
5094 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5095 if (EltNo >= NumElems/2)
5096 EltNo -= NumElems/2;
5099 // All i16 and i8 vector types can't be used directly by a generic shuffle
5100 // instruction because the target has no such instruction. Generate shuffles
5101 // which repeat i16 and i8 several times until they fit in i32, and then can
5102 // be manipulated by target suported shuffles.
5103 MVT EltVT = SrcVT.getVectorElementType();
5104 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5105 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5107 // Recreate the 256-bit vector and place the same 128-bit vector
5108 // into the low and high part. This is necessary because we want
5109 // to use VPERM* to shuffle the vectors
5111 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5114 return getLegalSplat(DAG, V1, EltNo);
5117 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5118 /// vector of zero or undef vector. This produces a shuffle where the low
5119 /// element of V2 is swizzled into the zero/undef vector, landing at element
5120 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5121 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5123 const X86Subtarget *Subtarget,
5124 SelectionDAG &DAG) {
5125 MVT VT = V2.getSimpleValueType();
5127 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5128 unsigned NumElems = VT.getVectorNumElements();
5129 SmallVector<int, 16> MaskVec;
5130 for (unsigned i = 0; i != NumElems; ++i)
5131 // If this is the insertion idx, put the low elt of V2 here.
5132 MaskVec.push_back(i == Idx ? NumElems : i);
5133 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5136 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5137 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5138 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5139 /// shuffles which use a single input multiple times, and in those cases it will
5140 /// adjust the mask to only have indices within that single input.
5141 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5142 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5143 unsigned NumElems = VT.getVectorNumElements();
5147 bool IsFakeUnary = false;
5148 switch(N->getOpcode()) {
5150 ImmN = N->getOperand(N->getNumOperands()-1);
5151 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5152 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5154 case X86ISD::UNPCKH:
5155 DecodeUNPCKHMask(VT, Mask);
5156 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5158 case X86ISD::UNPCKL:
5159 DecodeUNPCKLMask(VT, Mask);
5160 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5162 case X86ISD::MOVHLPS:
5163 DecodeMOVHLPSMask(NumElems, Mask);
5164 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5166 case X86ISD::MOVLHPS:
5167 DecodeMOVLHPSMask(NumElems, Mask);
5168 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5170 case X86ISD::PALIGNR:
5171 ImmN = N->getOperand(N->getNumOperands()-1);
5172 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5174 case X86ISD::PSHUFD:
5175 case X86ISD::VPERMILP:
5176 ImmN = N->getOperand(N->getNumOperands()-1);
5177 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5180 case X86ISD::PSHUFHW:
5181 ImmN = N->getOperand(N->getNumOperands()-1);
5182 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5185 case X86ISD::PSHUFLW:
5186 ImmN = N->getOperand(N->getNumOperands()-1);
5187 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5190 case X86ISD::PSHUFB: {
5192 SDValue MaskNode = N->getOperand(1);
5193 while (MaskNode->getOpcode() == ISD::BITCAST)
5194 MaskNode = MaskNode->getOperand(0);
5196 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5197 // If we have a build-vector, then things are easy.
5198 EVT VT = MaskNode.getValueType();
5199 assert(VT.isVector() &&
5200 "Can't produce a non-vector with a build_vector!");
5201 if (!VT.isInteger())
5204 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5206 SmallVector<uint64_t, 32> RawMask;
5207 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5208 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5211 APInt MaskElement = CN->getAPIntValue();
5213 // We now have to decode the element which could be any integer size and
5214 // extract each byte of it.
5215 for (int j = 0; j < NumBytesPerElement; ++j) {
5216 // Note that this is x86 and so always little endian: the low byte is
5217 // the first byte of the mask.
5218 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5219 MaskElement = MaskElement.lshr(8);
5222 DecodePSHUFBMask(RawMask, Mask);
5226 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5230 SDValue Ptr = MaskLoad->getBasePtr();
5231 if (Ptr->getOpcode() == X86ISD::Wrapper)
5232 Ptr = Ptr->getOperand(0);
5234 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5235 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5238 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5239 // FIXME: Support AVX-512 here.
5240 if (!C->getType()->isVectorTy() ||
5241 (C->getNumElements() != 16 && C->getNumElements() != 32))
5244 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5245 DecodePSHUFBMask(C, Mask);
5251 case X86ISD::VPERMI:
5252 ImmN = N->getOperand(N->getNumOperands()-1);
5253 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5257 case X86ISD::MOVSD: {
5258 // The index 0 always comes from the first element of the second source,
5259 // this is why MOVSS and MOVSD are used in the first place. The other
5260 // elements come from the other positions of the first source vector
5261 Mask.push_back(NumElems);
5262 for (unsigned i = 1; i != NumElems; ++i) {
5267 case X86ISD::VPERM2X128:
5268 ImmN = N->getOperand(N->getNumOperands()-1);
5269 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5270 if (Mask.empty()) return false;
5272 case X86ISD::MOVDDUP:
5273 case X86ISD::MOVLHPD:
5274 case X86ISD::MOVLPD:
5275 case X86ISD::MOVLPS:
5276 case X86ISD::MOVSHDUP:
5277 case X86ISD::MOVSLDUP:
5278 // Not yet implemented
5280 default: llvm_unreachable("unknown target shuffle node");
5283 // If we have a fake unary shuffle, the shuffle mask is spread across two
5284 // inputs that are actually the same node. Re-map the mask to always point
5285 // into the first input.
5288 if (M >= (int)Mask.size())
5294 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5295 /// element of the result of the vector shuffle.
5296 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5299 return SDValue(); // Limit search depth.
5301 SDValue V = SDValue(N, 0);
5302 EVT VT = V.getValueType();
5303 unsigned Opcode = V.getOpcode();
5305 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5306 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5307 int Elt = SV->getMaskElt(Index);
5310 return DAG.getUNDEF(VT.getVectorElementType());
5312 unsigned NumElems = VT.getVectorNumElements();
5313 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5314 : SV->getOperand(1);
5315 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5318 // Recurse into target specific vector shuffles to find scalars.
5319 if (isTargetShuffle(Opcode)) {
5320 MVT ShufVT = V.getSimpleValueType();
5321 unsigned NumElems = ShufVT.getVectorNumElements();
5322 SmallVector<int, 16> ShuffleMask;
5325 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5328 int Elt = ShuffleMask[Index];
5330 return DAG.getUNDEF(ShufVT.getVectorElementType());
5332 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5334 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5338 // Actual nodes that may contain scalar elements
5339 if (Opcode == ISD::BITCAST) {
5340 V = V.getOperand(0);
5341 EVT SrcVT = V.getValueType();
5342 unsigned NumElems = VT.getVectorNumElements();
5344 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5348 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5349 return (Index == 0) ? V.getOperand(0)
5350 : DAG.getUNDEF(VT.getVectorElementType());
5352 if (V.getOpcode() == ISD::BUILD_VECTOR)
5353 return V.getOperand(Index);
5358 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5359 /// shuffle operation which come from a consecutively from a zero. The
5360 /// search can start in two different directions, from left or right.
5361 /// We count undefs as zeros until PreferredNum is reached.
5362 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5363 unsigned NumElems, bool ZerosFromLeft,
5365 unsigned PreferredNum = -1U) {
5366 unsigned NumZeros = 0;
5367 for (unsigned i = 0; i != NumElems; ++i) {
5368 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5369 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5373 if (X86::isZeroNode(Elt))
5375 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5376 NumZeros = std::min(NumZeros + 1, PreferredNum);
5384 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5385 /// correspond consecutively to elements from one of the vector operands,
5386 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5388 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5389 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5390 unsigned NumElems, unsigned &OpNum) {
5391 bool SeenV1 = false;
5392 bool SeenV2 = false;
5394 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5395 int Idx = SVOp->getMaskElt(i);
5396 // Ignore undef indicies
5400 if (Idx < (int)NumElems)
5405 // Only accept consecutive elements from the same vector
5406 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5410 OpNum = SeenV1 ? 0 : 1;
5414 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5415 /// logical left shift of a vector.
5416 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5417 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5419 SVOp->getSimpleValueType(0).getVectorNumElements();
5420 unsigned NumZeros = getNumOfConsecutiveZeros(
5421 SVOp, NumElems, false /* check zeros from right */, DAG,
5422 SVOp->getMaskElt(0));
5428 // Considering the elements in the mask that are not consecutive zeros,
5429 // check if they consecutively come from only one of the source vectors.
5431 // V1 = {X, A, B, C} 0
5433 // vector_shuffle V1, V2 <1, 2, 3, X>
5435 if (!isShuffleMaskConsecutive(SVOp,
5436 0, // Mask Start Index
5437 NumElems-NumZeros, // Mask End Index(exclusive)
5438 NumZeros, // Where to start looking in the src vector
5439 NumElems, // Number of elements in vector
5440 OpSrc)) // Which source operand ?
5445 ShVal = SVOp->getOperand(OpSrc);
5449 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5450 /// logical left shift of a vector.
5451 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5452 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5454 SVOp->getSimpleValueType(0).getVectorNumElements();
5455 unsigned NumZeros = getNumOfConsecutiveZeros(
5456 SVOp, NumElems, true /* check zeros from left */, DAG,
5457 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5463 // Considering the elements in the mask that are not consecutive zeros,
5464 // check if they consecutively come from only one of the source vectors.
5466 // 0 { A, B, X, X } = V2
5468 // vector_shuffle V1, V2 <X, X, 4, 5>
5470 if (!isShuffleMaskConsecutive(SVOp,
5471 NumZeros, // Mask Start Index
5472 NumElems, // Mask End Index(exclusive)
5473 0, // Where to start looking in the src vector
5474 NumElems, // Number of elements in vector
5475 OpSrc)) // Which source operand ?
5480 ShVal = SVOp->getOperand(OpSrc);
5484 /// isVectorShift - Returns true if the shuffle can be implemented as a
5485 /// logical left or right shift of a vector.
5486 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5487 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5488 // Although the logic below support any bitwidth size, there are no
5489 // shift instructions which handle more than 128-bit vectors.
5490 if (!SVOp->getSimpleValueType(0).is128BitVector())
5493 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5494 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5500 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5502 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5503 unsigned NumNonZero, unsigned NumZero,
5505 const X86Subtarget* Subtarget,
5506 const TargetLowering &TLI) {
5513 for (unsigned i = 0; i < 16; ++i) {
5514 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5515 if (ThisIsNonZero && First) {
5517 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5519 V = DAG.getUNDEF(MVT::v8i16);
5524 SDValue ThisElt, LastElt;
5525 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5526 if (LastIsNonZero) {
5527 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5528 MVT::i16, Op.getOperand(i-1));
5530 if (ThisIsNonZero) {
5531 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5532 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5533 ThisElt, DAG.getConstant(8, MVT::i8));
5535 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5539 if (ThisElt.getNode())
5540 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5541 DAG.getIntPtrConstant(i/2));
5545 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5548 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5550 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5551 unsigned NumNonZero, unsigned NumZero,
5553 const X86Subtarget* Subtarget,
5554 const TargetLowering &TLI) {
5561 for (unsigned i = 0; i < 8; ++i) {
5562 bool isNonZero = (NonZeros & (1 << i)) != 0;
5566 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5568 V = DAG.getUNDEF(MVT::v8i16);
5571 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5572 MVT::v8i16, V, Op.getOperand(i),
5573 DAG.getIntPtrConstant(i));
5580 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5581 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5582 unsigned NonZeros, unsigned NumNonZero,
5583 unsigned NumZero, SelectionDAG &DAG,
5584 const X86Subtarget *Subtarget,
5585 const TargetLowering &TLI) {
5586 // We know there's at least one non-zero element
5587 unsigned FirstNonZeroIdx = 0;
5588 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5589 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5590 X86::isZeroNode(FirstNonZero)) {
5592 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5595 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5596 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5599 SDValue V = FirstNonZero.getOperand(0);
5600 MVT VVT = V.getSimpleValueType();
5601 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5604 unsigned FirstNonZeroDst =
5605 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5606 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5607 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5608 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5610 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5611 SDValue Elem = Op.getOperand(Idx);
5612 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5615 // TODO: What else can be here? Deal with it.
5616 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5619 // TODO: Some optimizations are still possible here
5620 // ex: Getting one element from a vector, and the rest from another.
5621 if (Elem.getOperand(0) != V)
5624 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5627 else if (IncorrectIdx == -1U) {
5631 // There was already one element with an incorrect index.
5632 // We can't optimize this case to an insertps.
5636 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5638 EVT VT = Op.getSimpleValueType();
5639 unsigned ElementMoveMask = 0;
5640 if (IncorrectIdx == -1U)
5641 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5643 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5645 SDValue InsertpsMask =
5646 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5647 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5653 /// getVShift - Return a vector logical shift node.
5655 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5656 unsigned NumBits, SelectionDAG &DAG,
5657 const TargetLowering &TLI, SDLoc dl) {
5658 assert(VT.is128BitVector() && "Unknown type for VShift");
5659 EVT ShVT = MVT::v2i64;
5660 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5661 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5662 return DAG.getNode(ISD::BITCAST, dl, VT,
5663 DAG.getNode(Opc, dl, ShVT, SrcOp,
5664 DAG.getConstant(NumBits,
5665 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5669 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5671 // Check if the scalar load can be widened into a vector load. And if
5672 // the address is "base + cst" see if the cst can be "absorbed" into
5673 // the shuffle mask.
5674 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5675 SDValue Ptr = LD->getBasePtr();
5676 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5678 EVT PVT = LD->getValueType(0);
5679 if (PVT != MVT::i32 && PVT != MVT::f32)
5684 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5685 FI = FINode->getIndex();
5687 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5688 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5689 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5690 Offset = Ptr.getConstantOperandVal(1);
5691 Ptr = Ptr.getOperand(0);
5696 // FIXME: 256-bit vector instructions don't require a strict alignment,
5697 // improve this code to support it better.
5698 unsigned RequiredAlign = VT.getSizeInBits()/8;
5699 SDValue Chain = LD->getChain();
5700 // Make sure the stack object alignment is at least 16 or 32.
5701 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5702 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5703 if (MFI->isFixedObjectIndex(FI)) {
5704 // Can't change the alignment. FIXME: It's possible to compute
5705 // the exact stack offset and reference FI + adjust offset instead.
5706 // If someone *really* cares about this. That's the way to implement it.
5709 MFI->setObjectAlignment(FI, RequiredAlign);
5713 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5714 // Ptr + (Offset & ~15).
5717 if ((Offset % RequiredAlign) & 3)
5719 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5721 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5722 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5724 int EltNo = (Offset - StartOffset) >> 2;
5725 unsigned NumElems = VT.getVectorNumElements();
5727 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5728 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5729 LD->getPointerInfo().getWithOffset(StartOffset),
5730 false, false, false, 0);
5732 SmallVector<int, 8> Mask;
5733 for (unsigned i = 0; i != NumElems; ++i)
5734 Mask.push_back(EltNo);
5736 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5742 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5743 /// vector of type 'VT', see if the elements can be replaced by a single large
5744 /// load which has the same value as a build_vector whose operands are 'elts'.
5746 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5748 /// FIXME: we'd also like to handle the case where the last elements are zero
5749 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5750 /// There's even a handy isZeroNode for that purpose.
5751 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5752 SDLoc &DL, SelectionDAG &DAG,
5753 bool isAfterLegalize) {
5754 EVT EltVT = VT.getVectorElementType();
5755 unsigned NumElems = Elts.size();
5757 LoadSDNode *LDBase = nullptr;
5758 unsigned LastLoadedElt = -1U;
5760 // For each element in the initializer, see if we've found a load or an undef.
5761 // If we don't find an initial load element, or later load elements are
5762 // non-consecutive, bail out.
5763 for (unsigned i = 0; i < NumElems; ++i) {
5764 SDValue Elt = Elts[i];
5766 if (!Elt.getNode() ||
5767 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5770 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5772 LDBase = cast<LoadSDNode>(Elt.getNode());
5776 if (Elt.getOpcode() == ISD::UNDEF)
5779 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5780 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5785 // If we have found an entire vector of loads and undefs, then return a large
5786 // load of the entire vector width starting at the base pointer. If we found
5787 // consecutive loads for the low half, generate a vzext_load node.
5788 if (LastLoadedElt == NumElems - 1) {
5790 if (isAfterLegalize &&
5791 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5794 SDValue NewLd = SDValue();
5796 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5797 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5798 LDBase->getPointerInfo(),
5799 LDBase->isVolatile(), LDBase->isNonTemporal(),
5800 LDBase->isInvariant(), 0);
5801 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5802 LDBase->getPointerInfo(),
5803 LDBase->isVolatile(), LDBase->isNonTemporal(),
5804 LDBase->isInvariant(), LDBase->getAlignment());
5806 if (LDBase->hasAnyUseOfValue(1)) {
5807 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5809 SDValue(NewLd.getNode(), 1));
5810 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5811 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5812 SDValue(NewLd.getNode(), 1));
5817 if (NumElems == 4 && LastLoadedElt == 1 &&
5818 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5819 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5820 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5822 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5823 LDBase->getPointerInfo(),
5824 LDBase->getAlignment(),
5825 false/*isVolatile*/, true/*ReadMem*/,
5828 // Make sure the newly-created LOAD is in the same position as LDBase in
5829 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5830 // update uses of LDBase's output chain to use the TokenFactor.
5831 if (LDBase->hasAnyUseOfValue(1)) {
5832 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5833 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5834 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5835 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5836 SDValue(ResNode.getNode(), 1));
5839 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5844 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5845 /// to generate a splat value for the following cases:
5846 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5847 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5848 /// a scalar load, or a constant.
5849 /// The VBROADCAST node is returned when a pattern is found,
5850 /// or SDValue() otherwise.
5851 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5852 SelectionDAG &DAG) {
5853 if (!Subtarget->hasFp256())
5856 MVT VT = Op.getSimpleValueType();
5859 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5860 "Unsupported vector type for broadcast.");
5865 switch (Op.getOpcode()) {
5867 // Unknown pattern found.
5870 case ISD::BUILD_VECTOR: {
5871 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5872 BitVector UndefElements;
5873 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5875 // We need a splat of a single value to use broadcast, and it doesn't
5876 // make any sense if the value is only in one element of the vector.
5877 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5881 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5882 Ld.getOpcode() == ISD::ConstantFP);
5884 // Make sure that all of the users of a non-constant load are from the
5885 // BUILD_VECTOR node.
5886 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5891 case ISD::VECTOR_SHUFFLE: {
5892 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5894 // Shuffles must have a splat mask where the first element is
5896 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5899 SDValue Sc = Op.getOperand(0);
5900 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5901 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5903 if (!Subtarget->hasInt256())
5906 // Use the register form of the broadcast instruction available on AVX2.
5907 if (VT.getSizeInBits() >= 256)
5908 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5909 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5912 Ld = Sc.getOperand(0);
5913 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5914 Ld.getOpcode() == ISD::ConstantFP);
5916 // The scalar_to_vector node and the suspected
5917 // load node must have exactly one user.
5918 // Constants may have multiple users.
5920 // AVX-512 has register version of the broadcast
5921 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5922 Ld.getValueType().getSizeInBits() >= 32;
5923 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5930 bool IsGE256 = (VT.getSizeInBits() >= 256);
5932 // Handle the broadcasting a single constant scalar from the constant pool
5933 // into a vector. On Sandybridge it is still better to load a constant vector
5934 // from the constant pool and not to broadcast it from a scalar.
5935 if (ConstSplatVal && Subtarget->hasInt256()) {
5936 EVT CVT = Ld.getValueType();
5937 assert(!CVT.isVector() && "Must not broadcast a vector type");
5938 unsigned ScalarSize = CVT.getSizeInBits();
5940 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5941 const Constant *C = nullptr;
5942 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5943 C = CI->getConstantIntValue();
5944 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5945 C = CF->getConstantFPValue();
5947 assert(C && "Invalid constant type");
5949 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5950 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5951 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5952 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5953 MachinePointerInfo::getConstantPool(),
5954 false, false, false, Alignment);
5956 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5960 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5961 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5963 // Handle AVX2 in-register broadcasts.
5964 if (!IsLoad && Subtarget->hasInt256() &&
5965 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5966 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5968 // The scalar source must be a normal load.
5972 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5973 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5975 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5976 // double since there is no vbroadcastsd xmm
5977 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5978 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5979 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5982 // Unsupported broadcast.
5986 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5987 /// underlying vector and index.
5989 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5991 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5993 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5994 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5997 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5999 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6001 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6002 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6005 // In this case the vector is the extract_subvector expression and the index
6006 // is 2, as specified by the shuffle.
6007 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6008 SDValue ShuffleVec = SVOp->getOperand(0);
6009 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6010 assert(ShuffleVecVT.getVectorElementType() ==
6011 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6013 int ShuffleIdx = SVOp->getMaskElt(Idx);
6014 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6015 ExtractedFromVec = ShuffleVec;
6021 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6022 MVT VT = Op.getSimpleValueType();
6024 // Skip if insert_vec_elt is not supported.
6025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6026 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6030 unsigned NumElems = Op.getNumOperands();
6034 SmallVector<unsigned, 4> InsertIndices;
6035 SmallVector<int, 8> Mask(NumElems, -1);
6037 for (unsigned i = 0; i != NumElems; ++i) {
6038 unsigned Opc = Op.getOperand(i).getOpcode();
6040 if (Opc == ISD::UNDEF)
6043 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6044 // Quit if more than 1 elements need inserting.
6045 if (InsertIndices.size() > 1)
6048 InsertIndices.push_back(i);
6052 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6053 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6054 // Quit if non-constant index.
6055 if (!isa<ConstantSDNode>(ExtIdx))
6057 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6059 // Quit if extracted from vector of different type.
6060 if (ExtractedFromVec.getValueType() != VT)
6063 if (!VecIn1.getNode())
6064 VecIn1 = ExtractedFromVec;
6065 else if (VecIn1 != ExtractedFromVec) {
6066 if (!VecIn2.getNode())
6067 VecIn2 = ExtractedFromVec;
6068 else if (VecIn2 != ExtractedFromVec)
6069 // Quit if more than 2 vectors to shuffle
6073 if (ExtractedFromVec == VecIn1)
6075 else if (ExtractedFromVec == VecIn2)
6076 Mask[i] = Idx + NumElems;
6079 if (!VecIn1.getNode())
6082 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6083 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6084 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6085 unsigned Idx = InsertIndices[i];
6086 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6087 DAG.getIntPtrConstant(Idx));
6093 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6095 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6097 MVT VT = Op.getSimpleValueType();
6098 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6099 "Unexpected type in LowerBUILD_VECTORvXi1!");
6102 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6103 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6104 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6105 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6108 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6109 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6110 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6111 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6114 bool AllContants = true;
6115 uint64_t Immediate = 0;
6116 int NonConstIdx = -1;
6117 bool IsSplat = true;
6118 unsigned NumNonConsts = 0;
6119 unsigned NumConsts = 0;
6120 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6121 SDValue In = Op.getOperand(idx);
6122 if (In.getOpcode() == ISD::UNDEF)
6124 if (!isa<ConstantSDNode>(In)) {
6125 AllContants = false;
6131 if (cast<ConstantSDNode>(In)->getZExtValue())
6132 Immediate |= (1ULL << idx);
6134 if (In != Op.getOperand(0))
6139 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6140 DAG.getConstant(Immediate, MVT::i16));
6141 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6142 DAG.getIntPtrConstant(0));
6145 if (NumNonConsts == 1 && NonConstIdx != 0) {
6148 SDValue VecAsImm = DAG.getConstant(Immediate,
6149 MVT::getIntegerVT(VT.getSizeInBits()));
6150 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6153 DstVec = DAG.getUNDEF(VT);
6154 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6155 Op.getOperand(NonConstIdx),
6156 DAG.getIntPtrConstant(NonConstIdx));
6158 if (!IsSplat && (NonConstIdx != 0))
6159 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6160 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6163 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6164 DAG.getConstant(-1, SelectVT),
6165 DAG.getConstant(0, SelectVT));
6167 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6168 DAG.getConstant((Immediate | 1), SelectVT),
6169 DAG.getConstant(Immediate, SelectVT));
6170 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6173 /// \brief Return true if \p N implements a horizontal binop and return the
6174 /// operands for the horizontal binop into V0 and V1.
6176 /// This is a helper function of PerformBUILD_VECTORCombine.
6177 /// This function checks that the build_vector \p N in input implements a
6178 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6179 /// operation to match.
6180 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6181 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6182 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6185 /// This function only analyzes elements of \p N whose indices are
6186 /// in range [BaseIdx, LastIdx).
6187 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6189 unsigned BaseIdx, unsigned LastIdx,
6190 SDValue &V0, SDValue &V1) {
6191 EVT VT = N->getValueType(0);
6193 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6194 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6195 "Invalid Vector in input!");
6197 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6198 bool CanFold = true;
6199 unsigned ExpectedVExtractIdx = BaseIdx;
6200 unsigned NumElts = LastIdx - BaseIdx;
6201 V0 = DAG.getUNDEF(VT);
6202 V1 = DAG.getUNDEF(VT);
6204 // Check if N implements a horizontal binop.
6205 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6206 SDValue Op = N->getOperand(i + BaseIdx);
6209 if (Op->getOpcode() == ISD::UNDEF) {
6210 // Update the expected vector extract index.
6211 if (i * 2 == NumElts)
6212 ExpectedVExtractIdx = BaseIdx;
6213 ExpectedVExtractIdx += 2;
6217 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6222 SDValue Op0 = Op.getOperand(0);
6223 SDValue Op1 = Op.getOperand(1);
6225 // Try to match the following pattern:
6226 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6227 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6228 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6229 Op0.getOperand(0) == Op1.getOperand(0) &&
6230 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6231 isa<ConstantSDNode>(Op1.getOperand(1)));
6235 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6236 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6238 if (i * 2 < NumElts) {
6239 if (V0.getOpcode() == ISD::UNDEF)
6240 V0 = Op0.getOperand(0);
6242 if (V1.getOpcode() == ISD::UNDEF)
6243 V1 = Op0.getOperand(0);
6244 if (i * 2 == NumElts)
6245 ExpectedVExtractIdx = BaseIdx;
6248 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6249 if (I0 == ExpectedVExtractIdx)
6250 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6251 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6252 // Try to match the following dag sequence:
6253 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6254 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6258 ExpectedVExtractIdx += 2;
6264 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6265 /// a concat_vector.
6267 /// This is a helper function of PerformBUILD_VECTORCombine.
6268 /// This function expects two 256-bit vectors called V0 and V1.
6269 /// At first, each vector is split into two separate 128-bit vectors.
6270 /// Then, the resulting 128-bit vectors are used to implement two
6271 /// horizontal binary operations.
6273 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6275 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6276 /// the two new horizontal binop.
6277 /// When Mode is set, the first horizontal binop dag node would take as input
6278 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6279 /// horizontal binop dag node would take as input the lower 128-bit of V1
6280 /// and the upper 128-bit of V1.
6282 /// HADD V0_LO, V0_HI
6283 /// HADD V1_LO, V1_HI
6285 /// Otherwise, the first horizontal binop dag node takes as input the lower
6286 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6287 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6289 /// HADD V0_LO, V1_LO
6290 /// HADD V0_HI, V1_HI
6292 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6293 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6294 /// the upper 128-bits of the result.
6295 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6296 SDLoc DL, SelectionDAG &DAG,
6297 unsigned X86Opcode, bool Mode,
6298 bool isUndefLO, bool isUndefHI) {
6299 EVT VT = V0.getValueType();
6300 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6301 "Invalid nodes in input!");
6303 unsigned NumElts = VT.getVectorNumElements();
6304 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6305 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6306 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6307 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6308 EVT NewVT = V0_LO.getValueType();
6310 SDValue LO = DAG.getUNDEF(NewVT);
6311 SDValue HI = DAG.getUNDEF(NewVT);
6314 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6315 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6316 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6317 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6318 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6320 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6321 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6322 V1_LO->getOpcode() != ISD::UNDEF))
6323 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6325 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6326 V1_HI->getOpcode() != ISD::UNDEF))
6327 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6330 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6333 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6334 /// sequence of 'vadd + vsub + blendi'.
6335 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6336 const X86Subtarget *Subtarget) {
6338 EVT VT = BV->getValueType(0);
6339 unsigned NumElts = VT.getVectorNumElements();
6340 SDValue InVec0 = DAG.getUNDEF(VT);
6341 SDValue InVec1 = DAG.getUNDEF(VT);
6343 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6344 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6346 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6348 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6351 // Odd-numbered elements in the input build vector are obtained from
6352 // adding two integer/float elements.
6353 // Even-numbered elements in the input build vector are obtained from
6354 // subtracting two integer/float elements.
6355 unsigned ExpectedOpcode = ISD::FSUB;
6356 unsigned NextExpectedOpcode = ISD::FADD;
6357 bool AddFound = false;
6358 bool SubFound = false;
6360 for (unsigned i = 0, e = NumElts; i != e; i++) {
6361 SDValue Op = BV->getOperand(i);
6363 // Skip 'undef' values.
6364 unsigned Opcode = Op.getOpcode();
6365 if (Opcode == ISD::UNDEF) {
6366 std::swap(ExpectedOpcode, NextExpectedOpcode);
6370 // Early exit if we found an unexpected opcode.
6371 if (Opcode != ExpectedOpcode)
6374 SDValue Op0 = Op.getOperand(0);
6375 SDValue Op1 = Op.getOperand(1);
6377 // Try to match the following pattern:
6378 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6379 // Early exit if we cannot match that sequence.
6380 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6381 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6382 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6383 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6384 Op0.getOperand(1) != Op1.getOperand(1))
6387 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6391 // We found a valid add/sub node. Update the information accordingly.
6397 // Update InVec0 and InVec1.
6398 if (InVec0.getOpcode() == ISD::UNDEF)
6399 InVec0 = Op0.getOperand(0);
6400 if (InVec1.getOpcode() == ISD::UNDEF)
6401 InVec1 = Op1.getOperand(0);
6403 // Make sure that operands in input to each add/sub node always
6404 // come from a same pair of vectors.
6405 if (InVec0 != Op0.getOperand(0)) {
6406 if (ExpectedOpcode == ISD::FSUB)
6409 // FADD is commutable. Try to commute the operands
6410 // and then test again.
6411 std::swap(Op0, Op1);
6412 if (InVec0 != Op0.getOperand(0))
6416 if (InVec1 != Op1.getOperand(0))
6419 // Update the pair of expected opcodes.
6420 std::swap(ExpectedOpcode, NextExpectedOpcode);
6423 // Don't try to fold this build_vector into a VSELECT if it has
6424 // too many UNDEF operands.
6425 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6426 InVec1.getOpcode() != ISD::UNDEF) {
6427 // Emit a sequence of vector add and sub followed by a VSELECT.
6428 // The new VSELECT will be lowered into a BLENDI.
6429 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6430 // and emit a single ADDSUB instruction.
6431 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6432 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6434 // Construct the VSELECT mask.
6435 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6436 EVT SVT = MaskVT.getVectorElementType();
6437 unsigned SVTBits = SVT.getSizeInBits();
6438 SmallVector<SDValue, 8> Ops;
6440 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6441 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6442 APInt::getAllOnesValue(SVTBits);
6443 SDValue Constant = DAG.getConstant(Value, SVT);
6444 Ops.push_back(Constant);
6447 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6448 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6454 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6455 const X86Subtarget *Subtarget) {
6457 EVT VT = N->getValueType(0);
6458 unsigned NumElts = VT.getVectorNumElements();
6459 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6460 SDValue InVec0, InVec1;
6462 // Try to match an ADDSUB.
6463 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6464 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6465 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6466 if (Value.getNode())
6470 // Try to match horizontal ADD/SUB.
6471 unsigned NumUndefsLO = 0;
6472 unsigned NumUndefsHI = 0;
6473 unsigned Half = NumElts/2;
6475 // Count the number of UNDEF operands in the build_vector in input.
6476 for (unsigned i = 0, e = Half; i != e; ++i)
6477 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6480 for (unsigned i = Half, e = NumElts; i != e; ++i)
6481 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6484 // Early exit if this is either a build_vector of all UNDEFs or all the
6485 // operands but one are UNDEF.
6486 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6489 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6490 // Try to match an SSE3 float HADD/HSUB.
6491 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6492 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6494 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6495 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6496 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6497 // Try to match an SSSE3 integer HADD/HSUB.
6498 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6499 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6501 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6502 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6505 if (!Subtarget->hasAVX())
6508 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6509 // Try to match an AVX horizontal add/sub of packed single/double
6510 // precision floating point values from 256-bit vectors.
6511 SDValue InVec2, InVec3;
6512 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6513 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6514 ((InVec0.getOpcode() == ISD::UNDEF ||
6515 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6516 ((InVec1.getOpcode() == ISD::UNDEF ||
6517 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6518 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6520 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6521 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6522 ((InVec0.getOpcode() == ISD::UNDEF ||
6523 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6524 ((InVec1.getOpcode() == ISD::UNDEF ||
6525 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6526 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6527 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6528 // Try to match an AVX2 horizontal add/sub of signed integers.
6529 SDValue InVec2, InVec3;
6531 bool CanFold = true;
6533 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6534 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6535 ((InVec0.getOpcode() == ISD::UNDEF ||
6536 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6537 ((InVec1.getOpcode() == ISD::UNDEF ||
6538 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6539 X86Opcode = X86ISD::HADD;
6540 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6541 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6542 ((InVec0.getOpcode() == ISD::UNDEF ||
6543 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6544 ((InVec1.getOpcode() == ISD::UNDEF ||
6545 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6546 X86Opcode = X86ISD::HSUB;
6551 // Fold this build_vector into a single horizontal add/sub.
6552 // Do this only if the target has AVX2.
6553 if (Subtarget->hasAVX2())
6554 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6556 // Do not try to expand this build_vector into a pair of horizontal
6557 // add/sub if we can emit a pair of scalar add/sub.
6558 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6561 // Convert this build_vector into a pair of horizontal binop followed by
6563 bool isUndefLO = NumUndefsLO == Half;
6564 bool isUndefHI = NumUndefsHI == Half;
6565 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6566 isUndefLO, isUndefHI);
6570 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6571 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6573 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6574 X86Opcode = X86ISD::HADD;
6575 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6576 X86Opcode = X86ISD::HSUB;
6577 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6578 X86Opcode = X86ISD::FHADD;
6579 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6580 X86Opcode = X86ISD::FHSUB;
6584 // Don't try to expand this build_vector into a pair of horizontal add/sub
6585 // if we can simply emit a pair of scalar add/sub.
6586 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6589 // Convert this build_vector into two horizontal add/sub followed by
6591 bool isUndefLO = NumUndefsLO == Half;
6592 bool isUndefHI = NumUndefsHI == Half;
6593 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6594 isUndefLO, isUndefHI);
6601 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6604 MVT VT = Op.getSimpleValueType();
6605 MVT ExtVT = VT.getVectorElementType();
6606 unsigned NumElems = Op.getNumOperands();
6608 // Generate vectors for predicate vectors.
6609 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6610 return LowerBUILD_VECTORvXi1(Op, DAG);
6612 // Vectors containing all zeros can be matched by pxor and xorps later
6613 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6614 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6615 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6616 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6619 return getZeroVector(VT, Subtarget, DAG, dl);
6622 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6623 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6624 // vpcmpeqd on 256-bit vectors.
6625 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6626 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6629 if (!VT.is512BitVector())
6630 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6633 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6634 if (Broadcast.getNode())
6637 unsigned EVTBits = ExtVT.getSizeInBits();
6639 unsigned NumZero = 0;
6640 unsigned NumNonZero = 0;
6641 unsigned NonZeros = 0;
6642 bool IsAllConstants = true;
6643 SmallSet<SDValue, 8> Values;
6644 for (unsigned i = 0; i < NumElems; ++i) {
6645 SDValue Elt = Op.getOperand(i);
6646 if (Elt.getOpcode() == ISD::UNDEF)
6649 if (Elt.getOpcode() != ISD::Constant &&
6650 Elt.getOpcode() != ISD::ConstantFP)
6651 IsAllConstants = false;
6652 if (X86::isZeroNode(Elt))
6655 NonZeros |= (1 << i);
6660 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6661 if (NumNonZero == 0)
6662 return DAG.getUNDEF(VT);
6664 // Special case for single non-zero, non-undef, element.
6665 if (NumNonZero == 1) {
6666 unsigned Idx = countTrailingZeros(NonZeros);
6667 SDValue Item = Op.getOperand(Idx);
6669 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6670 // the value are obviously zero, truncate the value to i32 and do the
6671 // insertion that way. Only do this if the value is non-constant or if the
6672 // value is a constant being inserted into element 0. It is cheaper to do
6673 // a constant pool load than it is to do a movd + shuffle.
6674 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6675 (!IsAllConstants || Idx == 0)) {
6676 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6678 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6679 EVT VecVT = MVT::v4i32;
6680 unsigned VecElts = 4;
6682 // Truncate the value (which may itself be a constant) to i32, and
6683 // convert it to a vector with movd (S2V+shuffle to zero extend).
6684 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6685 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6686 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6688 // Now we have our 32-bit value zero extended in the low element of
6689 // a vector. If Idx != 0, swizzle it into place.
6691 SmallVector<int, 4> Mask;
6692 Mask.push_back(Idx);
6693 for (unsigned i = 1; i != VecElts; ++i)
6695 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6698 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6702 // If we have a constant or non-constant insertion into the low element of
6703 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6704 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6705 // depending on what the source datatype is.
6708 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6710 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6711 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6712 if (VT.is256BitVector() || VT.is512BitVector()) {
6713 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6714 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6715 Item, DAG.getIntPtrConstant(0));
6717 assert(VT.is128BitVector() && "Expected an SSE value type!");
6718 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6719 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6720 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6723 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6724 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6725 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6726 if (VT.is256BitVector()) {
6727 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6728 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6730 assert(VT.is128BitVector() && "Expected an SSE value type!");
6731 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6733 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6737 // Is it a vector logical left shift?
6738 if (NumElems == 2 && Idx == 1 &&
6739 X86::isZeroNode(Op.getOperand(0)) &&
6740 !X86::isZeroNode(Op.getOperand(1))) {
6741 unsigned NumBits = VT.getSizeInBits();
6742 return getVShift(true, VT,
6743 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6744 VT, Op.getOperand(1)),
6745 NumBits/2, DAG, *this, dl);
6748 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6751 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6752 // is a non-constant being inserted into an element other than the low one,
6753 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6754 // movd/movss) to move this into the low element, then shuffle it into
6756 if (EVTBits == 32) {
6757 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6759 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6760 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6761 SmallVector<int, 8> MaskVec;
6762 for (unsigned i = 0; i != NumElems; ++i)
6763 MaskVec.push_back(i == Idx ? 0 : 1);
6764 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6768 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6769 if (Values.size() == 1) {
6770 if (EVTBits == 32) {
6771 // Instead of a shuffle like this:
6772 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6773 // Check if it's possible to issue this instead.
6774 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6775 unsigned Idx = countTrailingZeros(NonZeros);
6776 SDValue Item = Op.getOperand(Idx);
6777 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6778 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6783 // A vector full of immediates; various special cases are already
6784 // handled, so this is best done with a single constant-pool load.
6788 // For AVX-length vectors, build the individual 128-bit pieces and use
6789 // shuffles to put them in place.
6790 if (VT.is256BitVector() || VT.is512BitVector()) {
6791 SmallVector<SDValue, 64> V;
6792 for (unsigned i = 0; i != NumElems; ++i)
6793 V.push_back(Op.getOperand(i));
6795 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6797 // Build both the lower and upper subvector.
6798 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6799 makeArrayRef(&V[0], NumElems/2));
6800 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6801 makeArrayRef(&V[NumElems / 2], NumElems/2));
6803 // Recreate the wider vector with the lower and upper part.
6804 if (VT.is256BitVector())
6805 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6806 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6809 // Let legalizer expand 2-wide build_vectors.
6810 if (EVTBits == 64) {
6811 if (NumNonZero == 1) {
6812 // One half is zero or undef.
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6815 Op.getOperand(Idx));
6816 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6821 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6822 if (EVTBits == 8 && NumElems == 16) {
6823 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6825 if (V.getNode()) return V;
6828 if (EVTBits == 16 && NumElems == 8) {
6829 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6831 if (V.getNode()) return V;
6834 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6835 if (EVTBits == 32 && NumElems == 4) {
6836 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6837 NumZero, DAG, Subtarget, *this);
6842 // If element VT is == 32 bits, turn it into a number of shuffles.
6843 SmallVector<SDValue, 8> V(NumElems);
6844 if (NumElems == 4 && NumZero > 0) {
6845 for (unsigned i = 0; i < 4; ++i) {
6846 bool isZero = !(NonZeros & (1 << i));
6848 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6850 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6853 for (unsigned i = 0; i < 2; ++i) {
6854 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6857 V[i] = V[i*2]; // Must be a zero vector.
6860 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6863 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6866 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6871 bool Reverse1 = (NonZeros & 0x3) == 2;
6872 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6876 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6877 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6879 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6882 if (Values.size() > 1 && VT.is128BitVector()) {
6883 // Check for a build vector of consecutive loads.
6884 for (unsigned i = 0; i < NumElems; ++i)
6885 V[i] = Op.getOperand(i);
6887 // Check for elements which are consecutive loads.
6888 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6892 // Check for a build vector from mostly shuffle plus few inserting.
6893 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6897 // For SSE 4.1, use insertps to put the high elements into the low element.
6898 if (getSubtarget()->hasSSE41()) {
6900 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6901 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6903 Result = DAG.getUNDEF(VT);
6905 for (unsigned i = 1; i < NumElems; ++i) {
6906 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6907 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6908 Op.getOperand(i), DAG.getIntPtrConstant(i));
6913 // Otherwise, expand into a number of unpckl*, start by extending each of
6914 // our (non-undef) elements to the full vector width with the element in the
6915 // bottom slot of the vector (which generates no code for SSE).
6916 for (unsigned i = 0; i < NumElems; ++i) {
6917 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6918 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6920 V[i] = DAG.getUNDEF(VT);
6923 // Next, we iteratively mix elements, e.g. for v4f32:
6924 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6925 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6926 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6927 unsigned EltStride = NumElems >> 1;
6928 while (EltStride != 0) {
6929 for (unsigned i = 0; i < EltStride; ++i) {
6930 // If V[i+EltStride] is undef and this is the first round of mixing,
6931 // then it is safe to just drop this shuffle: V[i] is already in the
6932 // right place, the one element (since it's the first round) being
6933 // inserted as undef can be dropped. This isn't safe for successive
6934 // rounds because they will permute elements within both vectors.
6935 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6936 EltStride == NumElems/2)
6939 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6948 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6949 // to create 256-bit vectors from two other 128-bit ones.
6950 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6952 MVT ResVT = Op.getSimpleValueType();
6954 assert((ResVT.is256BitVector() ||
6955 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6957 SDValue V1 = Op.getOperand(0);
6958 SDValue V2 = Op.getOperand(1);
6959 unsigned NumElems = ResVT.getVectorNumElements();
6960 if(ResVT.is256BitVector())
6961 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6963 if (Op.getNumOperands() == 4) {
6964 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6965 ResVT.getVectorNumElements()/2);
6966 SDValue V3 = Op.getOperand(2);
6967 SDValue V4 = Op.getOperand(3);
6968 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6969 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6971 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6974 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6975 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6976 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6977 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6978 Op.getNumOperands() == 4)));
6980 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6981 // from two other 128-bit ones.
6983 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6984 return LowerAVXCONCAT_VECTORS(Op, DAG);
6988 //===----------------------------------------------------------------------===//
6989 // Vector shuffle lowering
6991 // This is an experimental code path for lowering vector shuffles on x86. It is
6992 // designed to handle arbitrary vector shuffles and blends, gracefully
6993 // degrading performance as necessary. It works hard to recognize idiomatic
6994 // shuffles and lower them to optimal instruction patterns without leaving
6995 // a framework that allows reasonably efficient handling of all vector shuffle
6997 //===----------------------------------------------------------------------===//
6999 /// \brief Tiny helper function to identify a no-op mask.
7001 /// This is a somewhat boring predicate function. It checks whether the mask
7002 /// array input, which is assumed to be a single-input shuffle mask of the kind
7003 /// used by the X86 shuffle instructions (not a fully general
7004 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7005 /// in-place shuffle are 'no-op's.
7006 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7007 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7008 if (Mask[i] != -1 && Mask[i] != i)
7013 /// \brief Helper function to classify a mask as a single-input mask.
7015 /// This isn't a generic single-input test because in the vector shuffle
7016 /// lowering we canonicalize single inputs to be the first input operand. This
7017 /// means we can more quickly test for a single input by only checking whether
7018 /// an input from the second operand exists. We also assume that the size of
7019 /// mask corresponds to the size of the input vectors which isn't true in the
7020 /// fully general case.
7021 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7023 if (M >= (int)Mask.size())
7028 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7030 /// This helper function produces an 8-bit shuffle immediate corresponding to
7031 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7032 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7035 /// NB: We rely heavily on "undef" masks preserving the input lane.
7036 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7037 SelectionDAG &DAG) {
7038 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7039 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7040 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7041 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7042 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7045 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7046 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7047 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7048 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7049 return DAG.getConstant(Imm, MVT::i8);
7052 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7054 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7055 /// support for floating point shuffles but not integer shuffles. These
7056 /// instructions will incur a domain crossing penalty on some chips though so
7057 /// it is better to avoid lowering through this for integer vectors where
7059 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7060 const X86Subtarget *Subtarget,
7061 SelectionDAG &DAG) {
7063 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7064 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7065 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7066 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7067 ArrayRef<int> Mask = SVOp->getMask();
7068 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7070 if (isSingleInputShuffleMask(Mask)) {
7071 // Straight shuffle of a single input vector. Simulate this by using the
7072 // single input as both of the "inputs" to this instruction..
7073 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7074 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7075 DAG.getConstant(SHUFPDMask, MVT::i8));
7077 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7078 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7080 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7081 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7082 DAG.getConstant(SHUFPDMask, MVT::i8));
7085 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7087 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7088 /// the integer unit to minimize domain crossing penalties. However, for blends
7089 /// it falls back to the floating point shuffle operation with appropriate bit
7091 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7092 const X86Subtarget *Subtarget,
7093 SelectionDAG &DAG) {
7095 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7096 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7097 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7098 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7099 ArrayRef<int> Mask = SVOp->getMask();
7100 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7102 if (isSingleInputShuffleMask(Mask)) {
7103 // Straight shuffle of a single input vector. For everything from SSE2
7104 // onward this has a single fast instruction with no scary immediates.
7105 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7106 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7107 int WidenedMask[4] = {
7108 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7109 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7111 ISD::BITCAST, DL, MVT::v2i64,
7112 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7113 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7116 // We implement this with SHUFPD which is pretty lame because it will likely
7117 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7118 // However, all the alternatives are still more cycles and newer chips don't
7119 // have this problem. It would be really nice if x86 had better shuffles here.
7120 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7121 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7122 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7123 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7126 /// \brief Lower 4-lane 32-bit floating point shuffles.
7128 /// Uses instructions exclusively from the floating point unit to minimize
7129 /// domain crossing penalties, as these are sufficient to implement all v4f32
7131 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7132 const X86Subtarget *Subtarget,
7133 SelectionDAG &DAG) {
7135 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7136 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7137 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7138 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7139 ArrayRef<int> Mask = SVOp->getMask();
7140 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7142 SDValue LowV = V1, HighV = V2;
7143 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7146 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7148 if (NumV2Elements == 0)
7149 // Straight shuffle of a single input vector. We pass the input vector to
7150 // both operands to simulate this with a SHUFPS.
7151 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7152 getV4X86ShuffleImm8ForMask(Mask, DAG));
7154 if (NumV2Elements == 1) {
7156 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7158 // Compute the index adjacent to V2Index and in the same half by toggling
7160 int V2AdjIndex = V2Index ^ 1;
7162 if (Mask[V2AdjIndex] == -1) {
7163 // Handles all the cases where we have a single V2 element and an undef.
7164 // This will only ever happen in the high lanes because we commute the
7165 // vector otherwise.
7167 std::swap(LowV, HighV);
7168 NewMask[V2Index] -= 4;
7170 // Handle the case where the V2 element ends up adjacent to a V1 element.
7171 // To make this work, blend them together as the first step.
7172 int V1Index = V2AdjIndex;
7173 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7174 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7175 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7177 // Now proceed to reconstruct the final blend as we have the necessary
7178 // high or low half formed.
7185 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7186 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7188 } else if (NumV2Elements == 2) {
7189 if (Mask[0] < 4 && Mask[1] < 4) {
7190 // Handle the easy case where we have V1 in the low lanes and V2 in the
7191 // high lanes. We never see this reversed because we sort the shuffle.
7195 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7196 // trying to place elements directly, just blend them and set up the final
7197 // shuffle to place them.
7199 // The first two blend mask elements are for V1, the second two are for
7201 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7202 Mask[2] < 4 ? Mask[2] : Mask[3],
7203 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7204 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7205 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7206 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7208 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7211 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7212 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7213 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7214 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7217 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7218 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7221 /// \brief Lower 4-lane i32 vector shuffles.
7223 /// We try to handle these with integer-domain shuffles where we can, but for
7224 /// blends we use the floating point domain blend instructions.
7225 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7226 const X86Subtarget *Subtarget,
7227 SelectionDAG &DAG) {
7229 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7230 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7231 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7232 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7233 ArrayRef<int> Mask = SVOp->getMask();
7234 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7236 if (isSingleInputShuffleMask(Mask))
7237 // Straight shuffle of a single input vector. For everything from SSE2
7238 // onward this has a single fast instruction with no scary immediates.
7239 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7240 getV4X86ShuffleImm8ForMask(Mask, DAG));
7242 // We implement this with SHUFPS because it can blend from two vectors.
7243 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7244 // up the inputs, bypassing domain shift penalties that we would encur if we
7245 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7247 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7248 DAG.getVectorShuffle(
7250 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7251 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7254 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7255 /// shuffle lowering, and the most complex part.
7257 /// The lowering strategy is to try to form pairs of input lanes which are
7258 /// targeted at the same half of the final vector, and then use a dword shuffle
7259 /// to place them onto the right half, and finally unpack the paired lanes into
7260 /// their final position.
7262 /// The exact breakdown of how to form these dword pairs and align them on the
7263 /// correct sides is really tricky. See the comments within the function for
7264 /// more of the details.
7265 static SDValue lowerV8I16SingleInputVectorShuffle(
7266 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7267 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7268 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7269 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7270 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7272 SmallVector<int, 4> LoInputs;
7273 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7274 [](int M) { return M >= 0; });
7275 std::sort(LoInputs.begin(), LoInputs.end());
7276 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7277 SmallVector<int, 4> HiInputs;
7278 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7279 [](int M) { return M >= 0; });
7280 std::sort(HiInputs.begin(), HiInputs.end());
7281 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7283 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7284 int NumHToL = LoInputs.size() - NumLToL;
7286 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7287 int NumHToH = HiInputs.size() - NumLToH;
7288 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7289 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7290 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7291 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7293 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7294 // such inputs we can swap two of the dwords across the half mark and end up
7295 // with <=2 inputs to each half in each half. Once there, we can fall through
7296 // to the generic code below. For example:
7298 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7299 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7301 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7303 auto balanceSides = [&](ArrayRef<int> ThreeInputs, int OneInput,
7304 int ThreeInputHalfSum, int OneInputHalfOffset) {
7305 // Compute the index of dword with only one word among the three inputs in
7306 // a half by taking the sum of the half with three inputs and subtracting
7307 // the sum of the actual three inputs. The difference is the remaining
7309 int DWordA = (ThreeInputHalfSum -
7310 std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
7312 int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
7314 int PSHUFDMask[] = {0, 1, 2, 3};
7315 PSHUFDMask[DWordA] = DWordB;
7316 PSHUFDMask[DWordB] = DWordA;
7317 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7318 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7319 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7320 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7322 // Adjust the mask to match the new locations of A and B.
7324 if (M != -1 && M/2 == DWordA)
7325 M = 2 * DWordB + M % 2;
7326 else if (M != -1 && M/2 == DWordB)
7327 M = 2 * DWordA + M % 2;
7329 // Recurse back into this routine to re-compute state now that this isn't
7330 // a 3 and 1 problem.
7331 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7334 if (NumLToL == 3 && NumHToL == 1)
7335 return balanceSides(LToLInputs, HToLInputs[0], 0 + 1 + 2 + 3, 4);
7336 else if (NumLToL == 1 && NumHToL == 3)
7337 return balanceSides(HToLInputs, LToLInputs[0], 4 + 5 + 6 + 7, 0);
7338 else if (NumLToH == 1 && NumHToH == 3)
7339 return balanceSides(HToHInputs, LToHInputs[0], 4 + 5 + 6 + 7, 0);
7340 else if (NumLToH == 3 && NumHToH == 1)
7341 return balanceSides(LToHInputs, HToHInputs[0], 0 + 1 + 2 + 3, 4);
7343 // At this point there are at most two inputs to the low and high halves from
7344 // each half. That means the inputs can always be grouped into dwords and
7345 // those dwords can then be moved to the correct half with a dword shuffle.
7346 // We use at most one low and one high word shuffle to collect these paired
7347 // inputs into dwords, and finally a dword shuffle to place them.
7348 int PSHUFLMask[4] = {-1, -1, -1, -1};
7349 int PSHUFHMask[4] = {-1, -1, -1, -1};
7350 int PSHUFDMask[4] = {-1, -1, -1, -1};
7352 // First fix the masks for all the inputs that are staying in their
7353 // original halves. This will then dictate the targets of the cross-half
7355 auto fixInPlaceInputs = [&PSHUFDMask](
7356 ArrayRef<int> InPlaceInputs, MutableArrayRef<int> SourceHalfMask,
7357 MutableArrayRef<int> HalfMask, int HalfOffset) {
7358 if (InPlaceInputs.empty())
7360 if (InPlaceInputs.size() == 1) {
7361 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7362 InPlaceInputs[0] - HalfOffset;
7363 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7367 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7368 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7369 InPlaceInputs[0] - HalfOffset;
7370 // Put the second input next to the first so that they are packed into
7371 // a dword. We find the adjacent index by toggling the low bit.
7372 int AdjIndex = InPlaceInputs[0] ^ 1;
7373 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7374 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7375 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7377 if (!HToLInputs.empty())
7378 fixInPlaceInputs(LToLInputs, PSHUFLMask, LoMask, 0);
7379 if (!LToHInputs.empty())
7380 fixInPlaceInputs(HToHInputs, PSHUFHMask, HiMask, 4);
7382 // Now gather the cross-half inputs and place them into a free dword of
7383 // their target half.
7384 // FIXME: This operation could almost certainly be simplified dramatically to
7385 // look more like the 3-1 fixing operation.
7386 auto moveInputsToRightHalf = [&PSHUFDMask](
7387 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7388 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7389 int SourceOffset, int DestOffset) {
7390 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7391 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7393 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7395 int LowWord = Word & ~1;
7396 int HighWord = Word | 1;
7397 return isWordClobbered(SourceHalfMask, LowWord) ||
7398 isWordClobbered(SourceHalfMask, HighWord);
7401 if (IncomingInputs.empty())
7404 if (ExistingInputs.empty()) {
7405 // Map any dwords with inputs from them into the right half.
7406 for (int Input : IncomingInputs) {
7407 // If the source half mask maps over the inputs, turn those into
7408 // swaps and use the swapped lane.
7409 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7410 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7411 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7412 Input - SourceOffset;
7413 // We have to swap the uses in our half mask in one sweep.
7414 for (int &M : HalfMask)
7415 if (M == SourceHalfMask[Input - SourceOffset])
7417 else if (M == Input)
7418 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7420 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7421 Input - SourceOffset &&
7422 "Previous placement doesn't match!");
7424 // Note that this correctly re-maps both when we do a swap and when
7425 // we observe the other side of the swap above. We rely on that to
7426 // avoid swapping the members of the input list directly.
7427 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7430 // Map the input's dword into the correct half.
7431 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7432 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7434 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7436 "Previous placement doesn't match!");
7439 // And just directly shift any other-half mask elements to be same-half
7440 // as we will have mirrored the dword containing the element into the
7441 // same position within that half.
7442 for (int &M : HalfMask)
7443 if (M >= SourceOffset && M < SourceOffset + 4) {
7444 M = M - SourceOffset + DestOffset;
7445 assert(M >= 0 && "This should never wrap below zero!");
7450 // Ensure we have the input in a viable dword of its current half. This
7451 // is particularly tricky because the original position may be clobbered
7452 // by inputs being moved and *staying* in that half.
7453 if (IncomingInputs.size() == 1) {
7454 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7455 int InputFixed = std::find(std::begin(SourceHalfMask),
7456 std::end(SourceHalfMask), -1) -
7457 std::begin(SourceHalfMask) + SourceOffset;
7458 SourceHalfMask[InputFixed - SourceOffset] =
7459 IncomingInputs[0] - SourceOffset;
7460 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7462 IncomingInputs[0] = InputFixed;
7464 } else if (IncomingInputs.size() == 2) {
7465 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7466 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7467 int SourceDWordBase = !isDWordClobbered(SourceHalfMask, 0) ? 0 : 2;
7468 assert(!isDWordClobbered(SourceHalfMask, SourceDWordBase) &&
7469 "Not all dwords can be clobbered!");
7470 SourceHalfMask[SourceDWordBase] = IncomingInputs[0] - SourceOffset;
7471 SourceHalfMask[SourceDWordBase + 1] = IncomingInputs[1] - SourceOffset;
7472 for (int &M : HalfMask)
7473 if (M == IncomingInputs[0])
7474 M = SourceDWordBase + SourceOffset;
7475 else if (M == IncomingInputs[1])
7476 M = SourceDWordBase + 1 + SourceOffset;
7477 IncomingInputs[0] = SourceDWordBase + SourceOffset;
7478 IncomingInputs[1] = SourceDWordBase + 1 + SourceOffset;
7481 llvm_unreachable("Unhandled input size!");
7484 // Now hoist the DWord down to the right half.
7485 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7486 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7487 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7488 for (int Input : IncomingInputs)
7489 std::replace(HalfMask.begin(), HalfMask.end(), Input,
7490 FreeDWord * 2 + Input % 2);
7492 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask,
7493 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7494 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask,
7495 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7497 // Now enact all the shuffles we've computed to move the inputs into their
7499 if (!isNoopShuffleMask(PSHUFLMask))
7500 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7501 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7502 if (!isNoopShuffleMask(PSHUFHMask))
7503 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7504 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7505 if (!isNoopShuffleMask(PSHUFDMask))
7506 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7507 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7508 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7509 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7511 // At this point, each half should contain all its inputs, and we can then
7512 // just shuffle them into their final position.
7513 assert(std::count_if(LoMask.begin(), LoMask.end(),
7514 [](int M) { return M >= 4; }) == 0 &&
7515 "Failed to lift all the high half inputs to the low mask!");
7516 assert(std::count_if(HiMask.begin(), HiMask.end(),
7517 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7518 "Failed to lift all the low half inputs to the high mask!");
7520 // Do a half shuffle for the low mask.
7521 if (!isNoopShuffleMask(LoMask))
7522 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7523 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7525 // Do a half shuffle with the high mask after shifting its values down.
7526 for (int &M : HiMask)
7529 if (!isNoopShuffleMask(HiMask))
7530 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7531 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7536 /// \brief Detect whether the mask pattern should be lowered through
7539 /// This essentially tests whether viewing the mask as an interleaving of two
7540 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7541 /// lowering it through interleaving is a significantly better strategy.
7542 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7543 int NumEvenInputs[2] = {0, 0};
7544 int NumOddInputs[2] = {0, 0};
7545 int NumLoInputs[2] = {0, 0};
7546 int NumHiInputs[2] = {0, 0};
7547 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7551 int InputIdx = Mask[i] >= Size;
7554 ++NumLoInputs[InputIdx];
7556 ++NumHiInputs[InputIdx];
7559 ++NumEvenInputs[InputIdx];
7561 ++NumOddInputs[InputIdx];
7564 // The minimum number of cross-input results for both the interleaved and
7565 // split cases. If interleaving results in fewer cross-input results, return
7567 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7568 NumEvenInputs[0] + NumOddInputs[1]);
7569 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7570 NumLoInputs[0] + NumHiInputs[1]);
7571 return InterleavedCrosses < SplitCrosses;
7574 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7576 /// This strategy only works when the inputs from each vector fit into a single
7577 /// half of that vector, and generally there are not so many inputs as to leave
7578 /// the in-place shuffles required highly constrained (and thus expensive). It
7579 /// shifts all the inputs into a single side of both input vectors and then
7580 /// uses an unpack to interleave these inputs in a single vector. At that
7581 /// point, we will fall back on the generic single input shuffle lowering.
7582 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7584 MutableArrayRef<int> Mask,
7585 const X86Subtarget *Subtarget,
7586 SelectionDAG &DAG) {
7587 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7588 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7589 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7590 for (int i = 0; i < 8; ++i)
7591 if (Mask[i] >= 0 && Mask[i] < 4)
7592 LoV1Inputs.push_back(i);
7593 else if (Mask[i] >= 4 && Mask[i] < 8)
7594 HiV1Inputs.push_back(i);
7595 else if (Mask[i] >= 8 && Mask[i] < 12)
7596 LoV2Inputs.push_back(i);
7597 else if (Mask[i] >= 12)
7598 HiV2Inputs.push_back(i);
7600 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7601 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7604 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7605 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7606 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7608 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7609 HiV1Inputs.size() + HiV2Inputs.size();
7611 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7612 ArrayRef<int> HiInputs, bool MoveToLo,
7614 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7615 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7616 if (BadInputs.empty())
7619 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7620 int MoveOffset = MoveToLo ? 0 : 4;
7622 if (GoodInputs.empty()) {
7623 for (int BadInput : BadInputs) {
7624 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7625 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7628 if (GoodInputs.size() == 2) {
7629 // If the low inputs are spread across two dwords, pack them into
7631 MoveMask[Mask[GoodInputs[0]] % 2 + MoveOffset] =
7632 Mask[GoodInputs[0]] - MaskOffset;
7633 MoveMask[Mask[GoodInputs[1]] % 2 + MoveOffset] =
7634 Mask[GoodInputs[1]] - MaskOffset;
7635 Mask[GoodInputs[0]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7636 Mask[GoodInputs[1]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7638 // Otherwise pin the low inputs.
7639 for (int GoodInput : GoodInputs)
7640 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7644 std::find(std::begin(MoveMask) + MoveOffset, std::end(MoveMask), -1) -
7645 std::begin(MoveMask);
7646 assert(MoveMaskIdx >= MoveOffset && "Established above");
7648 if (BadInputs.size() == 2) {
7649 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7650 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7651 MoveMask[MoveMaskIdx + Mask[BadInputs[0]] % 2] =
7652 Mask[BadInputs[0]] - MaskOffset;
7653 MoveMask[MoveMaskIdx + Mask[BadInputs[1]] % 2] =
7654 Mask[BadInputs[1]] - MaskOffset;
7655 Mask[BadInputs[0]] = MoveMaskIdx + Mask[BadInputs[0]] % 2 + MaskOffset;
7656 Mask[BadInputs[1]] = MoveMaskIdx + Mask[BadInputs[1]] % 2 + MaskOffset;
7658 assert(BadInputs.size() == 1 && "All sizes handled");
7659 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7660 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7664 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7667 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7669 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7672 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7673 // cross-half traffic in the final shuffle.
7675 // Munge the mask to be a single-input mask after the unpack merges the
7679 M = 2 * (M % 4) + (M / 8);
7681 return DAG.getVectorShuffle(
7682 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7683 DL, MVT::v8i16, V1, V2),
7684 DAG.getUNDEF(MVT::v8i16), Mask);
7687 /// \brief Generic lowering of 8-lane i16 shuffles.
7689 /// This handles both single-input shuffles and combined shuffle/blends with
7690 /// two inputs. The single input shuffles are immediately delegated to
7691 /// a dedicated lowering routine.
7693 /// The blends are lowered in one of three fundamental ways. If there are few
7694 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7695 /// of the input is significantly cheaper when lowered as an interleaving of
7696 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7697 /// halves of the inputs separately (making them have relatively few inputs)
7698 /// and then concatenate them.
7699 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7700 const X86Subtarget *Subtarget,
7701 SelectionDAG &DAG) {
7703 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7704 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7705 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7707 ArrayRef<int> OrigMask = SVOp->getMask();
7708 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7709 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7710 MutableArrayRef<int> Mask(MaskStorage);
7712 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7714 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7715 auto isV2 = [](int M) { return M >= 8; };
7717 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7718 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7720 if (NumV2Inputs == 0)
7721 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7723 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7724 "to be V1-input shuffles.");
7726 if (NumV1Inputs + NumV2Inputs <= 4)
7727 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7729 // Check whether an interleaving lowering is likely to be more efficient.
7730 // This isn't perfect but it is a strong heuristic that tends to work well on
7731 // the kinds of shuffles that show up in practice.
7733 // FIXME: Handle 1x, 2x, and 4x interleaving.
7734 if (shouldLowerAsInterleaving(Mask)) {
7735 // FIXME: Figure out whether we should pack these into the low or high
7738 int EMask[8], OMask[8];
7739 for (int i = 0; i < 4; ++i) {
7740 EMask[i] = Mask[2*i];
7741 OMask[i] = Mask[2*i + 1];
7746 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7747 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7749 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7752 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7753 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7755 for (int i = 0; i < 4; ++i) {
7756 LoBlendMask[i] = Mask[i];
7757 HiBlendMask[i] = Mask[i + 4];
7760 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7761 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7762 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7763 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7765 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7766 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7769 /// \brief Check whether a compaction lowering can be done by dropping even
7770 /// elements and compute how many times even elements must be dropped.
7772 /// This handles shuffles which take every Nth element where N is a power of
7773 /// two. Example shuffle masks:
7775 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
7776 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
7777 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
7778 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
7779 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
7780 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
7782 /// Any of these lanes can of course be undef.
7784 /// This routine only supports N <= 3.
7785 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
7788 /// \returns N above, or the number of times even elements must be dropped if
7789 /// there is such a number. Otherwise returns zero.
7790 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
7791 // Figure out whether we're looping over two inputs or just one.
7792 bool IsSingleInput = isSingleInputShuffleMask(Mask);
7794 // The modulus for the shuffle vector entries is based on whether this is
7795 // a single input or not.
7796 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
7797 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
7798 "We should only be called with masks with a power-of-2 size!");
7800 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
7802 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
7803 // and 2^3 simultaneously. This is because we may have ambiguity with
7804 // partially undef inputs.
7805 bool ViableForN[3] = {true, true, true};
7807 for (int i = 0, e = Mask.size(); i < e; ++i) {
7808 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
7813 bool IsAnyViable = false;
7814 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
7815 if (ViableForN[j]) {
7818 // The shuffle mask must be equal to (i * 2^N) % M.
7819 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
7822 ViableForN[j] = false;
7824 // Early exit if we exhaust the possible powers of two.
7829 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
7833 // Return 0 as there is no viable power of two.
7837 /// \brief Generic lowering of v16i8 shuffles.
7839 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7840 /// detect any complexity reducing interleaving. If that doesn't help, it uses
7841 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
7842 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
7844 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7845 const X86Subtarget *Subtarget,
7846 SelectionDAG &DAG) {
7848 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7849 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7850 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7851 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7852 ArrayRef<int> OrigMask = SVOp->getMask();
7853 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
7854 int MaskStorage[16] = {
7855 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7856 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
7857 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
7858 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
7859 MutableArrayRef<int> Mask(MaskStorage);
7860 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
7861 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
7863 // For single-input shuffles, there are some nicer lowering tricks we can use.
7864 if (isSingleInputShuffleMask(Mask)) {
7865 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
7866 // Notably, this handles splat and partial-splat shuffles more efficiently.
7867 // However, it only makes sense if the pre-duplication shuffle simplifies
7868 // things significantly. Currently, this means we need to be able to
7869 // express the pre-duplication shuffle as an i16 shuffle.
7871 // FIXME: We should check for other patterns which can be widened into an
7872 // i16 shuffle as well.
7873 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
7874 for (int i = 0; i < 16; i += 2) {
7875 if (Mask[i] != Mask[i + 1])
7880 auto tryToWidenViaDuplication = [&]() -> SDValue {
7881 if (!canWidenViaDuplication(Mask))
7883 SmallVector<int, 4> LoInputs;
7884 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
7885 [](int M) { return M >= 0 && M < 8; });
7886 std::sort(LoInputs.begin(), LoInputs.end());
7887 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
7889 SmallVector<int, 4> HiInputs;
7890 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
7891 [](int M) { return M >= 8; });
7892 std::sort(HiInputs.begin(), HiInputs.end());
7893 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
7896 bool TargetLo = LoInputs.size() >= HiInputs.size();
7897 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
7898 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
7900 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7901 SmallDenseMap<int, int, 8> LaneMap;
7902 for (int I : InPlaceInputs) {
7903 PreDupI16Shuffle[I/2] = I/2;
7906 int j = TargetLo ? 0 : 4, je = j + 4;
7907 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
7908 // Check if j is already a shuffle of this input. This happens when
7909 // there are two adjacent bytes after we move the low one.
7910 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
7911 // If we haven't yet mapped the input, search for a slot into which
7913 while (j < je && PreDupI16Shuffle[j] != -1)
7917 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
7920 // Map this input with the i16 shuffle.
7921 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
7924 // Update the lane map based on the mapping we ended up with.
7925 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
7928 ISD::BITCAST, DL, MVT::v16i8,
7929 DAG.getVectorShuffle(MVT::v8i16, DL,
7930 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7931 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
7933 // Unpack the bytes to form the i16s that will be shuffled into place.
7934 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7935 MVT::v16i8, V1, V1);
7937 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7938 for (int i = 0; i < 16; i += 2) {
7940 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
7941 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
7944 ISD::BITCAST, DL, MVT::v16i8,
7945 DAG.getVectorShuffle(MVT::v8i16, DL,
7946 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7947 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
7949 if (SDValue V = tryToWidenViaDuplication())
7953 // Check whether an interleaving lowering is likely to be more efficient.
7954 // This isn't perfect but it is a strong heuristic that tends to work well on
7955 // the kinds of shuffles that show up in practice.
7957 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
7958 if (shouldLowerAsInterleaving(Mask)) {
7959 // FIXME: Figure out whether we should pack these into the low or high
7962 int EMask[16], OMask[16];
7963 for (int i = 0; i < 8; ++i) {
7964 EMask[i] = Mask[2*i];
7965 OMask[i] = Mask[2*i + 1];
7970 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
7971 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
7973 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
7976 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
7977 // with PSHUFB. It is important to do this before we attempt to generate any
7978 // blends but after all of the single-input lowerings. If the single input
7979 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
7980 // want to preserve that and we can DAG combine any longer sequences into
7981 // a PSHUFB in the end. But once we start blending from multiple inputs,
7982 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
7983 // and there are *very* few patterns that would actually be faster than the
7984 // PSHUFB approach because of its ability to zero lanes.
7986 // FIXME: The only exceptions to the above are blends which are exact
7987 // interleavings with direct instructions supporting them. We currently don't
7988 // handle those well here.
7989 if (Subtarget->hasSSSE3()) {
7992 for (int i = 0; i < 16; ++i)
7993 if (Mask[i] == -1) {
7994 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
7996 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
7998 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8000 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8001 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8002 if (isSingleInputShuffleMask(Mask))
8003 return V1; // Single inputs are easy.
8005 // Otherwise, blend the two.
8006 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8007 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8008 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8011 // Check whether a compaction lowering can be done. This handles shuffles
8012 // which take every Nth element for some even N. See the helper function for
8015 // We special case these as they can be particularly efficiently handled with
8016 // the PACKUSB instruction on x86 and they show up in common patterns of
8017 // rearranging bytes to truncate wide elements.
8018 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8019 // NumEvenDrops is the power of two stride of the elements. Another way of
8020 // thinking about it is that we need to drop the even elements this many
8021 // times to get the original input.
8022 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8024 // First we need to zero all the dropped bytes.
8025 assert(NumEvenDrops <= 3 &&
8026 "No support for dropping even elements more than 3 times.");
8027 // We use the mask type to pick which bytes are preserved based on how many
8028 // elements are dropped.
8029 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8030 SDValue ByteClearMask =
8031 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8032 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8033 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8035 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8037 // Now pack things back together.
8038 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8039 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8040 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8041 for (int i = 1; i < NumEvenDrops; ++i) {
8042 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8043 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8049 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8050 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8051 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8052 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8054 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8055 MutableArrayRef<int> V1HalfBlendMask,
8056 MutableArrayRef<int> V2HalfBlendMask) {
8057 for (int i = 0; i < 8; ++i)
8058 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8059 V1HalfBlendMask[i] = HalfMask[i];
8061 } else if (HalfMask[i] >= 16) {
8062 V2HalfBlendMask[i] = HalfMask[i] - 16;
8063 HalfMask[i] = i + 8;
8066 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8067 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8069 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8071 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8072 MutableArrayRef<int> HiBlendMask) {
8074 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8075 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8077 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8078 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8079 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8080 [](int M) { return M >= 0 && M % 2 == 1; })) {
8081 // Use a mask to drop the high bytes.
8082 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8083 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8084 DAG.getConstant(0x00FF, MVT::v8i16));
8086 // This will be a single vector shuffle instead of a blend so nuke V2.
8087 V2 = DAG.getUNDEF(MVT::v8i16);
8089 // Squash the masks to point directly into V1.
8090 for (int &M : LoBlendMask)
8093 for (int &M : HiBlendMask)
8097 // Otherwise just unpack the low half of V into V1 and the high half into
8098 // V2 so that we can blend them as i16s.
8099 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8100 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8101 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8102 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8105 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8106 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8107 return std::make_pair(BlendedLo, BlendedHi);
8109 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8110 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8111 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8113 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8114 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8116 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8119 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8121 /// This routine breaks down the specific type of 128-bit shuffle and
8122 /// dispatches to the lowering routines accordingly.
8123 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8124 MVT VT, const X86Subtarget *Subtarget,
8125 SelectionDAG &DAG) {
8126 switch (VT.SimpleTy) {
8128 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8130 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8132 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8134 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8136 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8138 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8141 llvm_unreachable("Unimplemented!");
8145 /// \brief Tiny helper function to test whether adjacent masks are sequential.
8146 static bool areAdjacentMasksSequential(ArrayRef<int> Mask) {
8147 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8148 if (Mask[i] + 1 != Mask[i+1])
8154 /// \brief Top-level lowering for x86 vector shuffles.
8156 /// This handles decomposition, canonicalization, and lowering of all x86
8157 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8158 /// above in helper routines. The canonicalization attempts to widen shuffles
8159 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8160 /// s.t. only one of the two inputs needs to be tested, etc.
8161 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8162 SelectionDAG &DAG) {
8163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8164 ArrayRef<int> Mask = SVOp->getMask();
8165 SDValue V1 = Op.getOperand(0);
8166 SDValue V2 = Op.getOperand(1);
8167 MVT VT = Op.getSimpleValueType();
8168 int NumElements = VT.getVectorNumElements();
8171 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8173 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8174 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8175 if (V1IsUndef && V2IsUndef)
8176 return DAG.getUNDEF(VT);
8178 // When we create a shuffle node we put the UNDEF node to second operand,
8179 // but in some cases the first operand may be transformed to UNDEF.
8180 // In this case we should just commute the node.
8182 return DAG.getCommutedVectorShuffle(*SVOp);
8184 // Check for non-undef masks pointing at an undef vector and make the masks
8185 // undef as well. This makes it easier to match the shuffle based solely on
8189 if (M >= NumElements) {
8190 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8191 for (int &M : NewMask)
8192 if (M >= NumElements)
8194 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8197 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8198 // lanes but wider integers. We cap this to not form integers larger than i64
8199 // but it might be interesting to form i128 integers to handle flipping the
8200 // low and high halves of AVX 256-bit vectors.
8201 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8202 areAdjacentMasksSequential(Mask)) {
8203 SmallVector<int, 8> NewMask;
8204 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8205 NewMask.push_back(Mask[i] / 2);
8207 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8208 VT.getVectorNumElements() / 2);
8209 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8210 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8211 return DAG.getNode(ISD::BITCAST, dl, VT,
8212 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8215 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8216 for (int M : SVOp->getMask())
8219 else if (M < NumElements)
8224 // Commute the shuffle as needed such that more elements come from V1 than
8225 // V2. This allows us to match the shuffle pattern strictly on how many
8226 // elements come from V1 without handling the symmetric cases.
8227 if (NumV2Elements > NumV1Elements)
8228 return DAG.getCommutedVectorShuffle(*SVOp);
8230 // When the number of V1 and V2 elements are the same, try to minimize the
8231 // number of uses of V2 in the low half of the vector.
8232 if (NumV1Elements == NumV2Elements) {
8233 int LowV1Elements = 0, LowV2Elements = 0;
8234 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8235 if (M >= NumElements)
8239 if (LowV2Elements > LowV1Elements)
8240 return DAG.getCommutedVectorShuffle(*SVOp);
8243 // For each vector width, delegate to a specialized lowering routine.
8244 if (VT.getSizeInBits() == 128)
8245 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8247 llvm_unreachable("Unimplemented!");
8251 //===----------------------------------------------------------------------===//
8252 // Legacy vector shuffle lowering
8254 // This code is the legacy code handling vector shuffles until the above
8255 // replaces its functionality and performance.
8256 //===----------------------------------------------------------------------===//
8258 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8259 bool hasInt256, unsigned *MaskOut = nullptr) {
8260 MVT EltVT = VT.getVectorElementType();
8262 // There is no blend with immediate in AVX-512.
8263 if (VT.is512BitVector())
8266 if (!hasSSE41 || EltVT == MVT::i8)
8268 if (!hasInt256 && VT == MVT::v16i16)
8271 unsigned MaskValue = 0;
8272 unsigned NumElems = VT.getVectorNumElements();
8273 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8274 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8275 unsigned NumElemsInLane = NumElems / NumLanes;
8277 // Blend for v16i16 should be symetric for the both lanes.
8278 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8280 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8281 int EltIdx = MaskVals[i];
8283 if ((EltIdx < 0 || EltIdx == (int)i) &&
8284 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8287 if (((unsigned)EltIdx == (i + NumElems)) &&
8288 (SndLaneEltIdx < 0 ||
8289 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8290 MaskValue |= (1 << i);
8296 *MaskOut = MaskValue;
8300 // Try to lower a shuffle node into a simple blend instruction.
8301 // This function assumes isBlendMask returns true for this
8302 // SuffleVectorSDNode
8303 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8305 const X86Subtarget *Subtarget,
8306 SelectionDAG &DAG) {
8307 MVT VT = SVOp->getSimpleValueType(0);
8308 MVT EltVT = VT.getVectorElementType();
8309 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8310 Subtarget->hasInt256() && "Trying to lower a "
8311 "VECTOR_SHUFFLE to a Blend but "
8312 "with the wrong mask"));
8313 SDValue V1 = SVOp->getOperand(0);
8314 SDValue V2 = SVOp->getOperand(1);
8316 unsigned NumElems = VT.getVectorNumElements();
8318 // Convert i32 vectors to floating point if it is not AVX2.
8319 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8321 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8322 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8324 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8325 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8328 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8329 DAG.getConstant(MaskValue, MVT::i32));
8330 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8333 /// In vector type \p VT, return true if the element at index \p InputIdx
8334 /// falls on a different 128-bit lane than \p OutputIdx.
8335 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8336 unsigned OutputIdx) {
8337 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8338 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8341 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8342 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8343 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8344 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8346 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8347 SelectionDAG &DAG) {
8348 MVT VT = V1.getSimpleValueType();
8349 assert(VT.is128BitVector() || VT.is256BitVector());
8351 MVT EltVT = VT.getVectorElementType();
8352 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8353 unsigned NumElts = VT.getVectorNumElements();
8355 SmallVector<SDValue, 32> PshufbMask;
8356 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8357 int InputIdx = MaskVals[OutputIdx];
8358 unsigned InputByteIdx;
8360 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8361 InputByteIdx = 0x80;
8363 // Cross lane is not allowed.
8364 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8366 InputByteIdx = InputIdx * EltSizeInBytes;
8367 // Index is an byte offset within the 128-bit lane.
8368 InputByteIdx &= 0xf;
8371 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8372 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8373 if (InputByteIdx != 0x80)
8378 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8380 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8381 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8382 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8385 // v8i16 shuffles - Prefer shuffles in the following order:
8386 // 1. [all] pshuflw, pshufhw, optional move
8387 // 2. [ssse3] 1 x pshufb
8388 // 3. [ssse3] 2 x pshufb + 1 x por
8389 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8391 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8392 SelectionDAG &DAG) {
8393 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8394 SDValue V1 = SVOp->getOperand(0);
8395 SDValue V2 = SVOp->getOperand(1);
8397 SmallVector<int, 8> MaskVals;
8399 // Determine if more than 1 of the words in each of the low and high quadwords
8400 // of the result come from the same quadword of one of the two inputs. Undef
8401 // mask values count as coming from any quadword, for better codegen.
8403 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8404 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8405 unsigned LoQuad[] = { 0, 0, 0, 0 };
8406 unsigned HiQuad[] = { 0, 0, 0, 0 };
8407 // Indices of quads used.
8408 std::bitset<4> InputQuads;
8409 for (unsigned i = 0; i < 8; ++i) {
8410 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8411 int EltIdx = SVOp->getMaskElt(i);
8412 MaskVals.push_back(EltIdx);
8421 InputQuads.set(EltIdx / 4);
8424 int BestLoQuad = -1;
8425 unsigned MaxQuad = 1;
8426 for (unsigned i = 0; i < 4; ++i) {
8427 if (LoQuad[i] > MaxQuad) {
8429 MaxQuad = LoQuad[i];
8433 int BestHiQuad = -1;
8435 for (unsigned i = 0; i < 4; ++i) {
8436 if (HiQuad[i] > MaxQuad) {
8438 MaxQuad = HiQuad[i];
8442 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8443 // of the two input vectors, shuffle them into one input vector so only a
8444 // single pshufb instruction is necessary. If there are more than 2 input
8445 // quads, disable the next transformation since it does not help SSSE3.
8446 bool V1Used = InputQuads[0] || InputQuads[1];
8447 bool V2Used = InputQuads[2] || InputQuads[3];
8448 if (Subtarget->hasSSSE3()) {
8449 if (InputQuads.count() == 2 && V1Used && V2Used) {
8450 BestLoQuad = InputQuads[0] ? 0 : 1;
8451 BestHiQuad = InputQuads[2] ? 2 : 3;
8453 if (InputQuads.count() > 2) {
8459 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8460 // the shuffle mask. If a quad is scored as -1, that means that it contains
8461 // words from all 4 input quadwords.
8463 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8465 BestLoQuad < 0 ? 0 : BestLoQuad,
8466 BestHiQuad < 0 ? 1 : BestHiQuad
8468 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8469 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8470 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8471 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8473 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8474 // source words for the shuffle, to aid later transformations.
8475 bool AllWordsInNewV = true;
8476 bool InOrder[2] = { true, true };
8477 for (unsigned i = 0; i != 8; ++i) {
8478 int idx = MaskVals[i];
8480 InOrder[i/4] = false;
8481 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8483 AllWordsInNewV = false;
8487 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8488 if (AllWordsInNewV) {
8489 for (int i = 0; i != 8; ++i) {
8490 int idx = MaskVals[i];
8493 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8494 if ((idx != i) && idx < 4)
8496 if ((idx != i) && idx > 3)
8505 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8506 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8507 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8508 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8509 unsigned TargetMask = 0;
8510 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8511 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8513 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8514 getShufflePSHUFLWImmediate(SVOp);
8515 V1 = NewV.getOperand(0);
8516 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8520 // Promote splats to a larger type which usually leads to more efficient code.
8521 // FIXME: Is this true if pshufb is available?
8522 if (SVOp->isSplat())
8523 return PromoteSplat(SVOp, DAG);
8525 // If we have SSSE3, and all words of the result are from 1 input vector,
8526 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8527 // is present, fall back to case 4.
8528 if (Subtarget->hasSSSE3()) {
8529 SmallVector<SDValue,16> pshufbMask;
8531 // If we have elements from both input vectors, set the high bit of the
8532 // shuffle mask element to zero out elements that come from V2 in the V1
8533 // mask, and elements that come from V1 in the V2 mask, so that the two
8534 // results can be OR'd together.
8535 bool TwoInputs = V1Used && V2Used;
8536 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8538 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8540 // Calculate the shuffle mask for the second input, shuffle it, and
8541 // OR it with the first shuffled input.
8542 CommuteVectorShuffleMask(MaskVals, 8);
8543 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8544 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8545 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8548 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8549 // and update MaskVals with new element order.
8550 std::bitset<8> InOrder;
8551 if (BestLoQuad >= 0) {
8552 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8553 for (int i = 0; i != 4; ++i) {
8554 int idx = MaskVals[i];
8557 } else if ((idx / 4) == BestLoQuad) {
8562 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8565 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8566 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8567 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8569 getShufflePSHUFLWImmediate(SVOp), DAG);
8573 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8574 // and update MaskVals with the new element order.
8575 if (BestHiQuad >= 0) {
8576 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8577 for (unsigned i = 4; i != 8; ++i) {
8578 int idx = MaskVals[i];
8581 } else if ((idx / 4) == BestHiQuad) {
8582 MaskV[i] = (idx & 3) + 4;
8586 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8589 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8590 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8591 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8593 getShufflePSHUFHWImmediate(SVOp), DAG);
8597 // In case BestHi & BestLo were both -1, which means each quadword has a word
8598 // from each of the four input quadwords, calculate the InOrder bitvector now
8599 // before falling through to the insert/extract cleanup.
8600 if (BestLoQuad == -1 && BestHiQuad == -1) {
8602 for (int i = 0; i != 8; ++i)
8603 if (MaskVals[i] < 0 || MaskVals[i] == i)
8607 // The other elements are put in the right place using pextrw and pinsrw.
8608 for (unsigned i = 0; i != 8; ++i) {
8611 int EltIdx = MaskVals[i];
8614 SDValue ExtOp = (EltIdx < 8) ?
8615 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8616 DAG.getIntPtrConstant(EltIdx)) :
8617 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8618 DAG.getIntPtrConstant(EltIdx - 8));
8619 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8620 DAG.getIntPtrConstant(i));
8625 /// \brief v16i16 shuffles
8627 /// FIXME: We only support generation of a single pshufb currently. We can
8628 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8629 /// well (e.g 2 x pshufb + 1 x por).
8631 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8632 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8633 SDValue V1 = SVOp->getOperand(0);
8634 SDValue V2 = SVOp->getOperand(1);
8637 if (V2.getOpcode() != ISD::UNDEF)
8640 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8641 return getPSHUFB(MaskVals, V1, dl, DAG);
8644 // v16i8 shuffles - Prefer shuffles in the following order:
8645 // 1. [ssse3] 1 x pshufb
8646 // 2. [ssse3] 2 x pshufb + 1 x por
8647 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8648 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8649 const X86Subtarget* Subtarget,
8650 SelectionDAG &DAG) {
8651 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8652 SDValue V1 = SVOp->getOperand(0);
8653 SDValue V2 = SVOp->getOperand(1);
8655 ArrayRef<int> MaskVals = SVOp->getMask();
8657 // Promote splats to a larger type which usually leads to more efficient code.
8658 // FIXME: Is this true if pshufb is available?
8659 if (SVOp->isSplat())
8660 return PromoteSplat(SVOp, DAG);
8662 // If we have SSSE3, case 1 is generated when all result bytes come from
8663 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8664 // present, fall back to case 3.
8666 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8667 if (Subtarget->hasSSSE3()) {
8668 SmallVector<SDValue,16> pshufbMask;
8670 // If all result elements are from one input vector, then only translate
8671 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8673 // Otherwise, we have elements from both input vectors, and must zero out
8674 // elements that come from V2 in the first mask, and V1 in the second mask
8675 // so that we can OR them together.
8676 for (unsigned i = 0; i != 16; ++i) {
8677 int EltIdx = MaskVals[i];
8678 if (EltIdx < 0 || EltIdx >= 16)
8680 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8682 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8683 DAG.getNode(ISD::BUILD_VECTOR, dl,
8684 MVT::v16i8, pshufbMask));
8686 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8687 // the 2nd operand if it's undefined or zero.
8688 if (V2.getOpcode() == ISD::UNDEF ||
8689 ISD::isBuildVectorAllZeros(V2.getNode()))
8692 // Calculate the shuffle mask for the second input, shuffle it, and
8693 // OR it with the first shuffled input.
8695 for (unsigned i = 0; i != 16; ++i) {
8696 int EltIdx = MaskVals[i];
8697 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8698 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8700 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8701 DAG.getNode(ISD::BUILD_VECTOR, dl,
8702 MVT::v16i8, pshufbMask));
8703 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8706 // No SSSE3 - Calculate in place words and then fix all out of place words
8707 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8708 // the 16 different words that comprise the two doublequadword input vectors.
8709 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8710 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8712 for (int i = 0; i != 8; ++i) {
8713 int Elt0 = MaskVals[i*2];
8714 int Elt1 = MaskVals[i*2+1];
8716 // This word of the result is all undef, skip it.
8717 if (Elt0 < 0 && Elt1 < 0)
8720 // This word of the result is already in the correct place, skip it.
8721 if ((Elt0 == i*2) && (Elt1 == i*2+1))
8724 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8725 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8728 // If Elt0 and Elt1 are defined, are consecutive, and can be load
8729 // using a single extract together, load it and store it.
8730 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
8731 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8732 DAG.getIntPtrConstant(Elt1 / 2));
8733 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8734 DAG.getIntPtrConstant(i));
8738 // If Elt1 is defined, extract it from the appropriate source. If the
8739 // source byte is not also odd, shift the extracted word left 8 bits
8740 // otherwise clear the bottom 8 bits if we need to do an or.
8742 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8743 DAG.getIntPtrConstant(Elt1 / 2));
8744 if ((Elt1 & 1) == 0)
8745 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
8747 TLI.getShiftAmountTy(InsElt.getValueType())));
8749 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
8750 DAG.getConstant(0xFF00, MVT::i16));
8752 // If Elt0 is defined, extract it from the appropriate source. If the
8753 // source byte is not also even, shift the extracted word right 8 bits. If
8754 // Elt1 was also defined, OR the extracted values together before
8755 // inserting them in the result.
8757 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
8758 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
8759 if ((Elt0 & 1) != 0)
8760 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8762 TLI.getShiftAmountTy(InsElt0.getValueType())));
8764 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
8765 DAG.getConstant(0x00FF, MVT::i16));
8766 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
8769 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8770 DAG.getIntPtrConstant(i));
8772 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8775 // v32i8 shuffles - Translate to VPSHUFB if possible.
8777 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
8778 const X86Subtarget *Subtarget,
8779 SelectionDAG &DAG) {
8780 MVT VT = SVOp->getSimpleValueType(0);
8781 SDValue V1 = SVOp->getOperand(0);
8782 SDValue V2 = SVOp->getOperand(1);
8784 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8786 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8787 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
8788 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8790 // VPSHUFB may be generated if
8791 // (1) one of input vector is undefined or zeroinitializer.
8792 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
8793 // And (2) the mask indexes don't cross the 128-bit lane.
8794 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
8795 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
8798 if (V1IsAllZero && !V2IsAllZero) {
8799 CommuteVectorShuffleMask(MaskVals, 32);
8802 return getPSHUFB(MaskVals, V1, dl, DAG);
8805 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8806 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8807 /// done when every pair / quad of shuffle mask elements point to elements in
8808 /// the right sequence. e.g.
8809 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
8811 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
8812 SelectionDAG &DAG) {
8813 MVT VT = SVOp->getSimpleValueType(0);
8815 unsigned NumElems = VT.getVectorNumElements();
8818 switch (VT.SimpleTy) {
8819 default: llvm_unreachable("Unexpected!");
8822 return SDValue(SVOp, 0);
8823 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
8824 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8825 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8826 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8827 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8828 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
8831 SmallVector<int, 8> MaskVec;
8832 for (unsigned i = 0; i != NumElems; i += Scale) {
8834 for (unsigned j = 0; j != Scale; ++j) {
8835 int EltIdx = SVOp->getMaskElt(i+j);
8839 StartIdx = (EltIdx / Scale);
8840 if (EltIdx != (int)(StartIdx*Scale + j))
8843 MaskVec.push_back(StartIdx);
8846 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
8847 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8848 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8851 /// getVZextMovL - Return a zero-extending vector move low node.
8853 static SDValue getVZextMovL(MVT VT, MVT OpVT,
8854 SDValue SrcOp, SelectionDAG &DAG,
8855 const X86Subtarget *Subtarget, SDLoc dl) {
8856 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
8857 LoadSDNode *LD = nullptr;
8858 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
8859 LD = dyn_cast<LoadSDNode>(SrcOp);
8861 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
8863 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
8864 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
8865 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8866 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
8867 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
8869 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8870 return DAG.getNode(ISD::BITCAST, dl, VT,
8871 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8872 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8880 return DAG.getNode(ISD::BITCAST, dl, VT,
8881 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8882 DAG.getNode(ISD::BITCAST, dl,
8886 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
8887 /// which could not be matched by any known target speficic shuffle
8889 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8891 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
8892 if (NewOp.getNode())
8895 MVT VT = SVOp->getSimpleValueType(0);
8897 unsigned NumElems = VT.getVectorNumElements();
8898 unsigned NumLaneElems = NumElems / 2;
8901 MVT EltVT = VT.getVectorElementType();
8902 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
8905 SmallVector<int, 16> Mask;
8906 for (unsigned l = 0; l < 2; ++l) {
8907 // Build a shuffle mask for the output, discovering on the fly which
8908 // input vectors to use as shuffle operands (recorded in InputUsed).
8909 // If building a suitable shuffle vector proves too hard, then bail
8910 // out with UseBuildVector set.
8911 bool UseBuildVector = false;
8912 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
8913 unsigned LaneStart = l * NumLaneElems;
8914 for (unsigned i = 0; i != NumLaneElems; ++i) {
8915 // The mask element. This indexes into the input.
8916 int Idx = SVOp->getMaskElt(i+LaneStart);
8918 // the mask element does not index into any input vector.
8923 // The input vector this mask element indexes into.
8924 int Input = Idx / NumLaneElems;
8926 // Turn the index into an offset from the start of the input vector.
8927 Idx -= Input * NumLaneElems;
8929 // Find or create a shuffle vector operand to hold this input.
8931 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
8932 if (InputUsed[OpNo] == Input)
8933 // This input vector is already an operand.
8935 if (InputUsed[OpNo] < 0) {
8936 // Create a new operand for this input vector.
8937 InputUsed[OpNo] = Input;
8942 if (OpNo >= array_lengthof(InputUsed)) {
8943 // More than two input vectors used! Give up on trying to create a
8944 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
8945 UseBuildVector = true;
8949 // Add the mask index for the new shuffle vector.
8950 Mask.push_back(Idx + OpNo * NumLaneElems);
8953 if (UseBuildVector) {
8954 SmallVector<SDValue, 16> SVOps;
8955 for (unsigned i = 0; i != NumLaneElems; ++i) {
8956 // The mask element. This indexes into the input.
8957 int Idx = SVOp->getMaskElt(i+LaneStart);
8959 SVOps.push_back(DAG.getUNDEF(EltVT));
8963 // The input vector this mask element indexes into.
8964 int Input = Idx / NumElems;
8966 // Turn the index into an offset from the start of the input vector.
8967 Idx -= Input * NumElems;
8969 // Extract the vector element by hand.
8970 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
8971 SVOp->getOperand(Input),
8972 DAG.getIntPtrConstant(Idx)));
8975 // Construct the output using a BUILD_VECTOR.
8976 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
8977 } else if (InputUsed[0] < 0) {
8978 // No input vectors were used! The result is undefined.
8979 Output[l] = DAG.getUNDEF(NVT);
8981 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
8982 (InputUsed[0] % 2) * NumLaneElems,
8984 // If only one input was used, use an undefined vector for the other.
8985 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
8986 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
8987 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
8988 // At least one input vector was used. Create a new shuffle vector.
8989 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
8995 // Concatenate the result back
8996 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
8999 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9000 /// 4 elements, and match them with several different shuffle types.
9002 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9003 SDValue V1 = SVOp->getOperand(0);
9004 SDValue V2 = SVOp->getOperand(1);
9006 MVT VT = SVOp->getSimpleValueType(0);
9008 assert(VT.is128BitVector() && "Unsupported vector size");
9010 std::pair<int, int> Locs[4];
9011 int Mask1[] = { -1, -1, -1, -1 };
9012 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9016 for (unsigned i = 0; i != 4; ++i) {
9017 int Idx = PermMask[i];
9019 Locs[i] = std::make_pair(-1, -1);
9021 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9023 Locs[i] = std::make_pair(0, NumLo);
9027 Locs[i] = std::make_pair(1, NumHi);
9029 Mask1[2+NumHi] = Idx;
9035 if (NumLo <= 2 && NumHi <= 2) {
9036 // If no more than two elements come from either vector. This can be
9037 // implemented with two shuffles. First shuffle gather the elements.
9038 // The second shuffle, which takes the first shuffle as both of its
9039 // vector operands, put the elements into the right order.
9040 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9042 int Mask2[] = { -1, -1, -1, -1 };
9044 for (unsigned i = 0; i != 4; ++i)
9045 if (Locs[i].first != -1) {
9046 unsigned Idx = (i < 2) ? 0 : 4;
9047 Idx += Locs[i].first * 2 + Locs[i].second;
9051 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9054 if (NumLo == 3 || NumHi == 3) {
9055 // Otherwise, we must have three elements from one vector, call it X, and
9056 // one element from the other, call it Y. First, use a shufps to build an
9057 // intermediate vector with the one element from Y and the element from X
9058 // that will be in the same half in the final destination (the indexes don't
9059 // matter). Then, use a shufps to build the final vector, taking the half
9060 // containing the element from Y from the intermediate, and the other half
9063 // Normalize it so the 3 elements come from V1.
9064 CommuteVectorShuffleMask(PermMask, 4);
9068 // Find the element from V2.
9070 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9071 int Val = PermMask[HiIndex];
9078 Mask1[0] = PermMask[HiIndex];
9080 Mask1[2] = PermMask[HiIndex^1];
9082 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9085 Mask1[0] = PermMask[0];
9086 Mask1[1] = PermMask[1];
9087 Mask1[2] = HiIndex & 1 ? 6 : 4;
9088 Mask1[3] = HiIndex & 1 ? 4 : 6;
9089 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9092 Mask1[0] = HiIndex & 1 ? 2 : 0;
9093 Mask1[1] = HiIndex & 1 ? 0 : 2;
9094 Mask1[2] = PermMask[2];
9095 Mask1[3] = PermMask[3];
9100 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9103 // Break it into (shuffle shuffle_hi, shuffle_lo).
9104 int LoMask[] = { -1, -1, -1, -1 };
9105 int HiMask[] = { -1, -1, -1, -1 };
9107 int *MaskPtr = LoMask;
9108 unsigned MaskIdx = 0;
9111 for (unsigned i = 0; i != 4; ++i) {
9118 int Idx = PermMask[i];
9120 Locs[i] = std::make_pair(-1, -1);
9121 } else if (Idx < 4) {
9122 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9123 MaskPtr[LoIdx] = Idx;
9126 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9127 MaskPtr[HiIdx] = Idx;
9132 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9133 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9134 int MaskOps[] = { -1, -1, -1, -1 };
9135 for (unsigned i = 0; i != 4; ++i)
9136 if (Locs[i].first != -1)
9137 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9138 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9141 static bool MayFoldVectorLoad(SDValue V) {
9142 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9143 V = V.getOperand(0);
9145 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9146 V = V.getOperand(0);
9147 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9148 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9149 // BUILD_VECTOR (load), undef
9150 V = V.getOperand(0);
9152 return MayFoldLoad(V);
9156 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9157 MVT VT = Op.getSimpleValueType();
9159 // Canonizalize to v2f64.
9160 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9161 return DAG.getNode(ISD::BITCAST, dl, VT,
9162 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9167 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9169 SDValue V1 = Op.getOperand(0);
9170 SDValue V2 = Op.getOperand(1);
9171 MVT VT = Op.getSimpleValueType();
9173 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9175 if (HasSSE2 && VT == MVT::v2f64)
9176 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9178 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9179 return DAG.getNode(ISD::BITCAST, dl, VT,
9180 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9181 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9182 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9186 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9187 SDValue V1 = Op.getOperand(0);
9188 SDValue V2 = Op.getOperand(1);
9189 MVT VT = Op.getSimpleValueType();
9191 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9192 "unsupported shuffle type");
9194 if (V2.getOpcode() == ISD::UNDEF)
9198 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9202 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9203 SDValue V1 = Op.getOperand(0);
9204 SDValue V2 = Op.getOperand(1);
9205 MVT VT = Op.getSimpleValueType();
9206 unsigned NumElems = VT.getVectorNumElements();
9208 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9209 // operand of these instructions is only memory, so check if there's a
9210 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9212 bool CanFoldLoad = false;
9214 // Trivial case, when V2 comes from a load.
9215 if (MayFoldVectorLoad(V2))
9218 // When V1 is a load, it can be folded later into a store in isel, example:
9219 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9221 // (MOVLPSmr addr:$src1, VR128:$src2)
9222 // So, recognize this potential and also use MOVLPS or MOVLPD
9223 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9226 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9228 if (HasSSE2 && NumElems == 2)
9229 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9232 // If we don't care about the second element, proceed to use movss.
9233 if (SVOp->getMaskElt(1) != -1)
9234 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9237 // movl and movlp will both match v2i64, but v2i64 is never matched by
9238 // movl earlier because we make it strict to avoid messing with the movlp load
9239 // folding logic (see the code above getMOVLP call). Match it here then,
9240 // this is horrible, but will stay like this until we move all shuffle
9241 // matching to x86 specific nodes. Note that for the 1st condition all
9242 // types are matched with movsd.
9244 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9245 // as to remove this logic from here, as much as possible
9246 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9247 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9248 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9251 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9253 // Invert the operand order and use SHUFPS to match it.
9254 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9255 getShuffleSHUFImmediate(SVOp), DAG);
9258 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9259 SelectionDAG &DAG) {
9261 MVT VT = Load->getSimpleValueType(0);
9262 MVT EVT = VT.getVectorElementType();
9263 SDValue Addr = Load->getOperand(1);
9264 SDValue NewAddr = DAG.getNode(
9265 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9266 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9269 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9270 DAG.getMachineFunction().getMachineMemOperand(
9271 Load->getMemOperand(), 0, EVT.getStoreSize()));
9275 // It is only safe to call this function if isINSERTPSMask is true for
9276 // this shufflevector mask.
9277 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9278 SelectionDAG &DAG) {
9279 // Generate an insertps instruction when inserting an f32 from memory onto a
9280 // v4f32 or when copying a member from one v4f32 to another.
9281 // We also use it for transferring i32 from one register to another,
9282 // since it simply copies the same bits.
9283 // If we're transferring an i32 from memory to a specific element in a
9284 // register, we output a generic DAG that will match the PINSRD
9286 MVT VT = SVOp->getSimpleValueType(0);
9287 MVT EVT = VT.getVectorElementType();
9288 SDValue V1 = SVOp->getOperand(0);
9289 SDValue V2 = SVOp->getOperand(1);
9290 auto Mask = SVOp->getMask();
9291 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9292 "unsupported vector type for insertps/pinsrd");
9294 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9295 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9296 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9304 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9307 // If we have 1 element from each vector, we have to check if we're
9308 // changing V1's element's place. If so, we're done. Otherwise, we
9309 // should assume we're changing V2's element's place and behave
9311 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9312 assert(DestIndex <= INT32_MAX && "truncated destination index");
9313 if (FromV1 == FromV2 &&
9314 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
9318 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9321 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9322 "More than one element from V1 and from V2, or no elements from one "
9323 "of the vectors. This case should not have returned true from "
9328 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9331 // Get an index into the source vector in the range [0,4) (the mask is
9332 // in the range [0,8) because it can address V1 and V2)
9333 unsigned SrcIndex = Mask[DestIndex] % 4;
9334 if (MayFoldLoad(From)) {
9335 // Trivial case, when From comes from a load and is only used by the
9336 // shuffle. Make it use insertps from the vector that we need from that
9339 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9340 if (!NewLoad.getNode())
9343 if (EVT == MVT::f32) {
9344 // Create this as a scalar to vector to match the instruction pattern.
9345 SDValue LoadScalarToVector =
9346 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9347 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9348 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9350 } else { // EVT == MVT::i32
9351 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9352 // instruction, to match the PINSRD instruction, which loads an i32 to a
9353 // certain vector element.
9354 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9355 DAG.getConstant(DestIndex, MVT::i32));
9359 // Vector-element-to-vector
9360 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9361 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9364 // Reduce a vector shuffle to zext.
9365 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9366 SelectionDAG &DAG) {
9367 // PMOVZX is only available from SSE41.
9368 if (!Subtarget->hasSSE41())
9371 MVT VT = Op.getSimpleValueType();
9373 // Only AVX2 support 256-bit vector integer extending.
9374 if (!Subtarget->hasInt256() && VT.is256BitVector())
9377 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9379 SDValue V1 = Op.getOperand(0);
9380 SDValue V2 = Op.getOperand(1);
9381 unsigned NumElems = VT.getVectorNumElements();
9383 // Extending is an unary operation and the element type of the source vector
9384 // won't be equal to or larger than i64.
9385 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9386 VT.getVectorElementType() == MVT::i64)
9389 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9390 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9391 while ((1U << Shift) < NumElems) {
9392 if (SVOp->getMaskElt(1U << Shift) == 1)
9395 // The maximal ratio is 8, i.e. from i8 to i64.
9400 // Check the shuffle mask.
9401 unsigned Mask = (1U << Shift) - 1;
9402 for (unsigned i = 0; i != NumElems; ++i) {
9403 int EltIdx = SVOp->getMaskElt(i);
9404 if ((i & Mask) != 0 && EltIdx != -1)
9406 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9410 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9411 MVT NeVT = MVT::getIntegerVT(NBits);
9412 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9414 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9417 // Simplify the operand as it's prepared to be fed into shuffle.
9418 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9419 if (V1.getOpcode() == ISD::BITCAST &&
9420 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9421 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9422 V1.getOperand(0).getOperand(0)
9423 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9424 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9425 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9426 ConstantSDNode *CIdx =
9427 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9428 // If it's foldable, i.e. normal load with single use, we will let code
9429 // selection to fold it. Otherwise, we will short the conversion sequence.
9430 if (CIdx && CIdx->getZExtValue() == 0 &&
9431 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9432 MVT FullVT = V.getSimpleValueType();
9433 MVT V1VT = V1.getSimpleValueType();
9434 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9435 // The "ext_vec_elt" node is wider than the result node.
9436 // In this case we should extract subvector from V.
9437 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9438 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9439 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9440 FullVT.getVectorNumElements()/Ratio);
9441 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9442 DAG.getIntPtrConstant(0));
9444 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9448 return DAG.getNode(ISD::BITCAST, DL, VT,
9449 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9452 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9453 SelectionDAG &DAG) {
9454 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9455 MVT VT = Op.getSimpleValueType();
9457 SDValue V1 = Op.getOperand(0);
9458 SDValue V2 = Op.getOperand(1);
9460 if (isZeroShuffle(SVOp))
9461 return getZeroVector(VT, Subtarget, DAG, dl);
9463 // Handle splat operations
9464 if (SVOp->isSplat()) {
9465 // Use vbroadcast whenever the splat comes from a foldable load
9466 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9467 if (Broadcast.getNode())
9471 // Check integer expanding shuffles.
9472 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9473 if (NewOp.getNode())
9476 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9478 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9480 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9481 if (NewOp.getNode())
9482 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9483 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9484 // FIXME: Figure out a cleaner way to do this.
9485 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9486 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9487 if (NewOp.getNode()) {
9488 MVT NewVT = NewOp.getSimpleValueType();
9489 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9490 NewVT, true, false))
9491 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9494 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9495 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9496 if (NewOp.getNode()) {
9497 MVT NewVT = NewOp.getSimpleValueType();
9498 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9499 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9508 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9509 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9510 SDValue V1 = Op.getOperand(0);
9511 SDValue V2 = Op.getOperand(1);
9512 MVT VT = Op.getSimpleValueType();
9514 unsigned NumElems = VT.getVectorNumElements();
9515 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9516 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9517 bool V1IsSplat = false;
9518 bool V2IsSplat = false;
9519 bool HasSSE2 = Subtarget->hasSSE2();
9520 bool HasFp256 = Subtarget->hasFp256();
9521 bool HasInt256 = Subtarget->hasInt256();
9522 MachineFunction &MF = DAG.getMachineFunction();
9523 bool OptForSize = MF.getFunction()->getAttributes().
9524 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9526 // Check if we should use the experimental vector shuffle lowering. If so,
9527 // delegate completely to that code path.
9528 if (ExperimentalVectorShuffleLowering)
9529 return lowerVectorShuffle(Op, Subtarget, DAG);
9531 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9533 if (V1IsUndef && V2IsUndef)
9534 return DAG.getUNDEF(VT);
9536 // When we create a shuffle node we put the UNDEF node to second operand,
9537 // but in some cases the first operand may be transformed to UNDEF.
9538 // In this case we should just commute the node.
9540 return DAG.getCommutedVectorShuffle(*SVOp);
9542 // Vector shuffle lowering takes 3 steps:
9544 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9545 // narrowing and commutation of operands should be handled.
9546 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9548 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9549 // so the shuffle can be broken into other shuffles and the legalizer can
9550 // try the lowering again.
9552 // The general idea is that no vector_shuffle operation should be left to
9553 // be matched during isel, all of them must be converted to a target specific
9556 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9557 // narrowing and commutation of operands should be handled. The actual code
9558 // doesn't include all of those, work in progress...
9559 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9560 if (NewOp.getNode())
9563 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9565 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9566 // unpckh_undef). Only use pshufd if speed is more important than size.
9567 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9568 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9569 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9570 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9572 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9573 V2IsUndef && MayFoldVectorLoad(V1))
9574 return getMOVDDup(Op, dl, V1, DAG);
9576 if (isMOVHLPS_v_undef_Mask(M, VT))
9577 return getMOVHighToLow(Op, dl, DAG);
9579 // Use to match splats
9580 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9581 (VT == MVT::v2f64 || VT == MVT::v2i64))
9582 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9584 if (isPSHUFDMask(M, VT)) {
9585 // The actual implementation will match the mask in the if above and then
9586 // during isel it can match several different instructions, not only pshufd
9587 // as its name says, sad but true, emulate the behavior for now...
9588 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9589 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9591 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9593 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9594 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9596 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9597 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9600 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9604 if (isPALIGNRMask(M, VT, Subtarget))
9605 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9606 getShufflePALIGNRImmediate(SVOp),
9609 // Check if this can be converted into a logical shift.
9610 bool isLeft = false;
9613 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9614 if (isShift && ShVal.hasOneUse()) {
9615 // If the shifted value has multiple uses, it may be cheaper to use
9616 // v_set0 + movlhps or movhlps, etc.
9617 MVT EltVT = VT.getVectorElementType();
9618 ShAmt *= EltVT.getSizeInBits();
9619 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9622 if (isMOVLMask(M, VT)) {
9623 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9624 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9625 if (!isMOVLPMask(M, VT)) {
9626 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9627 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9629 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9630 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9634 // FIXME: fold these into legal mask.
9635 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9636 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9638 if (isMOVHLPSMask(M, VT))
9639 return getMOVHighToLow(Op, dl, DAG);
9641 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9642 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9644 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9645 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9647 if (isMOVLPMask(M, VT))
9648 return getMOVLP(Op, dl, DAG, HasSSE2);
9650 if (ShouldXformToMOVHLPS(M, VT) ||
9651 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9652 return DAG.getCommutedVectorShuffle(*SVOp);
9655 // No better options. Use a vshldq / vsrldq.
9656 MVT EltVT = VT.getVectorElementType();
9657 ShAmt *= EltVT.getSizeInBits();
9658 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9661 bool Commuted = false;
9662 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9663 // 1,1,1,1 -> v8i16 though.
9664 BitVector UndefElements;
9665 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9666 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9668 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9669 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9672 // Canonicalize the splat or undef, if present, to be on the RHS.
9673 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9674 CommuteVectorShuffleMask(M, NumElems);
9676 std::swap(V1IsSplat, V2IsSplat);
9680 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9681 // Shuffling low element of v1 into undef, just return v1.
9684 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9685 // the instruction selector will not match, so get a canonical MOVL with
9686 // swapped operands to undo the commute.
9687 return getMOVL(DAG, dl, VT, V2, V1);
9690 if (isUNPCKLMask(M, VT, HasInt256))
9691 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9693 if (isUNPCKHMask(M, VT, HasInt256))
9694 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9697 // Normalize mask so all entries that point to V2 points to its first
9698 // element then try to match unpck{h|l} again. If match, return a
9699 // new vector_shuffle with the corrected mask.p
9700 SmallVector<int, 8> NewMask(M.begin(), M.end());
9701 NormalizeMask(NewMask, NumElems);
9702 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9703 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9704 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9705 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9709 // Commute is back and try unpck* again.
9710 // FIXME: this seems wrong.
9711 CommuteVectorShuffleMask(M, NumElems);
9713 std::swap(V1IsSplat, V2IsSplat);
9715 if (isUNPCKLMask(M, VT, HasInt256))
9716 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9718 if (isUNPCKHMask(M, VT, HasInt256))
9719 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9722 // Normalize the node to match x86 shuffle ops if needed
9723 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9724 return DAG.getCommutedVectorShuffle(*SVOp);
9726 // The checks below are all present in isShuffleMaskLegal, but they are
9727 // inlined here right now to enable us to directly emit target specific
9728 // nodes, and remove one by one until they don't return Op anymore.
9730 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9731 SVOp->getSplatIndex() == 0 && V2IsUndef) {
9732 if (VT == MVT::v2f64 || VT == MVT::v2i64)
9733 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9736 if (isPSHUFHWMask(M, VT, HasInt256))
9737 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9738 getShufflePSHUFHWImmediate(SVOp),
9741 if (isPSHUFLWMask(M, VT, HasInt256))
9742 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9743 getShufflePSHUFLWImmediate(SVOp),
9747 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9749 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9751 if (isSHUFPMask(M, VT))
9752 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9753 getShuffleSHUFImmediate(SVOp), DAG);
9755 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9756 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9757 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9758 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9760 //===--------------------------------------------------------------------===//
9761 // Generate target specific nodes for 128 or 256-bit shuffles only
9762 // supported in the AVX instruction set.
9765 // Handle VMOVDDUPY permutations
9766 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9767 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9769 // Handle VPERMILPS/D* permutations
9770 if (isVPERMILPMask(M, VT)) {
9771 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9772 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9773 getShuffleSHUFImmediate(SVOp), DAG);
9774 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9775 getShuffleSHUFImmediate(SVOp), DAG);
9779 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9780 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9781 Idx*(NumElems/2), DAG, dl);
9783 // Handle VPERM2F128/VPERM2I128 permutations
9784 if (isVPERM2X128Mask(M, VT, HasFp256))
9785 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9786 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9788 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9789 return getINSERTPS(SVOp, dl, DAG);
9792 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9793 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9795 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9796 VT.is512BitVector()) {
9797 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9798 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9799 SmallVector<SDValue, 16> permclMask;
9800 for (unsigned i = 0; i != NumElems; ++i) {
9801 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9804 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9806 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9807 return DAG.getNode(X86ISD::VPERMV, dl, VT,
9808 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9809 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9810 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9813 //===--------------------------------------------------------------------===//
9814 // Since no target specific shuffle was selected for this generic one,
9815 // lower it into other known shuffles. FIXME: this isn't true yet, but
9816 // this is the plan.
9819 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9820 if (VT == MVT::v8i16) {
9821 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9822 if (NewOp.getNode())
9826 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9827 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9828 if (NewOp.getNode())
9832 if (VT == MVT::v16i8) {
9833 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9834 if (NewOp.getNode())
9838 if (VT == MVT::v32i8) {
9839 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9840 if (NewOp.getNode())
9844 // Handle all 128-bit wide vectors with 4 elements, and match them with
9845 // several different shuffle types.
9846 if (NumElems == 4 && VT.is128BitVector())
9847 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9849 // Handle general 256-bit shuffles
9850 if (VT.is256BitVector())
9851 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9856 // This function assumes its argument is a BUILD_VECTOR of constants or
9857 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
9859 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
9860 unsigned &MaskValue) {
9862 unsigned NumElems = BuildVector->getNumOperands();
9863 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9864 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9865 unsigned NumElemsInLane = NumElems / NumLanes;
9867 // Blend for v16i16 should be symetric for the both lanes.
9868 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9869 SDValue EltCond = BuildVector->getOperand(i);
9870 SDValue SndLaneEltCond =
9871 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
9873 int Lane1Cond = -1, Lane2Cond = -1;
9874 if (isa<ConstantSDNode>(EltCond))
9875 Lane1Cond = !isZero(EltCond);
9876 if (isa<ConstantSDNode>(SndLaneEltCond))
9877 Lane2Cond = !isZero(SndLaneEltCond);
9879 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
9880 // Lane1Cond != 0, means we want the first argument.
9881 // Lane1Cond == 0, means we want the second argument.
9882 // The encoding of this argument is 0 for the first argument, 1
9883 // for the second. Therefore, invert the condition.
9884 MaskValue |= !Lane1Cond << i;
9885 else if (Lane1Cond < 0)
9886 MaskValue |= !Lane2Cond << i;
9893 // Try to lower a vselect node into a simple blend instruction.
9894 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
9895 SelectionDAG &DAG) {
9896 SDValue Cond = Op.getOperand(0);
9897 SDValue LHS = Op.getOperand(1);
9898 SDValue RHS = Op.getOperand(2);
9900 MVT VT = Op.getSimpleValueType();
9901 MVT EltVT = VT.getVectorElementType();
9902 unsigned NumElems = VT.getVectorNumElements();
9904 // There is no blend with immediate in AVX-512.
9905 if (VT.is512BitVector())
9908 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
9910 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
9913 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
9916 // Check the mask for BLEND and build the value.
9917 unsigned MaskValue = 0;
9918 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
9921 // Convert i32 vectors to floating point if it is not AVX2.
9922 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9924 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9925 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9927 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
9928 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
9931 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
9932 DAG.getConstant(MaskValue, MVT::i32));
9933 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9936 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
9937 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
9938 if (BlendOp.getNode())
9941 // Some types for vselect were previously set to Expand, not Legal or
9942 // Custom. Return an empty SDValue so we fall-through to Expand, after
9943 // the Custom lowering phase.
9944 MVT VT = Op.getSimpleValueType();
9945 switch (VT.SimpleTy) {
9953 // We couldn't create a "Blend with immediate" node.
9954 // This node should still be legal, but we'll have to emit a blendv*
9959 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9960 MVT VT = Op.getSimpleValueType();
9963 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
9966 if (VT.getSizeInBits() == 8) {
9967 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
9968 Op.getOperand(0), Op.getOperand(1));
9969 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9970 DAG.getValueType(VT));
9971 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9974 if (VT.getSizeInBits() == 16) {
9975 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9976 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
9978 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9979 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9980 DAG.getNode(ISD::BITCAST, dl,
9984 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
9985 Op.getOperand(0), Op.getOperand(1));
9986 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9987 DAG.getValueType(VT));
9988 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9991 if (VT == MVT::f32) {
9992 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
9993 // the result back to FR32 register. It's only worth matching if the
9994 // result has a single use which is a store or a bitcast to i32. And in
9995 // the case of a store, it's not worth it if the index is a constant 0,
9996 // because a MOVSSmr can be used instead, which is smaller and faster.
9997 if (!Op.hasOneUse())
9999 SDNode *User = *Op.getNode()->use_begin();
10000 if ((User->getOpcode() != ISD::STORE ||
10001 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10002 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10003 (User->getOpcode() != ISD::BITCAST ||
10004 User->getValueType(0) != MVT::i32))
10006 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10007 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10010 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10013 if (VT == MVT::i32 || VT == MVT::i64) {
10014 // ExtractPS/pextrq works with constant index.
10015 if (isa<ConstantSDNode>(Op.getOperand(1)))
10021 /// Extract one bit from mask vector, like v16i1 or v8i1.
10022 /// AVX-512 feature.
10024 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10025 SDValue Vec = Op.getOperand(0);
10027 MVT VecVT = Vec.getSimpleValueType();
10028 SDValue Idx = Op.getOperand(1);
10029 MVT EltVT = Op.getSimpleValueType();
10031 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10033 // variable index can't be handled in mask registers,
10034 // extend vector to VR512
10035 if (!isa<ConstantSDNode>(Idx)) {
10036 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10037 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10038 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10039 ExtVT.getVectorElementType(), Ext, Idx);
10040 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10043 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10044 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10045 unsigned MaxSift = rc->getSize()*8 - 1;
10046 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10047 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10048 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10049 DAG.getConstant(MaxSift, MVT::i8));
10050 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10051 DAG.getIntPtrConstant(0));
10055 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10056 SelectionDAG &DAG) const {
10058 SDValue Vec = Op.getOperand(0);
10059 MVT VecVT = Vec.getSimpleValueType();
10060 SDValue Idx = Op.getOperand(1);
10062 if (Op.getSimpleValueType() == MVT::i1)
10063 return ExtractBitFromMaskVector(Op, DAG);
10065 if (!isa<ConstantSDNode>(Idx)) {
10066 if (VecVT.is512BitVector() ||
10067 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10068 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10071 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10072 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10073 MaskEltVT.getSizeInBits());
10075 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10076 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10077 getZeroVector(MaskVT, Subtarget, DAG, dl),
10078 Idx, DAG.getConstant(0, getPointerTy()));
10079 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10080 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10081 Perm, DAG.getConstant(0, getPointerTy()));
10086 // If this is a 256-bit vector result, first extract the 128-bit vector and
10087 // then extract the element from the 128-bit vector.
10088 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10090 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10091 // Get the 128-bit vector.
10092 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10093 MVT EltVT = VecVT.getVectorElementType();
10095 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10097 //if (IdxVal >= NumElems/2)
10098 // IdxVal -= NumElems/2;
10099 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10100 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10101 DAG.getConstant(IdxVal, MVT::i32));
10104 assert(VecVT.is128BitVector() && "Unexpected vector length");
10106 if (Subtarget->hasSSE41()) {
10107 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10112 MVT VT = Op.getSimpleValueType();
10113 // TODO: handle v16i8.
10114 if (VT.getSizeInBits() == 16) {
10115 SDValue Vec = Op.getOperand(0);
10116 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10118 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10119 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10120 DAG.getNode(ISD::BITCAST, dl,
10122 Op.getOperand(1)));
10123 // Transform it so it match pextrw which produces a 32-bit result.
10124 MVT EltVT = MVT::i32;
10125 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10126 Op.getOperand(0), Op.getOperand(1));
10127 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10128 DAG.getValueType(VT));
10129 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10132 if (VT.getSizeInBits() == 32) {
10133 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10137 // SHUFPS the element to the lowest double word, then movss.
10138 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10139 MVT VVT = Op.getOperand(0).getSimpleValueType();
10140 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10141 DAG.getUNDEF(VVT), Mask);
10142 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10143 DAG.getIntPtrConstant(0));
10146 if (VT.getSizeInBits() == 64) {
10147 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10148 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10149 // to match extract_elt for f64.
10150 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10154 // UNPCKHPD the element to the lowest double word, then movsd.
10155 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10156 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10157 int Mask[2] = { 1, -1 };
10158 MVT VVT = Op.getOperand(0).getSimpleValueType();
10159 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10160 DAG.getUNDEF(VVT), Mask);
10161 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10162 DAG.getIntPtrConstant(0));
10168 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10169 MVT VT = Op.getSimpleValueType();
10170 MVT EltVT = VT.getVectorElementType();
10173 SDValue N0 = Op.getOperand(0);
10174 SDValue N1 = Op.getOperand(1);
10175 SDValue N2 = Op.getOperand(2);
10177 if (!VT.is128BitVector())
10180 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
10181 isa<ConstantSDNode>(N2)) {
10183 if (VT == MVT::v8i16)
10184 Opc = X86ISD::PINSRW;
10185 else if (VT == MVT::v16i8)
10186 Opc = X86ISD::PINSRB;
10188 Opc = X86ISD::PINSRB;
10190 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10192 if (N1.getValueType() != MVT::i32)
10193 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10194 if (N2.getValueType() != MVT::i32)
10195 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10196 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10199 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
10200 // Bits [7:6] of the constant are the source select. This will always be
10201 // zero here. The DAG Combiner may combine an extract_elt index into these
10202 // bits. For example (insert (extract, 3), 2) could be matched by putting
10203 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10204 // Bits [5:4] of the constant are the destination select. This is the
10205 // value of the incoming immediate.
10206 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10207 // combine either bitwise AND or insert of float 0.0 to set these bits.
10208 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
10209 // Create this as a scalar to vector..
10210 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10211 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10214 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
10215 // PINSR* works with constant index.
10221 /// Insert one bit to mask vector, like v16i1 or v8i1.
10222 /// AVX-512 feature.
10224 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10226 SDValue Vec = Op.getOperand(0);
10227 SDValue Elt = Op.getOperand(1);
10228 SDValue Idx = Op.getOperand(2);
10229 MVT VecVT = Vec.getSimpleValueType();
10231 if (!isa<ConstantSDNode>(Idx)) {
10232 // Non constant index. Extend source and destination,
10233 // insert element and then truncate the result.
10234 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10235 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10236 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10237 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10238 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10239 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10242 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10243 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10244 if (Vec.getOpcode() == ISD::UNDEF)
10245 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10246 DAG.getConstant(IdxVal, MVT::i8));
10247 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10248 unsigned MaxSift = rc->getSize()*8 - 1;
10249 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10250 DAG.getConstant(MaxSift, MVT::i8));
10251 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10252 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10253 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10256 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
10257 MVT VT = Op.getSimpleValueType();
10258 MVT EltVT = VT.getVectorElementType();
10260 if (EltVT == MVT::i1)
10261 return InsertBitToMaskVector(Op, DAG);
10264 SDValue N0 = Op.getOperand(0);
10265 SDValue N1 = Op.getOperand(1);
10266 SDValue N2 = Op.getOperand(2);
10268 // If this is a 256-bit vector result, first extract the 128-bit vector,
10269 // insert the element into the extracted half and then place it back.
10270 if (VT.is256BitVector() || VT.is512BitVector()) {
10271 if (!isa<ConstantSDNode>(N2))
10274 // Get the desired 128-bit vector half.
10275 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10276 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10278 // Insert the element into the desired half.
10279 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10280 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10282 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10283 DAG.getConstant(IdxIn128, MVT::i32));
10285 // Insert the changed part back to the 256-bit vector
10286 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10289 if (Subtarget->hasSSE41())
10290 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10292 if (EltVT == MVT::i8)
10295 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10296 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10297 // as its second argument.
10298 if (N1.getValueType() != MVT::i32)
10299 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10300 if (N2.getValueType() != MVT::i32)
10301 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10302 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10307 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10309 MVT OpVT = Op.getSimpleValueType();
10311 // If this is a 256-bit vector result, first insert into a 128-bit
10312 // vector and then insert into the 256-bit vector.
10313 if (!OpVT.is128BitVector()) {
10314 // Insert into a 128-bit vector.
10315 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10316 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10317 OpVT.getVectorNumElements() / SizeFactor);
10319 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10321 // Insert the 128-bit vector.
10322 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10325 if (OpVT == MVT::v1i64 &&
10326 Op.getOperand(0).getValueType() == MVT::i64)
10327 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10329 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10330 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10331 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10332 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10335 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10336 // a simple subregister reference or explicit instructions to grab
10337 // upper bits of a vector.
10338 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10339 SelectionDAG &DAG) {
10341 SDValue In = Op.getOperand(0);
10342 SDValue Idx = Op.getOperand(1);
10343 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10344 MVT ResVT = Op.getSimpleValueType();
10345 MVT InVT = In.getSimpleValueType();
10347 if (Subtarget->hasFp256()) {
10348 if (ResVT.is128BitVector() &&
10349 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10350 isa<ConstantSDNode>(Idx)) {
10351 return Extract128BitVector(In, IdxVal, DAG, dl);
10353 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10354 isa<ConstantSDNode>(Idx)) {
10355 return Extract256BitVector(In, IdxVal, DAG, dl);
10361 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10362 // simple superregister reference or explicit instructions to insert
10363 // the upper bits of a vector.
10364 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10365 SelectionDAG &DAG) {
10366 if (Subtarget->hasFp256()) {
10367 SDLoc dl(Op.getNode());
10368 SDValue Vec = Op.getNode()->getOperand(0);
10369 SDValue SubVec = Op.getNode()->getOperand(1);
10370 SDValue Idx = Op.getNode()->getOperand(2);
10372 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10373 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10374 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10375 isa<ConstantSDNode>(Idx)) {
10376 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10377 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10380 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10381 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10382 isa<ConstantSDNode>(Idx)) {
10383 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10384 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10390 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10391 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10392 // one of the above mentioned nodes. It has to be wrapped because otherwise
10393 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10394 // be used to form addressing mode. These wrapped nodes will be selected
10397 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10398 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10400 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10401 // global base reg.
10402 unsigned char OpFlag = 0;
10403 unsigned WrapperKind = X86ISD::Wrapper;
10404 CodeModel::Model M = DAG.getTarget().getCodeModel();
10406 if (Subtarget->isPICStyleRIPRel() &&
10407 (M == CodeModel::Small || M == CodeModel::Kernel))
10408 WrapperKind = X86ISD::WrapperRIP;
10409 else if (Subtarget->isPICStyleGOT())
10410 OpFlag = X86II::MO_GOTOFF;
10411 else if (Subtarget->isPICStyleStubPIC())
10412 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10414 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10415 CP->getAlignment(),
10416 CP->getOffset(), OpFlag);
10418 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10419 // With PIC, the address is actually $g + Offset.
10421 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10422 DAG.getNode(X86ISD::GlobalBaseReg,
10423 SDLoc(), getPointerTy()),
10430 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10431 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10433 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10434 // global base reg.
10435 unsigned char OpFlag = 0;
10436 unsigned WrapperKind = X86ISD::Wrapper;
10437 CodeModel::Model M = DAG.getTarget().getCodeModel();
10439 if (Subtarget->isPICStyleRIPRel() &&
10440 (M == CodeModel::Small || M == CodeModel::Kernel))
10441 WrapperKind = X86ISD::WrapperRIP;
10442 else if (Subtarget->isPICStyleGOT())
10443 OpFlag = X86II::MO_GOTOFF;
10444 else if (Subtarget->isPICStyleStubPIC())
10445 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10447 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10450 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10452 // With PIC, the address is actually $g + Offset.
10454 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10455 DAG.getNode(X86ISD::GlobalBaseReg,
10456 SDLoc(), getPointerTy()),
10463 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10464 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10466 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10467 // global base reg.
10468 unsigned char OpFlag = 0;
10469 unsigned WrapperKind = X86ISD::Wrapper;
10470 CodeModel::Model M = DAG.getTarget().getCodeModel();
10472 if (Subtarget->isPICStyleRIPRel() &&
10473 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10474 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10475 OpFlag = X86II::MO_GOTPCREL;
10476 WrapperKind = X86ISD::WrapperRIP;
10477 } else if (Subtarget->isPICStyleGOT()) {
10478 OpFlag = X86II::MO_GOT;
10479 } else if (Subtarget->isPICStyleStubPIC()) {
10480 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10481 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10482 OpFlag = X86II::MO_DARWIN_NONLAZY;
10485 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10488 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10490 // With PIC, the address is actually $g + Offset.
10491 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10492 !Subtarget->is64Bit()) {
10493 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10494 DAG.getNode(X86ISD::GlobalBaseReg,
10495 SDLoc(), getPointerTy()),
10499 // For symbols that require a load from a stub to get the address, emit the
10501 if (isGlobalStubReference(OpFlag))
10502 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10503 MachinePointerInfo::getGOT(), false, false, false, 0);
10509 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10510 // Create the TargetBlockAddressAddress node.
10511 unsigned char OpFlags =
10512 Subtarget->ClassifyBlockAddressReference();
10513 CodeModel::Model M = DAG.getTarget().getCodeModel();
10514 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10515 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10517 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10520 if (Subtarget->isPICStyleRIPRel() &&
10521 (M == CodeModel::Small || M == CodeModel::Kernel))
10522 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10524 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10526 // With PIC, the address is actually $g + Offset.
10527 if (isGlobalRelativeToPICBase(OpFlags)) {
10528 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10529 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10537 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10538 int64_t Offset, SelectionDAG &DAG) const {
10539 // Create the TargetGlobalAddress node, folding in the constant
10540 // offset if it is legal.
10541 unsigned char OpFlags =
10542 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10543 CodeModel::Model M = DAG.getTarget().getCodeModel();
10545 if (OpFlags == X86II::MO_NO_FLAG &&
10546 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10547 // A direct static reference to a global.
10548 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10551 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10554 if (Subtarget->isPICStyleRIPRel() &&
10555 (M == CodeModel::Small || M == CodeModel::Kernel))
10556 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10558 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10560 // With PIC, the address is actually $g + Offset.
10561 if (isGlobalRelativeToPICBase(OpFlags)) {
10562 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10563 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10567 // For globals that require a load from a stub to get the address, emit the
10569 if (isGlobalStubReference(OpFlags))
10570 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10571 MachinePointerInfo::getGOT(), false, false, false, 0);
10573 // If there was a non-zero offset that we didn't fold, create an explicit
10574 // addition for it.
10576 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10577 DAG.getConstant(Offset, getPointerTy()));
10583 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10584 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10585 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10586 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10590 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10591 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10592 unsigned char OperandFlags, bool LocalDynamic = false) {
10593 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10594 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10596 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10597 GA->getValueType(0),
10601 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10605 SDValue Ops[] = { Chain, TGA, *InFlag };
10606 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10608 SDValue Ops[] = { Chain, TGA };
10609 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10612 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10613 MFI->setAdjustsStack(true);
10615 SDValue Flag = Chain.getValue(1);
10616 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10619 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10621 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10624 SDLoc dl(GA); // ? function entry point might be better
10625 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10626 DAG.getNode(X86ISD::GlobalBaseReg,
10627 SDLoc(), PtrVT), InFlag);
10628 InFlag = Chain.getValue(1);
10630 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10633 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10635 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10637 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10638 X86::RAX, X86II::MO_TLSGD);
10641 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10647 // Get the start address of the TLS block for this module.
10648 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10649 .getInfo<X86MachineFunctionInfo>();
10650 MFI->incNumLocalDynamicTLSAccesses();
10654 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10655 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10658 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10659 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10660 InFlag = Chain.getValue(1);
10661 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10662 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10665 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10669 unsigned char OperandFlags = X86II::MO_DTPOFF;
10670 unsigned WrapperKind = X86ISD::Wrapper;
10671 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10672 GA->getValueType(0),
10673 GA->getOffset(), OperandFlags);
10674 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10676 // Add x@dtpoff with the base.
10677 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10680 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10681 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10682 const EVT PtrVT, TLSModel::Model model,
10683 bool is64Bit, bool isPIC) {
10686 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10687 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10688 is64Bit ? 257 : 256));
10690 SDValue ThreadPointer =
10691 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10692 MachinePointerInfo(Ptr), false, false, false, 0);
10694 unsigned char OperandFlags = 0;
10695 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10697 unsigned WrapperKind = X86ISD::Wrapper;
10698 if (model == TLSModel::LocalExec) {
10699 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10700 } else if (model == TLSModel::InitialExec) {
10702 OperandFlags = X86II::MO_GOTTPOFF;
10703 WrapperKind = X86ISD::WrapperRIP;
10705 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10708 llvm_unreachable("Unexpected model");
10711 // emit "addl x@ntpoff,%eax" (local exec)
10712 // or "addl x@indntpoff,%eax" (initial exec)
10713 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10715 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10716 GA->getOffset(), OperandFlags);
10717 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10719 if (model == TLSModel::InitialExec) {
10720 if (isPIC && !is64Bit) {
10721 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10722 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10726 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10727 MachinePointerInfo::getGOT(), false, false, false, 0);
10730 // The address of the thread local variable is the add of the thread
10731 // pointer with the offset of the variable.
10732 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10736 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10738 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10739 const GlobalValue *GV = GA->getGlobal();
10741 if (Subtarget->isTargetELF()) {
10742 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10745 case TLSModel::GeneralDynamic:
10746 if (Subtarget->is64Bit())
10747 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10748 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10749 case TLSModel::LocalDynamic:
10750 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10751 Subtarget->is64Bit());
10752 case TLSModel::InitialExec:
10753 case TLSModel::LocalExec:
10754 return LowerToTLSExecModel(
10755 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10756 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10758 llvm_unreachable("Unknown TLS model.");
10761 if (Subtarget->isTargetDarwin()) {
10762 // Darwin only has one model of TLS. Lower to that.
10763 unsigned char OpFlag = 0;
10764 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10765 X86ISD::WrapperRIP : X86ISD::Wrapper;
10767 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10768 // global base reg.
10769 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10770 !Subtarget->is64Bit();
10772 OpFlag = X86II::MO_TLVP_PIC_BASE;
10774 OpFlag = X86II::MO_TLVP;
10776 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10777 GA->getValueType(0),
10778 GA->getOffset(), OpFlag);
10779 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10781 // With PIC32, the address is actually $g + Offset.
10783 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10784 DAG.getNode(X86ISD::GlobalBaseReg,
10785 SDLoc(), getPointerTy()),
10788 // Lowering the machine isd will make sure everything is in the right
10790 SDValue Chain = DAG.getEntryNode();
10791 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10792 SDValue Args[] = { Chain, Offset };
10793 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10795 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10796 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10797 MFI->setAdjustsStack(true);
10799 // And our return value (tls address) is in the standard call return value
10801 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10802 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10803 Chain.getValue(1));
10806 if (Subtarget->isTargetKnownWindowsMSVC() ||
10807 Subtarget->isTargetWindowsGNU()) {
10808 // Just use the implicit TLS architecture
10809 // Need to generate someting similar to:
10810 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10812 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10813 // mov rcx, qword [rdx+rcx*8]
10814 // mov eax, .tls$:tlsvar
10815 // [rax+rcx] contains the address
10816 // Windows 64bit: gs:0x58
10817 // Windows 32bit: fs:__tls_array
10820 SDValue Chain = DAG.getEntryNode();
10822 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10823 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10824 // use its literal value of 0x2C.
10825 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10826 ? Type::getInt8PtrTy(*DAG.getContext(),
10828 : Type::getInt32PtrTy(*DAG.getContext(),
10832 Subtarget->is64Bit()
10833 ? DAG.getIntPtrConstant(0x58)
10834 : (Subtarget->isTargetWindowsGNU()
10835 ? DAG.getIntPtrConstant(0x2C)
10836 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10838 SDValue ThreadPointer =
10839 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10840 MachinePointerInfo(Ptr), false, false, false, 0);
10842 // Load the _tls_index variable
10843 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10844 if (Subtarget->is64Bit())
10845 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10846 IDX, MachinePointerInfo(), MVT::i32,
10847 false, false, false, 0);
10849 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10850 false, false, false, 0);
10852 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10854 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10856 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10857 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10858 false, false, false, 0);
10860 // Get the offset of start of .tls section
10861 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10862 GA->getValueType(0),
10863 GA->getOffset(), X86II::MO_SECREL);
10864 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10866 // The address of the thread local variable is the add of the thread
10867 // pointer with the offset of the variable.
10868 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10871 llvm_unreachable("TLS not implemented for this target.");
10874 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
10875 /// and take a 2 x i32 value to shift plus a shift amount.
10876 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
10877 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
10878 MVT VT = Op.getSimpleValueType();
10879 unsigned VTBits = VT.getSizeInBits();
10881 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
10882 SDValue ShOpLo = Op.getOperand(0);
10883 SDValue ShOpHi = Op.getOperand(1);
10884 SDValue ShAmt = Op.getOperand(2);
10885 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
10886 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
10888 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10889 DAG.getConstant(VTBits - 1, MVT::i8));
10890 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
10891 DAG.getConstant(VTBits - 1, MVT::i8))
10892 : DAG.getConstant(0, VT);
10894 SDValue Tmp2, Tmp3;
10895 if (Op.getOpcode() == ISD::SHL_PARTS) {
10896 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
10897 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10899 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
10900 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
10903 // If the shift amount is larger or equal than the width of a part we can't
10904 // rely on the results of shld/shrd. Insert a test and select the appropriate
10905 // values for large shift amounts.
10906 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10907 DAG.getConstant(VTBits, MVT::i8));
10908 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10909 AndNode, DAG.getConstant(0, MVT::i8));
10912 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10913 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
10914 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
10916 if (Op.getOpcode() == ISD::SHL_PARTS) {
10917 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10918 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10920 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10921 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10924 SDValue Ops[2] = { Lo, Hi };
10925 return DAG.getMergeValues(Ops, dl);
10928 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
10929 SelectionDAG &DAG) const {
10930 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
10932 if (SrcVT.isVector())
10935 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
10936 "Unknown SINT_TO_FP to lower!");
10938 // These are really Legal; return the operand so the caller accepts it as
10940 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
10942 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
10943 Subtarget->is64Bit()) {
10948 unsigned Size = SrcVT.getSizeInBits()/8;
10949 MachineFunction &MF = DAG.getMachineFunction();
10950 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
10951 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10952 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10954 MachinePointerInfo::getFixedStack(SSFI),
10956 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
10959 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
10961 SelectionDAG &DAG) const {
10965 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
10967 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
10969 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
10971 unsigned ByteSize = SrcVT.getSizeInBits()/8;
10973 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
10974 MachineMemOperand *MMO;
10976 int SSFI = FI->getIndex();
10978 DAG.getMachineFunction()
10979 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10980 MachineMemOperand::MOLoad, ByteSize, ByteSize);
10982 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
10983 StackSlot = StackSlot.getOperand(1);
10985 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
10986 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
10988 Tys, Ops, SrcVT, MMO);
10991 Chain = Result.getValue(1);
10992 SDValue InFlag = Result.getValue(2);
10994 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
10995 // shouldn't be necessary except that RFP cannot be live across
10996 // multiple blocks. When stackifier is fixed, they can be uncoupled.
10997 MachineFunction &MF = DAG.getMachineFunction();
10998 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
10999 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11000 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11001 Tys = DAG.getVTList(MVT::Other);
11003 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11005 MachineMemOperand *MMO =
11006 DAG.getMachineFunction()
11007 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11008 MachineMemOperand::MOStore, SSFISize, SSFISize);
11010 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11011 Ops, Op.getValueType(), MMO);
11012 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11013 MachinePointerInfo::getFixedStack(SSFI),
11014 false, false, false, 0);
11020 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11021 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11022 SelectionDAG &DAG) const {
11023 // This algorithm is not obvious. Here it is what we're trying to output:
11026 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11027 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11029 haddpd %xmm0, %xmm0
11031 pshufd $0x4e, %xmm0, %xmm1
11037 LLVMContext *Context = DAG.getContext();
11039 // Build some magic constants.
11040 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11041 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11042 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11044 SmallVector<Constant*,2> CV1;
11046 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11047 APInt(64, 0x4330000000000000ULL))));
11049 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11050 APInt(64, 0x4530000000000000ULL))));
11051 Constant *C1 = ConstantVector::get(CV1);
11052 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11054 // Load the 64-bit value into an XMM register.
11055 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11057 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11058 MachinePointerInfo::getConstantPool(),
11059 false, false, false, 16);
11060 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11061 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11064 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11065 MachinePointerInfo::getConstantPool(),
11066 false, false, false, 16);
11067 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11068 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11071 if (Subtarget->hasSSE3()) {
11072 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11073 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11075 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11076 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11078 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11079 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11083 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11084 DAG.getIntPtrConstant(0));
11087 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11088 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11089 SelectionDAG &DAG) const {
11091 // FP constant to bias correct the final result.
11092 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11095 // Load the 32-bit value into an XMM register.
11096 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11099 // Zero out the upper parts of the register.
11100 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11102 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11103 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11104 DAG.getIntPtrConstant(0));
11106 // Or the load with the bias.
11107 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11108 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11109 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11110 MVT::v2f64, Load)),
11111 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11112 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11113 MVT::v2f64, Bias)));
11114 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11115 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11116 DAG.getIntPtrConstant(0));
11118 // Subtract the bias.
11119 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11121 // Handle final rounding.
11122 EVT DestVT = Op.getValueType();
11124 if (DestVT.bitsLT(MVT::f64))
11125 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11126 DAG.getIntPtrConstant(0));
11127 if (DestVT.bitsGT(MVT::f64))
11128 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11130 // Handle final rounding.
11134 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11135 SelectionDAG &DAG) const {
11136 SDValue N0 = Op.getOperand(0);
11137 MVT SVT = N0.getSimpleValueType();
11140 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11141 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11142 "Custom UINT_TO_FP is not supported!");
11144 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11145 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11146 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11149 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11150 SelectionDAG &DAG) const {
11151 SDValue N0 = Op.getOperand(0);
11154 if (Op.getValueType().isVector())
11155 return lowerUINT_TO_FP_vec(Op, DAG);
11157 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11158 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11159 // the optimization here.
11160 if (DAG.SignBitIsZero(N0))
11161 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11163 MVT SrcVT = N0.getSimpleValueType();
11164 MVT DstVT = Op.getSimpleValueType();
11165 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11166 return LowerUINT_TO_FP_i64(Op, DAG);
11167 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11168 return LowerUINT_TO_FP_i32(Op, DAG);
11169 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11172 // Make a 64-bit buffer, and use it to build an FILD.
11173 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11174 if (SrcVT == MVT::i32) {
11175 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11176 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11177 getPointerTy(), StackSlot, WordOff);
11178 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11179 StackSlot, MachinePointerInfo(),
11181 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11182 OffsetSlot, MachinePointerInfo(),
11184 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11188 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11189 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11190 StackSlot, MachinePointerInfo(),
11192 // For i64 source, we need to add the appropriate power of 2 if the input
11193 // was negative. This is the same as the optimization in
11194 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11195 // we must be careful to do the computation in x87 extended precision, not
11196 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11197 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11198 MachineMemOperand *MMO =
11199 DAG.getMachineFunction()
11200 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11201 MachineMemOperand::MOLoad, 8, 8);
11203 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11204 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11205 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11208 APInt FF(32, 0x5F800000ULL);
11210 // Check whether the sign bit is set.
11211 SDValue SignSet = DAG.getSetCC(dl,
11212 getSetCCResultType(*DAG.getContext(), MVT::i64),
11213 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11216 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11217 SDValue FudgePtr = DAG.getConstantPool(
11218 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11221 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11222 SDValue Zero = DAG.getIntPtrConstant(0);
11223 SDValue Four = DAG.getIntPtrConstant(4);
11224 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11226 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11228 // Load the value out, extending it from f32 to f80.
11229 // FIXME: Avoid the extend by constructing the right constant pool?
11230 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11231 FudgePtr, MachinePointerInfo::getConstantPool(),
11232 MVT::f32, false, false, false, 4);
11233 // Extend everything to 80 bits to force it to be done on x87.
11234 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11235 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11238 std::pair<SDValue,SDValue>
11239 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11240 bool IsSigned, bool IsReplace) const {
11243 EVT DstTy = Op.getValueType();
11245 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11246 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11250 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11251 DstTy.getSimpleVT() >= MVT::i16 &&
11252 "Unknown FP_TO_INT to lower!");
11254 // These are really Legal.
11255 if (DstTy == MVT::i32 &&
11256 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11257 return std::make_pair(SDValue(), SDValue());
11258 if (Subtarget->is64Bit() &&
11259 DstTy == MVT::i64 &&
11260 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11261 return std::make_pair(SDValue(), SDValue());
11263 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11264 // stack slot, or into the FTOL runtime function.
11265 MachineFunction &MF = DAG.getMachineFunction();
11266 unsigned MemSize = DstTy.getSizeInBits()/8;
11267 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11268 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11271 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11272 Opc = X86ISD::WIN_FTOL;
11274 switch (DstTy.getSimpleVT().SimpleTy) {
11275 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11276 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11277 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11278 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11281 SDValue Chain = DAG.getEntryNode();
11282 SDValue Value = Op.getOperand(0);
11283 EVT TheVT = Op.getOperand(0).getValueType();
11284 // FIXME This causes a redundant load/store if the SSE-class value is already
11285 // in memory, such as if it is on the callstack.
11286 if (isScalarFPTypeInSSEReg(TheVT)) {
11287 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11288 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11289 MachinePointerInfo::getFixedStack(SSFI),
11291 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11293 Chain, StackSlot, DAG.getValueType(TheVT)
11296 MachineMemOperand *MMO =
11297 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11298 MachineMemOperand::MOLoad, MemSize, MemSize);
11299 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11300 Chain = Value.getValue(1);
11301 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11302 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11305 MachineMemOperand *MMO =
11306 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11307 MachineMemOperand::MOStore, MemSize, MemSize);
11309 if (Opc != X86ISD::WIN_FTOL) {
11310 // Build the FP_TO_INT*_IN_MEM
11311 SDValue Ops[] = { Chain, Value, StackSlot };
11312 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11314 return std::make_pair(FIST, StackSlot);
11316 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11317 DAG.getVTList(MVT::Other, MVT::Glue),
11319 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11320 MVT::i32, ftol.getValue(1));
11321 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11322 MVT::i32, eax.getValue(2));
11323 SDValue Ops[] = { eax, edx };
11324 SDValue pair = IsReplace
11325 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11326 : DAG.getMergeValues(Ops, DL);
11327 return std::make_pair(pair, SDValue());
11331 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11332 const X86Subtarget *Subtarget) {
11333 MVT VT = Op->getSimpleValueType(0);
11334 SDValue In = Op->getOperand(0);
11335 MVT InVT = In.getSimpleValueType();
11338 // Optimize vectors in AVX mode:
11341 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11342 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11343 // Concat upper and lower parts.
11346 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11347 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11348 // Concat upper and lower parts.
11351 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11352 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11353 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11356 if (Subtarget->hasInt256())
11357 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11359 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11360 SDValue Undef = DAG.getUNDEF(InVT);
11361 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11362 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11363 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11365 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11366 VT.getVectorNumElements()/2);
11368 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11369 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11371 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11374 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11375 SelectionDAG &DAG) {
11376 MVT VT = Op->getSimpleValueType(0);
11377 SDValue In = Op->getOperand(0);
11378 MVT InVT = In.getSimpleValueType();
11380 unsigned int NumElts = VT.getVectorNumElements();
11381 if (NumElts != 8 && NumElts != 16)
11384 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11385 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11387 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11388 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11389 // Now we have only mask extension
11390 assert(InVT.getVectorElementType() == MVT::i1);
11391 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11392 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11393 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11394 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11395 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11396 MachinePointerInfo::getConstantPool(),
11397 false, false, false, Alignment);
11399 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11400 if (VT.is512BitVector())
11402 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11405 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11406 SelectionDAG &DAG) {
11407 if (Subtarget->hasFp256()) {
11408 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11416 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11417 SelectionDAG &DAG) {
11419 MVT VT = Op.getSimpleValueType();
11420 SDValue In = Op.getOperand(0);
11421 MVT SVT = In.getSimpleValueType();
11423 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11424 return LowerZERO_EXTEND_AVX512(Op, DAG);
11426 if (Subtarget->hasFp256()) {
11427 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11432 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11433 VT.getVectorNumElements() != SVT.getVectorNumElements());
11437 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11439 MVT VT = Op.getSimpleValueType();
11440 SDValue In = Op.getOperand(0);
11441 MVT InVT = In.getSimpleValueType();
11443 if (VT == MVT::i1) {
11444 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11445 "Invalid scalar TRUNCATE operation");
11446 if (InVT == MVT::i32)
11448 if (InVT.getSizeInBits() == 64)
11449 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11450 else if (InVT.getSizeInBits() < 32)
11451 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11452 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11454 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11455 "Invalid TRUNCATE operation");
11457 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11458 if (VT.getVectorElementType().getSizeInBits() >=8)
11459 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11461 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11462 unsigned NumElts = InVT.getVectorNumElements();
11463 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11464 if (InVT.getSizeInBits() < 512) {
11465 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11466 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11470 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11471 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11472 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11473 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11474 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11475 MachinePointerInfo::getConstantPool(),
11476 false, false, false, Alignment);
11477 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11478 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11479 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11482 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11483 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11484 if (Subtarget->hasInt256()) {
11485 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11486 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11487 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11489 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11490 DAG.getIntPtrConstant(0));
11493 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11494 DAG.getIntPtrConstant(0));
11495 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11496 DAG.getIntPtrConstant(2));
11497 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11498 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11499 static const int ShufMask[] = {0, 2, 4, 6};
11500 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11503 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11504 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11505 if (Subtarget->hasInt256()) {
11506 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11508 SmallVector<SDValue,32> pshufbMask;
11509 for (unsigned i = 0; i < 2; ++i) {
11510 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11511 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11512 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11513 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11514 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11515 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11516 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11517 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11518 for (unsigned j = 0; j < 8; ++j)
11519 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11521 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11522 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11523 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11525 static const int ShufMask[] = {0, 2, -1, -1};
11526 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11528 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11529 DAG.getIntPtrConstant(0));
11530 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11533 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11534 DAG.getIntPtrConstant(0));
11536 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11537 DAG.getIntPtrConstant(4));
11539 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11540 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11542 // The PSHUFB mask:
11543 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11544 -1, -1, -1, -1, -1, -1, -1, -1};
11546 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11547 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11548 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11550 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11551 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11553 // The MOVLHPS Mask:
11554 static const int ShufMask2[] = {0, 1, 4, 5};
11555 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11556 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11559 // Handle truncation of V256 to V128 using shuffles.
11560 if (!VT.is128BitVector() || !InVT.is256BitVector())
11563 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11565 unsigned NumElems = VT.getVectorNumElements();
11566 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11568 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11569 // Prepare truncation shuffle mask
11570 for (unsigned i = 0; i != NumElems; ++i)
11571 MaskVec[i] = i * 2;
11572 SDValue V = DAG.getVectorShuffle(NVT, DL,
11573 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11574 DAG.getUNDEF(NVT), &MaskVec[0]);
11575 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11576 DAG.getIntPtrConstant(0));
11579 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11580 SelectionDAG &DAG) const {
11581 assert(!Op.getSimpleValueType().isVector());
11583 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11584 /*IsSigned=*/ true, /*IsReplace=*/ false);
11585 SDValue FIST = Vals.first, StackSlot = Vals.second;
11586 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11587 if (!FIST.getNode()) return Op;
11589 if (StackSlot.getNode())
11590 // Load the result.
11591 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11592 FIST, StackSlot, MachinePointerInfo(),
11593 false, false, false, 0);
11595 // The node is the result.
11599 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11600 SelectionDAG &DAG) const {
11601 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11602 /*IsSigned=*/ false, /*IsReplace=*/ false);
11603 SDValue FIST = Vals.first, StackSlot = Vals.second;
11604 assert(FIST.getNode() && "Unexpected failure");
11606 if (StackSlot.getNode())
11607 // Load the result.
11608 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11609 FIST, StackSlot, MachinePointerInfo(),
11610 false, false, false, 0);
11612 // The node is the result.
11616 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11618 MVT VT = Op.getSimpleValueType();
11619 SDValue In = Op.getOperand(0);
11620 MVT SVT = In.getSimpleValueType();
11622 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11624 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11625 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11626 In, DAG.getUNDEF(SVT)));
11629 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11630 LLVMContext *Context = DAG.getContext();
11632 MVT VT = Op.getSimpleValueType();
11634 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11635 if (VT.isVector()) {
11636 EltVT = VT.getVectorElementType();
11637 NumElts = VT.getVectorNumElements();
11640 if (EltVT == MVT::f64)
11641 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11642 APInt(64, ~(1ULL << 63))));
11644 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11645 APInt(32, ~(1U << 31))));
11646 C = ConstantVector::getSplat(NumElts, C);
11647 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11648 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11649 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11650 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11651 MachinePointerInfo::getConstantPool(),
11652 false, false, false, Alignment);
11653 if (VT.isVector()) {
11654 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11655 return DAG.getNode(ISD::BITCAST, dl, VT,
11656 DAG.getNode(ISD::AND, dl, ANDVT,
11657 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11659 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11661 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11664 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11665 LLVMContext *Context = DAG.getContext();
11667 MVT VT = Op.getSimpleValueType();
11669 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11670 if (VT.isVector()) {
11671 EltVT = VT.getVectorElementType();
11672 NumElts = VT.getVectorNumElements();
11675 if (EltVT == MVT::f64)
11676 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11677 APInt(64, 1ULL << 63)));
11679 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11680 APInt(32, 1U << 31)));
11681 C = ConstantVector::getSplat(NumElts, C);
11682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11683 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11684 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11685 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11686 MachinePointerInfo::getConstantPool(),
11687 false, false, false, Alignment);
11688 if (VT.isVector()) {
11689 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11690 return DAG.getNode(ISD::BITCAST, dl, VT,
11691 DAG.getNode(ISD::XOR, dl, XORVT,
11692 DAG.getNode(ISD::BITCAST, dl, XORVT,
11694 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11697 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11700 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11702 LLVMContext *Context = DAG.getContext();
11703 SDValue Op0 = Op.getOperand(0);
11704 SDValue Op1 = Op.getOperand(1);
11706 MVT VT = Op.getSimpleValueType();
11707 MVT SrcVT = Op1.getSimpleValueType();
11709 // If second operand is smaller, extend it first.
11710 if (SrcVT.bitsLT(VT)) {
11711 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
11714 // And if it is bigger, shrink it first.
11715 if (SrcVT.bitsGT(VT)) {
11716 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
11720 // At this point the operands and the result should have the same
11721 // type, and that won't be f80 since that is not custom lowered.
11723 // First get the sign bit of second operand.
11724 SmallVector<Constant*,4> CV;
11725 if (SrcVT == MVT::f64) {
11726 const fltSemantics &Sem = APFloat::IEEEdouble;
11727 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
11728 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11730 const fltSemantics &Sem = APFloat::IEEEsingle;
11731 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
11732 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11733 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11734 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11736 Constant *C = ConstantVector::get(CV);
11737 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11738 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
11739 MachinePointerInfo::getConstantPool(),
11740 false, false, false, 16);
11741 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
11743 // Shift sign bit right or left if the two operands have different types.
11744 if (SrcVT.bitsGT(VT)) {
11745 // Op0 is MVT::f32, Op1 is MVT::f64.
11746 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
11747 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
11748 DAG.getConstant(32, MVT::i32));
11749 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11750 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
11751 DAG.getIntPtrConstant(0));
11754 // Clear first operand sign bit.
11756 if (VT == MVT::f64) {
11757 const fltSemantics &Sem = APFloat::IEEEdouble;
11758 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11759 APInt(64, ~(1ULL << 63)))));
11760 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11762 const fltSemantics &Sem = APFloat::IEEEsingle;
11763 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11764 APInt(32, ~(1U << 31)))));
11765 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11766 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11767 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11769 C = ConstantVector::get(CV);
11770 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11771 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11772 MachinePointerInfo::getConstantPool(),
11773 false, false, false, 16);
11774 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
11776 // Or the value with the sign bit.
11777 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
11780 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
11781 SDValue N0 = Op.getOperand(0);
11783 MVT VT = Op.getSimpleValueType();
11785 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
11786 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
11787 DAG.getConstant(1, VT));
11788 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
11791 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
11793 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
11794 SelectionDAG &DAG) {
11795 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
11797 if (!Subtarget->hasSSE41())
11800 if (!Op->hasOneUse())
11803 SDNode *N = Op.getNode();
11806 SmallVector<SDValue, 8> Opnds;
11807 DenseMap<SDValue, unsigned> VecInMap;
11808 SmallVector<SDValue, 8> VecIns;
11809 EVT VT = MVT::Other;
11811 // Recognize a special case where a vector is casted into wide integer to
11813 Opnds.push_back(N->getOperand(0));
11814 Opnds.push_back(N->getOperand(1));
11816 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
11817 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
11818 // BFS traverse all OR'd operands.
11819 if (I->getOpcode() == ISD::OR) {
11820 Opnds.push_back(I->getOperand(0));
11821 Opnds.push_back(I->getOperand(1));
11822 // Re-evaluate the number of nodes to be traversed.
11823 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11827 // Quit if a non-EXTRACT_VECTOR_ELT
11828 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11831 // Quit if without a constant index.
11832 SDValue Idx = I->getOperand(1);
11833 if (!isa<ConstantSDNode>(Idx))
11836 SDValue ExtractedFromVec = I->getOperand(0);
11837 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
11838 if (M == VecInMap.end()) {
11839 VT = ExtractedFromVec.getValueType();
11840 // Quit if not 128/256-bit vector.
11841 if (!VT.is128BitVector() && !VT.is256BitVector())
11843 // Quit if not the same type.
11844 if (VecInMap.begin() != VecInMap.end() &&
11845 VT != VecInMap.begin()->first.getValueType())
11847 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
11848 VecIns.push_back(ExtractedFromVec);
11850 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
11853 assert((VT.is128BitVector() || VT.is256BitVector()) &&
11854 "Not extracted from 128-/256-bit vector.");
11856 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
11858 for (DenseMap<SDValue, unsigned>::const_iterator
11859 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
11860 // Quit if not all elements are used.
11861 if (I->second != FullMask)
11865 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11867 // Cast all vectors into TestVT for PTEST.
11868 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
11869 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
11871 // If more than one full vectors are evaluated, OR them first before PTEST.
11872 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
11873 // Each iteration will OR 2 nodes and append the result until there is only
11874 // 1 node left, i.e. the final OR'd value of all vectors.
11875 SDValue LHS = VecIns[Slot];
11876 SDValue RHS = VecIns[Slot + 1];
11877 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11880 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
11881 VecIns.back(), VecIns.back());
11884 /// \brief return true if \c Op has a use that doesn't just read flags.
11885 static bool hasNonFlagsUse(SDValue Op) {
11886 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
11888 SDNode *User = *UI;
11889 unsigned UOpNo = UI.getOperandNo();
11890 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
11891 // Look pass truncate.
11892 UOpNo = User->use_begin().getOperandNo();
11893 User = *User->use_begin();
11896 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11897 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
11903 /// Emit nodes that will be selected as "test Op0,Op0", or something
11905 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
11906 SelectionDAG &DAG) const {
11907 if (Op.getValueType() == MVT::i1)
11908 // KORTEST instruction should be selected
11909 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11910 DAG.getConstant(0, Op.getValueType()));
11912 // CF and OF aren't always set the way we want. Determine which
11913 // of these we need.
11914 bool NeedCF = false;
11915 bool NeedOF = false;
11918 case X86::COND_A: case X86::COND_AE:
11919 case X86::COND_B: case X86::COND_BE:
11922 case X86::COND_G: case X86::COND_GE:
11923 case X86::COND_L: case X86::COND_LE:
11924 case X86::COND_O: case X86::COND_NO: {
11925 // Check if we really need to set the
11926 // Overflow flag. If NoSignedWrap is present
11927 // that is not actually needed.
11928 switch (Op->getOpcode()) {
11933 const BinaryWithFlagsSDNode *BinNode =
11934 cast<BinaryWithFlagsSDNode>(Op.getNode());
11935 if (BinNode->hasNoSignedWrap())
11945 // See if we can use the EFLAGS value from the operand instead of
11946 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
11947 // we prove that the arithmetic won't overflow, we can't use OF or CF.
11948 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
11949 // Emit a CMP with 0, which is the TEST pattern.
11950 //if (Op.getValueType() == MVT::i1)
11951 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
11952 // DAG.getConstant(0, MVT::i1));
11953 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11954 DAG.getConstant(0, Op.getValueType()));
11956 unsigned Opcode = 0;
11957 unsigned NumOperands = 0;
11959 // Truncate operations may prevent the merge of the SETCC instruction
11960 // and the arithmetic instruction before it. Attempt to truncate the operands
11961 // of the arithmetic instruction and use a reduced bit-width instruction.
11962 bool NeedTruncation = false;
11963 SDValue ArithOp = Op;
11964 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
11965 SDValue Arith = Op->getOperand(0);
11966 // Both the trunc and the arithmetic op need to have one user each.
11967 if (Arith->hasOneUse())
11968 switch (Arith.getOpcode()) {
11975 NeedTruncation = true;
11981 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
11982 // which may be the result of a CAST. We use the variable 'Op', which is the
11983 // non-casted variable when we check for possible users.
11984 switch (ArithOp.getOpcode()) {
11986 // Due to an isel shortcoming, be conservative if this add is likely to be
11987 // selected as part of a load-modify-store instruction. When the root node
11988 // in a match is a store, isel doesn't know how to remap non-chain non-flag
11989 // uses of other nodes in the match, such as the ADD in this case. This
11990 // leads to the ADD being left around and reselected, with the result being
11991 // two adds in the output. Alas, even if none our users are stores, that
11992 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
11993 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
11994 // climbing the DAG back to the root, and it doesn't seem to be worth the
11996 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11997 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11998 if (UI->getOpcode() != ISD::CopyToReg &&
11999 UI->getOpcode() != ISD::SETCC &&
12000 UI->getOpcode() != ISD::STORE)
12003 if (ConstantSDNode *C =
12004 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12005 // An add of one will be selected as an INC.
12006 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12007 Opcode = X86ISD::INC;
12012 // An add of negative one (subtract of one) will be selected as a DEC.
12013 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12014 Opcode = X86ISD::DEC;
12020 // Otherwise use a regular EFLAGS-setting add.
12021 Opcode = X86ISD::ADD;
12026 // If we have a constant logical shift that's only used in a comparison
12027 // against zero turn it into an equivalent AND. This allows turning it into
12028 // a TEST instruction later.
12029 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12030 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12031 EVT VT = Op.getValueType();
12032 unsigned BitWidth = VT.getSizeInBits();
12033 unsigned ShAmt = Op->getConstantOperandVal(1);
12034 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12036 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12037 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12038 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12039 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12041 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12042 DAG.getConstant(Mask, VT));
12043 DAG.ReplaceAllUsesWith(Op, New);
12049 // If the primary and result isn't used, don't bother using X86ISD::AND,
12050 // because a TEST instruction will be better.
12051 if (!hasNonFlagsUse(Op))
12057 // Due to the ISEL shortcoming noted above, be conservative if this op is
12058 // likely to be selected as part of a load-modify-store instruction.
12059 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12060 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12061 if (UI->getOpcode() == ISD::STORE)
12064 // Otherwise use a regular EFLAGS-setting instruction.
12065 switch (ArithOp.getOpcode()) {
12066 default: llvm_unreachable("unexpected operator!");
12067 case ISD::SUB: Opcode = X86ISD::SUB; break;
12068 case ISD::XOR: Opcode = X86ISD::XOR; break;
12069 case ISD::AND: Opcode = X86ISD::AND; break;
12071 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12072 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12073 if (EFLAGS.getNode())
12076 Opcode = X86ISD::OR;
12090 return SDValue(Op.getNode(), 1);
12096 // If we found that truncation is beneficial, perform the truncation and
12098 if (NeedTruncation) {
12099 EVT VT = Op.getValueType();
12100 SDValue WideVal = Op->getOperand(0);
12101 EVT WideVT = WideVal.getValueType();
12102 unsigned ConvertedOp = 0;
12103 // Use a target machine opcode to prevent further DAGCombine
12104 // optimizations that may separate the arithmetic operations
12105 // from the setcc node.
12106 switch (WideVal.getOpcode()) {
12108 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12109 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12110 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12111 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12112 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12117 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12118 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12119 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12120 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12126 // Emit a CMP with 0, which is the TEST pattern.
12127 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12128 DAG.getConstant(0, Op.getValueType()));
12130 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12131 SmallVector<SDValue, 4> Ops;
12132 for (unsigned i = 0; i != NumOperands; ++i)
12133 Ops.push_back(Op.getOperand(i));
12135 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12136 DAG.ReplaceAllUsesWith(Op, New);
12137 return SDValue(New.getNode(), 1);
12140 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12142 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12143 SDLoc dl, SelectionDAG &DAG) const {
12144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12145 if (C->getAPIntValue() == 0)
12146 return EmitTest(Op0, X86CC, dl, DAG);
12148 if (Op0.getValueType() == MVT::i1)
12149 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12152 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12153 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12154 // Do the comparison at i32 if it's smaller, besides the Atom case.
12155 // This avoids subregister aliasing issues. Keep the smaller reference
12156 // if we're optimizing for size, however, as that'll allow better folding
12157 // of memory operations.
12158 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12159 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12160 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12161 !Subtarget->isAtom()) {
12162 unsigned ExtendOp =
12163 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12164 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12165 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12167 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12168 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12169 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12171 return SDValue(Sub.getNode(), 1);
12173 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12176 /// Convert a comparison if required by the subtarget.
12177 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12178 SelectionDAG &DAG) const {
12179 // If the subtarget does not support the FUCOMI instruction, floating-point
12180 // comparisons have to be converted.
12181 if (Subtarget->hasCMov() ||
12182 Cmp.getOpcode() != X86ISD::CMP ||
12183 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12184 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12187 // The instruction selector will select an FUCOM instruction instead of
12188 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12189 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12190 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12192 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12193 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12194 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12195 DAG.getConstant(8, MVT::i8));
12196 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12197 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12200 static bool isAllOnes(SDValue V) {
12201 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12202 return C && C->isAllOnesValue();
12205 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12206 /// if it's possible.
12207 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12208 SDLoc dl, SelectionDAG &DAG) const {
12209 SDValue Op0 = And.getOperand(0);
12210 SDValue Op1 = And.getOperand(1);
12211 if (Op0.getOpcode() == ISD::TRUNCATE)
12212 Op0 = Op0.getOperand(0);
12213 if (Op1.getOpcode() == ISD::TRUNCATE)
12214 Op1 = Op1.getOperand(0);
12217 if (Op1.getOpcode() == ISD::SHL)
12218 std::swap(Op0, Op1);
12219 if (Op0.getOpcode() == ISD::SHL) {
12220 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12221 if (And00C->getZExtValue() == 1) {
12222 // If we looked past a truncate, check that it's only truncating away
12224 unsigned BitWidth = Op0.getValueSizeInBits();
12225 unsigned AndBitWidth = And.getValueSizeInBits();
12226 if (BitWidth > AndBitWidth) {
12228 DAG.computeKnownBits(Op0, Zeros, Ones);
12229 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12233 RHS = Op0.getOperand(1);
12235 } else if (Op1.getOpcode() == ISD::Constant) {
12236 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12237 uint64_t AndRHSVal = AndRHS->getZExtValue();
12238 SDValue AndLHS = Op0;
12240 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12241 LHS = AndLHS.getOperand(0);
12242 RHS = AndLHS.getOperand(1);
12245 // Use BT if the immediate can't be encoded in a TEST instruction.
12246 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12248 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12252 if (LHS.getNode()) {
12253 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12254 // instruction. Since the shift amount is in-range-or-undefined, we know
12255 // that doing a bittest on the i32 value is ok. We extend to i32 because
12256 // the encoding for the i16 version is larger than the i32 version.
12257 // Also promote i16 to i32 for performance / code size reason.
12258 if (LHS.getValueType() == MVT::i8 ||
12259 LHS.getValueType() == MVT::i16)
12260 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12262 // If the operand types disagree, extend the shift amount to match. Since
12263 // BT ignores high bits (like shifts) we can use anyextend.
12264 if (LHS.getValueType() != RHS.getValueType())
12265 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12267 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12268 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12269 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12270 DAG.getConstant(Cond, MVT::i8), BT);
12276 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12278 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12283 // SSE Condition code mapping:
12292 switch (SetCCOpcode) {
12293 default: llvm_unreachable("Unexpected SETCC condition");
12295 case ISD::SETEQ: SSECC = 0; break;
12297 case ISD::SETGT: Swap = true; // Fallthrough
12299 case ISD::SETOLT: SSECC = 1; break;
12301 case ISD::SETGE: Swap = true; // Fallthrough
12303 case ISD::SETOLE: SSECC = 2; break;
12304 case ISD::SETUO: SSECC = 3; break;
12306 case ISD::SETNE: SSECC = 4; break;
12307 case ISD::SETULE: Swap = true; // Fallthrough
12308 case ISD::SETUGE: SSECC = 5; break;
12309 case ISD::SETULT: Swap = true; // Fallthrough
12310 case ISD::SETUGT: SSECC = 6; break;
12311 case ISD::SETO: SSECC = 7; break;
12313 case ISD::SETONE: SSECC = 8; break;
12316 std::swap(Op0, Op1);
12321 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12322 // ones, and then concatenate the result back.
12323 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12324 MVT VT = Op.getSimpleValueType();
12326 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12327 "Unsupported value type for operation");
12329 unsigned NumElems = VT.getVectorNumElements();
12331 SDValue CC = Op.getOperand(2);
12333 // Extract the LHS vectors
12334 SDValue LHS = Op.getOperand(0);
12335 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12336 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12338 // Extract the RHS vectors
12339 SDValue RHS = Op.getOperand(1);
12340 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12341 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12343 // Issue the operation on the smaller types and concatenate the result back
12344 MVT EltVT = VT.getVectorElementType();
12345 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12346 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12347 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12348 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12351 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12352 const X86Subtarget *Subtarget) {
12353 SDValue Op0 = Op.getOperand(0);
12354 SDValue Op1 = Op.getOperand(1);
12355 SDValue CC = Op.getOperand(2);
12356 MVT VT = Op.getSimpleValueType();
12359 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12360 Op.getValueType().getScalarType() == MVT::i1 &&
12361 "Cannot set masked compare for this operation");
12363 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12365 bool Unsigned = false;
12368 switch (SetCCOpcode) {
12369 default: llvm_unreachable("Unexpected SETCC condition");
12370 case ISD::SETNE: SSECC = 4; break;
12371 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12372 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12373 case ISD::SETLT: Swap = true; //fall-through
12374 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12375 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12376 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12377 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12378 case ISD::SETULE: Unsigned = true; //fall-through
12379 case ISD::SETLE: SSECC = 2; break;
12383 std::swap(Op0, Op1);
12385 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12386 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12387 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12388 DAG.getConstant(SSECC, MVT::i8));
12391 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12392 /// operand \p Op1. If non-trivial (for example because it's not constant)
12393 /// return an empty value.
12394 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12396 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12400 MVT VT = Op1.getSimpleValueType();
12401 MVT EVT = VT.getVectorElementType();
12402 unsigned n = VT.getVectorNumElements();
12403 SmallVector<SDValue, 8> ULTOp1;
12405 for (unsigned i = 0; i < n; ++i) {
12406 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12407 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12410 // Avoid underflow.
12411 APInt Val = Elt->getAPIntValue();
12415 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12418 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12421 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12422 SelectionDAG &DAG) {
12423 SDValue Op0 = Op.getOperand(0);
12424 SDValue Op1 = Op.getOperand(1);
12425 SDValue CC = Op.getOperand(2);
12426 MVT VT = Op.getSimpleValueType();
12427 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12428 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12433 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12434 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12437 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12438 unsigned Opc = X86ISD::CMPP;
12439 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12440 assert(VT.getVectorNumElements() <= 16);
12441 Opc = X86ISD::CMPM;
12443 // In the two special cases we can't handle, emit two comparisons.
12446 unsigned CombineOpc;
12447 if (SetCCOpcode == ISD::SETUEQ) {
12448 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12450 assert(SetCCOpcode == ISD::SETONE);
12451 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12454 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12455 DAG.getConstant(CC0, MVT::i8));
12456 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12457 DAG.getConstant(CC1, MVT::i8));
12458 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12460 // Handle all other FP comparisons here.
12461 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12462 DAG.getConstant(SSECC, MVT::i8));
12465 // Break 256-bit integer vector compare into smaller ones.
12466 if (VT.is256BitVector() && !Subtarget->hasInt256())
12467 return Lower256IntVSETCC(Op, DAG);
12469 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12470 EVT OpVT = Op1.getValueType();
12471 if (Subtarget->hasAVX512()) {
12472 if (Op1.getValueType().is512BitVector() ||
12473 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12474 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12476 // In AVX-512 architecture setcc returns mask with i1 elements,
12477 // But there is no compare instruction for i8 and i16 elements.
12478 // We are not talking about 512-bit operands in this case, these
12479 // types are illegal.
12481 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12482 OpVT.getVectorElementType().getSizeInBits() >= 8))
12483 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12484 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12487 // We are handling one of the integer comparisons here. Since SSE only has
12488 // GT and EQ comparisons for integer, swapping operands and multiple
12489 // operations may be required for some comparisons.
12491 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12492 bool Subus = false;
12494 switch (SetCCOpcode) {
12495 default: llvm_unreachable("Unexpected SETCC condition");
12496 case ISD::SETNE: Invert = true;
12497 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12498 case ISD::SETLT: Swap = true;
12499 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12500 case ISD::SETGE: Swap = true;
12501 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12502 Invert = true; break;
12503 case ISD::SETULT: Swap = true;
12504 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12505 FlipSigns = true; break;
12506 case ISD::SETUGE: Swap = true;
12507 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12508 FlipSigns = true; Invert = true; break;
12511 // Special case: Use min/max operations for SETULE/SETUGE
12512 MVT VET = VT.getVectorElementType();
12514 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12515 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12518 switch (SetCCOpcode) {
12520 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12521 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12524 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12527 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12528 if (!MinMax && hasSubus) {
12529 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12531 // t = psubus Op0, Op1
12532 // pcmpeq t, <0..0>
12533 switch (SetCCOpcode) {
12535 case ISD::SETULT: {
12536 // If the comparison is against a constant we can turn this into a
12537 // setule. With psubus, setule does not require a swap. This is
12538 // beneficial because the constant in the register is no longer
12539 // destructed as the destination so it can be hoisted out of a loop.
12540 // Only do this pre-AVX since vpcmp* is no longer destructive.
12541 if (Subtarget->hasAVX())
12543 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12544 if (ULEOp1.getNode()) {
12546 Subus = true; Invert = false; Swap = false;
12550 // Psubus is better than flip-sign because it requires no inversion.
12551 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12552 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12556 Opc = X86ISD::SUBUS;
12562 std::swap(Op0, Op1);
12564 // Check that the operation in question is available (most are plain SSE2,
12565 // but PCMPGTQ and PCMPEQQ have different requirements).
12566 if (VT == MVT::v2i64) {
12567 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12568 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12570 // First cast everything to the right type.
12571 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12572 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12574 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12575 // bits of the inputs before performing those operations. The lower
12576 // compare is always unsigned.
12579 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12581 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12582 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12583 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12584 Sign, Zero, Sign, Zero);
12586 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12587 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12589 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12590 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12591 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12593 // Create masks for only the low parts/high parts of the 64 bit integers.
12594 static const int MaskHi[] = { 1, 1, 3, 3 };
12595 static const int MaskLo[] = { 0, 0, 2, 2 };
12596 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12597 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12598 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12600 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12601 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12604 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12606 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12609 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12610 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12611 // pcmpeqd + pshufd + pand.
12612 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12614 // First cast everything to the right type.
12615 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12616 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12619 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12621 // Make sure the lower and upper halves are both all-ones.
12622 static const int Mask[] = { 1, 0, 3, 2 };
12623 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12624 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12627 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12629 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12633 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12634 // bits of the inputs before performing those operations.
12636 EVT EltVT = VT.getVectorElementType();
12637 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12638 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12639 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12642 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12644 // If the logical-not of the result is required, perform that now.
12646 Result = DAG.getNOT(dl, Result, VT);
12649 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12652 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12653 getZeroVector(VT, Subtarget, DAG, dl));
12658 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12660 MVT VT = Op.getSimpleValueType();
12662 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12664 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12665 && "SetCC type must be 8-bit or 1-bit integer");
12666 SDValue Op0 = Op.getOperand(0);
12667 SDValue Op1 = Op.getOperand(1);
12669 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12671 // Optimize to BT if possible.
12672 // Lower (X & (1 << N)) == 0 to BT(X, N).
12673 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12674 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12675 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12676 Op1.getOpcode() == ISD::Constant &&
12677 cast<ConstantSDNode>(Op1)->isNullValue() &&
12678 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12679 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12680 if (NewSetCC.getNode())
12684 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12686 if (Op1.getOpcode() == ISD::Constant &&
12687 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12688 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12689 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12691 // If the input is a setcc, then reuse the input setcc or use a new one with
12692 // the inverted condition.
12693 if (Op0.getOpcode() == X86ISD::SETCC) {
12694 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12695 bool Invert = (CC == ISD::SETNE) ^
12696 cast<ConstantSDNode>(Op1)->isNullValue();
12700 CCode = X86::GetOppositeBranchCondition(CCode);
12701 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12702 DAG.getConstant(CCode, MVT::i8),
12703 Op0.getOperand(1));
12705 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12709 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12710 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12711 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12713 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12714 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12717 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12718 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12719 if (X86CC == X86::COND_INVALID)
12722 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12723 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12724 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12725 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12727 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12731 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
12732 static bool isX86LogicalCmp(SDValue Op) {
12733 unsigned Opc = Op.getNode()->getOpcode();
12734 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
12735 Opc == X86ISD::SAHF)
12737 if (Op.getResNo() == 1 &&
12738 (Opc == X86ISD::ADD ||
12739 Opc == X86ISD::SUB ||
12740 Opc == X86ISD::ADC ||
12741 Opc == X86ISD::SBB ||
12742 Opc == X86ISD::SMUL ||
12743 Opc == X86ISD::UMUL ||
12744 Opc == X86ISD::INC ||
12745 Opc == X86ISD::DEC ||
12746 Opc == X86ISD::OR ||
12747 Opc == X86ISD::XOR ||
12748 Opc == X86ISD::AND))
12751 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
12757 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
12758 if (V.getOpcode() != ISD::TRUNCATE)
12761 SDValue VOp0 = V.getOperand(0);
12762 unsigned InBits = VOp0.getValueSizeInBits();
12763 unsigned Bits = V.getValueSizeInBits();
12764 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
12767 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
12768 bool addTest = true;
12769 SDValue Cond = Op.getOperand(0);
12770 SDValue Op1 = Op.getOperand(1);
12771 SDValue Op2 = Op.getOperand(2);
12773 EVT VT = Op1.getValueType();
12776 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12777 // are available. Otherwise fp cmovs get lowered into a less efficient branch
12778 // sequence later on.
12779 if (Cond.getOpcode() == ISD::SETCC &&
12780 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12781 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12782 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12783 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12784 int SSECC = translateX86FSETCC(
12785 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12788 if (Subtarget->hasAVX512()) {
12789 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12790 DAG.getConstant(SSECC, MVT::i8));
12791 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12793 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12794 DAG.getConstant(SSECC, MVT::i8));
12795 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12796 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12797 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12801 if (Cond.getOpcode() == ISD::SETCC) {
12802 SDValue NewCond = LowerSETCC(Cond, DAG);
12803 if (NewCond.getNode())
12807 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12808 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12809 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12810 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12811 if (Cond.getOpcode() == X86ISD::SETCC &&
12812 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12813 isZero(Cond.getOperand(1).getOperand(1))) {
12814 SDValue Cmp = Cond.getOperand(1);
12816 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12818 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12819 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12820 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12822 SDValue CmpOp0 = Cmp.getOperand(0);
12823 // Apply further optimizations for special cases
12824 // (select (x != 0), -1, 0) -> neg & sbb
12825 // (select (x == 0), 0, -1) -> neg & sbb
12826 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12827 if (YC->isNullValue() &&
12828 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12829 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12830 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12831 DAG.getConstant(0, CmpOp0.getValueType()),
12833 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12834 DAG.getConstant(X86::COND_B, MVT::i8),
12835 SDValue(Neg.getNode(), 1));
12839 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12840 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12841 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12843 SDValue Res = // Res = 0 or -1.
12844 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12845 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12847 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12848 Res = DAG.getNOT(DL, Res, Res.getValueType());
12850 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12851 if (!N2C || !N2C->isNullValue())
12852 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12857 // Look past (and (setcc_carry (cmp ...)), 1).
12858 if (Cond.getOpcode() == ISD::AND &&
12859 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12860 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12861 if (C && C->getAPIntValue() == 1)
12862 Cond = Cond.getOperand(0);
12865 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12866 // setting operand in place of the X86ISD::SETCC.
12867 unsigned CondOpcode = Cond.getOpcode();
12868 if (CondOpcode == X86ISD::SETCC ||
12869 CondOpcode == X86ISD::SETCC_CARRY) {
12870 CC = Cond.getOperand(0);
12872 SDValue Cmp = Cond.getOperand(1);
12873 unsigned Opc = Cmp.getOpcode();
12874 MVT VT = Op.getSimpleValueType();
12876 bool IllegalFPCMov = false;
12877 if (VT.isFloatingPoint() && !VT.isVector() &&
12878 !isScalarFPTypeInSSEReg(VT)) // FPStack?
12879 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12881 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12882 Opc == X86ISD::BT) { // FIXME
12886 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12887 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12888 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12889 Cond.getOperand(0).getValueType() != MVT::i8)) {
12890 SDValue LHS = Cond.getOperand(0);
12891 SDValue RHS = Cond.getOperand(1);
12892 unsigned X86Opcode;
12895 switch (CondOpcode) {
12896 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12897 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12898 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12899 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12900 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12901 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12902 default: llvm_unreachable("unexpected overflowing operator");
12904 if (CondOpcode == ISD::UMULO)
12905 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12908 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12910 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12912 if (CondOpcode == ISD::UMULO)
12913 Cond = X86Op.getValue(2);
12915 Cond = X86Op.getValue(1);
12917 CC = DAG.getConstant(X86Cond, MVT::i8);
12922 // Look pass the truncate if the high bits are known zero.
12923 if (isTruncWithZeroHighBitsInput(Cond, DAG))
12924 Cond = Cond.getOperand(0);
12926 // We know the result of AND is compared against zero. Try to match
12928 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
12929 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
12930 if (NewSetCC.getNode()) {
12931 CC = NewSetCC.getOperand(0);
12932 Cond = NewSetCC.getOperand(1);
12939 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12940 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
12943 // a < b ? -1 : 0 -> RES = ~setcc_carry
12944 // a < b ? 0 : -1 -> RES = setcc_carry
12945 // a >= b ? -1 : 0 -> RES = setcc_carry
12946 // a >= b ? 0 : -1 -> RES = ~setcc_carry
12947 if (Cond.getOpcode() == X86ISD::SUB) {
12948 Cond = ConvertCmpIfNecessary(Cond, DAG);
12949 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
12951 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
12952 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
12953 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12954 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
12955 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
12956 return DAG.getNOT(DL, Res, Res.getValueType());
12961 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
12962 // widen the cmov and push the truncate through. This avoids introducing a new
12963 // branch during isel and doesn't add any extensions.
12964 if (Op.getValueType() == MVT::i8 &&
12965 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
12966 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
12967 if (T1.getValueType() == T2.getValueType() &&
12968 // Blacklist CopyFromReg to avoid partial register stalls.
12969 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
12970 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
12971 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
12972 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
12976 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
12977 // condition is true.
12978 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
12979 SDValue Ops[] = { Op2, Op1, CC, Cond };
12980 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
12983 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
12984 MVT VT = Op->getSimpleValueType(0);
12985 SDValue In = Op->getOperand(0);
12986 MVT InVT = In.getSimpleValueType();
12989 unsigned int NumElts = VT.getVectorNumElements();
12990 if (NumElts != 8 && NumElts != 16)
12993 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12994 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12996 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12997 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12999 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13000 Constant *C = ConstantInt::get(*DAG.getContext(),
13001 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13003 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13004 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13005 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13006 MachinePointerInfo::getConstantPool(),
13007 false, false, false, Alignment);
13008 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13009 if (VT.is512BitVector())
13011 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13014 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13015 SelectionDAG &DAG) {
13016 MVT VT = Op->getSimpleValueType(0);
13017 SDValue In = Op->getOperand(0);
13018 MVT InVT = In.getSimpleValueType();
13021 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13022 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13024 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13025 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13026 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13029 if (Subtarget->hasInt256())
13030 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13032 // Optimize vectors in AVX mode
13033 // Sign extend v8i16 to v8i32 and
13036 // Divide input vector into two parts
13037 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13038 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13039 // concat the vectors to original VT
13041 unsigned NumElems = InVT.getVectorNumElements();
13042 SDValue Undef = DAG.getUNDEF(InVT);
13044 SmallVector<int,8> ShufMask1(NumElems, -1);
13045 for (unsigned i = 0; i != NumElems/2; ++i)
13048 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13050 SmallVector<int,8> ShufMask2(NumElems, -1);
13051 for (unsigned i = 0; i != NumElems/2; ++i)
13052 ShufMask2[i] = i + NumElems/2;
13054 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13056 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13057 VT.getVectorNumElements()/2);
13059 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13060 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13062 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13065 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13066 // may emit an illegal shuffle but the expansion is still better than scalar
13067 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13068 // we'll emit a shuffle and a arithmetic shift.
13069 // TODO: It is possible to support ZExt by zeroing the undef values during
13070 // the shuffle phase or after the shuffle.
13071 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13072 SelectionDAG &DAG) {
13073 MVT RegVT = Op.getSimpleValueType();
13074 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13075 assert(RegVT.isInteger() &&
13076 "We only custom lower integer vector sext loads.");
13078 // Nothing useful we can do without SSE2 shuffles.
13079 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13081 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13083 EVT MemVT = Ld->getMemoryVT();
13084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13085 unsigned RegSz = RegVT.getSizeInBits();
13087 ISD::LoadExtType Ext = Ld->getExtensionType();
13089 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13090 && "Only anyext and sext are currently implemented.");
13091 assert(MemVT != RegVT && "Cannot extend to the same type");
13092 assert(MemVT.isVector() && "Must load a vector from memory");
13094 unsigned NumElems = RegVT.getVectorNumElements();
13095 unsigned MemSz = MemVT.getSizeInBits();
13096 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13098 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13099 // The only way in which we have a legal 256-bit vector result but not the
13100 // integer 256-bit operations needed to directly lower a sextload is if we
13101 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13102 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13103 // correctly legalized. We do this late to allow the canonical form of
13104 // sextload to persist throughout the rest of the DAG combiner -- it wants
13105 // to fold together any extensions it can, and so will fuse a sign_extend
13106 // of an sextload into an sextload targeting a wider value.
13108 if (MemSz == 128) {
13109 // Just switch this to a normal load.
13110 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13111 "it must be a legal 128-bit vector "
13113 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13114 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13115 Ld->isInvariant(), Ld->getAlignment());
13117 assert(MemSz < 128 &&
13118 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13119 // Do an sext load to a 128-bit vector type. We want to use the same
13120 // number of elements, but elements half as wide. This will end up being
13121 // recursively lowered by this routine, but will succeed as we definitely
13122 // have all the necessary features if we're using AVX1.
13124 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13125 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13127 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13128 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13129 Ld->isNonTemporal(), Ld->isInvariant(),
13130 Ld->getAlignment());
13133 // Replace chain users with the new chain.
13134 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13135 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13137 // Finally, do a normal sign-extend to the desired register.
13138 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13141 // All sizes must be a power of two.
13142 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13143 "Non-power-of-two elements are not custom lowered!");
13145 // Attempt to load the original value using scalar loads.
13146 // Find the largest scalar type that divides the total loaded size.
13147 MVT SclrLoadTy = MVT::i8;
13148 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13149 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13150 MVT Tp = (MVT::SimpleValueType)tp;
13151 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13156 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13157 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13159 SclrLoadTy = MVT::f64;
13161 // Calculate the number of scalar loads that we need to perform
13162 // in order to load our vector from memory.
13163 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13165 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13166 "Can only lower sext loads with a single scalar load!");
13168 unsigned loadRegZize = RegSz;
13169 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13172 // Represent our vector as a sequence of elements which are the
13173 // largest scalar that we can load.
13174 EVT LoadUnitVecVT = EVT::getVectorVT(
13175 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13177 // Represent the data using the same element type that is stored in
13178 // memory. In practice, we ''widen'' MemVT.
13180 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13181 loadRegZize / MemVT.getScalarType().getSizeInBits());
13183 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13184 "Invalid vector type");
13186 // We can't shuffle using an illegal type.
13187 assert(TLI.isTypeLegal(WideVecVT) &&
13188 "We only lower types that form legal widened vector types");
13190 SmallVector<SDValue, 8> Chains;
13191 SDValue Ptr = Ld->getBasePtr();
13192 SDValue Increment =
13193 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13194 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13196 for (unsigned i = 0; i < NumLoads; ++i) {
13197 // Perform a single load.
13198 SDValue ScalarLoad =
13199 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13200 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13201 Ld->getAlignment());
13202 Chains.push_back(ScalarLoad.getValue(1));
13203 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13204 // another round of DAGCombining.
13206 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13208 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13209 ScalarLoad, DAG.getIntPtrConstant(i));
13211 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13214 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13216 // Bitcast the loaded value to a vector of the original element type, in
13217 // the size of the target vector type.
13218 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13219 unsigned SizeRatio = RegSz / MemSz;
13221 if (Ext == ISD::SEXTLOAD) {
13222 // If we have SSE4.1 we can directly emit a VSEXT node.
13223 if (Subtarget->hasSSE41()) {
13224 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13225 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13229 // Otherwise we'll shuffle the small elements in the high bits of the
13230 // larger type and perform an arithmetic shift. If the shift is not legal
13231 // it's better to scalarize.
13232 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13233 "We can't implement an sext load without a arithmetic right shift!");
13235 // Redistribute the loaded elements into the different locations.
13236 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13237 for (unsigned i = 0; i != NumElems; ++i)
13238 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13240 SDValue Shuff = DAG.getVectorShuffle(
13241 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13243 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13245 // Build the arithmetic shift.
13246 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13247 MemVT.getVectorElementType().getSizeInBits();
13249 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13251 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13255 // Redistribute the loaded elements into the different locations.
13256 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13257 for (unsigned i = 0; i != NumElems; ++i)
13258 ShuffleVec[i * SizeRatio] = i;
13260 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13261 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13263 // Bitcast to the requested type.
13264 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13265 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13269 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13270 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13271 // from the AND / OR.
13272 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13273 Opc = Op.getOpcode();
13274 if (Opc != ISD::OR && Opc != ISD::AND)
13276 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13277 Op.getOperand(0).hasOneUse() &&
13278 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13279 Op.getOperand(1).hasOneUse());
13282 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13283 // 1 and that the SETCC node has a single use.
13284 static bool isXor1OfSetCC(SDValue Op) {
13285 if (Op.getOpcode() != ISD::XOR)
13287 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13288 if (N1C && N1C->getAPIntValue() == 1) {
13289 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13290 Op.getOperand(0).hasOneUse();
13295 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13296 bool addTest = true;
13297 SDValue Chain = Op.getOperand(0);
13298 SDValue Cond = Op.getOperand(1);
13299 SDValue Dest = Op.getOperand(2);
13302 bool Inverted = false;
13304 if (Cond.getOpcode() == ISD::SETCC) {
13305 // Check for setcc([su]{add,sub,mul}o == 0).
13306 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13307 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13308 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13309 Cond.getOperand(0).getResNo() == 1 &&
13310 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13311 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13312 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13313 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13314 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13315 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13317 Cond = Cond.getOperand(0);
13319 SDValue NewCond = LowerSETCC(Cond, DAG);
13320 if (NewCond.getNode())
13325 // FIXME: LowerXALUO doesn't handle these!!
13326 else if (Cond.getOpcode() == X86ISD::ADD ||
13327 Cond.getOpcode() == X86ISD::SUB ||
13328 Cond.getOpcode() == X86ISD::SMUL ||
13329 Cond.getOpcode() == X86ISD::UMUL)
13330 Cond = LowerXALUO(Cond, DAG);
13333 // Look pass (and (setcc_carry (cmp ...)), 1).
13334 if (Cond.getOpcode() == ISD::AND &&
13335 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13336 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13337 if (C && C->getAPIntValue() == 1)
13338 Cond = Cond.getOperand(0);
13341 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13342 // setting operand in place of the X86ISD::SETCC.
13343 unsigned CondOpcode = Cond.getOpcode();
13344 if (CondOpcode == X86ISD::SETCC ||
13345 CondOpcode == X86ISD::SETCC_CARRY) {
13346 CC = Cond.getOperand(0);
13348 SDValue Cmp = Cond.getOperand(1);
13349 unsigned Opc = Cmp.getOpcode();
13350 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13351 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13355 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13359 // These can only come from an arithmetic instruction with overflow,
13360 // e.g. SADDO, UADDO.
13361 Cond = Cond.getNode()->getOperand(1);
13367 CondOpcode = Cond.getOpcode();
13368 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13369 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13370 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13371 Cond.getOperand(0).getValueType() != MVT::i8)) {
13372 SDValue LHS = Cond.getOperand(0);
13373 SDValue RHS = Cond.getOperand(1);
13374 unsigned X86Opcode;
13377 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13378 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13380 switch (CondOpcode) {
13381 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13385 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13388 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13389 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13391 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13393 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13396 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13397 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13398 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13399 default: llvm_unreachable("unexpected overflowing operator");
13402 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13403 if (CondOpcode == ISD::UMULO)
13404 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13407 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13409 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13411 if (CondOpcode == ISD::UMULO)
13412 Cond = X86Op.getValue(2);
13414 Cond = X86Op.getValue(1);
13416 CC = DAG.getConstant(X86Cond, MVT::i8);
13420 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13421 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13422 if (CondOpc == ISD::OR) {
13423 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13424 // two branches instead of an explicit OR instruction with a
13426 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13427 isX86LogicalCmp(Cmp)) {
13428 CC = Cond.getOperand(0).getOperand(0);
13429 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13430 Chain, Dest, CC, Cmp);
13431 CC = Cond.getOperand(1).getOperand(0);
13435 } else { // ISD::AND
13436 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13437 // two branches instead of an explicit AND instruction with a
13438 // separate test. However, we only do this if this block doesn't
13439 // have a fall-through edge, because this requires an explicit
13440 // jmp when the condition is false.
13441 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13442 isX86LogicalCmp(Cmp) &&
13443 Op.getNode()->hasOneUse()) {
13444 X86::CondCode CCode =
13445 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13446 CCode = X86::GetOppositeBranchCondition(CCode);
13447 CC = DAG.getConstant(CCode, MVT::i8);
13448 SDNode *User = *Op.getNode()->use_begin();
13449 // Look for an unconditional branch following this conditional branch.
13450 // We need this because we need to reverse the successors in order
13451 // to implement FCMP_OEQ.
13452 if (User->getOpcode() == ISD::BR) {
13453 SDValue FalseBB = User->getOperand(1);
13455 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13456 assert(NewBR == User);
13460 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13461 Chain, Dest, CC, Cmp);
13462 X86::CondCode CCode =
13463 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13464 CCode = X86::GetOppositeBranchCondition(CCode);
13465 CC = DAG.getConstant(CCode, MVT::i8);
13471 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13472 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13473 // It should be transformed during dag combiner except when the condition
13474 // is set by a arithmetics with overflow node.
13475 X86::CondCode CCode =
13476 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13477 CCode = X86::GetOppositeBranchCondition(CCode);
13478 CC = DAG.getConstant(CCode, MVT::i8);
13479 Cond = Cond.getOperand(0).getOperand(1);
13481 } else if (Cond.getOpcode() == ISD::SETCC &&
13482 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13483 // For FCMP_OEQ, we can emit
13484 // two branches instead of an explicit AND instruction with a
13485 // separate test. However, we only do this if this block doesn't
13486 // have a fall-through edge, because this requires an explicit
13487 // jmp when the condition is false.
13488 if (Op.getNode()->hasOneUse()) {
13489 SDNode *User = *Op.getNode()->use_begin();
13490 // Look for an unconditional branch following this conditional branch.
13491 // We need this because we need to reverse the successors in order
13492 // to implement FCMP_OEQ.
13493 if (User->getOpcode() == ISD::BR) {
13494 SDValue FalseBB = User->getOperand(1);
13496 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13497 assert(NewBR == User);
13501 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13502 Cond.getOperand(0), Cond.getOperand(1));
13503 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13504 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13505 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13506 Chain, Dest, CC, Cmp);
13507 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13512 } else if (Cond.getOpcode() == ISD::SETCC &&
13513 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13514 // For FCMP_UNE, we can emit
13515 // two branches instead of an explicit AND instruction with a
13516 // separate test. However, we only do this if this block doesn't
13517 // have a fall-through edge, because this requires an explicit
13518 // jmp when the condition is false.
13519 if (Op.getNode()->hasOneUse()) {
13520 SDNode *User = *Op.getNode()->use_begin();
13521 // Look for an unconditional branch following this conditional branch.
13522 // We need this because we need to reverse the successors in order
13523 // to implement FCMP_UNE.
13524 if (User->getOpcode() == ISD::BR) {
13525 SDValue FalseBB = User->getOperand(1);
13527 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13528 assert(NewBR == User);
13531 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13532 Cond.getOperand(0), Cond.getOperand(1));
13533 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13534 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13535 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13536 Chain, Dest, CC, Cmp);
13537 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13547 // Look pass the truncate if the high bits are known zero.
13548 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13549 Cond = Cond.getOperand(0);
13551 // We know the result of AND is compared against zero. Try to match
13553 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13554 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13555 if (NewSetCC.getNode()) {
13556 CC = NewSetCC.getOperand(0);
13557 Cond = NewSetCC.getOperand(1);
13564 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13565 CC = DAG.getConstant(X86Cond, MVT::i8);
13566 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13568 Cond = ConvertCmpIfNecessary(Cond, DAG);
13569 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13570 Chain, Dest, CC, Cond);
13573 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13574 // Calls to _alloca is needed to probe the stack when allocating more than 4k
13575 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13576 // that the guard pages used by the OS virtual memory manager are allocated in
13577 // correct sequence.
13579 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13580 SelectionDAG &DAG) const {
13581 MachineFunction &MF = DAG.getMachineFunction();
13582 bool SplitStack = MF.shouldSplitStack();
13583 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13588 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13589 SDNode* Node = Op.getNode();
13591 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13592 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13593 " not tell us which reg is the stack pointer!");
13594 EVT VT = Node->getValueType(0);
13595 SDValue Tmp1 = SDValue(Node, 0);
13596 SDValue Tmp2 = SDValue(Node, 1);
13597 SDValue Tmp3 = Node->getOperand(2);
13598 SDValue Chain = Tmp1.getOperand(0);
13600 // Chain the dynamic stack allocation so that it doesn't modify the stack
13601 // pointer when other instructions are using the stack.
13602 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13605 SDValue Size = Tmp2.getOperand(1);
13606 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13607 Chain = SP.getValue(1);
13608 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13609 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
13610 unsigned StackAlign = TFI.getStackAlignment();
13611 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13612 if (Align > StackAlign)
13613 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13614 DAG.getConstant(-(uint64_t)Align, VT));
13615 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13617 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13618 DAG.getIntPtrConstant(0, true), SDValue(),
13621 SDValue Ops[2] = { Tmp1, Tmp2 };
13622 return DAG.getMergeValues(Ops, dl);
13626 SDValue Chain = Op.getOperand(0);
13627 SDValue Size = Op.getOperand(1);
13628 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13629 EVT VT = Op.getNode()->getValueType(0);
13631 bool Is64Bit = Subtarget->is64Bit();
13632 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13635 MachineRegisterInfo &MRI = MF.getRegInfo();
13638 // The 64 bit implementation of segmented stacks needs to clobber both r10
13639 // r11. This makes it impossible to use it along with nested parameters.
13640 const Function *F = MF.getFunction();
13642 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13644 if (I->hasNestAttr())
13645 report_fatal_error("Cannot use segmented stacks with functions that "
13646 "have nested arguments.");
13649 const TargetRegisterClass *AddrRegClass =
13650 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13651 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13652 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13653 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13654 DAG.getRegister(Vreg, SPTy));
13655 SDValue Ops1[2] = { Value, Chain };
13656 return DAG.getMergeValues(Ops1, dl);
13659 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13661 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13662 Flag = Chain.getValue(1);
13663 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13665 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13667 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
13668 DAG.getSubtarget().getRegisterInfo());
13669 unsigned SPReg = RegInfo->getStackRegister();
13670 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13671 Chain = SP.getValue(1);
13674 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13675 DAG.getConstant(-(uint64_t)Align, VT));
13676 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13679 SDValue Ops1[2] = { SP, Chain };
13680 return DAG.getMergeValues(Ops1, dl);
13684 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13685 MachineFunction &MF = DAG.getMachineFunction();
13686 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13688 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13691 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13692 // vastart just stores the address of the VarArgsFrameIndex slot into the
13693 // memory location argument.
13694 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13696 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13697 MachinePointerInfo(SV), false, false, 0);
13701 // gp_offset (0 - 6 * 8)
13702 // fp_offset (48 - 48 + 8 * 16)
13703 // overflow_arg_area (point to parameters coming in memory).
13705 SmallVector<SDValue, 8> MemOps;
13706 SDValue FIN = Op.getOperand(1);
13708 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13709 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13711 FIN, MachinePointerInfo(SV), false, false, 0);
13712 MemOps.push_back(Store);
13715 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13716 FIN, DAG.getIntPtrConstant(4));
13717 Store = DAG.getStore(Op.getOperand(0), DL,
13718 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13720 FIN, MachinePointerInfo(SV, 4), false, false, 0);
13721 MemOps.push_back(Store);
13723 // Store ptr to overflow_arg_area
13724 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13725 FIN, DAG.getIntPtrConstant(4));
13726 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13728 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13729 MachinePointerInfo(SV, 8),
13731 MemOps.push_back(Store);
13733 // Store ptr to reg_save_area.
13734 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13735 FIN, DAG.getIntPtrConstant(8));
13736 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13738 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13739 MachinePointerInfo(SV, 16), false, false, 0);
13740 MemOps.push_back(Store);
13741 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13744 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
13745 assert(Subtarget->is64Bit() &&
13746 "LowerVAARG only handles 64-bit va_arg!");
13747 assert((Subtarget->isTargetLinux() ||
13748 Subtarget->isTargetDarwin()) &&
13749 "Unhandled target in LowerVAARG");
13750 assert(Op.getNode()->getNumOperands() == 4);
13751 SDValue Chain = Op.getOperand(0);
13752 SDValue SrcPtr = Op.getOperand(1);
13753 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13754 unsigned Align = Op.getConstantOperandVal(3);
13757 EVT ArgVT = Op.getNode()->getValueType(0);
13758 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13759 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13762 // Decide which area this value should be read from.
13763 // TODO: Implement the AMD64 ABI in its entirety. This simple
13764 // selection mechanism works only for the basic types.
13765 if (ArgVT == MVT::f80) {
13766 llvm_unreachable("va_arg for f80 not yet implemented");
13767 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13768 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13769 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13770 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13772 llvm_unreachable("Unhandled argument type in LowerVAARG");
13775 if (ArgMode == 2) {
13776 // Sanity Check: Make sure using fp_offset makes sense.
13777 assert(!DAG.getTarget().Options.UseSoftFloat &&
13778 !(DAG.getMachineFunction()
13779 .getFunction()->getAttributes()
13780 .hasAttribute(AttributeSet::FunctionIndex,
13781 Attribute::NoImplicitFloat)) &&
13782 Subtarget->hasSSE1());
13785 // Insert VAARG_64 node into the DAG
13786 // VAARG_64 returns two values: Variable Argument Address, Chain
13787 SmallVector<SDValue, 11> InstOps;
13788 InstOps.push_back(Chain);
13789 InstOps.push_back(SrcPtr);
13790 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13791 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13792 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13793 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13794 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13795 VTs, InstOps, MVT::i64,
13796 MachinePointerInfo(SV),
13798 /*Volatile=*/false,
13800 /*WriteMem=*/true);
13801 Chain = VAARG.getValue(1);
13803 // Load the next argument and return it
13804 return DAG.getLoad(ArgVT, dl,
13807 MachinePointerInfo(),
13808 false, false, false, 0);
13811 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
13812 SelectionDAG &DAG) {
13813 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
13814 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
13815 SDValue Chain = Op.getOperand(0);
13816 SDValue DstPtr = Op.getOperand(1);
13817 SDValue SrcPtr = Op.getOperand(2);
13818 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
13819 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
13822 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
13823 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
13825 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
13828 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
13829 // amount is a constant. Takes immediate version of shift as input.
13830 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
13831 SDValue SrcOp, uint64_t ShiftAmt,
13832 SelectionDAG &DAG) {
13833 MVT ElementType = VT.getVectorElementType();
13835 // Fold this packed shift into its first operand if ShiftAmt is 0.
13839 // Check for ShiftAmt >= element width
13840 if (ShiftAmt >= ElementType.getSizeInBits()) {
13841 if (Opc == X86ISD::VSRAI)
13842 ShiftAmt = ElementType.getSizeInBits() - 1;
13844 return DAG.getConstant(0, VT);
13847 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
13848 && "Unknown target vector shift-by-constant node");
13850 // Fold this packed vector shift into a build vector if SrcOp is a
13851 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
13852 if (VT == SrcOp.getSimpleValueType() &&
13853 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
13854 SmallVector<SDValue, 8> Elts;
13855 unsigned NumElts = SrcOp->getNumOperands();
13856 ConstantSDNode *ND;
13859 default: llvm_unreachable(nullptr);
13860 case X86ISD::VSHLI:
13861 for (unsigned i=0; i!=NumElts; ++i) {
13862 SDValue CurrentOp = SrcOp->getOperand(i);
13863 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13864 Elts.push_back(CurrentOp);
13867 ND = cast<ConstantSDNode>(CurrentOp);
13868 const APInt &C = ND->getAPIntValue();
13869 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
13872 case X86ISD::VSRLI:
13873 for (unsigned i=0; i!=NumElts; ++i) {
13874 SDValue CurrentOp = SrcOp->getOperand(i);
13875 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13876 Elts.push_back(CurrentOp);
13879 ND = cast<ConstantSDNode>(CurrentOp);
13880 const APInt &C = ND->getAPIntValue();
13881 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
13884 case X86ISD::VSRAI:
13885 for (unsigned i=0; i!=NumElts; ++i) {
13886 SDValue CurrentOp = SrcOp->getOperand(i);
13887 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13888 Elts.push_back(CurrentOp);
13891 ND = cast<ConstantSDNode>(CurrentOp);
13892 const APInt &C = ND->getAPIntValue();
13893 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
13898 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13901 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
13904 // getTargetVShiftNode - Handle vector element shifts where the shift amount
13905 // may or may not be a constant. Takes immediate version of shift as input.
13906 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
13907 SDValue SrcOp, SDValue ShAmt,
13908 SelectionDAG &DAG) {
13909 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
13911 // Catch shift-by-constant.
13912 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
13913 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
13914 CShAmt->getZExtValue(), DAG);
13916 // Change opcode to non-immediate version
13918 default: llvm_unreachable("Unknown target vector shift node");
13919 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
13920 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
13921 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
13924 // Need to build a vector containing shift amount
13925 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
13928 ShOps[1] = DAG.getConstant(0, MVT::i32);
13929 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
13930 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
13932 // The return type has to be a 128-bit type with the same element
13933 // type as the input type.
13934 MVT EltVT = VT.getVectorElementType();
13935 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
13937 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
13938 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
13941 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
13943 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13945 default: return SDValue(); // Don't custom lower most intrinsics.
13946 // Comparison intrinsics.
13947 case Intrinsic::x86_sse_comieq_ss:
13948 case Intrinsic::x86_sse_comilt_ss:
13949 case Intrinsic::x86_sse_comile_ss:
13950 case Intrinsic::x86_sse_comigt_ss:
13951 case Intrinsic::x86_sse_comige_ss:
13952 case Intrinsic::x86_sse_comineq_ss:
13953 case Intrinsic::x86_sse_ucomieq_ss:
13954 case Intrinsic::x86_sse_ucomilt_ss:
13955 case Intrinsic::x86_sse_ucomile_ss:
13956 case Intrinsic::x86_sse_ucomigt_ss:
13957 case Intrinsic::x86_sse_ucomige_ss:
13958 case Intrinsic::x86_sse_ucomineq_ss:
13959 case Intrinsic::x86_sse2_comieq_sd:
13960 case Intrinsic::x86_sse2_comilt_sd:
13961 case Intrinsic::x86_sse2_comile_sd:
13962 case Intrinsic::x86_sse2_comigt_sd:
13963 case Intrinsic::x86_sse2_comige_sd:
13964 case Intrinsic::x86_sse2_comineq_sd:
13965 case Intrinsic::x86_sse2_ucomieq_sd:
13966 case Intrinsic::x86_sse2_ucomilt_sd:
13967 case Intrinsic::x86_sse2_ucomile_sd:
13968 case Intrinsic::x86_sse2_ucomigt_sd:
13969 case Intrinsic::x86_sse2_ucomige_sd:
13970 case Intrinsic::x86_sse2_ucomineq_sd: {
13974 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13975 case Intrinsic::x86_sse_comieq_ss:
13976 case Intrinsic::x86_sse2_comieq_sd:
13977 Opc = X86ISD::COMI;
13980 case Intrinsic::x86_sse_comilt_ss:
13981 case Intrinsic::x86_sse2_comilt_sd:
13982 Opc = X86ISD::COMI;
13985 case Intrinsic::x86_sse_comile_ss:
13986 case Intrinsic::x86_sse2_comile_sd:
13987 Opc = X86ISD::COMI;
13990 case Intrinsic::x86_sse_comigt_ss:
13991 case Intrinsic::x86_sse2_comigt_sd:
13992 Opc = X86ISD::COMI;
13995 case Intrinsic::x86_sse_comige_ss:
13996 case Intrinsic::x86_sse2_comige_sd:
13997 Opc = X86ISD::COMI;
14000 case Intrinsic::x86_sse_comineq_ss:
14001 case Intrinsic::x86_sse2_comineq_sd:
14002 Opc = X86ISD::COMI;
14005 case Intrinsic::x86_sse_ucomieq_ss:
14006 case Intrinsic::x86_sse2_ucomieq_sd:
14007 Opc = X86ISD::UCOMI;
14010 case Intrinsic::x86_sse_ucomilt_ss:
14011 case Intrinsic::x86_sse2_ucomilt_sd:
14012 Opc = X86ISD::UCOMI;
14015 case Intrinsic::x86_sse_ucomile_ss:
14016 case Intrinsic::x86_sse2_ucomile_sd:
14017 Opc = X86ISD::UCOMI;
14020 case Intrinsic::x86_sse_ucomigt_ss:
14021 case Intrinsic::x86_sse2_ucomigt_sd:
14022 Opc = X86ISD::UCOMI;
14025 case Intrinsic::x86_sse_ucomige_ss:
14026 case Intrinsic::x86_sse2_ucomige_sd:
14027 Opc = X86ISD::UCOMI;
14030 case Intrinsic::x86_sse_ucomineq_ss:
14031 case Intrinsic::x86_sse2_ucomineq_sd:
14032 Opc = X86ISD::UCOMI;
14037 SDValue LHS = Op.getOperand(1);
14038 SDValue RHS = Op.getOperand(2);
14039 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14040 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14041 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
14042 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14043 DAG.getConstant(X86CC, MVT::i8), Cond);
14044 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14047 // Arithmetic intrinsics.
14048 case Intrinsic::x86_sse2_pmulu_dq:
14049 case Intrinsic::x86_avx2_pmulu_dq:
14050 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14051 Op.getOperand(1), Op.getOperand(2));
14053 case Intrinsic::x86_sse41_pmuldq:
14054 case Intrinsic::x86_avx2_pmul_dq:
14055 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14056 Op.getOperand(1), Op.getOperand(2));
14058 case Intrinsic::x86_sse2_pmulhu_w:
14059 case Intrinsic::x86_avx2_pmulhu_w:
14060 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14061 Op.getOperand(1), Op.getOperand(2));
14063 case Intrinsic::x86_sse2_pmulh_w:
14064 case Intrinsic::x86_avx2_pmulh_w:
14065 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14066 Op.getOperand(1), Op.getOperand(2));
14068 // SSE2/AVX2 sub with unsigned saturation intrinsics
14069 case Intrinsic::x86_sse2_psubus_b:
14070 case Intrinsic::x86_sse2_psubus_w:
14071 case Intrinsic::x86_avx2_psubus_b:
14072 case Intrinsic::x86_avx2_psubus_w:
14073 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
14074 Op.getOperand(1), Op.getOperand(2));
14076 // SSE3/AVX horizontal add/sub intrinsics
14077 case Intrinsic::x86_sse3_hadd_ps:
14078 case Intrinsic::x86_sse3_hadd_pd:
14079 case Intrinsic::x86_avx_hadd_ps_256:
14080 case Intrinsic::x86_avx_hadd_pd_256:
14081 case Intrinsic::x86_sse3_hsub_ps:
14082 case Intrinsic::x86_sse3_hsub_pd:
14083 case Intrinsic::x86_avx_hsub_ps_256:
14084 case Intrinsic::x86_avx_hsub_pd_256:
14085 case Intrinsic::x86_ssse3_phadd_w_128:
14086 case Intrinsic::x86_ssse3_phadd_d_128:
14087 case Intrinsic::x86_avx2_phadd_w:
14088 case Intrinsic::x86_avx2_phadd_d:
14089 case Intrinsic::x86_ssse3_phsub_w_128:
14090 case Intrinsic::x86_ssse3_phsub_d_128:
14091 case Intrinsic::x86_avx2_phsub_w:
14092 case Intrinsic::x86_avx2_phsub_d: {
14095 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14096 case Intrinsic::x86_sse3_hadd_ps:
14097 case Intrinsic::x86_sse3_hadd_pd:
14098 case Intrinsic::x86_avx_hadd_ps_256:
14099 case Intrinsic::x86_avx_hadd_pd_256:
14100 Opcode = X86ISD::FHADD;
14102 case Intrinsic::x86_sse3_hsub_ps:
14103 case Intrinsic::x86_sse3_hsub_pd:
14104 case Intrinsic::x86_avx_hsub_ps_256:
14105 case Intrinsic::x86_avx_hsub_pd_256:
14106 Opcode = X86ISD::FHSUB;
14108 case Intrinsic::x86_ssse3_phadd_w_128:
14109 case Intrinsic::x86_ssse3_phadd_d_128:
14110 case Intrinsic::x86_avx2_phadd_w:
14111 case Intrinsic::x86_avx2_phadd_d:
14112 Opcode = X86ISD::HADD;
14114 case Intrinsic::x86_ssse3_phsub_w_128:
14115 case Intrinsic::x86_ssse3_phsub_d_128:
14116 case Intrinsic::x86_avx2_phsub_w:
14117 case Intrinsic::x86_avx2_phsub_d:
14118 Opcode = X86ISD::HSUB;
14121 return DAG.getNode(Opcode, dl, Op.getValueType(),
14122 Op.getOperand(1), Op.getOperand(2));
14125 // SSE2/SSE41/AVX2 integer max/min intrinsics.
14126 case Intrinsic::x86_sse2_pmaxu_b:
14127 case Intrinsic::x86_sse41_pmaxuw:
14128 case Intrinsic::x86_sse41_pmaxud:
14129 case Intrinsic::x86_avx2_pmaxu_b:
14130 case Intrinsic::x86_avx2_pmaxu_w:
14131 case Intrinsic::x86_avx2_pmaxu_d:
14132 case Intrinsic::x86_sse2_pminu_b:
14133 case Intrinsic::x86_sse41_pminuw:
14134 case Intrinsic::x86_sse41_pminud:
14135 case Intrinsic::x86_avx2_pminu_b:
14136 case Intrinsic::x86_avx2_pminu_w:
14137 case Intrinsic::x86_avx2_pminu_d:
14138 case Intrinsic::x86_sse41_pmaxsb:
14139 case Intrinsic::x86_sse2_pmaxs_w:
14140 case Intrinsic::x86_sse41_pmaxsd:
14141 case Intrinsic::x86_avx2_pmaxs_b:
14142 case Intrinsic::x86_avx2_pmaxs_w:
14143 case Intrinsic::x86_avx2_pmaxs_d:
14144 case Intrinsic::x86_sse41_pminsb:
14145 case Intrinsic::x86_sse2_pmins_w:
14146 case Intrinsic::x86_sse41_pminsd:
14147 case Intrinsic::x86_avx2_pmins_b:
14148 case Intrinsic::x86_avx2_pmins_w:
14149 case Intrinsic::x86_avx2_pmins_d: {
14152 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14153 case Intrinsic::x86_sse2_pmaxu_b:
14154 case Intrinsic::x86_sse41_pmaxuw:
14155 case Intrinsic::x86_sse41_pmaxud:
14156 case Intrinsic::x86_avx2_pmaxu_b:
14157 case Intrinsic::x86_avx2_pmaxu_w:
14158 case Intrinsic::x86_avx2_pmaxu_d:
14159 Opcode = X86ISD::UMAX;
14161 case Intrinsic::x86_sse2_pminu_b:
14162 case Intrinsic::x86_sse41_pminuw:
14163 case Intrinsic::x86_sse41_pminud:
14164 case Intrinsic::x86_avx2_pminu_b:
14165 case Intrinsic::x86_avx2_pminu_w:
14166 case Intrinsic::x86_avx2_pminu_d:
14167 Opcode = X86ISD::UMIN;
14169 case Intrinsic::x86_sse41_pmaxsb:
14170 case Intrinsic::x86_sse2_pmaxs_w:
14171 case Intrinsic::x86_sse41_pmaxsd:
14172 case Intrinsic::x86_avx2_pmaxs_b:
14173 case Intrinsic::x86_avx2_pmaxs_w:
14174 case Intrinsic::x86_avx2_pmaxs_d:
14175 Opcode = X86ISD::SMAX;
14177 case Intrinsic::x86_sse41_pminsb:
14178 case Intrinsic::x86_sse2_pmins_w:
14179 case Intrinsic::x86_sse41_pminsd:
14180 case Intrinsic::x86_avx2_pmins_b:
14181 case Intrinsic::x86_avx2_pmins_w:
14182 case Intrinsic::x86_avx2_pmins_d:
14183 Opcode = X86ISD::SMIN;
14186 return DAG.getNode(Opcode, dl, Op.getValueType(),
14187 Op.getOperand(1), Op.getOperand(2));
14190 // SSE/SSE2/AVX floating point max/min intrinsics.
14191 case Intrinsic::x86_sse_max_ps:
14192 case Intrinsic::x86_sse2_max_pd:
14193 case Intrinsic::x86_avx_max_ps_256:
14194 case Intrinsic::x86_avx_max_pd_256:
14195 case Intrinsic::x86_sse_min_ps:
14196 case Intrinsic::x86_sse2_min_pd:
14197 case Intrinsic::x86_avx_min_ps_256:
14198 case Intrinsic::x86_avx_min_pd_256: {
14201 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14202 case Intrinsic::x86_sse_max_ps:
14203 case Intrinsic::x86_sse2_max_pd:
14204 case Intrinsic::x86_avx_max_ps_256:
14205 case Intrinsic::x86_avx_max_pd_256:
14206 Opcode = X86ISD::FMAX;
14208 case Intrinsic::x86_sse_min_ps:
14209 case Intrinsic::x86_sse2_min_pd:
14210 case Intrinsic::x86_avx_min_ps_256:
14211 case Intrinsic::x86_avx_min_pd_256:
14212 Opcode = X86ISD::FMIN;
14215 return DAG.getNode(Opcode, dl, Op.getValueType(),
14216 Op.getOperand(1), Op.getOperand(2));
14219 // AVX2 variable shift intrinsics
14220 case Intrinsic::x86_avx2_psllv_d:
14221 case Intrinsic::x86_avx2_psllv_q:
14222 case Intrinsic::x86_avx2_psllv_d_256:
14223 case Intrinsic::x86_avx2_psllv_q_256:
14224 case Intrinsic::x86_avx2_psrlv_d:
14225 case Intrinsic::x86_avx2_psrlv_q:
14226 case Intrinsic::x86_avx2_psrlv_d_256:
14227 case Intrinsic::x86_avx2_psrlv_q_256:
14228 case Intrinsic::x86_avx2_psrav_d:
14229 case Intrinsic::x86_avx2_psrav_d_256: {
14232 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14233 case Intrinsic::x86_avx2_psllv_d:
14234 case Intrinsic::x86_avx2_psllv_q:
14235 case Intrinsic::x86_avx2_psllv_d_256:
14236 case Intrinsic::x86_avx2_psllv_q_256:
14239 case Intrinsic::x86_avx2_psrlv_d:
14240 case Intrinsic::x86_avx2_psrlv_q:
14241 case Intrinsic::x86_avx2_psrlv_d_256:
14242 case Intrinsic::x86_avx2_psrlv_q_256:
14245 case Intrinsic::x86_avx2_psrav_d:
14246 case Intrinsic::x86_avx2_psrav_d_256:
14250 return DAG.getNode(Opcode, dl, Op.getValueType(),
14251 Op.getOperand(1), Op.getOperand(2));
14254 case Intrinsic::x86_sse2_packssdw_128:
14255 case Intrinsic::x86_sse2_packsswb_128:
14256 case Intrinsic::x86_avx2_packssdw:
14257 case Intrinsic::x86_avx2_packsswb:
14258 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14259 Op.getOperand(1), Op.getOperand(2));
14261 case Intrinsic::x86_sse2_packuswb_128:
14262 case Intrinsic::x86_sse41_packusdw:
14263 case Intrinsic::x86_avx2_packuswb:
14264 case Intrinsic::x86_avx2_packusdw:
14265 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14266 Op.getOperand(1), Op.getOperand(2));
14268 case Intrinsic::x86_ssse3_pshuf_b_128:
14269 case Intrinsic::x86_avx2_pshuf_b:
14270 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14271 Op.getOperand(1), Op.getOperand(2));
14273 case Intrinsic::x86_sse2_pshuf_d:
14274 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14275 Op.getOperand(1), Op.getOperand(2));
14277 case Intrinsic::x86_sse2_pshufl_w:
14278 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14279 Op.getOperand(1), Op.getOperand(2));
14281 case Intrinsic::x86_sse2_pshufh_w:
14282 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14283 Op.getOperand(1), Op.getOperand(2));
14285 case Intrinsic::x86_ssse3_psign_b_128:
14286 case Intrinsic::x86_ssse3_psign_w_128:
14287 case Intrinsic::x86_ssse3_psign_d_128:
14288 case Intrinsic::x86_avx2_psign_b:
14289 case Intrinsic::x86_avx2_psign_w:
14290 case Intrinsic::x86_avx2_psign_d:
14291 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14292 Op.getOperand(1), Op.getOperand(2));
14294 case Intrinsic::x86_sse41_insertps:
14295 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
14296 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14298 case Intrinsic::x86_avx_vperm2f128_ps_256:
14299 case Intrinsic::x86_avx_vperm2f128_pd_256:
14300 case Intrinsic::x86_avx_vperm2f128_si_256:
14301 case Intrinsic::x86_avx2_vperm2i128:
14302 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
14303 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14305 case Intrinsic::x86_avx2_permd:
14306 case Intrinsic::x86_avx2_permps:
14307 // Operands intentionally swapped. Mask is last operand to intrinsic,
14308 // but second operand for node/instruction.
14309 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14310 Op.getOperand(2), Op.getOperand(1));
14312 case Intrinsic::x86_sse_sqrt_ps:
14313 case Intrinsic::x86_sse2_sqrt_pd:
14314 case Intrinsic::x86_avx_sqrt_ps_256:
14315 case Intrinsic::x86_avx_sqrt_pd_256:
14316 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
14318 // ptest and testp intrinsics. The intrinsic these come from are designed to
14319 // return an integer value, not just an instruction so lower it to the ptest
14320 // or testp pattern and a setcc for the result.
14321 case Intrinsic::x86_sse41_ptestz:
14322 case Intrinsic::x86_sse41_ptestc:
14323 case Intrinsic::x86_sse41_ptestnzc:
14324 case Intrinsic::x86_avx_ptestz_256:
14325 case Intrinsic::x86_avx_ptestc_256:
14326 case Intrinsic::x86_avx_ptestnzc_256:
14327 case Intrinsic::x86_avx_vtestz_ps:
14328 case Intrinsic::x86_avx_vtestc_ps:
14329 case Intrinsic::x86_avx_vtestnzc_ps:
14330 case Intrinsic::x86_avx_vtestz_pd:
14331 case Intrinsic::x86_avx_vtestc_pd:
14332 case Intrinsic::x86_avx_vtestnzc_pd:
14333 case Intrinsic::x86_avx_vtestz_ps_256:
14334 case Intrinsic::x86_avx_vtestc_ps_256:
14335 case Intrinsic::x86_avx_vtestnzc_ps_256:
14336 case Intrinsic::x86_avx_vtestz_pd_256:
14337 case Intrinsic::x86_avx_vtestc_pd_256:
14338 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14339 bool IsTestPacked = false;
14342 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14343 case Intrinsic::x86_avx_vtestz_ps:
14344 case Intrinsic::x86_avx_vtestz_pd:
14345 case Intrinsic::x86_avx_vtestz_ps_256:
14346 case Intrinsic::x86_avx_vtestz_pd_256:
14347 IsTestPacked = true; // Fallthrough
14348 case Intrinsic::x86_sse41_ptestz:
14349 case Intrinsic::x86_avx_ptestz_256:
14351 X86CC = X86::COND_E;
14353 case Intrinsic::x86_avx_vtestc_ps:
14354 case Intrinsic::x86_avx_vtestc_pd:
14355 case Intrinsic::x86_avx_vtestc_ps_256:
14356 case Intrinsic::x86_avx_vtestc_pd_256:
14357 IsTestPacked = true; // Fallthrough
14358 case Intrinsic::x86_sse41_ptestc:
14359 case Intrinsic::x86_avx_ptestc_256:
14361 X86CC = X86::COND_B;
14363 case Intrinsic::x86_avx_vtestnzc_ps:
14364 case Intrinsic::x86_avx_vtestnzc_pd:
14365 case Intrinsic::x86_avx_vtestnzc_ps_256:
14366 case Intrinsic::x86_avx_vtestnzc_pd_256:
14367 IsTestPacked = true; // Fallthrough
14368 case Intrinsic::x86_sse41_ptestnzc:
14369 case Intrinsic::x86_avx_ptestnzc_256:
14371 X86CC = X86::COND_A;
14375 SDValue LHS = Op.getOperand(1);
14376 SDValue RHS = Op.getOperand(2);
14377 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14378 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14379 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14380 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14381 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14383 case Intrinsic::x86_avx512_kortestz_w:
14384 case Intrinsic::x86_avx512_kortestc_w: {
14385 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14386 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14387 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14388 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14389 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14390 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14391 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14394 // SSE/AVX shift intrinsics
14395 case Intrinsic::x86_sse2_psll_w:
14396 case Intrinsic::x86_sse2_psll_d:
14397 case Intrinsic::x86_sse2_psll_q:
14398 case Intrinsic::x86_avx2_psll_w:
14399 case Intrinsic::x86_avx2_psll_d:
14400 case Intrinsic::x86_avx2_psll_q:
14401 case Intrinsic::x86_sse2_psrl_w:
14402 case Intrinsic::x86_sse2_psrl_d:
14403 case Intrinsic::x86_sse2_psrl_q:
14404 case Intrinsic::x86_avx2_psrl_w:
14405 case Intrinsic::x86_avx2_psrl_d:
14406 case Intrinsic::x86_avx2_psrl_q:
14407 case Intrinsic::x86_sse2_psra_w:
14408 case Intrinsic::x86_sse2_psra_d:
14409 case Intrinsic::x86_avx2_psra_w:
14410 case Intrinsic::x86_avx2_psra_d: {
14413 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14414 case Intrinsic::x86_sse2_psll_w:
14415 case Intrinsic::x86_sse2_psll_d:
14416 case Intrinsic::x86_sse2_psll_q:
14417 case Intrinsic::x86_avx2_psll_w:
14418 case Intrinsic::x86_avx2_psll_d:
14419 case Intrinsic::x86_avx2_psll_q:
14420 Opcode = X86ISD::VSHL;
14422 case Intrinsic::x86_sse2_psrl_w:
14423 case Intrinsic::x86_sse2_psrl_d:
14424 case Intrinsic::x86_sse2_psrl_q:
14425 case Intrinsic::x86_avx2_psrl_w:
14426 case Intrinsic::x86_avx2_psrl_d:
14427 case Intrinsic::x86_avx2_psrl_q:
14428 Opcode = X86ISD::VSRL;
14430 case Intrinsic::x86_sse2_psra_w:
14431 case Intrinsic::x86_sse2_psra_d:
14432 case Intrinsic::x86_avx2_psra_w:
14433 case Intrinsic::x86_avx2_psra_d:
14434 Opcode = X86ISD::VSRA;
14437 return DAG.getNode(Opcode, dl, Op.getValueType(),
14438 Op.getOperand(1), Op.getOperand(2));
14441 // SSE/AVX immediate shift intrinsics
14442 case Intrinsic::x86_sse2_pslli_w:
14443 case Intrinsic::x86_sse2_pslli_d:
14444 case Intrinsic::x86_sse2_pslli_q:
14445 case Intrinsic::x86_avx2_pslli_w:
14446 case Intrinsic::x86_avx2_pslli_d:
14447 case Intrinsic::x86_avx2_pslli_q:
14448 case Intrinsic::x86_sse2_psrli_w:
14449 case Intrinsic::x86_sse2_psrli_d:
14450 case Intrinsic::x86_sse2_psrli_q:
14451 case Intrinsic::x86_avx2_psrli_w:
14452 case Intrinsic::x86_avx2_psrli_d:
14453 case Intrinsic::x86_avx2_psrli_q:
14454 case Intrinsic::x86_sse2_psrai_w:
14455 case Intrinsic::x86_sse2_psrai_d:
14456 case Intrinsic::x86_avx2_psrai_w:
14457 case Intrinsic::x86_avx2_psrai_d: {
14460 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14461 case Intrinsic::x86_sse2_pslli_w:
14462 case Intrinsic::x86_sse2_pslli_d:
14463 case Intrinsic::x86_sse2_pslli_q:
14464 case Intrinsic::x86_avx2_pslli_w:
14465 case Intrinsic::x86_avx2_pslli_d:
14466 case Intrinsic::x86_avx2_pslli_q:
14467 Opcode = X86ISD::VSHLI;
14469 case Intrinsic::x86_sse2_psrli_w:
14470 case Intrinsic::x86_sse2_psrli_d:
14471 case Intrinsic::x86_sse2_psrli_q:
14472 case Intrinsic::x86_avx2_psrli_w:
14473 case Intrinsic::x86_avx2_psrli_d:
14474 case Intrinsic::x86_avx2_psrli_q:
14475 Opcode = X86ISD::VSRLI;
14477 case Intrinsic::x86_sse2_psrai_w:
14478 case Intrinsic::x86_sse2_psrai_d:
14479 case Intrinsic::x86_avx2_psrai_w:
14480 case Intrinsic::x86_avx2_psrai_d:
14481 Opcode = X86ISD::VSRAI;
14484 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
14485 Op.getOperand(1), Op.getOperand(2), DAG);
14488 case Intrinsic::x86_sse42_pcmpistria128:
14489 case Intrinsic::x86_sse42_pcmpestria128:
14490 case Intrinsic::x86_sse42_pcmpistric128:
14491 case Intrinsic::x86_sse42_pcmpestric128:
14492 case Intrinsic::x86_sse42_pcmpistrio128:
14493 case Intrinsic::x86_sse42_pcmpestrio128:
14494 case Intrinsic::x86_sse42_pcmpistris128:
14495 case Intrinsic::x86_sse42_pcmpestris128:
14496 case Intrinsic::x86_sse42_pcmpistriz128:
14497 case Intrinsic::x86_sse42_pcmpestriz128: {
14501 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14502 case Intrinsic::x86_sse42_pcmpistria128:
14503 Opcode = X86ISD::PCMPISTRI;
14504 X86CC = X86::COND_A;
14506 case Intrinsic::x86_sse42_pcmpestria128:
14507 Opcode = X86ISD::PCMPESTRI;
14508 X86CC = X86::COND_A;
14510 case Intrinsic::x86_sse42_pcmpistric128:
14511 Opcode = X86ISD::PCMPISTRI;
14512 X86CC = X86::COND_B;
14514 case Intrinsic::x86_sse42_pcmpestric128:
14515 Opcode = X86ISD::PCMPESTRI;
14516 X86CC = X86::COND_B;
14518 case Intrinsic::x86_sse42_pcmpistrio128:
14519 Opcode = X86ISD::PCMPISTRI;
14520 X86CC = X86::COND_O;
14522 case Intrinsic::x86_sse42_pcmpestrio128:
14523 Opcode = X86ISD::PCMPESTRI;
14524 X86CC = X86::COND_O;
14526 case Intrinsic::x86_sse42_pcmpistris128:
14527 Opcode = X86ISD::PCMPISTRI;
14528 X86CC = X86::COND_S;
14530 case Intrinsic::x86_sse42_pcmpestris128:
14531 Opcode = X86ISD::PCMPESTRI;
14532 X86CC = X86::COND_S;
14534 case Intrinsic::x86_sse42_pcmpistriz128:
14535 Opcode = X86ISD::PCMPISTRI;
14536 X86CC = X86::COND_E;
14538 case Intrinsic::x86_sse42_pcmpestriz128:
14539 Opcode = X86ISD::PCMPESTRI;
14540 X86CC = X86::COND_E;
14543 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14544 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14545 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14546 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14547 DAG.getConstant(X86CC, MVT::i8),
14548 SDValue(PCMP.getNode(), 1));
14549 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14552 case Intrinsic::x86_sse42_pcmpistri128:
14553 case Intrinsic::x86_sse42_pcmpestri128: {
14555 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14556 Opcode = X86ISD::PCMPISTRI;
14558 Opcode = X86ISD::PCMPESTRI;
14560 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14561 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14562 return DAG.getNode(Opcode, dl, VTs, NewOps);
14564 case Intrinsic::x86_fma_vfmadd_ps:
14565 case Intrinsic::x86_fma_vfmadd_pd:
14566 case Intrinsic::x86_fma_vfmsub_ps:
14567 case Intrinsic::x86_fma_vfmsub_pd:
14568 case Intrinsic::x86_fma_vfnmadd_ps:
14569 case Intrinsic::x86_fma_vfnmadd_pd:
14570 case Intrinsic::x86_fma_vfnmsub_ps:
14571 case Intrinsic::x86_fma_vfnmsub_pd:
14572 case Intrinsic::x86_fma_vfmaddsub_ps:
14573 case Intrinsic::x86_fma_vfmaddsub_pd:
14574 case Intrinsic::x86_fma_vfmsubadd_ps:
14575 case Intrinsic::x86_fma_vfmsubadd_pd:
14576 case Intrinsic::x86_fma_vfmadd_ps_256:
14577 case Intrinsic::x86_fma_vfmadd_pd_256:
14578 case Intrinsic::x86_fma_vfmsub_ps_256:
14579 case Intrinsic::x86_fma_vfmsub_pd_256:
14580 case Intrinsic::x86_fma_vfnmadd_ps_256:
14581 case Intrinsic::x86_fma_vfnmadd_pd_256:
14582 case Intrinsic::x86_fma_vfnmsub_ps_256:
14583 case Intrinsic::x86_fma_vfnmsub_pd_256:
14584 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14585 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14586 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14587 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14588 case Intrinsic::x86_fma_vfmadd_ps_512:
14589 case Intrinsic::x86_fma_vfmadd_pd_512:
14590 case Intrinsic::x86_fma_vfmsub_ps_512:
14591 case Intrinsic::x86_fma_vfmsub_pd_512:
14592 case Intrinsic::x86_fma_vfnmadd_ps_512:
14593 case Intrinsic::x86_fma_vfnmadd_pd_512:
14594 case Intrinsic::x86_fma_vfnmsub_ps_512:
14595 case Intrinsic::x86_fma_vfnmsub_pd_512:
14596 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14597 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14598 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14599 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
14602 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14603 case Intrinsic::x86_fma_vfmadd_ps:
14604 case Intrinsic::x86_fma_vfmadd_pd:
14605 case Intrinsic::x86_fma_vfmadd_ps_256:
14606 case Intrinsic::x86_fma_vfmadd_pd_256:
14607 case Intrinsic::x86_fma_vfmadd_ps_512:
14608 case Intrinsic::x86_fma_vfmadd_pd_512:
14609 Opc = X86ISD::FMADD;
14611 case Intrinsic::x86_fma_vfmsub_ps:
14612 case Intrinsic::x86_fma_vfmsub_pd:
14613 case Intrinsic::x86_fma_vfmsub_ps_256:
14614 case Intrinsic::x86_fma_vfmsub_pd_256:
14615 case Intrinsic::x86_fma_vfmsub_ps_512:
14616 case Intrinsic::x86_fma_vfmsub_pd_512:
14617 Opc = X86ISD::FMSUB;
14619 case Intrinsic::x86_fma_vfnmadd_ps:
14620 case Intrinsic::x86_fma_vfnmadd_pd:
14621 case Intrinsic::x86_fma_vfnmadd_ps_256:
14622 case Intrinsic::x86_fma_vfnmadd_pd_256:
14623 case Intrinsic::x86_fma_vfnmadd_ps_512:
14624 case Intrinsic::x86_fma_vfnmadd_pd_512:
14625 Opc = X86ISD::FNMADD;
14627 case Intrinsic::x86_fma_vfnmsub_ps:
14628 case Intrinsic::x86_fma_vfnmsub_pd:
14629 case Intrinsic::x86_fma_vfnmsub_ps_256:
14630 case Intrinsic::x86_fma_vfnmsub_pd_256:
14631 case Intrinsic::x86_fma_vfnmsub_ps_512:
14632 case Intrinsic::x86_fma_vfnmsub_pd_512:
14633 Opc = X86ISD::FNMSUB;
14635 case Intrinsic::x86_fma_vfmaddsub_ps:
14636 case Intrinsic::x86_fma_vfmaddsub_pd:
14637 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14638 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14639 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14640 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14641 Opc = X86ISD::FMADDSUB;
14643 case Intrinsic::x86_fma_vfmsubadd_ps:
14644 case Intrinsic::x86_fma_vfmsubadd_pd:
14645 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14646 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14647 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14648 case Intrinsic::x86_fma_vfmsubadd_pd_512:
14649 Opc = X86ISD::FMSUBADD;
14653 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
14654 Op.getOperand(2), Op.getOperand(3));
14659 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14660 SDValue Src, SDValue Mask, SDValue Base,
14661 SDValue Index, SDValue ScaleOp, SDValue Chain,
14662 const X86Subtarget * Subtarget) {
14664 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14665 assert(C && "Invalid scale type");
14666 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14667 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14668 Index.getSimpleValueType().getVectorNumElements());
14670 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14672 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14674 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14675 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14676 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14677 SDValue Segment = DAG.getRegister(0, MVT::i32);
14678 if (Src.getOpcode() == ISD::UNDEF)
14679 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14680 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14681 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14682 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14683 return DAG.getMergeValues(RetOps, dl);
14686 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14687 SDValue Src, SDValue Mask, SDValue Base,
14688 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14690 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14691 assert(C && "Invalid scale type");
14692 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14693 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14694 SDValue Segment = DAG.getRegister(0, MVT::i32);
14695 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14696 Index.getSimpleValueType().getVectorNumElements());
14698 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14700 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14702 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14703 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14704 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14705 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14706 return SDValue(Res, 1);
14709 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14710 SDValue Mask, SDValue Base, SDValue Index,
14711 SDValue ScaleOp, SDValue Chain) {
14713 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14714 assert(C && "Invalid scale type");
14715 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14716 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14717 SDValue Segment = DAG.getRegister(0, MVT::i32);
14719 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14721 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14723 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14725 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14726 //SDVTList VTs = DAG.getVTList(MVT::Other);
14727 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14728 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14729 return SDValue(Res, 0);
14732 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14733 // read performance monitor counters (x86_rdpmc).
14734 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14735 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14736 SmallVectorImpl<SDValue> &Results) {
14737 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14738 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14741 // The ECX register is used to select the index of the performance counter
14743 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14745 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14747 // Reads the content of a 64-bit performance counter and returns it in the
14748 // registers EDX:EAX.
14749 if (Subtarget->is64Bit()) {
14750 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14751 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14754 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14755 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14758 Chain = HI.getValue(1);
14760 if (Subtarget->is64Bit()) {
14761 // The EAX register is loaded with the low-order 32 bits. The EDX register
14762 // is loaded with the supported high-order bits of the counter.
14763 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14764 DAG.getConstant(32, MVT::i8));
14765 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14766 Results.push_back(Chain);
14770 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14771 SDValue Ops[] = { LO, HI };
14772 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14773 Results.push_back(Pair);
14774 Results.push_back(Chain);
14777 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14778 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14779 // also used to custom lower READCYCLECOUNTER nodes.
14780 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14781 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14782 SmallVectorImpl<SDValue> &Results) {
14783 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14784 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14787 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14788 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14789 // and the EAX register is loaded with the low-order 32 bits.
14790 if (Subtarget->is64Bit()) {
14791 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14792 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14795 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14796 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14799 SDValue Chain = HI.getValue(1);
14801 if (Opcode == X86ISD::RDTSCP_DAG) {
14802 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14804 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14805 // the ECX register. Add 'ecx' explicitly to the chain.
14806 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14808 // Explicitly store the content of ECX at the location passed in input
14809 // to the 'rdtscp' intrinsic.
14810 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14811 MachinePointerInfo(), false, false, 0);
14814 if (Subtarget->is64Bit()) {
14815 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14816 // the EAX register is loaded with the low-order 32 bits.
14817 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14818 DAG.getConstant(32, MVT::i8));
14819 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14820 Results.push_back(Chain);
14824 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14825 SDValue Ops[] = { LO, HI };
14826 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14827 Results.push_back(Pair);
14828 Results.push_back(Chain);
14831 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14832 SelectionDAG &DAG) {
14833 SmallVector<SDValue, 2> Results;
14835 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14837 return DAG.getMergeValues(Results, DL);
14840 enum IntrinsicType {
14841 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
14844 struct IntrinsicData {
14845 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
14846 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
14847 IntrinsicType Type;
14852 std::map < unsigned, IntrinsicData> IntrMap;
14853 static void InitIntinsicsMap() {
14854 static bool Initialized = false;
14857 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14858 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14859 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14860 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14861 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
14862 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
14863 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
14864 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
14865 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
14866 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
14867 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
14868 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
14869 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
14870 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
14871 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
14872 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
14873 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
14874 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
14876 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
14877 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
14878 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
14879 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
14880 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
14881 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
14882 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
14883 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
14884 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
14885 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
14886 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
14887 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
14888 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
14889 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
14890 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
14891 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
14893 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
14894 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
14895 X86::VGATHERPF1QPSm)));
14896 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
14897 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
14898 X86::VGATHERPF1QPDm)));
14899 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
14900 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
14901 X86::VGATHERPF1DPDm)));
14902 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
14903 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
14904 X86::VGATHERPF1DPSm)));
14905 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
14906 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
14907 X86::VSCATTERPF1QPSm)));
14908 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
14909 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
14910 X86::VSCATTERPF1QPDm)));
14911 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
14912 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
14913 X86::VSCATTERPF1DPDm)));
14914 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
14915 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
14916 X86::VSCATTERPF1DPSm)));
14917 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
14918 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14919 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
14920 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14921 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
14922 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14923 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
14924 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14925 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
14926 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14927 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
14928 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14929 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
14930 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
14931 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
14932 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
14933 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
14934 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
14935 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
14936 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
14937 Initialized = true;
14940 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14941 SelectionDAG &DAG) {
14942 InitIntinsicsMap();
14943 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14944 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
14945 if (itr == IntrMap.end())
14949 IntrinsicData Intr = itr->second;
14950 switch(Intr.Type) {
14953 // Emit the node with the right value type.
14954 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14955 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
14957 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
14958 // Otherwise return the value from Rand, which is always 0, casted to i32.
14959 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
14960 DAG.getConstant(1, Op->getValueType(1)),
14961 DAG.getConstant(X86::COND_B, MVT::i32),
14962 SDValue(Result.getNode(), 1) };
14963 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14964 DAG.getVTList(Op->getValueType(1), MVT::Glue),
14967 // Return { result, isValid, chain }.
14968 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
14969 SDValue(Result.getNode(), 2));
14972 //gather(v1, mask, index, base, scale);
14973 SDValue Chain = Op.getOperand(0);
14974 SDValue Src = Op.getOperand(2);
14975 SDValue Base = Op.getOperand(3);
14976 SDValue Index = Op.getOperand(4);
14977 SDValue Mask = Op.getOperand(5);
14978 SDValue Scale = Op.getOperand(6);
14979 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
14983 //scatter(base, mask, index, v1, scale);
14984 SDValue Chain = Op.getOperand(0);
14985 SDValue Base = Op.getOperand(2);
14986 SDValue Mask = Op.getOperand(3);
14987 SDValue Index = Op.getOperand(4);
14988 SDValue Src = Op.getOperand(5);
14989 SDValue Scale = Op.getOperand(6);
14990 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
14993 SDValue Hint = Op.getOperand(6);
14995 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
14996 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
14997 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
14998 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
14999 SDValue Chain = Op.getOperand(0);
15000 SDValue Mask = Op.getOperand(2);
15001 SDValue Index = Op.getOperand(3);
15002 SDValue Base = Op.getOperand(4);
15003 SDValue Scale = Op.getOperand(5);
15004 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15006 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15008 SmallVector<SDValue, 2> Results;
15009 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
15010 return DAG.getMergeValues(Results, dl);
15012 // Read Performance Monitoring Counters.
15014 SmallVector<SDValue, 2> Results;
15015 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15016 return DAG.getMergeValues(Results, dl);
15018 // XTEST intrinsics.
15020 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15021 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
15022 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15023 DAG.getConstant(X86::COND_NE, MVT::i8),
15025 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15026 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15027 Ret, SDValue(InTrans.getNode(), 1));
15030 llvm_unreachable("Unknown Intrinsic Type");
15033 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15034 SelectionDAG &DAG) const {
15035 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15036 MFI->setReturnAddressIsTaken(true);
15038 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15041 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15043 EVT PtrVT = getPointerTy();
15046 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15047 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15048 DAG.getSubtarget().getRegisterInfo());
15049 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15050 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15051 DAG.getNode(ISD::ADD, dl, PtrVT,
15052 FrameAddr, Offset),
15053 MachinePointerInfo(), false, false, false, 0);
15056 // Just load the return address.
15057 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15058 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15059 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15062 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15063 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15064 MFI->setFrameAddressIsTaken(true);
15066 EVT VT = Op.getValueType();
15067 SDLoc dl(Op); // FIXME probably not meaningful
15068 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15069 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15070 DAG.getSubtarget().getRegisterInfo());
15071 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15072 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15073 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15074 "Invalid Frame Register!");
15075 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15077 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15078 MachinePointerInfo(),
15079 false, false, false, 0);
15083 // FIXME? Maybe this could be a TableGen attribute on some registers and
15084 // this table could be generated automatically from RegInfo.
15085 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15087 unsigned Reg = StringSwitch<unsigned>(RegName)
15088 .Case("esp", X86::ESP)
15089 .Case("rsp", X86::RSP)
15093 report_fatal_error("Invalid register name global variable");
15096 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15097 SelectionDAG &DAG) const {
15098 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15099 DAG.getSubtarget().getRegisterInfo());
15100 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15103 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15104 SDValue Chain = Op.getOperand(0);
15105 SDValue Offset = Op.getOperand(1);
15106 SDValue Handler = Op.getOperand(2);
15109 EVT PtrVT = getPointerTy();
15110 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15111 DAG.getSubtarget().getRegisterInfo());
15112 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15113 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15114 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15115 "Invalid Frame Register!");
15116 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15117 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15119 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15120 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15121 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15122 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15124 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15126 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15127 DAG.getRegister(StoreAddrReg, PtrVT));
15130 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15131 SelectionDAG &DAG) const {
15133 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15134 DAG.getVTList(MVT::i32, MVT::Other),
15135 Op.getOperand(0), Op.getOperand(1));
15138 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15139 SelectionDAG &DAG) const {
15141 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15142 Op.getOperand(0), Op.getOperand(1));
15145 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15146 return Op.getOperand(0);
15149 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15150 SelectionDAG &DAG) const {
15151 SDValue Root = Op.getOperand(0);
15152 SDValue Trmp = Op.getOperand(1); // trampoline
15153 SDValue FPtr = Op.getOperand(2); // nested function
15154 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15157 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15158 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15160 if (Subtarget->is64Bit()) {
15161 SDValue OutChains[6];
15163 // Large code-model.
15164 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15165 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15167 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15168 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15170 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15172 // Load the pointer to the nested function into R11.
15173 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15174 SDValue Addr = Trmp;
15175 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15176 Addr, MachinePointerInfo(TrmpAddr),
15179 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15180 DAG.getConstant(2, MVT::i64));
15181 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15182 MachinePointerInfo(TrmpAddr, 2),
15185 // Load the 'nest' parameter value into R10.
15186 // R10 is specified in X86CallingConv.td
15187 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15188 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15189 DAG.getConstant(10, MVT::i64));
15190 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15191 Addr, MachinePointerInfo(TrmpAddr, 10),
15194 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15195 DAG.getConstant(12, MVT::i64));
15196 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15197 MachinePointerInfo(TrmpAddr, 12),
15200 // Jump to the nested function.
15201 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15202 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15203 DAG.getConstant(20, MVT::i64));
15204 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15205 Addr, MachinePointerInfo(TrmpAddr, 20),
15208 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15209 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15210 DAG.getConstant(22, MVT::i64));
15211 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15212 MachinePointerInfo(TrmpAddr, 22),
15215 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15217 const Function *Func =
15218 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15219 CallingConv::ID CC = Func->getCallingConv();
15224 llvm_unreachable("Unsupported calling convention");
15225 case CallingConv::C:
15226 case CallingConv::X86_StdCall: {
15227 // Pass 'nest' parameter in ECX.
15228 // Must be kept in sync with X86CallingConv.td
15229 NestReg = X86::ECX;
15231 // Check that ECX wasn't needed by an 'inreg' parameter.
15232 FunctionType *FTy = Func->getFunctionType();
15233 const AttributeSet &Attrs = Func->getAttributes();
15235 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15236 unsigned InRegCount = 0;
15239 for (FunctionType::param_iterator I = FTy->param_begin(),
15240 E = FTy->param_end(); I != E; ++I, ++Idx)
15241 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15242 // FIXME: should only count parameters that are lowered to integers.
15243 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15245 if (InRegCount > 2) {
15246 report_fatal_error("Nest register in use - reduce number of inreg"
15252 case CallingConv::X86_FastCall:
15253 case CallingConv::X86_ThisCall:
15254 case CallingConv::Fast:
15255 // Pass 'nest' parameter in EAX.
15256 // Must be kept in sync with X86CallingConv.td
15257 NestReg = X86::EAX;
15261 SDValue OutChains[4];
15262 SDValue Addr, Disp;
15264 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15265 DAG.getConstant(10, MVT::i32));
15266 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15268 // This is storing the opcode for MOV32ri.
15269 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15270 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15271 OutChains[0] = DAG.getStore(Root, dl,
15272 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15273 Trmp, MachinePointerInfo(TrmpAddr),
15276 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15277 DAG.getConstant(1, MVT::i32));
15278 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15279 MachinePointerInfo(TrmpAddr, 1),
15282 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15283 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15284 DAG.getConstant(5, MVT::i32));
15285 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15286 MachinePointerInfo(TrmpAddr, 5),
15289 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15290 DAG.getConstant(6, MVT::i32));
15291 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15292 MachinePointerInfo(TrmpAddr, 6),
15295 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15299 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15300 SelectionDAG &DAG) const {
15302 The rounding mode is in bits 11:10 of FPSR, and has the following
15304 00 Round to nearest
15309 FLT_ROUNDS, on the other hand, expects the following:
15316 To perform the conversion, we do:
15317 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15320 MachineFunction &MF = DAG.getMachineFunction();
15321 const TargetMachine &TM = MF.getTarget();
15322 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15323 unsigned StackAlignment = TFI.getStackAlignment();
15324 MVT VT = Op.getSimpleValueType();
15327 // Save FP Control Word to stack slot
15328 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15329 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15331 MachineMemOperand *MMO =
15332 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15333 MachineMemOperand::MOStore, 2, 2);
15335 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15336 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15337 DAG.getVTList(MVT::Other),
15338 Ops, MVT::i16, MMO);
15340 // Load FP Control Word from stack slot
15341 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15342 MachinePointerInfo(), false, false, false, 0);
15344 // Transform as necessary
15346 DAG.getNode(ISD::SRL, DL, MVT::i16,
15347 DAG.getNode(ISD::AND, DL, MVT::i16,
15348 CWD, DAG.getConstant(0x800, MVT::i16)),
15349 DAG.getConstant(11, MVT::i8));
15351 DAG.getNode(ISD::SRL, DL, MVT::i16,
15352 DAG.getNode(ISD::AND, DL, MVT::i16,
15353 CWD, DAG.getConstant(0x400, MVT::i16)),
15354 DAG.getConstant(9, MVT::i8));
15357 DAG.getNode(ISD::AND, DL, MVT::i16,
15358 DAG.getNode(ISD::ADD, DL, MVT::i16,
15359 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15360 DAG.getConstant(1, MVT::i16)),
15361 DAG.getConstant(3, MVT::i16));
15363 return DAG.getNode((VT.getSizeInBits() < 16 ?
15364 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15367 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15368 MVT VT = Op.getSimpleValueType();
15370 unsigned NumBits = VT.getSizeInBits();
15373 Op = Op.getOperand(0);
15374 if (VT == MVT::i8) {
15375 // Zero extend to i32 since there is not an i8 bsr.
15377 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15380 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15381 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15382 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15384 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15387 DAG.getConstant(NumBits+NumBits-1, OpVT),
15388 DAG.getConstant(X86::COND_E, MVT::i8),
15391 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15393 // Finally xor with NumBits-1.
15394 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15397 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15401 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15402 MVT VT = Op.getSimpleValueType();
15404 unsigned NumBits = VT.getSizeInBits();
15407 Op = Op.getOperand(0);
15408 if (VT == MVT::i8) {
15409 // Zero extend to i32 since there is not an i8 bsr.
15411 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15414 // Issue a bsr (scan bits in reverse).
15415 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15416 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15418 // And xor with NumBits-1.
15419 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15422 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15426 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15427 MVT VT = Op.getSimpleValueType();
15428 unsigned NumBits = VT.getSizeInBits();
15430 Op = Op.getOperand(0);
15432 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15433 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15434 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15436 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15439 DAG.getConstant(NumBits, VT),
15440 DAG.getConstant(X86::COND_E, MVT::i8),
15443 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15446 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15447 // ones, and then concatenate the result back.
15448 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15449 MVT VT = Op.getSimpleValueType();
15451 assert(VT.is256BitVector() && VT.isInteger() &&
15452 "Unsupported value type for operation");
15454 unsigned NumElems = VT.getVectorNumElements();
15457 // Extract the LHS vectors
15458 SDValue LHS = Op.getOperand(0);
15459 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15460 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15462 // Extract the RHS vectors
15463 SDValue RHS = Op.getOperand(1);
15464 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15465 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15467 MVT EltVT = VT.getVectorElementType();
15468 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15470 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15471 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15472 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15475 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15476 assert(Op.getSimpleValueType().is256BitVector() &&
15477 Op.getSimpleValueType().isInteger() &&
15478 "Only handle AVX 256-bit vector integer operation");
15479 return Lower256IntArith(Op, DAG);
15482 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15483 assert(Op.getSimpleValueType().is256BitVector() &&
15484 Op.getSimpleValueType().isInteger() &&
15485 "Only handle AVX 256-bit vector integer operation");
15486 return Lower256IntArith(Op, DAG);
15489 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15490 SelectionDAG &DAG) {
15492 MVT VT = Op.getSimpleValueType();
15494 // Decompose 256-bit ops into smaller 128-bit ops.
15495 if (VT.is256BitVector() && !Subtarget->hasInt256())
15496 return Lower256IntArith(Op, DAG);
15498 SDValue A = Op.getOperand(0);
15499 SDValue B = Op.getOperand(1);
15501 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15502 if (VT == MVT::v4i32) {
15503 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15504 "Should not custom lower when pmuldq is available!");
15506 // Extract the odd parts.
15507 static const int UnpackMask[] = { 1, -1, 3, -1 };
15508 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15509 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15511 // Multiply the even parts.
15512 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15513 // Now multiply odd parts.
15514 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15516 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15517 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15519 // Merge the two vectors back together with a shuffle. This expands into 2
15521 static const int ShufMask[] = { 0, 4, 2, 6 };
15522 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15525 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15526 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15528 // Ahi = psrlqi(a, 32);
15529 // Bhi = psrlqi(b, 32);
15531 // AloBlo = pmuludq(a, b);
15532 // AloBhi = pmuludq(a, Bhi);
15533 // AhiBlo = pmuludq(Ahi, b);
15535 // AloBhi = psllqi(AloBhi, 32);
15536 // AhiBlo = psllqi(AhiBlo, 32);
15537 // return AloBlo + AloBhi + AhiBlo;
15539 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15540 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15542 // Bit cast to 32-bit vectors for MULUDQ
15543 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15544 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15545 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15546 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15547 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15548 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15550 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15551 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15552 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15554 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15555 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15557 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15558 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15561 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15562 assert(Subtarget->isTargetWin64() && "Unexpected target");
15563 EVT VT = Op.getValueType();
15564 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15565 "Unexpected return type for lowering");
15569 switch (Op->getOpcode()) {
15570 default: llvm_unreachable("Unexpected request for libcall!");
15571 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15572 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15573 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15574 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15575 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15576 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15580 SDValue InChain = DAG.getEntryNode();
15582 TargetLowering::ArgListTy Args;
15583 TargetLowering::ArgListEntry Entry;
15584 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15585 EVT ArgVT = Op->getOperand(i).getValueType();
15586 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15587 "Unexpected argument type for lowering");
15588 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15589 Entry.Node = StackPtr;
15590 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15592 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15593 Entry.Ty = PointerType::get(ArgTy,0);
15594 Entry.isSExt = false;
15595 Entry.isZExt = false;
15596 Args.push_back(Entry);
15599 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15602 TargetLowering::CallLoweringInfo CLI(DAG);
15603 CLI.setDebugLoc(dl).setChain(InChain)
15604 .setCallee(getLibcallCallingConv(LC),
15605 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15606 Callee, std::move(Args), 0)
15607 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15609 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15610 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15613 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15614 SelectionDAG &DAG) {
15615 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15616 EVT VT = Op0.getValueType();
15619 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15620 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15622 // PMULxD operations multiply each even value (starting at 0) of LHS with
15623 // the related value of RHS and produce a widen result.
15624 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15625 // => <2 x i64> <ae|cg>
15627 // In other word, to have all the results, we need to perform two PMULxD:
15628 // 1. one with the even values.
15629 // 2. one with the odd values.
15630 // To achieve #2, with need to place the odd values at an even position.
15632 // Place the odd value at an even position (basically, shift all values 1
15633 // step to the left):
15634 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15635 // <a|b|c|d> => <b|undef|d|undef>
15636 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15637 // <e|f|g|h> => <f|undef|h|undef>
15638 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15640 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15642 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15643 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15645 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15646 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15647 // => <2 x i64> <ae|cg>
15648 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15649 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15650 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15651 // => <2 x i64> <bf|dh>
15652 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15653 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15655 // Shuffle it back into the right order.
15656 SDValue Highs, Lows;
15657 if (VT == MVT::v8i32) {
15658 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15659 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15660 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15661 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15663 const int HighMask[] = {1, 5, 3, 7};
15664 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15665 const int LowMask[] = {1, 4, 2, 6};
15666 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15669 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15670 // unsigned multiply.
15671 if (IsSigned && !Subtarget->hasSSE41()) {
15673 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15674 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15675 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15676 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15677 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15679 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15680 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15683 // The first result of MUL_LOHI is actually the low value, followed by the
15685 SDValue Ops[] = {Lows, Highs};
15686 return DAG.getMergeValues(Ops, dl);
15689 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15690 const X86Subtarget *Subtarget) {
15691 MVT VT = Op.getSimpleValueType();
15693 SDValue R = Op.getOperand(0);
15694 SDValue Amt = Op.getOperand(1);
15696 // Optimize shl/srl/sra with constant shift amount.
15697 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15698 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15699 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15701 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15702 (Subtarget->hasInt256() &&
15703 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15704 (Subtarget->hasAVX512() &&
15705 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15706 if (Op.getOpcode() == ISD::SHL)
15707 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15709 if (Op.getOpcode() == ISD::SRL)
15710 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15712 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15713 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15717 if (VT == MVT::v16i8) {
15718 if (Op.getOpcode() == ISD::SHL) {
15719 // Make a large shift.
15720 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15721 MVT::v8i16, R, ShiftAmt,
15723 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15724 // Zero out the rightmost bits.
15725 SmallVector<SDValue, 16> V(16,
15726 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15728 return DAG.getNode(ISD::AND, dl, VT, SHL,
15729 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15731 if (Op.getOpcode() == ISD::SRL) {
15732 // Make a large shift.
15733 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15734 MVT::v8i16, R, ShiftAmt,
15736 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15737 // Zero out the leftmost bits.
15738 SmallVector<SDValue, 16> V(16,
15739 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15741 return DAG.getNode(ISD::AND, dl, VT, SRL,
15742 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15744 if (Op.getOpcode() == ISD::SRA) {
15745 if (ShiftAmt == 7) {
15746 // R s>> 7 === R s< 0
15747 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15748 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15751 // R s>> a === ((R u>> a) ^ m) - m
15752 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15753 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15755 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15756 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15757 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15760 llvm_unreachable("Unknown shift opcode.");
15763 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15764 if (Op.getOpcode() == ISD::SHL) {
15765 // Make a large shift.
15766 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15767 MVT::v16i16, R, ShiftAmt,
15769 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15770 // Zero out the rightmost bits.
15771 SmallVector<SDValue, 32> V(32,
15772 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15774 return DAG.getNode(ISD::AND, dl, VT, SHL,
15775 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15777 if (Op.getOpcode() == ISD::SRL) {
15778 // Make a large shift.
15779 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15780 MVT::v16i16, R, ShiftAmt,
15782 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15783 // Zero out the leftmost bits.
15784 SmallVector<SDValue, 32> V(32,
15785 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15787 return DAG.getNode(ISD::AND, dl, VT, SRL,
15788 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15790 if (Op.getOpcode() == ISD::SRA) {
15791 if (ShiftAmt == 7) {
15792 // R s>> 7 === R s< 0
15793 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15794 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15797 // R s>> a === ((R u>> a) ^ m) - m
15798 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15799 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
15801 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15802 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15803 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15806 llvm_unreachable("Unknown shift opcode.");
15811 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15812 if (!Subtarget->is64Bit() &&
15813 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15814 Amt.getOpcode() == ISD::BITCAST &&
15815 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15816 Amt = Amt.getOperand(0);
15817 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15818 VT.getVectorNumElements();
15819 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15820 uint64_t ShiftAmt = 0;
15821 for (unsigned i = 0; i != Ratio; ++i) {
15822 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15826 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15828 // Check remaining shift amounts.
15829 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15830 uint64_t ShAmt = 0;
15831 for (unsigned j = 0; j != Ratio; ++j) {
15832 ConstantSDNode *C =
15833 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15837 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15839 if (ShAmt != ShiftAmt)
15842 switch (Op.getOpcode()) {
15844 llvm_unreachable("Unknown shift opcode!");
15846 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15849 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15852 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15860 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15861 const X86Subtarget* Subtarget) {
15862 MVT VT = Op.getSimpleValueType();
15864 SDValue R = Op.getOperand(0);
15865 SDValue Amt = Op.getOperand(1);
15867 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15868 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15869 (Subtarget->hasInt256() &&
15870 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15871 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15872 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15874 EVT EltVT = VT.getVectorElementType();
15876 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15877 unsigned NumElts = VT.getVectorNumElements();
15879 for (i = 0; i != NumElts; ++i) {
15880 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
15884 for (j = i; j != NumElts; ++j) {
15885 SDValue Arg = Amt.getOperand(j);
15886 if (Arg.getOpcode() == ISD::UNDEF) continue;
15887 if (Arg != Amt.getOperand(i))
15890 if (i != NumElts && j == NumElts)
15891 BaseShAmt = Amt.getOperand(i);
15893 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15894 Amt = Amt.getOperand(0);
15895 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
15896 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
15897 SDValue InVec = Amt.getOperand(0);
15898 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15899 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15901 for (; i != NumElts; ++i) {
15902 SDValue Arg = InVec.getOperand(i);
15903 if (Arg.getOpcode() == ISD::UNDEF) continue;
15907 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15908 if (ConstantSDNode *C =
15909 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15910 unsigned SplatIdx =
15911 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
15912 if (C->getZExtValue() == SplatIdx)
15913 BaseShAmt = InVec.getOperand(1);
15916 if (!BaseShAmt.getNode())
15917 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
15918 DAG.getIntPtrConstant(0));
15922 if (BaseShAmt.getNode()) {
15923 if (EltVT.bitsGT(MVT::i32))
15924 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
15925 else if (EltVT.bitsLT(MVT::i32))
15926 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15928 switch (Op.getOpcode()) {
15930 llvm_unreachable("Unknown shift opcode!");
15932 switch (VT.SimpleTy) {
15933 default: return SDValue();
15942 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15945 switch (VT.SimpleTy) {
15946 default: return SDValue();
15953 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
15956 switch (VT.SimpleTy) {
15957 default: return SDValue();
15966 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
15972 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15973 if (!Subtarget->is64Bit() &&
15974 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
15975 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
15976 Amt.getOpcode() == ISD::BITCAST &&
15977 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15978 Amt = Amt.getOperand(0);
15979 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15980 VT.getVectorNumElements();
15981 std::vector<SDValue> Vals(Ratio);
15982 for (unsigned i = 0; i != Ratio; ++i)
15983 Vals[i] = Amt.getOperand(i);
15984 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15985 for (unsigned j = 0; j != Ratio; ++j)
15986 if (Vals[j] != Amt.getOperand(i + j))
15989 switch (Op.getOpcode()) {
15991 llvm_unreachable("Unknown shift opcode!");
15993 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
15995 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
15997 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16004 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16005 SelectionDAG &DAG) {
16006 MVT VT = Op.getSimpleValueType();
16008 SDValue R = Op.getOperand(0);
16009 SDValue Amt = Op.getOperand(1);
16012 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16013 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16015 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16019 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16023 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16025 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16026 if (Subtarget->hasInt256()) {
16027 if (Op.getOpcode() == ISD::SRL &&
16028 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16029 VT == MVT::v4i64 || VT == MVT::v8i32))
16031 if (Op.getOpcode() == ISD::SHL &&
16032 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16033 VT == MVT::v4i64 || VT == MVT::v8i32))
16035 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16039 // If possible, lower this packed shift into a vector multiply instead of
16040 // expanding it into a sequence of scalar shifts.
16041 // Do this only if the vector shift count is a constant build_vector.
16042 if (Op.getOpcode() == ISD::SHL &&
16043 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16044 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16045 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16046 SmallVector<SDValue, 8> Elts;
16047 EVT SVT = VT.getScalarType();
16048 unsigned SVTBits = SVT.getSizeInBits();
16049 const APInt &One = APInt(SVTBits, 1);
16050 unsigned NumElems = VT.getVectorNumElements();
16052 for (unsigned i=0; i !=NumElems; ++i) {
16053 SDValue Op = Amt->getOperand(i);
16054 if (Op->getOpcode() == ISD::UNDEF) {
16055 Elts.push_back(Op);
16059 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16060 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16061 uint64_t ShAmt = C.getZExtValue();
16062 if (ShAmt >= SVTBits) {
16063 Elts.push_back(DAG.getUNDEF(SVT));
16066 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16068 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16069 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16072 // Lower SHL with variable shift amount.
16073 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16074 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16076 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16077 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16078 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16079 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16082 // If possible, lower this shift as a sequence of two shifts by
16083 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16085 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16087 // Could be rewritten as:
16088 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16090 // The advantage is that the two shifts from the example would be
16091 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16092 // the vector shift into four scalar shifts plus four pairs of vector
16094 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16095 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16096 unsigned TargetOpcode = X86ISD::MOVSS;
16097 bool CanBeSimplified;
16098 // The splat value for the first packed shift (the 'X' from the example).
16099 SDValue Amt1 = Amt->getOperand(0);
16100 // The splat value for the second packed shift (the 'Y' from the example).
16101 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16102 Amt->getOperand(2);
16104 // See if it is possible to replace this node with a sequence of
16105 // two shifts followed by a MOVSS/MOVSD
16106 if (VT == MVT::v4i32) {
16107 // Check if it is legal to use a MOVSS.
16108 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16109 Amt2 == Amt->getOperand(3);
16110 if (!CanBeSimplified) {
16111 // Otherwise, check if we can still simplify this node using a MOVSD.
16112 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16113 Amt->getOperand(2) == Amt->getOperand(3);
16114 TargetOpcode = X86ISD::MOVSD;
16115 Amt2 = Amt->getOperand(2);
16118 // Do similar checks for the case where the machine value type
16120 CanBeSimplified = Amt1 == Amt->getOperand(1);
16121 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16122 CanBeSimplified = Amt2 == Amt->getOperand(i);
16124 if (!CanBeSimplified) {
16125 TargetOpcode = X86ISD::MOVSD;
16126 CanBeSimplified = true;
16127 Amt2 = Amt->getOperand(4);
16128 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16129 CanBeSimplified = Amt1 == Amt->getOperand(i);
16130 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16131 CanBeSimplified = Amt2 == Amt->getOperand(j);
16135 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16136 isa<ConstantSDNode>(Amt2)) {
16137 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16138 EVT CastVT = MVT::v4i32;
16140 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16141 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16143 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16144 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16145 if (TargetOpcode == X86ISD::MOVSD)
16146 CastVT = MVT::v2i64;
16147 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16148 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16149 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16151 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16155 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16156 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16159 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16160 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16162 // Turn 'a' into a mask suitable for VSELECT
16163 SDValue VSelM = DAG.getConstant(0x80, VT);
16164 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16165 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16167 SDValue CM1 = DAG.getConstant(0x0f, VT);
16168 SDValue CM2 = DAG.getConstant(0x3f, VT);
16170 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16171 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16172 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16173 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16174 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16177 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16178 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16179 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16181 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16182 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16183 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16184 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16185 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16188 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16189 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16190 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16192 // return VSELECT(r, r+r, a);
16193 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16194 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16198 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16199 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16200 // solution better.
16201 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16202 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16204 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16205 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16206 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16207 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16208 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16211 // Decompose 256-bit shifts into smaller 128-bit shifts.
16212 if (VT.is256BitVector()) {
16213 unsigned NumElems = VT.getVectorNumElements();
16214 MVT EltVT = VT.getVectorElementType();
16215 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16217 // Extract the two vectors
16218 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16219 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16221 // Recreate the shift amount vectors
16222 SDValue Amt1, Amt2;
16223 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16224 // Constant shift amount
16225 SmallVector<SDValue, 4> Amt1Csts;
16226 SmallVector<SDValue, 4> Amt2Csts;
16227 for (unsigned i = 0; i != NumElems/2; ++i)
16228 Amt1Csts.push_back(Amt->getOperand(i));
16229 for (unsigned i = NumElems/2; i != NumElems; ++i)
16230 Amt2Csts.push_back(Amt->getOperand(i));
16232 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16233 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16235 // Variable shift amount
16236 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16237 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16240 // Issue new vector shifts for the smaller types
16241 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16242 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16244 // Concatenate the result back
16245 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16251 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16252 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16253 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16254 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16255 // has only one use.
16256 SDNode *N = Op.getNode();
16257 SDValue LHS = N->getOperand(0);
16258 SDValue RHS = N->getOperand(1);
16259 unsigned BaseOp = 0;
16262 switch (Op.getOpcode()) {
16263 default: llvm_unreachable("Unknown ovf instruction!");
16265 // A subtract of one will be selected as a INC. Note that INC doesn't
16266 // set CF, so we can't do this for UADDO.
16267 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16269 BaseOp = X86ISD::INC;
16270 Cond = X86::COND_O;
16273 BaseOp = X86ISD::ADD;
16274 Cond = X86::COND_O;
16277 BaseOp = X86ISD::ADD;
16278 Cond = X86::COND_B;
16281 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16282 // set CF, so we can't do this for USUBO.
16283 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16285 BaseOp = X86ISD::DEC;
16286 Cond = X86::COND_O;
16289 BaseOp = X86ISD::SUB;
16290 Cond = X86::COND_O;
16293 BaseOp = X86ISD::SUB;
16294 Cond = X86::COND_B;
16297 BaseOp = X86ISD::SMUL;
16298 Cond = X86::COND_O;
16300 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16301 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16303 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16306 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16307 DAG.getConstant(X86::COND_O, MVT::i32),
16308 SDValue(Sum.getNode(), 2));
16310 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16314 // Also sets EFLAGS.
16315 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16316 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16319 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16320 DAG.getConstant(Cond, MVT::i32),
16321 SDValue(Sum.getNode(), 1));
16323 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16326 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16327 SelectionDAG &DAG) const {
16329 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16330 MVT VT = Op.getSimpleValueType();
16332 if (!Subtarget->hasSSE2() || !VT.isVector())
16335 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16336 ExtraVT.getScalarType().getSizeInBits();
16338 switch (VT.SimpleTy) {
16339 default: return SDValue();
16342 if (!Subtarget->hasFp256())
16344 if (!Subtarget->hasInt256()) {
16345 // needs to be split
16346 unsigned NumElems = VT.getVectorNumElements();
16348 // Extract the LHS vectors
16349 SDValue LHS = Op.getOperand(0);
16350 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16351 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16353 MVT EltVT = VT.getVectorElementType();
16354 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16356 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16357 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16358 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16360 SDValue Extra = DAG.getValueType(ExtraVT);
16362 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16363 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16365 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16370 SDValue Op0 = Op.getOperand(0);
16371 SDValue Op00 = Op0.getOperand(0);
16373 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
16374 if (Op0.getOpcode() == ISD::BITCAST &&
16375 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
16376 // (sext (vzext x)) -> (vsext x)
16377 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
16378 if (Tmp1.getNode()) {
16379 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16380 // This folding is only valid when the in-reg type is a vector of i8,
16382 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
16383 ExtraEltVT == MVT::i32) {
16384 SDValue Tmp1Op0 = Tmp1.getOperand(0);
16385 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
16386 "This optimization is invalid without a VZEXT.");
16387 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
16393 // If the above didn't work, then just use Shift-Left + Shift-Right.
16394 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
16396 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
16402 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16403 SelectionDAG &DAG) {
16405 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16406 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16407 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16408 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16410 // The only fence that needs an instruction is a sequentially-consistent
16411 // cross-thread fence.
16412 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16413 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16414 // no-sse2). There isn't any reason to disable it if the target processor
16416 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16417 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16419 SDValue Chain = Op.getOperand(0);
16420 SDValue Zero = DAG.getConstant(0, MVT::i32);
16422 DAG.getRegister(X86::ESP, MVT::i32), // Base
16423 DAG.getTargetConstant(1, MVT::i8), // Scale
16424 DAG.getRegister(0, MVT::i32), // Index
16425 DAG.getTargetConstant(0, MVT::i32), // Disp
16426 DAG.getRegister(0, MVT::i32), // Segment.
16430 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16431 return SDValue(Res, 0);
16434 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16435 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16438 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16439 SelectionDAG &DAG) {
16440 MVT T = Op.getSimpleValueType();
16444 switch(T.SimpleTy) {
16445 default: llvm_unreachable("Invalid value type!");
16446 case MVT::i8: Reg = X86::AL; size = 1; break;
16447 case MVT::i16: Reg = X86::AX; size = 2; break;
16448 case MVT::i32: Reg = X86::EAX; size = 4; break;
16450 assert(Subtarget->is64Bit() && "Node not type legal!");
16451 Reg = X86::RAX; size = 8;
16454 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16455 Op.getOperand(2), SDValue());
16456 SDValue Ops[] = { cpIn.getValue(0),
16459 DAG.getTargetConstant(size, MVT::i8),
16460 cpIn.getValue(1) };
16461 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16462 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16463 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16467 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16468 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16469 MVT::i32, cpOut.getValue(2));
16470 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16471 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16473 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16474 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16475 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16479 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16480 SelectionDAG &DAG) {
16481 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16482 MVT DstVT = Op.getSimpleValueType();
16484 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16485 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16486 if (DstVT != MVT::f64)
16487 // This conversion needs to be expanded.
16490 SDValue InVec = Op->getOperand(0);
16492 unsigned NumElts = SrcVT.getVectorNumElements();
16493 EVT SVT = SrcVT.getVectorElementType();
16495 // Widen the vector in input in the case of MVT::v2i32.
16496 // Example: from MVT::v2i32 to MVT::v4i32.
16497 SmallVector<SDValue, 16> Elts;
16498 for (unsigned i = 0, e = NumElts; i != e; ++i)
16499 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16500 DAG.getIntPtrConstant(i)));
16502 // Explicitly mark the extra elements as Undef.
16503 SDValue Undef = DAG.getUNDEF(SVT);
16504 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16505 Elts.push_back(Undef);
16507 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16508 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16509 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16510 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16511 DAG.getIntPtrConstant(0));
16514 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16515 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16516 assert((DstVT == MVT::i64 ||
16517 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16518 "Unexpected custom BITCAST");
16519 // i64 <=> MMX conversions are Legal.
16520 if (SrcVT==MVT::i64 && DstVT.isVector())
16522 if (DstVT==MVT::i64 && SrcVT.isVector())
16524 // MMX <=> MMX conversions are Legal.
16525 if (SrcVT.isVector() && DstVT.isVector())
16527 // All other conversions need to be expanded.
16531 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16532 SDNode *Node = Op.getNode();
16534 EVT T = Node->getValueType(0);
16535 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16536 DAG.getConstant(0, T), Node->getOperand(2));
16537 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16538 cast<AtomicSDNode>(Node)->getMemoryVT(),
16539 Node->getOperand(0),
16540 Node->getOperand(1), negOp,
16541 cast<AtomicSDNode>(Node)->getMemOperand(),
16542 cast<AtomicSDNode>(Node)->getOrdering(),
16543 cast<AtomicSDNode>(Node)->getSynchScope());
16546 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16547 SDNode *Node = Op.getNode();
16549 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16551 // Convert seq_cst store -> xchg
16552 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16553 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16554 // (The only way to get a 16-byte store is cmpxchg16b)
16555 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16556 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16557 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16558 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16559 cast<AtomicSDNode>(Node)->getMemoryVT(),
16560 Node->getOperand(0),
16561 Node->getOperand(1), Node->getOperand(2),
16562 cast<AtomicSDNode>(Node)->getMemOperand(),
16563 cast<AtomicSDNode>(Node)->getOrdering(),
16564 cast<AtomicSDNode>(Node)->getSynchScope());
16565 return Swap.getValue(1);
16567 // Other atomic stores have a simple pattern.
16571 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16572 EVT VT = Op.getNode()->getSimpleValueType(0);
16574 // Let legalize expand this if it isn't a legal type yet.
16575 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16578 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16581 bool ExtraOp = false;
16582 switch (Op.getOpcode()) {
16583 default: llvm_unreachable("Invalid code");
16584 case ISD::ADDC: Opc = X86ISD::ADD; break;
16585 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16586 case ISD::SUBC: Opc = X86ISD::SUB; break;
16587 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16591 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16593 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16594 Op.getOperand(1), Op.getOperand(2));
16597 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16598 SelectionDAG &DAG) {
16599 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16601 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16602 // which returns the values as { float, float } (in XMM0) or
16603 // { double, double } (which is returned in XMM0, XMM1).
16605 SDValue Arg = Op.getOperand(0);
16606 EVT ArgVT = Arg.getValueType();
16607 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16609 TargetLowering::ArgListTy Args;
16610 TargetLowering::ArgListEntry Entry;
16614 Entry.isSExt = false;
16615 Entry.isZExt = false;
16616 Args.push_back(Entry);
16618 bool isF64 = ArgVT == MVT::f64;
16619 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16620 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16621 // the results are returned via SRet in memory.
16622 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16624 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16626 Type *RetTy = isF64
16627 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16628 : (Type*)VectorType::get(ArgTy, 4);
16630 TargetLowering::CallLoweringInfo CLI(DAG);
16631 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16632 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16634 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16637 // Returned in xmm0 and xmm1.
16638 return CallResult.first;
16640 // Returned in bits 0:31 and 32:64 xmm0.
16641 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16642 CallResult.first, DAG.getIntPtrConstant(0));
16643 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16644 CallResult.first, DAG.getIntPtrConstant(1));
16645 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16646 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16649 /// LowerOperation - Provide custom lowering hooks for some operations.
16651 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16652 switch (Op.getOpcode()) {
16653 default: llvm_unreachable("Should not custom lower this!");
16654 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16655 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16656 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16657 return LowerCMP_SWAP(Op, Subtarget, DAG);
16658 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16659 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16660 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16661 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16662 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16663 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16664 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16665 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16666 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16667 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16668 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16669 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16670 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16671 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16672 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16673 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16674 case ISD::SHL_PARTS:
16675 case ISD::SRA_PARTS:
16676 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16677 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16678 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16679 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16680 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16681 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16682 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16683 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16684 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16685 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16686 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
16687 case ISD::FABS: return LowerFABS(Op, DAG);
16688 case ISD::FNEG: return LowerFNEG(Op, DAG);
16689 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16690 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16691 case ISD::SETCC: return LowerSETCC(Op, DAG);
16692 case ISD::SELECT: return LowerSELECT(Op, DAG);
16693 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16694 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16695 case ISD::VASTART: return LowerVASTART(Op, DAG);
16696 case ISD::VAARG: return LowerVAARG(Op, DAG);
16697 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16698 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16699 case ISD::INTRINSIC_VOID:
16700 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16701 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16702 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16703 case ISD::FRAME_TO_ARGS_OFFSET:
16704 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16705 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16706 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16707 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16708 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16709 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16710 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16711 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16712 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16713 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16714 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16715 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16716 case ISD::UMUL_LOHI:
16717 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16720 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16726 case ISD::UMULO: return LowerXALUO(Op, DAG);
16727 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16728 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16732 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16733 case ISD::ADD: return LowerADD(Op, DAG);
16734 case ISD::SUB: return LowerSUB(Op, DAG);
16735 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16739 static void ReplaceATOMIC_LOAD(SDNode *Node,
16740 SmallVectorImpl<SDValue> &Results,
16741 SelectionDAG &DAG) {
16743 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16745 // Convert wide load -> cmpxchg8b/cmpxchg16b
16746 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16747 // (The only way to get a 16-byte load is cmpxchg16b)
16748 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16749 SDValue Zero = DAG.getConstant(0, VT);
16750 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16752 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16753 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16754 cast<AtomicSDNode>(Node)->getMemOperand(),
16755 cast<AtomicSDNode>(Node)->getOrdering(),
16756 cast<AtomicSDNode>(Node)->getOrdering(),
16757 cast<AtomicSDNode>(Node)->getSynchScope());
16758 Results.push_back(Swap.getValue(0));
16759 Results.push_back(Swap.getValue(2));
16762 /// ReplaceNodeResults - Replace a node with an illegal result type
16763 /// with a new node built out of custom code.
16764 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16765 SmallVectorImpl<SDValue>&Results,
16766 SelectionDAG &DAG) const {
16768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16769 switch (N->getOpcode()) {
16771 llvm_unreachable("Do not know how to custom type legalize this operation!");
16772 case ISD::SIGN_EXTEND_INREG:
16777 // We don't want to expand or promote these.
16784 case ISD::UDIVREM: {
16785 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16786 Results.push_back(V);
16789 case ISD::FP_TO_SINT:
16790 case ISD::FP_TO_UINT: {
16791 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16793 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16796 std::pair<SDValue,SDValue> Vals =
16797 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16798 SDValue FIST = Vals.first, StackSlot = Vals.second;
16799 if (FIST.getNode()) {
16800 EVT VT = N->getValueType(0);
16801 // Return a load from the stack slot.
16802 if (StackSlot.getNode())
16803 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16804 MachinePointerInfo(),
16805 false, false, false, 0));
16807 Results.push_back(FIST);
16811 case ISD::UINT_TO_FP: {
16812 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16813 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16814 N->getValueType(0) != MVT::v2f32)
16816 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16818 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16820 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16821 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16822 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16823 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16824 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16825 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16828 case ISD::FP_ROUND: {
16829 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16831 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16832 Results.push_back(V);
16835 case ISD::INTRINSIC_W_CHAIN: {
16836 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16838 default : llvm_unreachable("Do not know how to custom type "
16839 "legalize this intrinsic operation!");
16840 case Intrinsic::x86_rdtsc:
16841 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16843 case Intrinsic::x86_rdtscp:
16844 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16846 case Intrinsic::x86_rdpmc:
16847 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16850 case ISD::READCYCLECOUNTER: {
16851 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16854 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16855 EVT T = N->getValueType(0);
16856 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16857 bool Regs64bit = T == MVT::i128;
16858 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16859 SDValue cpInL, cpInH;
16860 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16861 DAG.getConstant(0, HalfT));
16862 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16863 DAG.getConstant(1, HalfT));
16864 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16865 Regs64bit ? X86::RAX : X86::EAX,
16867 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16868 Regs64bit ? X86::RDX : X86::EDX,
16869 cpInH, cpInL.getValue(1));
16870 SDValue swapInL, swapInH;
16871 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16872 DAG.getConstant(0, HalfT));
16873 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16874 DAG.getConstant(1, HalfT));
16875 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16876 Regs64bit ? X86::RBX : X86::EBX,
16877 swapInL, cpInH.getValue(1));
16878 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16879 Regs64bit ? X86::RCX : X86::ECX,
16880 swapInH, swapInL.getValue(1));
16881 SDValue Ops[] = { swapInH.getValue(0),
16883 swapInH.getValue(1) };
16884 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16885 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16886 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16887 X86ISD::LCMPXCHG8_DAG;
16888 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16889 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16890 Regs64bit ? X86::RAX : X86::EAX,
16891 HalfT, Result.getValue(1));
16892 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16893 Regs64bit ? X86::RDX : X86::EDX,
16894 HalfT, cpOutL.getValue(2));
16895 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16897 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16898 MVT::i32, cpOutH.getValue(2));
16900 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16901 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16902 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
16904 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
16905 Results.push_back(Success);
16906 Results.push_back(EFLAGS.getValue(1));
16909 case ISD::ATOMIC_SWAP:
16910 case ISD::ATOMIC_LOAD_ADD:
16911 case ISD::ATOMIC_LOAD_SUB:
16912 case ISD::ATOMIC_LOAD_AND:
16913 case ISD::ATOMIC_LOAD_OR:
16914 case ISD::ATOMIC_LOAD_XOR:
16915 case ISD::ATOMIC_LOAD_NAND:
16916 case ISD::ATOMIC_LOAD_MIN:
16917 case ISD::ATOMIC_LOAD_MAX:
16918 case ISD::ATOMIC_LOAD_UMIN:
16919 case ISD::ATOMIC_LOAD_UMAX:
16920 // Delegate to generic TypeLegalization. Situations we can really handle
16921 // should have already been dealt with by X86AtomicExpand.cpp.
16923 case ISD::ATOMIC_LOAD: {
16924 ReplaceATOMIC_LOAD(N, Results, DAG);
16927 case ISD::BITCAST: {
16928 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16929 EVT DstVT = N->getValueType(0);
16930 EVT SrcVT = N->getOperand(0)->getValueType(0);
16932 if (SrcVT != MVT::f64 ||
16933 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
16936 unsigned NumElts = DstVT.getVectorNumElements();
16937 EVT SVT = DstVT.getVectorElementType();
16938 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16939 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
16940 MVT::v2f64, N->getOperand(0));
16941 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
16943 if (ExperimentalVectorWideningLegalization) {
16944 // If we are legalizing vectors by widening, we already have the desired
16945 // legal vector type, just return it.
16946 Results.push_back(ToVecInt);
16950 SmallVector<SDValue, 8> Elts;
16951 for (unsigned i = 0, e = NumElts; i != e; ++i)
16952 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
16953 ToVecInt, DAG.getIntPtrConstant(i)));
16955 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
16960 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
16962 default: return nullptr;
16963 case X86ISD::BSF: return "X86ISD::BSF";
16964 case X86ISD::BSR: return "X86ISD::BSR";
16965 case X86ISD::SHLD: return "X86ISD::SHLD";
16966 case X86ISD::SHRD: return "X86ISD::SHRD";
16967 case X86ISD::FAND: return "X86ISD::FAND";
16968 case X86ISD::FANDN: return "X86ISD::FANDN";
16969 case X86ISD::FOR: return "X86ISD::FOR";
16970 case X86ISD::FXOR: return "X86ISD::FXOR";
16971 case X86ISD::FSRL: return "X86ISD::FSRL";
16972 case X86ISD::FILD: return "X86ISD::FILD";
16973 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
16974 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
16975 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
16976 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
16977 case X86ISD::FLD: return "X86ISD::FLD";
16978 case X86ISD::FST: return "X86ISD::FST";
16979 case X86ISD::CALL: return "X86ISD::CALL";
16980 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
16981 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
16982 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
16983 case X86ISD::BT: return "X86ISD::BT";
16984 case X86ISD::CMP: return "X86ISD::CMP";
16985 case X86ISD::COMI: return "X86ISD::COMI";
16986 case X86ISD::UCOMI: return "X86ISD::UCOMI";
16987 case X86ISD::CMPM: return "X86ISD::CMPM";
16988 case X86ISD::CMPMU: return "X86ISD::CMPMU";
16989 case X86ISD::SETCC: return "X86ISD::SETCC";
16990 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
16991 case X86ISD::FSETCC: return "X86ISD::FSETCC";
16992 case X86ISD::CMOV: return "X86ISD::CMOV";
16993 case X86ISD::BRCOND: return "X86ISD::BRCOND";
16994 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
16995 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
16996 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
16997 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
16998 case X86ISD::Wrapper: return "X86ISD::Wrapper";
16999 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17000 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17001 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17002 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17003 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17004 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17005 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17006 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17007 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17008 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17009 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17010 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17011 case X86ISD::HADD: return "X86ISD::HADD";
17012 case X86ISD::HSUB: return "X86ISD::HSUB";
17013 case X86ISD::FHADD: return "X86ISD::FHADD";
17014 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17015 case X86ISD::UMAX: return "X86ISD::UMAX";
17016 case X86ISD::UMIN: return "X86ISD::UMIN";
17017 case X86ISD::SMAX: return "X86ISD::SMAX";
17018 case X86ISD::SMIN: return "X86ISD::SMIN";
17019 case X86ISD::FMAX: return "X86ISD::FMAX";
17020 case X86ISD::FMIN: return "X86ISD::FMIN";
17021 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17022 case X86ISD::FMINC: return "X86ISD::FMINC";
17023 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17024 case X86ISD::FRCP: return "X86ISD::FRCP";
17025 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17026 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17027 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17028 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17029 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17030 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17031 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17032 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17033 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17034 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17035 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17036 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17037 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17038 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17039 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17040 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17041 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17042 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17043 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17044 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17045 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17046 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17047 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17048 case X86ISD::VSHL: return "X86ISD::VSHL";
17049 case X86ISD::VSRL: return "X86ISD::VSRL";
17050 case X86ISD::VSRA: return "X86ISD::VSRA";
17051 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17052 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17053 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17054 case X86ISD::CMPP: return "X86ISD::CMPP";
17055 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17056 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17057 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17058 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17059 case X86ISD::ADD: return "X86ISD::ADD";
17060 case X86ISD::SUB: return "X86ISD::SUB";
17061 case X86ISD::ADC: return "X86ISD::ADC";
17062 case X86ISD::SBB: return "X86ISD::SBB";
17063 case X86ISD::SMUL: return "X86ISD::SMUL";
17064 case X86ISD::UMUL: return "X86ISD::UMUL";
17065 case X86ISD::INC: return "X86ISD::INC";
17066 case X86ISD::DEC: return "X86ISD::DEC";
17067 case X86ISD::OR: return "X86ISD::OR";
17068 case X86ISD::XOR: return "X86ISD::XOR";
17069 case X86ISD::AND: return "X86ISD::AND";
17070 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17071 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17072 case X86ISD::PTEST: return "X86ISD::PTEST";
17073 case X86ISD::TESTP: return "X86ISD::TESTP";
17074 case X86ISD::TESTM: return "X86ISD::TESTM";
17075 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17076 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17077 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17078 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17079 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17080 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17081 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17082 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17083 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17084 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17085 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17086 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17087 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17088 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17089 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17090 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17091 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17092 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17093 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17094 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17095 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17096 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17097 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17098 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17099 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17100 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17101 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17102 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17103 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17104 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17105 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17106 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17107 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17108 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17109 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17110 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17111 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17112 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17113 case X86ISD::SAHF: return "X86ISD::SAHF";
17114 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17115 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17116 case X86ISD::FMADD: return "X86ISD::FMADD";
17117 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17118 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17119 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17120 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17121 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17122 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17123 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17124 case X86ISD::XTEST: return "X86ISD::XTEST";
17128 // isLegalAddressingMode - Return true if the addressing mode represented
17129 // by AM is legal for this target, for a load/store of the specified type.
17130 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17132 // X86 supports extremely general addressing modes.
17133 CodeModel::Model M = getTargetMachine().getCodeModel();
17134 Reloc::Model R = getTargetMachine().getRelocationModel();
17136 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17137 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17142 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17144 // If a reference to this global requires an extra load, we can't fold it.
17145 if (isGlobalStubReference(GVFlags))
17148 // If BaseGV requires a register for the PIC base, we cannot also have a
17149 // BaseReg specified.
17150 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17153 // If lower 4G is not available, then we must use rip-relative addressing.
17154 if ((M != CodeModel::Small || R != Reloc::Static) &&
17155 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17159 switch (AM.Scale) {
17165 // These scales always work.
17170 // These scales are formed with basereg+scalereg. Only accept if there is
17175 default: // Other stuff never works.
17182 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17183 unsigned Bits = Ty->getScalarSizeInBits();
17185 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17186 // particularly cheaper than those without.
17190 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17191 // variable shifts just as cheap as scalar ones.
17192 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17195 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17196 // fully general vector.
17200 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17201 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17203 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17204 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17205 return NumBits1 > NumBits2;
17208 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17209 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17212 if (!isTypeLegal(EVT::getEVT(Ty1)))
17215 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17217 // Assuming the caller doesn't have a zeroext or signext return parameter,
17218 // truncation all the way down to i1 is valid.
17222 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17223 return isInt<32>(Imm);
17226 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17227 // Can also use sub to handle negated immediates.
17228 return isInt<32>(Imm);
17231 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17232 if (!VT1.isInteger() || !VT2.isInteger())
17234 unsigned NumBits1 = VT1.getSizeInBits();
17235 unsigned NumBits2 = VT2.getSizeInBits();
17236 return NumBits1 > NumBits2;
17239 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17240 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17241 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17244 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17245 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17246 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17249 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17250 EVT VT1 = Val.getValueType();
17251 if (isZExtFree(VT1, VT2))
17254 if (Val.getOpcode() != ISD::LOAD)
17257 if (!VT1.isSimple() || !VT1.isInteger() ||
17258 !VT2.isSimple() || !VT2.isInteger())
17261 switch (VT1.getSimpleVT().SimpleTy) {
17266 // X86 has 8, 16, and 32-bit zero-extending loads.
17274 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17275 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17278 VT = VT.getScalarType();
17280 if (!VT.isSimple())
17283 switch (VT.getSimpleVT().SimpleTy) {
17294 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17295 // i16 instructions are longer (0x66 prefix) and potentially slower.
17296 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17299 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17300 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17301 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17302 /// are assumed to be legal.
17304 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17306 if (!VT.isSimple())
17309 MVT SVT = VT.getSimpleVT();
17311 // Very little shuffling can be done for 64-bit vectors right now.
17312 if (VT.getSizeInBits() == 64)
17315 // If this is a single-input shuffle with no 128 bit lane crossings we can
17316 // lower it into pshufb.
17317 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17318 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17319 bool isLegal = true;
17320 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17321 if (M[I] >= (int)SVT.getVectorNumElements() ||
17322 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17331 // FIXME: blends, shifts.
17332 return (SVT.getVectorNumElements() == 2 ||
17333 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17334 isMOVLMask(M, SVT) ||
17335 isMOVHLPSMask(M, SVT) ||
17336 isSHUFPMask(M, SVT) ||
17337 isPSHUFDMask(M, SVT) ||
17338 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17339 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17340 isPALIGNRMask(M, SVT, Subtarget) ||
17341 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17342 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17343 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17344 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17345 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17349 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17351 if (!VT.isSimple())
17354 MVT SVT = VT.getSimpleVT();
17355 unsigned NumElts = SVT.getVectorNumElements();
17356 // FIXME: This collection of masks seems suspect.
17359 if (NumElts == 4 && SVT.is128BitVector()) {
17360 return (isMOVLMask(Mask, SVT) ||
17361 isCommutedMOVLMask(Mask, SVT, true) ||
17362 isSHUFPMask(Mask, SVT) ||
17363 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17368 //===----------------------------------------------------------------------===//
17369 // X86 Scheduler Hooks
17370 //===----------------------------------------------------------------------===//
17372 /// Utility function to emit xbegin specifying the start of an RTM region.
17373 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17374 const TargetInstrInfo *TII) {
17375 DebugLoc DL = MI->getDebugLoc();
17377 const BasicBlock *BB = MBB->getBasicBlock();
17378 MachineFunction::iterator I = MBB;
17381 // For the v = xbegin(), we generate
17392 MachineBasicBlock *thisMBB = MBB;
17393 MachineFunction *MF = MBB->getParent();
17394 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17395 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17396 MF->insert(I, mainMBB);
17397 MF->insert(I, sinkMBB);
17399 // Transfer the remainder of BB and its successor edges to sinkMBB.
17400 sinkMBB->splice(sinkMBB->begin(), MBB,
17401 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17402 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17406 // # fallthrough to mainMBB
17407 // # abortion to sinkMBB
17408 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17409 thisMBB->addSuccessor(mainMBB);
17410 thisMBB->addSuccessor(sinkMBB);
17414 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17415 mainMBB->addSuccessor(sinkMBB);
17418 // EAX is live into the sinkMBB
17419 sinkMBB->addLiveIn(X86::EAX);
17420 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17421 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17424 MI->eraseFromParent();
17428 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17429 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17430 // in the .td file.
17431 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17432 const TargetInstrInfo *TII) {
17434 switch (MI->getOpcode()) {
17435 default: llvm_unreachable("illegal opcode!");
17436 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17437 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17438 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17439 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17440 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17441 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17442 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17443 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17446 DebugLoc dl = MI->getDebugLoc();
17447 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17449 unsigned NumArgs = MI->getNumOperands();
17450 for (unsigned i = 1; i < NumArgs; ++i) {
17451 MachineOperand &Op = MI->getOperand(i);
17452 if (!(Op.isReg() && Op.isImplicit()))
17453 MIB.addOperand(Op);
17455 if (MI->hasOneMemOperand())
17456 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17458 BuildMI(*BB, MI, dl,
17459 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17460 .addReg(X86::XMM0);
17462 MI->eraseFromParent();
17466 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17467 // defs in an instruction pattern
17468 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17469 const TargetInstrInfo *TII) {
17471 switch (MI->getOpcode()) {
17472 default: llvm_unreachable("illegal opcode!");
17473 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17474 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17475 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17476 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17477 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17478 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17479 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17480 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17483 DebugLoc dl = MI->getDebugLoc();
17484 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17486 unsigned NumArgs = MI->getNumOperands(); // remove the results
17487 for (unsigned i = 1; i < NumArgs; ++i) {
17488 MachineOperand &Op = MI->getOperand(i);
17489 if (!(Op.isReg() && Op.isImplicit()))
17490 MIB.addOperand(Op);
17492 if (MI->hasOneMemOperand())
17493 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17495 BuildMI(*BB, MI, dl,
17496 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17499 MI->eraseFromParent();
17503 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17504 const TargetInstrInfo *TII,
17505 const X86Subtarget* Subtarget) {
17506 DebugLoc dl = MI->getDebugLoc();
17508 // Address into RAX/EAX, other two args into ECX, EDX.
17509 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17510 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17511 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17512 for (int i = 0; i < X86::AddrNumOperands; ++i)
17513 MIB.addOperand(MI->getOperand(i));
17515 unsigned ValOps = X86::AddrNumOperands;
17516 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17517 .addReg(MI->getOperand(ValOps).getReg());
17518 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17519 .addReg(MI->getOperand(ValOps+1).getReg());
17521 // The instruction doesn't actually take any operands though.
17522 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17524 MI->eraseFromParent(); // The pseudo is gone now.
17528 MachineBasicBlock *
17529 X86TargetLowering::EmitVAARG64WithCustomInserter(
17531 MachineBasicBlock *MBB) const {
17532 // Emit va_arg instruction on X86-64.
17534 // Operands to this pseudo-instruction:
17535 // 0 ) Output : destination address (reg)
17536 // 1-5) Input : va_list address (addr, i64mem)
17537 // 6 ) ArgSize : Size (in bytes) of vararg type
17538 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17539 // 8 ) Align : Alignment of type
17540 // 9 ) EFLAGS (implicit-def)
17542 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17543 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17545 unsigned DestReg = MI->getOperand(0).getReg();
17546 MachineOperand &Base = MI->getOperand(1);
17547 MachineOperand &Scale = MI->getOperand(2);
17548 MachineOperand &Index = MI->getOperand(3);
17549 MachineOperand &Disp = MI->getOperand(4);
17550 MachineOperand &Segment = MI->getOperand(5);
17551 unsigned ArgSize = MI->getOperand(6).getImm();
17552 unsigned ArgMode = MI->getOperand(7).getImm();
17553 unsigned Align = MI->getOperand(8).getImm();
17555 // Memory Reference
17556 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17557 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17558 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17560 // Machine Information
17561 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17562 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17563 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17564 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17565 DebugLoc DL = MI->getDebugLoc();
17567 // struct va_list {
17570 // i64 overflow_area (address)
17571 // i64 reg_save_area (address)
17573 // sizeof(va_list) = 24
17574 // alignment(va_list) = 8
17576 unsigned TotalNumIntRegs = 6;
17577 unsigned TotalNumXMMRegs = 8;
17578 bool UseGPOffset = (ArgMode == 1);
17579 bool UseFPOffset = (ArgMode == 2);
17580 unsigned MaxOffset = TotalNumIntRegs * 8 +
17581 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17583 /* Align ArgSize to a multiple of 8 */
17584 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17585 bool NeedsAlign = (Align > 8);
17587 MachineBasicBlock *thisMBB = MBB;
17588 MachineBasicBlock *overflowMBB;
17589 MachineBasicBlock *offsetMBB;
17590 MachineBasicBlock *endMBB;
17592 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17593 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17594 unsigned OffsetReg = 0;
17596 if (!UseGPOffset && !UseFPOffset) {
17597 // If we only pull from the overflow region, we don't create a branch.
17598 // We don't need to alter control flow.
17599 OffsetDestReg = 0; // unused
17600 OverflowDestReg = DestReg;
17602 offsetMBB = nullptr;
17603 overflowMBB = thisMBB;
17606 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17607 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17608 // If not, pull from overflow_area. (branch to overflowMBB)
17613 // offsetMBB overflowMBB
17618 // Registers for the PHI in endMBB
17619 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17620 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17622 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17623 MachineFunction *MF = MBB->getParent();
17624 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17625 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17626 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17628 MachineFunction::iterator MBBIter = MBB;
17631 // Insert the new basic blocks
17632 MF->insert(MBBIter, offsetMBB);
17633 MF->insert(MBBIter, overflowMBB);
17634 MF->insert(MBBIter, endMBB);
17636 // Transfer the remainder of MBB and its successor edges to endMBB.
17637 endMBB->splice(endMBB->begin(), thisMBB,
17638 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17639 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17641 // Make offsetMBB and overflowMBB successors of thisMBB
17642 thisMBB->addSuccessor(offsetMBB);
17643 thisMBB->addSuccessor(overflowMBB);
17645 // endMBB is a successor of both offsetMBB and overflowMBB
17646 offsetMBB->addSuccessor(endMBB);
17647 overflowMBB->addSuccessor(endMBB);
17649 // Load the offset value into a register
17650 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17651 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17655 .addDisp(Disp, UseFPOffset ? 4 : 0)
17656 .addOperand(Segment)
17657 .setMemRefs(MMOBegin, MMOEnd);
17659 // Check if there is enough room left to pull this argument.
17660 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17662 .addImm(MaxOffset + 8 - ArgSizeA8);
17664 // Branch to "overflowMBB" if offset >= max
17665 // Fall through to "offsetMBB" otherwise
17666 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17667 .addMBB(overflowMBB);
17670 // In offsetMBB, emit code to use the reg_save_area.
17672 assert(OffsetReg != 0);
17674 // Read the reg_save_area address.
17675 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17676 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17681 .addOperand(Segment)
17682 .setMemRefs(MMOBegin, MMOEnd);
17684 // Zero-extend the offset
17685 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17686 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17689 .addImm(X86::sub_32bit);
17691 // Add the offset to the reg_save_area to get the final address.
17692 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17693 .addReg(OffsetReg64)
17694 .addReg(RegSaveReg);
17696 // Compute the offset for the next argument
17697 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17698 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17700 .addImm(UseFPOffset ? 16 : 8);
17702 // Store it back into the va_list.
17703 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17707 .addDisp(Disp, UseFPOffset ? 4 : 0)
17708 .addOperand(Segment)
17709 .addReg(NextOffsetReg)
17710 .setMemRefs(MMOBegin, MMOEnd);
17713 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17718 // Emit code to use overflow area
17721 // Load the overflow_area address into a register.
17722 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17723 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17728 .addOperand(Segment)
17729 .setMemRefs(MMOBegin, MMOEnd);
17731 // If we need to align it, do so. Otherwise, just copy the address
17732 // to OverflowDestReg.
17734 // Align the overflow address
17735 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17736 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17738 // aligned_addr = (addr + (align-1)) & ~(align-1)
17739 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17740 .addReg(OverflowAddrReg)
17743 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17745 .addImm(~(uint64_t)(Align-1));
17747 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17748 .addReg(OverflowAddrReg);
17751 // Compute the next overflow address after this argument.
17752 // (the overflow address should be kept 8-byte aligned)
17753 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17754 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17755 .addReg(OverflowDestReg)
17756 .addImm(ArgSizeA8);
17758 // Store the new overflow address.
17759 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17764 .addOperand(Segment)
17765 .addReg(NextAddrReg)
17766 .setMemRefs(MMOBegin, MMOEnd);
17768 // If we branched, emit the PHI to the front of endMBB.
17770 BuildMI(*endMBB, endMBB->begin(), DL,
17771 TII->get(X86::PHI), DestReg)
17772 .addReg(OffsetDestReg).addMBB(offsetMBB)
17773 .addReg(OverflowDestReg).addMBB(overflowMBB);
17776 // Erase the pseudo instruction
17777 MI->eraseFromParent();
17782 MachineBasicBlock *
17783 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17785 MachineBasicBlock *MBB) const {
17786 // Emit code to save XMM registers to the stack. The ABI says that the
17787 // number of registers to save is given in %al, so it's theoretically
17788 // possible to do an indirect jump trick to avoid saving all of them,
17789 // however this code takes a simpler approach and just executes all
17790 // of the stores if %al is non-zero. It's less code, and it's probably
17791 // easier on the hardware branch predictor, and stores aren't all that
17792 // expensive anyway.
17794 // Create the new basic blocks. One block contains all the XMM stores,
17795 // and one block is the final destination regardless of whether any
17796 // stores were performed.
17797 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17798 MachineFunction *F = MBB->getParent();
17799 MachineFunction::iterator MBBIter = MBB;
17801 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17802 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17803 F->insert(MBBIter, XMMSaveMBB);
17804 F->insert(MBBIter, EndMBB);
17806 // Transfer the remainder of MBB and its successor edges to EndMBB.
17807 EndMBB->splice(EndMBB->begin(), MBB,
17808 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17809 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17811 // The original block will now fall through to the XMM save block.
17812 MBB->addSuccessor(XMMSaveMBB);
17813 // The XMMSaveMBB will fall through to the end block.
17814 XMMSaveMBB->addSuccessor(EndMBB);
17816 // Now add the instructions.
17817 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17818 DebugLoc DL = MI->getDebugLoc();
17820 unsigned CountReg = MI->getOperand(0).getReg();
17821 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17822 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17824 if (!Subtarget->isTargetWin64()) {
17825 // If %al is 0, branch around the XMM save block.
17826 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17827 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17828 MBB->addSuccessor(EndMBB);
17831 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17832 // that was just emitted, but clearly shouldn't be "saved".
17833 assert((MI->getNumOperands() <= 3 ||
17834 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17835 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17836 && "Expected last argument to be EFLAGS");
17837 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17838 // In the XMM save block, save all the XMM argument registers.
17839 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17840 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17841 MachineMemOperand *MMO =
17842 F->getMachineMemOperand(
17843 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17844 MachineMemOperand::MOStore,
17845 /*Size=*/16, /*Align=*/16);
17846 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17847 .addFrameIndex(RegSaveFrameIndex)
17848 .addImm(/*Scale=*/1)
17849 .addReg(/*IndexReg=*/0)
17850 .addImm(/*Disp=*/Offset)
17851 .addReg(/*Segment=*/0)
17852 .addReg(MI->getOperand(i).getReg())
17853 .addMemOperand(MMO);
17856 MI->eraseFromParent(); // The pseudo instruction is gone now.
17861 // The EFLAGS operand of SelectItr might be missing a kill marker
17862 // because there were multiple uses of EFLAGS, and ISel didn't know
17863 // which to mark. Figure out whether SelectItr should have had a
17864 // kill marker, and set it if it should. Returns the correct kill
17866 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
17867 MachineBasicBlock* BB,
17868 const TargetRegisterInfo* TRI) {
17869 // Scan forward through BB for a use/def of EFLAGS.
17870 MachineBasicBlock::iterator miI(std::next(SelectItr));
17871 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
17872 const MachineInstr& mi = *miI;
17873 if (mi.readsRegister(X86::EFLAGS))
17875 if (mi.definesRegister(X86::EFLAGS))
17876 break; // Should have kill-flag - update below.
17879 // If we hit the end of the block, check whether EFLAGS is live into a
17881 if (miI == BB->end()) {
17882 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
17883 sEnd = BB->succ_end();
17884 sItr != sEnd; ++sItr) {
17885 MachineBasicBlock* succ = *sItr;
17886 if (succ->isLiveIn(X86::EFLAGS))
17891 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
17892 // out. SelectMI should have a kill flag on EFLAGS.
17893 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
17897 MachineBasicBlock *
17898 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
17899 MachineBasicBlock *BB) const {
17900 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
17901 DebugLoc DL = MI->getDebugLoc();
17903 // To "insert" a SELECT_CC instruction, we actually have to insert the
17904 // diamond control-flow pattern. The incoming instruction knows the
17905 // destination vreg to set, the condition code register to branch on, the
17906 // true/false values to select between, and a branch opcode to use.
17907 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17908 MachineFunction::iterator It = BB;
17914 // cmpTY ccX, r1, r2
17916 // fallthrough --> copy0MBB
17917 MachineBasicBlock *thisMBB = BB;
17918 MachineFunction *F = BB->getParent();
17919 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
17920 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
17921 F->insert(It, copy0MBB);
17922 F->insert(It, sinkMBB);
17924 // If the EFLAGS register isn't dead in the terminator, then claim that it's
17925 // live into the sink and copy blocks.
17926 const TargetRegisterInfo *TRI =
17927 BB->getParent()->getSubtarget().getRegisterInfo();
17928 if (!MI->killsRegister(X86::EFLAGS) &&
17929 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
17930 copy0MBB->addLiveIn(X86::EFLAGS);
17931 sinkMBB->addLiveIn(X86::EFLAGS);
17934 // Transfer the remainder of BB and its successor edges to sinkMBB.
17935 sinkMBB->splice(sinkMBB->begin(), BB,
17936 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17937 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
17939 // Add the true and fallthrough blocks as its successors.
17940 BB->addSuccessor(copy0MBB);
17941 BB->addSuccessor(sinkMBB);
17943 // Create the conditional branch instruction.
17945 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
17946 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
17949 // %FalseValue = ...
17950 // # fallthrough to sinkMBB
17951 copy0MBB->addSuccessor(sinkMBB);
17954 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
17956 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17957 TII->get(X86::PHI), MI->getOperand(0).getReg())
17958 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
17959 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
17961 MI->eraseFromParent(); // The pseudo instruction is gone now.
17965 MachineBasicBlock *
17966 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
17967 bool Is64Bit) const {
17968 MachineFunction *MF = BB->getParent();
17969 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
17970 DebugLoc DL = MI->getDebugLoc();
17971 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17973 assert(MF->shouldSplitStack());
17975 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
17976 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
17979 // ... [Till the alloca]
17980 // If stacklet is not large enough, jump to mallocMBB
17983 // Allocate by subtracting from RSP
17984 // Jump to continueMBB
17987 // Allocate by call to runtime
17991 // [rest of original BB]
17994 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17995 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17996 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17998 MachineRegisterInfo &MRI = MF->getRegInfo();
17999 const TargetRegisterClass *AddrRegClass =
18000 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18002 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18003 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18004 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18005 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18006 sizeVReg = MI->getOperand(1).getReg(),
18007 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18009 MachineFunction::iterator MBBIter = BB;
18012 MF->insert(MBBIter, bumpMBB);
18013 MF->insert(MBBIter, mallocMBB);
18014 MF->insert(MBBIter, continueMBB);
18016 continueMBB->splice(continueMBB->begin(), BB,
18017 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18018 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18020 // Add code to the main basic block to check if the stack limit has been hit,
18021 // and if so, jump to mallocMBB otherwise to bumpMBB.
18022 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18023 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18024 .addReg(tmpSPVReg).addReg(sizeVReg);
18025 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18026 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18027 .addReg(SPLimitVReg);
18028 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18030 // bumpMBB simply decreases the stack pointer, since we know the current
18031 // stacklet has enough space.
18032 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18033 .addReg(SPLimitVReg);
18034 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18035 .addReg(SPLimitVReg);
18036 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18038 // Calls into a routine in libgcc to allocate more space from the heap.
18039 const uint32_t *RegMask = MF->getTarget()
18040 .getSubtargetImpl()
18041 ->getRegisterInfo()
18042 ->getCallPreservedMask(CallingConv::C);
18044 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18046 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18047 .addExternalSymbol("__morestack_allocate_stack_space")
18048 .addRegMask(RegMask)
18049 .addReg(X86::RDI, RegState::Implicit)
18050 .addReg(X86::RAX, RegState::ImplicitDefine);
18052 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18054 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18055 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18056 .addExternalSymbol("__morestack_allocate_stack_space")
18057 .addRegMask(RegMask)
18058 .addReg(X86::EAX, RegState::ImplicitDefine);
18062 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18065 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18066 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18067 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18069 // Set up the CFG correctly.
18070 BB->addSuccessor(bumpMBB);
18071 BB->addSuccessor(mallocMBB);
18072 mallocMBB->addSuccessor(continueMBB);
18073 bumpMBB->addSuccessor(continueMBB);
18075 // Take care of the PHI nodes.
18076 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18077 MI->getOperand(0).getReg())
18078 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18079 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18081 // Delete the original pseudo instruction.
18082 MI->eraseFromParent();
18085 return continueMBB;
18088 MachineBasicBlock *
18089 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18090 MachineBasicBlock *BB) const {
18091 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18092 DebugLoc DL = MI->getDebugLoc();
18094 assert(!Subtarget->isTargetMacho());
18096 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18097 // non-trivial part is impdef of ESP.
18099 if (Subtarget->isTargetWin64()) {
18100 if (Subtarget->isTargetCygMing()) {
18101 // ___chkstk(Mingw64):
18102 // Clobbers R10, R11, RAX and EFLAGS.
18104 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18105 .addExternalSymbol("___chkstk")
18106 .addReg(X86::RAX, RegState::Implicit)
18107 .addReg(X86::RSP, RegState::Implicit)
18108 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18109 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18110 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18112 // __chkstk(MSVCRT): does not update stack pointer.
18113 // Clobbers R10, R11 and EFLAGS.
18114 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18115 .addExternalSymbol("__chkstk")
18116 .addReg(X86::RAX, RegState::Implicit)
18117 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18118 // RAX has the offset to be subtracted from RSP.
18119 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18124 const char *StackProbeSymbol =
18125 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18127 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18128 .addExternalSymbol(StackProbeSymbol)
18129 .addReg(X86::EAX, RegState::Implicit)
18130 .addReg(X86::ESP, RegState::Implicit)
18131 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18132 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18133 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18136 MI->eraseFromParent(); // The pseudo instruction is gone now.
18140 MachineBasicBlock *
18141 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18142 MachineBasicBlock *BB) const {
18143 // This is pretty easy. We're taking the value that we received from
18144 // our load from the relocation, sticking it in either RDI (x86-64)
18145 // or EAX and doing an indirect call. The return value will then
18146 // be in the normal return register.
18147 MachineFunction *F = BB->getParent();
18148 const X86InstrInfo *TII =
18149 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18150 DebugLoc DL = MI->getDebugLoc();
18152 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18153 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18155 // Get a register mask for the lowered call.
18156 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18157 // proper register mask.
18158 const uint32_t *RegMask = F->getTarget()
18159 .getSubtargetImpl()
18160 ->getRegisterInfo()
18161 ->getCallPreservedMask(CallingConv::C);
18162 if (Subtarget->is64Bit()) {
18163 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18164 TII->get(X86::MOV64rm), X86::RDI)
18166 .addImm(0).addReg(0)
18167 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18168 MI->getOperand(3).getTargetFlags())
18170 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18171 addDirectMem(MIB, X86::RDI);
18172 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18173 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18174 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18175 TII->get(X86::MOV32rm), X86::EAX)
18177 .addImm(0).addReg(0)
18178 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18179 MI->getOperand(3).getTargetFlags())
18181 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18182 addDirectMem(MIB, X86::EAX);
18183 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18185 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18186 TII->get(X86::MOV32rm), X86::EAX)
18187 .addReg(TII->getGlobalBaseReg(F))
18188 .addImm(0).addReg(0)
18189 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18190 MI->getOperand(3).getTargetFlags())
18192 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18193 addDirectMem(MIB, X86::EAX);
18194 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18197 MI->eraseFromParent(); // The pseudo instruction is gone now.
18201 MachineBasicBlock *
18202 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18203 MachineBasicBlock *MBB) const {
18204 DebugLoc DL = MI->getDebugLoc();
18205 MachineFunction *MF = MBB->getParent();
18206 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18207 MachineRegisterInfo &MRI = MF->getRegInfo();
18209 const BasicBlock *BB = MBB->getBasicBlock();
18210 MachineFunction::iterator I = MBB;
18213 // Memory Reference
18214 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18215 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18218 unsigned MemOpndSlot = 0;
18220 unsigned CurOp = 0;
18222 DstReg = MI->getOperand(CurOp++).getReg();
18223 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18224 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18225 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18226 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18228 MemOpndSlot = CurOp;
18230 MVT PVT = getPointerTy();
18231 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18232 "Invalid Pointer Size!");
18234 // For v = setjmp(buf), we generate
18237 // buf[LabelOffset] = restoreMBB
18238 // SjLjSetup restoreMBB
18244 // v = phi(main, restore)
18249 MachineBasicBlock *thisMBB = MBB;
18250 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18251 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18252 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18253 MF->insert(I, mainMBB);
18254 MF->insert(I, sinkMBB);
18255 MF->push_back(restoreMBB);
18257 MachineInstrBuilder MIB;
18259 // Transfer the remainder of BB and its successor edges to sinkMBB.
18260 sinkMBB->splice(sinkMBB->begin(), MBB,
18261 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18262 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18265 unsigned PtrStoreOpc = 0;
18266 unsigned LabelReg = 0;
18267 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18268 Reloc::Model RM = MF->getTarget().getRelocationModel();
18269 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18270 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18272 // Prepare IP either in reg or imm.
18273 if (!UseImmLabel) {
18274 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18275 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18276 LabelReg = MRI.createVirtualRegister(PtrRC);
18277 if (Subtarget->is64Bit()) {
18278 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18282 .addMBB(restoreMBB)
18285 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18286 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18287 .addReg(XII->getGlobalBaseReg(MF))
18290 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18294 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18296 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18297 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18298 if (i == X86::AddrDisp)
18299 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18301 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18304 MIB.addReg(LabelReg);
18306 MIB.addMBB(restoreMBB);
18307 MIB.setMemRefs(MMOBegin, MMOEnd);
18309 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18310 .addMBB(restoreMBB);
18312 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18313 MF->getSubtarget().getRegisterInfo());
18314 MIB.addRegMask(RegInfo->getNoPreservedMask());
18315 thisMBB->addSuccessor(mainMBB);
18316 thisMBB->addSuccessor(restoreMBB);
18320 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18321 mainMBB->addSuccessor(sinkMBB);
18324 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18325 TII->get(X86::PHI), DstReg)
18326 .addReg(mainDstReg).addMBB(mainMBB)
18327 .addReg(restoreDstReg).addMBB(restoreMBB);
18330 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18331 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18332 restoreMBB->addSuccessor(sinkMBB);
18334 MI->eraseFromParent();
18338 MachineBasicBlock *
18339 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18340 MachineBasicBlock *MBB) const {
18341 DebugLoc DL = MI->getDebugLoc();
18342 MachineFunction *MF = MBB->getParent();
18343 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18344 MachineRegisterInfo &MRI = MF->getRegInfo();
18346 // Memory Reference
18347 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18348 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18350 MVT PVT = getPointerTy();
18351 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18352 "Invalid Pointer Size!");
18354 const TargetRegisterClass *RC =
18355 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18356 unsigned Tmp = MRI.createVirtualRegister(RC);
18357 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18359 MF->getSubtarget().getRegisterInfo());
18360 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18361 unsigned SP = RegInfo->getStackRegister();
18363 MachineInstrBuilder MIB;
18365 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18366 const int64_t SPOffset = 2 * PVT.getStoreSize();
18368 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18369 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18372 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18373 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18374 MIB.addOperand(MI->getOperand(i));
18375 MIB.setMemRefs(MMOBegin, MMOEnd);
18377 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18378 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18379 if (i == X86::AddrDisp)
18380 MIB.addDisp(MI->getOperand(i), LabelOffset);
18382 MIB.addOperand(MI->getOperand(i));
18384 MIB.setMemRefs(MMOBegin, MMOEnd);
18386 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18387 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18388 if (i == X86::AddrDisp)
18389 MIB.addDisp(MI->getOperand(i), SPOffset);
18391 MIB.addOperand(MI->getOperand(i));
18393 MIB.setMemRefs(MMOBegin, MMOEnd);
18395 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18397 MI->eraseFromParent();
18401 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18402 // accumulator loops. Writing back to the accumulator allows the coalescer
18403 // to remove extra copies in the loop.
18404 MachineBasicBlock *
18405 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18406 MachineBasicBlock *MBB) const {
18407 MachineOperand &AddendOp = MI->getOperand(3);
18409 // Bail out early if the addend isn't a register - we can't switch these.
18410 if (!AddendOp.isReg())
18413 MachineFunction &MF = *MBB->getParent();
18414 MachineRegisterInfo &MRI = MF.getRegInfo();
18416 // Check whether the addend is defined by a PHI:
18417 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18418 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18419 if (!AddendDef.isPHI())
18422 // Look for the following pattern:
18424 // %addend = phi [%entry, 0], [%loop, %result]
18426 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18430 // %addend = phi [%entry, 0], [%loop, %result]
18432 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18434 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18435 assert(AddendDef.getOperand(i).isReg());
18436 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18437 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18438 if (&PHISrcInst == MI) {
18439 // Found a matching instruction.
18440 unsigned NewFMAOpc = 0;
18441 switch (MI->getOpcode()) {
18442 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18443 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18444 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18445 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18446 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18447 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18448 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18449 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18450 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18451 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18452 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18453 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18454 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18455 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18456 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18457 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18458 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18459 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18460 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18461 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18462 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18463 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18464 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18465 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18466 default: llvm_unreachable("Unrecognized FMA variant.");
18469 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18470 MachineInstrBuilder MIB =
18471 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18472 .addOperand(MI->getOperand(0))
18473 .addOperand(MI->getOperand(3))
18474 .addOperand(MI->getOperand(2))
18475 .addOperand(MI->getOperand(1));
18476 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18477 MI->eraseFromParent();
18484 MachineBasicBlock *
18485 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18486 MachineBasicBlock *BB) const {
18487 switch (MI->getOpcode()) {
18488 default: llvm_unreachable("Unexpected instr type to insert");
18489 case X86::TAILJMPd64:
18490 case X86::TAILJMPr64:
18491 case X86::TAILJMPm64:
18492 llvm_unreachable("TAILJMP64 would not be touched here.");
18493 case X86::TCRETURNdi64:
18494 case X86::TCRETURNri64:
18495 case X86::TCRETURNmi64:
18497 case X86::WIN_ALLOCA:
18498 return EmitLoweredWinAlloca(MI, BB);
18499 case X86::SEG_ALLOCA_32:
18500 return EmitLoweredSegAlloca(MI, BB, false);
18501 case X86::SEG_ALLOCA_64:
18502 return EmitLoweredSegAlloca(MI, BB, true);
18503 case X86::TLSCall_32:
18504 case X86::TLSCall_64:
18505 return EmitLoweredTLSCall(MI, BB);
18506 case X86::CMOV_GR8:
18507 case X86::CMOV_FR32:
18508 case X86::CMOV_FR64:
18509 case X86::CMOV_V4F32:
18510 case X86::CMOV_V2F64:
18511 case X86::CMOV_V2I64:
18512 case X86::CMOV_V8F32:
18513 case X86::CMOV_V4F64:
18514 case X86::CMOV_V4I64:
18515 case X86::CMOV_V16F32:
18516 case X86::CMOV_V8F64:
18517 case X86::CMOV_V8I64:
18518 case X86::CMOV_GR16:
18519 case X86::CMOV_GR32:
18520 case X86::CMOV_RFP32:
18521 case X86::CMOV_RFP64:
18522 case X86::CMOV_RFP80:
18523 return EmitLoweredSelect(MI, BB);
18525 case X86::FP32_TO_INT16_IN_MEM:
18526 case X86::FP32_TO_INT32_IN_MEM:
18527 case X86::FP32_TO_INT64_IN_MEM:
18528 case X86::FP64_TO_INT16_IN_MEM:
18529 case X86::FP64_TO_INT32_IN_MEM:
18530 case X86::FP64_TO_INT64_IN_MEM:
18531 case X86::FP80_TO_INT16_IN_MEM:
18532 case X86::FP80_TO_INT32_IN_MEM:
18533 case X86::FP80_TO_INT64_IN_MEM: {
18534 MachineFunction *F = BB->getParent();
18535 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
18536 DebugLoc DL = MI->getDebugLoc();
18538 // Change the floating point control register to use "round towards zero"
18539 // mode when truncating to an integer value.
18540 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18541 addFrameReference(BuildMI(*BB, MI, DL,
18542 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18544 // Load the old value of the high byte of the control word...
18546 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18547 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18550 // Set the high part to be round to zero...
18551 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18554 // Reload the modified control word now...
18555 addFrameReference(BuildMI(*BB, MI, DL,
18556 TII->get(X86::FLDCW16m)), CWFrameIdx);
18558 // Restore the memory image of control word to original value
18559 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18562 // Get the X86 opcode to use.
18564 switch (MI->getOpcode()) {
18565 default: llvm_unreachable("illegal opcode!");
18566 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18567 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18568 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18569 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18570 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18571 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18572 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18573 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18574 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18578 MachineOperand &Op = MI->getOperand(0);
18580 AM.BaseType = X86AddressMode::RegBase;
18581 AM.Base.Reg = Op.getReg();
18583 AM.BaseType = X86AddressMode::FrameIndexBase;
18584 AM.Base.FrameIndex = Op.getIndex();
18586 Op = MI->getOperand(1);
18588 AM.Scale = Op.getImm();
18589 Op = MI->getOperand(2);
18591 AM.IndexReg = Op.getImm();
18592 Op = MI->getOperand(3);
18593 if (Op.isGlobal()) {
18594 AM.GV = Op.getGlobal();
18596 AM.Disp = Op.getImm();
18598 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18599 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18601 // Reload the original control word now.
18602 addFrameReference(BuildMI(*BB, MI, DL,
18603 TII->get(X86::FLDCW16m)), CWFrameIdx);
18605 MI->eraseFromParent(); // The pseudo instruction is gone now.
18608 // String/text processing lowering.
18609 case X86::PCMPISTRM128REG:
18610 case X86::VPCMPISTRM128REG:
18611 case X86::PCMPISTRM128MEM:
18612 case X86::VPCMPISTRM128MEM:
18613 case X86::PCMPESTRM128REG:
18614 case X86::VPCMPESTRM128REG:
18615 case X86::PCMPESTRM128MEM:
18616 case X86::VPCMPESTRM128MEM:
18617 assert(Subtarget->hasSSE42() &&
18618 "Target must have SSE4.2 or AVX features enabled");
18619 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18621 // String/text processing lowering.
18622 case X86::PCMPISTRIREG:
18623 case X86::VPCMPISTRIREG:
18624 case X86::PCMPISTRIMEM:
18625 case X86::VPCMPISTRIMEM:
18626 case X86::PCMPESTRIREG:
18627 case X86::VPCMPESTRIREG:
18628 case X86::PCMPESTRIMEM:
18629 case X86::VPCMPESTRIMEM:
18630 assert(Subtarget->hasSSE42() &&
18631 "Target must have SSE4.2 or AVX features enabled");
18632 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18634 // Thread synchronization.
18636 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
18641 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18643 case X86::VASTART_SAVE_XMM_REGS:
18644 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18646 case X86::VAARG_64:
18647 return EmitVAARG64WithCustomInserter(MI, BB);
18649 case X86::EH_SjLj_SetJmp32:
18650 case X86::EH_SjLj_SetJmp64:
18651 return emitEHSjLjSetJmp(MI, BB);
18653 case X86::EH_SjLj_LongJmp32:
18654 case X86::EH_SjLj_LongJmp64:
18655 return emitEHSjLjLongJmp(MI, BB);
18657 case TargetOpcode::STACKMAP:
18658 case TargetOpcode::PATCHPOINT:
18659 return emitPatchPoint(MI, BB);
18661 case X86::VFMADDPDr213r:
18662 case X86::VFMADDPSr213r:
18663 case X86::VFMADDSDr213r:
18664 case X86::VFMADDSSr213r:
18665 case X86::VFMSUBPDr213r:
18666 case X86::VFMSUBPSr213r:
18667 case X86::VFMSUBSDr213r:
18668 case X86::VFMSUBSSr213r:
18669 case X86::VFNMADDPDr213r:
18670 case X86::VFNMADDPSr213r:
18671 case X86::VFNMADDSDr213r:
18672 case X86::VFNMADDSSr213r:
18673 case X86::VFNMSUBPDr213r:
18674 case X86::VFNMSUBPSr213r:
18675 case X86::VFNMSUBSDr213r:
18676 case X86::VFNMSUBSSr213r:
18677 case X86::VFMADDPDr213rY:
18678 case X86::VFMADDPSr213rY:
18679 case X86::VFMSUBPDr213rY:
18680 case X86::VFMSUBPSr213rY:
18681 case X86::VFNMADDPDr213rY:
18682 case X86::VFNMADDPSr213rY:
18683 case X86::VFNMSUBPDr213rY:
18684 case X86::VFNMSUBPSr213rY:
18685 return emitFMA3Instr(MI, BB);
18689 //===----------------------------------------------------------------------===//
18690 // X86 Optimization Hooks
18691 //===----------------------------------------------------------------------===//
18693 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18696 const SelectionDAG &DAG,
18697 unsigned Depth) const {
18698 unsigned BitWidth = KnownZero.getBitWidth();
18699 unsigned Opc = Op.getOpcode();
18700 assert((Opc >= ISD::BUILTIN_OP_END ||
18701 Opc == ISD::INTRINSIC_WO_CHAIN ||
18702 Opc == ISD::INTRINSIC_W_CHAIN ||
18703 Opc == ISD::INTRINSIC_VOID) &&
18704 "Should use MaskedValueIsZero if you don't know whether Op"
18705 " is a target node!");
18707 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18721 // These nodes' second result is a boolean.
18722 if (Op.getResNo() == 0)
18725 case X86ISD::SETCC:
18726 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18728 case ISD::INTRINSIC_WO_CHAIN: {
18729 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18730 unsigned NumLoBits = 0;
18733 case Intrinsic::x86_sse_movmsk_ps:
18734 case Intrinsic::x86_avx_movmsk_ps_256:
18735 case Intrinsic::x86_sse2_movmsk_pd:
18736 case Intrinsic::x86_avx_movmsk_pd_256:
18737 case Intrinsic::x86_mmx_pmovmskb:
18738 case Intrinsic::x86_sse2_pmovmskb_128:
18739 case Intrinsic::x86_avx2_pmovmskb: {
18740 // High bits of movmskp{s|d}, pmovmskb are known zero.
18742 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18743 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18744 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18745 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18746 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18747 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18748 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18749 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18751 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18760 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18762 const SelectionDAG &,
18763 unsigned Depth) const {
18764 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18765 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18766 return Op.getValueType().getScalarType().getSizeInBits();
18772 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18773 /// node is a GlobalAddress + offset.
18774 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18775 const GlobalValue* &GA,
18776 int64_t &Offset) const {
18777 if (N->getOpcode() == X86ISD::Wrapper) {
18778 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18779 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18780 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18784 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18787 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18788 /// same as extracting the high 128-bit part of 256-bit vector and then
18789 /// inserting the result into the low part of a new 256-bit vector
18790 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18791 EVT VT = SVOp->getValueType(0);
18792 unsigned NumElems = VT.getVectorNumElements();
18794 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18795 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18796 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18797 SVOp->getMaskElt(j) >= 0)
18803 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18804 /// same as extracting the low 128-bit part of 256-bit vector and then
18805 /// inserting the result into the high part of a new 256-bit vector
18806 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18807 EVT VT = SVOp->getValueType(0);
18808 unsigned NumElems = VT.getVectorNumElements();
18810 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18811 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18812 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18813 SVOp->getMaskElt(j) >= 0)
18819 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18820 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18821 TargetLowering::DAGCombinerInfo &DCI,
18822 const X86Subtarget* Subtarget) {
18824 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18825 SDValue V1 = SVOp->getOperand(0);
18826 SDValue V2 = SVOp->getOperand(1);
18827 EVT VT = SVOp->getValueType(0);
18828 unsigned NumElems = VT.getVectorNumElements();
18830 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18831 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18835 // V UNDEF BUILD_VECTOR UNDEF
18837 // CONCAT_VECTOR CONCAT_VECTOR
18840 // RESULT: V + zero extended
18842 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18843 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18844 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18847 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
18850 // To match the shuffle mask, the first half of the mask should
18851 // be exactly the first vector, and all the rest a splat with the
18852 // first element of the second one.
18853 for (unsigned i = 0; i != NumElems/2; ++i)
18854 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
18855 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
18858 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
18859 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
18860 if (Ld->hasNUsesOfValue(1, 0)) {
18861 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
18862 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
18864 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
18866 Ld->getPointerInfo(),
18867 Ld->getAlignment(),
18868 false/*isVolatile*/, true/*ReadMem*/,
18869 false/*WriteMem*/);
18871 // Make sure the newly-created LOAD is in the same position as Ld in
18872 // terms of dependency. We create a TokenFactor for Ld and ResNode,
18873 // and update uses of Ld's output chain to use the TokenFactor.
18874 if (Ld->hasAnyUseOfValue(1)) {
18875 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18876 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
18877 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
18878 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
18879 SDValue(ResNode.getNode(), 1));
18882 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
18886 // Emit a zeroed vector and insert the desired subvector on its
18888 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18889 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
18890 return DCI.CombineTo(N, InsV);
18893 //===--------------------------------------------------------------------===//
18894 // Combine some shuffles into subvector extracts and inserts:
18897 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18898 if (isShuffleHigh128VectorInsertLow(SVOp)) {
18899 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
18900 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
18901 return DCI.CombineTo(N, InsV);
18904 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18905 if (isShuffleLow128VectorInsertHigh(SVOp)) {
18906 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
18907 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
18908 return DCI.CombineTo(N, InsV);
18914 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
18917 /// This is the leaf of the recursive combinine below. When we have found some
18918 /// chain of single-use x86 shuffle instructions and accumulated the combined
18919 /// shuffle mask represented by them, this will try to pattern match that mask
18920 /// into either a single instruction if there is a special purpose instruction
18921 /// for this operation, or into a PSHUFB instruction which is a fully general
18922 /// instruction but should only be used to replace chains over a certain depth.
18923 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
18924 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
18925 TargetLowering::DAGCombinerInfo &DCI,
18926 const X86Subtarget *Subtarget) {
18927 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
18929 // Find the operand that enters the chain. Note that multiple uses are OK
18930 // here, we're not going to remove the operand we find.
18931 SDValue Input = Op.getOperand(0);
18932 while (Input.getOpcode() == ISD::BITCAST)
18933 Input = Input.getOperand(0);
18935 MVT VT = Input.getSimpleValueType();
18936 MVT RootVT = Root.getSimpleValueType();
18939 // Just remove no-op shuffle masks.
18940 if (Mask.size() == 1) {
18941 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
18946 // Use the float domain if the operand type is a floating point type.
18947 bool FloatDomain = VT.isFloatingPoint();
18949 // If we don't have access to VEX encodings, the generic PSHUF instructions
18950 // are preferable to some of the specialized forms despite requiring one more
18951 // byte to encode because they can implicitly copy.
18953 // IF we *do* have VEX encodings, than we can use shorter, more specific
18954 // shuffle instructions freely as they can copy due to the extra register
18956 if (Subtarget->hasAVX()) {
18957 // We have both floating point and integer variants of shuffles that dup
18958 // either the low or high half of the vector.
18959 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
18960 bool Lo = Mask.equals(0, 0);
18961 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
18962 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
18963 if (Depth == 1 && Root->getOpcode() == Shuffle)
18964 return false; // Nothing to do!
18965 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
18966 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
18967 DCI.AddToWorklist(Op.getNode());
18968 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
18969 DCI.AddToWorklist(Op.getNode());
18970 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
18975 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
18977 // For the integer domain we have specialized instructions for duplicating
18978 // any element size from the low or high half.
18979 if (!FloatDomain &&
18980 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
18981 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
18982 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
18983 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
18984 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
18986 bool Lo = Mask[0] == 0;
18987 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
18988 if (Depth == 1 && Root->getOpcode() == Shuffle)
18989 return false; // Nothing to do!
18991 switch (Mask.size()) {
18992 case 4: ShuffleVT = MVT::v4i32; break;
18993 case 8: ShuffleVT = MVT::v8i16; break;
18994 case 16: ShuffleVT = MVT::v16i8; break;
18996 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
18997 DCI.AddToWorklist(Op.getNode());
18998 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
18999 DCI.AddToWorklist(Op.getNode());
19000 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19006 // Don't try to re-form single instruction chains under any circumstances now
19007 // that we've done encoding canonicalization for them.
19011 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19012 // can replace them with a single PSHUFB instruction profitably. Intel's
19013 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19014 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19015 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19016 SmallVector<SDValue, 16> PSHUFBMask;
19017 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19018 int Ratio = 16 / Mask.size();
19019 for (unsigned i = 0; i < 16; ++i) {
19020 int M = Ratio * Mask[i / Ratio] + i % Ratio;
19021 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19023 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19024 DCI.AddToWorklist(Op.getNode());
19025 SDValue PSHUFBMaskOp =
19026 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19027 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19028 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19029 DCI.AddToWorklist(Op.getNode());
19030 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19035 // Failed to find any combines.
19039 /// \brief Fully generic combining of x86 shuffle instructions.
19041 /// This should be the last combine run over the x86 shuffle instructions. Once
19042 /// they have been fully optimized, this will recursively consdier all chains
19043 /// of single-use shuffle instructions, build a generic model of the cumulative
19044 /// shuffle operation, and check for simpler instructions which implement this
19045 /// operation. We use this primarily for two purposes:
19047 /// 1) Collapse generic shuffles to specialized single instructions when
19048 /// equivalent. In most cases, this is just an encoding size win, but
19049 /// sometimes we will collapse multiple generic shuffles into a single
19050 /// special-purpose shuffle.
19051 /// 2) Look for sequences of shuffle instructions with 3 or more total
19052 /// instructions, and replace them with the slightly more expensive SSSE3
19053 /// PSHUFB instruction if available. We do this as the last combining step
19054 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19055 /// a suitable short sequence of other instructions. The PHUFB will either
19056 /// use a register or have to read from memory and so is slightly (but only
19057 /// slightly) more expensive than the other shuffle instructions.
19059 /// Because this is inherently a quadratic operation (for each shuffle in
19060 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19061 /// This should never be an issue in practice as the shuffle lowering doesn't
19062 /// produce sequences of more than 8 instructions.
19064 /// FIXME: We will currently miss some cases where the redundant shuffling
19065 /// would simplify under the threshold for PSHUFB formation because of
19066 /// combine-ordering. To fix this, we should do the redundant instruction
19067 /// combining in this recursive walk.
19068 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19069 ArrayRef<int> IncomingMask, int Depth,
19070 bool HasPSHUFB, SelectionDAG &DAG,
19071 TargetLowering::DAGCombinerInfo &DCI,
19072 const X86Subtarget *Subtarget) {
19073 // Bound the depth of our recursive combine because this is ultimately
19074 // quadratic in nature.
19078 // Directly rip through bitcasts to find the underlying operand.
19079 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19080 Op = Op.getOperand(0);
19082 MVT VT = Op.getSimpleValueType();
19083 if (!VT.isVector())
19084 return false; // Bail if we hit a non-vector.
19085 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19086 // version should be added.
19087 if (VT.getSizeInBits() != 128)
19090 assert(Root.getSimpleValueType().isVector() &&
19091 "Shuffles operate on vector types!");
19092 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19093 "Can only combine shuffles of the same vector register size.");
19095 if (!isTargetShuffle(Op.getOpcode()))
19097 SmallVector<int, 16> OpMask;
19099 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19100 // We only can combine unary shuffles which we can decode the mask for.
19101 if (!HaveMask || !IsUnary)
19104 assert(VT.getVectorNumElements() == OpMask.size() &&
19105 "Different mask size from vector size!");
19107 SmallVector<int, 16> Mask;
19108 Mask.reserve(std::max(OpMask.size(), IncomingMask.size()));
19110 // Merge this shuffle operation's mask into our accumulated mask. This is
19111 // a bit tricky as the shuffle may have a different size from the root.
19112 if (OpMask.size() == IncomingMask.size()) {
19113 for (int M : IncomingMask)
19114 Mask.push_back(OpMask[M]);
19115 } else if (OpMask.size() < IncomingMask.size()) {
19116 assert(IncomingMask.size() % OpMask.size() == 0 &&
19117 "The smaller number of elements must divide the larger.");
19118 int Ratio = IncomingMask.size() / OpMask.size();
19119 for (int M : IncomingMask)
19120 Mask.push_back(Ratio * OpMask[M / Ratio] + M % Ratio);
19122 assert(OpMask.size() > IncomingMask.size() && "All other cases handled!");
19123 assert(OpMask.size() % IncomingMask.size() == 0 &&
19124 "The smaller number of elements must divide the larger.");
19125 int Ratio = OpMask.size() / IncomingMask.size();
19126 for (int i = 0, e = OpMask.size(); i < e; ++i)
19127 Mask.push_back(OpMask[Ratio * IncomingMask[i / Ratio] + i % Ratio]);
19130 // See if we can recurse into the operand to combine more things.
19131 switch (Op.getOpcode()) {
19132 case X86ISD::PSHUFB:
19134 case X86ISD::PSHUFD:
19135 case X86ISD::PSHUFHW:
19136 case X86ISD::PSHUFLW:
19137 if (Op.getOperand(0).hasOneUse() &&
19138 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19139 HasPSHUFB, DAG, DCI, Subtarget))
19143 case X86ISD::UNPCKL:
19144 case X86ISD::UNPCKH:
19145 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19146 // We can't check for single use, we have to check that this shuffle is the only user.
19147 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19148 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19149 HasPSHUFB, DAG, DCI, Subtarget))
19154 // Minor canonicalization of the accumulated shuffle mask to make it easier
19155 // to match below. All this does is detect masks with squential pairs of
19156 // elements, and shrink them to the half-width mask. It does this in a loop
19157 // so it will reduce the size of the mask to the minimal width mask which
19158 // performs an equivalent shuffle.
19159 while (Mask.size() > 1) {
19160 SmallVector<int, 16> NewMask;
19161 for (int i = 0, e = Mask.size()/2; i < e; ++i) {
19162 if (Mask[2*i] % 2 != 0 || Mask[2*i] != Mask[2*i + 1] + 1) {
19166 NewMask.push_back(Mask[2*i] / 2);
19168 if (NewMask.empty())
19170 Mask.swap(NewMask);
19173 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19177 /// \brief Get the PSHUF-style mask from PSHUF node.
19179 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19180 /// PSHUF-style masks that can be reused with such instructions.
19181 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19182 SmallVector<int, 4> Mask;
19184 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19188 switch (N.getOpcode()) {
19189 case X86ISD::PSHUFD:
19191 case X86ISD::PSHUFLW:
19194 case X86ISD::PSHUFHW:
19195 Mask.erase(Mask.begin(), Mask.begin() + 4);
19196 for (int &M : Mask)
19200 llvm_unreachable("No valid shuffle instruction found!");
19204 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19206 /// We walk up the chain and look for a combinable shuffle, skipping over
19207 /// shuffles that we could hoist this shuffle's transformation past without
19208 /// altering anything.
19209 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19211 TargetLowering::DAGCombinerInfo &DCI) {
19212 assert(N.getOpcode() == X86ISD::PSHUFD &&
19213 "Called with something other than an x86 128-bit half shuffle!");
19216 // Walk up a single-use chain looking for a combinable shuffle.
19217 SDValue V = N.getOperand(0);
19218 for (; V.hasOneUse(); V = V.getOperand(0)) {
19219 switch (V.getOpcode()) {
19221 return false; // Nothing combined!
19224 // Skip bitcasts as we always know the type for the target specific
19228 case X86ISD::PSHUFD:
19229 // Found another dword shuffle.
19232 case X86ISD::PSHUFLW:
19233 // Check that the low words (being shuffled) are the identity in the
19234 // dword shuffle, and the high words are self-contained.
19235 if (Mask[0] != 0 || Mask[1] != 1 ||
19236 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19241 case X86ISD::PSHUFHW:
19242 // Check that the high words (being shuffled) are the identity in the
19243 // dword shuffle, and the low words are self-contained.
19244 if (Mask[2] != 2 || Mask[3] != 3 ||
19245 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19250 case X86ISD::UNPCKL:
19251 case X86ISD::UNPCKH:
19252 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19253 // shuffle into a preceding word shuffle.
19254 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19257 // Search for a half-shuffle which we can combine with.
19258 unsigned CombineOp =
19259 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19260 if (V.getOperand(0) != V.getOperand(1) ||
19261 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19263 V = V.getOperand(0);
19265 switch (V.getOpcode()) {
19267 return false; // Nothing to combine.
19269 case X86ISD::PSHUFLW:
19270 case X86ISD::PSHUFHW:
19271 if (V.getOpcode() == CombineOp)
19276 V = V.getOperand(0);
19280 } while (V.hasOneUse());
19283 // Break out of the loop if we break out of the switch.
19287 if (!V.hasOneUse())
19288 // We fell out of the loop without finding a viable combining instruction.
19291 // Record the old value to use in RAUW-ing.
19294 // Merge this node's mask and our incoming mask.
19295 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19296 for (int &M : Mask)
19298 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19299 getV4X86ShuffleImm8ForMask(Mask, DAG));
19301 // It is possible that one of the combinable shuffles was completely absorbed
19302 // by the other, just replace it and revisit all users in that case.
19303 if (Old.getNode() == V.getNode()) {
19304 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
19308 // Replace N with its operand as we're going to combine that shuffle away.
19309 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
19311 // Replace the combinable shuffle with the combined one, updating all users
19312 // so that we re-evaluate the chain here.
19313 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19317 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19319 /// We walk up the chain, skipping shuffles of the other half and looking
19320 /// through shuffles which switch halves trying to find a shuffle of the same
19321 /// pair of dwords.
19322 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19324 TargetLowering::DAGCombinerInfo &DCI) {
19326 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19327 "Called with something other than an x86 128-bit half shuffle!");
19329 unsigned CombineOpcode = N.getOpcode();
19331 // Walk up a single-use chain looking for a combinable shuffle.
19332 SDValue V = N.getOperand(0);
19333 for (; V.hasOneUse(); V = V.getOperand(0)) {
19334 switch (V.getOpcode()) {
19336 return false; // Nothing combined!
19339 // Skip bitcasts as we always know the type for the target specific
19343 case X86ISD::PSHUFLW:
19344 case X86ISD::PSHUFHW:
19345 if (V.getOpcode() == CombineOpcode)
19348 // Other-half shuffles are no-ops.
19351 case X86ISD::PSHUFD: {
19352 // We can only handle pshufd if the half we are combining either stays in
19353 // its half, or switches to the other half. Bail if one of these isn't
19355 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19356 int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
19357 if (!((VMask[DOffset + 0] < 2 && VMask[DOffset + 1] < 2) ||
19358 (VMask[DOffset + 0] >= 2 && VMask[DOffset + 1] >= 2)))
19361 // Map the mask through the pshufd and keep walking up the chain.
19362 for (int i = 0; i < 4; ++i)
19363 Mask[i] = 2 * (VMask[DOffset + Mask[i] / 2] % 2) + Mask[i] % 2;
19365 // Switch halves if the pshufd does.
19367 VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19371 // Break out of the loop if we break out of the switch.
19375 if (!V.hasOneUse())
19376 // We fell out of the loop without finding a viable combining instruction.
19379 // Record the old value to use in RAUW-ing.
19382 // Merge this node's mask and our incoming mask (adjusted to account for all
19383 // the pshufd instructions encountered).
19384 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19385 for (int &M : Mask)
19387 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19388 getV4X86ShuffleImm8ForMask(Mask, DAG));
19390 // Replace N with its operand as we're going to combine that shuffle away.
19391 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
19393 // Replace the combinable shuffle with the combined one, updating all users
19394 // so that we re-evaluate the chain here.
19395 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19399 /// \brief Try to combine x86 target specific shuffles.
19400 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19401 TargetLowering::DAGCombinerInfo &DCI,
19402 const X86Subtarget *Subtarget) {
19404 MVT VT = N.getSimpleValueType();
19405 SmallVector<int, 4> Mask;
19407 switch (N.getOpcode()) {
19408 case X86ISD::PSHUFD:
19409 case X86ISD::PSHUFLW:
19410 case X86ISD::PSHUFHW:
19411 Mask = getPSHUFShuffleMask(N);
19412 assert(Mask.size() == 4);
19418 // Nuke no-op shuffles that show up after combining.
19419 if (isNoopShuffleMask(Mask))
19420 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19422 // Look for simplifications involving one or two shuffle instructions.
19423 SDValue V = N.getOperand(0);
19424 switch (N.getOpcode()) {
19427 case X86ISD::PSHUFLW:
19428 case X86ISD::PSHUFHW:
19429 assert(VT == MVT::v8i16);
19432 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19433 return SDValue(); // We combined away this shuffle, so we're done.
19435 // See if this reduces to a PSHUFD which is no more expensive and can
19436 // combine with more operations.
19437 if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
19438 areAdjacentMasksSequential(Mask)) {
19439 int DMask[] = {-1, -1, -1, -1};
19440 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19441 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19442 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19443 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19444 DCI.AddToWorklist(V.getNode());
19445 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19446 getV4X86ShuffleImm8ForMask(DMask, DAG));
19447 DCI.AddToWorklist(V.getNode());
19448 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19451 // Look for shuffle patterns which can be implemented as a single unpack.
19452 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19453 // only works when we have a PSHUFD followed by two half-shuffles.
19454 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19455 (V.getOpcode() == X86ISD::PSHUFLW ||
19456 V.getOpcode() == X86ISD::PSHUFHW) &&
19457 V.getOpcode() != N.getOpcode() &&
19459 SDValue D = V.getOperand(0);
19460 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19461 D = D.getOperand(0);
19462 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19463 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19464 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19465 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19466 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19468 for (int i = 0; i < 4; ++i) {
19469 WordMask[i + NOffset] = Mask[i] + NOffset;
19470 WordMask[i + VOffset] = VMask[i] + VOffset;
19472 // Map the word mask through the DWord mask.
19474 for (int i = 0; i < 8; ++i)
19475 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19476 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19477 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19478 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19479 std::begin(UnpackLoMask)) ||
19480 std::equal(std::begin(MappedMask), std::end(MappedMask),
19481 std::begin(UnpackHiMask))) {
19482 // We can replace all three shuffles with an unpack.
19483 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19484 DCI.AddToWorklist(V.getNode());
19485 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19487 DL, MVT::v8i16, V, V);
19494 case X86ISD::PSHUFD:
19495 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19496 return SDValue(); // We combined away this shuffle.
19504 /// PerformShuffleCombine - Performs several different shuffle combines.
19505 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19506 TargetLowering::DAGCombinerInfo &DCI,
19507 const X86Subtarget *Subtarget) {
19509 SDValue N0 = N->getOperand(0);
19510 SDValue N1 = N->getOperand(1);
19511 EVT VT = N->getValueType(0);
19513 // Don't create instructions with illegal types after legalize types has run.
19514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19515 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19518 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19519 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19520 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19521 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19523 // During Type Legalization, when promoting illegal vector types,
19524 // the backend might introduce new shuffle dag nodes and bitcasts.
19526 // This code performs the following transformation:
19527 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19528 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19530 // We do this only if both the bitcast and the BINOP dag nodes have
19531 // one use. Also, perform this transformation only if the new binary
19532 // operation is legal. This is to avoid introducing dag nodes that
19533 // potentially need to be further expanded (or custom lowered) into a
19534 // less optimal sequence of dag nodes.
19535 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19536 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19537 N0.getOpcode() == ISD::BITCAST) {
19538 SDValue BC0 = N0.getOperand(0);
19539 EVT SVT = BC0.getValueType();
19540 unsigned Opcode = BC0.getOpcode();
19541 unsigned NumElts = VT.getVectorNumElements();
19543 if (BC0.hasOneUse() && SVT.isVector() &&
19544 SVT.getVectorNumElements() * 2 == NumElts &&
19545 TLI.isOperationLegal(Opcode, VT)) {
19546 bool CanFold = false;
19558 unsigned SVTNumElts = SVT.getVectorNumElements();
19559 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19560 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19561 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19562 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19563 CanFold = SVOp->getMaskElt(i) < 0;
19566 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19567 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19568 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19569 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
19574 // Only handle 128 wide vector from here on.
19575 if (!VT.is128BitVector())
19578 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19579 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
19580 // consecutive, non-overlapping, and in the right order.
19581 SmallVector<SDValue, 16> Elts;
19582 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
19583 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
19585 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
19589 if (isTargetShuffle(N->getOpcode())) {
19591 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
19592 if (Shuffle.getNode())
19595 // Try recursively combining arbitrary sequences of x86 shuffle
19596 // instructions into higher-order shuffles. We do this after combining
19597 // specific PSHUF instruction sequences into their minimal form so that we
19598 // can evaluate how many specialized shuffle instructions are involved in
19599 // a particular chain.
19600 SmallVector<int, 1> NonceMask; // Just a placeholder.
19601 NonceMask.push_back(0);
19602 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
19603 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
19605 return SDValue(); // This routine will use CombineTo to replace N.
19611 /// PerformTruncateCombine - Converts truncate operation to
19612 /// a sequence of vector shuffle operations.
19613 /// It is possible when we truncate 256-bit vector to 128-bit vector
19614 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
19615 TargetLowering::DAGCombinerInfo &DCI,
19616 const X86Subtarget *Subtarget) {
19620 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
19621 /// specific shuffle of a load can be folded into a single element load.
19622 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
19623 /// shuffles have been customed lowered so we need to handle those here.
19624 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
19625 TargetLowering::DAGCombinerInfo &DCI) {
19626 if (DCI.isBeforeLegalizeOps())
19629 SDValue InVec = N->getOperand(0);
19630 SDValue EltNo = N->getOperand(1);
19632 if (!isa<ConstantSDNode>(EltNo))
19635 EVT VT = InVec.getValueType();
19637 bool HasShuffleIntoBitcast = false;
19638 if (InVec.getOpcode() == ISD::BITCAST) {
19639 // Don't duplicate a load with other uses.
19640 if (!InVec.hasOneUse())
19642 EVT BCVT = InVec.getOperand(0).getValueType();
19643 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
19645 InVec = InVec.getOperand(0);
19646 HasShuffleIntoBitcast = true;
19649 if (!isTargetShuffle(InVec.getOpcode()))
19652 // Don't duplicate a load with other uses.
19653 if (!InVec.hasOneUse())
19656 SmallVector<int, 16> ShuffleMask;
19658 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
19662 // Select the input vector, guarding against out of range extract vector.
19663 unsigned NumElems = VT.getVectorNumElements();
19664 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
19665 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
19666 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
19667 : InVec.getOperand(1);
19669 // If inputs to shuffle are the same for both ops, then allow 2 uses
19670 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
19672 if (LdNode.getOpcode() == ISD::BITCAST) {
19673 // Don't duplicate a load with other uses.
19674 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
19677 AllowedUses = 1; // only allow 1 load use if we have a bitcast
19678 LdNode = LdNode.getOperand(0);
19681 if (!ISD::isNormalLoad(LdNode.getNode()))
19684 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
19686 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
19689 if (HasShuffleIntoBitcast) {
19690 // If there's a bitcast before the shuffle, check if the load type and
19691 // alignment is valid.
19692 unsigned Align = LN0->getAlignment();
19693 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19694 unsigned NewAlign = TLI.getDataLayout()->
19695 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
19697 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
19701 // All checks match so transform back to vector_shuffle so that DAG combiner
19702 // can finish the job
19705 // Create shuffle node taking into account the case that its a unary shuffle
19706 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
19707 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
19708 InVec.getOperand(0), Shuffle,
19710 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
19711 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
19715 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
19716 /// generation and convert it from being a bunch of shuffles and extracts
19717 /// to a simple store and scalar loads to extract the elements.
19718 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
19719 TargetLowering::DAGCombinerInfo &DCI) {
19720 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
19721 if (NewOp.getNode())
19724 SDValue InputVector = N->getOperand(0);
19726 // Detect whether we are trying to convert from mmx to i32 and the bitcast
19727 // from mmx to v2i32 has a single usage.
19728 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
19729 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
19730 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
19731 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
19732 N->getValueType(0),
19733 InputVector.getNode()->getOperand(0));
19735 // Only operate on vectors of 4 elements, where the alternative shuffling
19736 // gets to be more expensive.
19737 if (InputVector.getValueType() != MVT::v4i32)
19740 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
19741 // single use which is a sign-extend or zero-extend, and all elements are
19743 SmallVector<SDNode *, 4> Uses;
19744 unsigned ExtractedElements = 0;
19745 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
19746 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
19747 if (UI.getUse().getResNo() != InputVector.getResNo())
19750 SDNode *Extract = *UI;
19751 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
19754 if (Extract->getValueType(0) != MVT::i32)
19756 if (!Extract->hasOneUse())
19758 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
19759 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
19761 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
19764 // Record which element was extracted.
19765 ExtractedElements |=
19766 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
19768 Uses.push_back(Extract);
19771 // If not all the elements were used, this may not be worthwhile.
19772 if (ExtractedElements != 15)
19775 // Ok, we've now decided to do the transformation.
19776 SDLoc dl(InputVector);
19778 // Store the value to a temporary stack slot.
19779 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
19780 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
19781 MachinePointerInfo(), false, false, 0);
19783 // Replace each use (extract) with a load of the appropriate element.
19784 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
19785 UE = Uses.end(); UI != UE; ++UI) {
19786 SDNode *Extract = *UI;
19788 // cOMpute the element's address.
19789 SDValue Idx = Extract->getOperand(1);
19791 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
19792 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
19793 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19794 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
19796 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
19797 StackPtr, OffsetVal);
19799 // Load the scalar.
19800 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
19801 ScalarAddr, MachinePointerInfo(),
19802 false, false, false, 0);
19804 // Replace the exact with the load.
19805 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
19808 // The replacement was made in place; don't return anything.
19812 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
19813 static std::pair<unsigned, bool>
19814 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
19815 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
19816 if (!VT.isVector())
19817 return std::make_pair(0, false);
19819 bool NeedSplit = false;
19820 switch (VT.getSimpleVT().SimpleTy) {
19821 default: return std::make_pair(0, false);
19825 if (!Subtarget->hasAVX2())
19827 if (!Subtarget->hasAVX())
19828 return std::make_pair(0, false);
19833 if (!Subtarget->hasSSE2())
19834 return std::make_pair(0, false);
19837 // SSE2 has only a small subset of the operations.
19838 bool hasUnsigned = Subtarget->hasSSE41() ||
19839 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19840 bool hasSigned = Subtarget->hasSSE41() ||
19841 (Subtarget->hasSSE2() && VT == MVT::v8i16);
19843 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19846 // Check for x CC y ? x : y.
19847 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19848 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19853 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19856 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19859 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19862 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19864 // Check for x CC y ? y : x -- a min/max with reversed arms.
19865 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19866 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19871 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19874 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19877 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19880 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19884 return std::make_pair(Opc, NeedSplit);
19888 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
19889 const X86Subtarget *Subtarget) {
19891 SDValue Cond = N->getOperand(0);
19892 SDValue LHS = N->getOperand(1);
19893 SDValue RHS = N->getOperand(2);
19895 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19896 SDValue CondSrc = Cond->getOperand(0);
19897 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
19898 Cond = CondSrc->getOperand(0);
19901 MVT VT = N->getSimpleValueType(0);
19902 MVT EltVT = VT.getVectorElementType();
19903 unsigned NumElems = VT.getVectorNumElements();
19904 // There is no blend with immediate in AVX-512.
19905 if (VT.is512BitVector())
19908 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
19910 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19913 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
19916 unsigned MaskValue = 0;
19917 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
19920 SmallVector<int, 8> ShuffleMask(NumElems, -1);
19921 for (unsigned i = 0; i < NumElems; ++i) {
19922 // Be sure we emit undef where we can.
19923 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
19924 ShuffleMask[i] = -1;
19926 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
19929 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
19932 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
19934 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
19935 TargetLowering::DAGCombinerInfo &DCI,
19936 const X86Subtarget *Subtarget) {
19938 SDValue Cond = N->getOperand(0);
19939 // Get the LHS/RHS of the select.
19940 SDValue LHS = N->getOperand(1);
19941 SDValue RHS = N->getOperand(2);
19942 EVT VT = LHS.getValueType();
19943 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19945 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
19946 // instructions match the semantics of the common C idiom x<y?x:y but not
19947 // x<=y?x:y, because of how they handle negative zero (which can be
19948 // ignored in unsafe-math mode).
19949 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
19950 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
19951 (Subtarget->hasSSE2() ||
19952 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
19953 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19955 unsigned Opcode = 0;
19956 // Check for x CC y ? x : y.
19957 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19958 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19962 // Converting this to a min would handle NaNs incorrectly, and swapping
19963 // the operands would cause it to handle comparisons between positive
19964 // and negative zero incorrectly.
19965 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19966 if (!DAG.getTarget().Options.UnsafeFPMath &&
19967 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19969 std::swap(LHS, RHS);
19971 Opcode = X86ISD::FMIN;
19974 // Converting this to a min would handle comparisons between positive
19975 // and negative zero incorrectly.
19976 if (!DAG.getTarget().Options.UnsafeFPMath &&
19977 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19979 Opcode = X86ISD::FMIN;
19982 // Converting this to a min would handle both negative zeros and NaNs
19983 // incorrectly, but we can swap the operands to fix both.
19984 std::swap(LHS, RHS);
19988 Opcode = X86ISD::FMIN;
19992 // Converting this to a max would handle comparisons between positive
19993 // and negative zero incorrectly.
19994 if (!DAG.getTarget().Options.UnsafeFPMath &&
19995 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19997 Opcode = X86ISD::FMAX;
20000 // Converting this to a max would handle NaNs incorrectly, and swapping
20001 // the operands would cause it to handle comparisons between positive
20002 // and negative zero incorrectly.
20003 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20004 if (!DAG.getTarget().Options.UnsafeFPMath &&
20005 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20007 std::swap(LHS, RHS);
20009 Opcode = X86ISD::FMAX;
20012 // Converting this to a max would handle both negative zeros and NaNs
20013 // incorrectly, but we can swap the operands to fix both.
20014 std::swap(LHS, RHS);
20018 Opcode = X86ISD::FMAX;
20021 // Check for x CC y ? y : x -- a min/max with reversed arms.
20022 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20023 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20027 // Converting this to a min would handle comparisons between positive
20028 // and negative zero incorrectly, and swapping the operands would
20029 // cause it to handle NaNs incorrectly.
20030 if (!DAG.getTarget().Options.UnsafeFPMath &&
20031 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20032 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20034 std::swap(LHS, RHS);
20036 Opcode = X86ISD::FMIN;
20039 // Converting this to a min would handle NaNs incorrectly.
20040 if (!DAG.getTarget().Options.UnsafeFPMath &&
20041 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20043 Opcode = X86ISD::FMIN;
20046 // Converting this to a min would handle both negative zeros and NaNs
20047 // incorrectly, but we can swap the operands to fix both.
20048 std::swap(LHS, RHS);
20052 Opcode = X86ISD::FMIN;
20056 // Converting this to a max would handle NaNs incorrectly.
20057 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20059 Opcode = X86ISD::FMAX;
20062 // Converting this to a max would handle comparisons between positive
20063 // and negative zero incorrectly, and swapping the operands would
20064 // cause it to handle NaNs incorrectly.
20065 if (!DAG.getTarget().Options.UnsafeFPMath &&
20066 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20067 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20069 std::swap(LHS, RHS);
20071 Opcode = X86ISD::FMAX;
20074 // Converting this to a max would handle both negative zeros and NaNs
20075 // incorrectly, but we can swap the operands to fix both.
20076 std::swap(LHS, RHS);
20080 Opcode = X86ISD::FMAX;
20086 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20089 EVT CondVT = Cond.getValueType();
20090 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20091 CondVT.getVectorElementType() == MVT::i1) {
20092 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20093 // lowering on AVX-512. In this case we convert it to
20094 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20095 // The same situation for all 128 and 256-bit vectors of i8 and i16
20096 EVT OpVT = LHS.getValueType();
20097 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20098 (OpVT.getVectorElementType() == MVT::i8 ||
20099 OpVT.getVectorElementType() == MVT::i16)) {
20100 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20101 DCI.AddToWorklist(Cond.getNode());
20102 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20105 // If this is a select between two integer constants, try to do some
20107 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20108 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20109 // Don't do this for crazy integer types.
20110 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20111 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20112 // so that TrueC (the true value) is larger than FalseC.
20113 bool NeedsCondInvert = false;
20115 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20116 // Efficiently invertible.
20117 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20118 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20119 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20120 NeedsCondInvert = true;
20121 std::swap(TrueC, FalseC);
20124 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20125 if (FalseC->getAPIntValue() == 0 &&
20126 TrueC->getAPIntValue().isPowerOf2()) {
20127 if (NeedsCondInvert) // Invert the condition if needed.
20128 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20129 DAG.getConstant(1, Cond.getValueType()));
20131 // Zero extend the condition if needed.
20132 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20134 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20135 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20136 DAG.getConstant(ShAmt, MVT::i8));
20139 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20140 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20141 if (NeedsCondInvert) // Invert the condition if needed.
20142 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20143 DAG.getConstant(1, Cond.getValueType()));
20145 // Zero extend the condition if needed.
20146 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20147 FalseC->getValueType(0), Cond);
20148 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20149 SDValue(FalseC, 0));
20152 // Optimize cases that will turn into an LEA instruction. This requires
20153 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20154 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20155 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20156 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20158 bool isFastMultiplier = false;
20160 switch ((unsigned char)Diff) {
20162 case 1: // result = add base, cond
20163 case 2: // result = lea base( , cond*2)
20164 case 3: // result = lea base(cond, cond*2)
20165 case 4: // result = lea base( , cond*4)
20166 case 5: // result = lea base(cond, cond*4)
20167 case 8: // result = lea base( , cond*8)
20168 case 9: // result = lea base(cond, cond*8)
20169 isFastMultiplier = true;
20174 if (isFastMultiplier) {
20175 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20176 if (NeedsCondInvert) // Invert the condition if needed.
20177 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20178 DAG.getConstant(1, Cond.getValueType()));
20180 // Zero extend the condition if needed.
20181 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20183 // Scale the condition by the difference.
20185 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20186 DAG.getConstant(Diff, Cond.getValueType()));
20188 // Add the base if non-zero.
20189 if (FalseC->getAPIntValue() != 0)
20190 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20191 SDValue(FalseC, 0));
20198 // Canonicalize max and min:
20199 // (x > y) ? x : y -> (x >= y) ? x : y
20200 // (x < y) ? x : y -> (x <= y) ? x : y
20201 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20202 // the need for an extra compare
20203 // against zero. e.g.
20204 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20206 // testl %edi, %edi
20208 // cmovgl %edi, %eax
20212 // cmovsl %eax, %edi
20213 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20214 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20215 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20216 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20221 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20222 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20223 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20224 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20229 // Early exit check
20230 if (!TLI.isTypeLegal(VT))
20233 // Match VSELECTs into subs with unsigned saturation.
20234 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20235 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20236 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20237 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20238 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20240 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20241 // left side invert the predicate to simplify logic below.
20243 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20245 CC = ISD::getSetCCInverse(CC, true);
20246 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20250 if (Other.getNode() && Other->getNumOperands() == 2 &&
20251 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20252 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20253 SDValue CondRHS = Cond->getOperand(1);
20255 // Look for a general sub with unsigned saturation first.
20256 // x >= y ? x-y : 0 --> subus x, y
20257 // x > y ? x-y : 0 --> subus x, y
20258 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20259 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20260 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20262 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20263 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20264 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20265 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20266 // If the RHS is a constant we have to reverse the const
20267 // canonicalization.
20268 // x > C-1 ? x+-C : 0 --> subus x, C
20269 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20270 CondRHSConst->getAPIntValue() ==
20271 (-OpRHSConst->getAPIntValue() - 1))
20272 return DAG.getNode(
20273 X86ISD::SUBUS, DL, VT, OpLHS,
20274 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20276 // Another special case: If C was a sign bit, the sub has been
20277 // canonicalized into a xor.
20278 // FIXME: Would it be better to use computeKnownBits to determine
20279 // whether it's safe to decanonicalize the xor?
20280 // x s< 0 ? x^C : 0 --> subus x, C
20281 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20282 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20283 OpRHSConst->getAPIntValue().isSignBit())
20284 // Note that we have to rebuild the RHS constant here to ensure we
20285 // don't rely on particular values of undef lanes.
20286 return DAG.getNode(
20287 X86ISD::SUBUS, DL, VT, OpLHS,
20288 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20293 // Try to match a min/max vector operation.
20294 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20295 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20296 unsigned Opc = ret.first;
20297 bool NeedSplit = ret.second;
20299 if (Opc && NeedSplit) {
20300 unsigned NumElems = VT.getVectorNumElements();
20301 // Extract the LHS vectors
20302 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20303 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20305 // Extract the RHS vectors
20306 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20307 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20309 // Create min/max for each subvector
20310 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20311 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20313 // Merge the result
20314 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20316 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20319 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20320 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20321 // Check if SETCC has already been promoted
20322 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20323 // Check that condition value type matches vselect operand type
20326 assert(Cond.getValueType().isVector() &&
20327 "vector select expects a vector selector!");
20329 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20330 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20332 if (!TValIsAllOnes && !FValIsAllZeros) {
20333 // Try invert the condition if true value is not all 1s and false value
20335 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20336 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20338 if (TValIsAllZeros || FValIsAllOnes) {
20339 SDValue CC = Cond.getOperand(2);
20340 ISD::CondCode NewCC =
20341 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20342 Cond.getOperand(0).getValueType().isInteger());
20343 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20344 std::swap(LHS, RHS);
20345 TValIsAllOnes = FValIsAllOnes;
20346 FValIsAllZeros = TValIsAllZeros;
20350 if (TValIsAllOnes || FValIsAllZeros) {
20353 if (TValIsAllOnes && FValIsAllZeros)
20355 else if (TValIsAllOnes)
20356 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20357 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20358 else if (FValIsAllZeros)
20359 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20360 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20362 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20366 // Try to fold this VSELECT into a MOVSS/MOVSD
20367 if (N->getOpcode() == ISD::VSELECT &&
20368 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20369 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20370 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20371 bool CanFold = false;
20372 unsigned NumElems = Cond.getNumOperands();
20376 if (isZero(Cond.getOperand(0))) {
20379 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20380 // fold (vselect <0,-1> -> (movsd A, B)
20381 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20382 CanFold = isAllOnes(Cond.getOperand(i));
20383 } else if (isAllOnes(Cond.getOperand(0))) {
20387 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20388 // fold (vselect <-1,0> -> (movsd B, A)
20389 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20390 CanFold = isZero(Cond.getOperand(i));
20394 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20395 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20396 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20399 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20400 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20401 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20402 // (v2i64 (bitcast B)))))
20404 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20405 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20406 // (v2f64 (bitcast B)))))
20408 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20409 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20410 // (v2i64 (bitcast A)))))
20412 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20413 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20414 // (v2f64 (bitcast A)))))
20416 CanFold = (isZero(Cond.getOperand(0)) &&
20417 isZero(Cond.getOperand(1)) &&
20418 isAllOnes(Cond.getOperand(2)) &&
20419 isAllOnes(Cond.getOperand(3)));
20421 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20422 isAllOnes(Cond.getOperand(1)) &&
20423 isZero(Cond.getOperand(2)) &&
20424 isZero(Cond.getOperand(3))) {
20426 std::swap(LHS, RHS);
20430 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20431 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20432 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20433 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20435 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20441 // If we know that this node is legal then we know that it is going to be
20442 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20443 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20444 // to simplify previous instructions.
20445 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20446 !DCI.isBeforeLegalize() &&
20447 // We explicitly check against v8i16 and v16i16 because, although
20448 // they're marked as Custom, they might only be legal when Cond is a
20449 // build_vector of constants. This will be taken care in a later
20451 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20452 VT != MVT::v8i16)) {
20453 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20455 // Don't optimize vector selects that map to mask-registers.
20459 // Check all uses of that condition operand to check whether it will be
20460 // consumed by non-BLEND instructions, which may depend on all bits are set
20462 for (SDNode::use_iterator I = Cond->use_begin(),
20463 E = Cond->use_end(); I != E; ++I)
20464 if (I->getOpcode() != ISD::VSELECT)
20465 // TODO: Add other opcodes eventually lowered into BLEND.
20468 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20469 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20471 APInt KnownZero, KnownOne;
20472 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20473 DCI.isBeforeLegalizeOps());
20474 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20475 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20476 DCI.CommitTargetLoweringOpt(TLO);
20479 // We should generate an X86ISD::BLENDI from a vselect if its argument
20480 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20481 // constants. This specific pattern gets generated when we split a
20482 // selector for a 512 bit vector in a machine without AVX512 (but with
20483 // 256-bit vectors), during legalization:
20485 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20487 // Iff we find this pattern and the build_vectors are built from
20488 // constants, we translate the vselect into a shuffle_vector that we
20489 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20490 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20491 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20492 if (Shuffle.getNode())
20499 // Check whether a boolean test is testing a boolean value generated by
20500 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20503 // Simplify the following patterns:
20504 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20505 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20506 // to (Op EFLAGS Cond)
20508 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20509 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20510 // to (Op EFLAGS !Cond)
20512 // where Op could be BRCOND or CMOV.
20514 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20515 // Quit if not CMP and SUB with its value result used.
20516 if (Cmp.getOpcode() != X86ISD::CMP &&
20517 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20520 // Quit if not used as a boolean value.
20521 if (CC != X86::COND_E && CC != X86::COND_NE)
20524 // Check CMP operands. One of them should be 0 or 1 and the other should be
20525 // an SetCC or extended from it.
20526 SDValue Op1 = Cmp.getOperand(0);
20527 SDValue Op2 = Cmp.getOperand(1);
20530 const ConstantSDNode* C = nullptr;
20531 bool needOppositeCond = (CC == X86::COND_E);
20532 bool checkAgainstTrue = false; // Is it a comparison against 1?
20534 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20536 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20538 else // Quit if all operands are not constants.
20541 if (C->getZExtValue() == 1) {
20542 needOppositeCond = !needOppositeCond;
20543 checkAgainstTrue = true;
20544 } else if (C->getZExtValue() != 0)
20545 // Quit if the constant is neither 0 or 1.
20548 bool truncatedToBoolWithAnd = false;
20549 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20550 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20551 SetCC.getOpcode() == ISD::TRUNCATE ||
20552 SetCC.getOpcode() == ISD::AND) {
20553 if (SetCC.getOpcode() == ISD::AND) {
20555 ConstantSDNode *CS;
20556 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20557 CS->getZExtValue() == 1)
20559 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20560 CS->getZExtValue() == 1)
20564 SetCC = SetCC.getOperand(OpIdx);
20565 truncatedToBoolWithAnd = true;
20567 SetCC = SetCC.getOperand(0);
20570 switch (SetCC.getOpcode()) {
20571 case X86ISD::SETCC_CARRY:
20572 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
20573 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
20574 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
20575 // truncated to i1 using 'and'.
20576 if (checkAgainstTrue && !truncatedToBoolWithAnd)
20578 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
20579 "Invalid use of SETCC_CARRY!");
20581 case X86ISD::SETCC:
20582 // Set the condition code or opposite one if necessary.
20583 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
20584 if (needOppositeCond)
20585 CC = X86::GetOppositeBranchCondition(CC);
20586 return SetCC.getOperand(1);
20587 case X86ISD::CMOV: {
20588 // Check whether false/true value has canonical one, i.e. 0 or 1.
20589 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
20590 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
20591 // Quit if true value is not a constant.
20594 // Quit if false value is not a constant.
20596 SDValue Op = SetCC.getOperand(0);
20597 // Skip 'zext' or 'trunc' node.
20598 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
20599 Op.getOpcode() == ISD::TRUNCATE)
20600 Op = Op.getOperand(0);
20601 // A special case for rdrand/rdseed, where 0 is set if false cond is
20603 if ((Op.getOpcode() != X86ISD::RDRAND &&
20604 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
20607 // Quit if false value is not the constant 0 or 1.
20608 bool FValIsFalse = true;
20609 if (FVal && FVal->getZExtValue() != 0) {
20610 if (FVal->getZExtValue() != 1)
20612 // If FVal is 1, opposite cond is needed.
20613 needOppositeCond = !needOppositeCond;
20614 FValIsFalse = false;
20616 // Quit if TVal is not the constant opposite of FVal.
20617 if (FValIsFalse && TVal->getZExtValue() != 1)
20619 if (!FValIsFalse && TVal->getZExtValue() != 0)
20621 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
20622 if (needOppositeCond)
20623 CC = X86::GetOppositeBranchCondition(CC);
20624 return SetCC.getOperand(3);
20631 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
20632 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
20633 TargetLowering::DAGCombinerInfo &DCI,
20634 const X86Subtarget *Subtarget) {
20637 // If the flag operand isn't dead, don't touch this CMOV.
20638 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
20641 SDValue FalseOp = N->getOperand(0);
20642 SDValue TrueOp = N->getOperand(1);
20643 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
20644 SDValue Cond = N->getOperand(3);
20646 if (CC == X86::COND_E || CC == X86::COND_NE) {
20647 switch (Cond.getOpcode()) {
20651 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
20652 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
20653 return (CC == X86::COND_E) ? FalseOp : TrueOp;
20659 Flags = checkBoolTestSetCCCombine(Cond, CC);
20660 if (Flags.getNode() &&
20661 // Extra check as FCMOV only supports a subset of X86 cond.
20662 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
20663 SDValue Ops[] = { FalseOp, TrueOp,
20664 DAG.getConstant(CC, MVT::i8), Flags };
20665 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
20668 // If this is a select between two integer constants, try to do some
20669 // optimizations. Note that the operands are ordered the opposite of SELECT
20671 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
20672 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
20673 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
20674 // larger than FalseC (the false value).
20675 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
20676 CC = X86::GetOppositeBranchCondition(CC);
20677 std::swap(TrueC, FalseC);
20678 std::swap(TrueOp, FalseOp);
20681 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
20682 // This is efficient for any integer data type (including i8/i16) and
20684 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
20685 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20686 DAG.getConstant(CC, MVT::i8), Cond);
20688 // Zero extend the condition if needed.
20689 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
20691 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20692 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
20693 DAG.getConstant(ShAmt, MVT::i8));
20694 if (N->getNumValues() == 2) // Dead flag value?
20695 return DCI.CombineTo(N, Cond, SDValue());
20699 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
20700 // for any integer data type, including i8/i16.
20701 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20702 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20703 DAG.getConstant(CC, MVT::i8), Cond);
20705 // Zero extend the condition if needed.
20706 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20707 FalseC->getValueType(0), Cond);
20708 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20709 SDValue(FalseC, 0));
20711 if (N->getNumValues() == 2) // Dead flag value?
20712 return DCI.CombineTo(N, Cond, SDValue());
20716 // Optimize cases that will turn into an LEA instruction. This requires
20717 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20718 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20719 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20720 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20722 bool isFastMultiplier = false;
20724 switch ((unsigned char)Diff) {
20726 case 1: // result = add base, cond
20727 case 2: // result = lea base( , cond*2)
20728 case 3: // result = lea base(cond, cond*2)
20729 case 4: // result = lea base( , cond*4)
20730 case 5: // result = lea base(cond, cond*4)
20731 case 8: // result = lea base( , cond*8)
20732 case 9: // result = lea base(cond, cond*8)
20733 isFastMultiplier = true;
20738 if (isFastMultiplier) {
20739 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20740 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20741 DAG.getConstant(CC, MVT::i8), Cond);
20742 // Zero extend the condition if needed.
20743 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20745 // Scale the condition by the difference.
20747 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20748 DAG.getConstant(Diff, Cond.getValueType()));
20750 // Add the base if non-zero.
20751 if (FalseC->getAPIntValue() != 0)
20752 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20753 SDValue(FalseC, 0));
20754 if (N->getNumValues() == 2) // Dead flag value?
20755 return DCI.CombineTo(N, Cond, SDValue());
20762 // Handle these cases:
20763 // (select (x != c), e, c) -> select (x != c), e, x),
20764 // (select (x == c), c, e) -> select (x == c), x, e)
20765 // where the c is an integer constant, and the "select" is the combination
20766 // of CMOV and CMP.
20768 // The rationale for this change is that the conditional-move from a constant
20769 // needs two instructions, however, conditional-move from a register needs
20770 // only one instruction.
20772 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
20773 // some instruction-combining opportunities. This opt needs to be
20774 // postponed as late as possible.
20776 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
20777 // the DCI.xxxx conditions are provided to postpone the optimization as
20778 // late as possible.
20780 ConstantSDNode *CmpAgainst = nullptr;
20781 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
20782 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
20783 !isa<ConstantSDNode>(Cond.getOperand(0))) {
20785 if (CC == X86::COND_NE &&
20786 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
20787 CC = X86::GetOppositeBranchCondition(CC);
20788 std::swap(TrueOp, FalseOp);
20791 if (CC == X86::COND_E &&
20792 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
20793 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
20794 DAG.getConstant(CC, MVT::i8), Cond };
20795 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
20803 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
20804 const X86Subtarget *Subtarget) {
20805 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
20807 default: return SDValue();
20808 // SSE/AVX/AVX2 blend intrinsics.
20809 case Intrinsic::x86_avx2_pblendvb:
20810 case Intrinsic::x86_avx2_pblendw:
20811 case Intrinsic::x86_avx2_pblendd_128:
20812 case Intrinsic::x86_avx2_pblendd_256:
20813 // Don't try to simplify this intrinsic if we don't have AVX2.
20814 if (!Subtarget->hasAVX2())
20817 case Intrinsic::x86_avx_blend_pd_256:
20818 case Intrinsic::x86_avx_blend_ps_256:
20819 case Intrinsic::x86_avx_blendv_pd_256:
20820 case Intrinsic::x86_avx_blendv_ps_256:
20821 // Don't try to simplify this intrinsic if we don't have AVX.
20822 if (!Subtarget->hasAVX())
20825 case Intrinsic::x86_sse41_pblendw:
20826 case Intrinsic::x86_sse41_blendpd:
20827 case Intrinsic::x86_sse41_blendps:
20828 case Intrinsic::x86_sse41_blendvps:
20829 case Intrinsic::x86_sse41_blendvpd:
20830 case Intrinsic::x86_sse41_pblendvb: {
20831 SDValue Op0 = N->getOperand(1);
20832 SDValue Op1 = N->getOperand(2);
20833 SDValue Mask = N->getOperand(3);
20835 // Don't try to simplify this intrinsic if we don't have SSE4.1.
20836 if (!Subtarget->hasSSE41())
20839 // fold (blend A, A, Mask) -> A
20842 // fold (blend A, B, allZeros) -> A
20843 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
20845 // fold (blend A, B, allOnes) -> B
20846 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
20849 // Simplify the case where the mask is a constant i32 value.
20850 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
20851 if (C->isNullValue())
20853 if (C->isAllOnesValue())
20860 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
20861 case Intrinsic::x86_sse2_psrai_w:
20862 case Intrinsic::x86_sse2_psrai_d:
20863 case Intrinsic::x86_avx2_psrai_w:
20864 case Intrinsic::x86_avx2_psrai_d:
20865 case Intrinsic::x86_sse2_psra_w:
20866 case Intrinsic::x86_sse2_psra_d:
20867 case Intrinsic::x86_avx2_psra_w:
20868 case Intrinsic::x86_avx2_psra_d: {
20869 SDValue Op0 = N->getOperand(1);
20870 SDValue Op1 = N->getOperand(2);
20871 EVT VT = Op0.getValueType();
20872 assert(VT.isVector() && "Expected a vector type!");
20874 if (isa<BuildVectorSDNode>(Op1))
20875 Op1 = Op1.getOperand(0);
20877 if (!isa<ConstantSDNode>(Op1))
20880 EVT SVT = VT.getVectorElementType();
20881 unsigned SVTBits = SVT.getSizeInBits();
20883 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
20884 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
20885 uint64_t ShAmt = C.getZExtValue();
20887 // Don't try to convert this shift into a ISD::SRA if the shift
20888 // count is bigger than or equal to the element size.
20889 if (ShAmt >= SVTBits)
20892 // Trivial case: if the shift count is zero, then fold this
20893 // into the first operand.
20897 // Replace this packed shift intrinsic with a target independent
20899 SDValue Splat = DAG.getConstant(C, VT);
20900 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
20905 /// PerformMulCombine - Optimize a single multiply with constant into two
20906 /// in order to implement it with two cheaper instructions, e.g.
20907 /// LEA + SHL, LEA + LEA.
20908 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
20909 TargetLowering::DAGCombinerInfo &DCI) {
20910 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
20913 EVT VT = N->getValueType(0);
20914 if (VT != MVT::i64)
20917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
20920 uint64_t MulAmt = C->getZExtValue();
20921 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
20924 uint64_t MulAmt1 = 0;
20925 uint64_t MulAmt2 = 0;
20926 if ((MulAmt % 9) == 0) {
20928 MulAmt2 = MulAmt / 9;
20929 } else if ((MulAmt % 5) == 0) {
20931 MulAmt2 = MulAmt / 5;
20932 } else if ((MulAmt % 3) == 0) {
20934 MulAmt2 = MulAmt / 3;
20937 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
20940 if (isPowerOf2_64(MulAmt2) &&
20941 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
20942 // If second multiplifer is pow2, issue it first. We want the multiply by
20943 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
20945 std::swap(MulAmt1, MulAmt2);
20948 if (isPowerOf2_64(MulAmt1))
20949 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
20950 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
20952 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
20953 DAG.getConstant(MulAmt1, VT));
20955 if (isPowerOf2_64(MulAmt2))
20956 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
20957 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
20959 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
20960 DAG.getConstant(MulAmt2, VT));
20962 // Do not add new nodes to DAG combiner worklist.
20963 DCI.CombineTo(N, NewMul, false);
20968 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
20969 SDValue N0 = N->getOperand(0);
20970 SDValue N1 = N->getOperand(1);
20971 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
20972 EVT VT = N0.getValueType();
20974 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
20975 // since the result of setcc_c is all zero's or all ones.
20976 if (VT.isInteger() && !VT.isVector() &&
20977 N1C && N0.getOpcode() == ISD::AND &&
20978 N0.getOperand(1).getOpcode() == ISD::Constant) {
20979 SDValue N00 = N0.getOperand(0);
20980 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
20981 ((N00.getOpcode() == ISD::ANY_EXTEND ||
20982 N00.getOpcode() == ISD::ZERO_EXTEND) &&
20983 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
20984 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
20985 APInt ShAmt = N1C->getAPIntValue();
20986 Mask = Mask.shl(ShAmt);
20988 return DAG.getNode(ISD::AND, SDLoc(N), VT,
20989 N00, DAG.getConstant(Mask, VT));
20993 // Hardware support for vector shifts is sparse which makes us scalarize the
20994 // vector operations in many cases. Also, on sandybridge ADD is faster than
20996 // (shl V, 1) -> add V,V
20997 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
20998 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
20999 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21000 // We shift all of the values by one. In many cases we do not have
21001 // hardware support for this operation. This is better expressed as an ADD
21003 if (N1SplatC->getZExtValue() == 1)
21004 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21010 /// \brief Returns a vector of 0s if the node in input is a vector logical
21011 /// shift by a constant amount which is known to be bigger than or equal
21012 /// to the vector element size in bits.
21013 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21014 const X86Subtarget *Subtarget) {
21015 EVT VT = N->getValueType(0);
21017 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21018 (!Subtarget->hasInt256() ||
21019 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21022 SDValue Amt = N->getOperand(1);
21024 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21025 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21026 APInt ShiftAmt = AmtSplat->getAPIntValue();
21027 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21029 // SSE2/AVX2 logical shifts always return a vector of 0s
21030 // if the shift amount is bigger than or equal to
21031 // the element size. The constant shift amount will be
21032 // encoded as a 8-bit immediate.
21033 if (ShiftAmt.trunc(8).uge(MaxAmount))
21034 return getZeroVector(VT, Subtarget, DAG, DL);
21040 /// PerformShiftCombine - Combine shifts.
21041 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21042 TargetLowering::DAGCombinerInfo &DCI,
21043 const X86Subtarget *Subtarget) {
21044 if (N->getOpcode() == ISD::SHL) {
21045 SDValue V = PerformSHLCombine(N, DAG);
21046 if (V.getNode()) return V;
21049 if (N->getOpcode() != ISD::SRA) {
21050 // Try to fold this logical shift into a zero vector.
21051 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21052 if (V.getNode()) return V;
21058 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21059 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21060 // and friends. Likewise for OR -> CMPNEQSS.
21061 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21062 TargetLowering::DAGCombinerInfo &DCI,
21063 const X86Subtarget *Subtarget) {
21066 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21067 // we're requiring SSE2 for both.
21068 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21069 SDValue N0 = N->getOperand(0);
21070 SDValue N1 = N->getOperand(1);
21071 SDValue CMP0 = N0->getOperand(1);
21072 SDValue CMP1 = N1->getOperand(1);
21075 // The SETCCs should both refer to the same CMP.
21076 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21079 SDValue CMP00 = CMP0->getOperand(0);
21080 SDValue CMP01 = CMP0->getOperand(1);
21081 EVT VT = CMP00.getValueType();
21083 if (VT == MVT::f32 || VT == MVT::f64) {
21084 bool ExpectingFlags = false;
21085 // Check for any users that want flags:
21086 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21087 !ExpectingFlags && UI != UE; ++UI)
21088 switch (UI->getOpcode()) {
21093 ExpectingFlags = true;
21095 case ISD::CopyToReg:
21096 case ISD::SIGN_EXTEND:
21097 case ISD::ZERO_EXTEND:
21098 case ISD::ANY_EXTEND:
21102 if (!ExpectingFlags) {
21103 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21104 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21106 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21107 X86::CondCode tmp = cc0;
21112 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21113 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21114 // FIXME: need symbolic constants for these magic numbers.
21115 // See X86ATTInstPrinter.cpp:printSSECC().
21116 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21117 if (Subtarget->hasAVX512()) {
21118 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21119 CMP01, DAG.getConstant(x86cc, MVT::i8));
21120 if (N->getValueType(0) != MVT::i1)
21121 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21125 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21126 CMP00.getValueType(), CMP00, CMP01,
21127 DAG.getConstant(x86cc, MVT::i8));
21129 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21130 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21132 if (is64BitFP && !Subtarget->is64Bit()) {
21133 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21134 // 64-bit integer, since that's not a legal type. Since
21135 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21136 // bits, but can do this little dance to extract the lowest 32 bits
21137 // and work with those going forward.
21138 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21140 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21142 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21143 Vector32, DAG.getIntPtrConstant(0));
21147 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21148 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21149 DAG.getConstant(1, IntVT));
21150 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21151 return OneBitOfTruth;
21159 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21160 /// so it can be folded inside ANDNP.
21161 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21162 EVT VT = N->getValueType(0);
21164 // Match direct AllOnes for 128 and 256-bit vectors
21165 if (ISD::isBuildVectorAllOnes(N))
21168 // Look through a bit convert.
21169 if (N->getOpcode() == ISD::BITCAST)
21170 N = N->getOperand(0).getNode();
21172 // Sometimes the operand may come from a insert_subvector building a 256-bit
21174 if (VT.is256BitVector() &&
21175 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21176 SDValue V1 = N->getOperand(0);
21177 SDValue V2 = N->getOperand(1);
21179 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21180 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21181 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21182 ISD::isBuildVectorAllOnes(V2.getNode()))
21189 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21190 // register. In most cases we actually compare or select YMM-sized registers
21191 // and mixing the two types creates horrible code. This method optimizes
21192 // some of the transition sequences.
21193 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21194 TargetLowering::DAGCombinerInfo &DCI,
21195 const X86Subtarget *Subtarget) {
21196 EVT VT = N->getValueType(0);
21197 if (!VT.is256BitVector())
21200 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21201 N->getOpcode() == ISD::ZERO_EXTEND ||
21202 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21204 SDValue Narrow = N->getOperand(0);
21205 EVT NarrowVT = Narrow->getValueType(0);
21206 if (!NarrowVT.is128BitVector())
21209 if (Narrow->getOpcode() != ISD::XOR &&
21210 Narrow->getOpcode() != ISD::AND &&
21211 Narrow->getOpcode() != ISD::OR)
21214 SDValue N0 = Narrow->getOperand(0);
21215 SDValue N1 = Narrow->getOperand(1);
21218 // The Left side has to be a trunc.
21219 if (N0.getOpcode() != ISD::TRUNCATE)
21222 // The type of the truncated inputs.
21223 EVT WideVT = N0->getOperand(0)->getValueType(0);
21227 // The right side has to be a 'trunc' or a constant vector.
21228 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21229 ConstantSDNode *RHSConstSplat = nullptr;
21230 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21231 RHSConstSplat = RHSBV->getConstantSplatNode();
21232 if (!RHSTrunc && !RHSConstSplat)
21235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21237 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21240 // Set N0 and N1 to hold the inputs to the new wide operation.
21241 N0 = N0->getOperand(0);
21242 if (RHSConstSplat) {
21243 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21244 SDValue(RHSConstSplat, 0));
21245 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21246 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21247 } else if (RHSTrunc) {
21248 N1 = N1->getOperand(0);
21251 // Generate the wide operation.
21252 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21253 unsigned Opcode = N->getOpcode();
21255 case ISD::ANY_EXTEND:
21257 case ISD::ZERO_EXTEND: {
21258 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21259 APInt Mask = APInt::getAllOnesValue(InBits);
21260 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21261 return DAG.getNode(ISD::AND, DL, VT,
21262 Op, DAG.getConstant(Mask, VT));
21264 case ISD::SIGN_EXTEND:
21265 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21266 Op, DAG.getValueType(NarrowVT));
21268 llvm_unreachable("Unexpected opcode");
21272 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21273 TargetLowering::DAGCombinerInfo &DCI,
21274 const X86Subtarget *Subtarget) {
21275 EVT VT = N->getValueType(0);
21276 if (DCI.isBeforeLegalizeOps())
21279 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21283 // Create BEXTR instructions
21284 // BEXTR is ((X >> imm) & (2**size-1))
21285 if (VT == MVT::i32 || VT == MVT::i64) {
21286 SDValue N0 = N->getOperand(0);
21287 SDValue N1 = N->getOperand(1);
21290 // Check for BEXTR.
21291 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21292 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21293 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21294 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21295 if (MaskNode && ShiftNode) {
21296 uint64_t Mask = MaskNode->getZExtValue();
21297 uint64_t Shift = ShiftNode->getZExtValue();
21298 if (isMask_64(Mask)) {
21299 uint64_t MaskSize = CountPopulation_64(Mask);
21300 if (Shift + MaskSize <= VT.getSizeInBits())
21301 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21302 DAG.getConstant(Shift | (MaskSize << 8), VT));
21310 // Want to form ANDNP nodes:
21311 // 1) In the hopes of then easily combining them with OR and AND nodes
21312 // to form PBLEND/PSIGN.
21313 // 2) To match ANDN packed intrinsics
21314 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21317 SDValue N0 = N->getOperand(0);
21318 SDValue N1 = N->getOperand(1);
21321 // Check LHS for vnot
21322 if (N0.getOpcode() == ISD::XOR &&
21323 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21324 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21325 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21327 // Check RHS for vnot
21328 if (N1.getOpcode() == ISD::XOR &&
21329 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21330 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21331 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21336 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21337 TargetLowering::DAGCombinerInfo &DCI,
21338 const X86Subtarget *Subtarget) {
21339 if (DCI.isBeforeLegalizeOps())
21342 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21346 SDValue N0 = N->getOperand(0);
21347 SDValue N1 = N->getOperand(1);
21348 EVT VT = N->getValueType(0);
21350 // look for psign/blend
21351 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21352 if (!Subtarget->hasSSSE3() ||
21353 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21356 // Canonicalize pandn to RHS
21357 if (N0.getOpcode() == X86ISD::ANDNP)
21359 // or (and (m, y), (pandn m, x))
21360 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21361 SDValue Mask = N1.getOperand(0);
21362 SDValue X = N1.getOperand(1);
21364 if (N0.getOperand(0) == Mask)
21365 Y = N0.getOperand(1);
21366 if (N0.getOperand(1) == Mask)
21367 Y = N0.getOperand(0);
21369 // Check to see if the mask appeared in both the AND and ANDNP and
21373 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21374 // Look through mask bitcast.
21375 if (Mask.getOpcode() == ISD::BITCAST)
21376 Mask = Mask.getOperand(0);
21377 if (X.getOpcode() == ISD::BITCAST)
21378 X = X.getOperand(0);
21379 if (Y.getOpcode() == ISD::BITCAST)
21380 Y = Y.getOperand(0);
21382 EVT MaskVT = Mask.getValueType();
21384 // Validate that the Mask operand is a vector sra node.
21385 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21386 // there is no psrai.b
21387 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21388 unsigned SraAmt = ~0;
21389 if (Mask.getOpcode() == ISD::SRA) {
21390 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21391 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21392 SraAmt = AmtConst->getZExtValue();
21393 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21394 SDValue SraC = Mask.getOperand(1);
21395 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21397 if ((SraAmt + 1) != EltBits)
21402 // Now we know we at least have a plendvb with the mask val. See if
21403 // we can form a psignb/w/d.
21404 // psign = x.type == y.type == mask.type && y = sub(0, x);
21405 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21406 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21407 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21408 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21409 "Unsupported VT for PSIGN");
21410 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21411 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21413 // PBLENDVB only available on SSE 4.1
21414 if (!Subtarget->hasSSE41())
21417 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21419 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21420 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21421 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21422 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21423 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21427 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21430 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21431 MachineFunction &MF = DAG.getMachineFunction();
21432 bool OptForSize = MF.getFunction()->getAttributes().
21433 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21435 // SHLD/SHRD instructions have lower register pressure, but on some
21436 // platforms they have higher latency than the equivalent
21437 // series of shifts/or that would otherwise be generated.
21438 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21439 // have higher latencies and we are not optimizing for size.
21440 if (!OptForSize && Subtarget->isSHLDSlow())
21443 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21445 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21447 if (!N0.hasOneUse() || !N1.hasOneUse())
21450 SDValue ShAmt0 = N0.getOperand(1);
21451 if (ShAmt0.getValueType() != MVT::i8)
21453 SDValue ShAmt1 = N1.getOperand(1);
21454 if (ShAmt1.getValueType() != MVT::i8)
21456 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21457 ShAmt0 = ShAmt0.getOperand(0);
21458 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21459 ShAmt1 = ShAmt1.getOperand(0);
21462 unsigned Opc = X86ISD::SHLD;
21463 SDValue Op0 = N0.getOperand(0);
21464 SDValue Op1 = N1.getOperand(0);
21465 if (ShAmt0.getOpcode() == ISD::SUB) {
21466 Opc = X86ISD::SHRD;
21467 std::swap(Op0, Op1);
21468 std::swap(ShAmt0, ShAmt1);
21471 unsigned Bits = VT.getSizeInBits();
21472 if (ShAmt1.getOpcode() == ISD::SUB) {
21473 SDValue Sum = ShAmt1.getOperand(0);
21474 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21475 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21476 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21477 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21478 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21479 return DAG.getNode(Opc, DL, VT,
21481 DAG.getNode(ISD::TRUNCATE, DL,
21484 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21485 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21487 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21488 return DAG.getNode(Opc, DL, VT,
21489 N0.getOperand(0), N1.getOperand(0),
21490 DAG.getNode(ISD::TRUNCATE, DL,
21497 // Generate NEG and CMOV for integer abs.
21498 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21499 EVT VT = N->getValueType(0);
21501 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21502 // 8-bit integer abs to NEG and CMOV.
21503 if (VT.isInteger() && VT.getSizeInBits() == 8)
21506 SDValue N0 = N->getOperand(0);
21507 SDValue N1 = N->getOperand(1);
21510 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21511 // and change it to SUB and CMOV.
21512 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21513 N0.getOpcode() == ISD::ADD &&
21514 N0.getOperand(1) == N1 &&
21515 N1.getOpcode() == ISD::SRA &&
21516 N1.getOperand(0) == N0.getOperand(0))
21517 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21518 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21519 // Generate SUB & CMOV.
21520 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21521 DAG.getConstant(0, VT), N0.getOperand(0));
21523 SDValue Ops[] = { N0.getOperand(0), Neg,
21524 DAG.getConstant(X86::COND_GE, MVT::i8),
21525 SDValue(Neg.getNode(), 1) };
21526 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21531 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
21532 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
21533 TargetLowering::DAGCombinerInfo &DCI,
21534 const X86Subtarget *Subtarget) {
21535 if (DCI.isBeforeLegalizeOps())
21538 if (Subtarget->hasCMov()) {
21539 SDValue RV = performIntegerAbsCombine(N, DAG);
21547 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
21548 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
21549 TargetLowering::DAGCombinerInfo &DCI,
21550 const X86Subtarget *Subtarget) {
21551 LoadSDNode *Ld = cast<LoadSDNode>(N);
21552 EVT RegVT = Ld->getValueType(0);
21553 EVT MemVT = Ld->getMemoryVT();
21555 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21557 // On Sandybridge unaligned 256bit loads are inefficient.
21558 ISD::LoadExtType Ext = Ld->getExtensionType();
21559 unsigned Alignment = Ld->getAlignment();
21560 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
21561 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
21562 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
21563 unsigned NumElems = RegVT.getVectorNumElements();
21567 SDValue Ptr = Ld->getBasePtr();
21568 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
21570 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
21572 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21573 Ld->getPointerInfo(), Ld->isVolatile(),
21574 Ld->isNonTemporal(), Ld->isInvariant(),
21576 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21577 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21578 Ld->getPointerInfo(), Ld->isVolatile(),
21579 Ld->isNonTemporal(), Ld->isInvariant(),
21580 std::min(16U, Alignment));
21581 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21583 Load2.getValue(1));
21585 SDValue NewVec = DAG.getUNDEF(RegVT);
21586 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
21587 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
21588 return DCI.CombineTo(N, NewVec, TF, true);
21594 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
21595 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
21596 const X86Subtarget *Subtarget) {
21597 StoreSDNode *St = cast<StoreSDNode>(N);
21598 EVT VT = St->getValue().getValueType();
21599 EVT StVT = St->getMemoryVT();
21601 SDValue StoredVal = St->getOperand(1);
21602 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21604 // If we are saving a concatenation of two XMM registers, perform two stores.
21605 // On Sandy Bridge, 256-bit memory operations are executed by two
21606 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
21607 // memory operation.
21608 unsigned Alignment = St->getAlignment();
21609 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
21610 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
21611 StVT == VT && !IsAligned) {
21612 unsigned NumElems = VT.getVectorNumElements();
21616 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
21617 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
21619 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
21620 SDValue Ptr0 = St->getBasePtr();
21621 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
21623 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
21624 St->getPointerInfo(), St->isVolatile(),
21625 St->isNonTemporal(), Alignment);
21626 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
21627 St->getPointerInfo(), St->isVolatile(),
21628 St->isNonTemporal(),
21629 std::min(16U, Alignment));
21630 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
21633 // Optimize trunc store (of multiple scalars) to shuffle and store.
21634 // First, pack all of the elements in one place. Next, store to memory
21635 // in fewer chunks.
21636 if (St->isTruncatingStore() && VT.isVector()) {
21637 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21638 unsigned NumElems = VT.getVectorNumElements();
21639 assert(StVT != VT && "Cannot truncate to the same type");
21640 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
21641 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
21643 // From, To sizes and ElemCount must be pow of two
21644 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
21645 // We are going to use the original vector elt for storing.
21646 // Accumulated smaller vector elements must be a multiple of the store size.
21647 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
21649 unsigned SizeRatio = FromSz / ToSz;
21651 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
21653 // Create a type on which we perform the shuffle
21654 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
21655 StVT.getScalarType(), NumElems*SizeRatio);
21657 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
21659 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
21660 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21661 for (unsigned i = 0; i != NumElems; ++i)
21662 ShuffleVec[i] = i * SizeRatio;
21664 // Can't shuffle using an illegal type.
21665 if (!TLI.isTypeLegal(WideVecVT))
21668 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
21669 DAG.getUNDEF(WideVecVT),
21671 // At this point all of the data is stored at the bottom of the
21672 // register. We now need to save it to mem.
21674 // Find the largest store unit
21675 MVT StoreType = MVT::i8;
21676 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
21677 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
21678 MVT Tp = (MVT::SimpleValueType)tp;
21679 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
21683 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
21684 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
21685 (64 <= NumElems * ToSz))
21686 StoreType = MVT::f64;
21688 // Bitcast the original vector into a vector of store-size units
21689 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21690 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21691 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21692 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21693 SmallVector<SDValue, 8> Chains;
21694 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21695 TLI.getPointerTy());
21696 SDValue Ptr = St->getBasePtr();
21698 // Perform one or more big stores into memory.
21699 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21700 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21701 StoreType, ShuffWide,
21702 DAG.getIntPtrConstant(i));
21703 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21704 St->getPointerInfo(), St->isVolatile(),
21705 St->isNonTemporal(), St->getAlignment());
21706 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21707 Chains.push_back(Ch);
21710 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21713 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21714 // the FP state in cases where an emms may be missing.
21715 // A preferable solution to the general problem is to figure out the right
21716 // places to insert EMMS. This qualifies as a quick hack.
21718 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21719 if (VT.getSizeInBits() != 64)
21722 const Function *F = DAG.getMachineFunction().getFunction();
21723 bool NoImplicitFloatOps = F->getAttributes().
21724 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21725 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21726 && Subtarget->hasSSE2();
21727 if ((VT.isVector() ||
21728 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21729 isa<LoadSDNode>(St->getValue()) &&
21730 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21731 St->getChain().hasOneUse() && !St->isVolatile()) {
21732 SDNode* LdVal = St->getValue().getNode();
21733 LoadSDNode *Ld = nullptr;
21734 int TokenFactorIndex = -1;
21735 SmallVector<SDValue, 8> Ops;
21736 SDNode* ChainVal = St->getChain().getNode();
21737 // Must be a store of a load. We currently handle two cases: the load
21738 // is a direct child, and it's under an intervening TokenFactor. It is
21739 // possible to dig deeper under nested TokenFactors.
21740 if (ChainVal == LdVal)
21741 Ld = cast<LoadSDNode>(St->getChain());
21742 else if (St->getValue().hasOneUse() &&
21743 ChainVal->getOpcode() == ISD::TokenFactor) {
21744 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21745 if (ChainVal->getOperand(i).getNode() == LdVal) {
21746 TokenFactorIndex = i;
21747 Ld = cast<LoadSDNode>(St->getValue());
21749 Ops.push_back(ChainVal->getOperand(i));
21753 if (!Ld || !ISD::isNormalLoad(Ld))
21756 // If this is not the MMX case, i.e. we are just turning i64 load/store
21757 // into f64 load/store, avoid the transformation if there are multiple
21758 // uses of the loaded value.
21759 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21764 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21765 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
21767 if (Subtarget->is64Bit() || F64IsLegal) {
21768 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
21769 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
21770 Ld->getPointerInfo(), Ld->isVolatile(),
21771 Ld->isNonTemporal(), Ld->isInvariant(),
21772 Ld->getAlignment());
21773 SDValue NewChain = NewLd.getValue(1);
21774 if (TokenFactorIndex != -1) {
21775 Ops.push_back(NewChain);
21776 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21778 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
21779 St->getPointerInfo(),
21780 St->isVolatile(), St->isNonTemporal(),
21781 St->getAlignment());
21784 // Otherwise, lower to two pairs of 32-bit loads / stores.
21785 SDValue LoAddr = Ld->getBasePtr();
21786 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
21787 DAG.getConstant(4, MVT::i32));
21789 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
21790 Ld->getPointerInfo(),
21791 Ld->isVolatile(), Ld->isNonTemporal(),
21792 Ld->isInvariant(), Ld->getAlignment());
21793 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
21794 Ld->getPointerInfo().getWithOffset(4),
21795 Ld->isVolatile(), Ld->isNonTemporal(),
21797 MinAlign(Ld->getAlignment(), 4));
21799 SDValue NewChain = LoLd.getValue(1);
21800 if (TokenFactorIndex != -1) {
21801 Ops.push_back(LoLd);
21802 Ops.push_back(HiLd);
21803 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21806 LoAddr = St->getBasePtr();
21807 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
21808 DAG.getConstant(4, MVT::i32));
21810 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
21811 St->getPointerInfo(),
21812 St->isVolatile(), St->isNonTemporal(),
21813 St->getAlignment());
21814 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
21815 St->getPointerInfo().getWithOffset(4),
21817 St->isNonTemporal(),
21818 MinAlign(St->getAlignment(), 4));
21819 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
21824 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
21825 /// and return the operands for the horizontal operation in LHS and RHS. A
21826 /// horizontal operation performs the binary operation on successive elements
21827 /// of its first operand, then on successive elements of its second operand,
21828 /// returning the resulting values in a vector. For example, if
21829 /// A = < float a0, float a1, float a2, float a3 >
21831 /// B = < float b0, float b1, float b2, float b3 >
21832 /// then the result of doing a horizontal operation on A and B is
21833 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
21834 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21835 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21836 /// set to A, RHS to B, and the routine returns 'true'.
21837 /// Note that the binary operation should have the property that if one of the
21838 /// operands is UNDEF then the result is UNDEF.
21839 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21840 // Look for the following pattern: if
21841 // A = < float a0, float a1, float a2, float a3 >
21842 // B = < float b0, float b1, float b2, float b3 >
21844 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21845 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
21846 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21847 // which is A horizontal-op B.
21849 // At least one of the operands should be a vector shuffle.
21850 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21851 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
21854 MVT VT = LHS.getSimpleValueType();
21856 assert((VT.is128BitVector() || VT.is256BitVector()) &&
21857 "Unsupported vector type for horizontal add/sub");
21859 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
21860 // operate independently on 128-bit lanes.
21861 unsigned NumElts = VT.getVectorNumElements();
21862 unsigned NumLanes = VT.getSizeInBits()/128;
21863 unsigned NumLaneElts = NumElts / NumLanes;
21864 assert((NumLaneElts % 2 == 0) &&
21865 "Vector type should have an even number of elements in each lane");
21866 unsigned HalfLaneElts = NumLaneElts/2;
21868 // View LHS in the form
21869 // LHS = VECTOR_SHUFFLE A, B, LMask
21870 // If LHS is not a shuffle then pretend it is the shuffle
21871 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21872 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
21875 SmallVector<int, 16> LMask(NumElts);
21876 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21877 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21878 A = LHS.getOperand(0);
21879 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21880 B = LHS.getOperand(1);
21881 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21882 std::copy(Mask.begin(), Mask.end(), LMask.begin());
21884 if (LHS.getOpcode() != ISD::UNDEF)
21886 for (unsigned i = 0; i != NumElts; ++i)
21890 // Likewise, view RHS in the form
21891 // RHS = VECTOR_SHUFFLE C, D, RMask
21893 SmallVector<int, 16> RMask(NumElts);
21894 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21895 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
21896 C = RHS.getOperand(0);
21897 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
21898 D = RHS.getOperand(1);
21899 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
21900 std::copy(Mask.begin(), Mask.end(), RMask.begin());
21902 if (RHS.getOpcode() != ISD::UNDEF)
21904 for (unsigned i = 0; i != NumElts; ++i)
21908 // Check that the shuffles are both shuffling the same vectors.
21909 if (!(A == C && B == D) && !(A == D && B == C))
21912 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
21913 if (!A.getNode() && !B.getNode())
21916 // If A and B occur in reverse order in RHS, then "swap" them (which means
21917 // rewriting the mask).
21919 CommuteVectorShuffleMask(RMask, NumElts);
21921 // At this point LHS and RHS are equivalent to
21922 // LHS = VECTOR_SHUFFLE A, B, LMask
21923 // RHS = VECTOR_SHUFFLE A, B, RMask
21924 // Check that the masks correspond to performing a horizontal operation.
21925 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
21926 for (unsigned i = 0; i != NumLaneElts; ++i) {
21927 int LIdx = LMask[i+l], RIdx = RMask[i+l];
21929 // Ignore any UNDEF components.
21930 if (LIdx < 0 || RIdx < 0 ||
21931 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
21932 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
21935 // Check that successive elements are being operated on. If not, this is
21936 // not a horizontal operation.
21937 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
21938 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
21939 if (!(LIdx == Index && RIdx == Index + 1) &&
21940 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
21945 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
21946 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
21950 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
21951 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
21952 const X86Subtarget *Subtarget) {
21953 EVT VT = N->getValueType(0);
21954 SDValue LHS = N->getOperand(0);
21955 SDValue RHS = N->getOperand(1);
21957 // Try to synthesize horizontal adds from adds of shuffles.
21958 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21959 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21960 isHorizontalBinOp(LHS, RHS, true))
21961 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
21965 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
21966 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
21967 const X86Subtarget *Subtarget) {
21968 EVT VT = N->getValueType(0);
21969 SDValue LHS = N->getOperand(0);
21970 SDValue RHS = N->getOperand(1);
21972 // Try to synthesize horizontal subs from subs of shuffles.
21973 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21974 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21975 isHorizontalBinOp(LHS, RHS, false))
21976 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
21980 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
21981 /// X86ISD::FXOR nodes.
21982 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
21983 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
21984 // F[X]OR(0.0, x) -> x
21985 // F[X]OR(x, 0.0) -> x
21986 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21987 if (C->getValueAPF().isPosZero())
21988 return N->getOperand(1);
21989 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21990 if (C->getValueAPF().isPosZero())
21991 return N->getOperand(0);
21995 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
21996 /// X86ISD::FMAX nodes.
21997 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
21998 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22000 // Only perform optimizations if UnsafeMath is used.
22001 if (!DAG.getTarget().Options.UnsafeFPMath)
22004 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22005 // into FMINC and FMAXC, which are Commutative operations.
22006 unsigned NewOp = 0;
22007 switch (N->getOpcode()) {
22008 default: llvm_unreachable("unknown opcode");
22009 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22010 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22013 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22014 N->getOperand(0), N->getOperand(1));
22017 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22018 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22019 // FAND(0.0, x) -> 0.0
22020 // FAND(x, 0.0) -> 0.0
22021 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22022 if (C->getValueAPF().isPosZero())
22023 return N->getOperand(0);
22024 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22025 if (C->getValueAPF().isPosZero())
22026 return N->getOperand(1);
22030 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22031 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22032 // FANDN(x, 0.0) -> 0.0
22033 // FANDN(0.0, x) -> x
22034 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22035 if (C->getValueAPF().isPosZero())
22036 return N->getOperand(1);
22037 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22038 if (C->getValueAPF().isPosZero())
22039 return N->getOperand(1);
22043 static SDValue PerformBTCombine(SDNode *N,
22045 TargetLowering::DAGCombinerInfo &DCI) {
22046 // BT ignores high bits in the bit index operand.
22047 SDValue Op1 = N->getOperand(1);
22048 if (Op1.hasOneUse()) {
22049 unsigned BitWidth = Op1.getValueSizeInBits();
22050 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22051 APInt KnownZero, KnownOne;
22052 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22053 !DCI.isBeforeLegalizeOps());
22054 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22055 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22056 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22057 DCI.CommitTargetLoweringOpt(TLO);
22062 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22063 SDValue Op = N->getOperand(0);
22064 if (Op.getOpcode() == ISD::BITCAST)
22065 Op = Op.getOperand(0);
22066 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22067 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22068 VT.getVectorElementType().getSizeInBits() ==
22069 OpVT.getVectorElementType().getSizeInBits()) {
22070 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22075 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22076 const X86Subtarget *Subtarget) {
22077 EVT VT = N->getValueType(0);
22078 if (!VT.isVector())
22081 SDValue N0 = N->getOperand(0);
22082 SDValue N1 = N->getOperand(1);
22083 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22086 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22087 // both SSE and AVX2 since there is no sign-extended shift right
22088 // operation on a vector with 64-bit elements.
22089 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22090 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22091 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22092 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22093 SDValue N00 = N0.getOperand(0);
22095 // EXTLOAD has a better solution on AVX2,
22096 // it may be replaced with X86ISD::VSEXT node.
22097 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22098 if (!ISD::isNormalLoad(N00.getNode()))
22101 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22102 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22104 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22110 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22111 TargetLowering::DAGCombinerInfo &DCI,
22112 const X86Subtarget *Subtarget) {
22113 if (!DCI.isBeforeLegalizeOps())
22116 if (!Subtarget->hasFp256())
22119 EVT VT = N->getValueType(0);
22120 if (VT.isVector() && VT.getSizeInBits() == 256) {
22121 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22129 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22130 const X86Subtarget* Subtarget) {
22132 EVT VT = N->getValueType(0);
22134 // Let legalize expand this if it isn't a legal type yet.
22135 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22138 EVT ScalarVT = VT.getScalarType();
22139 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22140 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22143 SDValue A = N->getOperand(0);
22144 SDValue B = N->getOperand(1);
22145 SDValue C = N->getOperand(2);
22147 bool NegA = (A.getOpcode() == ISD::FNEG);
22148 bool NegB = (B.getOpcode() == ISD::FNEG);
22149 bool NegC = (C.getOpcode() == ISD::FNEG);
22151 // Negative multiplication when NegA xor NegB
22152 bool NegMul = (NegA != NegB);
22154 A = A.getOperand(0);
22156 B = B.getOperand(0);
22158 C = C.getOperand(0);
22162 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22164 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22166 return DAG.getNode(Opcode, dl, VT, A, B, C);
22169 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22170 TargetLowering::DAGCombinerInfo &DCI,
22171 const X86Subtarget *Subtarget) {
22172 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22173 // (and (i32 x86isd::setcc_carry), 1)
22174 // This eliminates the zext. This transformation is necessary because
22175 // ISD::SETCC is always legalized to i8.
22177 SDValue N0 = N->getOperand(0);
22178 EVT VT = N->getValueType(0);
22180 if (N0.getOpcode() == ISD::AND &&
22182 N0.getOperand(0).hasOneUse()) {
22183 SDValue N00 = N0.getOperand(0);
22184 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22185 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22186 if (!C || C->getZExtValue() != 1)
22188 return DAG.getNode(ISD::AND, dl, VT,
22189 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22190 N00.getOperand(0), N00.getOperand(1)),
22191 DAG.getConstant(1, VT));
22195 if (N0.getOpcode() == ISD::TRUNCATE &&
22197 N0.getOperand(0).hasOneUse()) {
22198 SDValue N00 = N0.getOperand(0);
22199 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22200 return DAG.getNode(ISD::AND, dl, VT,
22201 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22202 N00.getOperand(0), N00.getOperand(1)),
22203 DAG.getConstant(1, VT));
22206 if (VT.is256BitVector()) {
22207 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22215 // Optimize x == -y --> x+y == 0
22216 // x != -y --> x+y != 0
22217 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22218 const X86Subtarget* Subtarget) {
22219 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22220 SDValue LHS = N->getOperand(0);
22221 SDValue RHS = N->getOperand(1);
22222 EVT VT = N->getValueType(0);
22225 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22227 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22228 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22229 LHS.getValueType(), RHS, LHS.getOperand(1));
22230 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22231 addV, DAG.getConstant(0, addV.getValueType()), CC);
22233 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22235 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22236 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22237 RHS.getValueType(), LHS, RHS.getOperand(1));
22238 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22239 addV, DAG.getConstant(0, addV.getValueType()), CC);
22242 if (VT.getScalarType() == MVT::i1) {
22243 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22244 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22245 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22246 if (!IsSEXT0 && !IsVZero0)
22248 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22249 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22250 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22252 if (!IsSEXT1 && !IsVZero1)
22255 if (IsSEXT0 && IsVZero1) {
22256 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22257 if (CC == ISD::SETEQ)
22258 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22259 return LHS.getOperand(0);
22261 if (IsSEXT1 && IsVZero0) {
22262 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22263 if (CC == ISD::SETEQ)
22264 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22265 return RHS.getOperand(0);
22272 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22273 const X86Subtarget *Subtarget) {
22275 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22276 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22277 "X86insertps is only defined for v4x32");
22279 SDValue Ld = N->getOperand(1);
22280 if (MayFoldLoad(Ld)) {
22281 // Extract the countS bits from the immediate so we can get the proper
22282 // address when narrowing the vector load to a specific element.
22283 // When the second source op is a memory address, interps doesn't use
22284 // countS and just gets an f32 from that address.
22285 unsigned DestIndex =
22286 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22287 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22291 // Create this as a scalar to vector to match the instruction pattern.
22292 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22293 // countS bits are ignored when loading from memory on insertps, which
22294 // means we don't need to explicitly set them to 0.
22295 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22296 LoadScalarToVector, N->getOperand(2));
22299 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22300 // as "sbb reg,reg", since it can be extended without zext and produces
22301 // an all-ones bit which is more useful than 0/1 in some cases.
22302 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22305 return DAG.getNode(ISD::AND, DL, VT,
22306 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22307 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22308 DAG.getConstant(1, VT));
22309 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22310 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22311 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22312 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22315 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22316 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22317 TargetLowering::DAGCombinerInfo &DCI,
22318 const X86Subtarget *Subtarget) {
22320 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22321 SDValue EFLAGS = N->getOperand(1);
22323 if (CC == X86::COND_A) {
22324 // Try to convert COND_A into COND_B in an attempt to facilitate
22325 // materializing "setb reg".
22327 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22328 // cannot take an immediate as its first operand.
22330 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22331 EFLAGS.getValueType().isInteger() &&
22332 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22333 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22334 EFLAGS.getNode()->getVTList(),
22335 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22336 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22337 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22341 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22342 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22344 if (CC == X86::COND_B)
22345 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22349 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22350 if (Flags.getNode()) {
22351 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22352 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22358 // Optimize branch condition evaluation.
22360 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22361 TargetLowering::DAGCombinerInfo &DCI,
22362 const X86Subtarget *Subtarget) {
22364 SDValue Chain = N->getOperand(0);
22365 SDValue Dest = N->getOperand(1);
22366 SDValue EFLAGS = N->getOperand(3);
22367 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22371 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22372 if (Flags.getNode()) {
22373 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22374 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22381 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22382 SelectionDAG &DAG) {
22383 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22384 // optimize away operation when it's from a constant.
22386 // The general transformation is:
22387 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22388 // AND(VECTOR_CMP(x,y), constant2)
22389 // constant2 = UNARYOP(constant)
22391 // Early exit if this isn't a vector operation, the operand of the
22392 // unary operation isn't a bitwise AND, or if the sizes of the operations
22393 // aren't the same.
22394 EVT VT = N->getValueType(0);
22395 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22396 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22397 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22400 // Now check that the other operand of the AND is a constant. We could
22401 // make the transformation for non-constant splats as well, but it's unclear
22402 // that would be a benefit as it would not eliminate any operations, just
22403 // perform one more step in scalar code before moving to the vector unit.
22404 if (BuildVectorSDNode *BV =
22405 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22406 // Bail out if the vector isn't a constant.
22407 if (!BV->isConstant())
22410 // Everything checks out. Build up the new and improved node.
22412 EVT IntVT = BV->getValueType(0);
22413 // Create a new constant of the appropriate type for the transformed
22415 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22416 // The AND node needs bitcasts to/from an integer vector type around it.
22417 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22418 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22419 N->getOperand(0)->getOperand(0), MaskConst);
22420 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22427 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22428 const X86TargetLowering *XTLI) {
22429 // First try to optimize away the conversion entirely when it's
22430 // conditionally from a constant. Vectors only.
22431 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22432 if (Res != SDValue())
22435 // Now move on to more general possibilities.
22436 SDValue Op0 = N->getOperand(0);
22437 EVT InVT = Op0->getValueType(0);
22439 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22440 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22442 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22443 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22444 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22447 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22448 // a 32-bit target where SSE doesn't support i64->FP operations.
22449 if (Op0.getOpcode() == ISD::LOAD) {
22450 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22451 EVT VT = Ld->getValueType(0);
22452 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22453 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22454 !XTLI->getSubtarget()->is64Bit() &&
22456 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22457 Ld->getChain(), Op0, DAG);
22458 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22465 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22466 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22467 X86TargetLowering::DAGCombinerInfo &DCI) {
22468 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22469 // the result is either zero or one (depending on the input carry bit).
22470 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22471 if (X86::isZeroNode(N->getOperand(0)) &&
22472 X86::isZeroNode(N->getOperand(1)) &&
22473 // We don't have a good way to replace an EFLAGS use, so only do this when
22475 SDValue(N, 1).use_empty()) {
22477 EVT VT = N->getValueType(0);
22478 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22479 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22480 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22481 DAG.getConstant(X86::COND_B,MVT::i8),
22483 DAG.getConstant(1, VT));
22484 return DCI.CombineTo(N, Res1, CarryOut);
22490 // fold (add Y, (sete X, 0)) -> adc 0, Y
22491 // (add Y, (setne X, 0)) -> sbb -1, Y
22492 // (sub (sete X, 0), Y) -> sbb 0, Y
22493 // (sub (setne X, 0), Y) -> adc -1, Y
22494 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
22497 // Look through ZExts.
22498 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
22499 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
22502 SDValue SetCC = Ext.getOperand(0);
22503 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
22506 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
22507 if (CC != X86::COND_E && CC != X86::COND_NE)
22510 SDValue Cmp = SetCC.getOperand(1);
22511 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
22512 !X86::isZeroNode(Cmp.getOperand(1)) ||
22513 !Cmp.getOperand(0).getValueType().isInteger())
22516 SDValue CmpOp0 = Cmp.getOperand(0);
22517 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
22518 DAG.getConstant(1, CmpOp0.getValueType()));
22520 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
22521 if (CC == X86::COND_NE)
22522 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
22523 DL, OtherVal.getValueType(), OtherVal,
22524 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
22525 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
22526 DL, OtherVal.getValueType(), OtherVal,
22527 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
22530 /// PerformADDCombine - Do target-specific dag combines on integer adds.
22531 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
22532 const X86Subtarget *Subtarget) {
22533 EVT VT = N->getValueType(0);
22534 SDValue Op0 = N->getOperand(0);
22535 SDValue Op1 = N->getOperand(1);
22537 // Try to synthesize horizontal adds from adds of shuffles.
22538 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22539 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22540 isHorizontalBinOp(Op0, Op1, true))
22541 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
22543 return OptimizeConditionalInDecrement(N, DAG);
22546 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
22547 const X86Subtarget *Subtarget) {
22548 SDValue Op0 = N->getOperand(0);
22549 SDValue Op1 = N->getOperand(1);
22551 // X86 can't encode an immediate LHS of a sub. See if we can push the
22552 // negation into a preceding instruction.
22553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
22554 // If the RHS of the sub is a XOR with one use and a constant, invert the
22555 // immediate. Then add one to the LHS of the sub so we can turn
22556 // X-Y -> X+~Y+1, saving one register.
22557 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
22558 isa<ConstantSDNode>(Op1.getOperand(1))) {
22559 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
22560 EVT VT = Op0.getValueType();
22561 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
22563 DAG.getConstant(~XorC, VT));
22564 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
22565 DAG.getConstant(C->getAPIntValue()+1, VT));
22569 // Try to synthesize horizontal adds from adds of shuffles.
22570 EVT VT = N->getValueType(0);
22571 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22572 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22573 isHorizontalBinOp(Op0, Op1, true))
22574 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
22576 return OptimizeConditionalInDecrement(N, DAG);
22579 /// performVZEXTCombine - Performs build vector combines
22580 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
22581 TargetLowering::DAGCombinerInfo &DCI,
22582 const X86Subtarget *Subtarget) {
22583 // (vzext (bitcast (vzext (x)) -> (vzext x)
22584 SDValue In = N->getOperand(0);
22585 while (In.getOpcode() == ISD::BITCAST)
22586 In = In.getOperand(0);
22588 if (In.getOpcode() != X86ISD::VZEXT)
22591 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
22595 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
22596 DAGCombinerInfo &DCI) const {
22597 SelectionDAG &DAG = DCI.DAG;
22598 switch (N->getOpcode()) {
22600 case ISD::EXTRACT_VECTOR_ELT:
22601 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22603 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22604 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22605 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
22606 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
22607 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
22608 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
22611 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
22612 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
22613 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
22614 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
22615 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
22616 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
22617 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
22618 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
22619 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
22621 case X86ISD::FOR: return PerformFORCombine(N, DAG);
22623 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
22624 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
22625 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
22626 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
22627 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
22628 case ISD::ANY_EXTEND:
22629 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
22630 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22631 case ISD::SIGN_EXTEND_INREG:
22632 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
22633 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
22634 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22635 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
22636 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
22637 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
22638 case X86ISD::SHUFP: // Handle all target specific shuffles
22639 case X86ISD::PALIGNR:
22640 case X86ISD::UNPCKH:
22641 case X86ISD::UNPCKL:
22642 case X86ISD::MOVHLPS:
22643 case X86ISD::MOVLHPS:
22644 case X86ISD::PSHUFB:
22645 case X86ISD::PSHUFD:
22646 case X86ISD::PSHUFHW:
22647 case X86ISD::PSHUFLW:
22648 case X86ISD::MOVSS:
22649 case X86ISD::MOVSD:
22650 case X86ISD::VPERMILP:
22651 case X86ISD::VPERM2X128:
22652 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
22653 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
22654 case ISD::INTRINSIC_WO_CHAIN:
22655 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
22656 case X86ISD::INSERTPS:
22657 return PerformINSERTPSCombine(N, DAG, Subtarget);
22658 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
22664 /// isTypeDesirableForOp - Return true if the target has native support for
22665 /// the specified value type and it is 'desirable' to use the type for the
22666 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
22667 /// instruction encodings are longer and some i16 instructions are slow.
22668 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
22669 if (!isTypeLegal(VT))
22671 if (VT != MVT::i16)
22678 case ISD::SIGN_EXTEND:
22679 case ISD::ZERO_EXTEND:
22680 case ISD::ANY_EXTEND:
22693 /// IsDesirableToPromoteOp - This method query the target whether it is
22694 /// beneficial for dag combiner to promote the specified node. If true, it
22695 /// should return the desired promotion type by reference.
22696 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
22697 EVT VT = Op.getValueType();
22698 if (VT != MVT::i16)
22701 bool Promote = false;
22702 bool Commute = false;
22703 switch (Op.getOpcode()) {
22706 LoadSDNode *LD = cast<LoadSDNode>(Op);
22707 // If the non-extending load has a single use and it's not live out, then it
22708 // might be folded.
22709 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
22710 Op.hasOneUse()*/) {
22711 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
22712 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
22713 // The only case where we'd want to promote LOAD (rather then it being
22714 // promoted as an operand is when it's only use is liveout.
22715 if (UI->getOpcode() != ISD::CopyToReg)
22722 case ISD::SIGN_EXTEND:
22723 case ISD::ZERO_EXTEND:
22724 case ISD::ANY_EXTEND:
22729 SDValue N0 = Op.getOperand(0);
22730 // Look out for (store (shl (load), x)).
22731 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22744 SDValue N0 = Op.getOperand(0);
22745 SDValue N1 = Op.getOperand(1);
22746 if (!Commute && MayFoldLoad(N1))
22748 // Avoid disabling potential load folding opportunities.
22749 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22751 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22761 //===----------------------------------------------------------------------===//
22762 // X86 Inline Assembly Support
22763 //===----------------------------------------------------------------------===//
22766 // Helper to match a string separated by whitespace.
22767 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
22768 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
22770 for (unsigned i = 0, e = args.size(); i != e; ++i) {
22771 StringRef piece(*args[i]);
22772 if (!s.startswith(piece)) // Check if the piece matches.
22775 s = s.substr(piece.size());
22776 StringRef::size_type pos = s.find_first_not_of(" \t");
22777 if (pos == 0) // We matched a prefix.
22785 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
22788 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
22790 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
22791 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
22792 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
22793 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
22795 if (AsmPieces.size() == 3)
22797 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
22804 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
22805 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22807 std::string AsmStr = IA->getAsmString();
22809 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22810 if (!Ty || Ty->getBitWidth() % 16 != 0)
22813 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22814 SmallVector<StringRef, 4> AsmPieces;
22815 SplitString(AsmStr, AsmPieces, ";\n");
22817 switch (AsmPieces.size()) {
22818 default: return false;
22820 // FIXME: this should verify that we are targeting a 486 or better. If not,
22821 // we will turn this bswap into something that will be lowered to logical
22822 // ops instead of emitting the bswap asm. For now, we don't support 486 or
22823 // lower so don't worry about this.
22825 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22826 matchAsm(AsmPieces[0], "bswapl", "$0") ||
22827 matchAsm(AsmPieces[0], "bswapq", "$0") ||
22828 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22829 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22830 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22831 // No need to check constraints, nothing other than the equivalent of
22832 // "=r,0" would be valid here.
22833 return IntrinsicLowering::LowerToByteSwap(CI);
22836 // rorw $$8, ${0:w} --> llvm.bswap.i16
22837 if (CI->getType()->isIntegerTy(16) &&
22838 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22839 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22840 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22842 const std::string &ConstraintsStr = IA->getConstraintString();
22843 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22844 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22845 if (clobbersFlagRegisters(AsmPieces))
22846 return IntrinsicLowering::LowerToByteSwap(CI);
22850 if (CI->getType()->isIntegerTy(32) &&
22851 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22852 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22853 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22854 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22856 const std::string &ConstraintsStr = IA->getConstraintString();
22857 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22858 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22859 if (clobbersFlagRegisters(AsmPieces))
22860 return IntrinsicLowering::LowerToByteSwap(CI);
22863 if (CI->getType()->isIntegerTy(64)) {
22864 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22865 if (Constraints.size() >= 2 &&
22866 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22867 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22868 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22869 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22870 matchAsm(AsmPieces[1], "bswap", "%edx") &&
22871 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22872 return IntrinsicLowering::LowerToByteSwap(CI);
22880 /// getConstraintType - Given a constraint letter, return the type of
22881 /// constraint it is for this target.
22882 X86TargetLowering::ConstraintType
22883 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
22884 if (Constraint.size() == 1) {
22885 switch (Constraint[0]) {
22896 return C_RegisterClass;
22920 return TargetLowering::getConstraintType(Constraint);
22923 /// Examine constraint type and operand type and determine a weight value.
22924 /// This object must already have been set up with the operand type
22925 /// and the current alternative constraint selected.
22926 TargetLowering::ConstraintWeight
22927 X86TargetLowering::getSingleConstraintMatchWeight(
22928 AsmOperandInfo &info, const char *constraint) const {
22929 ConstraintWeight weight = CW_Invalid;
22930 Value *CallOperandVal = info.CallOperandVal;
22931 // If we don't have a value, we can't do a match,
22932 // but allow it at the lowest weight.
22933 if (!CallOperandVal)
22935 Type *type = CallOperandVal->getType();
22936 // Look at the constraint type.
22937 switch (*constraint) {
22939 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
22950 if (CallOperandVal->getType()->isIntegerTy())
22951 weight = CW_SpecificReg;
22956 if (type->isFloatingPointTy())
22957 weight = CW_SpecificReg;
22960 if (type->isX86_MMXTy() && Subtarget->hasMMX())
22961 weight = CW_SpecificReg;
22965 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
22966 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
22967 weight = CW_Register;
22970 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
22971 if (C->getZExtValue() <= 31)
22972 weight = CW_Constant;
22976 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22977 if (C->getZExtValue() <= 63)
22978 weight = CW_Constant;
22982 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22983 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
22984 weight = CW_Constant;
22988 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22989 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
22990 weight = CW_Constant;
22994 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22995 if (C->getZExtValue() <= 3)
22996 weight = CW_Constant;
23000 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23001 if (C->getZExtValue() <= 0xff)
23002 weight = CW_Constant;
23007 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23008 weight = CW_Constant;
23012 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23013 if ((C->getSExtValue() >= -0x80000000LL) &&
23014 (C->getSExtValue() <= 0x7fffffffLL))
23015 weight = CW_Constant;
23019 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23020 if (C->getZExtValue() <= 0xffffffff)
23021 weight = CW_Constant;
23028 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23029 /// with another that has more specific requirements based on the type of the
23030 /// corresponding operand.
23031 const char *X86TargetLowering::
23032 LowerXConstraint(EVT ConstraintVT) const {
23033 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23034 // 'f' like normal targets.
23035 if (ConstraintVT.isFloatingPoint()) {
23036 if (Subtarget->hasSSE2())
23038 if (Subtarget->hasSSE1())
23042 return TargetLowering::LowerXConstraint(ConstraintVT);
23045 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23046 /// vector. If it is invalid, don't add anything to Ops.
23047 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23048 std::string &Constraint,
23049 std::vector<SDValue>&Ops,
23050 SelectionDAG &DAG) const {
23053 // Only support length 1 constraints for now.
23054 if (Constraint.length() > 1) return;
23056 char ConstraintLetter = Constraint[0];
23057 switch (ConstraintLetter) {
23060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23061 if (C->getZExtValue() <= 31) {
23062 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23068 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23069 if (C->getZExtValue() <= 63) {
23070 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23076 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23077 if (isInt<8>(C->getSExtValue())) {
23078 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23085 if (C->getZExtValue() <= 255) {
23086 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23092 // 32-bit signed value
23093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23094 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23095 C->getSExtValue())) {
23096 // Widen to 64 bits here to get it sign extended.
23097 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23100 // FIXME gcc accepts some relocatable values here too, but only in certain
23101 // memory models; it's complicated.
23106 // 32-bit unsigned value
23107 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23108 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23109 C->getZExtValue())) {
23110 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23114 // FIXME gcc accepts some relocatable values here too, but only in certain
23115 // memory models; it's complicated.
23119 // Literal immediates are always ok.
23120 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23121 // Widen to 64 bits here to get it sign extended.
23122 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23126 // In any sort of PIC mode addresses need to be computed at runtime by
23127 // adding in a register or some sort of table lookup. These can't
23128 // be used as immediates.
23129 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23132 // If we are in non-pic codegen mode, we allow the address of a global (with
23133 // an optional displacement) to be used with 'i'.
23134 GlobalAddressSDNode *GA = nullptr;
23135 int64_t Offset = 0;
23137 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23139 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23140 Offset += GA->getOffset();
23142 } else if (Op.getOpcode() == ISD::ADD) {
23143 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23144 Offset += C->getZExtValue();
23145 Op = Op.getOperand(0);
23148 } else if (Op.getOpcode() == ISD::SUB) {
23149 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23150 Offset += -C->getZExtValue();
23151 Op = Op.getOperand(0);
23156 // Otherwise, this isn't something we can handle, reject it.
23160 const GlobalValue *GV = GA->getGlobal();
23161 // If we require an extra load to get this address, as in PIC mode, we
23162 // can't accept it.
23163 if (isGlobalStubReference(
23164 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23167 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23168 GA->getValueType(0), Offset);
23173 if (Result.getNode()) {
23174 Ops.push_back(Result);
23177 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23180 std::pair<unsigned, const TargetRegisterClass*>
23181 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23183 // First, see if this is a constraint that directly corresponds to an LLVM
23185 if (Constraint.size() == 1) {
23186 // GCC Constraint Letters
23187 switch (Constraint[0]) {
23189 // TODO: Slight differences here in allocation order and leaving
23190 // RIP in the class. Do they matter any more here than they do
23191 // in the normal allocation?
23192 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23193 if (Subtarget->is64Bit()) {
23194 if (VT == MVT::i32 || VT == MVT::f32)
23195 return std::make_pair(0U, &X86::GR32RegClass);
23196 if (VT == MVT::i16)
23197 return std::make_pair(0U, &X86::GR16RegClass);
23198 if (VT == MVT::i8 || VT == MVT::i1)
23199 return std::make_pair(0U, &X86::GR8RegClass);
23200 if (VT == MVT::i64 || VT == MVT::f64)
23201 return std::make_pair(0U, &X86::GR64RegClass);
23204 // 32-bit fallthrough
23205 case 'Q': // Q_REGS
23206 if (VT == MVT::i32 || VT == MVT::f32)
23207 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23208 if (VT == MVT::i16)
23209 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23210 if (VT == MVT::i8 || VT == MVT::i1)
23211 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23212 if (VT == MVT::i64)
23213 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23215 case 'r': // GENERAL_REGS
23216 case 'l': // INDEX_REGS
23217 if (VT == MVT::i8 || VT == MVT::i1)
23218 return std::make_pair(0U, &X86::GR8RegClass);
23219 if (VT == MVT::i16)
23220 return std::make_pair(0U, &X86::GR16RegClass);
23221 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23222 return std::make_pair(0U, &X86::GR32RegClass);
23223 return std::make_pair(0U, &X86::GR64RegClass);
23224 case 'R': // LEGACY_REGS
23225 if (VT == MVT::i8 || VT == MVT::i1)
23226 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23227 if (VT == MVT::i16)
23228 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23229 if (VT == MVT::i32 || !Subtarget->is64Bit())
23230 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23231 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23232 case 'f': // FP Stack registers.
23233 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23234 // value to the correct fpstack register class.
23235 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23236 return std::make_pair(0U, &X86::RFP32RegClass);
23237 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23238 return std::make_pair(0U, &X86::RFP64RegClass);
23239 return std::make_pair(0U, &X86::RFP80RegClass);
23240 case 'y': // MMX_REGS if MMX allowed.
23241 if (!Subtarget->hasMMX()) break;
23242 return std::make_pair(0U, &X86::VR64RegClass);
23243 case 'Y': // SSE_REGS if SSE2 allowed
23244 if (!Subtarget->hasSSE2()) break;
23246 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23247 if (!Subtarget->hasSSE1()) break;
23249 switch (VT.SimpleTy) {
23251 // Scalar SSE types.
23254 return std::make_pair(0U, &X86::FR32RegClass);
23257 return std::make_pair(0U, &X86::FR64RegClass);
23265 return std::make_pair(0U, &X86::VR128RegClass);
23273 return std::make_pair(0U, &X86::VR256RegClass);
23278 return std::make_pair(0U, &X86::VR512RegClass);
23284 // Use the default implementation in TargetLowering to convert the register
23285 // constraint into a member of a register class.
23286 std::pair<unsigned, const TargetRegisterClass*> Res;
23287 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23289 // Not found as a standard register?
23291 // Map st(0) -> st(7) -> ST0
23292 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23293 tolower(Constraint[1]) == 's' &&
23294 tolower(Constraint[2]) == 't' &&
23295 Constraint[3] == '(' &&
23296 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23297 Constraint[5] == ')' &&
23298 Constraint[6] == '}') {
23300 Res.first = X86::FP0+Constraint[4]-'0';
23301 Res.second = &X86::RFP80RegClass;
23305 // GCC allows "st(0)" to be called just plain "st".
23306 if (StringRef("{st}").equals_lower(Constraint)) {
23307 Res.first = X86::FP0;
23308 Res.second = &X86::RFP80RegClass;
23313 if (StringRef("{flags}").equals_lower(Constraint)) {
23314 Res.first = X86::EFLAGS;
23315 Res.second = &X86::CCRRegClass;
23319 // 'A' means EAX + EDX.
23320 if (Constraint == "A") {
23321 Res.first = X86::EAX;
23322 Res.second = &X86::GR32_ADRegClass;
23328 // Otherwise, check to see if this is a register class of the wrong value
23329 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23330 // turn into {ax},{dx}.
23331 if (Res.second->hasType(VT))
23332 return Res; // Correct type already, nothing to do.
23334 // All of the single-register GCC register classes map their values onto
23335 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23336 // really want an 8-bit or 32-bit register, map to the appropriate register
23337 // class and return the appropriate register.
23338 if (Res.second == &X86::GR16RegClass) {
23339 if (VT == MVT::i8 || VT == MVT::i1) {
23340 unsigned DestReg = 0;
23341 switch (Res.first) {
23343 case X86::AX: DestReg = X86::AL; break;
23344 case X86::DX: DestReg = X86::DL; break;
23345 case X86::CX: DestReg = X86::CL; break;
23346 case X86::BX: DestReg = X86::BL; break;
23349 Res.first = DestReg;
23350 Res.second = &X86::GR8RegClass;
23352 } else if (VT == MVT::i32 || VT == MVT::f32) {
23353 unsigned DestReg = 0;
23354 switch (Res.first) {
23356 case X86::AX: DestReg = X86::EAX; break;
23357 case X86::DX: DestReg = X86::EDX; break;
23358 case X86::CX: DestReg = X86::ECX; break;
23359 case X86::BX: DestReg = X86::EBX; break;
23360 case X86::SI: DestReg = X86::ESI; break;
23361 case X86::DI: DestReg = X86::EDI; break;
23362 case X86::BP: DestReg = X86::EBP; break;
23363 case X86::SP: DestReg = X86::ESP; break;
23366 Res.first = DestReg;
23367 Res.second = &X86::GR32RegClass;
23369 } else if (VT == MVT::i64 || VT == MVT::f64) {
23370 unsigned DestReg = 0;
23371 switch (Res.first) {
23373 case X86::AX: DestReg = X86::RAX; break;
23374 case X86::DX: DestReg = X86::RDX; break;
23375 case X86::CX: DestReg = X86::RCX; break;
23376 case X86::BX: DestReg = X86::RBX; break;
23377 case X86::SI: DestReg = X86::RSI; break;
23378 case X86::DI: DestReg = X86::RDI; break;
23379 case X86::BP: DestReg = X86::RBP; break;
23380 case X86::SP: DestReg = X86::RSP; break;
23383 Res.first = DestReg;
23384 Res.second = &X86::GR64RegClass;
23387 } else if (Res.second == &X86::FR32RegClass ||
23388 Res.second == &X86::FR64RegClass ||
23389 Res.second == &X86::VR128RegClass ||
23390 Res.second == &X86::VR256RegClass ||
23391 Res.second == &X86::FR32XRegClass ||
23392 Res.second == &X86::FR64XRegClass ||
23393 Res.second == &X86::VR128XRegClass ||
23394 Res.second == &X86::VR256XRegClass ||
23395 Res.second == &X86::VR512RegClass) {
23396 // Handle references to XMM physical registers that got mapped into the
23397 // wrong class. This can happen with constraints like {xmm0} where the
23398 // target independent register mapper will just pick the first match it can
23399 // find, ignoring the required type.
23401 if (VT == MVT::f32 || VT == MVT::i32)
23402 Res.second = &X86::FR32RegClass;
23403 else if (VT == MVT::f64 || VT == MVT::i64)
23404 Res.second = &X86::FR64RegClass;
23405 else if (X86::VR128RegClass.hasType(VT))
23406 Res.second = &X86::VR128RegClass;
23407 else if (X86::VR256RegClass.hasType(VT))
23408 Res.second = &X86::VR256RegClass;
23409 else if (X86::VR512RegClass.hasType(VT))
23410 Res.second = &X86::VR512RegClass;
23416 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23418 // Scaling factors are not free at all.
23419 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23420 // will take 2 allocations in the out of order engine instead of 1
23421 // for plain addressing mode, i.e. inst (reg1).
23423 // vaddps (%rsi,%drx), %ymm0, %ymm1
23424 // Requires two allocations (one for the load, one for the computation)
23426 // vaddps (%rsi), %ymm0, %ymm1
23427 // Requires just 1 allocation, i.e., freeing allocations for other operations
23428 // and having less micro operations to execute.
23430 // For some X86 architectures, this is even worse because for instance for
23431 // stores, the complex addressing mode forces the instruction to use the
23432 // "load" ports instead of the dedicated "store" port.
23433 // E.g., on Haswell:
23434 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23435 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23436 if (isLegalAddressingMode(AM, Ty))
23437 // Scale represents reg2 * scale, thus account for 1
23438 // as soon as we use a second register.
23439 return AM.Scale != 0;
23443 bool X86TargetLowering::isTargetFTOL() const {
23444 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();