1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetWindows())
193 return new X86WindowsTargetObjectFile();
194 if (Subtarget->isTargetCOFF())
195 return new TargetLoweringObjectFileCOFF();
196 llvm_unreachable("unknown subtarget type");
199 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
200 : TargetLowering(TM, createTLOF(TM)) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird, it always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit since we have so many registers use the ILP scheduler, for
234 // 32-bit code use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2
247 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
248 addBypassSlowDiv(32, 8);
249 if (Subtarget->is64Bit())
250 addBypassSlowDiv(64, 16);
253 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
254 // Setup Windows compiler runtime calls.
255 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
256 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
257 setLibcallName(RTLIB::SREM_I64, "_allrem");
258 setLibcallName(RTLIB::UREM_I64, "_aullrem");
259 setLibcallName(RTLIB::MUL_I64, "_allmul");
260 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
266 // The _ftol2 runtime function has an unusual calling conv, which
267 // is modeled by a special pseudo-instruction.
268 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
270 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
271 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
274 if (Subtarget->isTargetDarwin()) {
275 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
276 setUseUnderscoreSetJmp(false);
277 setUseUnderscoreLongJmp(false);
278 } else if (Subtarget->isTargetMingw()) {
279 // MS runtime is weird: it exports _setjmp, but longjmp!
280 setUseUnderscoreSetJmp(true);
281 setUseUnderscoreLongJmp(false);
283 setUseUnderscoreSetJmp(true);
284 setUseUnderscoreLongJmp(true);
287 // Set up the register classes.
288 addRegisterClass(MVT::i8, &X86::GR8RegClass);
289 addRegisterClass(MVT::i16, &X86::GR16RegClass);
290 addRegisterClass(MVT::i32, &X86::GR32RegClass);
291 if (Subtarget->is64Bit())
292 addRegisterClass(MVT::i64, &X86::GR64RegClass);
294 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
296 // We don't accept any truncstore of integer registers.
297 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
302 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
304 // SETOEQ and SETUNE require checking two conditions.
305 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
312 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
314 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
316 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
318 if (Subtarget->is64Bit()) {
319 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
320 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
321 } else if (!TM.Options.UseSoftFloat) {
322 // We have an algorithm for SSE2->double, and we turn this into a
323 // 64-bit FILD followed by conditional FADD for other targets.
324 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 // We have an algorithm for SSE2, and we turn this into a 64-bit
326 // FILD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
330 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
332 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
333 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
335 if (!TM.Options.UseSoftFloat) {
336 // SSE has no i16 to fp conversion, only i32
337 if (X86ScalarSSEf32) {
338 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
339 // f32 and f64 cases are Legal, f80 case is not
340 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
350 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
351 // are Legal, f80 is custom lowered.
352 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
355 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
357 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
358 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
360 if (X86ScalarSSEf32) {
361 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
362 // f32 and f64 cases are Legal, f80 case is not
363 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 // Handle FP_TO_UINT by promoting the destination to a larger signed
371 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
373 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
375 if (Subtarget->is64Bit()) {
376 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
377 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
378 } else if (!TM.Options.UseSoftFloat) {
379 // Since AVX is a superset of SSE3, only check for SSE here.
380 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
381 // Expand FP_TO_UINT into a select.
382 // FIXME: We would like to use a Custom expander here eventually to do
383 // the optimal thing for SSE vs. the default expansion in the legalizer.
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
386 // With SSE3 we can use fisttpll to convert to a signed i64; without
387 // SSE, we're stuck with a fistpll.
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
391 if (isTargetFTOL()) {
392 // Use the _ftol2 runtime function, which has a pseudo-instruction
393 // to handle its weird calling convention.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
397 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
398 if (!X86ScalarSSEf64) {
399 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
400 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
401 if (Subtarget->is64Bit()) {
402 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
403 // Without SSE, i64->f64 goes through memory.
404 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
408 // Scalar integer divide and remainder are lowered to use operations that
409 // produce two results, to match the available instructions. This exposes
410 // the two-result form to trivial CSE, which is able to combine x/y and x%y
411 // into a single instruction.
413 // Scalar integer multiply-high is also lowered to use two-result
414 // operations, to match the available instructions. However, plain multiply
415 // (low) operations are left as Legal, as there are single-result
416 // instructions for this in x86. Using the two-result multiply instructions
417 // when both high and low results are needed must be arranged by dagcombine.
418 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
420 setOperationAction(ISD::MULHS, VT, Expand);
421 setOperationAction(ISD::MULHU, VT, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
423 setOperationAction(ISD::UDIV, VT, Expand);
424 setOperationAction(ISD::SREM, VT, Expand);
425 setOperationAction(ISD::UREM, VT, Expand);
427 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
428 setOperationAction(ISD::ADDC, VT, Custom);
429 setOperationAction(ISD::ADDE, VT, Custom);
430 setOperationAction(ISD::SUBC, VT, Custom);
431 setOperationAction(ISD::SUBE, VT, Custom);
434 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
435 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
436 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
438 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
443 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
444 if (Subtarget->is64Bit())
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
448 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
449 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f32 , Expand);
451 setOperationAction(ISD::FREM , MVT::f64 , Expand);
452 setOperationAction(ISD::FREM , MVT::f80 , Expand);
453 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
455 // Promote the i8 variants and force them on up to i32 which has a shorter
457 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
459 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
460 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
461 if (Subtarget->hasBMI()) {
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
467 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
468 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
473 if (Subtarget->hasLZCNT()) {
474 // When promoting the i8 variants, force them to i32 for a shorter
476 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
485 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
487 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
491 if (Subtarget->is64Bit()) {
492 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
497 if (Subtarget->hasPOPCNT()) {
498 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
500 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
502 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
507 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
508 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
510 // These should be promoted to a larger select which is supported.
511 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
512 // X86 wants to expand cmov itself.
513 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
515 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
518 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
521 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
524 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
525 if (Subtarget->is64Bit()) {
526 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
527 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
529 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
530 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
531 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
532 // support continuation, user-level threading, and etc.. As a result, no
533 // other SjLj exception interfaces are implemented and please don't build
534 // your own exception handling based on them.
535 // LLVM/Clang supports zero-cost DWARF exception handling.
536 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
537 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
540 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
541 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
544 if (Subtarget->is64Bit())
545 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
546 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
547 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
550 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
551 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
552 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
553 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
555 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
556 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
558 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
562 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
565 if (Subtarget->hasSSE1())
566 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
568 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
570 // Expand certain atomics
571 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
573 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
575 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
578 if (!Subtarget->is64Bit()) {
579 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
590 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
593 if (Subtarget->hasCmpxchg16b()) {
594 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
597 // FIXME - use subtarget debug flags
598 if (!Subtarget->isTargetDarwin() &&
599 !Subtarget->isTargetELF() &&
600 !Subtarget->isTargetCygMing()) {
601 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
604 if (Subtarget->is64Bit()) {
605 setExceptionPointerRegister(X86::RAX);
606 setExceptionSelectorRegister(X86::RDX);
608 setExceptionPointerRegister(X86::EAX);
609 setExceptionSelectorRegister(X86::EDX);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
612 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
614 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
617 setOperationAction(ISD::TRAP, MVT::Other, Legal);
618 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
620 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
621 setOperationAction(ISD::VASTART , MVT::Other, Custom);
622 setOperationAction(ISD::VAEND , MVT::Other, Expand);
623 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
624 // TargetInfo::X86_64ABIBuiltinVaList
625 setOperationAction(ISD::VAARG , MVT::Other, Custom);
626 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
628 // TargetInfo::CharPtrBuiltinVaList
629 setOperationAction(ISD::VAARG , MVT::Other, Expand);
630 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
633 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
634 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
636 if (Subtarget->isOSWindows() && !Subtarget->isTargetMacho())
637 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
638 MVT::i64 : MVT::i32, Custom);
639 else if (TM.Options.EnableSegmentedStacks)
640 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
641 MVT::i64 : MVT::i32, Custom);
643 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
644 MVT::i64 : MVT::i32, Expand);
646 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
647 // f32 and f64 use SSE.
648 // Set up the FP register classes.
649 addRegisterClass(MVT::f32, &X86::FR32RegClass);
650 addRegisterClass(MVT::f64, &X86::FR64RegClass);
652 // Use ANDPD to simulate FABS.
653 setOperationAction(ISD::FABS , MVT::f64, Custom);
654 setOperationAction(ISD::FABS , MVT::f32, Custom);
656 // Use XORP to simulate FNEG.
657 setOperationAction(ISD::FNEG , MVT::f64, Custom);
658 setOperationAction(ISD::FNEG , MVT::f32, Custom);
660 // Use ANDPD and ORPD to simulate FCOPYSIGN.
661 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
664 // Lower this to FGETSIGNx86 plus an AND.
665 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
666 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
668 // We don't support sin/cos/fmod
669 setOperationAction(ISD::FSIN , MVT::f64, Expand);
670 setOperationAction(ISD::FCOS , MVT::f64, Expand);
671 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
672 setOperationAction(ISD::FSIN , MVT::f32, Expand);
673 setOperationAction(ISD::FCOS , MVT::f32, Expand);
674 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
676 // Expand FP immediates into loads from the stack, except for the special
678 addLegalFPImmediate(APFloat(+0.0)); // xorpd
679 addLegalFPImmediate(APFloat(+0.0f)); // xorps
680 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
681 // Use SSE for f32, x87 for f64.
682 // Set up the FP register classes.
683 addRegisterClass(MVT::f32, &X86::FR32RegClass);
684 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
686 // Use ANDPS to simulate FABS.
687 setOperationAction(ISD::FABS , MVT::f32, Custom);
689 // Use XORP to simulate FNEG.
690 setOperationAction(ISD::FNEG , MVT::f32, Custom);
692 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
694 // Use ANDPS and ORPS to simulate FCOPYSIGN.
695 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
696 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
698 // We don't support sin/cos/fmod
699 setOperationAction(ISD::FSIN , MVT::f32, Expand);
700 setOperationAction(ISD::FCOS , MVT::f32, Expand);
701 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
703 // Special cases we handle for FP constants.
704 addLegalFPImmediate(APFloat(+0.0f)); // xorps
705 addLegalFPImmediate(APFloat(+0.0)); // FLD0
706 addLegalFPImmediate(APFloat(+1.0)); // FLD1
707 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
708 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
710 if (!TM.Options.UnsafeFPMath) {
711 setOperationAction(ISD::FSIN , MVT::f64, Expand);
712 setOperationAction(ISD::FCOS , MVT::f64, Expand);
713 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
715 } else if (!TM.Options.UseSoftFloat) {
716 // f32 and f64 in x87.
717 // Set up the FP register classes.
718 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
719 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
721 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
722 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
724 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FSIN , MVT::f32, Expand);
729 setOperationAction(ISD::FCOS , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f32, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
734 addLegalFPImmediate(APFloat(+0.0)); // FLD0
735 addLegalFPImmediate(APFloat(+1.0)); // FLD1
736 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
737 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
738 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
739 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
740 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
741 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
744 // We don't support FMA.
745 setOperationAction(ISD::FMA, MVT::f64, Expand);
746 setOperationAction(ISD::FMA, MVT::f32, Expand);
748 // Long double always uses X87.
749 if (!TM.Options.UseSoftFloat) {
750 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
751 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
752 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
754 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
755 addLegalFPImmediate(TmpFlt); // FLD0
757 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
760 APFloat TmpFlt2(+1.0);
761 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
763 addLegalFPImmediate(TmpFlt2); // FLD1
764 TmpFlt2.changeSign();
765 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
768 if (!TM.Options.UnsafeFPMath) {
769 setOperationAction(ISD::FSIN , MVT::f80, Expand);
770 setOperationAction(ISD::FCOS , MVT::f80, Expand);
771 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
774 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
775 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
776 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
777 setOperationAction(ISD::FRINT, MVT::f80, Expand);
778 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
779 setOperationAction(ISD::FMA, MVT::f80, Expand);
782 // Always use a library call for pow.
783 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
785 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
787 setOperationAction(ISD::FLOG, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
789 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP, MVT::f80, Expand);
791 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
793 // First set operation action for all vector types to either promote
794 // (for widening) or expand (for scalarization). Then we will selectively
795 // turn on ones that can be effectively codegen'd.
796 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
797 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
798 MVT VT = (MVT::SimpleValueType)i;
799 setOperationAction(ISD::ADD , VT, Expand);
800 setOperationAction(ISD::SUB , VT, Expand);
801 setOperationAction(ISD::FADD, VT, Expand);
802 setOperationAction(ISD::FNEG, VT, Expand);
803 setOperationAction(ISD::FSUB, VT, Expand);
804 setOperationAction(ISD::MUL , VT, Expand);
805 setOperationAction(ISD::FMUL, VT, Expand);
806 setOperationAction(ISD::SDIV, VT, Expand);
807 setOperationAction(ISD::UDIV, VT, Expand);
808 setOperationAction(ISD::FDIV, VT, Expand);
809 setOperationAction(ISD::SREM, VT, Expand);
810 setOperationAction(ISD::UREM, VT, Expand);
811 setOperationAction(ISD::LOAD, VT, Expand);
812 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
813 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
815 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
817 setOperationAction(ISD::FABS, VT, Expand);
818 setOperationAction(ISD::FSIN, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FCOS, VT, Expand);
821 setOperationAction(ISD::FSINCOS, VT, Expand);
822 setOperationAction(ISD::FREM, VT, Expand);
823 setOperationAction(ISD::FMA, VT, Expand);
824 setOperationAction(ISD::FPOWI, VT, Expand);
825 setOperationAction(ISD::FSQRT, VT, Expand);
826 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
827 setOperationAction(ISD::FFLOOR, VT, Expand);
828 setOperationAction(ISD::FCEIL, VT, Expand);
829 setOperationAction(ISD::FTRUNC, VT, Expand);
830 setOperationAction(ISD::FRINT, VT, Expand);
831 setOperationAction(ISD::FNEARBYINT, VT, Expand);
832 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
834 setOperationAction(ISD::SDIVREM, VT, Expand);
835 setOperationAction(ISD::UDIVREM, VT, Expand);
836 setOperationAction(ISD::FPOW, VT, Expand);
837 setOperationAction(ISD::CTPOP, VT, Expand);
838 setOperationAction(ISD::CTTZ, VT, Expand);
839 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::CTLZ, VT, Expand);
841 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
842 setOperationAction(ISD::SHL, VT, Expand);
843 setOperationAction(ISD::SRA, VT, Expand);
844 setOperationAction(ISD::SRL, VT, Expand);
845 setOperationAction(ISD::ROTL, VT, Expand);
846 setOperationAction(ISD::ROTR, VT, Expand);
847 setOperationAction(ISD::BSWAP, VT, Expand);
848 setOperationAction(ISD::SETCC, VT, Expand);
849 setOperationAction(ISD::FLOG, VT, Expand);
850 setOperationAction(ISD::FLOG2, VT, Expand);
851 setOperationAction(ISD::FLOG10, VT, Expand);
852 setOperationAction(ISD::FEXP, VT, Expand);
853 setOperationAction(ISD::FEXP2, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::VSELECT, VT, Expand);
864 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
865 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
866 setTruncStoreAction(VT,
867 (MVT::SimpleValueType)InnerVT, Expand);
868 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
870 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
873 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
874 // with -msoft-float, disable use of MMX as well.
875 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
876 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
877 // No operations on x86mmx supported, everything uses intrinsics.
880 // MMX-sized vectors (other than x86mmx) are expected to be expanded
881 // into smaller operations.
882 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
883 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
884 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
885 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
886 setOperationAction(ISD::AND, MVT::v8i8, Expand);
887 setOperationAction(ISD::AND, MVT::v4i16, Expand);
888 setOperationAction(ISD::AND, MVT::v2i32, Expand);
889 setOperationAction(ISD::AND, MVT::v1i64, Expand);
890 setOperationAction(ISD::OR, MVT::v8i8, Expand);
891 setOperationAction(ISD::OR, MVT::v4i16, Expand);
892 setOperationAction(ISD::OR, MVT::v2i32, Expand);
893 setOperationAction(ISD::OR, MVT::v1i64, Expand);
894 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
895 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
896 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
897 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
901 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
903 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
904 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
905 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
906 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
910 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
912 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
913 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
915 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
916 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
917 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
918 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
919 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
920 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
921 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
922 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
926 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
930 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
932 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
933 // registers cannot be used even for integer operations.
934 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
935 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
936 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
937 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
939 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
940 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
941 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
942 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
943 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
944 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
945 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
946 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
947 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
948 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
949 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
950 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
951 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
952 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
953 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
954 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
955 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
956 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
959 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
960 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
961 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
970 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
971 MVT VT = (MVT::SimpleValueType)i;
972 // Do not attempt to custom lower non-power-of-2 vectors
973 if (!isPowerOf2_32(VT.getVectorNumElements()))
975 // Do not attempt to custom lower non-128-bit vectors
976 if (!VT.is128BitVector())
978 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
979 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
980 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
984 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
986 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
990 if (Subtarget->is64Bit()) {
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
995 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
999 // Do not attempt to promote non-128-bit vectors
1000 if (!VT.is128BitVector())
1003 setOperationAction(ISD::AND, VT, Promote);
1004 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1005 setOperationAction(ISD::OR, VT, Promote);
1006 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1007 setOperationAction(ISD::XOR, VT, Promote);
1008 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1009 setOperationAction(ISD::LOAD, VT, Promote);
1010 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1011 setOperationAction(ISD::SELECT, VT, Promote);
1012 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1015 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1017 // Custom lower v2i64 and v2f64 selects.
1018 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1020 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1021 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1024 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1027 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1028 // As there is no 64-bit GPR available, we need build a special custom
1029 // sequence to convert from v2i32 to v2f32.
1030 if (!Subtarget->is64Bit())
1031 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1034 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1036 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1039 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1040 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1041 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1042 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1043 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1045 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1046 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1047 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1048 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1051 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1056 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1062 // FIXME: Do we need to handle scalar-to-vector here?
1063 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1071 // i8 and i16 vectors are custom , because the source register and source
1072 // source memory operand types are not the same width. f32 vectors are
1073 // custom since the immediate controlling the insert encodes additional
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1078 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1083 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1085 // FIXME: these should be Legal but thats only for the case where
1086 // the index is constant. For now custom expand to deal with that.
1087 if (Subtarget->is64Bit()) {
1088 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1089 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1093 if (Subtarget->hasSSE2()) {
1094 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1095 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1097 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1098 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1100 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1101 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1103 // In the customized shift lowering, the legal cases in AVX2 will be
1105 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1114 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1117 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1118 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1123 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1125 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1127 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1129 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1139 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1142 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1152 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1153 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1155 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1157 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1160 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1163 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1165 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1167 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1168 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1170 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1173 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1174 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1187 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1200 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1203 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1205 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1206 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1209 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1210 setOperationAction(ISD::FMA, MVT::f32, Legal);
1211 setOperationAction(ISD::FMA, MVT::f64, Legal);
1214 if (Subtarget->hasInt256()) {
1215 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1216 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1217 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1218 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1220 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1221 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1222 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1223 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1225 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1226 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1227 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1228 // Don't lower v32i8 because there is no 128-bit byte mul
1230 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1232 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1234 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1235 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1236 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1237 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1244 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1247 // Don't lower v32i8 because there is no 128-bit byte mul
1250 // In the customized shift lowering, the legal cases in AVX2 will be
1252 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1253 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1255 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1256 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1258 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1260 // Custom lower several nodes for 256-bit types.
1261 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1262 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1263 MVT VT = (MVT::SimpleValueType)i;
1265 // Extract subvector is special because the value type
1266 // (result) is 128-bit but the source is 256-bit wide.
1267 if (VT.is128BitVector())
1268 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1270 // Do not attempt to custom lower other non-256-bit vectors
1271 if (!VT.is256BitVector())
1274 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1275 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1276 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1278 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1279 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1280 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1283 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1284 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1285 MVT VT = (MVT::SimpleValueType)i;
1287 // Do not attempt to promote non-256-bit vectors
1288 if (!VT.is256BitVector())
1291 setOperationAction(ISD::AND, VT, Promote);
1292 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1293 setOperationAction(ISD::OR, VT, Promote);
1294 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1295 setOperationAction(ISD::XOR, VT, Promote);
1296 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1297 setOperationAction(ISD::LOAD, VT, Promote);
1298 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1299 setOperationAction(ISD::SELECT, VT, Promote);
1300 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1304 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1305 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1308 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1310 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1311 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1312 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1314 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1315 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1316 setOperationAction(ISD::XOR, MVT::i1, Legal);
1317 setOperationAction(ISD::OR, MVT::i1, Legal);
1318 setOperationAction(ISD::AND, MVT::i1, Legal);
1319 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1322 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1323 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1324 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1326 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1333 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1339 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1340 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1341 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1343 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1344 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1345 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1346 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1347 if (Subtarget->is64Bit()) {
1348 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1350 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1359 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1360 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1362 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1364 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1365 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1366 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1367 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1368 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1369 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1373 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1374 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1377 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1378 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1379 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1380 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1381 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1383 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1384 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1386 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1390 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1391 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1392 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1393 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1396 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1399 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1400 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1402 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1404 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1405 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1407 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1408 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1410 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1411 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1413 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1414 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1415 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1416 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1417 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1418 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1420 // Custom lower several nodes.
1421 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1422 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1423 MVT VT = (MVT::SimpleValueType)i;
1425 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1426 // Extract subvector is special because the value type
1427 // (result) is 256/128-bit but the source is 512-bit wide.
1428 if (VT.is128BitVector() || VT.is256BitVector())
1429 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1431 if (VT.getVectorElementType() == MVT::i1)
1432 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1434 // Do not attempt to custom lower other non-512-bit vectors
1435 if (!VT.is512BitVector())
1438 if ( EltSize >= 32) {
1439 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1440 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1441 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1442 setOperationAction(ISD::VSELECT, VT, Legal);
1443 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1444 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1445 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1448 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1449 MVT VT = (MVT::SimpleValueType)i;
1451 // Do not attempt to promote non-256-bit vectors
1452 if (!VT.is512BitVector())
1455 setOperationAction(ISD::SELECT, VT, Promote);
1456 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1460 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1461 // of this type with custom code.
1462 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1463 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1464 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1468 // We want to custom lower some of our intrinsics.
1469 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1470 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1471 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1473 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1474 // handle type legalization for these operations here.
1476 // FIXME: We really should do custom legalization for addition and
1477 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1478 // than generic legalization for 64-bit multiplication-with-overflow, though.
1479 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1480 // Add/Sub/Mul with overflow operations are custom lowered.
1482 setOperationAction(ISD::SADDO, VT, Custom);
1483 setOperationAction(ISD::UADDO, VT, Custom);
1484 setOperationAction(ISD::SSUBO, VT, Custom);
1485 setOperationAction(ISD::USUBO, VT, Custom);
1486 setOperationAction(ISD::SMULO, VT, Custom);
1487 setOperationAction(ISD::UMULO, VT, Custom);
1490 // There are no 8-bit 3-address imul/mul instructions
1491 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1492 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1494 if (!Subtarget->is64Bit()) {
1495 // These libcalls are not available in 32-bit.
1496 setLibcallName(RTLIB::SHL_I128, 0);
1497 setLibcallName(RTLIB::SRL_I128, 0);
1498 setLibcallName(RTLIB::SRA_I128, 0);
1501 // Combine sin / cos into one node or libcall if possible.
1502 if (Subtarget->hasSinCos()) {
1503 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1504 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1505 if (Subtarget->isTargetDarwin()) {
1506 // For MacOSX, we don't want to the normal expansion of a libcall to
1507 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1509 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1510 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1514 // We have target-specific dag combine patterns for the following nodes:
1515 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1516 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1517 setTargetDAGCombine(ISD::VSELECT);
1518 setTargetDAGCombine(ISD::SELECT);
1519 setTargetDAGCombine(ISD::SHL);
1520 setTargetDAGCombine(ISD::SRA);
1521 setTargetDAGCombine(ISD::SRL);
1522 setTargetDAGCombine(ISD::OR);
1523 setTargetDAGCombine(ISD::AND);
1524 setTargetDAGCombine(ISD::ADD);
1525 setTargetDAGCombine(ISD::FADD);
1526 setTargetDAGCombine(ISD::FSUB);
1527 setTargetDAGCombine(ISD::FMA);
1528 setTargetDAGCombine(ISD::SUB);
1529 setTargetDAGCombine(ISD::LOAD);
1530 setTargetDAGCombine(ISD::STORE);
1531 setTargetDAGCombine(ISD::ZERO_EXTEND);
1532 setTargetDAGCombine(ISD::ANY_EXTEND);
1533 setTargetDAGCombine(ISD::SIGN_EXTEND);
1534 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1535 setTargetDAGCombine(ISD::TRUNCATE);
1536 setTargetDAGCombine(ISD::SINT_TO_FP);
1537 setTargetDAGCombine(ISD::SETCC);
1538 if (Subtarget->is64Bit())
1539 setTargetDAGCombine(ISD::MUL);
1540 setTargetDAGCombine(ISD::XOR);
1542 computeRegisterProperties();
1544 // On Darwin, -Os means optimize for size without hurting performance,
1545 // do not reduce the limit.
1546 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1547 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1548 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1549 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1550 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1551 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1552 setPrefLoopAlignment(4); // 2^4 bytes.
1554 // Predictable cmov don't hurt on atom because it's in-order.
1555 PredictableSelectIsExpensive = !Subtarget->isAtom();
1557 setPrefFunctionAlignment(4); // 2^4 bytes.
1560 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1562 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1564 if (Subtarget->hasAVX512())
1565 switch(VT.getVectorNumElements()) {
1566 case 8: return MVT::v8i1;
1567 case 16: return MVT::v16i1;
1570 return VT.changeVectorElementTypeToInteger();
1573 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1574 /// the desired ByVal argument alignment.
1575 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1578 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1579 if (VTy->getBitWidth() == 128)
1581 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1582 unsigned EltAlign = 0;
1583 getMaxByValAlign(ATy->getElementType(), EltAlign);
1584 if (EltAlign > MaxAlign)
1585 MaxAlign = EltAlign;
1586 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1587 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1588 unsigned EltAlign = 0;
1589 getMaxByValAlign(STy->getElementType(i), EltAlign);
1590 if (EltAlign > MaxAlign)
1591 MaxAlign = EltAlign;
1598 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1599 /// function arguments in the caller parameter area. For X86, aggregates
1600 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1601 /// are at 4-byte boundaries.
1602 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1603 if (Subtarget->is64Bit()) {
1604 // Max of 8 and alignment of type.
1605 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1612 if (Subtarget->hasSSE1())
1613 getMaxByValAlign(Ty, Align);
1617 /// getOptimalMemOpType - Returns the target specific optimal type for load
1618 /// and store operations as a result of memset, memcpy, and memmove
1619 /// lowering. If DstAlign is zero that means it's safe to destination
1620 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1621 /// means there isn't a need to check it against alignment requirement,
1622 /// probably because the source does not need to be loaded. If 'IsMemset' is
1623 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1624 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1625 /// source is constant so it does not need to be loaded.
1626 /// It returns EVT::Other if the type should be determined using generic
1627 /// target-independent logic.
1629 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1630 unsigned DstAlign, unsigned SrcAlign,
1631 bool IsMemset, bool ZeroMemset,
1633 MachineFunction &MF) const {
1634 const Function *F = MF.getFunction();
1635 if ((!IsMemset || ZeroMemset) &&
1636 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1637 Attribute::NoImplicitFloat)) {
1639 (Subtarget->isUnalignedMemAccessFast() ||
1640 ((DstAlign == 0 || DstAlign >= 16) &&
1641 (SrcAlign == 0 || SrcAlign >= 16)))) {
1643 if (Subtarget->hasInt256())
1645 if (Subtarget->hasFp256())
1648 if (Subtarget->hasSSE2())
1650 if (Subtarget->hasSSE1())
1652 } else if (!MemcpyStrSrc && Size >= 8 &&
1653 !Subtarget->is64Bit() &&
1654 Subtarget->hasSSE2()) {
1655 // Do not use f64 to lower memcpy if source is string constant. It's
1656 // better to use i32 to avoid the loads.
1660 if (Subtarget->is64Bit() && Size >= 8)
1665 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1667 return X86ScalarSSEf32;
1668 else if (VT == MVT::f64)
1669 return X86ScalarSSEf64;
1674 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1678 *Fast = Subtarget->isUnalignedMemAccessFast();
1682 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1683 /// current function. The returned value is a member of the
1684 /// MachineJumpTableInfo::JTEntryKind enum.
1685 unsigned X86TargetLowering::getJumpTableEncoding() const {
1686 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1688 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1689 Subtarget->isPICStyleGOT())
1690 return MachineJumpTableInfo::EK_Custom32;
1692 // Otherwise, use the normal jump table encoding heuristics.
1693 return TargetLowering::getJumpTableEncoding();
1697 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1698 const MachineBasicBlock *MBB,
1699 unsigned uid,MCContext &Ctx) const{
1700 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1701 Subtarget->isPICStyleGOT());
1702 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1704 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1705 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1708 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1710 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1711 SelectionDAG &DAG) const {
1712 if (!Subtarget->is64Bit())
1713 // This doesn't have SDLoc associated with it, but is not really the
1714 // same as a Register.
1715 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1719 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1720 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1722 const MCExpr *X86TargetLowering::
1723 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1724 MCContext &Ctx) const {
1725 // X86-64 uses RIP relative addressing based on the jump table label.
1726 if (Subtarget->isPICStyleRIPRel())
1727 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1729 // Otherwise, the reference is relative to the PIC base.
1730 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1733 // FIXME: Why this routine is here? Move to RegInfo!
1734 std::pair<const TargetRegisterClass*, uint8_t>
1735 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1736 const TargetRegisterClass *RRC = 0;
1738 switch (VT.SimpleTy) {
1740 return TargetLowering::findRepresentativeClass(VT);
1741 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1742 RRC = Subtarget->is64Bit() ?
1743 (const TargetRegisterClass*)&X86::GR64RegClass :
1744 (const TargetRegisterClass*)&X86::GR32RegClass;
1747 RRC = &X86::VR64RegClass;
1749 case MVT::f32: case MVT::f64:
1750 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1751 case MVT::v4f32: case MVT::v2f64:
1752 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1754 RRC = &X86::VR128RegClass;
1757 return std::make_pair(RRC, Cost);
1760 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1761 unsigned &Offset) const {
1762 if (!Subtarget->isTargetLinux())
1765 if (Subtarget->is64Bit()) {
1766 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1768 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1780 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1781 unsigned DestAS) const {
1782 assert(SrcAS != DestAS && "Expected different address spaces!");
1784 return SrcAS < 256 && DestAS < 256;
1787 //===----------------------------------------------------------------------===//
1788 // Return Value Calling Convention Implementation
1789 //===----------------------------------------------------------------------===//
1791 #include "X86GenCallingConv.inc"
1794 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1795 MachineFunction &MF, bool isVarArg,
1796 const SmallVectorImpl<ISD::OutputArg> &Outs,
1797 LLVMContext &Context) const {
1798 SmallVector<CCValAssign, 16> RVLocs;
1799 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1801 return CCInfo.CheckReturn(Outs, RetCC_X86);
1804 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1805 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1810 X86TargetLowering::LowerReturn(SDValue Chain,
1811 CallingConv::ID CallConv, bool isVarArg,
1812 const SmallVectorImpl<ISD::OutputArg> &Outs,
1813 const SmallVectorImpl<SDValue> &OutVals,
1814 SDLoc dl, SelectionDAG &DAG) const {
1815 MachineFunction &MF = DAG.getMachineFunction();
1816 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1818 SmallVector<CCValAssign, 16> RVLocs;
1819 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1820 RVLocs, *DAG.getContext());
1821 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1824 SmallVector<SDValue, 6> RetOps;
1825 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1826 // Operand #1 = Bytes To Pop
1827 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1830 // Copy the result values into the output registers.
1831 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1832 CCValAssign &VA = RVLocs[i];
1833 assert(VA.isRegLoc() && "Can only return in registers!");
1834 SDValue ValToCopy = OutVals[i];
1835 EVT ValVT = ValToCopy.getValueType();
1837 // Promote values to the appropriate types
1838 if (VA.getLocInfo() == CCValAssign::SExt)
1839 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1840 else if (VA.getLocInfo() == CCValAssign::ZExt)
1841 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1842 else if (VA.getLocInfo() == CCValAssign::AExt)
1843 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1844 else if (VA.getLocInfo() == CCValAssign::BCvt)
1845 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1847 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1848 "Unexpected FP-extend for return value.");
1850 // If this is x86-64, and we disabled SSE, we can't return FP values,
1851 // or SSE or MMX vectors.
1852 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1853 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1854 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1855 report_fatal_error("SSE register return with SSE disabled");
1857 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1858 // llvm-gcc has never done it right and no one has noticed, so this
1859 // should be OK for now.
1860 if (ValVT == MVT::f64 &&
1861 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1862 report_fatal_error("SSE2 register return with SSE2 disabled");
1864 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1865 // the RET instruction and handled by the FP Stackifier.
1866 if (VA.getLocReg() == X86::ST0 ||
1867 VA.getLocReg() == X86::ST1) {
1868 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1869 // change the value to the FP stack register class.
1870 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1871 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1872 RetOps.push_back(ValToCopy);
1873 // Don't emit a copytoreg.
1877 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1878 // which is returned in RAX / RDX.
1879 if (Subtarget->is64Bit()) {
1880 if (ValVT == MVT::x86mmx) {
1881 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1882 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1883 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1885 // If we don't have SSE2 available, convert to v4f32 so the generated
1886 // register is legal.
1887 if (!Subtarget->hasSSE2())
1888 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1893 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1894 Flag = Chain.getValue(1);
1895 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1898 // The x86-64 ABIs require that for returning structs by value we copy
1899 // the sret argument into %rax/%eax (depending on ABI) for the return.
1900 // Win32 requires us to put the sret argument to %eax as well.
1901 // We saved the argument into a virtual register in the entry block,
1902 // so now we copy the value out and into %rax/%eax.
1903 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1904 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1905 MachineFunction &MF = DAG.getMachineFunction();
1906 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1907 unsigned Reg = FuncInfo->getSRetReturnReg();
1909 "SRetReturnReg should have been set in LowerFormalArguments().");
1910 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1913 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1914 X86::RAX : X86::EAX;
1915 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1916 Flag = Chain.getValue(1);
1918 // RAX/EAX now acts like a return value.
1919 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1922 RetOps[0] = Chain; // Update chain.
1924 // Add the flag if we have it.
1926 RetOps.push_back(Flag);
1928 return DAG.getNode(X86ISD::RET_FLAG, dl,
1929 MVT::Other, &RetOps[0], RetOps.size());
1932 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1933 if (N->getNumValues() != 1)
1935 if (!N->hasNUsesOfValue(1, 0))
1938 SDValue TCChain = Chain;
1939 SDNode *Copy = *N->use_begin();
1940 if (Copy->getOpcode() == ISD::CopyToReg) {
1941 // If the copy has a glue operand, we conservatively assume it isn't safe to
1942 // perform a tail call.
1943 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1945 TCChain = Copy->getOperand(0);
1946 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1949 bool HasRet = false;
1950 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1952 if (UI->getOpcode() != X86ISD::RET_FLAG)
1965 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1966 ISD::NodeType ExtendKind) const {
1968 // TODO: Is this also valid on 32-bit?
1969 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1970 ReturnMVT = MVT::i8;
1972 ReturnMVT = MVT::i32;
1974 MVT MinVT = getRegisterType(ReturnMVT);
1975 return VT.bitsLT(MinVT) ? MinVT : VT;
1978 /// LowerCallResult - Lower the result values of a call into the
1979 /// appropriate copies out of appropriate physical registers.
1982 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1983 CallingConv::ID CallConv, bool isVarArg,
1984 const SmallVectorImpl<ISD::InputArg> &Ins,
1985 SDLoc dl, SelectionDAG &DAG,
1986 SmallVectorImpl<SDValue> &InVals) const {
1988 // Assign locations to each value returned by this call.
1989 SmallVector<CCValAssign, 16> RVLocs;
1990 bool Is64Bit = Subtarget->is64Bit();
1991 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1992 getTargetMachine(), RVLocs, *DAG.getContext());
1993 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1995 // Copy all of the result registers out of their specified physreg.
1996 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1997 CCValAssign &VA = RVLocs[i];
1998 EVT CopyVT = VA.getValVT();
2000 // If this is x86-64, and we disabled SSE, we can't return FP values
2001 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2002 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2003 report_fatal_error("SSE register return with SSE disabled");
2008 // If this is a call to a function that returns an fp value on the floating
2009 // point stack, we must guarantee the value is popped from the stack, so
2010 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2011 // if the return value is not used. We use the FpPOP_RETVAL instruction
2013 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2014 // If we prefer to use the value in xmm registers, copy it out as f80 and
2015 // use a truncate to move it from fp stack reg to xmm reg.
2016 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2017 SDValue Ops[] = { Chain, InFlag };
2018 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2019 MVT::Other, MVT::Glue, Ops), 1);
2020 Val = Chain.getValue(0);
2022 // Round the f80 to the right size, which also moves it to the appropriate
2024 if (CopyVT != VA.getValVT())
2025 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2026 // This truncation won't change the value.
2027 DAG.getIntPtrConstant(1));
2029 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2030 CopyVT, InFlag).getValue(1);
2031 Val = Chain.getValue(0);
2033 InFlag = Chain.getValue(2);
2034 InVals.push_back(Val);
2040 //===----------------------------------------------------------------------===//
2041 // C & StdCall & Fast Calling Convention implementation
2042 //===----------------------------------------------------------------------===//
2043 // StdCall calling convention seems to be standard for many Windows' API
2044 // routines and around. It differs from C calling convention just a little:
2045 // callee should clean up the stack, not caller. Symbols should be also
2046 // decorated in some fancy way :) It doesn't support any vector arguments.
2047 // For info on fast calling convention see Fast Calling Convention (tail call)
2048 // implementation LowerX86_32FastCCCallTo.
2050 /// CallIsStructReturn - Determines whether a call uses struct return
2052 enum StructReturnType {
2057 static StructReturnType
2058 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2060 return NotStructReturn;
2062 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2063 if (!Flags.isSRet())
2064 return NotStructReturn;
2065 if (Flags.isInReg())
2066 return RegStructReturn;
2067 return StackStructReturn;
2070 /// ArgsAreStructReturn - Determines whether a function uses struct
2071 /// return semantics.
2072 static StructReturnType
2073 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2075 return NotStructReturn;
2077 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2078 if (!Flags.isSRet())
2079 return NotStructReturn;
2080 if (Flags.isInReg())
2081 return RegStructReturn;
2082 return StackStructReturn;
2085 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2086 /// by "Src" to address "Dst" with size and alignment information specified by
2087 /// the specific parameter attribute. The copy will be passed as a byval
2088 /// function parameter.
2090 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2091 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2093 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2095 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2096 /*isVolatile*/false, /*AlwaysInline=*/true,
2097 MachinePointerInfo(), MachinePointerInfo());
2100 /// IsTailCallConvention - Return true if the calling convention is one that
2101 /// supports tail call optimization.
2102 static bool IsTailCallConvention(CallingConv::ID CC) {
2103 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2104 CC == CallingConv::HiPE);
2107 /// \brief Return true if the calling convention is a C calling convention.
2108 static bool IsCCallConvention(CallingConv::ID CC) {
2109 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2110 CC == CallingConv::X86_64_SysV);
2113 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2114 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2118 CallingConv::ID CalleeCC = CS.getCallingConv();
2119 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2125 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2126 /// a tailcall target by changing its ABI.
2127 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2128 bool GuaranteedTailCallOpt) {
2129 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2133 X86TargetLowering::LowerMemArgument(SDValue Chain,
2134 CallingConv::ID CallConv,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2136 SDLoc dl, SelectionDAG &DAG,
2137 const CCValAssign &VA,
2138 MachineFrameInfo *MFI,
2140 // Create the nodes corresponding to a load from this parameter slot.
2141 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2142 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2143 getTargetMachine().Options.GuaranteedTailCallOpt);
2144 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2147 // If value is passed by pointer we have address passed instead of the value
2149 if (VA.getLocInfo() == CCValAssign::Indirect)
2150 ValVT = VA.getLocVT();
2152 ValVT = VA.getValVT();
2154 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2155 // changed with more analysis.
2156 // In case of tail call optimization mark all arguments mutable. Since they
2157 // could be overwritten by lowering of arguments in case of a tail call.
2158 if (Flags.isByVal()) {
2159 unsigned Bytes = Flags.getByValSize();
2160 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2161 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2162 return DAG.getFrameIndex(FI, getPointerTy());
2164 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2165 VA.getLocMemOffset(), isImmutable);
2166 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2167 return DAG.getLoad(ValVT, dl, Chain, FIN,
2168 MachinePointerInfo::getFixedStack(FI),
2169 false, false, false, 0);
2174 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2175 CallingConv::ID CallConv,
2177 const SmallVectorImpl<ISD::InputArg> &Ins,
2180 SmallVectorImpl<SDValue> &InVals)
2182 MachineFunction &MF = DAG.getMachineFunction();
2183 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2185 const Function* Fn = MF.getFunction();
2186 if (Fn->hasExternalLinkage() &&
2187 Subtarget->isTargetCygMing() &&
2188 Fn->getName() == "main")
2189 FuncInfo->setForceFramePointer(true);
2191 MachineFrameInfo *MFI = MF.getFrameInfo();
2192 bool Is64Bit = Subtarget->is64Bit();
2193 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2195 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2196 "Var args not supported with calling convention fastcc, ghc or hipe");
2198 // Assign locations to all of the incoming arguments.
2199 SmallVector<CCValAssign, 16> ArgLocs;
2200 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2201 ArgLocs, *DAG.getContext());
2203 // Allocate shadow area for Win64
2205 CCInfo.AllocateStack(32, 8);
2207 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2209 unsigned LastVal = ~0U;
2211 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2212 CCValAssign &VA = ArgLocs[i];
2213 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2215 assert(VA.getValNo() != LastVal &&
2216 "Don't support value assigned to multiple locs yet");
2218 LastVal = VA.getValNo();
2220 if (VA.isRegLoc()) {
2221 EVT RegVT = VA.getLocVT();
2222 const TargetRegisterClass *RC;
2223 if (RegVT == MVT::i32)
2224 RC = &X86::GR32RegClass;
2225 else if (Is64Bit && RegVT == MVT::i64)
2226 RC = &X86::GR64RegClass;
2227 else if (RegVT == MVT::f32)
2228 RC = &X86::FR32RegClass;
2229 else if (RegVT == MVT::f64)
2230 RC = &X86::FR64RegClass;
2231 else if (RegVT.is512BitVector())
2232 RC = &X86::VR512RegClass;
2233 else if (RegVT.is256BitVector())
2234 RC = &X86::VR256RegClass;
2235 else if (RegVT.is128BitVector())
2236 RC = &X86::VR128RegClass;
2237 else if (RegVT == MVT::x86mmx)
2238 RC = &X86::VR64RegClass;
2239 else if (RegVT == MVT::i1)
2240 RC = &X86::VK1RegClass;
2241 else if (RegVT == MVT::v8i1)
2242 RC = &X86::VK8RegClass;
2243 else if (RegVT == MVT::v16i1)
2244 RC = &X86::VK16RegClass;
2246 llvm_unreachable("Unknown argument type!");
2248 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2249 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2251 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2252 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2254 if (VA.getLocInfo() == CCValAssign::SExt)
2255 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2256 DAG.getValueType(VA.getValVT()));
2257 else if (VA.getLocInfo() == CCValAssign::ZExt)
2258 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2259 DAG.getValueType(VA.getValVT()));
2260 else if (VA.getLocInfo() == CCValAssign::BCvt)
2261 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2263 if (VA.isExtInLoc()) {
2264 // Handle MMX values passed in XMM regs.
2265 if (RegVT.isVector())
2266 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2268 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2271 assert(VA.isMemLoc());
2272 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2275 // If value is passed via pointer - do a load.
2276 if (VA.getLocInfo() == CCValAssign::Indirect)
2277 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2278 MachinePointerInfo(), false, false, false, 0);
2280 InVals.push_back(ArgValue);
2283 // The x86-64 ABIs require that for returning structs by value we copy
2284 // the sret argument into %rax/%eax (depending on ABI) for the return.
2285 // Win32 requires us to put the sret argument to %eax as well.
2286 // Save the argument into a virtual register so that we can access it
2287 // from the return points.
2288 if (MF.getFunction()->hasStructRetAttr() &&
2289 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2290 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2291 unsigned Reg = FuncInfo->getSRetReturnReg();
2293 MVT PtrTy = getPointerTy();
2294 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2295 FuncInfo->setSRetReturnReg(Reg);
2297 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2298 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2301 unsigned StackSize = CCInfo.getNextStackOffset();
2302 // Align stack specially for tail calls.
2303 if (FuncIsMadeTailCallSafe(CallConv,
2304 MF.getTarget().Options.GuaranteedTailCallOpt))
2305 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2307 // If the function takes variable number of arguments, make a frame index for
2308 // the start of the first vararg value... for expansion of llvm.va_start.
2310 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2311 CallConv != CallingConv::X86_ThisCall)) {
2312 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2315 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2317 // FIXME: We should really autogenerate these arrays
2318 static const uint16_t GPR64ArgRegsWin64[] = {
2319 X86::RCX, X86::RDX, X86::R8, X86::R9
2321 static const uint16_t GPR64ArgRegs64Bit[] = {
2322 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2324 static const uint16_t XMMArgRegs64Bit[] = {
2325 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2326 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2328 const uint16_t *GPR64ArgRegs;
2329 unsigned NumXMMRegs = 0;
2332 // The XMM registers which might contain var arg parameters are shadowed
2333 // in their paired GPR. So we only need to save the GPR to their home
2335 TotalNumIntRegs = 4;
2336 GPR64ArgRegs = GPR64ArgRegsWin64;
2338 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2339 GPR64ArgRegs = GPR64ArgRegs64Bit;
2341 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2344 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2347 bool NoImplicitFloatOps = Fn->getAttributes().
2348 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2349 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2350 "SSE register cannot be used when SSE is disabled!");
2351 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2352 NoImplicitFloatOps) &&
2353 "SSE register cannot be used when SSE is disabled!");
2354 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2355 !Subtarget->hasSSE1())
2356 // Kernel mode asks for SSE to be disabled, so don't push them
2358 TotalNumXMMRegs = 0;
2361 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2362 // Get to the caller-allocated home save location. Add 8 to account
2363 // for the return address.
2364 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2365 FuncInfo->setRegSaveFrameIndex(
2366 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2367 // Fixup to set vararg frame on shadow area (4 x i64).
2369 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2371 // For X86-64, if there are vararg parameters that are passed via
2372 // registers, then we must store them to their spots on the stack so
2373 // they may be loaded by deferencing the result of va_next.
2374 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2375 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2376 FuncInfo->setRegSaveFrameIndex(
2377 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2381 // Store the integer parameter registers.
2382 SmallVector<SDValue, 8> MemOps;
2383 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2385 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2386 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2387 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2388 DAG.getIntPtrConstant(Offset));
2389 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2390 &X86::GR64RegClass);
2391 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2393 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2394 MachinePointerInfo::getFixedStack(
2395 FuncInfo->getRegSaveFrameIndex(), Offset),
2397 MemOps.push_back(Store);
2401 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2402 // Now store the XMM (fp + vector) parameter registers.
2403 SmallVector<SDValue, 11> SaveXMMOps;
2404 SaveXMMOps.push_back(Chain);
2406 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2407 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2408 SaveXMMOps.push_back(ALVal);
2410 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2411 FuncInfo->getRegSaveFrameIndex()));
2412 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2413 FuncInfo->getVarArgsFPOffset()));
2415 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2416 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2417 &X86::VR128RegClass);
2418 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2419 SaveXMMOps.push_back(Val);
2421 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2423 &SaveXMMOps[0], SaveXMMOps.size()));
2426 if (!MemOps.empty())
2427 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2428 &MemOps[0], MemOps.size());
2432 // Some CCs need callee pop.
2433 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2434 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2435 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2437 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2438 // If this is an sret function, the return should pop the hidden pointer.
2439 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2440 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2441 argsAreStructReturn(Ins) == StackStructReturn)
2442 FuncInfo->setBytesToPopOnReturn(4);
2446 // RegSaveFrameIndex is X86-64 only.
2447 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2448 if (CallConv == CallingConv::X86_FastCall ||
2449 CallConv == CallingConv::X86_ThisCall)
2450 // fastcc functions can't have varargs.
2451 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2454 FuncInfo->setArgumentStackSize(StackSize);
2460 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2461 SDValue StackPtr, SDValue Arg,
2462 SDLoc dl, SelectionDAG &DAG,
2463 const CCValAssign &VA,
2464 ISD::ArgFlagsTy Flags) const {
2465 unsigned LocMemOffset = VA.getLocMemOffset();
2466 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2467 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2468 if (Flags.isByVal())
2469 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2471 return DAG.getStore(Chain, dl, Arg, PtrOff,
2472 MachinePointerInfo::getStack(LocMemOffset),
2476 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2477 /// optimization is performed and it is required.
2479 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2480 SDValue &OutRetAddr, SDValue Chain,
2481 bool IsTailCall, bool Is64Bit,
2482 int FPDiff, SDLoc dl) const {
2483 // Adjust the Return address stack slot.
2484 EVT VT = getPointerTy();
2485 OutRetAddr = getReturnAddressFrameIndex(DAG);
2487 // Load the "old" Return address.
2488 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2489 false, false, false, 0);
2490 return SDValue(OutRetAddr.getNode(), 1);
2493 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2494 /// optimization is performed and it is required (FPDiff!=0).
2496 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2497 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2498 unsigned SlotSize, int FPDiff, SDLoc dl) {
2499 // Store the return address to the appropriate stack slot.
2500 if (!FPDiff) return Chain;
2501 // Calculate the new stack slot for the return address.
2502 int NewReturnAddrFI =
2503 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2505 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2506 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2507 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2513 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2514 SmallVectorImpl<SDValue> &InVals) const {
2515 SelectionDAG &DAG = CLI.DAG;
2517 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2518 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2519 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2520 SDValue Chain = CLI.Chain;
2521 SDValue Callee = CLI.Callee;
2522 CallingConv::ID CallConv = CLI.CallConv;
2523 bool &isTailCall = CLI.IsTailCall;
2524 bool isVarArg = CLI.IsVarArg;
2526 MachineFunction &MF = DAG.getMachineFunction();
2527 bool Is64Bit = Subtarget->is64Bit();
2528 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2529 StructReturnType SR = callIsStructReturn(Outs);
2530 bool IsSibcall = false;
2532 if (MF.getTarget().Options.DisableTailCalls)
2536 // Check if it's really possible to do a tail call.
2537 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2538 isVarArg, SR != NotStructReturn,
2539 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2540 Outs, OutVals, Ins, DAG);
2542 // Sibcalls are automatically detected tailcalls which do not require
2544 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2551 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2552 "Var args not supported with calling convention fastcc, ghc or hipe");
2554 // Analyze operands of the call, assigning locations to each operand.
2555 SmallVector<CCValAssign, 16> ArgLocs;
2556 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2557 ArgLocs, *DAG.getContext());
2559 // Allocate shadow area for Win64
2561 CCInfo.AllocateStack(32, 8);
2563 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2565 // Get a count of how many bytes are to be pushed on the stack.
2566 unsigned NumBytes = CCInfo.getNextStackOffset();
2568 // This is a sibcall. The memory operands are available in caller's
2569 // own caller's stack.
2571 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2572 IsTailCallConvention(CallConv))
2573 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2576 if (isTailCall && !IsSibcall) {
2577 // Lower arguments at fp - stackoffset + fpdiff.
2578 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2579 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2581 FPDiff = NumBytesCallerPushed - NumBytes;
2583 // Set the delta of movement of the returnaddr stackslot.
2584 // But only set if delta is greater than previous delta.
2585 if (FPDiff < X86Info->getTCReturnAddrDelta())
2586 X86Info->setTCReturnAddrDelta(FPDiff);
2589 unsigned NumBytesToPush = NumBytes;
2590 unsigned NumBytesToPop = NumBytes;
2592 // If we have an inalloca argument, all stack space has already been allocated
2593 // for us and be right at the top of the stack. We don't support multiple
2594 // arguments passed in memory when using inalloca.
2595 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2597 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2598 "an inalloca argument must be the only memory argument");
2602 Chain = DAG.getCALLSEQ_START(
2603 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2605 SDValue RetAddrFrIdx;
2606 // Load return address for tail calls.
2607 if (isTailCall && FPDiff)
2608 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2609 Is64Bit, FPDiff, dl);
2611 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2612 SmallVector<SDValue, 8> MemOpChains;
2615 // Walk the register/memloc assignments, inserting copies/loads. In the case
2616 // of tail call optimization arguments are handle later.
2617 const X86RegisterInfo *RegInfo =
2618 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2619 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2620 // Skip inalloca arguments, they have already been written.
2621 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2622 if (Flags.isInAlloca())
2625 CCValAssign &VA = ArgLocs[i];
2626 EVT RegVT = VA.getLocVT();
2627 SDValue Arg = OutVals[i];
2628 bool isByVal = Flags.isByVal();
2630 // Promote the value if needed.
2631 switch (VA.getLocInfo()) {
2632 default: llvm_unreachable("Unknown loc info!");
2633 case CCValAssign::Full: break;
2634 case CCValAssign::SExt:
2635 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2637 case CCValAssign::ZExt:
2638 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2640 case CCValAssign::AExt:
2641 if (RegVT.is128BitVector()) {
2642 // Special case: passing MMX values in XMM registers.
2643 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2644 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2645 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2647 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2649 case CCValAssign::BCvt:
2650 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2652 case CCValAssign::Indirect: {
2653 // Store the argument.
2654 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2655 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2656 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2657 MachinePointerInfo::getFixedStack(FI),
2664 if (VA.isRegLoc()) {
2665 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2666 if (isVarArg && IsWin64) {
2667 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2668 // shadow reg if callee is a varargs function.
2669 unsigned ShadowReg = 0;
2670 switch (VA.getLocReg()) {
2671 case X86::XMM0: ShadowReg = X86::RCX; break;
2672 case X86::XMM1: ShadowReg = X86::RDX; break;
2673 case X86::XMM2: ShadowReg = X86::R8; break;
2674 case X86::XMM3: ShadowReg = X86::R9; break;
2677 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2679 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2680 assert(VA.isMemLoc());
2681 if (StackPtr.getNode() == 0)
2682 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2684 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2685 dl, DAG, VA, Flags));
2689 if (!MemOpChains.empty())
2690 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2691 &MemOpChains[0], MemOpChains.size());
2693 if (Subtarget->isPICStyleGOT()) {
2694 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2697 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2698 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2700 // If we are tail calling and generating PIC/GOT style code load the
2701 // address of the callee into ECX. The value in ecx is used as target of
2702 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2703 // for tail calls on PIC/GOT architectures. Normally we would just put the
2704 // address of GOT into ebx and then call target@PLT. But for tail calls
2705 // ebx would be restored (since ebx is callee saved) before jumping to the
2708 // Note: The actual moving to ECX is done further down.
2709 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2710 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2711 !G->getGlobal()->hasProtectedVisibility())
2712 Callee = LowerGlobalAddress(Callee, DAG);
2713 else if (isa<ExternalSymbolSDNode>(Callee))
2714 Callee = LowerExternalSymbol(Callee, DAG);
2718 if (Is64Bit && isVarArg && !IsWin64) {
2719 // From AMD64 ABI document:
2720 // For calls that may call functions that use varargs or stdargs
2721 // (prototype-less calls or calls to functions containing ellipsis (...) in
2722 // the declaration) %al is used as hidden argument to specify the number
2723 // of SSE registers used. The contents of %al do not need to match exactly
2724 // the number of registers, but must be an ubound on the number of SSE
2725 // registers used and is in the range 0 - 8 inclusive.
2727 // Count the number of XMM registers allocated.
2728 static const uint16_t XMMArgRegs[] = {
2729 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2730 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2732 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2733 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2734 && "SSE registers cannot be used when SSE is disabled");
2736 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2737 DAG.getConstant(NumXMMRegs, MVT::i8)));
2740 // For tail calls lower the arguments to the 'real' stack slot.
2742 // Force all the incoming stack arguments to be loaded from the stack
2743 // before any new outgoing arguments are stored to the stack, because the
2744 // outgoing stack slots may alias the incoming argument stack slots, and
2745 // the alias isn't otherwise explicit. This is slightly more conservative
2746 // than necessary, because it means that each store effectively depends
2747 // on every argument instead of just those arguments it would clobber.
2748 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2750 SmallVector<SDValue, 8> MemOpChains2;
2753 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2754 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2755 CCValAssign &VA = ArgLocs[i];
2758 assert(VA.isMemLoc());
2759 SDValue Arg = OutVals[i];
2760 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2761 // Create frame index.
2762 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2763 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2764 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2765 FIN = DAG.getFrameIndex(FI, getPointerTy());
2767 if (Flags.isByVal()) {
2768 // Copy relative to framepointer.
2769 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2770 if (StackPtr.getNode() == 0)
2771 StackPtr = DAG.getCopyFromReg(Chain, dl,
2772 RegInfo->getStackRegister(),
2774 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2776 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2780 // Store relative to framepointer.
2781 MemOpChains2.push_back(
2782 DAG.getStore(ArgChain, dl, Arg, FIN,
2783 MachinePointerInfo::getFixedStack(FI),
2789 if (!MemOpChains2.empty())
2790 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2791 &MemOpChains2[0], MemOpChains2.size());
2793 // Store the return address to the appropriate stack slot.
2794 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2795 getPointerTy(), RegInfo->getSlotSize(),
2799 // Build a sequence of copy-to-reg nodes chained together with token chain
2800 // and flag operands which copy the outgoing args into registers.
2802 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2803 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2804 RegsToPass[i].second, InFlag);
2805 InFlag = Chain.getValue(1);
2808 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2809 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2810 // In the 64-bit large code model, we have to make all calls
2811 // through a register, since the call instruction's 32-bit
2812 // pc-relative offset may not be large enough to hold the whole
2814 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2815 // If the callee is a GlobalAddress node (quite common, every direct call
2816 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2819 // We should use extra load for direct calls to dllimported functions in
2821 const GlobalValue *GV = G->getGlobal();
2822 if (!GV->hasDLLImportStorageClass()) {
2823 unsigned char OpFlags = 0;
2824 bool ExtraLoad = false;
2825 unsigned WrapperKind = ISD::DELETED_NODE;
2827 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2828 // external symbols most go through the PLT in PIC mode. If the symbol
2829 // has hidden or protected visibility, or if it is static or local, then
2830 // we don't need to use the PLT - we can directly call it.
2831 if (Subtarget->isTargetELF() &&
2832 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2833 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2834 OpFlags = X86II::MO_PLT;
2835 } else if (Subtarget->isPICStyleStubAny() &&
2836 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2837 (!Subtarget->getTargetTriple().isMacOSX() ||
2838 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2839 // PC-relative references to external symbols should go through $stub,
2840 // unless we're building with the leopard linker or later, which
2841 // automatically synthesizes these stubs.
2842 OpFlags = X86II::MO_DARWIN_STUB;
2843 } else if (Subtarget->isPICStyleRIPRel() &&
2844 isa<Function>(GV) &&
2845 cast<Function>(GV)->getAttributes().
2846 hasAttribute(AttributeSet::FunctionIndex,
2847 Attribute::NonLazyBind)) {
2848 // If the function is marked as non-lazy, generate an indirect call
2849 // which loads from the GOT directly. This avoids runtime overhead
2850 // at the cost of eager binding (and one extra byte of encoding).
2851 OpFlags = X86II::MO_GOTPCREL;
2852 WrapperKind = X86ISD::WrapperRIP;
2856 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2857 G->getOffset(), OpFlags);
2859 // Add a wrapper if needed.
2860 if (WrapperKind != ISD::DELETED_NODE)
2861 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2862 // Add extra indirection if needed.
2864 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2865 MachinePointerInfo::getGOT(),
2866 false, false, false, 0);
2868 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2869 unsigned char OpFlags = 0;
2871 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2872 // external symbols should go through the PLT.
2873 if (Subtarget->isTargetELF() &&
2874 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2875 OpFlags = X86II::MO_PLT;
2876 } else if (Subtarget->isPICStyleStubAny() &&
2877 (!Subtarget->getTargetTriple().isMacOSX() ||
2878 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2879 // PC-relative references to external symbols should go through $stub,
2880 // unless we're building with the leopard linker or later, which
2881 // automatically synthesizes these stubs.
2882 OpFlags = X86II::MO_DARWIN_STUB;
2885 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2889 // Returns a chain & a flag for retval copy to use.
2890 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2891 SmallVector<SDValue, 8> Ops;
2893 if (!IsSibcall && isTailCall) {
2894 Chain = DAG.getCALLSEQ_END(Chain,
2895 DAG.getIntPtrConstant(NumBytesToPop, true),
2896 DAG.getIntPtrConstant(0, true), InFlag, dl);
2897 InFlag = Chain.getValue(1);
2900 Ops.push_back(Chain);
2901 Ops.push_back(Callee);
2904 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2906 // Add argument registers to the end of the list so that they are known live
2908 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2909 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2910 RegsToPass[i].second.getValueType()));
2912 // Add a register mask operand representing the call-preserved registers.
2913 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2914 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2915 assert(Mask && "Missing call preserved mask for calling convention");
2916 Ops.push_back(DAG.getRegisterMask(Mask));
2918 if (InFlag.getNode())
2919 Ops.push_back(InFlag);
2923 //// If this is the first return lowered for this function, add the regs
2924 //// to the liveout set for the function.
2925 // This isn't right, although it's probably harmless on x86; liveouts
2926 // should be computed from returns not tail calls. Consider a void
2927 // function making a tail call to a function returning int.
2928 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2931 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2932 InFlag = Chain.getValue(1);
2934 // Create the CALLSEQ_END node.
2935 unsigned NumBytesForCalleeToPop;
2936 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2937 getTargetMachine().Options.GuaranteedTailCallOpt))
2938 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2939 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2940 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2941 SR == StackStructReturn)
2942 // If this is a call to a struct-return function, the callee
2943 // pops the hidden struct pointer, so we have to push it back.
2944 // This is common for Darwin/X86, Linux & Mingw32 targets.
2945 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2946 NumBytesForCalleeToPop = 4;
2948 NumBytesForCalleeToPop = 0; // Callee pops nothing.
2950 // Returns a flag for retval copy to use.
2952 Chain = DAG.getCALLSEQ_END(Chain,
2953 DAG.getIntPtrConstant(NumBytesToPop, true),
2954 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
2957 InFlag = Chain.getValue(1);
2960 // Handle result values, copying them out of physregs into vregs that we
2962 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2963 Ins, dl, DAG, InVals);
2966 //===----------------------------------------------------------------------===//
2967 // Fast Calling Convention (tail call) implementation
2968 //===----------------------------------------------------------------------===//
2970 // Like std call, callee cleans arguments, convention except that ECX is
2971 // reserved for storing the tail called function address. Only 2 registers are
2972 // free for argument passing (inreg). Tail call optimization is performed
2974 // * tailcallopt is enabled
2975 // * caller/callee are fastcc
2976 // On X86_64 architecture with GOT-style position independent code only local
2977 // (within module) calls are supported at the moment.
2978 // To keep the stack aligned according to platform abi the function
2979 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2980 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2981 // If a tail called function callee has more arguments than the caller the
2982 // caller needs to make sure that there is room to move the RETADDR to. This is
2983 // achieved by reserving an area the size of the argument delta right after the
2984 // original REtADDR, but before the saved framepointer or the spilled registers
2985 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2997 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2998 /// for a 16 byte align requirement.
3000 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3001 SelectionDAG& DAG) const {
3002 MachineFunction &MF = DAG.getMachineFunction();
3003 const TargetMachine &TM = MF.getTarget();
3004 const X86RegisterInfo *RegInfo =
3005 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3006 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3007 unsigned StackAlignment = TFI.getStackAlignment();
3008 uint64_t AlignMask = StackAlignment - 1;
3009 int64_t Offset = StackSize;
3010 unsigned SlotSize = RegInfo->getSlotSize();
3011 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3012 // Number smaller than 12 so just add the difference.
3013 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3015 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3016 Offset = ((~AlignMask) & Offset) + StackAlignment +
3017 (StackAlignment-SlotSize);
3022 /// MatchingStackOffset - Return true if the given stack call argument is
3023 /// already available in the same position (relatively) of the caller's
3024 /// incoming argument stack.
3026 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3027 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3028 const X86InstrInfo *TII) {
3029 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3031 if (Arg.getOpcode() == ISD::CopyFromReg) {
3032 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3033 if (!TargetRegisterInfo::isVirtualRegister(VR))
3035 MachineInstr *Def = MRI->getVRegDef(VR);
3038 if (!Flags.isByVal()) {
3039 if (!TII->isLoadFromStackSlot(Def, FI))
3042 unsigned Opcode = Def->getOpcode();
3043 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3044 Def->getOperand(1).isFI()) {
3045 FI = Def->getOperand(1).getIndex();
3046 Bytes = Flags.getByValSize();
3050 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3051 if (Flags.isByVal())
3052 // ByVal argument is passed in as a pointer but it's now being
3053 // dereferenced. e.g.
3054 // define @foo(%struct.X* %A) {
3055 // tail call @bar(%struct.X* byval %A)
3058 SDValue Ptr = Ld->getBasePtr();
3059 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3062 FI = FINode->getIndex();
3063 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3064 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3065 FI = FINode->getIndex();
3066 Bytes = Flags.getByValSize();
3070 assert(FI != INT_MAX);
3071 if (!MFI->isFixedObjectIndex(FI))
3073 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3076 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3077 /// for tail call optimization. Targets which want to do tail call
3078 /// optimization should implement this function.
3080 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3081 CallingConv::ID CalleeCC,
3083 bool isCalleeStructRet,
3084 bool isCallerStructRet,
3086 const SmallVectorImpl<ISD::OutputArg> &Outs,
3087 const SmallVectorImpl<SDValue> &OutVals,
3088 const SmallVectorImpl<ISD::InputArg> &Ins,
3089 SelectionDAG &DAG) const {
3090 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3093 // If -tailcallopt is specified, make fastcc functions tail-callable.
3094 const MachineFunction &MF = DAG.getMachineFunction();
3095 const Function *CallerF = MF.getFunction();
3097 // If the function return type is x86_fp80 and the callee return type is not,
3098 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3099 // perform a tailcall optimization here.
3100 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3103 CallingConv::ID CallerCC = CallerF->getCallingConv();
3104 bool CCMatch = CallerCC == CalleeCC;
3105 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3106 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3108 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3109 if (IsTailCallConvention(CalleeCC) && CCMatch)
3114 // Look for obvious safe cases to perform tail call optimization that do not
3115 // require ABI changes. This is what gcc calls sibcall.
3117 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3118 // emit a special epilogue.
3119 const X86RegisterInfo *RegInfo =
3120 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3121 if (RegInfo->needsStackRealignment(MF))
3124 // Also avoid sibcall optimization if either caller or callee uses struct
3125 // return semantics.
3126 if (isCalleeStructRet || isCallerStructRet)
3129 // An stdcall/thiscall caller is expected to clean up its arguments; the
3130 // callee isn't going to do that.
3131 // FIXME: this is more restrictive than needed. We could produce a tailcall
3132 // when the stack adjustment matches. For example, with a thiscall that takes
3133 // only one argument.
3134 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3135 CallerCC == CallingConv::X86_ThisCall))
3138 // Do not sibcall optimize vararg calls unless all arguments are passed via
3140 if (isVarArg && !Outs.empty()) {
3142 // Optimizing for varargs on Win64 is unlikely to be safe without
3143 // additional testing.
3144 if (IsCalleeWin64 || IsCallerWin64)
3147 SmallVector<CCValAssign, 16> ArgLocs;
3148 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3149 getTargetMachine(), ArgLocs, *DAG.getContext());
3151 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3152 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3153 if (!ArgLocs[i].isRegLoc())
3157 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3158 // stack. Therefore, if it's not used by the call it is not safe to optimize
3159 // this into a sibcall.
3160 bool Unused = false;
3161 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3168 SmallVector<CCValAssign, 16> RVLocs;
3169 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3170 getTargetMachine(), RVLocs, *DAG.getContext());
3171 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3172 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3173 CCValAssign &VA = RVLocs[i];
3174 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3179 // If the calling conventions do not match, then we'd better make sure the
3180 // results are returned in the same way as what the caller expects.
3182 SmallVector<CCValAssign, 16> RVLocs1;
3183 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3184 getTargetMachine(), RVLocs1, *DAG.getContext());
3185 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3187 SmallVector<CCValAssign, 16> RVLocs2;
3188 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3189 getTargetMachine(), RVLocs2, *DAG.getContext());
3190 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3192 if (RVLocs1.size() != RVLocs2.size())
3194 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3195 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3197 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3199 if (RVLocs1[i].isRegLoc()) {
3200 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3203 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3209 // If the callee takes no arguments then go on to check the results of the
3211 if (!Outs.empty()) {
3212 // Check if stack adjustment is needed. For now, do not do this if any
3213 // argument is passed on the stack.
3214 SmallVector<CCValAssign, 16> ArgLocs;
3215 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3216 getTargetMachine(), ArgLocs, *DAG.getContext());
3218 // Allocate shadow area for Win64
3220 CCInfo.AllocateStack(32, 8);
3222 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3223 if (CCInfo.getNextStackOffset()) {
3224 MachineFunction &MF = DAG.getMachineFunction();
3225 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3228 // Check if the arguments are already laid out in the right way as
3229 // the caller's fixed stack objects.
3230 MachineFrameInfo *MFI = MF.getFrameInfo();
3231 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3232 const X86InstrInfo *TII =
3233 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3234 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3235 CCValAssign &VA = ArgLocs[i];
3236 SDValue Arg = OutVals[i];
3237 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3238 if (VA.getLocInfo() == CCValAssign::Indirect)
3240 if (!VA.isRegLoc()) {
3241 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3248 // If the tailcall address may be in a register, then make sure it's
3249 // possible to register allocate for it. In 32-bit, the call address can
3250 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3251 // callee-saved registers are restored. These happen to be the same
3252 // registers used to pass 'inreg' arguments so watch out for those.
3253 if (!Subtarget->is64Bit() &&
3254 ((!isa<GlobalAddressSDNode>(Callee) &&
3255 !isa<ExternalSymbolSDNode>(Callee)) ||
3256 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3257 unsigned NumInRegs = 0;
3258 // In PIC we need an extra register to formulate the address computation
3260 unsigned MaxInRegs =
3261 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3263 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3264 CCValAssign &VA = ArgLocs[i];
3267 unsigned Reg = VA.getLocReg();
3270 case X86::EAX: case X86::EDX: case X86::ECX:
3271 if (++NumInRegs == MaxInRegs)
3283 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3284 const TargetLibraryInfo *libInfo) const {
3285 return X86::createFastISel(funcInfo, libInfo);
3288 //===----------------------------------------------------------------------===//
3289 // Other Lowering Hooks
3290 //===----------------------------------------------------------------------===//
3292 static bool MayFoldLoad(SDValue Op) {
3293 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3296 static bool MayFoldIntoStore(SDValue Op) {
3297 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3300 static bool isTargetShuffle(unsigned Opcode) {
3302 default: return false;
3303 case X86ISD::PSHUFD:
3304 case X86ISD::PSHUFHW:
3305 case X86ISD::PSHUFLW:
3307 case X86ISD::PALIGNR:
3308 case X86ISD::MOVLHPS:
3309 case X86ISD::MOVLHPD:
3310 case X86ISD::MOVHLPS:
3311 case X86ISD::MOVLPS:
3312 case X86ISD::MOVLPD:
3313 case X86ISD::MOVSHDUP:
3314 case X86ISD::MOVSLDUP:
3315 case X86ISD::MOVDDUP:
3318 case X86ISD::UNPCKL:
3319 case X86ISD::UNPCKH:
3320 case X86ISD::VPERMILP:
3321 case X86ISD::VPERM2X128:
3322 case X86ISD::VPERMI:
3327 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3328 SDValue V1, SelectionDAG &DAG) {
3330 default: llvm_unreachable("Unknown x86 shuffle node");
3331 case X86ISD::MOVSHDUP:
3332 case X86ISD::MOVSLDUP:
3333 case X86ISD::MOVDDUP:
3334 return DAG.getNode(Opc, dl, VT, V1);
3338 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3339 SDValue V1, unsigned TargetMask,
3340 SelectionDAG &DAG) {
3342 default: llvm_unreachable("Unknown x86 shuffle node");
3343 case X86ISD::PSHUFD:
3344 case X86ISD::PSHUFHW:
3345 case X86ISD::PSHUFLW:
3346 case X86ISD::VPERMILP:
3347 case X86ISD::VPERMI:
3348 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3352 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3353 SDValue V1, SDValue V2, unsigned TargetMask,
3354 SelectionDAG &DAG) {
3356 default: llvm_unreachable("Unknown x86 shuffle node");
3357 case X86ISD::PALIGNR:
3359 case X86ISD::VPERM2X128:
3360 return DAG.getNode(Opc, dl, VT, V1, V2,
3361 DAG.getConstant(TargetMask, MVT::i8));
3365 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3366 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3368 default: llvm_unreachable("Unknown x86 shuffle node");
3369 case X86ISD::MOVLHPS:
3370 case X86ISD::MOVLHPD:
3371 case X86ISD::MOVHLPS:
3372 case X86ISD::MOVLPS:
3373 case X86ISD::MOVLPD:
3376 case X86ISD::UNPCKL:
3377 case X86ISD::UNPCKH:
3378 return DAG.getNode(Opc, dl, VT, V1, V2);
3382 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3383 MachineFunction &MF = DAG.getMachineFunction();
3384 const X86RegisterInfo *RegInfo =
3385 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3387 int ReturnAddrIndex = FuncInfo->getRAIndex();
3389 if (ReturnAddrIndex == 0) {
3390 // Set up a frame object for the return address.
3391 unsigned SlotSize = RegInfo->getSlotSize();
3392 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3395 FuncInfo->setRAIndex(ReturnAddrIndex);
3398 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3401 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3402 bool hasSymbolicDisplacement) {
3403 // Offset should fit into 32 bit immediate field.
3404 if (!isInt<32>(Offset))
3407 // If we don't have a symbolic displacement - we don't have any extra
3409 if (!hasSymbolicDisplacement)
3412 // FIXME: Some tweaks might be needed for medium code model.
3413 if (M != CodeModel::Small && M != CodeModel::Kernel)
3416 // For small code model we assume that latest object is 16MB before end of 31
3417 // bits boundary. We may also accept pretty large negative constants knowing
3418 // that all objects are in the positive half of address space.
3419 if (M == CodeModel::Small && Offset < 16*1024*1024)
3422 // For kernel code model we know that all object resist in the negative half
3423 // of 32bits address space. We may not accept negative offsets, since they may
3424 // be just off and we may accept pretty large positive ones.
3425 if (M == CodeModel::Kernel && Offset > 0)
3431 /// isCalleePop - Determines whether the callee is required to pop its
3432 /// own arguments. Callee pop is necessary to support tail calls.
3433 bool X86::isCalleePop(CallingConv::ID CallingConv,
3434 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3438 switch (CallingConv) {
3441 case CallingConv::X86_StdCall:
3443 case CallingConv::X86_FastCall:
3445 case CallingConv::X86_ThisCall:
3447 case CallingConv::Fast:
3449 case CallingConv::GHC:
3451 case CallingConv::HiPE:
3456 /// \brief Return true if the condition is an unsigned comparison operation.
3457 static bool isX86CCUnsigned(unsigned X86CC) {
3459 default: llvm_unreachable("Invalid integer condition!");
3460 case X86::COND_E: return true;
3461 case X86::COND_G: return false;
3462 case X86::COND_GE: return false;
3463 case X86::COND_L: return false;
3464 case X86::COND_LE: return false;
3465 case X86::COND_NE: return true;
3466 case X86::COND_B: return true;
3467 case X86::COND_A: return true;
3468 case X86::COND_BE: return true;
3469 case X86::COND_AE: return true;
3471 llvm_unreachable("covered switch fell through?!");
3474 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3475 /// specific condition code, returning the condition code and the LHS/RHS of the
3476 /// comparison to make.
3477 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3478 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3480 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3481 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3482 // X > -1 -> X == 0, jump !sign.
3483 RHS = DAG.getConstant(0, RHS.getValueType());
3484 return X86::COND_NS;
3486 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3487 // X < 0 -> X == 0, jump on sign.
3490 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3492 RHS = DAG.getConstant(0, RHS.getValueType());
3493 return X86::COND_LE;
3497 switch (SetCCOpcode) {
3498 default: llvm_unreachable("Invalid integer condition!");
3499 case ISD::SETEQ: return X86::COND_E;
3500 case ISD::SETGT: return X86::COND_G;
3501 case ISD::SETGE: return X86::COND_GE;
3502 case ISD::SETLT: return X86::COND_L;
3503 case ISD::SETLE: return X86::COND_LE;
3504 case ISD::SETNE: return X86::COND_NE;
3505 case ISD::SETULT: return X86::COND_B;
3506 case ISD::SETUGT: return X86::COND_A;
3507 case ISD::SETULE: return X86::COND_BE;
3508 case ISD::SETUGE: return X86::COND_AE;
3512 // First determine if it is required or is profitable to flip the operands.
3514 // If LHS is a foldable load, but RHS is not, flip the condition.
3515 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3516 !ISD::isNON_EXTLoad(RHS.getNode())) {
3517 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3518 std::swap(LHS, RHS);
3521 switch (SetCCOpcode) {
3527 std::swap(LHS, RHS);
3531 // On a floating point condition, the flags are set as follows:
3533 // 0 | 0 | 0 | X > Y
3534 // 0 | 0 | 1 | X < Y
3535 // 1 | 0 | 0 | X == Y
3536 // 1 | 1 | 1 | unordered
3537 switch (SetCCOpcode) {
3538 default: llvm_unreachable("Condcode should be pre-legalized away");
3540 case ISD::SETEQ: return X86::COND_E;
3541 case ISD::SETOLT: // flipped
3543 case ISD::SETGT: return X86::COND_A;
3544 case ISD::SETOLE: // flipped
3546 case ISD::SETGE: return X86::COND_AE;
3547 case ISD::SETUGT: // flipped
3549 case ISD::SETLT: return X86::COND_B;
3550 case ISD::SETUGE: // flipped
3552 case ISD::SETLE: return X86::COND_BE;
3554 case ISD::SETNE: return X86::COND_NE;
3555 case ISD::SETUO: return X86::COND_P;
3556 case ISD::SETO: return X86::COND_NP;
3558 case ISD::SETUNE: return X86::COND_INVALID;
3562 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3563 /// code. Current x86 isa includes the following FP cmov instructions:
3564 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3565 static bool hasFPCMov(unsigned X86CC) {
3581 /// isFPImmLegal - Returns true if the target can instruction select the
3582 /// specified FP immediate natively. If false, the legalizer will
3583 /// materialize the FP immediate as a load from a constant pool.
3584 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3585 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3586 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3592 /// \brief Returns true if it is beneficial to convert a load of a constant
3593 /// to just the constant itself.
3594 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3596 assert(Ty->isIntegerTy());
3598 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3599 if (BitSize == 0 || BitSize > 64)
3604 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3605 /// the specified range (L, H].
3606 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3607 return (Val < 0) || (Val >= Low && Val < Hi);
3610 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3611 /// specified value.
3612 static bool isUndefOrEqual(int Val, int CmpVal) {
3613 return (Val < 0 || Val == CmpVal);
3616 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3617 /// from position Pos and ending in Pos+Size, falls within the specified
3618 /// sequential range (L, L+Pos]. or is undef.
3619 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3620 unsigned Pos, unsigned Size, int Low) {
3621 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3622 if (!isUndefOrEqual(Mask[i], Low))
3627 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3628 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3629 /// the second operand.
3630 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3631 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3632 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3633 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3634 return (Mask[0] < 2 && Mask[1] < 2);
3638 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3639 /// is suitable for input to PSHUFHW.
3640 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3641 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3644 // Lower quadword copied in order or undef.
3645 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3648 // Upper quadword shuffled.
3649 for (unsigned i = 4; i != 8; ++i)
3650 if (!isUndefOrInRange(Mask[i], 4, 8))
3653 if (VT == MVT::v16i16) {
3654 // Lower quadword copied in order or undef.
3655 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3658 // Upper quadword shuffled.
3659 for (unsigned i = 12; i != 16; ++i)
3660 if (!isUndefOrInRange(Mask[i], 12, 16))
3667 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3668 /// is suitable for input to PSHUFLW.
3669 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3670 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3673 // Upper quadword copied in order.
3674 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3677 // Lower quadword shuffled.
3678 for (unsigned i = 0; i != 4; ++i)
3679 if (!isUndefOrInRange(Mask[i], 0, 4))
3682 if (VT == MVT::v16i16) {
3683 // Upper quadword copied in order.
3684 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3687 // Lower quadword shuffled.
3688 for (unsigned i = 8; i != 12; ++i)
3689 if (!isUndefOrInRange(Mask[i], 8, 12))
3696 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3697 /// is suitable for input to PALIGNR.
3698 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3699 const X86Subtarget *Subtarget) {
3700 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3701 (VT.is256BitVector() && !Subtarget->hasInt256()))
3704 unsigned NumElts = VT.getVectorNumElements();
3705 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3706 unsigned NumLaneElts = NumElts/NumLanes;
3708 // Do not handle 64-bit element shuffles with palignr.
3709 if (NumLaneElts == 2)
3712 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3714 for (i = 0; i != NumLaneElts; ++i) {
3719 // Lane is all undef, go to next lane
3720 if (i == NumLaneElts)
3723 int Start = Mask[i+l];
3725 // Make sure its in this lane in one of the sources
3726 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3727 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3730 // If not lane 0, then we must match lane 0
3731 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3734 // Correct second source to be contiguous with first source
3735 if (Start >= (int)NumElts)
3736 Start -= NumElts - NumLaneElts;
3738 // Make sure we're shifting in the right direction.
3739 if (Start <= (int)(i+l))
3744 // Check the rest of the elements to see if they are consecutive.
3745 for (++i; i != NumLaneElts; ++i) {
3746 int Idx = Mask[i+l];
3748 // Make sure its in this lane
3749 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3750 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3753 // If not lane 0, then we must match lane 0
3754 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3757 if (Idx >= (int)NumElts)
3758 Idx -= NumElts - NumLaneElts;
3760 if (!isUndefOrEqual(Idx, Start+i))
3769 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3770 /// the two vector operands have swapped position.
3771 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3772 unsigned NumElems) {
3773 for (unsigned i = 0; i != NumElems; ++i) {
3777 else if (idx < (int)NumElems)
3778 Mask[i] = idx + NumElems;
3780 Mask[i] = idx - NumElems;
3784 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3785 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3786 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3787 /// reverse of what x86 shuffles want.
3788 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3790 unsigned NumElems = VT.getVectorNumElements();
3791 unsigned NumLanes = VT.getSizeInBits()/128;
3792 unsigned NumLaneElems = NumElems/NumLanes;
3794 if (NumLaneElems != 2 && NumLaneElems != 4)
3797 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3798 bool symetricMaskRequired =
3799 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3801 // VSHUFPSY divides the resulting vector into 4 chunks.
3802 // The sources are also splitted into 4 chunks, and each destination
3803 // chunk must come from a different source chunk.
3805 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3806 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3808 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3809 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3811 // VSHUFPDY divides the resulting vector into 4 chunks.
3812 // The sources are also splitted into 4 chunks, and each destination
3813 // chunk must come from a different source chunk.
3815 // SRC1 => X3 X2 X1 X0
3816 // SRC2 => Y3 Y2 Y1 Y0
3818 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3820 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3821 unsigned HalfLaneElems = NumLaneElems/2;
3822 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3823 for (unsigned i = 0; i != NumLaneElems; ++i) {
3824 int Idx = Mask[i+l];
3825 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3826 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3828 // For VSHUFPSY, the mask of the second half must be the same as the
3829 // first but with the appropriate offsets. This works in the same way as
3830 // VPERMILPS works with masks.
3831 if (!symetricMaskRequired || Idx < 0)
3833 if (MaskVal[i] < 0) {
3834 MaskVal[i] = Idx - l;
3837 if ((signed)(Idx - l) != MaskVal[i])
3845 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3846 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3847 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3848 if (!VT.is128BitVector())
3851 unsigned NumElems = VT.getVectorNumElements();
3856 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3857 return isUndefOrEqual(Mask[0], 6) &&
3858 isUndefOrEqual(Mask[1], 7) &&
3859 isUndefOrEqual(Mask[2], 2) &&
3860 isUndefOrEqual(Mask[3], 3);
3863 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3864 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3866 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3867 if (!VT.is128BitVector())
3870 unsigned NumElems = VT.getVectorNumElements();
3875 return isUndefOrEqual(Mask[0], 2) &&
3876 isUndefOrEqual(Mask[1], 3) &&
3877 isUndefOrEqual(Mask[2], 2) &&
3878 isUndefOrEqual(Mask[3], 3);
3881 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3882 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3883 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3884 if (!VT.is128BitVector())
3887 unsigned NumElems = VT.getVectorNumElements();
3889 if (NumElems != 2 && NumElems != 4)
3892 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3893 if (!isUndefOrEqual(Mask[i], i + NumElems))
3896 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3897 if (!isUndefOrEqual(Mask[i], i))
3903 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3904 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3905 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3906 if (!VT.is128BitVector())
3909 unsigned NumElems = VT.getVectorNumElements();
3911 if (NumElems != 2 && NumElems != 4)
3914 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3915 if (!isUndefOrEqual(Mask[i], i))
3918 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3919 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3926 // Some special combinations that can be optimized.
3929 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3930 SelectionDAG &DAG) {
3931 MVT VT = SVOp->getSimpleValueType(0);
3934 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3937 ArrayRef<int> Mask = SVOp->getMask();
3939 // These are the special masks that may be optimized.
3940 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3941 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3942 bool MatchEvenMask = true;
3943 bool MatchOddMask = true;
3944 for (int i=0; i<8; ++i) {
3945 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3946 MatchEvenMask = false;
3947 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3948 MatchOddMask = false;
3951 if (!MatchEvenMask && !MatchOddMask)
3954 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3956 SDValue Op0 = SVOp->getOperand(0);
3957 SDValue Op1 = SVOp->getOperand(1);
3959 if (MatchEvenMask) {
3960 // Shift the second operand right to 32 bits.
3961 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3962 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3964 // Shift the first operand left to 32 bits.
3965 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3966 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3968 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3969 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3972 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3973 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3974 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3975 bool HasInt256, bool V2IsSplat = false) {
3977 assert(VT.getSizeInBits() >= 128 &&
3978 "Unsupported vector type for unpckl");
3980 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3982 unsigned NumOf256BitLanes;
3983 unsigned NumElts = VT.getVectorNumElements();
3984 if (VT.is256BitVector()) {
3985 if (NumElts != 4 && NumElts != 8 &&
3986 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3989 NumOf256BitLanes = 1;
3990 } else if (VT.is512BitVector()) {
3991 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3992 "Unsupported vector type for unpckh");
3994 NumOf256BitLanes = 2;
3997 NumOf256BitLanes = 1;
4000 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4001 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4003 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4004 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4005 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4006 int BitI = Mask[l256*NumEltsInStride+l+i];
4007 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4008 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4010 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4012 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4020 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4021 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4022 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4023 bool HasInt256, bool V2IsSplat = false) {
4024 assert(VT.getSizeInBits() >= 128 &&
4025 "Unsupported vector type for unpckh");
4027 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4029 unsigned NumOf256BitLanes;
4030 unsigned NumElts = VT.getVectorNumElements();
4031 if (VT.is256BitVector()) {
4032 if (NumElts != 4 && NumElts != 8 &&
4033 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4036 NumOf256BitLanes = 1;
4037 } else if (VT.is512BitVector()) {
4038 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4039 "Unsupported vector type for unpckh");
4041 NumOf256BitLanes = 2;
4044 NumOf256BitLanes = 1;
4047 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4048 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4050 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4051 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4052 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4053 int BitI = Mask[l256*NumEltsInStride+l+i];
4054 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4055 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4057 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4059 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4067 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4068 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4070 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4071 unsigned NumElts = VT.getVectorNumElements();
4072 bool Is256BitVec = VT.is256BitVector();
4074 if (VT.is512BitVector())
4076 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4077 "Unsupported vector type for unpckh");
4079 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4080 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4083 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4084 // FIXME: Need a better way to get rid of this, there's no latency difference
4085 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4086 // the former later. We should also remove the "_undef" special mask.
4087 if (NumElts == 4 && Is256BitVec)
4090 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4091 // independently on 128-bit lanes.
4092 unsigned NumLanes = VT.getSizeInBits()/128;
4093 unsigned NumLaneElts = NumElts/NumLanes;
4095 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4096 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4097 int BitI = Mask[l+i];
4098 int BitI1 = Mask[l+i+1];
4100 if (!isUndefOrEqual(BitI, j))
4102 if (!isUndefOrEqual(BitI1, j))
4110 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4111 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4113 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4114 unsigned NumElts = VT.getVectorNumElements();
4116 if (VT.is512BitVector())
4119 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4120 "Unsupported vector type for unpckh");
4122 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4123 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4126 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4127 // independently on 128-bit lanes.
4128 unsigned NumLanes = VT.getSizeInBits()/128;
4129 unsigned NumLaneElts = NumElts/NumLanes;
4131 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4132 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4133 int BitI = Mask[l+i];
4134 int BitI1 = Mask[l+i+1];
4135 if (!isUndefOrEqual(BitI, j))
4137 if (!isUndefOrEqual(BitI1, j))
4144 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4145 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4146 /// MOVSD, and MOVD, i.e. setting the lowest element.
4147 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4148 if (VT.getVectorElementType().getSizeInBits() < 32)
4150 if (!VT.is128BitVector())
4153 unsigned NumElts = VT.getVectorNumElements();
4155 if (!isUndefOrEqual(Mask[0], NumElts))
4158 for (unsigned i = 1; i != NumElts; ++i)
4159 if (!isUndefOrEqual(Mask[i], i))
4165 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4166 /// as permutations between 128-bit chunks or halves. As an example: this
4168 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4169 /// The first half comes from the second half of V1 and the second half from the
4170 /// the second half of V2.
4171 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4172 if (!HasFp256 || !VT.is256BitVector())
4175 // The shuffle result is divided into half A and half B. In total the two
4176 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4177 // B must come from C, D, E or F.
4178 unsigned HalfSize = VT.getVectorNumElements()/2;
4179 bool MatchA = false, MatchB = false;
4181 // Check if A comes from one of C, D, E, F.
4182 for (unsigned Half = 0; Half != 4; ++Half) {
4183 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4189 // Check if B comes from one of C, D, E, F.
4190 for (unsigned Half = 0; Half != 4; ++Half) {
4191 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4197 return MatchA && MatchB;
4200 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4201 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4202 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4203 MVT VT = SVOp->getSimpleValueType(0);
4205 unsigned HalfSize = VT.getVectorNumElements()/2;
4207 unsigned FstHalf = 0, SndHalf = 0;
4208 for (unsigned i = 0; i < HalfSize; ++i) {
4209 if (SVOp->getMaskElt(i) > 0) {
4210 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4214 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4215 if (SVOp->getMaskElt(i) > 0) {
4216 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4221 return (FstHalf | (SndHalf << 4));
4224 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4225 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4226 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4230 unsigned NumElts = VT.getVectorNumElements();
4232 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4233 for (unsigned i = 0; i != NumElts; ++i) {
4236 Imm8 |= Mask[i] << (i*2);
4241 unsigned LaneSize = 4;
4242 SmallVector<int, 4> MaskVal(LaneSize, -1);
4244 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4245 for (unsigned i = 0; i != LaneSize; ++i) {
4246 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4250 if (MaskVal[i] < 0) {
4251 MaskVal[i] = Mask[i+l] - l;
4252 Imm8 |= MaskVal[i] << (i*2);
4255 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4262 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4263 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4264 /// Note that VPERMIL mask matching is different depending whether theunderlying
4265 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4266 /// to the same elements of the low, but to the higher half of the source.
4267 /// In VPERMILPD the two lanes could be shuffled independently of each other
4268 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4269 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4270 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4271 if (VT.getSizeInBits() < 256 || EltSize < 32)
4273 bool symetricMaskRequired = (EltSize == 32);
4274 unsigned NumElts = VT.getVectorNumElements();
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned LaneSize = NumElts/NumLanes;
4278 // 2 or 4 elements in one lane
4280 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4281 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4282 for (unsigned i = 0; i != LaneSize; ++i) {
4283 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4285 if (symetricMaskRequired) {
4286 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4287 ExpectedMaskVal[i] = Mask[i+l] - l;
4290 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4298 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4299 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4300 /// element of vector 2 and the other elements to come from vector 1 in order.
4301 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4302 bool V2IsSplat = false, bool V2IsUndef = false) {
4303 if (!VT.is128BitVector())
4306 unsigned NumOps = VT.getVectorNumElements();
4307 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4310 if (!isUndefOrEqual(Mask[0], 0))
4313 for (unsigned i = 1; i != NumOps; ++i)
4314 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4315 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4316 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4322 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4324 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4325 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4326 const X86Subtarget *Subtarget) {
4327 if (!Subtarget->hasSSE3())
4330 unsigned NumElems = VT.getVectorNumElements();
4332 if ((VT.is128BitVector() && NumElems != 4) ||
4333 (VT.is256BitVector() && NumElems != 8) ||
4334 (VT.is512BitVector() && NumElems != 16))
4337 // "i+1" is the value the indexed mask element must have
4338 for (unsigned i = 0; i != NumElems; i += 2)
4339 if (!isUndefOrEqual(Mask[i], i+1) ||
4340 !isUndefOrEqual(Mask[i+1], i+1))
4346 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4347 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4348 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4349 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4350 const X86Subtarget *Subtarget) {
4351 if (!Subtarget->hasSSE3())
4354 unsigned NumElems = VT.getVectorNumElements();
4356 if ((VT.is128BitVector() && NumElems != 4) ||
4357 (VT.is256BitVector() && NumElems != 8) ||
4358 (VT.is512BitVector() && NumElems != 16))
4361 // "i" is the value the indexed mask element must have
4362 for (unsigned i = 0; i != NumElems; i += 2)
4363 if (!isUndefOrEqual(Mask[i], i) ||
4364 !isUndefOrEqual(Mask[i+1], i))
4370 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4371 /// specifies a shuffle of elements that is suitable for input to 256-bit
4372 /// version of MOVDDUP.
4373 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4374 if (!HasFp256 || !VT.is256BitVector())
4377 unsigned NumElts = VT.getVectorNumElements();
4381 for (unsigned i = 0; i != NumElts/2; ++i)
4382 if (!isUndefOrEqual(Mask[i], 0))
4384 for (unsigned i = NumElts/2; i != NumElts; ++i)
4385 if (!isUndefOrEqual(Mask[i], NumElts/2))
4390 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4391 /// specifies a shuffle of elements that is suitable for input to 128-bit
4392 /// version of MOVDDUP.
4393 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4394 if (!VT.is128BitVector())
4397 unsigned e = VT.getVectorNumElements() / 2;
4398 for (unsigned i = 0; i != e; ++i)
4399 if (!isUndefOrEqual(Mask[i], i))
4401 for (unsigned i = 0; i != e; ++i)
4402 if (!isUndefOrEqual(Mask[e+i], i))
4407 /// isVEXTRACTIndex - Return true if the specified
4408 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4409 /// suitable for instruction that extract 128 or 256 bit vectors
4410 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4411 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4412 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4415 // The index should be aligned on a vecWidth-bit boundary.
4417 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4419 MVT VT = N->getSimpleValueType(0);
4420 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4421 bool Result = (Index * ElSize) % vecWidth == 0;
4426 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4427 /// operand specifies a subvector insert that is suitable for input to
4428 /// insertion of 128 or 256-bit subvectors
4429 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4430 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4431 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4433 // The index should be aligned on a vecWidth-bit boundary.
4435 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4437 MVT VT = N->getSimpleValueType(0);
4438 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4439 bool Result = (Index * ElSize) % vecWidth == 0;
4444 bool X86::isVINSERT128Index(SDNode *N) {
4445 return isVINSERTIndex(N, 128);
4448 bool X86::isVINSERT256Index(SDNode *N) {
4449 return isVINSERTIndex(N, 256);
4452 bool X86::isVEXTRACT128Index(SDNode *N) {
4453 return isVEXTRACTIndex(N, 128);
4456 bool X86::isVEXTRACT256Index(SDNode *N) {
4457 return isVEXTRACTIndex(N, 256);
4460 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4461 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4462 /// Handles 128-bit and 256-bit.
4463 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4464 MVT VT = N->getSimpleValueType(0);
4466 assert((VT.getSizeInBits() >= 128) &&
4467 "Unsupported vector type for PSHUF/SHUFP");
4469 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4470 // independently on 128-bit lanes.
4471 unsigned NumElts = VT.getVectorNumElements();
4472 unsigned NumLanes = VT.getSizeInBits()/128;
4473 unsigned NumLaneElts = NumElts/NumLanes;
4475 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4476 "Only supports 2, 4 or 8 elements per lane");
4478 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4480 for (unsigned i = 0; i != NumElts; ++i) {
4481 int Elt = N->getMaskElt(i);
4482 if (Elt < 0) continue;
4483 Elt &= NumLaneElts - 1;
4484 unsigned ShAmt = (i << Shift) % 8;
4485 Mask |= Elt << ShAmt;
4491 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4493 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4494 MVT VT = N->getSimpleValueType(0);
4496 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4497 "Unsupported vector type for PSHUFHW");
4499 unsigned NumElts = VT.getVectorNumElements();
4502 for (unsigned l = 0; l != NumElts; l += 8) {
4503 // 8 nodes per lane, but we only care about the last 4.
4504 for (unsigned i = 0; i < 4; ++i) {
4505 int Elt = N->getMaskElt(l+i+4);
4506 if (Elt < 0) continue;
4507 Elt &= 0x3; // only 2-bits.
4508 Mask |= Elt << (i * 2);
4515 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4516 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4517 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4518 MVT VT = N->getSimpleValueType(0);
4520 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4521 "Unsupported vector type for PSHUFHW");
4523 unsigned NumElts = VT.getVectorNumElements();
4526 for (unsigned l = 0; l != NumElts; l += 8) {
4527 // 8 nodes per lane, but we only care about the first 4.
4528 for (unsigned i = 0; i < 4; ++i) {
4529 int Elt = N->getMaskElt(l+i);
4530 if (Elt < 0) continue;
4531 Elt &= 0x3; // only 2-bits
4532 Mask |= Elt << (i * 2);
4539 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4540 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4541 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4542 MVT VT = SVOp->getSimpleValueType(0);
4543 unsigned EltSize = VT.is512BitVector() ? 1 :
4544 VT.getVectorElementType().getSizeInBits() >> 3;
4546 unsigned NumElts = VT.getVectorNumElements();
4547 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4548 unsigned NumLaneElts = NumElts/NumLanes;
4552 for (i = 0; i != NumElts; ++i) {
4553 Val = SVOp->getMaskElt(i);
4557 if (Val >= (int)NumElts)
4558 Val -= NumElts - NumLaneElts;
4560 assert(Val - i > 0 && "PALIGNR imm should be positive");
4561 return (Val - i) * EltSize;
4564 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4565 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4566 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4567 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4570 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4572 MVT VecVT = N->getOperand(0).getSimpleValueType();
4573 MVT ElVT = VecVT.getVectorElementType();
4575 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4576 return Index / NumElemsPerChunk;
4579 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4580 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4581 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4582 llvm_unreachable("Illegal insert subvector for VINSERT");
4585 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4587 MVT VecVT = N->getSimpleValueType(0);
4588 MVT ElVT = VecVT.getVectorElementType();
4590 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4591 return Index / NumElemsPerChunk;
4594 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4595 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4596 /// and VINSERTI128 instructions.
4597 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4598 return getExtractVEXTRACTImmediate(N, 128);
4601 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4602 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4603 /// and VINSERTI64x4 instructions.
4604 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4605 return getExtractVEXTRACTImmediate(N, 256);
4608 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4609 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4610 /// and VINSERTI128 instructions.
4611 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4612 return getInsertVINSERTImmediate(N, 128);
4615 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4616 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4617 /// and VINSERTI64x4 instructions.
4618 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4619 return getInsertVINSERTImmediate(N, 256);
4622 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4624 bool X86::isZeroNode(SDValue Elt) {
4625 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4626 return CN->isNullValue();
4627 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4628 return CFP->getValueAPF().isPosZero();
4632 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4633 /// their permute mask.
4634 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4635 SelectionDAG &DAG) {
4636 MVT VT = SVOp->getSimpleValueType(0);
4637 unsigned NumElems = VT.getVectorNumElements();
4638 SmallVector<int, 8> MaskVec;
4640 for (unsigned i = 0; i != NumElems; ++i) {
4641 int Idx = SVOp->getMaskElt(i);
4643 if (Idx < (int)NumElems)
4648 MaskVec.push_back(Idx);
4650 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4651 SVOp->getOperand(0), &MaskVec[0]);
4654 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4655 /// match movhlps. The lower half elements should come from upper half of
4656 /// V1 (and in order), and the upper half elements should come from the upper
4657 /// half of V2 (and in order).
4658 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4659 if (!VT.is128BitVector())
4661 if (VT.getVectorNumElements() != 4)
4663 for (unsigned i = 0, e = 2; i != e; ++i)
4664 if (!isUndefOrEqual(Mask[i], i+2))
4666 for (unsigned i = 2; i != 4; ++i)
4667 if (!isUndefOrEqual(Mask[i], i+4))
4672 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4673 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4675 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4676 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4678 N = N->getOperand(0).getNode();
4679 if (!ISD::isNON_EXTLoad(N))
4682 *LD = cast<LoadSDNode>(N);
4686 // Test whether the given value is a vector value which will be legalized
4688 static bool WillBeConstantPoolLoad(SDNode *N) {
4689 if (N->getOpcode() != ISD::BUILD_VECTOR)
4692 // Check for any non-constant elements.
4693 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4694 switch (N->getOperand(i).getNode()->getOpcode()) {
4696 case ISD::ConstantFP:
4703 // Vectors of all-zeros and all-ones are materialized with special
4704 // instructions rather than being loaded.
4705 return !ISD::isBuildVectorAllZeros(N) &&
4706 !ISD::isBuildVectorAllOnes(N);
4709 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4710 /// match movlp{s|d}. The lower half elements should come from lower half of
4711 /// V1 (and in order), and the upper half elements should come from the upper
4712 /// half of V2 (and in order). And since V1 will become the source of the
4713 /// MOVLP, it must be either a vector load or a scalar load to vector.
4714 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4715 ArrayRef<int> Mask, MVT VT) {
4716 if (!VT.is128BitVector())
4719 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4721 // Is V2 is a vector load, don't do this transformation. We will try to use
4722 // load folding shufps op.
4723 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4726 unsigned NumElems = VT.getVectorNumElements();
4728 if (NumElems != 2 && NumElems != 4)
4730 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4731 if (!isUndefOrEqual(Mask[i], i))
4733 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4734 if (!isUndefOrEqual(Mask[i], i+NumElems))
4739 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4741 static bool isSplatVector(SDNode *N) {
4742 if (N->getOpcode() != ISD::BUILD_VECTOR)
4745 SDValue SplatValue = N->getOperand(0);
4746 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4747 if (N->getOperand(i) != SplatValue)
4752 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4753 /// to an zero vector.
4754 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4755 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4756 SDValue V1 = N->getOperand(0);
4757 SDValue V2 = N->getOperand(1);
4758 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4759 for (unsigned i = 0; i != NumElems; ++i) {
4760 int Idx = N->getMaskElt(i);
4761 if (Idx >= (int)NumElems) {
4762 unsigned Opc = V2.getOpcode();
4763 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4765 if (Opc != ISD::BUILD_VECTOR ||
4766 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4768 } else if (Idx >= 0) {
4769 unsigned Opc = V1.getOpcode();
4770 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4772 if (Opc != ISD::BUILD_VECTOR ||
4773 !X86::isZeroNode(V1.getOperand(Idx)))
4780 /// getZeroVector - Returns a vector of specified type with all zero elements.
4782 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4783 SelectionDAG &DAG, SDLoc dl) {
4784 assert(VT.isVector() && "Expected a vector type");
4786 // Always build SSE zero vectors as <4 x i32> bitcasted
4787 // to their dest type. This ensures they get CSE'd.
4789 if (VT.is128BitVector()) { // SSE
4790 if (Subtarget->hasSSE2()) { // SSE2
4791 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4792 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4794 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4795 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4797 } else if (VT.is256BitVector()) { // AVX
4798 if (Subtarget->hasInt256()) { // AVX2
4799 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4800 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4801 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4802 array_lengthof(Ops));
4804 // 256-bit logic and arithmetic instructions in AVX are all
4805 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4806 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4807 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4808 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4809 array_lengthof(Ops));
4811 } else if (VT.is512BitVector()) { // AVX-512
4812 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4813 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4814 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4815 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4816 } else if (VT.getScalarType() == MVT::i1) {
4817 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4818 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4819 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4820 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4821 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
4822 Ops, VT.getVectorNumElements());
4824 llvm_unreachable("Unexpected vector type");
4826 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4829 /// getOnesVector - Returns a vector of specified type with all bits set.
4830 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4831 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4832 /// Then bitcast to their original type, ensuring they get CSE'd.
4833 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4835 assert(VT.isVector() && "Expected a vector type");
4837 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4839 if (VT.is256BitVector()) {
4840 if (HasInt256) { // AVX2
4841 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4842 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4843 array_lengthof(Ops));
4845 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4846 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4848 } else if (VT.is128BitVector()) {
4849 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4851 llvm_unreachable("Unexpected vector type");
4853 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4856 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4857 /// that point to V2 points to its first element.
4858 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4859 for (unsigned i = 0; i != NumElems; ++i) {
4860 if (Mask[i] > (int)NumElems) {
4866 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4867 /// operation of specified width.
4868 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4870 unsigned NumElems = VT.getVectorNumElements();
4871 SmallVector<int, 8> Mask;
4872 Mask.push_back(NumElems);
4873 for (unsigned i = 1; i != NumElems; ++i)
4875 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4878 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4879 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4881 unsigned NumElems = VT.getVectorNumElements();
4882 SmallVector<int, 8> Mask;
4883 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4885 Mask.push_back(i + NumElems);
4887 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4890 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4891 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4893 unsigned NumElems = VT.getVectorNumElements();
4894 SmallVector<int, 8> Mask;
4895 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4896 Mask.push_back(i + Half);
4897 Mask.push_back(i + NumElems + Half);
4899 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4902 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4903 // a generic shuffle instruction because the target has no such instructions.
4904 // Generate shuffles which repeat i16 and i8 several times until they can be
4905 // represented by v4f32 and then be manipulated by target suported shuffles.
4906 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4907 MVT VT = V.getSimpleValueType();
4908 int NumElems = VT.getVectorNumElements();
4911 while (NumElems > 4) {
4912 if (EltNo < NumElems/2) {
4913 V = getUnpackl(DAG, dl, VT, V, V);
4915 V = getUnpackh(DAG, dl, VT, V, V);
4916 EltNo -= NumElems/2;
4923 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4924 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4925 MVT VT = V.getSimpleValueType();
4928 if (VT.is128BitVector()) {
4929 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4930 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4931 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4933 } else if (VT.is256BitVector()) {
4934 // To use VPERMILPS to splat scalars, the second half of indicies must
4935 // refer to the higher part, which is a duplication of the lower one,
4936 // because VPERMILPS can only handle in-lane permutations.
4937 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4938 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4940 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4941 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4944 llvm_unreachable("Vector size not supported");
4946 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4949 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4950 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4951 MVT SrcVT = SV->getSimpleValueType(0);
4952 SDValue V1 = SV->getOperand(0);
4955 int EltNo = SV->getSplatIndex();
4956 int NumElems = SrcVT.getVectorNumElements();
4957 bool Is256BitVec = SrcVT.is256BitVector();
4959 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4960 "Unknown how to promote splat for type");
4962 // Extract the 128-bit part containing the splat element and update
4963 // the splat element index when it refers to the higher register.
4965 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4966 if (EltNo >= NumElems/2)
4967 EltNo -= NumElems/2;
4970 // All i16 and i8 vector types can't be used directly by a generic shuffle
4971 // instruction because the target has no such instruction. Generate shuffles
4972 // which repeat i16 and i8 several times until they fit in i32, and then can
4973 // be manipulated by target suported shuffles.
4974 MVT EltVT = SrcVT.getVectorElementType();
4975 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4976 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4978 // Recreate the 256-bit vector and place the same 128-bit vector
4979 // into the low and high part. This is necessary because we want
4980 // to use VPERM* to shuffle the vectors
4982 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4985 return getLegalSplat(DAG, V1, EltNo);
4988 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4989 /// vector of zero or undef vector. This produces a shuffle where the low
4990 /// element of V2 is swizzled into the zero/undef vector, landing at element
4991 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4992 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4994 const X86Subtarget *Subtarget,
4995 SelectionDAG &DAG) {
4996 MVT VT = V2.getSimpleValueType();
4998 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4999 unsigned NumElems = VT.getVectorNumElements();
5000 SmallVector<int, 16> MaskVec;
5001 for (unsigned i = 0; i != NumElems; ++i)
5002 // If this is the insertion idx, put the low elt of V2 here.
5003 MaskVec.push_back(i == Idx ? NumElems : i);
5004 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5007 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5008 /// target specific opcode. Returns true if the Mask could be calculated.
5009 /// Sets IsUnary to true if only uses one source.
5010 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5011 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5012 unsigned NumElems = VT.getVectorNumElements();
5016 switch(N->getOpcode()) {
5018 ImmN = N->getOperand(N->getNumOperands()-1);
5019 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5021 case X86ISD::UNPCKH:
5022 DecodeUNPCKHMask(VT, Mask);
5024 case X86ISD::UNPCKL:
5025 DecodeUNPCKLMask(VT, Mask);
5027 case X86ISD::MOVHLPS:
5028 DecodeMOVHLPSMask(NumElems, Mask);
5030 case X86ISD::MOVLHPS:
5031 DecodeMOVLHPSMask(NumElems, Mask);
5033 case X86ISD::PALIGNR:
5034 ImmN = N->getOperand(N->getNumOperands()-1);
5035 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5037 case X86ISD::PSHUFD:
5038 case X86ISD::VPERMILP:
5039 ImmN = N->getOperand(N->getNumOperands()-1);
5040 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5043 case X86ISD::PSHUFHW:
5044 ImmN = N->getOperand(N->getNumOperands()-1);
5045 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5048 case X86ISD::PSHUFLW:
5049 ImmN = N->getOperand(N->getNumOperands()-1);
5050 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5053 case X86ISD::VPERMI:
5054 ImmN = N->getOperand(N->getNumOperands()-1);
5055 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5059 case X86ISD::MOVSD: {
5060 // The index 0 always comes from the first element of the second source,
5061 // this is why MOVSS and MOVSD are used in the first place. The other
5062 // elements come from the other positions of the first source vector
5063 Mask.push_back(NumElems);
5064 for (unsigned i = 1; i != NumElems; ++i) {
5069 case X86ISD::VPERM2X128:
5070 ImmN = N->getOperand(N->getNumOperands()-1);
5071 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5072 if (Mask.empty()) return false;
5074 case X86ISD::MOVDDUP:
5075 case X86ISD::MOVLHPD:
5076 case X86ISD::MOVLPD:
5077 case X86ISD::MOVLPS:
5078 case X86ISD::MOVSHDUP:
5079 case X86ISD::MOVSLDUP:
5080 // Not yet implemented
5082 default: llvm_unreachable("unknown target shuffle node");
5088 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5089 /// element of the result of the vector shuffle.
5090 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5093 return SDValue(); // Limit search depth.
5095 SDValue V = SDValue(N, 0);
5096 EVT VT = V.getValueType();
5097 unsigned Opcode = V.getOpcode();
5099 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5100 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5101 int Elt = SV->getMaskElt(Index);
5104 return DAG.getUNDEF(VT.getVectorElementType());
5106 unsigned NumElems = VT.getVectorNumElements();
5107 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5108 : SV->getOperand(1);
5109 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5112 // Recurse into target specific vector shuffles to find scalars.
5113 if (isTargetShuffle(Opcode)) {
5114 MVT ShufVT = V.getSimpleValueType();
5115 unsigned NumElems = ShufVT.getVectorNumElements();
5116 SmallVector<int, 16> ShuffleMask;
5119 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5122 int Elt = ShuffleMask[Index];
5124 return DAG.getUNDEF(ShufVT.getVectorElementType());
5126 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5128 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5132 // Actual nodes that may contain scalar elements
5133 if (Opcode == ISD::BITCAST) {
5134 V = V.getOperand(0);
5135 EVT SrcVT = V.getValueType();
5136 unsigned NumElems = VT.getVectorNumElements();
5138 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5142 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5143 return (Index == 0) ? V.getOperand(0)
5144 : DAG.getUNDEF(VT.getVectorElementType());
5146 if (V.getOpcode() == ISD::BUILD_VECTOR)
5147 return V.getOperand(Index);
5152 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5153 /// shuffle operation which come from a consecutively from a zero. The
5154 /// search can start in two different directions, from left or right.
5155 /// We count undefs as zeros until PreferredNum is reached.
5156 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5157 unsigned NumElems, bool ZerosFromLeft,
5159 unsigned PreferredNum = -1U) {
5160 unsigned NumZeros = 0;
5161 for (unsigned i = 0; i != NumElems; ++i) {
5162 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5163 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5167 if (X86::isZeroNode(Elt))
5169 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5170 NumZeros = std::min(NumZeros + 1, PreferredNum);
5178 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5179 /// correspond consecutively to elements from one of the vector operands,
5180 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5182 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5183 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5184 unsigned NumElems, unsigned &OpNum) {
5185 bool SeenV1 = false;
5186 bool SeenV2 = false;
5188 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5189 int Idx = SVOp->getMaskElt(i);
5190 // Ignore undef indicies
5194 if (Idx < (int)NumElems)
5199 // Only accept consecutive elements from the same vector
5200 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5204 OpNum = SeenV1 ? 0 : 1;
5208 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5209 /// logical left shift of a vector.
5210 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5211 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5213 SVOp->getSimpleValueType(0).getVectorNumElements();
5214 unsigned NumZeros = getNumOfConsecutiveZeros(
5215 SVOp, NumElems, false /* check zeros from right */, DAG,
5216 SVOp->getMaskElt(0));
5222 // Considering the elements in the mask that are not consecutive zeros,
5223 // check if they consecutively come from only one of the source vectors.
5225 // V1 = {X, A, B, C} 0
5227 // vector_shuffle V1, V2 <1, 2, 3, X>
5229 if (!isShuffleMaskConsecutive(SVOp,
5230 0, // Mask Start Index
5231 NumElems-NumZeros, // Mask End Index(exclusive)
5232 NumZeros, // Where to start looking in the src vector
5233 NumElems, // Number of elements in vector
5234 OpSrc)) // Which source operand ?
5239 ShVal = SVOp->getOperand(OpSrc);
5243 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5244 /// logical left shift of a vector.
5245 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5246 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5248 SVOp->getSimpleValueType(0).getVectorNumElements();
5249 unsigned NumZeros = getNumOfConsecutiveZeros(
5250 SVOp, NumElems, true /* check zeros from left */, DAG,
5251 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5257 // Considering the elements in the mask that are not consecutive zeros,
5258 // check if they consecutively come from only one of the source vectors.
5260 // 0 { A, B, X, X } = V2
5262 // vector_shuffle V1, V2 <X, X, 4, 5>
5264 if (!isShuffleMaskConsecutive(SVOp,
5265 NumZeros, // Mask Start Index
5266 NumElems, // Mask End Index(exclusive)
5267 0, // Where to start looking in the src vector
5268 NumElems, // Number of elements in vector
5269 OpSrc)) // Which source operand ?
5274 ShVal = SVOp->getOperand(OpSrc);
5278 /// isVectorShift - Returns true if the shuffle can be implemented as a
5279 /// logical left or right shift of a vector.
5280 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5281 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5282 // Although the logic below support any bitwidth size, there are no
5283 // shift instructions which handle more than 128-bit vectors.
5284 if (!SVOp->getSimpleValueType(0).is128BitVector())
5287 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5288 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5294 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5296 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5297 unsigned NumNonZero, unsigned NumZero,
5299 const X86Subtarget* Subtarget,
5300 const TargetLowering &TLI) {
5307 for (unsigned i = 0; i < 16; ++i) {
5308 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5309 if (ThisIsNonZero && First) {
5311 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5313 V = DAG.getUNDEF(MVT::v8i16);
5318 SDValue ThisElt(0, 0), LastElt(0, 0);
5319 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5320 if (LastIsNonZero) {
5321 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5322 MVT::i16, Op.getOperand(i-1));
5324 if (ThisIsNonZero) {
5325 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5326 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5327 ThisElt, DAG.getConstant(8, MVT::i8));
5329 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5333 if (ThisElt.getNode())
5334 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5335 DAG.getIntPtrConstant(i/2));
5339 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5342 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5344 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5345 unsigned NumNonZero, unsigned NumZero,
5347 const X86Subtarget* Subtarget,
5348 const TargetLowering &TLI) {
5355 for (unsigned i = 0; i < 8; ++i) {
5356 bool isNonZero = (NonZeros & (1 << i)) != 0;
5360 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5362 V = DAG.getUNDEF(MVT::v8i16);
5365 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5366 MVT::v8i16, V, Op.getOperand(i),
5367 DAG.getIntPtrConstant(i));
5374 /// getVShift - Return a vector logical shift node.
5376 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5377 unsigned NumBits, SelectionDAG &DAG,
5378 const TargetLowering &TLI, SDLoc dl) {
5379 assert(VT.is128BitVector() && "Unknown type for VShift");
5380 EVT ShVT = MVT::v2i64;
5381 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5382 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5383 return DAG.getNode(ISD::BITCAST, dl, VT,
5384 DAG.getNode(Opc, dl, ShVT, SrcOp,
5385 DAG.getConstant(NumBits,
5386 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5390 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5392 // Check if the scalar load can be widened into a vector load. And if
5393 // the address is "base + cst" see if the cst can be "absorbed" into
5394 // the shuffle mask.
5395 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5396 SDValue Ptr = LD->getBasePtr();
5397 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5399 EVT PVT = LD->getValueType(0);
5400 if (PVT != MVT::i32 && PVT != MVT::f32)
5405 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5406 FI = FINode->getIndex();
5408 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5409 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5410 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5411 Offset = Ptr.getConstantOperandVal(1);
5412 Ptr = Ptr.getOperand(0);
5417 // FIXME: 256-bit vector instructions don't require a strict alignment,
5418 // improve this code to support it better.
5419 unsigned RequiredAlign = VT.getSizeInBits()/8;
5420 SDValue Chain = LD->getChain();
5421 // Make sure the stack object alignment is at least 16 or 32.
5422 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5423 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5424 if (MFI->isFixedObjectIndex(FI)) {
5425 // Can't change the alignment. FIXME: It's possible to compute
5426 // the exact stack offset and reference FI + adjust offset instead.
5427 // If someone *really* cares about this. That's the way to implement it.
5430 MFI->setObjectAlignment(FI, RequiredAlign);
5434 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5435 // Ptr + (Offset & ~15).
5438 if ((Offset % RequiredAlign) & 3)
5440 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5442 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5443 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5445 int EltNo = (Offset - StartOffset) >> 2;
5446 unsigned NumElems = VT.getVectorNumElements();
5448 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5449 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5450 LD->getPointerInfo().getWithOffset(StartOffset),
5451 false, false, false, 0);
5453 SmallVector<int, 8> Mask;
5454 for (unsigned i = 0; i != NumElems; ++i)
5455 Mask.push_back(EltNo);
5457 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5463 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5464 /// vector of type 'VT', see if the elements can be replaced by a single large
5465 /// load which has the same value as a build_vector whose operands are 'elts'.
5467 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5469 /// FIXME: we'd also like to handle the case where the last elements are zero
5470 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5471 /// There's even a handy isZeroNode for that purpose.
5472 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5473 SDLoc &DL, SelectionDAG &DAG,
5474 bool isAfterLegalize) {
5475 EVT EltVT = VT.getVectorElementType();
5476 unsigned NumElems = Elts.size();
5478 LoadSDNode *LDBase = NULL;
5479 unsigned LastLoadedElt = -1U;
5481 // For each element in the initializer, see if we've found a load or an undef.
5482 // If we don't find an initial load element, or later load elements are
5483 // non-consecutive, bail out.
5484 for (unsigned i = 0; i < NumElems; ++i) {
5485 SDValue Elt = Elts[i];
5487 if (!Elt.getNode() ||
5488 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5491 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5493 LDBase = cast<LoadSDNode>(Elt.getNode());
5497 if (Elt.getOpcode() == ISD::UNDEF)
5500 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5501 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5506 // If we have found an entire vector of loads and undefs, then return a large
5507 // load of the entire vector width starting at the base pointer. If we found
5508 // consecutive loads for the low half, generate a vzext_load node.
5509 if (LastLoadedElt == NumElems - 1) {
5511 if (isAfterLegalize &&
5512 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5515 SDValue NewLd = SDValue();
5517 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5518 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5519 LDBase->getPointerInfo(),
5520 LDBase->isVolatile(), LDBase->isNonTemporal(),
5521 LDBase->isInvariant(), 0);
5522 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5523 LDBase->getPointerInfo(),
5524 LDBase->isVolatile(), LDBase->isNonTemporal(),
5525 LDBase->isInvariant(), LDBase->getAlignment());
5527 if (LDBase->hasAnyUseOfValue(1)) {
5528 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5530 SDValue(NewLd.getNode(), 1));
5531 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5532 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5533 SDValue(NewLd.getNode(), 1));
5538 if (NumElems == 4 && LastLoadedElt == 1 &&
5539 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5540 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5541 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5543 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5544 array_lengthof(Ops), MVT::i64,
5545 LDBase->getPointerInfo(),
5546 LDBase->getAlignment(),
5547 false/*isVolatile*/, true/*ReadMem*/,
5550 // Make sure the newly-created LOAD is in the same position as LDBase in
5551 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5552 // update uses of LDBase's output chain to use the TokenFactor.
5553 if (LDBase->hasAnyUseOfValue(1)) {
5554 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5555 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5556 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5557 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5558 SDValue(ResNode.getNode(), 1));
5561 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5566 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5567 /// to generate a splat value for the following cases:
5568 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5569 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5570 /// a scalar load, or a constant.
5571 /// The VBROADCAST node is returned when a pattern is found,
5572 /// or SDValue() otherwise.
5573 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5574 SelectionDAG &DAG) {
5575 if (!Subtarget->hasFp256())
5578 MVT VT = Op.getSimpleValueType();
5581 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5582 "Unsupported vector type for broadcast.");
5587 switch (Op.getOpcode()) {
5589 // Unknown pattern found.
5592 case ISD::BUILD_VECTOR: {
5593 // The BUILD_VECTOR node must be a splat.
5594 if (!isSplatVector(Op.getNode()))
5597 Ld = Op.getOperand(0);
5598 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5599 Ld.getOpcode() == ISD::ConstantFP);
5601 // The suspected load node has several users. Make sure that all
5602 // of its users are from the BUILD_VECTOR node.
5603 // Constants may have multiple users.
5604 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5609 case ISD::VECTOR_SHUFFLE: {
5610 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5612 // Shuffles must have a splat mask where the first element is
5614 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5617 SDValue Sc = Op.getOperand(0);
5618 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5619 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5621 if (!Subtarget->hasInt256())
5624 // Use the register form of the broadcast instruction available on AVX2.
5625 if (VT.getSizeInBits() >= 256)
5626 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5627 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5630 Ld = Sc.getOperand(0);
5631 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5632 Ld.getOpcode() == ISD::ConstantFP);
5634 // The scalar_to_vector node and the suspected
5635 // load node must have exactly one user.
5636 // Constants may have multiple users.
5638 // AVX-512 has register version of the broadcast
5639 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5640 Ld.getValueType().getSizeInBits() >= 32;
5641 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5648 bool IsGE256 = (VT.getSizeInBits() >= 256);
5650 // Handle the broadcasting a single constant scalar from the constant pool
5651 // into a vector. On Sandybridge it is still better to load a constant vector
5652 // from the constant pool and not to broadcast it from a scalar.
5653 if (ConstSplatVal && Subtarget->hasInt256()) {
5654 EVT CVT = Ld.getValueType();
5655 assert(!CVT.isVector() && "Must not broadcast a vector type");
5656 unsigned ScalarSize = CVT.getSizeInBits();
5658 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5659 const Constant *C = 0;
5660 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5661 C = CI->getConstantIntValue();
5662 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5663 C = CF->getConstantFPValue();
5665 assert(C && "Invalid constant type");
5667 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5668 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5669 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5670 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5671 MachinePointerInfo::getConstantPool(),
5672 false, false, false, Alignment);
5674 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5678 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5679 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5681 // Handle AVX2 in-register broadcasts.
5682 if (!IsLoad && Subtarget->hasInt256() &&
5683 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5684 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5686 // The scalar source must be a normal load.
5690 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5691 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5693 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5694 // double since there is no vbroadcastsd xmm
5695 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5696 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5697 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5700 // Unsupported broadcast.
5704 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5705 MVT VT = Op.getSimpleValueType();
5707 // Skip if insert_vec_elt is not supported.
5708 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5709 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5713 unsigned NumElems = Op.getNumOperands();
5717 SmallVector<unsigned, 4> InsertIndices;
5718 SmallVector<int, 8> Mask(NumElems, -1);
5720 for (unsigned i = 0; i != NumElems; ++i) {
5721 unsigned Opc = Op.getOperand(i).getOpcode();
5723 if (Opc == ISD::UNDEF)
5726 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5727 // Quit if more than 1 elements need inserting.
5728 if (InsertIndices.size() > 1)
5731 InsertIndices.push_back(i);
5735 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5736 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5738 // Quit if extracted from vector of different type.
5739 if (ExtractedFromVec.getValueType() != VT)
5742 // Quit if non-constant index.
5743 if (!isa<ConstantSDNode>(ExtIdx))
5746 if (VecIn1.getNode() == 0)
5747 VecIn1 = ExtractedFromVec;
5748 else if (VecIn1 != ExtractedFromVec) {
5749 if (VecIn2.getNode() == 0)
5750 VecIn2 = ExtractedFromVec;
5751 else if (VecIn2 != ExtractedFromVec)
5752 // Quit if more than 2 vectors to shuffle
5756 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5758 if (ExtractedFromVec == VecIn1)
5760 else if (ExtractedFromVec == VecIn2)
5761 Mask[i] = Idx + NumElems;
5764 if (VecIn1.getNode() == 0)
5767 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5768 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5769 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5770 unsigned Idx = InsertIndices[i];
5771 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5772 DAG.getIntPtrConstant(Idx));
5778 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5780 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5782 MVT VT = Op.getSimpleValueType();
5783 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5784 "Unexpected type in LowerBUILD_VECTORvXi1!");
5787 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5788 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5789 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5790 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5791 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5792 Ops, VT.getVectorNumElements());
5795 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5796 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5797 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5798 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5799 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5800 Ops, VT.getVectorNumElements());
5803 bool AllContants = true;
5804 uint64_t Immediate = 0;
5805 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5806 SDValue In = Op.getOperand(idx);
5807 if (In.getOpcode() == ISD::UNDEF)
5809 if (!isa<ConstantSDNode>(In)) {
5810 AllContants = false;
5813 if (cast<ConstantSDNode>(In)->getZExtValue())
5814 Immediate |= (1ULL << idx);
5818 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5819 DAG.getConstant(Immediate, MVT::i16));
5820 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5821 DAG.getIntPtrConstant(0));
5824 // Splat vector (with undefs)
5825 SDValue In = Op.getOperand(0);
5826 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5827 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5828 llvm_unreachable("Unsupported predicate operation");
5831 SDValue EFLAGS, X86CC;
5832 if (In.getOpcode() == ISD::SETCC) {
5833 SDValue Op0 = In.getOperand(0);
5834 SDValue Op1 = In.getOperand(1);
5835 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5836 bool isFP = Op1.getValueType().isFloatingPoint();
5837 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5839 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5841 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5842 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5843 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5844 } else if (In.getOpcode() == X86ISD::SETCC) {
5845 X86CC = In.getOperand(0);
5846 EFLAGS = In.getOperand(1);
5855 // res = allOnes ### CMOVNE -1, %res
5858 MVT InVT = In.getSimpleValueType();
5859 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5860 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5861 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5864 if (VT == MVT::v16i1) {
5865 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5866 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5867 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5868 Cst0, Cst1, X86CC, EFLAGS);
5869 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5872 if (VT == MVT::v8i1) {
5873 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5874 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5875 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5876 Cst0, Cst1, X86CC, EFLAGS);
5877 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5878 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5880 llvm_unreachable("Unsupported predicate operation");
5884 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5887 MVT VT = Op.getSimpleValueType();
5888 MVT ExtVT = VT.getVectorElementType();
5889 unsigned NumElems = Op.getNumOperands();
5891 // Generate vectors for predicate vectors.
5892 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5893 return LowerBUILD_VECTORvXi1(Op, DAG);
5895 // Vectors containing all zeros can be matched by pxor and xorps later
5896 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5897 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5898 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5899 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5902 return getZeroVector(VT, Subtarget, DAG, dl);
5905 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5906 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5907 // vpcmpeqd on 256-bit vectors.
5908 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5909 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5912 if (!VT.is512BitVector())
5913 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5916 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5917 if (Broadcast.getNode())
5920 unsigned EVTBits = ExtVT.getSizeInBits();
5922 unsigned NumZero = 0;
5923 unsigned NumNonZero = 0;
5924 unsigned NonZeros = 0;
5925 bool IsAllConstants = true;
5926 SmallSet<SDValue, 8> Values;
5927 for (unsigned i = 0; i < NumElems; ++i) {
5928 SDValue Elt = Op.getOperand(i);
5929 if (Elt.getOpcode() == ISD::UNDEF)
5932 if (Elt.getOpcode() != ISD::Constant &&
5933 Elt.getOpcode() != ISD::ConstantFP)
5934 IsAllConstants = false;
5935 if (X86::isZeroNode(Elt))
5938 NonZeros |= (1 << i);
5943 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5944 if (NumNonZero == 0)
5945 return DAG.getUNDEF(VT);
5947 // Special case for single non-zero, non-undef, element.
5948 if (NumNonZero == 1) {
5949 unsigned Idx = countTrailingZeros(NonZeros);
5950 SDValue Item = Op.getOperand(Idx);
5952 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5953 // the value are obviously zero, truncate the value to i32 and do the
5954 // insertion that way. Only do this if the value is non-constant or if the
5955 // value is a constant being inserted into element 0. It is cheaper to do
5956 // a constant pool load than it is to do a movd + shuffle.
5957 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5958 (!IsAllConstants || Idx == 0)) {
5959 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5961 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5962 EVT VecVT = MVT::v4i32;
5963 unsigned VecElts = 4;
5965 // Truncate the value (which may itself be a constant) to i32, and
5966 // convert it to a vector with movd (S2V+shuffle to zero extend).
5967 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5968 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5969 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5971 // Now we have our 32-bit value zero extended in the low element of
5972 // a vector. If Idx != 0, swizzle it into place.
5974 SmallVector<int, 4> Mask;
5975 Mask.push_back(Idx);
5976 for (unsigned i = 1; i != VecElts; ++i)
5978 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5981 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5985 // If we have a constant or non-constant insertion into the low element of
5986 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5987 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5988 // depending on what the source datatype is.
5991 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5993 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5994 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5995 if (VT.is256BitVector() || VT.is512BitVector()) {
5996 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5997 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5998 Item, DAG.getIntPtrConstant(0));
6000 assert(VT.is128BitVector() && "Expected an SSE value type!");
6001 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6002 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6003 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6006 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6007 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6008 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6009 if (VT.is256BitVector()) {
6010 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6011 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6013 assert(VT.is128BitVector() && "Expected an SSE value type!");
6014 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6016 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6020 // Is it a vector logical left shift?
6021 if (NumElems == 2 && Idx == 1 &&
6022 X86::isZeroNode(Op.getOperand(0)) &&
6023 !X86::isZeroNode(Op.getOperand(1))) {
6024 unsigned NumBits = VT.getSizeInBits();
6025 return getVShift(true, VT,
6026 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6027 VT, Op.getOperand(1)),
6028 NumBits/2, DAG, *this, dl);
6031 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6034 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6035 // is a non-constant being inserted into an element other than the low one,
6036 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6037 // movd/movss) to move this into the low element, then shuffle it into
6039 if (EVTBits == 32) {
6040 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6042 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6043 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6044 SmallVector<int, 8> MaskVec;
6045 for (unsigned i = 0; i != NumElems; ++i)
6046 MaskVec.push_back(i == Idx ? 0 : 1);
6047 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6051 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6052 if (Values.size() == 1) {
6053 if (EVTBits == 32) {
6054 // Instead of a shuffle like this:
6055 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6056 // Check if it's possible to issue this instead.
6057 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6058 unsigned Idx = countTrailingZeros(NonZeros);
6059 SDValue Item = Op.getOperand(Idx);
6060 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6061 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6066 // A vector full of immediates; various special cases are already
6067 // handled, so this is best done with a single constant-pool load.
6071 // For AVX-length vectors, build the individual 128-bit pieces and use
6072 // shuffles to put them in place.
6073 if (VT.is256BitVector() || VT.is512BitVector()) {
6074 SmallVector<SDValue, 64> V;
6075 for (unsigned i = 0; i != NumElems; ++i)
6076 V.push_back(Op.getOperand(i));
6078 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6080 // Build both the lower and upper subvector.
6081 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6082 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6085 // Recreate the wider vector with the lower and upper part.
6086 if (VT.is256BitVector())
6087 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6088 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6091 // Let legalizer expand 2-wide build_vectors.
6092 if (EVTBits == 64) {
6093 if (NumNonZero == 1) {
6094 // One half is zero or undef.
6095 unsigned Idx = countTrailingZeros(NonZeros);
6096 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6097 Op.getOperand(Idx));
6098 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6103 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6104 if (EVTBits == 8 && NumElems == 16) {
6105 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6107 if (V.getNode()) return V;
6110 if (EVTBits == 16 && NumElems == 8) {
6111 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6113 if (V.getNode()) return V;
6116 // If element VT is == 32 bits, turn it into a number of shuffles.
6117 SmallVector<SDValue, 8> V(NumElems);
6118 if (NumElems == 4 && NumZero > 0) {
6119 for (unsigned i = 0; i < 4; ++i) {
6120 bool isZero = !(NonZeros & (1 << i));
6122 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6124 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6127 for (unsigned i = 0; i < 2; ++i) {
6128 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6131 V[i] = V[i*2]; // Must be a zero vector.
6134 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6137 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6140 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6145 bool Reverse1 = (NonZeros & 0x3) == 2;
6146 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6150 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6151 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6153 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6156 if (Values.size() > 1 && VT.is128BitVector()) {
6157 // Check for a build vector of consecutive loads.
6158 for (unsigned i = 0; i < NumElems; ++i)
6159 V[i] = Op.getOperand(i);
6161 // Check for elements which are consecutive loads.
6162 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6166 // Check for a build vector from mostly shuffle plus few inserting.
6167 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6171 // For SSE 4.1, use insertps to put the high elements into the low element.
6172 if (getSubtarget()->hasSSE41()) {
6174 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6175 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6177 Result = DAG.getUNDEF(VT);
6179 for (unsigned i = 1; i < NumElems; ++i) {
6180 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6181 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6182 Op.getOperand(i), DAG.getIntPtrConstant(i));
6187 // Otherwise, expand into a number of unpckl*, start by extending each of
6188 // our (non-undef) elements to the full vector width with the element in the
6189 // bottom slot of the vector (which generates no code for SSE).
6190 for (unsigned i = 0; i < NumElems; ++i) {
6191 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6192 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6194 V[i] = DAG.getUNDEF(VT);
6197 // Next, we iteratively mix elements, e.g. for v4f32:
6198 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6199 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6200 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6201 unsigned EltStride = NumElems >> 1;
6202 while (EltStride != 0) {
6203 for (unsigned i = 0; i < EltStride; ++i) {
6204 // If V[i+EltStride] is undef and this is the first round of mixing,
6205 // then it is safe to just drop this shuffle: V[i] is already in the
6206 // right place, the one element (since it's the first round) being
6207 // inserted as undef can be dropped. This isn't safe for successive
6208 // rounds because they will permute elements within both vectors.
6209 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6210 EltStride == NumElems/2)
6213 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6222 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6223 // to create 256-bit vectors from two other 128-bit ones.
6224 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6226 MVT ResVT = Op.getSimpleValueType();
6228 assert((ResVT.is256BitVector() ||
6229 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6231 SDValue V1 = Op.getOperand(0);
6232 SDValue V2 = Op.getOperand(1);
6233 unsigned NumElems = ResVT.getVectorNumElements();
6234 if(ResVT.is256BitVector())
6235 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6237 if (Op.getNumOperands() == 4) {
6238 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6239 ResVT.getVectorNumElements()/2);
6240 SDValue V3 = Op.getOperand(2);
6241 SDValue V4 = Op.getOperand(3);
6242 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6243 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6245 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6248 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6249 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6250 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6251 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6252 Op.getNumOperands() == 4)));
6254 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6255 // from two other 128-bit ones.
6257 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6258 return LowerAVXCONCAT_VECTORS(Op, DAG);
6261 // Try to lower a shuffle node into a simple blend instruction.
6263 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6264 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6265 SDValue V1 = SVOp->getOperand(0);
6266 SDValue V2 = SVOp->getOperand(1);
6268 MVT VT = SVOp->getSimpleValueType(0);
6269 MVT EltVT = VT.getVectorElementType();
6270 unsigned NumElems = VT.getVectorNumElements();
6272 // There is no blend with immediate in AVX-512.
6273 if (VT.is512BitVector())
6276 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6278 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6281 // Check the mask for BLEND and build the value.
6282 unsigned MaskValue = 0;
6283 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6284 unsigned NumLanes = (NumElems-1)/8 + 1;
6285 unsigned NumElemsInLane = NumElems / NumLanes;
6287 // Blend for v16i16 should be symetric for the both lanes.
6288 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6290 int SndLaneEltIdx = (NumLanes == 2) ?
6291 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6292 int EltIdx = SVOp->getMaskElt(i);
6294 if ((EltIdx < 0 || EltIdx == (int)i) &&
6295 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6298 if (((unsigned)EltIdx == (i + NumElems)) &&
6299 (SndLaneEltIdx < 0 ||
6300 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6301 MaskValue |= (1<<i);
6306 // Convert i32 vectors to floating point if it is not AVX2.
6307 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6309 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6310 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6312 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6313 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6316 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6317 DAG.getConstant(MaskValue, MVT::i32));
6318 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6321 // v8i16 shuffles - Prefer shuffles in the following order:
6322 // 1. [all] pshuflw, pshufhw, optional move
6323 // 2. [ssse3] 1 x pshufb
6324 // 3. [ssse3] 2 x pshufb + 1 x por
6325 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6327 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6328 SelectionDAG &DAG) {
6329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6330 SDValue V1 = SVOp->getOperand(0);
6331 SDValue V2 = SVOp->getOperand(1);
6333 SmallVector<int, 8> MaskVals;
6335 // Determine if more than 1 of the words in each of the low and high quadwords
6336 // of the result come from the same quadword of one of the two inputs. Undef
6337 // mask values count as coming from any quadword, for better codegen.
6338 unsigned LoQuad[] = { 0, 0, 0, 0 };
6339 unsigned HiQuad[] = { 0, 0, 0, 0 };
6340 std::bitset<4> InputQuads;
6341 for (unsigned i = 0; i < 8; ++i) {
6342 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6343 int EltIdx = SVOp->getMaskElt(i);
6344 MaskVals.push_back(EltIdx);
6353 InputQuads.set(EltIdx / 4);
6356 int BestLoQuad = -1;
6357 unsigned MaxQuad = 1;
6358 for (unsigned i = 0; i < 4; ++i) {
6359 if (LoQuad[i] > MaxQuad) {
6361 MaxQuad = LoQuad[i];
6365 int BestHiQuad = -1;
6367 for (unsigned i = 0; i < 4; ++i) {
6368 if (HiQuad[i] > MaxQuad) {
6370 MaxQuad = HiQuad[i];
6374 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6375 // of the two input vectors, shuffle them into one input vector so only a
6376 // single pshufb instruction is necessary. If There are more than 2 input
6377 // quads, disable the next transformation since it does not help SSSE3.
6378 bool V1Used = InputQuads[0] || InputQuads[1];
6379 bool V2Used = InputQuads[2] || InputQuads[3];
6380 if (Subtarget->hasSSSE3()) {
6381 if (InputQuads.count() == 2 && V1Used && V2Used) {
6382 BestLoQuad = InputQuads[0] ? 0 : 1;
6383 BestHiQuad = InputQuads[2] ? 2 : 3;
6385 if (InputQuads.count() > 2) {
6391 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6392 // the shuffle mask. If a quad is scored as -1, that means that it contains
6393 // words from all 4 input quadwords.
6395 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6397 BestLoQuad < 0 ? 0 : BestLoQuad,
6398 BestHiQuad < 0 ? 1 : BestHiQuad
6400 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6401 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6402 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6403 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6405 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6406 // source words for the shuffle, to aid later transformations.
6407 bool AllWordsInNewV = true;
6408 bool InOrder[2] = { true, true };
6409 for (unsigned i = 0; i != 8; ++i) {
6410 int idx = MaskVals[i];
6412 InOrder[i/4] = false;
6413 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6415 AllWordsInNewV = false;
6419 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6420 if (AllWordsInNewV) {
6421 for (int i = 0; i != 8; ++i) {
6422 int idx = MaskVals[i];
6425 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6426 if ((idx != i) && idx < 4)
6428 if ((idx != i) && idx > 3)
6437 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6438 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6439 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6440 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6441 unsigned TargetMask = 0;
6442 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6443 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6444 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6445 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6446 getShufflePSHUFLWImmediate(SVOp);
6447 V1 = NewV.getOperand(0);
6448 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6452 // Promote splats to a larger type which usually leads to more efficient code.
6453 // FIXME: Is this true if pshufb is available?
6454 if (SVOp->isSplat())
6455 return PromoteSplat(SVOp, DAG);
6457 // If we have SSSE3, and all words of the result are from 1 input vector,
6458 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6459 // is present, fall back to case 4.
6460 if (Subtarget->hasSSSE3()) {
6461 SmallVector<SDValue,16> pshufbMask;
6463 // If we have elements from both input vectors, set the high bit of the
6464 // shuffle mask element to zero out elements that come from V2 in the V1
6465 // mask, and elements that come from V1 in the V2 mask, so that the two
6466 // results can be OR'd together.
6467 bool TwoInputs = V1Used && V2Used;
6468 for (unsigned i = 0; i != 8; ++i) {
6469 int EltIdx = MaskVals[i] * 2;
6470 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6471 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6472 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6473 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6475 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6476 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6477 DAG.getNode(ISD::BUILD_VECTOR, dl,
6478 MVT::v16i8, &pshufbMask[0], 16));
6480 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6482 // Calculate the shuffle mask for the second input, shuffle it, and
6483 // OR it with the first shuffled input.
6485 for (unsigned i = 0; i != 8; ++i) {
6486 int EltIdx = MaskVals[i] * 2;
6487 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6488 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6489 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6490 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6492 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6493 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6494 DAG.getNode(ISD::BUILD_VECTOR, dl,
6495 MVT::v16i8, &pshufbMask[0], 16));
6496 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6497 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6500 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6501 // and update MaskVals with new element order.
6502 std::bitset<8> InOrder;
6503 if (BestLoQuad >= 0) {
6504 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6505 for (int i = 0; i != 4; ++i) {
6506 int idx = MaskVals[i];
6509 } else if ((idx / 4) == BestLoQuad) {
6514 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6517 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6518 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6519 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6521 getShufflePSHUFLWImmediate(SVOp), DAG);
6525 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6526 // and update MaskVals with the new element order.
6527 if (BestHiQuad >= 0) {
6528 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6529 for (unsigned i = 4; i != 8; ++i) {
6530 int idx = MaskVals[i];
6533 } else if ((idx / 4) == BestHiQuad) {
6534 MaskV[i] = (idx & 3) + 4;
6538 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6541 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6542 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6543 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6545 getShufflePSHUFHWImmediate(SVOp), DAG);
6549 // In case BestHi & BestLo were both -1, which means each quadword has a word
6550 // from each of the four input quadwords, calculate the InOrder bitvector now
6551 // before falling through to the insert/extract cleanup.
6552 if (BestLoQuad == -1 && BestHiQuad == -1) {
6554 for (int i = 0; i != 8; ++i)
6555 if (MaskVals[i] < 0 || MaskVals[i] == i)
6559 // The other elements are put in the right place using pextrw and pinsrw.
6560 for (unsigned i = 0; i != 8; ++i) {
6563 int EltIdx = MaskVals[i];
6566 SDValue ExtOp = (EltIdx < 8) ?
6567 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6568 DAG.getIntPtrConstant(EltIdx)) :
6569 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6570 DAG.getIntPtrConstant(EltIdx - 8));
6571 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6572 DAG.getIntPtrConstant(i));
6577 // v16i8 shuffles - Prefer shuffles in the following order:
6578 // 1. [ssse3] 1 x pshufb
6579 // 2. [ssse3] 2 x pshufb + 1 x por
6580 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6581 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6582 const X86Subtarget* Subtarget,
6583 SelectionDAG &DAG) {
6584 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6585 SDValue V1 = SVOp->getOperand(0);
6586 SDValue V2 = SVOp->getOperand(1);
6588 ArrayRef<int> MaskVals = SVOp->getMask();
6590 // Promote splats to a larger type which usually leads to more efficient code.
6591 // FIXME: Is this true if pshufb is available?
6592 if (SVOp->isSplat())
6593 return PromoteSplat(SVOp, DAG);
6595 // If we have SSSE3, case 1 is generated when all result bytes come from
6596 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6597 // present, fall back to case 3.
6599 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6600 if (Subtarget->hasSSSE3()) {
6601 SmallVector<SDValue,16> pshufbMask;
6603 // If all result elements are from one input vector, then only translate
6604 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6606 // Otherwise, we have elements from both input vectors, and must zero out
6607 // elements that come from V2 in the first mask, and V1 in the second mask
6608 // so that we can OR them together.
6609 for (unsigned i = 0; i != 16; ++i) {
6610 int EltIdx = MaskVals[i];
6611 if (EltIdx < 0 || EltIdx >= 16)
6613 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6615 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6616 DAG.getNode(ISD::BUILD_VECTOR, dl,
6617 MVT::v16i8, &pshufbMask[0], 16));
6619 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6620 // the 2nd operand if it's undefined or zero.
6621 if (V2.getOpcode() == ISD::UNDEF ||
6622 ISD::isBuildVectorAllZeros(V2.getNode()))
6625 // Calculate the shuffle mask for the second input, shuffle it, and
6626 // OR it with the first shuffled input.
6628 for (unsigned i = 0; i != 16; ++i) {
6629 int EltIdx = MaskVals[i];
6630 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6631 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6633 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6634 DAG.getNode(ISD::BUILD_VECTOR, dl,
6635 MVT::v16i8, &pshufbMask[0], 16));
6636 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6639 // No SSSE3 - Calculate in place words and then fix all out of place words
6640 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6641 // the 16 different words that comprise the two doublequadword input vectors.
6642 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6643 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6645 for (int i = 0; i != 8; ++i) {
6646 int Elt0 = MaskVals[i*2];
6647 int Elt1 = MaskVals[i*2+1];
6649 // This word of the result is all undef, skip it.
6650 if (Elt0 < 0 && Elt1 < 0)
6653 // This word of the result is already in the correct place, skip it.
6654 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6657 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6658 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6661 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6662 // using a single extract together, load it and store it.
6663 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6664 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6665 DAG.getIntPtrConstant(Elt1 / 2));
6666 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6667 DAG.getIntPtrConstant(i));
6671 // If Elt1 is defined, extract it from the appropriate source. If the
6672 // source byte is not also odd, shift the extracted word left 8 bits
6673 // otherwise clear the bottom 8 bits if we need to do an or.
6675 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6676 DAG.getIntPtrConstant(Elt1 / 2));
6677 if ((Elt1 & 1) == 0)
6678 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6680 TLI.getShiftAmountTy(InsElt.getValueType())));
6682 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6683 DAG.getConstant(0xFF00, MVT::i16));
6685 // If Elt0 is defined, extract it from the appropriate source. If the
6686 // source byte is not also even, shift the extracted word right 8 bits. If
6687 // Elt1 was also defined, OR the extracted values together before
6688 // inserting them in the result.
6690 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6691 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6692 if ((Elt0 & 1) != 0)
6693 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6695 TLI.getShiftAmountTy(InsElt0.getValueType())));
6697 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6698 DAG.getConstant(0x00FF, MVT::i16));
6699 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6702 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6703 DAG.getIntPtrConstant(i));
6705 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6708 // v32i8 shuffles - Translate to VPSHUFB if possible.
6710 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6711 const X86Subtarget *Subtarget,
6712 SelectionDAG &DAG) {
6713 MVT VT = SVOp->getSimpleValueType(0);
6714 SDValue V1 = SVOp->getOperand(0);
6715 SDValue V2 = SVOp->getOperand(1);
6717 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6719 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6720 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6721 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6723 // VPSHUFB may be generated if
6724 // (1) one of input vector is undefined or zeroinitializer.
6725 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6726 // And (2) the mask indexes don't cross the 128-bit lane.
6727 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6728 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6731 if (V1IsAllZero && !V2IsAllZero) {
6732 CommuteVectorShuffleMask(MaskVals, 32);
6735 SmallVector<SDValue, 32> pshufbMask;
6736 for (unsigned i = 0; i != 32; i++) {
6737 int EltIdx = MaskVals[i];
6738 if (EltIdx < 0 || EltIdx >= 32)
6741 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6742 // Cross lane is not allowed.
6746 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6748 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6749 DAG.getNode(ISD::BUILD_VECTOR, dl,
6750 MVT::v32i8, &pshufbMask[0], 32));
6753 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6754 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6755 /// done when every pair / quad of shuffle mask elements point to elements in
6756 /// the right sequence. e.g.
6757 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6759 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6760 SelectionDAG &DAG) {
6761 MVT VT = SVOp->getSimpleValueType(0);
6763 unsigned NumElems = VT.getVectorNumElements();
6766 switch (VT.SimpleTy) {
6767 default: llvm_unreachable("Unexpected!");
6768 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6769 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6770 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6771 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6772 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6773 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6776 SmallVector<int, 8> MaskVec;
6777 for (unsigned i = 0; i != NumElems; i += Scale) {
6779 for (unsigned j = 0; j != Scale; ++j) {
6780 int EltIdx = SVOp->getMaskElt(i+j);
6784 StartIdx = (EltIdx / Scale);
6785 if (EltIdx != (int)(StartIdx*Scale + j))
6788 MaskVec.push_back(StartIdx);
6791 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6792 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6793 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6796 /// getVZextMovL - Return a zero-extending vector move low node.
6798 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6799 SDValue SrcOp, SelectionDAG &DAG,
6800 const X86Subtarget *Subtarget, SDLoc dl) {
6801 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6802 LoadSDNode *LD = NULL;
6803 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6804 LD = dyn_cast<LoadSDNode>(SrcOp);
6806 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6808 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6809 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6810 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6811 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6812 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6814 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6815 return DAG.getNode(ISD::BITCAST, dl, VT,
6816 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6817 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6825 return DAG.getNode(ISD::BITCAST, dl, VT,
6826 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6827 DAG.getNode(ISD::BITCAST, dl,
6831 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6832 /// which could not be matched by any known target speficic shuffle
6834 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6836 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6837 if (NewOp.getNode())
6840 MVT VT = SVOp->getSimpleValueType(0);
6842 unsigned NumElems = VT.getVectorNumElements();
6843 unsigned NumLaneElems = NumElems / 2;
6846 MVT EltVT = VT.getVectorElementType();
6847 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6850 SmallVector<int, 16> Mask;
6851 for (unsigned l = 0; l < 2; ++l) {
6852 // Build a shuffle mask for the output, discovering on the fly which
6853 // input vectors to use as shuffle operands (recorded in InputUsed).
6854 // If building a suitable shuffle vector proves too hard, then bail
6855 // out with UseBuildVector set.
6856 bool UseBuildVector = false;
6857 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6858 unsigned LaneStart = l * NumLaneElems;
6859 for (unsigned i = 0; i != NumLaneElems; ++i) {
6860 // The mask element. This indexes into the input.
6861 int Idx = SVOp->getMaskElt(i+LaneStart);
6863 // the mask element does not index into any input vector.
6868 // The input vector this mask element indexes into.
6869 int Input = Idx / NumLaneElems;
6871 // Turn the index into an offset from the start of the input vector.
6872 Idx -= Input * NumLaneElems;
6874 // Find or create a shuffle vector operand to hold this input.
6876 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6877 if (InputUsed[OpNo] == Input)
6878 // This input vector is already an operand.
6880 if (InputUsed[OpNo] < 0) {
6881 // Create a new operand for this input vector.
6882 InputUsed[OpNo] = Input;
6887 if (OpNo >= array_lengthof(InputUsed)) {
6888 // More than two input vectors used! Give up on trying to create a
6889 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6890 UseBuildVector = true;
6894 // Add the mask index for the new shuffle vector.
6895 Mask.push_back(Idx + OpNo * NumLaneElems);
6898 if (UseBuildVector) {
6899 SmallVector<SDValue, 16> SVOps;
6900 for (unsigned i = 0; i != NumLaneElems; ++i) {
6901 // The mask element. This indexes into the input.
6902 int Idx = SVOp->getMaskElt(i+LaneStart);
6904 SVOps.push_back(DAG.getUNDEF(EltVT));
6908 // The input vector this mask element indexes into.
6909 int Input = Idx / NumElems;
6911 // Turn the index into an offset from the start of the input vector.
6912 Idx -= Input * NumElems;
6914 // Extract the vector element by hand.
6915 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6916 SVOp->getOperand(Input),
6917 DAG.getIntPtrConstant(Idx)));
6920 // Construct the output using a BUILD_VECTOR.
6921 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6923 } else if (InputUsed[0] < 0) {
6924 // No input vectors were used! The result is undefined.
6925 Output[l] = DAG.getUNDEF(NVT);
6927 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6928 (InputUsed[0] % 2) * NumLaneElems,
6930 // If only one input was used, use an undefined vector for the other.
6931 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6932 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6933 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6934 // At least one input vector was used. Create a new shuffle vector.
6935 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6941 // Concatenate the result back
6942 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6945 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6946 /// 4 elements, and match them with several different shuffle types.
6948 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6949 SDValue V1 = SVOp->getOperand(0);
6950 SDValue V2 = SVOp->getOperand(1);
6952 MVT VT = SVOp->getSimpleValueType(0);
6954 assert(VT.is128BitVector() && "Unsupported vector size");
6956 std::pair<int, int> Locs[4];
6957 int Mask1[] = { -1, -1, -1, -1 };
6958 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6962 for (unsigned i = 0; i != 4; ++i) {
6963 int Idx = PermMask[i];
6965 Locs[i] = std::make_pair(-1, -1);
6967 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6969 Locs[i] = std::make_pair(0, NumLo);
6973 Locs[i] = std::make_pair(1, NumHi);
6975 Mask1[2+NumHi] = Idx;
6981 if (NumLo <= 2 && NumHi <= 2) {
6982 // If no more than two elements come from either vector. This can be
6983 // implemented with two shuffles. First shuffle gather the elements.
6984 // The second shuffle, which takes the first shuffle as both of its
6985 // vector operands, put the elements into the right order.
6986 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6988 int Mask2[] = { -1, -1, -1, -1 };
6990 for (unsigned i = 0; i != 4; ++i)
6991 if (Locs[i].first != -1) {
6992 unsigned Idx = (i < 2) ? 0 : 4;
6993 Idx += Locs[i].first * 2 + Locs[i].second;
6997 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
7000 if (NumLo == 3 || NumHi == 3) {
7001 // Otherwise, we must have three elements from one vector, call it X, and
7002 // one element from the other, call it Y. First, use a shufps to build an
7003 // intermediate vector with the one element from Y and the element from X
7004 // that will be in the same half in the final destination (the indexes don't
7005 // matter). Then, use a shufps to build the final vector, taking the half
7006 // containing the element from Y from the intermediate, and the other half
7009 // Normalize it so the 3 elements come from V1.
7010 CommuteVectorShuffleMask(PermMask, 4);
7014 // Find the element from V2.
7016 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
7017 int Val = PermMask[HiIndex];
7024 Mask1[0] = PermMask[HiIndex];
7026 Mask1[2] = PermMask[HiIndex^1];
7028 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7031 Mask1[0] = PermMask[0];
7032 Mask1[1] = PermMask[1];
7033 Mask1[2] = HiIndex & 1 ? 6 : 4;
7034 Mask1[3] = HiIndex & 1 ? 4 : 6;
7035 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7038 Mask1[0] = HiIndex & 1 ? 2 : 0;
7039 Mask1[1] = HiIndex & 1 ? 0 : 2;
7040 Mask1[2] = PermMask[2];
7041 Mask1[3] = PermMask[3];
7046 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7049 // Break it into (shuffle shuffle_hi, shuffle_lo).
7050 int LoMask[] = { -1, -1, -1, -1 };
7051 int HiMask[] = { -1, -1, -1, -1 };
7053 int *MaskPtr = LoMask;
7054 unsigned MaskIdx = 0;
7057 for (unsigned i = 0; i != 4; ++i) {
7064 int Idx = PermMask[i];
7066 Locs[i] = std::make_pair(-1, -1);
7067 } else if (Idx < 4) {
7068 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7069 MaskPtr[LoIdx] = Idx;
7072 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7073 MaskPtr[HiIdx] = Idx;
7078 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7079 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7080 int MaskOps[] = { -1, -1, -1, -1 };
7081 for (unsigned i = 0; i != 4; ++i)
7082 if (Locs[i].first != -1)
7083 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7084 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7087 static bool MayFoldVectorLoad(SDValue V) {
7088 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7089 V = V.getOperand(0);
7091 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7092 V = V.getOperand(0);
7093 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7094 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7095 // BUILD_VECTOR (load), undef
7096 V = V.getOperand(0);
7098 return MayFoldLoad(V);
7102 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7103 MVT VT = Op.getSimpleValueType();
7105 // Canonizalize to v2f64.
7106 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7107 return DAG.getNode(ISD::BITCAST, dl, VT,
7108 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7113 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 MVT VT = Op.getSimpleValueType();
7119 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7121 if (HasSSE2 && VT == MVT::v2f64)
7122 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7124 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7125 return DAG.getNode(ISD::BITCAST, dl, VT,
7126 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7127 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7128 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7132 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7133 SDValue V1 = Op.getOperand(0);
7134 SDValue V2 = Op.getOperand(1);
7135 MVT VT = Op.getSimpleValueType();
7137 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7138 "unsupported shuffle type");
7140 if (V2.getOpcode() == ISD::UNDEF)
7144 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7148 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7149 SDValue V1 = Op.getOperand(0);
7150 SDValue V2 = Op.getOperand(1);
7151 MVT VT = Op.getSimpleValueType();
7152 unsigned NumElems = VT.getVectorNumElements();
7154 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7155 // operand of these instructions is only memory, so check if there's a
7156 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7158 bool CanFoldLoad = false;
7160 // Trivial case, when V2 comes from a load.
7161 if (MayFoldVectorLoad(V2))
7164 // When V1 is a load, it can be folded later into a store in isel, example:
7165 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7167 // (MOVLPSmr addr:$src1, VR128:$src2)
7168 // So, recognize this potential and also use MOVLPS or MOVLPD
7169 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7174 if (HasSSE2 && NumElems == 2)
7175 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7178 // If we don't care about the second element, proceed to use movss.
7179 if (SVOp->getMaskElt(1) != -1)
7180 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7183 // movl and movlp will both match v2i64, but v2i64 is never matched by
7184 // movl earlier because we make it strict to avoid messing with the movlp load
7185 // folding logic (see the code above getMOVLP call). Match it here then,
7186 // this is horrible, but will stay like this until we move all shuffle
7187 // matching to x86 specific nodes. Note that for the 1st condition all
7188 // types are matched with movsd.
7190 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7191 // as to remove this logic from here, as much as possible
7192 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7193 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7194 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7197 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7199 // Invert the operand order and use SHUFPS to match it.
7200 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7201 getShuffleSHUFImmediate(SVOp), DAG);
7204 // Reduce a vector shuffle to zext.
7205 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7206 SelectionDAG &DAG) {
7207 // PMOVZX is only available from SSE41.
7208 if (!Subtarget->hasSSE41())
7211 MVT VT = Op.getSimpleValueType();
7213 // Only AVX2 support 256-bit vector integer extending.
7214 if (!Subtarget->hasInt256() && VT.is256BitVector())
7217 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7219 SDValue V1 = Op.getOperand(0);
7220 SDValue V2 = Op.getOperand(1);
7221 unsigned NumElems = VT.getVectorNumElements();
7223 // Extending is an unary operation and the element type of the source vector
7224 // won't be equal to or larger than i64.
7225 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7226 VT.getVectorElementType() == MVT::i64)
7229 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7230 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7231 while ((1U << Shift) < NumElems) {
7232 if (SVOp->getMaskElt(1U << Shift) == 1)
7235 // The maximal ratio is 8, i.e. from i8 to i64.
7240 // Check the shuffle mask.
7241 unsigned Mask = (1U << Shift) - 1;
7242 for (unsigned i = 0; i != NumElems; ++i) {
7243 int EltIdx = SVOp->getMaskElt(i);
7244 if ((i & Mask) != 0 && EltIdx != -1)
7246 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7250 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7251 MVT NeVT = MVT::getIntegerVT(NBits);
7252 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7254 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7257 // Simplify the operand as it's prepared to be fed into shuffle.
7258 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7259 if (V1.getOpcode() == ISD::BITCAST &&
7260 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7261 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7262 V1.getOperand(0).getOperand(0)
7263 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7264 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7265 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7266 ConstantSDNode *CIdx =
7267 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7268 // If it's foldable, i.e. normal load with single use, we will let code
7269 // selection to fold it. Otherwise, we will short the conversion sequence.
7270 if (CIdx && CIdx->getZExtValue() == 0 &&
7271 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7272 MVT FullVT = V.getSimpleValueType();
7273 MVT V1VT = V1.getSimpleValueType();
7274 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7275 // The "ext_vec_elt" node is wider than the result node.
7276 // In this case we should extract subvector from V.
7277 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7278 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7279 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7280 FullVT.getVectorNumElements()/Ratio);
7281 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7282 DAG.getIntPtrConstant(0));
7284 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7288 return DAG.getNode(ISD::BITCAST, DL, VT,
7289 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7293 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7294 SelectionDAG &DAG) {
7295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7296 MVT VT = Op.getSimpleValueType();
7298 SDValue V1 = Op.getOperand(0);
7299 SDValue V2 = Op.getOperand(1);
7301 if (isZeroShuffle(SVOp))
7302 return getZeroVector(VT, Subtarget, DAG, dl);
7304 // Handle splat operations
7305 if (SVOp->isSplat()) {
7306 // Use vbroadcast whenever the splat comes from a foldable load
7307 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7308 if (Broadcast.getNode())
7312 // Check integer expanding shuffles.
7313 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7314 if (NewOp.getNode())
7317 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7319 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7320 VT == MVT::v16i16 || VT == MVT::v32i8) {
7321 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7322 if (NewOp.getNode())
7323 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7324 } else if ((VT == MVT::v4i32 ||
7325 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7326 // FIXME: Figure out a cleaner way to do this.
7327 // Try to make use of movq to zero out the top part.
7328 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7329 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7330 if (NewOp.getNode()) {
7331 MVT NewVT = NewOp.getSimpleValueType();
7332 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7333 NewVT, true, false))
7334 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7335 DAG, Subtarget, dl);
7337 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7338 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7339 if (NewOp.getNode()) {
7340 MVT NewVT = NewOp.getSimpleValueType();
7341 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7342 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7343 DAG, Subtarget, dl);
7351 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7352 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7353 SDValue V1 = Op.getOperand(0);
7354 SDValue V2 = Op.getOperand(1);
7355 MVT VT = Op.getSimpleValueType();
7357 unsigned NumElems = VT.getVectorNumElements();
7358 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7359 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7360 bool V1IsSplat = false;
7361 bool V2IsSplat = false;
7362 bool HasSSE2 = Subtarget->hasSSE2();
7363 bool HasFp256 = Subtarget->hasFp256();
7364 bool HasInt256 = Subtarget->hasInt256();
7365 MachineFunction &MF = DAG.getMachineFunction();
7366 bool OptForSize = MF.getFunction()->getAttributes().
7367 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7369 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7371 if (V1IsUndef && V2IsUndef)
7372 return DAG.getUNDEF(VT);
7374 // When we create a shuffle node we put the UNDEF node to second operand,
7375 // but in some cases the first operand may be transformed to UNDEF.
7376 // In this case we should just commute the node.
7378 return CommuteVectorShuffle(SVOp, DAG);
7380 // Vector shuffle lowering takes 3 steps:
7382 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7383 // narrowing and commutation of operands should be handled.
7384 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7386 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7387 // so the shuffle can be broken into other shuffles and the legalizer can
7388 // try the lowering again.
7390 // The general idea is that no vector_shuffle operation should be left to
7391 // be matched during isel, all of them must be converted to a target specific
7394 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7395 // narrowing and commutation of operands should be handled. The actual code
7396 // doesn't include all of those, work in progress...
7397 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7398 if (NewOp.getNode())
7401 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7403 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7404 // unpckh_undef). Only use pshufd if speed is more important than size.
7405 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7406 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7407 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7408 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7410 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7411 V2IsUndef && MayFoldVectorLoad(V1))
7412 return getMOVDDup(Op, dl, V1, DAG);
7414 if (isMOVHLPS_v_undef_Mask(M, VT))
7415 return getMOVHighToLow(Op, dl, DAG);
7417 // Use to match splats
7418 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7419 (VT == MVT::v2f64 || VT == MVT::v2i64))
7420 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7422 if (isPSHUFDMask(M, VT)) {
7423 // The actual implementation will match the mask in the if above and then
7424 // during isel it can match several different instructions, not only pshufd
7425 // as its name says, sad but true, emulate the behavior for now...
7426 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7427 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7429 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7431 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7432 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7434 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7435 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7438 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7442 if (isPALIGNRMask(M, VT, Subtarget))
7443 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7444 getShufflePALIGNRImmediate(SVOp),
7447 // Check if this can be converted into a logical shift.
7448 bool isLeft = false;
7451 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7452 if (isShift && ShVal.hasOneUse()) {
7453 // If the shifted value has multiple uses, it may be cheaper to use
7454 // v_set0 + movlhps or movhlps, etc.
7455 MVT EltVT = VT.getVectorElementType();
7456 ShAmt *= EltVT.getSizeInBits();
7457 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7460 if (isMOVLMask(M, VT)) {
7461 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7462 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7463 if (!isMOVLPMask(M, VT)) {
7464 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7465 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7467 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7468 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7472 // FIXME: fold these into legal mask.
7473 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7474 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7476 if (isMOVHLPSMask(M, VT))
7477 return getMOVHighToLow(Op, dl, DAG);
7479 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7480 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7482 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7483 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7485 if (isMOVLPMask(M, VT))
7486 return getMOVLP(Op, dl, DAG, HasSSE2);
7488 if (ShouldXformToMOVHLPS(M, VT) ||
7489 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7490 return CommuteVectorShuffle(SVOp, DAG);
7493 // No better options. Use a vshldq / vsrldq.
7494 MVT EltVT = VT.getVectorElementType();
7495 ShAmt *= EltVT.getSizeInBits();
7496 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7499 bool Commuted = false;
7500 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7501 // 1,1,1,1 -> v8i16 though.
7502 V1IsSplat = isSplatVector(V1.getNode());
7503 V2IsSplat = isSplatVector(V2.getNode());
7505 // Canonicalize the splat or undef, if present, to be on the RHS.
7506 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7507 CommuteVectorShuffleMask(M, NumElems);
7509 std::swap(V1IsSplat, V2IsSplat);
7513 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7514 // Shuffling low element of v1 into undef, just return v1.
7517 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7518 // the instruction selector will not match, so get a canonical MOVL with
7519 // swapped operands to undo the commute.
7520 return getMOVL(DAG, dl, VT, V2, V1);
7523 if (isUNPCKLMask(M, VT, HasInt256))
7524 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7526 if (isUNPCKHMask(M, VT, HasInt256))
7527 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7530 // Normalize mask so all entries that point to V2 points to its first
7531 // element then try to match unpck{h|l} again. If match, return a
7532 // new vector_shuffle with the corrected mask.p
7533 SmallVector<int, 8> NewMask(M.begin(), M.end());
7534 NormalizeMask(NewMask, NumElems);
7535 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7536 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7537 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7538 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7542 // Commute is back and try unpck* again.
7543 // FIXME: this seems wrong.
7544 CommuteVectorShuffleMask(M, NumElems);
7546 std::swap(V1IsSplat, V2IsSplat);
7549 if (isUNPCKLMask(M, VT, HasInt256))
7550 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7552 if (isUNPCKHMask(M, VT, HasInt256))
7553 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7556 // Normalize the node to match x86 shuffle ops if needed
7557 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7558 return CommuteVectorShuffle(SVOp, DAG);
7560 // The checks below are all present in isShuffleMaskLegal, but they are
7561 // inlined here right now to enable us to directly emit target specific
7562 // nodes, and remove one by one until they don't return Op anymore.
7564 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7565 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7566 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7567 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7570 if (isPSHUFHWMask(M, VT, HasInt256))
7571 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7572 getShufflePSHUFHWImmediate(SVOp),
7575 if (isPSHUFLWMask(M, VT, HasInt256))
7576 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7577 getShufflePSHUFLWImmediate(SVOp),
7580 if (isSHUFPMask(M, VT))
7581 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7582 getShuffleSHUFImmediate(SVOp), DAG);
7584 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7585 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7586 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7587 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7589 //===--------------------------------------------------------------------===//
7590 // Generate target specific nodes for 128 or 256-bit shuffles only
7591 // supported in the AVX instruction set.
7594 // Handle VMOVDDUPY permutations
7595 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7596 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7598 // Handle VPERMILPS/D* permutations
7599 if (isVPERMILPMask(M, VT)) {
7600 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7601 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7602 getShuffleSHUFImmediate(SVOp), DAG);
7603 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7604 getShuffleSHUFImmediate(SVOp), DAG);
7607 // Handle VPERM2F128/VPERM2I128 permutations
7608 if (isVPERM2X128Mask(M, VT, HasFp256))
7609 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7610 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7612 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7613 if (BlendOp.getNode())
7617 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7618 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7620 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7621 VT.is512BitVector()) {
7622 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7623 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7624 SmallVector<SDValue, 16> permclMask;
7625 for (unsigned i = 0; i != NumElems; ++i) {
7626 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7629 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7630 &permclMask[0], NumElems);
7632 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7633 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7634 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7635 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
7636 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
7639 //===--------------------------------------------------------------------===//
7640 // Since no target specific shuffle was selected for this generic one,
7641 // lower it into other known shuffles. FIXME: this isn't true yet, but
7642 // this is the plan.
7645 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7646 if (VT == MVT::v8i16) {
7647 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7648 if (NewOp.getNode())
7652 if (VT == MVT::v16i8) {
7653 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7654 if (NewOp.getNode())
7658 if (VT == MVT::v32i8) {
7659 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7660 if (NewOp.getNode())
7664 // Handle all 128-bit wide vectors with 4 elements, and match them with
7665 // several different shuffle types.
7666 if (NumElems == 4 && VT.is128BitVector())
7667 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7669 // Handle general 256-bit shuffles
7670 if (VT.is256BitVector())
7671 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7676 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7677 MVT VT = Op.getSimpleValueType();
7680 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7683 if (VT.getSizeInBits() == 8) {
7684 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7685 Op.getOperand(0), Op.getOperand(1));
7686 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7687 DAG.getValueType(VT));
7688 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7691 if (VT.getSizeInBits() == 16) {
7692 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7693 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7695 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7696 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7697 DAG.getNode(ISD::BITCAST, dl,
7701 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7702 Op.getOperand(0), Op.getOperand(1));
7703 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7704 DAG.getValueType(VT));
7705 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7708 if (VT == MVT::f32) {
7709 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7710 // the result back to FR32 register. It's only worth matching if the
7711 // result has a single use which is a store or a bitcast to i32. And in
7712 // the case of a store, it's not worth it if the index is a constant 0,
7713 // because a MOVSSmr can be used instead, which is smaller and faster.
7714 if (!Op.hasOneUse())
7716 SDNode *User = *Op.getNode()->use_begin();
7717 if ((User->getOpcode() != ISD::STORE ||
7718 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7719 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7720 (User->getOpcode() != ISD::BITCAST ||
7721 User->getValueType(0) != MVT::i32))
7723 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7724 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7727 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7730 if (VT == MVT::i32 || VT == MVT::i64) {
7731 // ExtractPS/pextrq works with constant index.
7732 if (isa<ConstantSDNode>(Op.getOperand(1)))
7738 /// Extract one bit from mask vector, like v16i1 or v8i1.
7739 /// AVX-512 feature.
7740 static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
7741 SDValue Vec = Op.getOperand(0);
7743 MVT VecVT = Vec.getSimpleValueType();
7744 SDValue Idx = Op.getOperand(1);
7745 MVT EltVT = Op.getSimpleValueType();
7747 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7749 // variable index can't be handled in mask registers,
7750 // extend vector to VR512
7751 if (!isa<ConstantSDNode>(Idx)) {
7752 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7753 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7754 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7755 ExtVT.getVectorElementType(), Ext, Idx);
7756 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7759 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7760 unsigned MaxSift = VecVT.getSizeInBits() - 1;
7761 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7762 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7763 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7764 DAG.getConstant(MaxSift, MVT::i8));
7765 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
7766 DAG.getIntPtrConstant(0));
7770 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7771 SelectionDAG &DAG) const {
7773 SDValue Vec = Op.getOperand(0);
7774 MVT VecVT = Vec.getSimpleValueType();
7775 SDValue Idx = Op.getOperand(1);
7777 if (Op.getSimpleValueType() == MVT::i1)
7778 return ExtractBitFromMaskVector(Op, DAG);
7780 if (!isa<ConstantSDNode>(Idx)) {
7781 if (VecVT.is512BitVector() ||
7782 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7783 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7786 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7787 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7788 MaskEltVT.getSizeInBits());
7790 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7791 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7792 getZeroVector(MaskVT, Subtarget, DAG, dl),
7793 Idx, DAG.getConstant(0, getPointerTy()));
7794 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7795 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7796 Perm, DAG.getConstant(0, getPointerTy()));
7801 // If this is a 256-bit vector result, first extract the 128-bit vector and
7802 // then extract the element from the 128-bit vector.
7803 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7805 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7806 // Get the 128-bit vector.
7807 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7808 MVT EltVT = VecVT.getVectorElementType();
7810 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7812 //if (IdxVal >= NumElems/2)
7813 // IdxVal -= NumElems/2;
7814 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7815 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7816 DAG.getConstant(IdxVal, MVT::i32));
7819 assert(VecVT.is128BitVector() && "Unexpected vector length");
7821 if (Subtarget->hasSSE41()) {
7822 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7827 MVT VT = Op.getSimpleValueType();
7828 // TODO: handle v16i8.
7829 if (VT.getSizeInBits() == 16) {
7830 SDValue Vec = Op.getOperand(0);
7831 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7833 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7834 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7835 DAG.getNode(ISD::BITCAST, dl,
7838 // Transform it so it match pextrw which produces a 32-bit result.
7839 MVT EltVT = MVT::i32;
7840 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7841 Op.getOperand(0), Op.getOperand(1));
7842 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7843 DAG.getValueType(VT));
7844 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7847 if (VT.getSizeInBits() == 32) {
7848 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7852 // SHUFPS the element to the lowest double word, then movss.
7853 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7854 MVT VVT = Op.getOperand(0).getSimpleValueType();
7855 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7856 DAG.getUNDEF(VVT), Mask);
7857 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7858 DAG.getIntPtrConstant(0));
7861 if (VT.getSizeInBits() == 64) {
7862 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7863 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7864 // to match extract_elt for f64.
7865 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7869 // UNPCKHPD the element to the lowest double word, then movsd.
7870 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7871 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7872 int Mask[2] = { 1, -1 };
7873 MVT VVT = Op.getOperand(0).getSimpleValueType();
7874 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7875 DAG.getUNDEF(VVT), Mask);
7876 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7877 DAG.getIntPtrConstant(0));
7883 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7884 MVT VT = Op.getSimpleValueType();
7885 MVT EltVT = VT.getVectorElementType();
7888 SDValue N0 = Op.getOperand(0);
7889 SDValue N1 = Op.getOperand(1);
7890 SDValue N2 = Op.getOperand(2);
7892 if (!VT.is128BitVector())
7895 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7896 isa<ConstantSDNode>(N2)) {
7898 if (VT == MVT::v8i16)
7899 Opc = X86ISD::PINSRW;
7900 else if (VT == MVT::v16i8)
7901 Opc = X86ISD::PINSRB;
7903 Opc = X86ISD::PINSRB;
7905 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7907 if (N1.getValueType() != MVT::i32)
7908 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7909 if (N2.getValueType() != MVT::i32)
7910 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7911 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7914 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7915 // Bits [7:6] of the constant are the source select. This will always be
7916 // zero here. The DAG Combiner may combine an extract_elt index into these
7917 // bits. For example (insert (extract, 3), 2) could be matched by putting
7918 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7919 // Bits [5:4] of the constant are the destination select. This is the
7920 // value of the incoming immediate.
7921 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7922 // combine either bitwise AND or insert of float 0.0 to set these bits.
7923 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7924 // Create this as a scalar to vector..
7925 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7926 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7929 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7930 // PINSR* works with constant index.
7937 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7938 MVT VT = Op.getSimpleValueType();
7939 MVT EltVT = VT.getVectorElementType();
7942 SDValue N0 = Op.getOperand(0);
7943 SDValue N1 = Op.getOperand(1);
7944 SDValue N2 = Op.getOperand(2);
7946 // If this is a 256-bit vector result, first extract the 128-bit vector,
7947 // insert the element into the extracted half and then place it back.
7948 if (VT.is256BitVector() || VT.is512BitVector()) {
7949 if (!isa<ConstantSDNode>(N2))
7952 // Get the desired 128-bit vector half.
7953 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7954 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7956 // Insert the element into the desired half.
7957 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7958 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7960 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7961 DAG.getConstant(IdxIn128, MVT::i32));
7963 // Insert the changed part back to the 256-bit vector
7964 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7967 if (Subtarget->hasSSE41())
7968 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7970 if (EltVT == MVT::i8)
7973 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7974 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7975 // as its second argument.
7976 if (N1.getValueType() != MVT::i32)
7977 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7978 if (N2.getValueType() != MVT::i32)
7979 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7980 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7985 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7987 MVT OpVT = Op.getSimpleValueType();
7989 // If this is a 256-bit vector result, first insert into a 128-bit
7990 // vector and then insert into the 256-bit vector.
7991 if (!OpVT.is128BitVector()) {
7992 // Insert into a 128-bit vector.
7993 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7994 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7995 OpVT.getVectorNumElements() / SizeFactor);
7997 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7999 // Insert the 128-bit vector.
8000 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
8003 if (OpVT == MVT::v1i64 &&
8004 Op.getOperand(0).getValueType() == MVT::i64)
8005 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
8007 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
8008 assert(OpVT.is128BitVector() && "Expected an SSE type!");
8009 return DAG.getNode(ISD::BITCAST, dl, OpVT,
8010 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
8013 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
8014 // a simple subregister reference or explicit instructions to grab
8015 // upper bits of a vector.
8016 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8017 SelectionDAG &DAG) {
8019 SDValue In = Op.getOperand(0);
8020 SDValue Idx = Op.getOperand(1);
8021 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8022 MVT ResVT = Op.getSimpleValueType();
8023 MVT InVT = In.getSimpleValueType();
8025 if (Subtarget->hasFp256()) {
8026 if (ResVT.is128BitVector() &&
8027 (InVT.is256BitVector() || InVT.is512BitVector()) &&
8028 isa<ConstantSDNode>(Idx)) {
8029 return Extract128BitVector(In, IdxVal, DAG, dl);
8031 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
8032 isa<ConstantSDNode>(Idx)) {
8033 return Extract256BitVector(In, IdxVal, DAG, dl);
8039 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8040 // simple superregister reference or explicit instructions to insert
8041 // the upper bits of a vector.
8042 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8043 SelectionDAG &DAG) {
8044 if (Subtarget->hasFp256()) {
8045 SDLoc dl(Op.getNode());
8046 SDValue Vec = Op.getNode()->getOperand(0);
8047 SDValue SubVec = Op.getNode()->getOperand(1);
8048 SDValue Idx = Op.getNode()->getOperand(2);
8050 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8051 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8052 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8053 isa<ConstantSDNode>(Idx)) {
8054 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8055 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8058 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8059 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8060 isa<ConstantSDNode>(Idx)) {
8061 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8062 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8068 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8069 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8070 // one of the above mentioned nodes. It has to be wrapped because otherwise
8071 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8072 // be used to form addressing mode. These wrapped nodes will be selected
8075 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8076 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8078 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8080 unsigned char OpFlag = 0;
8081 unsigned WrapperKind = X86ISD::Wrapper;
8082 CodeModel::Model M = getTargetMachine().getCodeModel();
8084 if (Subtarget->isPICStyleRIPRel() &&
8085 (M == CodeModel::Small || M == CodeModel::Kernel))
8086 WrapperKind = X86ISD::WrapperRIP;
8087 else if (Subtarget->isPICStyleGOT())
8088 OpFlag = X86II::MO_GOTOFF;
8089 else if (Subtarget->isPICStyleStubPIC())
8090 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8092 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8094 CP->getOffset(), OpFlag);
8096 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8097 // With PIC, the address is actually $g + Offset.
8099 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8100 DAG.getNode(X86ISD::GlobalBaseReg,
8101 SDLoc(), getPointerTy()),
8108 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8109 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8111 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8113 unsigned char OpFlag = 0;
8114 unsigned WrapperKind = X86ISD::Wrapper;
8115 CodeModel::Model M = getTargetMachine().getCodeModel();
8117 if (Subtarget->isPICStyleRIPRel() &&
8118 (M == CodeModel::Small || M == CodeModel::Kernel))
8119 WrapperKind = X86ISD::WrapperRIP;
8120 else if (Subtarget->isPICStyleGOT())
8121 OpFlag = X86II::MO_GOTOFF;
8122 else if (Subtarget->isPICStyleStubPIC())
8123 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8125 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8128 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8130 // With PIC, the address is actually $g + Offset.
8132 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8133 DAG.getNode(X86ISD::GlobalBaseReg,
8134 SDLoc(), getPointerTy()),
8141 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8142 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8144 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8146 unsigned char OpFlag = 0;
8147 unsigned WrapperKind = X86ISD::Wrapper;
8148 CodeModel::Model M = getTargetMachine().getCodeModel();
8150 if (Subtarget->isPICStyleRIPRel() &&
8151 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8152 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8153 OpFlag = X86II::MO_GOTPCREL;
8154 WrapperKind = X86ISD::WrapperRIP;
8155 } else if (Subtarget->isPICStyleGOT()) {
8156 OpFlag = X86II::MO_GOT;
8157 } else if (Subtarget->isPICStyleStubPIC()) {
8158 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8159 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8160 OpFlag = X86II::MO_DARWIN_NONLAZY;
8163 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8166 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8168 // With PIC, the address is actually $g + Offset.
8169 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8170 !Subtarget->is64Bit()) {
8171 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8172 DAG.getNode(X86ISD::GlobalBaseReg,
8173 SDLoc(), getPointerTy()),
8177 // For symbols that require a load from a stub to get the address, emit the
8179 if (isGlobalStubReference(OpFlag))
8180 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8181 MachinePointerInfo::getGOT(), false, false, false, 0);
8187 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8188 // Create the TargetBlockAddressAddress node.
8189 unsigned char OpFlags =
8190 Subtarget->ClassifyBlockAddressReference();
8191 CodeModel::Model M = getTargetMachine().getCodeModel();
8192 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8193 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8195 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8198 if (Subtarget->isPICStyleRIPRel() &&
8199 (M == CodeModel::Small || M == CodeModel::Kernel))
8200 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8202 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8204 // With PIC, the address is actually $g + Offset.
8205 if (isGlobalRelativeToPICBase(OpFlags)) {
8206 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8207 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8215 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8216 int64_t Offset, SelectionDAG &DAG) const {
8217 // Create the TargetGlobalAddress node, folding in the constant
8218 // offset if it is legal.
8219 unsigned char OpFlags =
8220 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8221 CodeModel::Model M = getTargetMachine().getCodeModel();
8223 if (OpFlags == X86II::MO_NO_FLAG &&
8224 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8225 // A direct static reference to a global.
8226 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8229 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8232 if (Subtarget->isPICStyleRIPRel() &&
8233 (M == CodeModel::Small || M == CodeModel::Kernel))
8234 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8236 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8238 // With PIC, the address is actually $g + Offset.
8239 if (isGlobalRelativeToPICBase(OpFlags)) {
8240 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8241 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8245 // For globals that require a load from a stub to get the address, emit the
8247 if (isGlobalStubReference(OpFlags))
8248 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8249 MachinePointerInfo::getGOT(), false, false, false, 0);
8251 // If there was a non-zero offset that we didn't fold, create an explicit
8254 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8255 DAG.getConstant(Offset, getPointerTy()));
8261 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8262 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8263 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8264 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8268 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8269 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8270 unsigned char OperandFlags, bool LocalDynamic = false) {
8271 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8272 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8274 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8275 GA->getValueType(0),
8279 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8283 SDValue Ops[] = { Chain, TGA, *InFlag };
8284 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8286 SDValue Ops[] = { Chain, TGA };
8287 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8290 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8291 MFI->setAdjustsStack(true);
8293 SDValue Flag = Chain.getValue(1);
8294 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8297 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8299 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8302 SDLoc dl(GA); // ? function entry point might be better
8303 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8304 DAG.getNode(X86ISD::GlobalBaseReg,
8305 SDLoc(), PtrVT), InFlag);
8306 InFlag = Chain.getValue(1);
8308 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8311 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8313 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8315 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8316 X86::RAX, X86II::MO_TLSGD);
8319 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8325 // Get the start address of the TLS block for this module.
8326 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8327 .getInfo<X86MachineFunctionInfo>();
8328 MFI->incNumLocalDynamicTLSAccesses();
8332 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8333 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8336 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8337 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8338 InFlag = Chain.getValue(1);
8339 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8340 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8343 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8347 unsigned char OperandFlags = X86II::MO_DTPOFF;
8348 unsigned WrapperKind = X86ISD::Wrapper;
8349 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8350 GA->getValueType(0),
8351 GA->getOffset(), OperandFlags);
8352 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8354 // Add x@dtpoff with the base.
8355 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8358 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8359 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8360 const EVT PtrVT, TLSModel::Model model,
8361 bool is64Bit, bool isPIC) {
8364 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8365 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8366 is64Bit ? 257 : 256));
8368 SDValue ThreadPointer =
8369 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8370 MachinePointerInfo(Ptr), false, false, false, 0);
8372 unsigned char OperandFlags = 0;
8373 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8375 unsigned WrapperKind = X86ISD::Wrapper;
8376 if (model == TLSModel::LocalExec) {
8377 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8378 } else if (model == TLSModel::InitialExec) {
8380 OperandFlags = X86II::MO_GOTTPOFF;
8381 WrapperKind = X86ISD::WrapperRIP;
8383 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8386 llvm_unreachable("Unexpected model");
8389 // emit "addl x@ntpoff,%eax" (local exec)
8390 // or "addl x@indntpoff,%eax" (initial exec)
8391 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8393 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8394 GA->getOffset(), OperandFlags);
8395 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8397 if (model == TLSModel::InitialExec) {
8398 if (isPIC && !is64Bit) {
8399 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8400 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8404 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8405 MachinePointerInfo::getGOT(), false, false, false, 0);
8408 // The address of the thread local variable is the add of the thread
8409 // pointer with the offset of the variable.
8410 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8414 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8416 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8417 const GlobalValue *GV = GA->getGlobal();
8419 if (Subtarget->isTargetELF()) {
8420 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8423 case TLSModel::GeneralDynamic:
8424 if (Subtarget->is64Bit())
8425 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8426 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8427 case TLSModel::LocalDynamic:
8428 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8429 Subtarget->is64Bit());
8430 case TLSModel::InitialExec:
8431 case TLSModel::LocalExec:
8432 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8433 Subtarget->is64Bit(),
8434 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8436 llvm_unreachable("Unknown TLS model.");
8439 if (Subtarget->isTargetDarwin()) {
8440 // Darwin only has one model of TLS. Lower to that.
8441 unsigned char OpFlag = 0;
8442 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8443 X86ISD::WrapperRIP : X86ISD::Wrapper;
8445 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8447 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8448 !Subtarget->is64Bit();
8450 OpFlag = X86II::MO_TLVP_PIC_BASE;
8452 OpFlag = X86II::MO_TLVP;
8454 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8455 GA->getValueType(0),
8456 GA->getOffset(), OpFlag);
8457 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8459 // With PIC32, the address is actually $g + Offset.
8461 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8462 DAG.getNode(X86ISD::GlobalBaseReg,
8463 SDLoc(), getPointerTy()),
8466 // Lowering the machine isd will make sure everything is in the right
8468 SDValue Chain = DAG.getEntryNode();
8469 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8470 SDValue Args[] = { Chain, Offset };
8471 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8473 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8474 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8475 MFI->setAdjustsStack(true);
8477 // And our return value (tls address) is in the standard call return value
8479 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8480 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8484 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8485 // Just use the implicit TLS architecture
8486 // Need to generate someting similar to:
8487 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8489 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8490 // mov rcx, qword [rdx+rcx*8]
8491 // mov eax, .tls$:tlsvar
8492 // [rax+rcx] contains the address
8493 // Windows 64bit: gs:0x58
8494 // Windows 32bit: fs:__tls_array
8496 // If GV is an alias then use the aliasee for determining
8497 // thread-localness.
8498 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8499 GV = GA->resolveAliasedGlobal(false);
8501 SDValue Chain = DAG.getEntryNode();
8503 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8504 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8505 // use its literal value of 0x2C.
8506 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8507 ? Type::getInt8PtrTy(*DAG.getContext(),
8509 : Type::getInt32PtrTy(*DAG.getContext(),
8512 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8513 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8514 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8516 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8517 MachinePointerInfo(Ptr),
8518 false, false, false, 0);
8520 // Load the _tls_index variable
8521 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8522 if (Subtarget->is64Bit())
8523 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8524 IDX, MachinePointerInfo(), MVT::i32,
8527 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8528 false, false, false, 0);
8530 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8532 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8534 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8535 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8536 false, false, false, 0);
8538 // Get the offset of start of .tls section
8539 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8540 GA->getValueType(0),
8541 GA->getOffset(), X86II::MO_SECREL);
8542 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8544 // The address of the thread local variable is the add of the thread
8545 // pointer with the offset of the variable.
8546 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8549 llvm_unreachable("TLS not implemented for this target.");
8552 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8553 /// and take a 2 x i32 value to shift plus a shift amount.
8554 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
8555 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8556 MVT VT = Op.getSimpleValueType();
8557 unsigned VTBits = VT.getSizeInBits();
8559 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8560 SDValue ShOpLo = Op.getOperand(0);
8561 SDValue ShOpHi = Op.getOperand(1);
8562 SDValue ShAmt = Op.getOperand(2);
8563 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8564 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8566 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8567 DAG.getConstant(VTBits - 1, MVT::i8));
8568 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8569 DAG.getConstant(VTBits - 1, MVT::i8))
8570 : DAG.getConstant(0, VT);
8573 if (Op.getOpcode() == ISD::SHL_PARTS) {
8574 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8575 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8577 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8578 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8581 // If the shift amount is larger or equal than the width of a part we can't
8582 // rely on the results of shld/shrd. Insert a test and select the appropriate
8583 // values for large shift amounts.
8584 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8585 DAG.getConstant(VTBits, MVT::i8));
8586 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8587 AndNode, DAG.getConstant(0, MVT::i8));
8590 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8591 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8592 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8594 if (Op.getOpcode() == ISD::SHL_PARTS) {
8595 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8596 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8598 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8599 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8602 SDValue Ops[2] = { Lo, Hi };
8603 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8606 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8607 SelectionDAG &DAG) const {
8608 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
8610 if (SrcVT.isVector())
8613 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
8614 "Unknown SINT_TO_FP to lower!");
8616 // These are really Legal; return the operand so the caller accepts it as
8618 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8620 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8621 Subtarget->is64Bit()) {
8626 unsigned Size = SrcVT.getSizeInBits()/8;
8627 MachineFunction &MF = DAG.getMachineFunction();
8628 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8629 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8630 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8632 MachinePointerInfo::getFixedStack(SSFI),
8634 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8637 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8639 SelectionDAG &DAG) const {
8643 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8645 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8647 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8649 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8651 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8652 MachineMemOperand *MMO;
8654 int SSFI = FI->getIndex();
8656 DAG.getMachineFunction()
8657 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8658 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8660 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8661 StackSlot = StackSlot.getOperand(1);
8663 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8664 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8666 Tys, Ops, array_lengthof(Ops),
8670 Chain = Result.getValue(1);
8671 SDValue InFlag = Result.getValue(2);
8673 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8674 // shouldn't be necessary except that RFP cannot be live across
8675 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8676 MachineFunction &MF = DAG.getMachineFunction();
8677 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8678 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8679 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8680 Tys = DAG.getVTList(MVT::Other);
8682 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8684 MachineMemOperand *MMO =
8685 DAG.getMachineFunction()
8686 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8687 MachineMemOperand::MOStore, SSFISize, SSFISize);
8689 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8690 Ops, array_lengthof(Ops),
8691 Op.getValueType(), MMO);
8692 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8693 MachinePointerInfo::getFixedStack(SSFI),
8694 false, false, false, 0);
8700 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8701 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8702 SelectionDAG &DAG) const {
8703 // This algorithm is not obvious. Here it is what we're trying to output:
8706 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8707 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8711 pshufd $0x4e, %xmm0, %xmm1
8717 LLVMContext *Context = DAG.getContext();
8719 // Build some magic constants.
8720 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8721 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8722 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8724 SmallVector<Constant*,2> CV1;
8726 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8727 APInt(64, 0x4330000000000000ULL))));
8729 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8730 APInt(64, 0x4530000000000000ULL))));
8731 Constant *C1 = ConstantVector::get(CV1);
8732 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8734 // Load the 64-bit value into an XMM register.
8735 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8737 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8738 MachinePointerInfo::getConstantPool(),
8739 false, false, false, 16);
8740 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8741 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8744 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8745 MachinePointerInfo::getConstantPool(),
8746 false, false, false, 16);
8747 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8748 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8751 if (Subtarget->hasSSE3()) {
8752 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8753 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8755 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8756 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8758 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8759 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8763 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8764 DAG.getIntPtrConstant(0));
8767 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8768 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8769 SelectionDAG &DAG) const {
8771 // FP constant to bias correct the final result.
8772 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8775 // Load the 32-bit value into an XMM register.
8776 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8779 // Zero out the upper parts of the register.
8780 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8782 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8783 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8784 DAG.getIntPtrConstant(0));
8786 // Or the load with the bias.
8787 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8788 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8789 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8791 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8792 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8793 MVT::v2f64, Bias)));
8794 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8795 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8796 DAG.getIntPtrConstant(0));
8798 // Subtract the bias.
8799 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8801 // Handle final rounding.
8802 EVT DestVT = Op.getValueType();
8804 if (DestVT.bitsLT(MVT::f64))
8805 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8806 DAG.getIntPtrConstant(0));
8807 if (DestVT.bitsGT(MVT::f64))
8808 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8810 // Handle final rounding.
8814 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8815 SelectionDAG &DAG) const {
8816 SDValue N0 = Op.getOperand(0);
8817 MVT SVT = N0.getSimpleValueType();
8820 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8821 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8822 "Custom UINT_TO_FP is not supported!");
8824 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
8825 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8826 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8829 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8830 SelectionDAG &DAG) const {
8831 SDValue N0 = Op.getOperand(0);
8834 if (Op.getValueType().isVector())
8835 return lowerUINT_TO_FP_vec(Op, DAG);
8837 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8838 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8839 // the optimization here.
8840 if (DAG.SignBitIsZero(N0))
8841 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8843 MVT SrcVT = N0.getSimpleValueType();
8844 MVT DstVT = Op.getSimpleValueType();
8845 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8846 return LowerUINT_TO_FP_i64(Op, DAG);
8847 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8848 return LowerUINT_TO_FP_i32(Op, DAG);
8849 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8852 // Make a 64-bit buffer, and use it to build an FILD.
8853 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8854 if (SrcVT == MVT::i32) {
8855 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8856 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8857 getPointerTy(), StackSlot, WordOff);
8858 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8859 StackSlot, MachinePointerInfo(),
8861 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8862 OffsetSlot, MachinePointerInfo(),
8864 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8868 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8869 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8870 StackSlot, MachinePointerInfo(),
8872 // For i64 source, we need to add the appropriate power of 2 if the input
8873 // was negative. This is the same as the optimization in
8874 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8875 // we must be careful to do the computation in x87 extended precision, not
8876 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8877 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8878 MachineMemOperand *MMO =
8879 DAG.getMachineFunction()
8880 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8881 MachineMemOperand::MOLoad, 8, 8);
8883 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8884 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8885 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8886 array_lengthof(Ops), MVT::i64, MMO);
8888 APInt FF(32, 0x5F800000ULL);
8890 // Check whether the sign bit is set.
8891 SDValue SignSet = DAG.getSetCC(dl,
8892 getSetCCResultType(*DAG.getContext(), MVT::i64),
8893 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8896 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8897 SDValue FudgePtr = DAG.getConstantPool(
8898 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8901 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8902 SDValue Zero = DAG.getIntPtrConstant(0);
8903 SDValue Four = DAG.getIntPtrConstant(4);
8904 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8906 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8908 // Load the value out, extending it from f32 to f80.
8909 // FIXME: Avoid the extend by constructing the right constant pool?
8910 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8911 FudgePtr, MachinePointerInfo::getConstantPool(),
8912 MVT::f32, false, false, 4);
8913 // Extend everything to 80 bits to force it to be done on x87.
8914 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8915 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8918 std::pair<SDValue,SDValue>
8919 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8920 bool IsSigned, bool IsReplace) const {
8923 EVT DstTy = Op.getValueType();
8925 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8926 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8930 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8931 DstTy.getSimpleVT() >= MVT::i16 &&
8932 "Unknown FP_TO_INT to lower!");
8934 // These are really Legal.
8935 if (DstTy == MVT::i32 &&
8936 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8937 return std::make_pair(SDValue(), SDValue());
8938 if (Subtarget->is64Bit() &&
8939 DstTy == MVT::i64 &&
8940 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8941 return std::make_pair(SDValue(), SDValue());
8943 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8944 // stack slot, or into the FTOL runtime function.
8945 MachineFunction &MF = DAG.getMachineFunction();
8946 unsigned MemSize = DstTy.getSizeInBits()/8;
8947 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8948 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8951 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8952 Opc = X86ISD::WIN_FTOL;
8954 switch (DstTy.getSimpleVT().SimpleTy) {
8955 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8956 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8957 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8958 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8961 SDValue Chain = DAG.getEntryNode();
8962 SDValue Value = Op.getOperand(0);
8963 EVT TheVT = Op.getOperand(0).getValueType();
8964 // FIXME This causes a redundant load/store if the SSE-class value is already
8965 // in memory, such as if it is on the callstack.
8966 if (isScalarFPTypeInSSEReg(TheVT)) {
8967 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8968 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8969 MachinePointerInfo::getFixedStack(SSFI),
8971 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8973 Chain, StackSlot, DAG.getValueType(TheVT)
8976 MachineMemOperand *MMO =
8977 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8978 MachineMemOperand::MOLoad, MemSize, MemSize);
8979 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8980 array_lengthof(Ops), DstTy, MMO);
8981 Chain = Value.getValue(1);
8982 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8983 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8986 MachineMemOperand *MMO =
8987 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8988 MachineMemOperand::MOStore, MemSize, MemSize);
8990 if (Opc != X86ISD::WIN_FTOL) {
8991 // Build the FP_TO_INT*_IN_MEM
8992 SDValue Ops[] = { Chain, Value, StackSlot };
8993 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8994 Ops, array_lengthof(Ops), DstTy,
8996 return std::make_pair(FIST, StackSlot);
8998 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8999 DAG.getVTList(MVT::Other, MVT::Glue),
9001 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
9002 MVT::i32, ftol.getValue(1));
9003 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
9004 MVT::i32, eax.getValue(2));
9005 SDValue Ops[] = { eax, edx };
9006 SDValue pair = IsReplace
9007 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
9008 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
9009 return std::make_pair(pair, SDValue());
9013 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
9014 const X86Subtarget *Subtarget) {
9015 MVT VT = Op->getSimpleValueType(0);
9016 SDValue In = Op->getOperand(0);
9017 MVT InVT = In.getSimpleValueType();
9020 // Optimize vectors in AVX mode:
9023 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
9024 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
9025 // Concat upper and lower parts.
9028 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
9029 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
9030 // Concat upper and lower parts.
9033 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
9034 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
9035 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
9038 if (Subtarget->hasInt256())
9039 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
9041 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
9042 SDValue Undef = DAG.getUNDEF(InVT);
9043 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
9044 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9045 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9047 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9048 VT.getVectorNumElements()/2);
9050 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9051 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9053 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9056 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9057 SelectionDAG &DAG) {
9058 MVT VT = Op->getSimpleValueType(0);
9059 SDValue In = Op->getOperand(0);
9060 MVT InVT = In.getSimpleValueType();
9062 unsigned int NumElts = VT.getVectorNumElements();
9063 if (NumElts != 8 && NumElts != 16)
9066 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9067 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9069 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9070 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9071 // Now we have only mask extension
9072 assert(InVT.getVectorElementType() == MVT::i1);
9073 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9074 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9075 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9076 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9077 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9078 MachinePointerInfo::getConstantPool(),
9079 false, false, false, Alignment);
9081 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9082 if (VT.is512BitVector())
9084 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9087 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9088 SelectionDAG &DAG) {
9089 if (Subtarget->hasFp256()) {
9090 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9098 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9099 SelectionDAG &DAG) {
9101 MVT VT = Op.getSimpleValueType();
9102 SDValue In = Op.getOperand(0);
9103 MVT SVT = In.getSimpleValueType();
9105 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9106 return LowerZERO_EXTEND_AVX512(Op, DAG);
9108 if (Subtarget->hasFp256()) {
9109 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9114 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9115 VT.getVectorNumElements() != SVT.getVectorNumElements());
9119 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9121 MVT VT = Op.getSimpleValueType();
9122 SDValue In = Op.getOperand(0);
9123 MVT InVT = In.getSimpleValueType();
9125 if (VT == MVT::i1) {
9126 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9127 "Invalid scalar TRUNCATE operation");
9128 if (InVT == MVT::i32)
9130 if (InVT.getSizeInBits() == 64)
9131 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9132 else if (InVT.getSizeInBits() < 32)
9133 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9134 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9136 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9137 "Invalid TRUNCATE operation");
9139 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9140 if (VT.getVectorElementType().getSizeInBits() >=8)
9141 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9143 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9144 unsigned NumElts = InVT.getVectorNumElements();
9145 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9146 if (InVT.getSizeInBits() < 512) {
9147 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9148 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9152 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9153 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9154 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9155 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9156 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9157 MachinePointerInfo::getConstantPool(),
9158 false, false, false, Alignment);
9159 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9160 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9161 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9164 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9165 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9166 if (Subtarget->hasInt256()) {
9167 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9168 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9169 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9171 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9172 DAG.getIntPtrConstant(0));
9175 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9176 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9177 DAG.getIntPtrConstant(0));
9178 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9179 DAG.getIntPtrConstant(2));
9181 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9182 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9185 static const int ShufMask1[] = {0, 2, 0, 0};
9186 SDValue Undef = DAG.getUNDEF(VT);
9187 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9188 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9190 // The MOVLHPS mask:
9191 static const int ShufMask2[] = {0, 1, 4, 5};
9192 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9195 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9196 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9197 if (Subtarget->hasInt256()) {
9198 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9200 SmallVector<SDValue,32> pshufbMask;
9201 for (unsigned i = 0; i < 2; ++i) {
9202 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9203 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9204 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9205 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9206 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9207 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9208 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9209 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9210 for (unsigned j = 0; j < 8; ++j)
9211 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9213 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9214 &pshufbMask[0], 32);
9215 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9216 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9218 static const int ShufMask[] = {0, 2, -1, -1};
9219 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9221 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9222 DAG.getIntPtrConstant(0));
9223 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9226 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9227 DAG.getIntPtrConstant(0));
9229 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9230 DAG.getIntPtrConstant(4));
9232 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9233 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9236 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9237 -1, -1, -1, -1, -1, -1, -1, -1};
9239 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9240 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9241 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9243 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9244 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9246 // The MOVLHPS Mask:
9247 static const int ShufMask2[] = {0, 1, 4, 5};
9248 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9249 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9252 // Handle truncation of V256 to V128 using shuffles.
9253 if (!VT.is128BitVector() || !InVT.is256BitVector())
9256 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9258 unsigned NumElems = VT.getVectorNumElements();
9259 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
9261 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9262 // Prepare truncation shuffle mask
9263 for (unsigned i = 0; i != NumElems; ++i)
9265 SDValue V = DAG.getVectorShuffle(NVT, DL,
9266 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9267 DAG.getUNDEF(NVT), &MaskVec[0]);
9268 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9269 DAG.getIntPtrConstant(0));
9272 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9273 SelectionDAG &DAG) const {
9274 MVT VT = Op.getSimpleValueType();
9275 if (VT.isVector()) {
9276 if (VT == MVT::v8i16)
9277 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9278 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9279 MVT::v8i32, Op.getOperand(0)));
9283 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9284 /*IsSigned=*/ true, /*IsReplace=*/ false);
9285 SDValue FIST = Vals.first, StackSlot = Vals.second;
9286 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9287 if (FIST.getNode() == 0) return Op;
9289 if (StackSlot.getNode())
9291 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9292 FIST, StackSlot, MachinePointerInfo(),
9293 false, false, false, 0);
9295 // The node is the result.
9299 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9300 SelectionDAG &DAG) const {
9301 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9302 /*IsSigned=*/ false, /*IsReplace=*/ false);
9303 SDValue FIST = Vals.first, StackSlot = Vals.second;
9304 assert(FIST.getNode() && "Unexpected failure");
9306 if (StackSlot.getNode())
9308 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9309 FIST, StackSlot, MachinePointerInfo(),
9310 false, false, false, 0);
9312 // The node is the result.
9316 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9318 MVT VT = Op.getSimpleValueType();
9319 SDValue In = Op.getOperand(0);
9320 MVT SVT = In.getSimpleValueType();
9322 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9324 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9325 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9326 In, DAG.getUNDEF(SVT)));
9329 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
9330 LLVMContext *Context = DAG.getContext();
9332 MVT VT = Op.getSimpleValueType();
9334 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9335 if (VT.isVector()) {
9336 EltVT = VT.getVectorElementType();
9337 NumElts = VT.getVectorNumElements();
9340 if (EltVT == MVT::f64)
9341 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9342 APInt(64, ~(1ULL << 63))));
9344 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9345 APInt(32, ~(1U << 31))));
9346 C = ConstantVector::getSplat(NumElts, C);
9347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9348 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9349 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9350 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9351 MachinePointerInfo::getConstantPool(),
9352 false, false, false, Alignment);
9353 if (VT.isVector()) {
9354 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9355 return DAG.getNode(ISD::BITCAST, dl, VT,
9356 DAG.getNode(ISD::AND, dl, ANDVT,
9357 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9359 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9361 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9364 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
9365 LLVMContext *Context = DAG.getContext();
9367 MVT VT = Op.getSimpleValueType();
9369 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9370 if (VT.isVector()) {
9371 EltVT = VT.getVectorElementType();
9372 NumElts = VT.getVectorNumElements();
9375 if (EltVT == MVT::f64)
9376 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9377 APInt(64, 1ULL << 63)));
9379 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9380 APInt(32, 1U << 31)));
9381 C = ConstantVector::getSplat(NumElts, C);
9382 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9383 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9384 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9385 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9386 MachinePointerInfo::getConstantPool(),
9387 false, false, false, Alignment);
9388 if (VT.isVector()) {
9389 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9390 return DAG.getNode(ISD::BITCAST, dl, VT,
9391 DAG.getNode(ISD::XOR, dl, XORVT,
9392 DAG.getNode(ISD::BITCAST, dl, XORVT,
9394 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9397 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9400 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
9401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9402 LLVMContext *Context = DAG.getContext();
9403 SDValue Op0 = Op.getOperand(0);
9404 SDValue Op1 = Op.getOperand(1);
9406 MVT VT = Op.getSimpleValueType();
9407 MVT SrcVT = Op1.getSimpleValueType();
9409 // If second operand is smaller, extend it first.
9410 if (SrcVT.bitsLT(VT)) {
9411 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9414 // And if it is bigger, shrink it first.
9415 if (SrcVT.bitsGT(VT)) {
9416 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9420 // At this point the operands and the result should have the same
9421 // type, and that won't be f80 since that is not custom lowered.
9423 // First get the sign bit of second operand.
9424 SmallVector<Constant*,4> CV;
9425 if (SrcVT == MVT::f64) {
9426 const fltSemantics &Sem = APFloat::IEEEdouble;
9427 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9428 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9430 const fltSemantics &Sem = APFloat::IEEEsingle;
9431 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9432 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9433 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9434 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9436 Constant *C = ConstantVector::get(CV);
9437 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9438 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9439 MachinePointerInfo::getConstantPool(),
9440 false, false, false, 16);
9441 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9443 // Shift sign bit right or left if the two operands have different types.
9444 if (SrcVT.bitsGT(VT)) {
9445 // Op0 is MVT::f32, Op1 is MVT::f64.
9446 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9447 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9448 DAG.getConstant(32, MVT::i32));
9449 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9450 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9451 DAG.getIntPtrConstant(0));
9454 // Clear first operand sign bit.
9456 if (VT == MVT::f64) {
9457 const fltSemantics &Sem = APFloat::IEEEdouble;
9458 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9459 APInt(64, ~(1ULL << 63)))));
9460 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9462 const fltSemantics &Sem = APFloat::IEEEsingle;
9463 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9464 APInt(32, ~(1U << 31)))));
9465 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9466 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9467 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9469 C = ConstantVector::get(CV);
9470 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9471 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9472 MachinePointerInfo::getConstantPool(),
9473 false, false, false, 16);
9474 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9476 // Or the value with the sign bit.
9477 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9480 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9481 SDValue N0 = Op.getOperand(0);
9483 MVT VT = Op.getSimpleValueType();
9485 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9486 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9487 DAG.getConstant(1, VT));
9488 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9491 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9493 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9494 SelectionDAG &DAG) {
9495 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9497 if (!Subtarget->hasSSE41())
9500 if (!Op->hasOneUse())
9503 SDNode *N = Op.getNode();
9506 SmallVector<SDValue, 8> Opnds;
9507 DenseMap<SDValue, unsigned> VecInMap;
9508 EVT VT = MVT::Other;
9510 // Recognize a special case where a vector is casted into wide integer to
9512 Opnds.push_back(N->getOperand(0));
9513 Opnds.push_back(N->getOperand(1));
9515 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9516 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9517 // BFS traverse all OR'd operands.
9518 if (I->getOpcode() == ISD::OR) {
9519 Opnds.push_back(I->getOperand(0));
9520 Opnds.push_back(I->getOperand(1));
9521 // Re-evaluate the number of nodes to be traversed.
9522 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9526 // Quit if a non-EXTRACT_VECTOR_ELT
9527 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9530 // Quit if without a constant index.
9531 SDValue Idx = I->getOperand(1);
9532 if (!isa<ConstantSDNode>(Idx))
9535 SDValue ExtractedFromVec = I->getOperand(0);
9536 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9537 if (M == VecInMap.end()) {
9538 VT = ExtractedFromVec.getValueType();
9539 // Quit if not 128/256-bit vector.
9540 if (!VT.is128BitVector() && !VT.is256BitVector())
9542 // Quit if not the same type.
9543 if (VecInMap.begin() != VecInMap.end() &&
9544 VT != VecInMap.begin()->first.getValueType())
9546 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9548 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9551 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9552 "Not extracted from 128-/256-bit vector.");
9554 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9555 SmallVector<SDValue, 8> VecIns;
9557 for (DenseMap<SDValue, unsigned>::const_iterator
9558 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9559 // Quit if not all elements are used.
9560 if (I->second != FullMask)
9562 VecIns.push_back(I->first);
9565 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9567 // Cast all vectors into TestVT for PTEST.
9568 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9569 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9571 // If more than one full vectors are evaluated, OR them first before PTEST.
9572 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9573 // Each iteration will OR 2 nodes and append the result until there is only
9574 // 1 node left, i.e. the final OR'd value of all vectors.
9575 SDValue LHS = VecIns[Slot];
9576 SDValue RHS = VecIns[Slot + 1];
9577 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9580 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9581 VecIns.back(), VecIns.back());
9584 /// Emit nodes that will be selected as "test Op0,Op0", or something
9586 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9587 SelectionDAG &DAG) const {
9590 if (Op.getValueType() == MVT::i1)
9591 // KORTEST instruction should be selected
9592 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9593 DAG.getConstant(0, Op.getValueType()));
9595 // CF and OF aren't always set the way we want. Determine which
9596 // of these we need.
9597 bool NeedCF = false;
9598 bool NeedOF = false;
9601 case X86::COND_A: case X86::COND_AE:
9602 case X86::COND_B: case X86::COND_BE:
9605 case X86::COND_G: case X86::COND_GE:
9606 case X86::COND_L: case X86::COND_LE:
9607 case X86::COND_O: case X86::COND_NO:
9611 // See if we can use the EFLAGS value from the operand instead of
9612 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9613 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9614 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
9615 // Emit a CMP with 0, which is the TEST pattern.
9616 //if (Op.getValueType() == MVT::i1)
9617 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
9618 // DAG.getConstant(0, MVT::i1));
9619 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9620 DAG.getConstant(0, Op.getValueType()));
9622 unsigned Opcode = 0;
9623 unsigned NumOperands = 0;
9625 // Truncate operations may prevent the merge of the SETCC instruction
9626 // and the arithmetic instruction before it. Attempt to truncate the operands
9627 // of the arithmetic instruction and use a reduced bit-width instruction.
9628 bool NeedTruncation = false;
9629 SDValue ArithOp = Op;
9630 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9631 SDValue Arith = Op->getOperand(0);
9632 // Both the trunc and the arithmetic op need to have one user each.
9633 if (Arith->hasOneUse())
9634 switch (Arith.getOpcode()) {
9641 NeedTruncation = true;
9647 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9648 // which may be the result of a CAST. We use the variable 'Op', which is the
9649 // non-casted variable when we check for possible users.
9650 switch (ArithOp.getOpcode()) {
9652 // Due to an isel shortcoming, be conservative if this add is likely to be
9653 // selected as part of a load-modify-store instruction. When the root node
9654 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9655 // uses of other nodes in the match, such as the ADD in this case. This
9656 // leads to the ADD being left around and reselected, with the result being
9657 // two adds in the output. Alas, even if none our users are stores, that
9658 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9659 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9660 // climbing the DAG back to the root, and it doesn't seem to be worth the
9662 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9663 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9664 if (UI->getOpcode() != ISD::CopyToReg &&
9665 UI->getOpcode() != ISD::SETCC &&
9666 UI->getOpcode() != ISD::STORE)
9669 if (ConstantSDNode *C =
9670 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9671 // An add of one will be selected as an INC.
9672 if (C->getAPIntValue() == 1) {
9673 Opcode = X86ISD::INC;
9678 // An add of negative one (subtract of one) will be selected as a DEC.
9679 if (C->getAPIntValue().isAllOnesValue()) {
9680 Opcode = X86ISD::DEC;
9686 // Otherwise use a regular EFLAGS-setting add.
9687 Opcode = X86ISD::ADD;
9691 // If the primary and result isn't used, don't bother using X86ISD::AND,
9692 // because a TEST instruction will be better.
9693 bool NonFlagUse = false;
9694 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9695 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9697 unsigned UOpNo = UI.getOperandNo();
9698 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9699 // Look pass truncate.
9700 UOpNo = User->use_begin().getOperandNo();
9701 User = *User->use_begin();
9704 if (User->getOpcode() != ISD::BRCOND &&
9705 User->getOpcode() != ISD::SETCC &&
9706 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9719 // Due to the ISEL shortcoming noted above, be conservative if this op is
9720 // likely to be selected as part of a load-modify-store instruction.
9721 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9722 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9723 if (UI->getOpcode() == ISD::STORE)
9726 // Otherwise use a regular EFLAGS-setting instruction.
9727 switch (ArithOp.getOpcode()) {
9728 default: llvm_unreachable("unexpected operator!");
9729 case ISD::SUB: Opcode = X86ISD::SUB; break;
9730 case ISD::XOR: Opcode = X86ISD::XOR; break;
9731 case ISD::AND: Opcode = X86ISD::AND; break;
9733 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9734 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9735 if (EFLAGS.getNode())
9738 Opcode = X86ISD::OR;
9752 return SDValue(Op.getNode(), 1);
9758 // If we found that truncation is beneficial, perform the truncation and
9760 if (NeedTruncation) {
9761 EVT VT = Op.getValueType();
9762 SDValue WideVal = Op->getOperand(0);
9763 EVT WideVT = WideVal.getValueType();
9764 unsigned ConvertedOp = 0;
9765 // Use a target machine opcode to prevent further DAGCombine
9766 // optimizations that may separate the arithmetic operations
9767 // from the setcc node.
9768 switch (WideVal.getOpcode()) {
9770 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9771 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9772 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9773 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9774 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9778 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9779 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9780 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9781 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9782 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9788 // Emit a CMP with 0, which is the TEST pattern.
9789 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9790 DAG.getConstant(0, Op.getValueType()));
9792 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9793 SmallVector<SDValue, 4> Ops;
9794 for (unsigned i = 0; i != NumOperands; ++i)
9795 Ops.push_back(Op.getOperand(i));
9797 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9798 DAG.ReplaceAllUsesWith(Op, New);
9799 return SDValue(New.getNode(), 1);
9802 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9804 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9805 SelectionDAG &DAG) const {
9807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9808 if (C->getAPIntValue() == 0)
9809 return EmitTest(Op0, X86CC, DAG);
9811 if (Op0.getValueType() == MVT::i1) {
9813 Op0 = DAG.getNode(ISD::XOR, dl, MVT::i1, Op0,
9814 DAG.getConstant(-1, MVT::i1));
9815 return EmitTest(Op0, X86CC, DAG);
9819 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9820 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9821 // Do the comparison at i32 if it's smaller. This avoids subregister
9822 // aliasing issues. Keep the smaller reference if we're optimizing for
9823 // size, however, as that'll allow better folding of memory operations.
9824 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9825 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9826 AttributeSet::FunctionIndex, Attribute::MinSize)) {
9828 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9829 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9830 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9832 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9833 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9834 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9836 return SDValue(Sub.getNode(), 1);
9838 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9841 /// Convert a comparison if required by the subtarget.
9842 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9843 SelectionDAG &DAG) const {
9844 // If the subtarget does not support the FUCOMI instruction, floating-point
9845 // comparisons have to be converted.
9846 if (Subtarget->hasCMov() ||
9847 Cmp.getOpcode() != X86ISD::CMP ||
9848 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9849 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9852 // The instruction selector will select an FUCOM instruction instead of
9853 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9854 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9855 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9857 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9858 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9859 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9860 DAG.getConstant(8, MVT::i8));
9861 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9862 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9865 static bool isAllOnes(SDValue V) {
9866 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9867 return C && C->isAllOnesValue();
9870 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9871 /// if it's possible.
9872 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9873 SDLoc dl, SelectionDAG &DAG) const {
9874 SDValue Op0 = And.getOperand(0);
9875 SDValue Op1 = And.getOperand(1);
9876 if (Op0.getOpcode() == ISD::TRUNCATE)
9877 Op0 = Op0.getOperand(0);
9878 if (Op1.getOpcode() == ISD::TRUNCATE)
9879 Op1 = Op1.getOperand(0);
9882 if (Op1.getOpcode() == ISD::SHL)
9883 std::swap(Op0, Op1);
9884 if (Op0.getOpcode() == ISD::SHL) {
9885 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9886 if (And00C->getZExtValue() == 1) {
9887 // If we looked past a truncate, check that it's only truncating away
9889 unsigned BitWidth = Op0.getValueSizeInBits();
9890 unsigned AndBitWidth = And.getValueSizeInBits();
9891 if (BitWidth > AndBitWidth) {
9893 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9894 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9898 RHS = Op0.getOperand(1);
9900 } else if (Op1.getOpcode() == ISD::Constant) {
9901 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9902 uint64_t AndRHSVal = AndRHS->getZExtValue();
9903 SDValue AndLHS = Op0;
9905 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9906 LHS = AndLHS.getOperand(0);
9907 RHS = AndLHS.getOperand(1);
9910 // Use BT if the immediate can't be encoded in a TEST instruction.
9911 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9913 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9917 if (LHS.getNode()) {
9918 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9919 // instruction. Since the shift amount is in-range-or-undefined, we know
9920 // that doing a bittest on the i32 value is ok. We extend to i32 because
9921 // the encoding for the i16 version is larger than the i32 version.
9922 // Also promote i16 to i32 for performance / code size reason.
9923 if (LHS.getValueType() == MVT::i8 ||
9924 LHS.getValueType() == MVT::i16)
9925 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9927 // If the operand types disagree, extend the shift amount to match. Since
9928 // BT ignores high bits (like shifts) we can use anyextend.
9929 if (LHS.getValueType() != RHS.getValueType())
9930 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9932 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9933 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9934 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9935 DAG.getConstant(Cond, MVT::i8), BT);
9941 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9943 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9948 // SSE Condition code mapping:
9957 switch (SetCCOpcode) {
9958 default: llvm_unreachable("Unexpected SETCC condition");
9960 case ISD::SETEQ: SSECC = 0; break;
9962 case ISD::SETGT: Swap = true; // Fallthrough
9964 case ISD::SETOLT: SSECC = 1; break;
9966 case ISD::SETGE: Swap = true; // Fallthrough
9968 case ISD::SETOLE: SSECC = 2; break;
9969 case ISD::SETUO: SSECC = 3; break;
9971 case ISD::SETNE: SSECC = 4; break;
9972 case ISD::SETULE: Swap = true; // Fallthrough
9973 case ISD::SETUGE: SSECC = 5; break;
9974 case ISD::SETULT: Swap = true; // Fallthrough
9975 case ISD::SETUGT: SSECC = 6; break;
9976 case ISD::SETO: SSECC = 7; break;
9978 case ISD::SETONE: SSECC = 8; break;
9981 std::swap(Op0, Op1);
9986 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9987 // ones, and then concatenate the result back.
9988 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9989 MVT VT = Op.getSimpleValueType();
9991 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9992 "Unsupported value type for operation");
9994 unsigned NumElems = VT.getVectorNumElements();
9996 SDValue CC = Op.getOperand(2);
9998 // Extract the LHS vectors
9999 SDValue LHS = Op.getOperand(0);
10000 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10001 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10003 // Extract the RHS vectors
10004 SDValue RHS = Op.getOperand(1);
10005 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10006 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10008 // Issue the operation on the smaller types and concatenate the result back
10009 MVT EltVT = VT.getVectorElementType();
10010 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10011 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10012 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
10013 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
10016 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
10017 const X86Subtarget *Subtarget) {
10018 SDValue Op0 = Op.getOperand(0);
10019 SDValue Op1 = Op.getOperand(1);
10020 SDValue CC = Op.getOperand(2);
10021 MVT VT = Op.getSimpleValueType();
10024 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
10025 Op.getValueType().getScalarType() == MVT::i1 &&
10026 "Cannot set masked compare for this operation");
10028 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10030 bool Unsigned = false;
10033 switch (SetCCOpcode) {
10034 default: llvm_unreachable("Unexpected SETCC condition");
10035 case ISD::SETNE: SSECC = 4; break;
10036 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
10037 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
10038 case ISD::SETLT: Swap = true; //fall-through
10039 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
10040 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
10041 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
10042 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
10043 case ISD::SETULE: Unsigned = true; //fall-through
10044 case ISD::SETLE: SSECC = 2; break;
10048 std::swap(Op0, Op1);
10050 return DAG.getNode(Opc, dl, VT, Op0, Op1);
10051 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
10052 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10053 DAG.getConstant(SSECC, MVT::i8));
10056 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
10057 SelectionDAG &DAG) {
10058 SDValue Op0 = Op.getOperand(0);
10059 SDValue Op1 = Op.getOperand(1);
10060 SDValue CC = Op.getOperand(2);
10061 MVT VT = Op.getSimpleValueType();
10062 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10063 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10068 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10069 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10072 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10073 unsigned Opc = X86ISD::CMPP;
10074 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10075 assert(VT.getVectorNumElements() <= 16);
10076 Opc = X86ISD::CMPM;
10078 // In the two special cases we can't handle, emit two comparisons.
10081 unsigned CombineOpc;
10082 if (SetCCOpcode == ISD::SETUEQ) {
10083 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10085 assert(SetCCOpcode == ISD::SETONE);
10086 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10089 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10090 DAG.getConstant(CC0, MVT::i8));
10091 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10092 DAG.getConstant(CC1, MVT::i8));
10093 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10095 // Handle all other FP comparisons here.
10096 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10097 DAG.getConstant(SSECC, MVT::i8));
10100 // Break 256-bit integer vector compare into smaller ones.
10101 if (VT.is256BitVector() && !Subtarget->hasInt256())
10102 return Lower256IntVSETCC(Op, DAG);
10104 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10105 EVT OpVT = Op1.getValueType();
10106 if (Subtarget->hasAVX512()) {
10107 if (Op1.getValueType().is512BitVector() ||
10108 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10109 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
10111 // In AVX-512 architecture setcc returns mask with i1 elements,
10112 // But there is no compare instruction for i8 and i16 elements.
10113 // We are not talking about 512-bit operands in this case, these
10114 // types are illegal.
10116 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10117 OpVT.getVectorElementType().getSizeInBits() >= 8))
10118 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10119 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10122 // We are handling one of the integer comparisons here. Since SSE only has
10123 // GT and EQ comparisons for integer, swapping operands and multiple
10124 // operations may be required for some comparisons.
10126 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10128 switch (SetCCOpcode) {
10129 default: llvm_unreachable("Unexpected SETCC condition");
10130 case ISD::SETNE: Invert = true;
10131 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
10132 case ISD::SETLT: Swap = true;
10133 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
10134 case ISD::SETGE: Swap = true;
10135 case ISD::SETLE: Opc = X86ISD::PCMPGT;
10136 Invert = true; break;
10137 case ISD::SETULT: Swap = true;
10138 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
10139 FlipSigns = true; break;
10140 case ISD::SETUGE: Swap = true;
10141 case ISD::SETULE: Opc = X86ISD::PCMPGT;
10142 FlipSigns = true; Invert = true; break;
10145 // Special case: Use min/max operations for SETULE/SETUGE
10146 MVT VET = VT.getVectorElementType();
10148 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10149 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10152 switch (SetCCOpcode) {
10154 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10155 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10158 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10162 std::swap(Op0, Op1);
10164 // Check that the operation in question is available (most are plain SSE2,
10165 // but PCMPGTQ and PCMPEQQ have different requirements).
10166 if (VT == MVT::v2i64) {
10167 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10168 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10170 // First cast everything to the right type.
10171 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10172 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10174 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10175 // bits of the inputs before performing those operations. The lower
10176 // compare is always unsigned.
10179 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10181 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10182 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10183 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10184 Sign, Zero, Sign, Zero);
10186 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10187 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10189 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10190 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10191 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10193 // Create masks for only the low parts/high parts of the 64 bit integers.
10194 static const int MaskHi[] = { 1, 1, 3, 3 };
10195 static const int MaskLo[] = { 0, 0, 2, 2 };
10196 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10197 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10198 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10200 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10201 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10204 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10206 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10209 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10210 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10211 // pcmpeqd + pshufd + pand.
10212 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10214 // First cast everything to the right type.
10215 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10216 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10219 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10221 // Make sure the lower and upper halves are both all-ones.
10222 static const int Mask[] = { 1, 0, 3, 2 };
10223 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10224 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10227 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10229 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10233 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10234 // bits of the inputs before performing those operations.
10236 EVT EltVT = VT.getVectorElementType();
10237 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10238 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10239 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10242 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10244 // If the logical-not of the result is required, perform that now.
10246 Result = DAG.getNOT(dl, Result, VT);
10249 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10254 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10256 MVT VT = Op.getSimpleValueType();
10258 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10260 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10261 && "SetCC type must be 8-bit or 1-bit integer");
10262 SDValue Op0 = Op.getOperand(0);
10263 SDValue Op1 = Op.getOperand(1);
10265 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10267 // Optimize to BT if possible.
10268 // Lower (X & (1 << N)) == 0 to BT(X, N).
10269 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10270 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10271 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10272 Op1.getOpcode() == ISD::Constant &&
10273 cast<ConstantSDNode>(Op1)->isNullValue() &&
10274 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10275 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10276 if (NewSetCC.getNode())
10280 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10282 if (Op1.getOpcode() == ISD::Constant &&
10283 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10284 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10285 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10287 // If the input is a setcc, then reuse the input setcc or use a new one with
10288 // the inverted condition.
10289 if (Op0.getOpcode() == X86ISD::SETCC) {
10290 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10291 bool Invert = (CC == ISD::SETNE) ^
10292 cast<ConstantSDNode>(Op1)->isNullValue();
10296 CCode = X86::GetOppositeBranchCondition(CCode);
10297 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10298 DAG.getConstant(CCode, MVT::i8),
10299 Op0.getOperand(1));
10301 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10306 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10307 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10308 if (X86CC == X86::COND_INVALID)
10311 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10312 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10313 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10314 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10316 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10320 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10321 static bool isX86LogicalCmp(SDValue Op) {
10322 unsigned Opc = Op.getNode()->getOpcode();
10323 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10324 Opc == X86ISD::SAHF)
10326 if (Op.getResNo() == 1 &&
10327 (Opc == X86ISD::ADD ||
10328 Opc == X86ISD::SUB ||
10329 Opc == X86ISD::ADC ||
10330 Opc == X86ISD::SBB ||
10331 Opc == X86ISD::SMUL ||
10332 Opc == X86ISD::UMUL ||
10333 Opc == X86ISD::INC ||
10334 Opc == X86ISD::DEC ||
10335 Opc == X86ISD::OR ||
10336 Opc == X86ISD::XOR ||
10337 Opc == X86ISD::AND))
10340 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10346 static bool isZero(SDValue V) {
10347 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10348 return C && C->isNullValue();
10351 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10352 if (V.getOpcode() != ISD::TRUNCATE)
10355 SDValue VOp0 = V.getOperand(0);
10356 unsigned InBits = VOp0.getValueSizeInBits();
10357 unsigned Bits = V.getValueSizeInBits();
10358 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10361 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10362 bool addTest = true;
10363 SDValue Cond = Op.getOperand(0);
10364 SDValue Op1 = Op.getOperand(1);
10365 SDValue Op2 = Op.getOperand(2);
10367 EVT VT = Op1.getValueType();
10370 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10371 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10372 // sequence later on.
10373 if (Cond.getOpcode() == ISD::SETCC &&
10374 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10375 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10376 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10377 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10378 int SSECC = translateX86FSETCC(
10379 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10382 if (Subtarget->hasAVX512()) {
10383 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10384 DAG.getConstant(SSECC, MVT::i8));
10385 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10387 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10388 DAG.getConstant(SSECC, MVT::i8));
10389 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10390 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10391 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10395 if (Cond.getOpcode() == ISD::SETCC) {
10396 SDValue NewCond = LowerSETCC(Cond, DAG);
10397 if (NewCond.getNode())
10401 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10402 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10403 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10404 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10405 if (Cond.getOpcode() == X86ISD::SETCC &&
10406 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10407 isZero(Cond.getOperand(1).getOperand(1))) {
10408 SDValue Cmp = Cond.getOperand(1);
10410 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10412 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10413 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10414 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10416 SDValue CmpOp0 = Cmp.getOperand(0);
10417 // Apply further optimizations for special cases
10418 // (select (x != 0), -1, 0) -> neg & sbb
10419 // (select (x == 0), 0, -1) -> neg & sbb
10420 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10421 if (YC->isNullValue() &&
10422 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10423 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10424 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10425 DAG.getConstant(0, CmpOp0.getValueType()),
10427 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10428 DAG.getConstant(X86::COND_B, MVT::i8),
10429 SDValue(Neg.getNode(), 1));
10433 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10434 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10435 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10437 SDValue Res = // Res = 0 or -1.
10438 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10439 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10441 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10442 Res = DAG.getNOT(DL, Res, Res.getValueType());
10444 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10445 if (N2C == 0 || !N2C->isNullValue())
10446 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10451 // Look past (and (setcc_carry (cmp ...)), 1).
10452 if (Cond.getOpcode() == ISD::AND &&
10453 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10454 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10455 if (C && C->getAPIntValue() == 1)
10456 Cond = Cond.getOperand(0);
10459 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10460 // setting operand in place of the X86ISD::SETCC.
10461 unsigned CondOpcode = Cond.getOpcode();
10462 if (CondOpcode == X86ISD::SETCC ||
10463 CondOpcode == X86ISD::SETCC_CARRY) {
10464 CC = Cond.getOperand(0);
10466 SDValue Cmp = Cond.getOperand(1);
10467 unsigned Opc = Cmp.getOpcode();
10468 MVT VT = Op.getSimpleValueType();
10470 bool IllegalFPCMov = false;
10471 if (VT.isFloatingPoint() && !VT.isVector() &&
10472 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10473 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10475 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10476 Opc == X86ISD::BT) { // FIXME
10480 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10481 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10482 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10483 Cond.getOperand(0).getValueType() != MVT::i8)) {
10484 SDValue LHS = Cond.getOperand(0);
10485 SDValue RHS = Cond.getOperand(1);
10486 unsigned X86Opcode;
10489 switch (CondOpcode) {
10490 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10491 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10492 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10493 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10494 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10495 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10496 default: llvm_unreachable("unexpected overflowing operator");
10498 if (CondOpcode == ISD::UMULO)
10499 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10502 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10504 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10506 if (CondOpcode == ISD::UMULO)
10507 Cond = X86Op.getValue(2);
10509 Cond = X86Op.getValue(1);
10511 CC = DAG.getConstant(X86Cond, MVT::i8);
10516 // Look pass the truncate if the high bits are known zero.
10517 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10518 Cond = Cond.getOperand(0);
10520 // We know the result of AND is compared against zero. Try to match
10522 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10523 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10524 if (NewSetCC.getNode()) {
10525 CC = NewSetCC.getOperand(0);
10526 Cond = NewSetCC.getOperand(1);
10533 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10534 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10537 // a < b ? -1 : 0 -> RES = ~setcc_carry
10538 // a < b ? 0 : -1 -> RES = setcc_carry
10539 // a >= b ? -1 : 0 -> RES = setcc_carry
10540 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10541 if (Cond.getOpcode() == X86ISD::SUB) {
10542 Cond = ConvertCmpIfNecessary(Cond, DAG);
10543 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10545 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10546 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10547 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10548 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10549 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10550 return DAG.getNOT(DL, Res, Res.getValueType());
10555 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10556 // widen the cmov and push the truncate through. This avoids introducing a new
10557 // branch during isel and doesn't add any extensions.
10558 if (Op.getValueType() == MVT::i8 &&
10559 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10560 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10561 if (T1.getValueType() == T2.getValueType() &&
10562 // Blacklist CopyFromReg to avoid partial register stalls.
10563 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10564 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10565 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10566 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10570 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10571 // condition is true.
10572 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10573 SDValue Ops[] = { Op2, Op1, CC, Cond };
10574 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10577 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10578 MVT VT = Op->getSimpleValueType(0);
10579 SDValue In = Op->getOperand(0);
10580 MVT InVT = In.getSimpleValueType();
10583 unsigned int NumElts = VT.getVectorNumElements();
10584 if (NumElts != 8 && NumElts != 16)
10587 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10588 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10590 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10591 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10593 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10594 Constant *C = ConstantInt::get(*DAG.getContext(),
10595 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10597 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10598 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10599 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10600 MachinePointerInfo::getConstantPool(),
10601 false, false, false, Alignment);
10602 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10603 if (VT.is512BitVector())
10605 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10608 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10609 SelectionDAG &DAG) {
10610 MVT VT = Op->getSimpleValueType(0);
10611 SDValue In = Op->getOperand(0);
10612 MVT InVT = In.getSimpleValueType();
10615 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10616 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10618 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10619 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10620 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10623 if (Subtarget->hasInt256())
10624 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10626 // Optimize vectors in AVX mode
10627 // Sign extend v8i16 to v8i32 and
10630 // Divide input vector into two parts
10631 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10632 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10633 // concat the vectors to original VT
10635 unsigned NumElems = InVT.getVectorNumElements();
10636 SDValue Undef = DAG.getUNDEF(InVT);
10638 SmallVector<int,8> ShufMask1(NumElems, -1);
10639 for (unsigned i = 0; i != NumElems/2; ++i)
10642 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10644 SmallVector<int,8> ShufMask2(NumElems, -1);
10645 for (unsigned i = 0; i != NumElems/2; ++i)
10646 ShufMask2[i] = i + NumElems/2;
10648 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10650 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10651 VT.getVectorNumElements()/2);
10653 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
10654 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
10656 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10659 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10660 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10661 // from the AND / OR.
10662 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10663 Opc = Op.getOpcode();
10664 if (Opc != ISD::OR && Opc != ISD::AND)
10666 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10667 Op.getOperand(0).hasOneUse() &&
10668 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10669 Op.getOperand(1).hasOneUse());
10672 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10673 // 1 and that the SETCC node has a single use.
10674 static bool isXor1OfSetCC(SDValue Op) {
10675 if (Op.getOpcode() != ISD::XOR)
10677 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10678 if (N1C && N1C->getAPIntValue() == 1) {
10679 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10680 Op.getOperand(0).hasOneUse();
10685 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10686 bool addTest = true;
10687 SDValue Chain = Op.getOperand(0);
10688 SDValue Cond = Op.getOperand(1);
10689 SDValue Dest = Op.getOperand(2);
10692 bool Inverted = false;
10694 if (Cond.getOpcode() == ISD::SETCC) {
10695 // Check for setcc([su]{add,sub,mul}o == 0).
10696 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10697 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10698 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10699 Cond.getOperand(0).getResNo() == 1 &&
10700 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10701 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10702 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10703 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10704 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10705 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10707 Cond = Cond.getOperand(0);
10709 SDValue NewCond = LowerSETCC(Cond, DAG);
10710 if (NewCond.getNode())
10715 // FIXME: LowerXALUO doesn't handle these!!
10716 else if (Cond.getOpcode() == X86ISD::ADD ||
10717 Cond.getOpcode() == X86ISD::SUB ||
10718 Cond.getOpcode() == X86ISD::SMUL ||
10719 Cond.getOpcode() == X86ISD::UMUL)
10720 Cond = LowerXALUO(Cond, DAG);
10723 // Look pass (and (setcc_carry (cmp ...)), 1).
10724 if (Cond.getOpcode() == ISD::AND &&
10725 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10726 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10727 if (C && C->getAPIntValue() == 1)
10728 Cond = Cond.getOperand(0);
10731 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10732 // setting operand in place of the X86ISD::SETCC.
10733 unsigned CondOpcode = Cond.getOpcode();
10734 if (CondOpcode == X86ISD::SETCC ||
10735 CondOpcode == X86ISD::SETCC_CARRY) {
10736 CC = Cond.getOperand(0);
10738 SDValue Cmp = Cond.getOperand(1);
10739 unsigned Opc = Cmp.getOpcode();
10740 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10741 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10745 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10749 // These can only come from an arithmetic instruction with overflow,
10750 // e.g. SADDO, UADDO.
10751 Cond = Cond.getNode()->getOperand(1);
10757 CondOpcode = Cond.getOpcode();
10758 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10759 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10760 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10761 Cond.getOperand(0).getValueType() != MVT::i8)) {
10762 SDValue LHS = Cond.getOperand(0);
10763 SDValue RHS = Cond.getOperand(1);
10764 unsigned X86Opcode;
10767 // Keep this in sync with LowerXALUO, otherwise we might create redundant
10768 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
10770 switch (CondOpcode) {
10771 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10773 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10775 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
10778 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10779 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10783 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
10786 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10787 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10788 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10789 default: llvm_unreachable("unexpected overflowing operator");
10792 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10793 if (CondOpcode == ISD::UMULO)
10794 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10797 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10799 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10801 if (CondOpcode == ISD::UMULO)
10802 Cond = X86Op.getValue(2);
10804 Cond = X86Op.getValue(1);
10806 CC = DAG.getConstant(X86Cond, MVT::i8);
10810 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10811 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10812 if (CondOpc == ISD::OR) {
10813 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10814 // two branches instead of an explicit OR instruction with a
10816 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10817 isX86LogicalCmp(Cmp)) {
10818 CC = Cond.getOperand(0).getOperand(0);
10819 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10820 Chain, Dest, CC, Cmp);
10821 CC = Cond.getOperand(1).getOperand(0);
10825 } else { // ISD::AND
10826 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10827 // two branches instead of an explicit AND instruction with a
10828 // separate test. However, we only do this if this block doesn't
10829 // have a fall-through edge, because this requires an explicit
10830 // jmp when the condition is false.
10831 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10832 isX86LogicalCmp(Cmp) &&
10833 Op.getNode()->hasOneUse()) {
10834 X86::CondCode CCode =
10835 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10836 CCode = X86::GetOppositeBranchCondition(CCode);
10837 CC = DAG.getConstant(CCode, MVT::i8);
10838 SDNode *User = *Op.getNode()->use_begin();
10839 // Look for an unconditional branch following this conditional branch.
10840 // We need this because we need to reverse the successors in order
10841 // to implement FCMP_OEQ.
10842 if (User->getOpcode() == ISD::BR) {
10843 SDValue FalseBB = User->getOperand(1);
10845 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10846 assert(NewBR == User);
10850 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10851 Chain, Dest, CC, Cmp);
10852 X86::CondCode CCode =
10853 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10854 CCode = X86::GetOppositeBranchCondition(CCode);
10855 CC = DAG.getConstant(CCode, MVT::i8);
10861 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10862 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10863 // It should be transformed during dag combiner except when the condition
10864 // is set by a arithmetics with overflow node.
10865 X86::CondCode CCode =
10866 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10867 CCode = X86::GetOppositeBranchCondition(CCode);
10868 CC = DAG.getConstant(CCode, MVT::i8);
10869 Cond = Cond.getOperand(0).getOperand(1);
10871 } else if (Cond.getOpcode() == ISD::SETCC &&
10872 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10873 // For FCMP_OEQ, we can emit
10874 // two branches instead of an explicit AND instruction with a
10875 // separate test. However, we only do this if this block doesn't
10876 // have a fall-through edge, because this requires an explicit
10877 // jmp when the condition is false.
10878 if (Op.getNode()->hasOneUse()) {
10879 SDNode *User = *Op.getNode()->use_begin();
10880 // Look for an unconditional branch following this conditional branch.
10881 // We need this because we need to reverse the successors in order
10882 // to implement FCMP_OEQ.
10883 if (User->getOpcode() == ISD::BR) {
10884 SDValue FalseBB = User->getOperand(1);
10886 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10887 assert(NewBR == User);
10891 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10892 Cond.getOperand(0), Cond.getOperand(1));
10893 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10894 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10895 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10896 Chain, Dest, CC, Cmp);
10897 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10902 } else if (Cond.getOpcode() == ISD::SETCC &&
10903 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10904 // For FCMP_UNE, we can emit
10905 // two branches instead of an explicit AND instruction with a
10906 // separate test. However, we only do this if this block doesn't
10907 // have a fall-through edge, because this requires an explicit
10908 // jmp when the condition is false.
10909 if (Op.getNode()->hasOneUse()) {
10910 SDNode *User = *Op.getNode()->use_begin();
10911 // Look for an unconditional branch following this conditional branch.
10912 // We need this because we need to reverse the successors in order
10913 // to implement FCMP_UNE.
10914 if (User->getOpcode() == ISD::BR) {
10915 SDValue FalseBB = User->getOperand(1);
10917 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10918 assert(NewBR == User);
10921 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10922 Cond.getOperand(0), Cond.getOperand(1));
10923 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10924 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10925 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10926 Chain, Dest, CC, Cmp);
10927 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10937 // Look pass the truncate if the high bits are known zero.
10938 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10939 Cond = Cond.getOperand(0);
10941 // We know the result of AND is compared against zero. Try to match
10943 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10944 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10945 if (NewSetCC.getNode()) {
10946 CC = NewSetCC.getOperand(0);
10947 Cond = NewSetCC.getOperand(1);
10954 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10955 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10957 Cond = ConvertCmpIfNecessary(Cond, DAG);
10958 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10959 Chain, Dest, CC, Cond);
10962 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10963 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10964 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10965 // that the guard pages used by the OS virtual memory manager are allocated in
10966 // correct sequence.
10968 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10969 SelectionDAG &DAG) const {
10970 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10971 getTargetMachine().Options.EnableSegmentedStacks) &&
10972 "This should be used only on Windows targets or when segmented stacks "
10974 assert(!Subtarget->isTargetMacho() && "Not implemented");
10978 SDValue Chain = Op.getOperand(0);
10979 SDValue Size = Op.getOperand(1);
10980 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10981 EVT VT = Op.getNode()->getValueType(0);
10983 bool Is64Bit = Subtarget->is64Bit();
10984 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10986 if (getTargetMachine().Options.EnableSegmentedStacks) {
10987 MachineFunction &MF = DAG.getMachineFunction();
10988 MachineRegisterInfo &MRI = MF.getRegInfo();
10991 // The 64 bit implementation of segmented stacks needs to clobber both r10
10992 // r11. This makes it impossible to use it along with nested parameters.
10993 const Function *F = MF.getFunction();
10995 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10997 if (I->hasNestAttr())
10998 report_fatal_error("Cannot use segmented stacks with functions that "
10999 "have nested arguments.");
11002 const TargetRegisterClass *AddrRegClass =
11003 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
11004 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
11005 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
11006 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
11007 DAG.getRegister(Vreg, SPTy));
11008 SDValue Ops1[2] = { Value, Chain };
11009 return DAG.getMergeValues(Ops1, 2, dl);
11012 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
11014 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
11015 Flag = Chain.getValue(1);
11016 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11018 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
11020 const X86RegisterInfo *RegInfo =
11021 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11022 unsigned SPReg = RegInfo->getStackRegister();
11023 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
11024 Chain = SP.getValue(1);
11027 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
11028 DAG.getConstant(-(uint64_t)Align, VT));
11029 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
11032 SDValue Ops1[2] = { SP, Chain };
11033 return DAG.getMergeValues(Ops1, 2, dl);
11037 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
11038 MachineFunction &MF = DAG.getMachineFunction();
11039 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
11041 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11044 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
11045 // vastart just stores the address of the VarArgsFrameIndex slot into the
11046 // memory location argument.
11047 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11049 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
11050 MachinePointerInfo(SV), false, false, 0);
11054 // gp_offset (0 - 6 * 8)
11055 // fp_offset (48 - 48 + 8 * 16)
11056 // overflow_arg_area (point to parameters coming in memory).
11058 SmallVector<SDValue, 8> MemOps;
11059 SDValue FIN = Op.getOperand(1);
11061 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
11062 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
11064 FIN, MachinePointerInfo(SV), false, false, 0);
11065 MemOps.push_back(Store);
11068 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11069 FIN, DAG.getIntPtrConstant(4));
11070 Store = DAG.getStore(Op.getOperand(0), DL,
11071 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
11073 FIN, MachinePointerInfo(SV, 4), false, false, 0);
11074 MemOps.push_back(Store);
11076 // Store ptr to overflow_arg_area
11077 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11078 FIN, DAG.getIntPtrConstant(4));
11079 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11081 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11082 MachinePointerInfo(SV, 8),
11084 MemOps.push_back(Store);
11086 // Store ptr to reg_save_area.
11087 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11088 FIN, DAG.getIntPtrConstant(8));
11089 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11091 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11092 MachinePointerInfo(SV, 16), false, false, 0);
11093 MemOps.push_back(Store);
11094 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11095 &MemOps[0], MemOps.size());
11098 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11099 assert(Subtarget->is64Bit() &&
11100 "LowerVAARG only handles 64-bit va_arg!");
11101 assert((Subtarget->isTargetLinux() ||
11102 Subtarget->isTargetDarwin()) &&
11103 "Unhandled target in LowerVAARG");
11104 assert(Op.getNode()->getNumOperands() == 4);
11105 SDValue Chain = Op.getOperand(0);
11106 SDValue SrcPtr = Op.getOperand(1);
11107 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11108 unsigned Align = Op.getConstantOperandVal(3);
11111 EVT ArgVT = Op.getNode()->getValueType(0);
11112 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11113 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11116 // Decide which area this value should be read from.
11117 // TODO: Implement the AMD64 ABI in its entirety. This simple
11118 // selection mechanism works only for the basic types.
11119 if (ArgVT == MVT::f80) {
11120 llvm_unreachable("va_arg for f80 not yet implemented");
11121 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11122 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11123 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11124 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11126 llvm_unreachable("Unhandled argument type in LowerVAARG");
11129 if (ArgMode == 2) {
11130 // Sanity Check: Make sure using fp_offset makes sense.
11131 assert(!getTargetMachine().Options.UseSoftFloat &&
11132 !(DAG.getMachineFunction()
11133 .getFunction()->getAttributes()
11134 .hasAttribute(AttributeSet::FunctionIndex,
11135 Attribute::NoImplicitFloat)) &&
11136 Subtarget->hasSSE1());
11139 // Insert VAARG_64 node into the DAG
11140 // VAARG_64 returns two values: Variable Argument Address, Chain
11141 SmallVector<SDValue, 11> InstOps;
11142 InstOps.push_back(Chain);
11143 InstOps.push_back(SrcPtr);
11144 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11145 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11146 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11147 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11148 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11149 VTs, &InstOps[0], InstOps.size(),
11151 MachinePointerInfo(SV),
11153 /*Volatile=*/false,
11155 /*WriteMem=*/true);
11156 Chain = VAARG.getValue(1);
11158 // Load the next argument and return it
11159 return DAG.getLoad(ArgVT, dl,
11162 MachinePointerInfo(),
11163 false, false, false, 0);
11166 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11167 SelectionDAG &DAG) {
11168 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11169 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11170 SDValue Chain = Op.getOperand(0);
11171 SDValue DstPtr = Op.getOperand(1);
11172 SDValue SrcPtr = Op.getOperand(2);
11173 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11174 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11177 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11178 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11180 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11183 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11184 // amount is a constant. Takes immediate version of shift as input.
11185 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
11186 SDValue SrcOp, uint64_t ShiftAmt,
11187 SelectionDAG &DAG) {
11188 MVT ElementType = VT.getVectorElementType();
11190 // Check for ShiftAmt >= element width
11191 if (ShiftAmt >= ElementType.getSizeInBits()) {
11192 if (Opc == X86ISD::VSRAI)
11193 ShiftAmt = ElementType.getSizeInBits() - 1;
11195 return DAG.getConstant(0, VT);
11198 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11199 && "Unknown target vector shift-by-constant node");
11201 // Fold this packed vector shift into a build vector if SrcOp is a
11202 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
11203 if (VT == SrcOp.getSimpleValueType() &&
11204 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11205 SmallVector<SDValue, 8> Elts;
11206 unsigned NumElts = SrcOp->getNumOperands();
11207 ConstantSDNode *ND;
11210 default: llvm_unreachable(0);
11211 case X86ISD::VSHLI:
11212 for (unsigned i=0; i!=NumElts; ++i) {
11213 SDValue CurrentOp = SrcOp->getOperand(i);
11214 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11215 Elts.push_back(CurrentOp);
11218 ND = cast<ConstantSDNode>(CurrentOp);
11219 const APInt &C = ND->getAPIntValue();
11220 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11223 case X86ISD::VSRLI:
11224 for (unsigned i=0; i!=NumElts; ++i) {
11225 SDValue CurrentOp = SrcOp->getOperand(i);
11226 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11227 Elts.push_back(CurrentOp);
11230 ND = cast<ConstantSDNode>(CurrentOp);
11231 const APInt &C = ND->getAPIntValue();
11232 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11235 case X86ISD::VSRAI:
11236 for (unsigned i=0; i!=NumElts; ++i) {
11237 SDValue CurrentOp = SrcOp->getOperand(i);
11238 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11239 Elts.push_back(CurrentOp);
11242 ND = cast<ConstantSDNode>(CurrentOp);
11243 const APInt &C = ND->getAPIntValue();
11244 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11249 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
11252 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11255 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11256 // may or may not be a constant. Takes immediate version of shift as input.
11257 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
11258 SDValue SrcOp, SDValue ShAmt,
11259 SelectionDAG &DAG) {
11260 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11262 // Catch shift-by-constant.
11263 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11264 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11265 CShAmt->getZExtValue(), DAG);
11267 // Change opcode to non-immediate version
11269 default: llvm_unreachable("Unknown target vector shift node");
11270 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11271 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11272 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11275 // Need to build a vector containing shift amount
11276 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11279 ShOps[1] = DAG.getConstant(0, MVT::i32);
11280 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11281 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11283 // The return type has to be a 128-bit type with the same element
11284 // type as the input type.
11285 MVT EltVT = VT.getVectorElementType();
11286 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11288 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11289 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11292 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11294 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11296 default: return SDValue(); // Don't custom lower most intrinsics.
11297 // Comparison intrinsics.
11298 case Intrinsic::x86_sse_comieq_ss:
11299 case Intrinsic::x86_sse_comilt_ss:
11300 case Intrinsic::x86_sse_comile_ss:
11301 case Intrinsic::x86_sse_comigt_ss:
11302 case Intrinsic::x86_sse_comige_ss:
11303 case Intrinsic::x86_sse_comineq_ss:
11304 case Intrinsic::x86_sse_ucomieq_ss:
11305 case Intrinsic::x86_sse_ucomilt_ss:
11306 case Intrinsic::x86_sse_ucomile_ss:
11307 case Intrinsic::x86_sse_ucomigt_ss:
11308 case Intrinsic::x86_sse_ucomige_ss:
11309 case Intrinsic::x86_sse_ucomineq_ss:
11310 case Intrinsic::x86_sse2_comieq_sd:
11311 case Intrinsic::x86_sse2_comilt_sd:
11312 case Intrinsic::x86_sse2_comile_sd:
11313 case Intrinsic::x86_sse2_comigt_sd:
11314 case Intrinsic::x86_sse2_comige_sd:
11315 case Intrinsic::x86_sse2_comineq_sd:
11316 case Intrinsic::x86_sse2_ucomieq_sd:
11317 case Intrinsic::x86_sse2_ucomilt_sd:
11318 case Intrinsic::x86_sse2_ucomile_sd:
11319 case Intrinsic::x86_sse2_ucomigt_sd:
11320 case Intrinsic::x86_sse2_ucomige_sd:
11321 case Intrinsic::x86_sse2_ucomineq_sd: {
11325 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11326 case Intrinsic::x86_sse_comieq_ss:
11327 case Intrinsic::x86_sse2_comieq_sd:
11328 Opc = X86ISD::COMI;
11331 case Intrinsic::x86_sse_comilt_ss:
11332 case Intrinsic::x86_sse2_comilt_sd:
11333 Opc = X86ISD::COMI;
11336 case Intrinsic::x86_sse_comile_ss:
11337 case Intrinsic::x86_sse2_comile_sd:
11338 Opc = X86ISD::COMI;
11341 case Intrinsic::x86_sse_comigt_ss:
11342 case Intrinsic::x86_sse2_comigt_sd:
11343 Opc = X86ISD::COMI;
11346 case Intrinsic::x86_sse_comige_ss:
11347 case Intrinsic::x86_sse2_comige_sd:
11348 Opc = X86ISD::COMI;
11351 case Intrinsic::x86_sse_comineq_ss:
11352 case Intrinsic::x86_sse2_comineq_sd:
11353 Opc = X86ISD::COMI;
11356 case Intrinsic::x86_sse_ucomieq_ss:
11357 case Intrinsic::x86_sse2_ucomieq_sd:
11358 Opc = X86ISD::UCOMI;
11361 case Intrinsic::x86_sse_ucomilt_ss:
11362 case Intrinsic::x86_sse2_ucomilt_sd:
11363 Opc = X86ISD::UCOMI;
11366 case Intrinsic::x86_sse_ucomile_ss:
11367 case Intrinsic::x86_sse2_ucomile_sd:
11368 Opc = X86ISD::UCOMI;
11371 case Intrinsic::x86_sse_ucomigt_ss:
11372 case Intrinsic::x86_sse2_ucomigt_sd:
11373 Opc = X86ISD::UCOMI;
11376 case Intrinsic::x86_sse_ucomige_ss:
11377 case Intrinsic::x86_sse2_ucomige_sd:
11378 Opc = X86ISD::UCOMI;
11381 case Intrinsic::x86_sse_ucomineq_ss:
11382 case Intrinsic::x86_sse2_ucomineq_sd:
11383 Opc = X86ISD::UCOMI;
11388 SDValue LHS = Op.getOperand(1);
11389 SDValue RHS = Op.getOperand(2);
11390 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11391 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11392 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11393 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11394 DAG.getConstant(X86CC, MVT::i8), Cond);
11395 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11398 // Arithmetic intrinsics.
11399 case Intrinsic::x86_sse2_pmulu_dq:
11400 case Intrinsic::x86_avx2_pmulu_dq:
11401 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11402 Op.getOperand(1), Op.getOperand(2));
11404 // SSE2/AVX2 sub with unsigned saturation intrinsics
11405 case Intrinsic::x86_sse2_psubus_b:
11406 case Intrinsic::x86_sse2_psubus_w:
11407 case Intrinsic::x86_avx2_psubus_b:
11408 case Intrinsic::x86_avx2_psubus_w:
11409 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11410 Op.getOperand(1), Op.getOperand(2));
11412 // SSE3/AVX horizontal add/sub intrinsics
11413 case Intrinsic::x86_sse3_hadd_ps:
11414 case Intrinsic::x86_sse3_hadd_pd:
11415 case Intrinsic::x86_avx_hadd_ps_256:
11416 case Intrinsic::x86_avx_hadd_pd_256:
11417 case Intrinsic::x86_sse3_hsub_ps:
11418 case Intrinsic::x86_sse3_hsub_pd:
11419 case Intrinsic::x86_avx_hsub_ps_256:
11420 case Intrinsic::x86_avx_hsub_pd_256:
11421 case Intrinsic::x86_ssse3_phadd_w_128:
11422 case Intrinsic::x86_ssse3_phadd_d_128:
11423 case Intrinsic::x86_avx2_phadd_w:
11424 case Intrinsic::x86_avx2_phadd_d:
11425 case Intrinsic::x86_ssse3_phsub_w_128:
11426 case Intrinsic::x86_ssse3_phsub_d_128:
11427 case Intrinsic::x86_avx2_phsub_w:
11428 case Intrinsic::x86_avx2_phsub_d: {
11431 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11432 case Intrinsic::x86_sse3_hadd_ps:
11433 case Intrinsic::x86_sse3_hadd_pd:
11434 case Intrinsic::x86_avx_hadd_ps_256:
11435 case Intrinsic::x86_avx_hadd_pd_256:
11436 Opcode = X86ISD::FHADD;
11438 case Intrinsic::x86_sse3_hsub_ps:
11439 case Intrinsic::x86_sse3_hsub_pd:
11440 case Intrinsic::x86_avx_hsub_ps_256:
11441 case Intrinsic::x86_avx_hsub_pd_256:
11442 Opcode = X86ISD::FHSUB;
11444 case Intrinsic::x86_ssse3_phadd_w_128:
11445 case Intrinsic::x86_ssse3_phadd_d_128:
11446 case Intrinsic::x86_avx2_phadd_w:
11447 case Intrinsic::x86_avx2_phadd_d:
11448 Opcode = X86ISD::HADD;
11450 case Intrinsic::x86_ssse3_phsub_w_128:
11451 case Intrinsic::x86_ssse3_phsub_d_128:
11452 case Intrinsic::x86_avx2_phsub_w:
11453 case Intrinsic::x86_avx2_phsub_d:
11454 Opcode = X86ISD::HSUB;
11457 return DAG.getNode(Opcode, dl, Op.getValueType(),
11458 Op.getOperand(1), Op.getOperand(2));
11461 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11462 case Intrinsic::x86_sse2_pmaxu_b:
11463 case Intrinsic::x86_sse41_pmaxuw:
11464 case Intrinsic::x86_sse41_pmaxud:
11465 case Intrinsic::x86_avx2_pmaxu_b:
11466 case Intrinsic::x86_avx2_pmaxu_w:
11467 case Intrinsic::x86_avx2_pmaxu_d:
11468 case Intrinsic::x86_sse2_pminu_b:
11469 case Intrinsic::x86_sse41_pminuw:
11470 case Intrinsic::x86_sse41_pminud:
11471 case Intrinsic::x86_avx2_pminu_b:
11472 case Intrinsic::x86_avx2_pminu_w:
11473 case Intrinsic::x86_avx2_pminu_d:
11474 case Intrinsic::x86_sse41_pmaxsb:
11475 case Intrinsic::x86_sse2_pmaxs_w:
11476 case Intrinsic::x86_sse41_pmaxsd:
11477 case Intrinsic::x86_avx2_pmaxs_b:
11478 case Intrinsic::x86_avx2_pmaxs_w:
11479 case Intrinsic::x86_avx2_pmaxs_d:
11480 case Intrinsic::x86_sse41_pminsb:
11481 case Intrinsic::x86_sse2_pmins_w:
11482 case Intrinsic::x86_sse41_pminsd:
11483 case Intrinsic::x86_avx2_pmins_b:
11484 case Intrinsic::x86_avx2_pmins_w:
11485 case Intrinsic::x86_avx2_pmins_d: {
11488 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11489 case Intrinsic::x86_sse2_pmaxu_b:
11490 case Intrinsic::x86_sse41_pmaxuw:
11491 case Intrinsic::x86_sse41_pmaxud:
11492 case Intrinsic::x86_avx2_pmaxu_b:
11493 case Intrinsic::x86_avx2_pmaxu_w:
11494 case Intrinsic::x86_avx2_pmaxu_d:
11495 Opcode = X86ISD::UMAX;
11497 case Intrinsic::x86_sse2_pminu_b:
11498 case Intrinsic::x86_sse41_pminuw:
11499 case Intrinsic::x86_sse41_pminud:
11500 case Intrinsic::x86_avx2_pminu_b:
11501 case Intrinsic::x86_avx2_pminu_w:
11502 case Intrinsic::x86_avx2_pminu_d:
11503 Opcode = X86ISD::UMIN;
11505 case Intrinsic::x86_sse41_pmaxsb:
11506 case Intrinsic::x86_sse2_pmaxs_w:
11507 case Intrinsic::x86_sse41_pmaxsd:
11508 case Intrinsic::x86_avx2_pmaxs_b:
11509 case Intrinsic::x86_avx2_pmaxs_w:
11510 case Intrinsic::x86_avx2_pmaxs_d:
11511 Opcode = X86ISD::SMAX;
11513 case Intrinsic::x86_sse41_pminsb:
11514 case Intrinsic::x86_sse2_pmins_w:
11515 case Intrinsic::x86_sse41_pminsd:
11516 case Intrinsic::x86_avx2_pmins_b:
11517 case Intrinsic::x86_avx2_pmins_w:
11518 case Intrinsic::x86_avx2_pmins_d:
11519 Opcode = X86ISD::SMIN;
11522 return DAG.getNode(Opcode, dl, Op.getValueType(),
11523 Op.getOperand(1), Op.getOperand(2));
11526 // SSE/SSE2/AVX floating point max/min intrinsics.
11527 case Intrinsic::x86_sse_max_ps:
11528 case Intrinsic::x86_sse2_max_pd:
11529 case Intrinsic::x86_avx_max_ps_256:
11530 case Intrinsic::x86_avx_max_pd_256:
11531 case Intrinsic::x86_sse_min_ps:
11532 case Intrinsic::x86_sse2_min_pd:
11533 case Intrinsic::x86_avx_min_ps_256:
11534 case Intrinsic::x86_avx_min_pd_256: {
11537 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11538 case Intrinsic::x86_sse_max_ps:
11539 case Intrinsic::x86_sse2_max_pd:
11540 case Intrinsic::x86_avx_max_ps_256:
11541 case Intrinsic::x86_avx_max_pd_256:
11542 Opcode = X86ISD::FMAX;
11544 case Intrinsic::x86_sse_min_ps:
11545 case Intrinsic::x86_sse2_min_pd:
11546 case Intrinsic::x86_avx_min_ps_256:
11547 case Intrinsic::x86_avx_min_pd_256:
11548 Opcode = X86ISD::FMIN;
11551 return DAG.getNode(Opcode, dl, Op.getValueType(),
11552 Op.getOperand(1), Op.getOperand(2));
11555 // AVX2 variable shift intrinsics
11556 case Intrinsic::x86_avx2_psllv_d:
11557 case Intrinsic::x86_avx2_psllv_q:
11558 case Intrinsic::x86_avx2_psllv_d_256:
11559 case Intrinsic::x86_avx2_psllv_q_256:
11560 case Intrinsic::x86_avx2_psrlv_d:
11561 case Intrinsic::x86_avx2_psrlv_q:
11562 case Intrinsic::x86_avx2_psrlv_d_256:
11563 case Intrinsic::x86_avx2_psrlv_q_256:
11564 case Intrinsic::x86_avx2_psrav_d:
11565 case Intrinsic::x86_avx2_psrav_d_256: {
11568 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11569 case Intrinsic::x86_avx2_psllv_d:
11570 case Intrinsic::x86_avx2_psllv_q:
11571 case Intrinsic::x86_avx2_psllv_d_256:
11572 case Intrinsic::x86_avx2_psllv_q_256:
11575 case Intrinsic::x86_avx2_psrlv_d:
11576 case Intrinsic::x86_avx2_psrlv_q:
11577 case Intrinsic::x86_avx2_psrlv_d_256:
11578 case Intrinsic::x86_avx2_psrlv_q_256:
11581 case Intrinsic::x86_avx2_psrav_d:
11582 case Intrinsic::x86_avx2_psrav_d_256:
11586 return DAG.getNode(Opcode, dl, Op.getValueType(),
11587 Op.getOperand(1), Op.getOperand(2));
11590 case Intrinsic::x86_ssse3_pshuf_b_128:
11591 case Intrinsic::x86_avx2_pshuf_b:
11592 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11593 Op.getOperand(1), Op.getOperand(2));
11595 case Intrinsic::x86_ssse3_psign_b_128:
11596 case Intrinsic::x86_ssse3_psign_w_128:
11597 case Intrinsic::x86_ssse3_psign_d_128:
11598 case Intrinsic::x86_avx2_psign_b:
11599 case Intrinsic::x86_avx2_psign_w:
11600 case Intrinsic::x86_avx2_psign_d:
11601 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11602 Op.getOperand(1), Op.getOperand(2));
11604 case Intrinsic::x86_sse41_insertps:
11605 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11606 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11608 case Intrinsic::x86_avx_vperm2f128_ps_256:
11609 case Intrinsic::x86_avx_vperm2f128_pd_256:
11610 case Intrinsic::x86_avx_vperm2f128_si_256:
11611 case Intrinsic::x86_avx2_vperm2i128:
11612 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11613 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11615 case Intrinsic::x86_avx2_permd:
11616 case Intrinsic::x86_avx2_permps:
11617 // Operands intentionally swapped. Mask is last operand to intrinsic,
11618 // but second operand for node/instruction.
11619 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11620 Op.getOperand(2), Op.getOperand(1));
11622 case Intrinsic::x86_sse_sqrt_ps:
11623 case Intrinsic::x86_sse2_sqrt_pd:
11624 case Intrinsic::x86_avx_sqrt_ps_256:
11625 case Intrinsic::x86_avx_sqrt_pd_256:
11626 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11628 // ptest and testp intrinsics. The intrinsic these come from are designed to
11629 // return an integer value, not just an instruction so lower it to the ptest
11630 // or testp pattern and a setcc for the result.
11631 case Intrinsic::x86_sse41_ptestz:
11632 case Intrinsic::x86_sse41_ptestc:
11633 case Intrinsic::x86_sse41_ptestnzc:
11634 case Intrinsic::x86_avx_ptestz_256:
11635 case Intrinsic::x86_avx_ptestc_256:
11636 case Intrinsic::x86_avx_ptestnzc_256:
11637 case Intrinsic::x86_avx_vtestz_ps:
11638 case Intrinsic::x86_avx_vtestc_ps:
11639 case Intrinsic::x86_avx_vtestnzc_ps:
11640 case Intrinsic::x86_avx_vtestz_pd:
11641 case Intrinsic::x86_avx_vtestc_pd:
11642 case Intrinsic::x86_avx_vtestnzc_pd:
11643 case Intrinsic::x86_avx_vtestz_ps_256:
11644 case Intrinsic::x86_avx_vtestc_ps_256:
11645 case Intrinsic::x86_avx_vtestnzc_ps_256:
11646 case Intrinsic::x86_avx_vtestz_pd_256:
11647 case Intrinsic::x86_avx_vtestc_pd_256:
11648 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11649 bool IsTestPacked = false;
11652 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11653 case Intrinsic::x86_avx_vtestz_ps:
11654 case Intrinsic::x86_avx_vtestz_pd:
11655 case Intrinsic::x86_avx_vtestz_ps_256:
11656 case Intrinsic::x86_avx_vtestz_pd_256:
11657 IsTestPacked = true; // Fallthrough
11658 case Intrinsic::x86_sse41_ptestz:
11659 case Intrinsic::x86_avx_ptestz_256:
11661 X86CC = X86::COND_E;
11663 case Intrinsic::x86_avx_vtestc_ps:
11664 case Intrinsic::x86_avx_vtestc_pd:
11665 case Intrinsic::x86_avx_vtestc_ps_256:
11666 case Intrinsic::x86_avx_vtestc_pd_256:
11667 IsTestPacked = true; // Fallthrough
11668 case Intrinsic::x86_sse41_ptestc:
11669 case Intrinsic::x86_avx_ptestc_256:
11671 X86CC = X86::COND_B;
11673 case Intrinsic::x86_avx_vtestnzc_ps:
11674 case Intrinsic::x86_avx_vtestnzc_pd:
11675 case Intrinsic::x86_avx_vtestnzc_ps_256:
11676 case Intrinsic::x86_avx_vtestnzc_pd_256:
11677 IsTestPacked = true; // Fallthrough
11678 case Intrinsic::x86_sse41_ptestnzc:
11679 case Intrinsic::x86_avx_ptestnzc_256:
11681 X86CC = X86::COND_A;
11685 SDValue LHS = Op.getOperand(1);
11686 SDValue RHS = Op.getOperand(2);
11687 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11688 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11689 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11690 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11691 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11693 case Intrinsic::x86_avx512_kortestz_w:
11694 case Intrinsic::x86_avx512_kortestc_w: {
11695 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11696 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11697 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11698 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11699 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11700 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
11701 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11704 // SSE/AVX shift intrinsics
11705 case Intrinsic::x86_sse2_psll_w:
11706 case Intrinsic::x86_sse2_psll_d:
11707 case Intrinsic::x86_sse2_psll_q:
11708 case Intrinsic::x86_avx2_psll_w:
11709 case Intrinsic::x86_avx2_psll_d:
11710 case Intrinsic::x86_avx2_psll_q:
11711 case Intrinsic::x86_sse2_psrl_w:
11712 case Intrinsic::x86_sse2_psrl_d:
11713 case Intrinsic::x86_sse2_psrl_q:
11714 case Intrinsic::x86_avx2_psrl_w:
11715 case Intrinsic::x86_avx2_psrl_d:
11716 case Intrinsic::x86_avx2_psrl_q:
11717 case Intrinsic::x86_sse2_psra_w:
11718 case Intrinsic::x86_sse2_psra_d:
11719 case Intrinsic::x86_avx2_psra_w:
11720 case Intrinsic::x86_avx2_psra_d: {
11723 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11724 case Intrinsic::x86_sse2_psll_w:
11725 case Intrinsic::x86_sse2_psll_d:
11726 case Intrinsic::x86_sse2_psll_q:
11727 case Intrinsic::x86_avx2_psll_w:
11728 case Intrinsic::x86_avx2_psll_d:
11729 case Intrinsic::x86_avx2_psll_q:
11730 Opcode = X86ISD::VSHL;
11732 case Intrinsic::x86_sse2_psrl_w:
11733 case Intrinsic::x86_sse2_psrl_d:
11734 case Intrinsic::x86_sse2_psrl_q:
11735 case Intrinsic::x86_avx2_psrl_w:
11736 case Intrinsic::x86_avx2_psrl_d:
11737 case Intrinsic::x86_avx2_psrl_q:
11738 Opcode = X86ISD::VSRL;
11740 case Intrinsic::x86_sse2_psra_w:
11741 case Intrinsic::x86_sse2_psra_d:
11742 case Intrinsic::x86_avx2_psra_w:
11743 case Intrinsic::x86_avx2_psra_d:
11744 Opcode = X86ISD::VSRA;
11747 return DAG.getNode(Opcode, dl, Op.getValueType(),
11748 Op.getOperand(1), Op.getOperand(2));
11751 // SSE/AVX immediate shift intrinsics
11752 case Intrinsic::x86_sse2_pslli_w:
11753 case Intrinsic::x86_sse2_pslli_d:
11754 case Intrinsic::x86_sse2_pslli_q:
11755 case Intrinsic::x86_avx2_pslli_w:
11756 case Intrinsic::x86_avx2_pslli_d:
11757 case Intrinsic::x86_avx2_pslli_q:
11758 case Intrinsic::x86_sse2_psrli_w:
11759 case Intrinsic::x86_sse2_psrli_d:
11760 case Intrinsic::x86_sse2_psrli_q:
11761 case Intrinsic::x86_avx2_psrli_w:
11762 case Intrinsic::x86_avx2_psrli_d:
11763 case Intrinsic::x86_avx2_psrli_q:
11764 case Intrinsic::x86_sse2_psrai_w:
11765 case Intrinsic::x86_sse2_psrai_d:
11766 case Intrinsic::x86_avx2_psrai_w:
11767 case Intrinsic::x86_avx2_psrai_d: {
11770 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11771 case Intrinsic::x86_sse2_pslli_w:
11772 case Intrinsic::x86_sse2_pslli_d:
11773 case Intrinsic::x86_sse2_pslli_q:
11774 case Intrinsic::x86_avx2_pslli_w:
11775 case Intrinsic::x86_avx2_pslli_d:
11776 case Intrinsic::x86_avx2_pslli_q:
11777 Opcode = X86ISD::VSHLI;
11779 case Intrinsic::x86_sse2_psrli_w:
11780 case Intrinsic::x86_sse2_psrli_d:
11781 case Intrinsic::x86_sse2_psrli_q:
11782 case Intrinsic::x86_avx2_psrli_w:
11783 case Intrinsic::x86_avx2_psrli_d:
11784 case Intrinsic::x86_avx2_psrli_q:
11785 Opcode = X86ISD::VSRLI;
11787 case Intrinsic::x86_sse2_psrai_w:
11788 case Intrinsic::x86_sse2_psrai_d:
11789 case Intrinsic::x86_avx2_psrai_w:
11790 case Intrinsic::x86_avx2_psrai_d:
11791 Opcode = X86ISD::VSRAI;
11794 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
11795 Op.getOperand(1), Op.getOperand(2), DAG);
11798 case Intrinsic::x86_sse42_pcmpistria128:
11799 case Intrinsic::x86_sse42_pcmpestria128:
11800 case Intrinsic::x86_sse42_pcmpistric128:
11801 case Intrinsic::x86_sse42_pcmpestric128:
11802 case Intrinsic::x86_sse42_pcmpistrio128:
11803 case Intrinsic::x86_sse42_pcmpestrio128:
11804 case Intrinsic::x86_sse42_pcmpistris128:
11805 case Intrinsic::x86_sse42_pcmpestris128:
11806 case Intrinsic::x86_sse42_pcmpistriz128:
11807 case Intrinsic::x86_sse42_pcmpestriz128: {
11811 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11812 case Intrinsic::x86_sse42_pcmpistria128:
11813 Opcode = X86ISD::PCMPISTRI;
11814 X86CC = X86::COND_A;
11816 case Intrinsic::x86_sse42_pcmpestria128:
11817 Opcode = X86ISD::PCMPESTRI;
11818 X86CC = X86::COND_A;
11820 case Intrinsic::x86_sse42_pcmpistric128:
11821 Opcode = X86ISD::PCMPISTRI;
11822 X86CC = X86::COND_B;
11824 case Intrinsic::x86_sse42_pcmpestric128:
11825 Opcode = X86ISD::PCMPESTRI;
11826 X86CC = X86::COND_B;
11828 case Intrinsic::x86_sse42_pcmpistrio128:
11829 Opcode = X86ISD::PCMPISTRI;
11830 X86CC = X86::COND_O;
11832 case Intrinsic::x86_sse42_pcmpestrio128:
11833 Opcode = X86ISD::PCMPESTRI;
11834 X86CC = X86::COND_O;
11836 case Intrinsic::x86_sse42_pcmpistris128:
11837 Opcode = X86ISD::PCMPISTRI;
11838 X86CC = X86::COND_S;
11840 case Intrinsic::x86_sse42_pcmpestris128:
11841 Opcode = X86ISD::PCMPESTRI;
11842 X86CC = X86::COND_S;
11844 case Intrinsic::x86_sse42_pcmpistriz128:
11845 Opcode = X86ISD::PCMPISTRI;
11846 X86CC = X86::COND_E;
11848 case Intrinsic::x86_sse42_pcmpestriz128:
11849 Opcode = X86ISD::PCMPESTRI;
11850 X86CC = X86::COND_E;
11853 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11854 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11855 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11856 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11857 DAG.getConstant(X86CC, MVT::i8),
11858 SDValue(PCMP.getNode(), 1));
11859 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11862 case Intrinsic::x86_sse42_pcmpistri128:
11863 case Intrinsic::x86_sse42_pcmpestri128: {
11865 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11866 Opcode = X86ISD::PCMPISTRI;
11868 Opcode = X86ISD::PCMPESTRI;
11870 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11871 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11872 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11874 case Intrinsic::x86_fma_vfmadd_ps:
11875 case Intrinsic::x86_fma_vfmadd_pd:
11876 case Intrinsic::x86_fma_vfmsub_ps:
11877 case Intrinsic::x86_fma_vfmsub_pd:
11878 case Intrinsic::x86_fma_vfnmadd_ps:
11879 case Intrinsic::x86_fma_vfnmadd_pd:
11880 case Intrinsic::x86_fma_vfnmsub_ps:
11881 case Intrinsic::x86_fma_vfnmsub_pd:
11882 case Intrinsic::x86_fma_vfmaddsub_ps:
11883 case Intrinsic::x86_fma_vfmaddsub_pd:
11884 case Intrinsic::x86_fma_vfmsubadd_ps:
11885 case Intrinsic::x86_fma_vfmsubadd_pd:
11886 case Intrinsic::x86_fma_vfmadd_ps_256:
11887 case Intrinsic::x86_fma_vfmadd_pd_256:
11888 case Intrinsic::x86_fma_vfmsub_ps_256:
11889 case Intrinsic::x86_fma_vfmsub_pd_256:
11890 case Intrinsic::x86_fma_vfnmadd_ps_256:
11891 case Intrinsic::x86_fma_vfnmadd_pd_256:
11892 case Intrinsic::x86_fma_vfnmsub_ps_256:
11893 case Intrinsic::x86_fma_vfnmsub_pd_256:
11894 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11895 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11896 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11897 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11898 case Intrinsic::x86_fma_vfmadd_ps_512:
11899 case Intrinsic::x86_fma_vfmadd_pd_512:
11900 case Intrinsic::x86_fma_vfmsub_ps_512:
11901 case Intrinsic::x86_fma_vfmsub_pd_512:
11902 case Intrinsic::x86_fma_vfnmadd_ps_512:
11903 case Intrinsic::x86_fma_vfnmadd_pd_512:
11904 case Intrinsic::x86_fma_vfnmsub_ps_512:
11905 case Intrinsic::x86_fma_vfnmsub_pd_512:
11906 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11907 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11908 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11909 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11912 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11913 case Intrinsic::x86_fma_vfmadd_ps:
11914 case Intrinsic::x86_fma_vfmadd_pd:
11915 case Intrinsic::x86_fma_vfmadd_ps_256:
11916 case Intrinsic::x86_fma_vfmadd_pd_256:
11917 case Intrinsic::x86_fma_vfmadd_ps_512:
11918 case Intrinsic::x86_fma_vfmadd_pd_512:
11919 Opc = X86ISD::FMADD;
11921 case Intrinsic::x86_fma_vfmsub_ps:
11922 case Intrinsic::x86_fma_vfmsub_pd:
11923 case Intrinsic::x86_fma_vfmsub_ps_256:
11924 case Intrinsic::x86_fma_vfmsub_pd_256:
11925 case Intrinsic::x86_fma_vfmsub_ps_512:
11926 case Intrinsic::x86_fma_vfmsub_pd_512:
11927 Opc = X86ISD::FMSUB;
11929 case Intrinsic::x86_fma_vfnmadd_ps:
11930 case Intrinsic::x86_fma_vfnmadd_pd:
11931 case Intrinsic::x86_fma_vfnmadd_ps_256:
11932 case Intrinsic::x86_fma_vfnmadd_pd_256:
11933 case Intrinsic::x86_fma_vfnmadd_ps_512:
11934 case Intrinsic::x86_fma_vfnmadd_pd_512:
11935 Opc = X86ISD::FNMADD;
11937 case Intrinsic::x86_fma_vfnmsub_ps:
11938 case Intrinsic::x86_fma_vfnmsub_pd:
11939 case Intrinsic::x86_fma_vfnmsub_ps_256:
11940 case Intrinsic::x86_fma_vfnmsub_pd_256:
11941 case Intrinsic::x86_fma_vfnmsub_ps_512:
11942 case Intrinsic::x86_fma_vfnmsub_pd_512:
11943 Opc = X86ISD::FNMSUB;
11945 case Intrinsic::x86_fma_vfmaddsub_ps:
11946 case Intrinsic::x86_fma_vfmaddsub_pd:
11947 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11948 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11949 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11950 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11951 Opc = X86ISD::FMADDSUB;
11953 case Intrinsic::x86_fma_vfmsubadd_ps:
11954 case Intrinsic::x86_fma_vfmsubadd_pd:
11955 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11956 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11957 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11958 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11959 Opc = X86ISD::FMSUBADD;
11963 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11964 Op.getOperand(2), Op.getOperand(3));
11969 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11970 SDValue Base, SDValue Index,
11971 SDValue ScaleOp, SDValue Chain,
11972 const X86Subtarget * Subtarget) {
11974 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11975 assert(C && "Invalid scale type");
11976 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11977 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11978 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11979 Index.getSimpleValueType().getVectorNumElements());
11980 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11981 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11982 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11983 SDValue Segment = DAG.getRegister(0, MVT::i32);
11984 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11985 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11986 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11987 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11990 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11991 SDValue Src, SDValue Mask, SDValue Base,
11992 SDValue Index, SDValue ScaleOp, SDValue Chain,
11993 const X86Subtarget * Subtarget) {
11995 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11996 assert(C && "Invalid scale type");
11997 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11998 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11999 Index.getSimpleValueType().getVectorNumElements());
12000 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12001 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
12002 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12003 SDValue Segment = DAG.getRegister(0, MVT::i32);
12004 if (Src.getOpcode() == ISD::UNDEF)
12005 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
12006 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12007 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12008 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12009 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
12012 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12013 SDValue Src, SDValue Base, SDValue Index,
12014 SDValue ScaleOp, SDValue Chain) {
12016 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12017 assert(C && "Invalid scale type");
12018 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12019 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12020 SDValue Segment = DAG.getRegister(0, MVT::i32);
12021 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12022 Index.getSimpleValueType().getVectorNumElements());
12023 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
12024 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12025 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12026 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12027 return SDValue(Res, 1);
12030 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12031 SDValue Src, SDValue Mask, SDValue Base,
12032 SDValue Index, SDValue ScaleOp, SDValue Chain) {
12034 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12035 assert(C && "Invalid scale type");
12036 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12037 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12038 SDValue Segment = DAG.getRegister(0, MVT::i32);
12039 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12040 Index.getSimpleValueType().getVectorNumElements());
12041 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12042 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12043 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12044 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12045 return SDValue(Res, 1);
12048 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
12049 SelectionDAG &DAG) {
12051 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12053 default: return SDValue(); // Don't custom lower most intrinsics.
12055 // RDRAND/RDSEED intrinsics.
12056 case Intrinsic::x86_rdrand_16:
12057 case Intrinsic::x86_rdrand_32:
12058 case Intrinsic::x86_rdrand_64:
12059 case Intrinsic::x86_rdseed_16:
12060 case Intrinsic::x86_rdseed_32:
12061 case Intrinsic::x86_rdseed_64: {
12062 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
12063 IntNo == Intrinsic::x86_rdseed_32 ||
12064 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
12066 // Emit the node with the right value type.
12067 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12068 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
12070 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12071 // Otherwise return the value from Rand, which is always 0, casted to i32.
12072 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12073 DAG.getConstant(1, Op->getValueType(1)),
12074 DAG.getConstant(X86::COND_B, MVT::i32),
12075 SDValue(Result.getNode(), 1) };
12076 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12077 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12078 Ops, array_lengthof(Ops));
12080 // Return { result, isValid, chain }.
12081 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12082 SDValue(Result.getNode(), 2));
12084 //int_gather(index, base, scale);
12085 case Intrinsic::x86_avx512_gather_qpd_512:
12086 case Intrinsic::x86_avx512_gather_qps_512:
12087 case Intrinsic::x86_avx512_gather_dpd_512:
12088 case Intrinsic::x86_avx512_gather_qpi_512:
12089 case Intrinsic::x86_avx512_gather_qpq_512:
12090 case Intrinsic::x86_avx512_gather_dpq_512:
12091 case Intrinsic::x86_avx512_gather_dps_512:
12092 case Intrinsic::x86_avx512_gather_dpi_512: {
12095 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12096 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
12097 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
12098 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
12099 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
12100 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
12101 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
12102 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
12103 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
12105 SDValue Chain = Op.getOperand(0);
12106 SDValue Index = Op.getOperand(2);
12107 SDValue Base = Op.getOperand(3);
12108 SDValue Scale = Op.getOperand(4);
12109 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
12111 //int_gather_mask(v1, mask, index, base, scale);
12112 case Intrinsic::x86_avx512_gather_qps_mask_512:
12113 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12114 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12115 case Intrinsic::x86_avx512_gather_dps_mask_512:
12116 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12117 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12118 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12119 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
12122 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12123 case Intrinsic::x86_avx512_gather_qps_mask_512:
12124 Opc = X86::VGATHERQPSZrm; break;
12125 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12126 Opc = X86::VGATHERQPDZrm; break;
12127 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12128 Opc = X86::VGATHERDPDZrm; break;
12129 case Intrinsic::x86_avx512_gather_dps_mask_512:
12130 Opc = X86::VGATHERDPSZrm; break;
12131 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12132 Opc = X86::VPGATHERQDZrm; break;
12133 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12134 Opc = X86::VPGATHERQQZrm; break;
12135 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12136 Opc = X86::VPGATHERDDZrm; break;
12137 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12138 Opc = X86::VPGATHERDQZrm; break;
12140 SDValue Chain = Op.getOperand(0);
12141 SDValue Src = Op.getOperand(2);
12142 SDValue Mask = Op.getOperand(3);
12143 SDValue Index = Op.getOperand(4);
12144 SDValue Base = Op.getOperand(5);
12145 SDValue Scale = Op.getOperand(6);
12146 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12149 //int_scatter(base, index, v1, scale);
12150 case Intrinsic::x86_avx512_scatter_qpd_512:
12151 case Intrinsic::x86_avx512_scatter_qps_512:
12152 case Intrinsic::x86_avx512_scatter_dpd_512:
12153 case Intrinsic::x86_avx512_scatter_qpi_512:
12154 case Intrinsic::x86_avx512_scatter_qpq_512:
12155 case Intrinsic::x86_avx512_scatter_dpq_512:
12156 case Intrinsic::x86_avx512_scatter_dps_512:
12157 case Intrinsic::x86_avx512_scatter_dpi_512: {
12160 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12161 case Intrinsic::x86_avx512_scatter_qpd_512:
12162 Opc = X86::VSCATTERQPDZmr; break;
12163 case Intrinsic::x86_avx512_scatter_qps_512:
12164 Opc = X86::VSCATTERQPSZmr; break;
12165 case Intrinsic::x86_avx512_scatter_dpd_512:
12166 Opc = X86::VSCATTERDPDZmr; break;
12167 case Intrinsic::x86_avx512_scatter_dps_512:
12168 Opc = X86::VSCATTERDPSZmr; break;
12169 case Intrinsic::x86_avx512_scatter_qpi_512:
12170 Opc = X86::VPSCATTERQDZmr; break;
12171 case Intrinsic::x86_avx512_scatter_qpq_512:
12172 Opc = X86::VPSCATTERQQZmr; break;
12173 case Intrinsic::x86_avx512_scatter_dpq_512:
12174 Opc = X86::VPSCATTERDQZmr; break;
12175 case Intrinsic::x86_avx512_scatter_dpi_512:
12176 Opc = X86::VPSCATTERDDZmr; break;
12178 SDValue Chain = Op.getOperand(0);
12179 SDValue Base = Op.getOperand(2);
12180 SDValue Index = Op.getOperand(3);
12181 SDValue Src = Op.getOperand(4);
12182 SDValue Scale = Op.getOperand(5);
12183 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12185 //int_scatter_mask(base, mask, index, v1, scale);
12186 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12187 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12188 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12189 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12190 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12191 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12192 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12193 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12196 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12197 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12198 Opc = X86::VSCATTERQPDZmr; break;
12199 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12200 Opc = X86::VSCATTERQPSZmr; break;
12201 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12202 Opc = X86::VSCATTERDPDZmr; break;
12203 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12204 Opc = X86::VSCATTERDPSZmr; break;
12205 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12206 Opc = X86::VPSCATTERQDZmr; break;
12207 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12208 Opc = X86::VPSCATTERQQZmr; break;
12209 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12210 Opc = X86::VPSCATTERDQZmr; break;
12211 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12212 Opc = X86::VPSCATTERDDZmr; break;
12214 SDValue Chain = Op.getOperand(0);
12215 SDValue Base = Op.getOperand(2);
12216 SDValue Mask = Op.getOperand(3);
12217 SDValue Index = Op.getOperand(4);
12218 SDValue Src = Op.getOperand(5);
12219 SDValue Scale = Op.getOperand(6);
12220 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12222 // XTEST intrinsics.
12223 case Intrinsic::x86_xtest: {
12224 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12225 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12226 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12227 DAG.getConstant(X86::COND_NE, MVT::i8),
12229 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12230 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12231 Ret, SDValue(InTrans.getNode(), 1));
12236 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12237 SelectionDAG &DAG) const {
12238 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12239 MFI->setReturnAddressIsTaken(true);
12241 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12244 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12246 EVT PtrVT = getPointerTy();
12249 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12250 const X86RegisterInfo *RegInfo =
12251 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12252 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12253 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12254 DAG.getNode(ISD::ADD, dl, PtrVT,
12255 FrameAddr, Offset),
12256 MachinePointerInfo(), false, false, false, 0);
12259 // Just load the return address.
12260 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12261 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12262 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12265 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12266 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12267 MFI->setFrameAddressIsTaken(true);
12269 EVT VT = Op.getValueType();
12270 SDLoc dl(Op); // FIXME probably not meaningful
12271 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12272 const X86RegisterInfo *RegInfo =
12273 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12274 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12275 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12276 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12277 "Invalid Frame Register!");
12278 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12280 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12281 MachinePointerInfo(),
12282 false, false, false, 0);
12286 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12287 SelectionDAG &DAG) const {
12288 const X86RegisterInfo *RegInfo =
12289 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12290 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12293 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12294 SDValue Chain = Op.getOperand(0);
12295 SDValue Offset = Op.getOperand(1);
12296 SDValue Handler = Op.getOperand(2);
12299 EVT PtrVT = getPointerTy();
12300 const X86RegisterInfo *RegInfo =
12301 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12302 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12303 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12304 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12305 "Invalid Frame Register!");
12306 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12307 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12309 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12310 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12311 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12312 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12314 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12316 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12317 DAG.getRegister(StoreAddrReg, PtrVT));
12320 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12321 SelectionDAG &DAG) const {
12323 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12324 DAG.getVTList(MVT::i32, MVT::Other),
12325 Op.getOperand(0), Op.getOperand(1));
12328 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12329 SelectionDAG &DAG) const {
12331 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12332 Op.getOperand(0), Op.getOperand(1));
12335 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12336 return Op.getOperand(0);
12339 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12340 SelectionDAG &DAG) const {
12341 SDValue Root = Op.getOperand(0);
12342 SDValue Trmp = Op.getOperand(1); // trampoline
12343 SDValue FPtr = Op.getOperand(2); // nested function
12344 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12347 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12348 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12350 if (Subtarget->is64Bit()) {
12351 SDValue OutChains[6];
12353 // Large code-model.
12354 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12355 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12357 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12358 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12360 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12362 // Load the pointer to the nested function into R11.
12363 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12364 SDValue Addr = Trmp;
12365 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12366 Addr, MachinePointerInfo(TrmpAddr),
12369 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12370 DAG.getConstant(2, MVT::i64));
12371 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12372 MachinePointerInfo(TrmpAddr, 2),
12375 // Load the 'nest' parameter value into R10.
12376 // R10 is specified in X86CallingConv.td
12377 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12378 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12379 DAG.getConstant(10, MVT::i64));
12380 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12381 Addr, MachinePointerInfo(TrmpAddr, 10),
12384 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12385 DAG.getConstant(12, MVT::i64));
12386 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12387 MachinePointerInfo(TrmpAddr, 12),
12390 // Jump to the nested function.
12391 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12392 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12393 DAG.getConstant(20, MVT::i64));
12394 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12395 Addr, MachinePointerInfo(TrmpAddr, 20),
12398 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12399 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12400 DAG.getConstant(22, MVT::i64));
12401 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12402 MachinePointerInfo(TrmpAddr, 22),
12405 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12407 const Function *Func =
12408 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12409 CallingConv::ID CC = Func->getCallingConv();
12414 llvm_unreachable("Unsupported calling convention");
12415 case CallingConv::C:
12416 case CallingConv::X86_StdCall: {
12417 // Pass 'nest' parameter in ECX.
12418 // Must be kept in sync with X86CallingConv.td
12419 NestReg = X86::ECX;
12421 // Check that ECX wasn't needed by an 'inreg' parameter.
12422 FunctionType *FTy = Func->getFunctionType();
12423 const AttributeSet &Attrs = Func->getAttributes();
12425 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12426 unsigned InRegCount = 0;
12429 for (FunctionType::param_iterator I = FTy->param_begin(),
12430 E = FTy->param_end(); I != E; ++I, ++Idx)
12431 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12432 // FIXME: should only count parameters that are lowered to integers.
12433 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12435 if (InRegCount > 2) {
12436 report_fatal_error("Nest register in use - reduce number of inreg"
12442 case CallingConv::X86_FastCall:
12443 case CallingConv::X86_ThisCall:
12444 case CallingConv::Fast:
12445 // Pass 'nest' parameter in EAX.
12446 // Must be kept in sync with X86CallingConv.td
12447 NestReg = X86::EAX;
12451 SDValue OutChains[4];
12452 SDValue Addr, Disp;
12454 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12455 DAG.getConstant(10, MVT::i32));
12456 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12458 // This is storing the opcode for MOV32ri.
12459 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12460 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12461 OutChains[0] = DAG.getStore(Root, dl,
12462 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12463 Trmp, MachinePointerInfo(TrmpAddr),
12466 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12467 DAG.getConstant(1, MVT::i32));
12468 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12469 MachinePointerInfo(TrmpAddr, 1),
12472 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12473 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12474 DAG.getConstant(5, MVT::i32));
12475 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12476 MachinePointerInfo(TrmpAddr, 5),
12479 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12480 DAG.getConstant(6, MVT::i32));
12481 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12482 MachinePointerInfo(TrmpAddr, 6),
12485 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12489 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12490 SelectionDAG &DAG) const {
12492 The rounding mode is in bits 11:10 of FPSR, and has the following
12494 00 Round to nearest
12499 FLT_ROUNDS, on the other hand, expects the following:
12506 To perform the conversion, we do:
12507 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12510 MachineFunction &MF = DAG.getMachineFunction();
12511 const TargetMachine &TM = MF.getTarget();
12512 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12513 unsigned StackAlignment = TFI.getStackAlignment();
12514 MVT VT = Op.getSimpleValueType();
12517 // Save FP Control Word to stack slot
12518 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12519 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12521 MachineMemOperand *MMO =
12522 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12523 MachineMemOperand::MOStore, 2, 2);
12525 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12526 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12527 DAG.getVTList(MVT::Other),
12528 Ops, array_lengthof(Ops), MVT::i16,
12531 // Load FP Control Word from stack slot
12532 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12533 MachinePointerInfo(), false, false, false, 0);
12535 // Transform as necessary
12537 DAG.getNode(ISD::SRL, DL, MVT::i16,
12538 DAG.getNode(ISD::AND, DL, MVT::i16,
12539 CWD, DAG.getConstant(0x800, MVT::i16)),
12540 DAG.getConstant(11, MVT::i8));
12542 DAG.getNode(ISD::SRL, DL, MVT::i16,
12543 DAG.getNode(ISD::AND, DL, MVT::i16,
12544 CWD, DAG.getConstant(0x400, MVT::i16)),
12545 DAG.getConstant(9, MVT::i8));
12548 DAG.getNode(ISD::AND, DL, MVT::i16,
12549 DAG.getNode(ISD::ADD, DL, MVT::i16,
12550 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12551 DAG.getConstant(1, MVT::i16)),
12552 DAG.getConstant(3, MVT::i16));
12554 return DAG.getNode((VT.getSizeInBits() < 16 ?
12555 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12558 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12559 MVT VT = Op.getSimpleValueType();
12561 unsigned NumBits = VT.getSizeInBits();
12564 Op = Op.getOperand(0);
12565 if (VT == MVT::i8) {
12566 // Zero extend to i32 since there is not an i8 bsr.
12568 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12571 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12572 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12573 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12575 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12578 DAG.getConstant(NumBits+NumBits-1, OpVT),
12579 DAG.getConstant(X86::COND_E, MVT::i8),
12582 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12584 // Finally xor with NumBits-1.
12585 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12588 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12592 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12593 MVT VT = Op.getSimpleValueType();
12595 unsigned NumBits = VT.getSizeInBits();
12598 Op = Op.getOperand(0);
12599 if (VT == MVT::i8) {
12600 // Zero extend to i32 since there is not an i8 bsr.
12602 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12605 // Issue a bsr (scan bits in reverse).
12606 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12607 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12609 // And xor with NumBits-1.
12610 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12613 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12617 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12618 MVT VT = Op.getSimpleValueType();
12619 unsigned NumBits = VT.getSizeInBits();
12621 Op = Op.getOperand(0);
12623 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12624 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12625 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12627 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12630 DAG.getConstant(NumBits, VT),
12631 DAG.getConstant(X86::COND_E, MVT::i8),
12634 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12637 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12638 // ones, and then concatenate the result back.
12639 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12640 MVT VT = Op.getSimpleValueType();
12642 assert(VT.is256BitVector() && VT.isInteger() &&
12643 "Unsupported value type for operation");
12645 unsigned NumElems = VT.getVectorNumElements();
12648 // Extract the LHS vectors
12649 SDValue LHS = Op.getOperand(0);
12650 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12651 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12653 // Extract the RHS vectors
12654 SDValue RHS = Op.getOperand(1);
12655 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12656 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12658 MVT EltVT = VT.getVectorElementType();
12659 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12661 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12662 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12663 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12666 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12667 assert(Op.getSimpleValueType().is256BitVector() &&
12668 Op.getSimpleValueType().isInteger() &&
12669 "Only handle AVX 256-bit vector integer operation");
12670 return Lower256IntArith(Op, DAG);
12673 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12674 assert(Op.getSimpleValueType().is256BitVector() &&
12675 Op.getSimpleValueType().isInteger() &&
12676 "Only handle AVX 256-bit vector integer operation");
12677 return Lower256IntArith(Op, DAG);
12680 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12681 SelectionDAG &DAG) {
12683 MVT VT = Op.getSimpleValueType();
12685 // Decompose 256-bit ops into smaller 128-bit ops.
12686 if (VT.is256BitVector() && !Subtarget->hasInt256())
12687 return Lower256IntArith(Op, DAG);
12689 SDValue A = Op.getOperand(0);
12690 SDValue B = Op.getOperand(1);
12692 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12693 if (VT == MVT::v4i32) {
12694 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12695 "Should not custom lower when pmuldq is available!");
12697 // Extract the odd parts.
12698 static const int UnpackMask[] = { 1, -1, 3, -1 };
12699 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12700 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12702 // Multiply the even parts.
12703 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12704 // Now multiply odd parts.
12705 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12707 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12708 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12710 // Merge the two vectors back together with a shuffle. This expands into 2
12712 static const int ShufMask[] = { 0, 4, 2, 6 };
12713 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12716 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12717 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12719 // Ahi = psrlqi(a, 32);
12720 // Bhi = psrlqi(b, 32);
12722 // AloBlo = pmuludq(a, b);
12723 // AloBhi = pmuludq(a, Bhi);
12724 // AhiBlo = pmuludq(Ahi, b);
12726 // AloBhi = psllqi(AloBhi, 32);
12727 // AhiBlo = psllqi(AhiBlo, 32);
12728 // return AloBlo + AloBhi + AhiBlo;
12730 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12731 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12733 // Bit cast to 32-bit vectors for MULUDQ
12734 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12735 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12736 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12737 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12738 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12739 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12741 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12742 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12743 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12745 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12746 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12748 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12749 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12752 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12753 MVT VT = Op.getSimpleValueType();
12754 MVT EltTy = VT.getVectorElementType();
12755 unsigned NumElts = VT.getVectorNumElements();
12756 SDValue N0 = Op.getOperand(0);
12759 // Lower sdiv X, pow2-const.
12760 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12764 APInt SplatValue, SplatUndef;
12765 unsigned SplatBitSize;
12767 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12769 EltTy.getSizeInBits() < SplatBitSize)
12772 if ((SplatValue != 0) &&
12773 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12774 unsigned Lg2 = SplatValue.countTrailingZeros();
12775 // Splat the sign bit.
12776 SmallVector<SDValue, 16> Sz(NumElts,
12777 DAG.getConstant(EltTy.getSizeInBits() - 1,
12779 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12780 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12782 // Add (N0 < 0) ? abs2 - 1 : 0;
12783 SmallVector<SDValue, 16> Amt(NumElts,
12784 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12786 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12787 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12789 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12790 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12791 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12792 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12795 // If we're dividing by a positive value, we're done. Otherwise, we must
12796 // negate the result.
12797 if (SplatValue.isNonNegative())
12800 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12801 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12802 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12807 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12808 const X86Subtarget *Subtarget) {
12809 MVT VT = Op.getSimpleValueType();
12811 SDValue R = Op.getOperand(0);
12812 SDValue Amt = Op.getOperand(1);
12814 // Optimize shl/srl/sra with constant shift amount.
12815 if (isSplatVector(Amt.getNode())) {
12816 SDValue SclrAmt = Amt->getOperand(0);
12817 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12818 uint64_t ShiftAmt = C->getZExtValue();
12820 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12821 (Subtarget->hasInt256() &&
12822 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12823 (Subtarget->hasAVX512() &&
12824 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12825 if (Op.getOpcode() == ISD::SHL)
12826 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12828 if (Op.getOpcode() == ISD::SRL)
12829 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12831 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12832 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12836 if (VT == MVT::v16i8) {
12837 if (Op.getOpcode() == ISD::SHL) {
12838 // Make a large shift.
12839 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12840 MVT::v8i16, R, ShiftAmt,
12842 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12843 // Zero out the rightmost bits.
12844 SmallVector<SDValue, 16> V(16,
12845 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12847 return DAG.getNode(ISD::AND, dl, VT, SHL,
12848 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12850 if (Op.getOpcode() == ISD::SRL) {
12851 // Make a large shift.
12852 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12853 MVT::v8i16, R, ShiftAmt,
12855 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12856 // Zero out the leftmost bits.
12857 SmallVector<SDValue, 16> V(16,
12858 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12860 return DAG.getNode(ISD::AND, dl, VT, SRL,
12861 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12863 if (Op.getOpcode() == ISD::SRA) {
12864 if (ShiftAmt == 7) {
12865 // R s>> 7 === R s< 0
12866 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12867 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12870 // R s>> a === ((R u>> a) ^ m) - m
12871 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12872 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12874 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12875 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12876 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12879 llvm_unreachable("Unknown shift opcode.");
12882 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12883 if (Op.getOpcode() == ISD::SHL) {
12884 // Make a large shift.
12885 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12886 MVT::v16i16, R, ShiftAmt,
12888 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12889 // Zero out the rightmost bits.
12890 SmallVector<SDValue, 32> V(32,
12891 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12893 return DAG.getNode(ISD::AND, dl, VT, SHL,
12894 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12896 if (Op.getOpcode() == ISD::SRL) {
12897 // Make a large shift.
12898 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12899 MVT::v16i16, R, ShiftAmt,
12901 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12902 // Zero out the leftmost bits.
12903 SmallVector<SDValue, 32> V(32,
12904 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12906 return DAG.getNode(ISD::AND, dl, VT, SRL,
12907 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12909 if (Op.getOpcode() == ISD::SRA) {
12910 if (ShiftAmt == 7) {
12911 // R s>> 7 === R s< 0
12912 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12913 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12916 // R s>> a === ((R u>> a) ^ m) - m
12917 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12918 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12920 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12921 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12922 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12925 llvm_unreachable("Unknown shift opcode.");
12930 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12931 if (!Subtarget->is64Bit() &&
12932 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12933 Amt.getOpcode() == ISD::BITCAST &&
12934 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12935 Amt = Amt.getOperand(0);
12936 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
12937 VT.getVectorNumElements();
12938 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12939 uint64_t ShiftAmt = 0;
12940 for (unsigned i = 0; i != Ratio; ++i) {
12941 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12945 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12947 // Check remaining shift amounts.
12948 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12949 uint64_t ShAmt = 0;
12950 for (unsigned j = 0; j != Ratio; ++j) {
12951 ConstantSDNode *C =
12952 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12956 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12958 if (ShAmt != ShiftAmt)
12961 switch (Op.getOpcode()) {
12963 llvm_unreachable("Unknown shift opcode!");
12965 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12968 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12971 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12979 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12980 const X86Subtarget* Subtarget) {
12981 MVT VT = Op.getSimpleValueType();
12983 SDValue R = Op.getOperand(0);
12984 SDValue Amt = Op.getOperand(1);
12986 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12987 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12988 (Subtarget->hasInt256() &&
12989 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12990 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12991 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12993 EVT EltVT = VT.getVectorElementType();
12995 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12996 unsigned NumElts = VT.getVectorNumElements();
12998 for (i = 0; i != NumElts; ++i) {
12999 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
13003 for (j = i; j != NumElts; ++j) {
13004 SDValue Arg = Amt.getOperand(j);
13005 if (Arg.getOpcode() == ISD::UNDEF) continue;
13006 if (Arg != Amt.getOperand(i))
13009 if (i != NumElts && j == NumElts)
13010 BaseShAmt = Amt.getOperand(i);
13012 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
13013 Amt = Amt.getOperand(0);
13014 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
13015 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
13016 SDValue InVec = Amt.getOperand(0);
13017 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13018 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13020 for (; i != NumElts; ++i) {
13021 SDValue Arg = InVec.getOperand(i);
13022 if (Arg.getOpcode() == ISD::UNDEF) continue;
13026 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13027 if (ConstantSDNode *C =
13028 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13029 unsigned SplatIdx =
13030 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
13031 if (C->getZExtValue() == SplatIdx)
13032 BaseShAmt = InVec.getOperand(1);
13035 if (BaseShAmt.getNode() == 0)
13036 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
13037 DAG.getIntPtrConstant(0));
13041 if (BaseShAmt.getNode()) {
13042 if (EltVT.bitsGT(MVT::i32))
13043 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
13044 else if (EltVT.bitsLT(MVT::i32))
13045 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
13047 switch (Op.getOpcode()) {
13049 llvm_unreachable("Unknown shift opcode!");
13051 switch (VT.SimpleTy) {
13052 default: return SDValue();
13061 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13064 switch (VT.SimpleTy) {
13065 default: return SDValue();
13072 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13075 switch (VT.SimpleTy) {
13076 default: return SDValue();
13085 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13091 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13092 if (!Subtarget->is64Bit() &&
13093 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13094 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13095 Amt.getOpcode() == ISD::BITCAST &&
13096 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13097 Amt = Amt.getOperand(0);
13098 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13099 VT.getVectorNumElements();
13100 std::vector<SDValue> Vals(Ratio);
13101 for (unsigned i = 0; i != Ratio; ++i)
13102 Vals[i] = Amt.getOperand(i);
13103 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13104 for (unsigned j = 0; j != Ratio; ++j)
13105 if (Vals[j] != Amt.getOperand(i + j))
13108 switch (Op.getOpcode()) {
13110 llvm_unreachable("Unknown shift opcode!");
13112 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13114 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13116 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13123 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13124 SelectionDAG &DAG) {
13126 MVT VT = Op.getSimpleValueType();
13128 SDValue R = Op.getOperand(0);
13129 SDValue Amt = Op.getOperand(1);
13132 if (!Subtarget->hasSSE2())
13135 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13139 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13143 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13145 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13146 if (Subtarget->hasInt256()) {
13147 if (Op.getOpcode() == ISD::SRL &&
13148 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13149 VT == MVT::v4i64 || VT == MVT::v8i32))
13151 if (Op.getOpcode() == ISD::SHL &&
13152 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13153 VT == MVT::v4i64 || VT == MVT::v8i32))
13155 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13159 // Lower SHL with variable shift amount.
13160 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13161 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13163 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13164 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13165 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13166 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13168 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13169 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13172 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13173 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13175 // Turn 'a' into a mask suitable for VSELECT
13176 SDValue VSelM = DAG.getConstant(0x80, VT);
13177 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13178 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13180 SDValue CM1 = DAG.getConstant(0x0f, VT);
13181 SDValue CM2 = DAG.getConstant(0x3f, VT);
13183 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13184 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13185 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13186 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13187 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13190 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13191 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13192 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13194 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13195 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13196 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13197 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13198 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13201 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13202 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13203 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13205 // return VSELECT(r, r+r, a);
13206 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13207 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13211 // Decompose 256-bit shifts into smaller 128-bit shifts.
13212 if (VT.is256BitVector()) {
13213 unsigned NumElems = VT.getVectorNumElements();
13214 MVT EltVT = VT.getVectorElementType();
13215 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13217 // Extract the two vectors
13218 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13219 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13221 // Recreate the shift amount vectors
13222 SDValue Amt1, Amt2;
13223 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13224 // Constant shift amount
13225 SmallVector<SDValue, 4> Amt1Csts;
13226 SmallVector<SDValue, 4> Amt2Csts;
13227 for (unsigned i = 0; i != NumElems/2; ++i)
13228 Amt1Csts.push_back(Amt->getOperand(i));
13229 for (unsigned i = NumElems/2; i != NumElems; ++i)
13230 Amt2Csts.push_back(Amt->getOperand(i));
13232 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13233 &Amt1Csts[0], NumElems/2);
13234 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13235 &Amt2Csts[0], NumElems/2);
13237 // Variable shift amount
13238 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13239 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13242 // Issue new vector shifts for the smaller types
13243 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13244 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13246 // Concatenate the result back
13247 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13253 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13254 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13255 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13256 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13257 // has only one use.
13258 SDNode *N = Op.getNode();
13259 SDValue LHS = N->getOperand(0);
13260 SDValue RHS = N->getOperand(1);
13261 unsigned BaseOp = 0;
13264 switch (Op.getOpcode()) {
13265 default: llvm_unreachable("Unknown ovf instruction!");
13267 // A subtract of one will be selected as a INC. Note that INC doesn't
13268 // set CF, so we can't do this for UADDO.
13269 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13271 BaseOp = X86ISD::INC;
13272 Cond = X86::COND_O;
13275 BaseOp = X86ISD::ADD;
13276 Cond = X86::COND_O;
13279 BaseOp = X86ISD::ADD;
13280 Cond = X86::COND_B;
13283 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13284 // set CF, so we can't do this for USUBO.
13285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13287 BaseOp = X86ISD::DEC;
13288 Cond = X86::COND_O;
13291 BaseOp = X86ISD::SUB;
13292 Cond = X86::COND_O;
13295 BaseOp = X86ISD::SUB;
13296 Cond = X86::COND_B;
13299 BaseOp = X86ISD::SMUL;
13300 Cond = X86::COND_O;
13302 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13303 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13305 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13308 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13309 DAG.getConstant(X86::COND_O, MVT::i32),
13310 SDValue(Sum.getNode(), 2));
13312 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13316 // Also sets EFLAGS.
13317 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13318 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13321 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13322 DAG.getConstant(Cond, MVT::i32),
13323 SDValue(Sum.getNode(), 1));
13325 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13328 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13329 SelectionDAG &DAG) const {
13331 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13332 MVT VT = Op.getSimpleValueType();
13334 if (!Subtarget->hasSSE2() || !VT.isVector())
13337 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13338 ExtraVT.getScalarType().getSizeInBits();
13340 switch (VT.SimpleTy) {
13341 default: return SDValue();
13344 if (!Subtarget->hasFp256())
13346 if (!Subtarget->hasInt256()) {
13347 // needs to be split
13348 unsigned NumElems = VT.getVectorNumElements();
13350 // Extract the LHS vectors
13351 SDValue LHS = Op.getOperand(0);
13352 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13353 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13355 MVT EltVT = VT.getVectorElementType();
13356 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13358 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13359 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13360 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13362 SDValue Extra = DAG.getValueType(ExtraVT);
13364 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13365 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13367 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13372 SDValue Op0 = Op.getOperand(0);
13373 SDValue Op00 = Op0.getOperand(0);
13375 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13376 if (Op0.getOpcode() == ISD::BITCAST &&
13377 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13378 // (sext (vzext x)) -> (vsext x)
13379 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13380 if (Tmp1.getNode()) {
13381 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13382 // This folding is only valid when the in-reg type is a vector of i8,
13384 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13385 ExtraEltVT == MVT::i32) {
13386 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13387 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13388 "This optimization is invalid without a VZEXT.");
13389 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13395 // If the above didn't work, then just use Shift-Left + Shift-Right.
13396 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13398 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13404 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13405 SelectionDAG &DAG) {
13407 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13408 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13409 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13410 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13412 // The only fence that needs an instruction is a sequentially-consistent
13413 // cross-thread fence.
13414 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13415 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13416 // no-sse2). There isn't any reason to disable it if the target processor
13418 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13419 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13421 SDValue Chain = Op.getOperand(0);
13422 SDValue Zero = DAG.getConstant(0, MVT::i32);
13424 DAG.getRegister(X86::ESP, MVT::i32), // Base
13425 DAG.getTargetConstant(1, MVT::i8), // Scale
13426 DAG.getRegister(0, MVT::i32), // Index
13427 DAG.getTargetConstant(0, MVT::i32), // Disp
13428 DAG.getRegister(0, MVT::i32), // Segment.
13432 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13433 return SDValue(Res, 0);
13436 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13437 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13440 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13441 SelectionDAG &DAG) {
13442 MVT T = Op.getSimpleValueType();
13446 switch(T.SimpleTy) {
13447 default: llvm_unreachable("Invalid value type!");
13448 case MVT::i8: Reg = X86::AL; size = 1; break;
13449 case MVT::i16: Reg = X86::AX; size = 2; break;
13450 case MVT::i32: Reg = X86::EAX; size = 4; break;
13452 assert(Subtarget->is64Bit() && "Node not type legal!");
13453 Reg = X86::RAX; size = 8;
13456 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13457 Op.getOperand(2), SDValue());
13458 SDValue Ops[] = { cpIn.getValue(0),
13461 DAG.getTargetConstant(size, MVT::i8),
13462 cpIn.getValue(1) };
13463 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13464 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13465 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13466 Ops, array_lengthof(Ops), T, MMO);
13468 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13472 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13473 SelectionDAG &DAG) {
13474 assert(Subtarget->is64Bit() && "Result not type legalized?");
13475 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13476 SDValue TheChain = Op.getOperand(0);
13478 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13479 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13480 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13482 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13483 DAG.getConstant(32, MVT::i8));
13485 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13488 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13491 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13492 SelectionDAG &DAG) {
13493 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13494 MVT DstVT = Op.getSimpleValueType();
13495 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13496 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13497 assert((DstVT == MVT::i64 ||
13498 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13499 "Unexpected custom BITCAST");
13500 // i64 <=> MMX conversions are Legal.
13501 if (SrcVT==MVT::i64 && DstVT.isVector())
13503 if (DstVT==MVT::i64 && SrcVT.isVector())
13505 // MMX <=> MMX conversions are Legal.
13506 if (SrcVT.isVector() && DstVT.isVector())
13508 // All other conversions need to be expanded.
13512 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13513 SDNode *Node = Op.getNode();
13515 EVT T = Node->getValueType(0);
13516 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13517 DAG.getConstant(0, T), Node->getOperand(2));
13518 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13519 cast<AtomicSDNode>(Node)->getMemoryVT(),
13520 Node->getOperand(0),
13521 Node->getOperand(1), negOp,
13522 cast<AtomicSDNode>(Node)->getSrcValue(),
13523 cast<AtomicSDNode>(Node)->getAlignment(),
13524 cast<AtomicSDNode>(Node)->getOrdering(),
13525 cast<AtomicSDNode>(Node)->getSynchScope());
13528 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13529 SDNode *Node = Op.getNode();
13531 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13533 // Convert seq_cst store -> xchg
13534 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13535 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13536 // (The only way to get a 16-byte store is cmpxchg16b)
13537 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13538 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13539 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13540 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13541 cast<AtomicSDNode>(Node)->getMemoryVT(),
13542 Node->getOperand(0),
13543 Node->getOperand(1), Node->getOperand(2),
13544 cast<AtomicSDNode>(Node)->getMemOperand(),
13545 cast<AtomicSDNode>(Node)->getOrdering(),
13546 cast<AtomicSDNode>(Node)->getSynchScope());
13547 return Swap.getValue(1);
13549 // Other atomic stores have a simple pattern.
13553 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13554 EVT VT = Op.getNode()->getSimpleValueType(0);
13556 // Let legalize expand this if it isn't a legal type yet.
13557 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13560 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13563 bool ExtraOp = false;
13564 switch (Op.getOpcode()) {
13565 default: llvm_unreachable("Invalid code");
13566 case ISD::ADDC: Opc = X86ISD::ADD; break;
13567 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13568 case ISD::SUBC: Opc = X86ISD::SUB; break;
13569 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13573 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13575 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13576 Op.getOperand(1), Op.getOperand(2));
13579 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13580 SelectionDAG &DAG) {
13581 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13583 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13584 // which returns the values as { float, float } (in XMM0) or
13585 // { double, double } (which is returned in XMM0, XMM1).
13587 SDValue Arg = Op.getOperand(0);
13588 EVT ArgVT = Arg.getValueType();
13589 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13591 TargetLowering::ArgListTy Args;
13592 TargetLowering::ArgListEntry Entry;
13596 Entry.isSExt = false;
13597 Entry.isZExt = false;
13598 Args.push_back(Entry);
13600 bool isF64 = ArgVT == MVT::f64;
13601 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13602 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13603 // the results are returned via SRet in memory.
13604 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13605 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13606 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13608 Type *RetTy = isF64
13609 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13610 : (Type*)VectorType::get(ArgTy, 4);
13612 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13613 false, false, false, false, 0,
13614 CallingConv::C, /*isTaillCall=*/false,
13615 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13616 Callee, Args, DAG, dl);
13617 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13620 // Returned in xmm0 and xmm1.
13621 return CallResult.first;
13623 // Returned in bits 0:31 and 32:64 xmm0.
13624 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13625 CallResult.first, DAG.getIntPtrConstant(0));
13626 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13627 CallResult.first, DAG.getIntPtrConstant(1));
13628 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13629 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13632 /// LowerOperation - Provide custom lowering hooks for some operations.
13634 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13635 switch (Op.getOpcode()) {
13636 default: llvm_unreachable("Should not custom lower this!");
13637 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13638 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13639 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13640 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13641 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13642 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13643 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13644 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13645 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13646 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13647 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13648 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13649 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13650 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13651 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13652 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13653 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13654 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13655 case ISD::SHL_PARTS:
13656 case ISD::SRA_PARTS:
13657 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13658 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13659 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13660 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13661 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13662 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13663 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13664 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13665 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13666 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13667 case ISD::FABS: return LowerFABS(Op, DAG);
13668 case ISD::FNEG: return LowerFNEG(Op, DAG);
13669 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13670 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13671 case ISD::SETCC: return LowerSETCC(Op, DAG);
13672 case ISD::SELECT: return LowerSELECT(Op, DAG);
13673 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13674 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13675 case ISD::VASTART: return LowerVASTART(Op, DAG);
13676 case ISD::VAARG: return LowerVAARG(Op, DAG);
13677 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13678 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13679 case ISD::INTRINSIC_VOID:
13680 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13681 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13682 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13683 case ISD::FRAME_TO_ARGS_OFFSET:
13684 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13685 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13686 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13687 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13688 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13689 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13690 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13691 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13692 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13693 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13694 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13695 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13698 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13704 case ISD::UMULO: return LowerXALUO(Op, DAG);
13705 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13706 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13710 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13711 case ISD::ADD: return LowerADD(Op, DAG);
13712 case ISD::SUB: return LowerSUB(Op, DAG);
13713 case ISD::SDIV: return LowerSDIV(Op, DAG);
13714 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13718 static void ReplaceATOMIC_LOAD(SDNode *Node,
13719 SmallVectorImpl<SDValue> &Results,
13720 SelectionDAG &DAG) {
13722 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13724 // Convert wide load -> cmpxchg8b/cmpxchg16b
13725 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13726 // (The only way to get a 16-byte load is cmpxchg16b)
13727 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13728 SDValue Zero = DAG.getConstant(0, VT);
13729 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13730 Node->getOperand(0),
13731 Node->getOperand(1), Zero, Zero,
13732 cast<AtomicSDNode>(Node)->getMemOperand(),
13733 cast<AtomicSDNode>(Node)->getOrdering(),
13734 cast<AtomicSDNode>(Node)->getSynchScope());
13735 Results.push_back(Swap.getValue(0));
13736 Results.push_back(Swap.getValue(1));
13740 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13741 SelectionDAG &DAG, unsigned NewOp) {
13743 assert (Node->getValueType(0) == MVT::i64 &&
13744 "Only know how to expand i64 atomics");
13746 SDValue Chain = Node->getOperand(0);
13747 SDValue In1 = Node->getOperand(1);
13748 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13749 Node->getOperand(2), DAG.getIntPtrConstant(0));
13750 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13751 Node->getOperand(2), DAG.getIntPtrConstant(1));
13752 SDValue Ops[] = { Chain, In1, In2L, In2H };
13753 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13755 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13756 cast<MemSDNode>(Node)->getMemOperand());
13757 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13758 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13759 Results.push_back(Result.getValue(2));
13762 /// ReplaceNodeResults - Replace a node with an illegal result type
13763 /// with a new node built out of custom code.
13764 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13765 SmallVectorImpl<SDValue>&Results,
13766 SelectionDAG &DAG) const {
13768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13769 switch (N->getOpcode()) {
13771 llvm_unreachable("Do not know how to custom type legalize this operation!");
13772 case ISD::SIGN_EXTEND_INREG:
13777 // We don't want to expand or promote these.
13779 case ISD::FP_TO_SINT:
13780 case ISD::FP_TO_UINT: {
13781 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13783 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13786 std::pair<SDValue,SDValue> Vals =
13787 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13788 SDValue FIST = Vals.first, StackSlot = Vals.second;
13789 if (FIST.getNode() != 0) {
13790 EVT VT = N->getValueType(0);
13791 // Return a load from the stack slot.
13792 if (StackSlot.getNode() != 0)
13793 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13794 MachinePointerInfo(),
13795 false, false, false, 0));
13797 Results.push_back(FIST);
13801 case ISD::UINT_TO_FP: {
13802 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13803 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13804 N->getValueType(0) != MVT::v2f32)
13806 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13808 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13810 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13811 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13812 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13813 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13814 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13815 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13818 case ISD::FP_ROUND: {
13819 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13821 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13822 Results.push_back(V);
13825 case ISD::READCYCLECOUNTER: {
13826 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13827 SDValue TheChain = N->getOperand(0);
13828 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13829 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13831 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13833 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13834 SDValue Ops[] = { eax, edx };
13835 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13836 array_lengthof(Ops)));
13837 Results.push_back(edx.getValue(1));
13840 case ISD::ATOMIC_CMP_SWAP: {
13841 EVT T = N->getValueType(0);
13842 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13843 bool Regs64bit = T == MVT::i128;
13844 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13845 SDValue cpInL, cpInH;
13846 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13847 DAG.getConstant(0, HalfT));
13848 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13849 DAG.getConstant(1, HalfT));
13850 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13851 Regs64bit ? X86::RAX : X86::EAX,
13853 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13854 Regs64bit ? X86::RDX : X86::EDX,
13855 cpInH, cpInL.getValue(1));
13856 SDValue swapInL, swapInH;
13857 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13858 DAG.getConstant(0, HalfT));
13859 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13860 DAG.getConstant(1, HalfT));
13861 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13862 Regs64bit ? X86::RBX : X86::EBX,
13863 swapInL, cpInH.getValue(1));
13864 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13865 Regs64bit ? X86::RCX : X86::ECX,
13866 swapInH, swapInL.getValue(1));
13867 SDValue Ops[] = { swapInH.getValue(0),
13869 swapInH.getValue(1) };
13870 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13871 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13872 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13873 X86ISD::LCMPXCHG8_DAG;
13874 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13875 Ops, array_lengthof(Ops), T, MMO);
13876 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13877 Regs64bit ? X86::RAX : X86::EAX,
13878 HalfT, Result.getValue(1));
13879 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13880 Regs64bit ? X86::RDX : X86::EDX,
13881 HalfT, cpOutL.getValue(2));
13882 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13883 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13884 Results.push_back(cpOutH.getValue(1));
13887 case ISD::ATOMIC_LOAD_ADD:
13888 case ISD::ATOMIC_LOAD_AND:
13889 case ISD::ATOMIC_LOAD_NAND:
13890 case ISD::ATOMIC_LOAD_OR:
13891 case ISD::ATOMIC_LOAD_SUB:
13892 case ISD::ATOMIC_LOAD_XOR:
13893 case ISD::ATOMIC_LOAD_MAX:
13894 case ISD::ATOMIC_LOAD_MIN:
13895 case ISD::ATOMIC_LOAD_UMAX:
13896 case ISD::ATOMIC_LOAD_UMIN:
13897 case ISD::ATOMIC_SWAP: {
13899 switch (N->getOpcode()) {
13900 default: llvm_unreachable("Unexpected opcode");
13901 case ISD::ATOMIC_LOAD_ADD:
13902 Opc = X86ISD::ATOMADD64_DAG;
13904 case ISD::ATOMIC_LOAD_AND:
13905 Opc = X86ISD::ATOMAND64_DAG;
13907 case ISD::ATOMIC_LOAD_NAND:
13908 Opc = X86ISD::ATOMNAND64_DAG;
13910 case ISD::ATOMIC_LOAD_OR:
13911 Opc = X86ISD::ATOMOR64_DAG;
13913 case ISD::ATOMIC_LOAD_SUB:
13914 Opc = X86ISD::ATOMSUB64_DAG;
13916 case ISD::ATOMIC_LOAD_XOR:
13917 Opc = X86ISD::ATOMXOR64_DAG;
13919 case ISD::ATOMIC_LOAD_MAX:
13920 Opc = X86ISD::ATOMMAX64_DAG;
13922 case ISD::ATOMIC_LOAD_MIN:
13923 Opc = X86ISD::ATOMMIN64_DAG;
13925 case ISD::ATOMIC_LOAD_UMAX:
13926 Opc = X86ISD::ATOMUMAX64_DAG;
13928 case ISD::ATOMIC_LOAD_UMIN:
13929 Opc = X86ISD::ATOMUMIN64_DAG;
13931 case ISD::ATOMIC_SWAP:
13932 Opc = X86ISD::ATOMSWAP64_DAG;
13935 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13938 case ISD::ATOMIC_LOAD:
13939 ReplaceATOMIC_LOAD(N, Results, DAG);
13943 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13945 default: return NULL;
13946 case X86ISD::BSF: return "X86ISD::BSF";
13947 case X86ISD::BSR: return "X86ISD::BSR";
13948 case X86ISD::SHLD: return "X86ISD::SHLD";
13949 case X86ISD::SHRD: return "X86ISD::SHRD";
13950 case X86ISD::FAND: return "X86ISD::FAND";
13951 case X86ISD::FANDN: return "X86ISD::FANDN";
13952 case X86ISD::FOR: return "X86ISD::FOR";
13953 case X86ISD::FXOR: return "X86ISD::FXOR";
13954 case X86ISD::FSRL: return "X86ISD::FSRL";
13955 case X86ISD::FILD: return "X86ISD::FILD";
13956 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13957 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13958 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13959 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13960 case X86ISD::FLD: return "X86ISD::FLD";
13961 case X86ISD::FST: return "X86ISD::FST";
13962 case X86ISD::CALL: return "X86ISD::CALL";
13963 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13964 case X86ISD::BT: return "X86ISD::BT";
13965 case X86ISD::CMP: return "X86ISD::CMP";
13966 case X86ISD::COMI: return "X86ISD::COMI";
13967 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13968 case X86ISD::CMPM: return "X86ISD::CMPM";
13969 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13970 case X86ISD::SETCC: return "X86ISD::SETCC";
13971 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13972 case X86ISD::FSETCC: return "X86ISD::FSETCC";
13973 case X86ISD::CMOV: return "X86ISD::CMOV";
13974 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13975 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13976 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13977 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13978 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13979 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13980 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13981 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13982 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13983 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13984 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13985 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13986 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13987 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13988 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13989 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13990 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13991 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13992 case X86ISD::HADD: return "X86ISD::HADD";
13993 case X86ISD::HSUB: return "X86ISD::HSUB";
13994 case X86ISD::FHADD: return "X86ISD::FHADD";
13995 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13996 case X86ISD::UMAX: return "X86ISD::UMAX";
13997 case X86ISD::UMIN: return "X86ISD::UMIN";
13998 case X86ISD::SMAX: return "X86ISD::SMAX";
13999 case X86ISD::SMIN: return "X86ISD::SMIN";
14000 case X86ISD::FMAX: return "X86ISD::FMAX";
14001 case X86ISD::FMIN: return "X86ISD::FMIN";
14002 case X86ISD::FMAXC: return "X86ISD::FMAXC";
14003 case X86ISD::FMINC: return "X86ISD::FMINC";
14004 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
14005 case X86ISD::FRCP: return "X86ISD::FRCP";
14006 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
14007 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
14008 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
14009 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
14010 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
14011 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
14012 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
14013 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
14014 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
14015 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
14016 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
14017 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
14018 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
14019 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
14020 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
14021 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
14022 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
14023 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
14024 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
14025 case X86ISD::VZEXT: return "X86ISD::VZEXT";
14026 case X86ISD::VSEXT: return "X86ISD::VSEXT";
14027 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
14028 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
14029 case X86ISD::VINSERT: return "X86ISD::VINSERT";
14030 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
14031 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
14032 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
14033 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
14034 case X86ISD::VSHL: return "X86ISD::VSHL";
14035 case X86ISD::VSRL: return "X86ISD::VSRL";
14036 case X86ISD::VSRA: return "X86ISD::VSRA";
14037 case X86ISD::VSHLI: return "X86ISD::VSHLI";
14038 case X86ISD::VSRLI: return "X86ISD::VSRLI";
14039 case X86ISD::VSRAI: return "X86ISD::VSRAI";
14040 case X86ISD::CMPP: return "X86ISD::CMPP";
14041 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
14042 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
14043 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
14044 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
14045 case X86ISD::ADD: return "X86ISD::ADD";
14046 case X86ISD::SUB: return "X86ISD::SUB";
14047 case X86ISD::ADC: return "X86ISD::ADC";
14048 case X86ISD::SBB: return "X86ISD::SBB";
14049 case X86ISD::SMUL: return "X86ISD::SMUL";
14050 case X86ISD::UMUL: return "X86ISD::UMUL";
14051 case X86ISD::INC: return "X86ISD::INC";
14052 case X86ISD::DEC: return "X86ISD::DEC";
14053 case X86ISD::OR: return "X86ISD::OR";
14054 case X86ISD::XOR: return "X86ISD::XOR";
14055 case X86ISD::AND: return "X86ISD::AND";
14056 case X86ISD::BZHI: return "X86ISD::BZHI";
14057 case X86ISD::BEXTR: return "X86ISD::BEXTR";
14058 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
14059 case X86ISD::PTEST: return "X86ISD::PTEST";
14060 case X86ISD::TESTP: return "X86ISD::TESTP";
14061 case X86ISD::TESTM: return "X86ISD::TESTM";
14062 case X86ISD::TESTNM: return "X86ISD::TESTNM";
14063 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14064 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14065 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14066 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14067 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14068 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14069 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14070 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14071 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14072 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14073 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14074 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14075 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14076 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14077 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14078 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14079 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14080 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14081 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14082 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14083 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14084 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14085 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14086 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14087 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
14088 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14089 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14090 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14091 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14092 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14093 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14094 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14095 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14096 case X86ISD::SAHF: return "X86ISD::SAHF";
14097 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14098 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14099 case X86ISD::FMADD: return "X86ISD::FMADD";
14100 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14101 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14102 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14103 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14104 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14105 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14106 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14107 case X86ISD::XTEST: return "X86ISD::XTEST";
14111 // isLegalAddressingMode - Return true if the addressing mode represented
14112 // by AM is legal for this target, for a load/store of the specified type.
14113 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14115 // X86 supports extremely general addressing modes.
14116 CodeModel::Model M = getTargetMachine().getCodeModel();
14117 Reloc::Model R = getTargetMachine().getRelocationModel();
14119 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14120 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
14125 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14127 // If a reference to this global requires an extra load, we can't fold it.
14128 if (isGlobalStubReference(GVFlags))
14131 // If BaseGV requires a register for the PIC base, we cannot also have a
14132 // BaseReg specified.
14133 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14136 // If lower 4G is not available, then we must use rip-relative addressing.
14137 if ((M != CodeModel::Small || R != Reloc::Static) &&
14138 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14142 switch (AM.Scale) {
14148 // These scales always work.
14153 // These scales are formed with basereg+scalereg. Only accept if there is
14158 default: // Other stuff never works.
14165 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14166 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14168 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14169 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14170 return NumBits1 > NumBits2;
14173 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14174 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14177 if (!isTypeLegal(EVT::getEVT(Ty1)))
14180 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14182 // Assuming the caller doesn't have a zeroext or signext return parameter,
14183 // truncation all the way down to i1 is valid.
14187 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14188 return isInt<32>(Imm);
14191 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14192 // Can also use sub to handle negated immediates.
14193 return isInt<32>(Imm);
14196 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14197 if (!VT1.isInteger() || !VT2.isInteger())
14199 unsigned NumBits1 = VT1.getSizeInBits();
14200 unsigned NumBits2 = VT2.getSizeInBits();
14201 return NumBits1 > NumBits2;
14204 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14205 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14206 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14209 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14210 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14211 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14214 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14215 EVT VT1 = Val.getValueType();
14216 if (isZExtFree(VT1, VT2))
14219 if (Val.getOpcode() != ISD::LOAD)
14222 if (!VT1.isSimple() || !VT1.isInteger() ||
14223 !VT2.isSimple() || !VT2.isInteger())
14226 switch (VT1.getSimpleVT().SimpleTy) {
14231 // X86 has 8, 16, and 32-bit zero-extending loads.
14239 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14240 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14243 VT = VT.getScalarType();
14245 if (!VT.isSimple())
14248 switch (VT.getSimpleVT().SimpleTy) {
14259 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14260 // i16 instructions are longer (0x66 prefix) and potentially slower.
14261 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14264 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14265 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14266 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14267 /// are assumed to be legal.
14269 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14271 if (!VT.isSimple())
14274 MVT SVT = VT.getSimpleVT();
14276 // Very little shuffling can be done for 64-bit vectors right now.
14277 if (VT.getSizeInBits() == 64)
14280 // FIXME: pshufb, blends, shifts.
14281 return (SVT.getVectorNumElements() == 2 ||
14282 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14283 isMOVLMask(M, SVT) ||
14284 isSHUFPMask(M, SVT) ||
14285 isPSHUFDMask(M, SVT) ||
14286 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14287 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14288 isPALIGNRMask(M, SVT, Subtarget) ||
14289 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14290 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14291 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14292 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14296 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14298 if (!VT.isSimple())
14301 MVT SVT = VT.getSimpleVT();
14302 unsigned NumElts = SVT.getVectorNumElements();
14303 // FIXME: This collection of masks seems suspect.
14306 if (NumElts == 4 && SVT.is128BitVector()) {
14307 return (isMOVLMask(Mask, SVT) ||
14308 isCommutedMOVLMask(Mask, SVT, true) ||
14309 isSHUFPMask(Mask, SVT) ||
14310 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14315 //===----------------------------------------------------------------------===//
14316 // X86 Scheduler Hooks
14317 //===----------------------------------------------------------------------===//
14319 /// Utility function to emit xbegin specifying the start of an RTM region.
14320 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14321 const TargetInstrInfo *TII) {
14322 DebugLoc DL = MI->getDebugLoc();
14324 const BasicBlock *BB = MBB->getBasicBlock();
14325 MachineFunction::iterator I = MBB;
14328 // For the v = xbegin(), we generate
14339 MachineBasicBlock *thisMBB = MBB;
14340 MachineFunction *MF = MBB->getParent();
14341 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14342 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14343 MF->insert(I, mainMBB);
14344 MF->insert(I, sinkMBB);
14346 // Transfer the remainder of BB and its successor edges to sinkMBB.
14347 sinkMBB->splice(sinkMBB->begin(), MBB,
14348 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14349 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14353 // # fallthrough to mainMBB
14354 // # abortion to sinkMBB
14355 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14356 thisMBB->addSuccessor(mainMBB);
14357 thisMBB->addSuccessor(sinkMBB);
14361 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14362 mainMBB->addSuccessor(sinkMBB);
14365 // EAX is live into the sinkMBB
14366 sinkMBB->addLiveIn(X86::EAX);
14367 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14368 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14371 MI->eraseFromParent();
14375 // Get CMPXCHG opcode for the specified data type.
14376 static unsigned getCmpXChgOpcode(EVT VT) {
14377 switch (VT.getSimpleVT().SimpleTy) {
14378 case MVT::i8: return X86::LCMPXCHG8;
14379 case MVT::i16: return X86::LCMPXCHG16;
14380 case MVT::i32: return X86::LCMPXCHG32;
14381 case MVT::i64: return X86::LCMPXCHG64;
14385 llvm_unreachable("Invalid operand size!");
14388 // Get LOAD opcode for the specified data type.
14389 static unsigned getLoadOpcode(EVT VT) {
14390 switch (VT.getSimpleVT().SimpleTy) {
14391 case MVT::i8: return X86::MOV8rm;
14392 case MVT::i16: return X86::MOV16rm;
14393 case MVT::i32: return X86::MOV32rm;
14394 case MVT::i64: return X86::MOV64rm;
14398 llvm_unreachable("Invalid operand size!");
14401 // Get opcode of the non-atomic one from the specified atomic instruction.
14402 static unsigned getNonAtomicOpcode(unsigned Opc) {
14404 case X86::ATOMAND8: return X86::AND8rr;
14405 case X86::ATOMAND16: return X86::AND16rr;
14406 case X86::ATOMAND32: return X86::AND32rr;
14407 case X86::ATOMAND64: return X86::AND64rr;
14408 case X86::ATOMOR8: return X86::OR8rr;
14409 case X86::ATOMOR16: return X86::OR16rr;
14410 case X86::ATOMOR32: return X86::OR32rr;
14411 case X86::ATOMOR64: return X86::OR64rr;
14412 case X86::ATOMXOR8: return X86::XOR8rr;
14413 case X86::ATOMXOR16: return X86::XOR16rr;
14414 case X86::ATOMXOR32: return X86::XOR32rr;
14415 case X86::ATOMXOR64: return X86::XOR64rr;
14417 llvm_unreachable("Unhandled atomic-load-op opcode!");
14420 // Get opcode of the non-atomic one from the specified atomic instruction with
14422 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14423 unsigned &ExtraOpc) {
14425 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14426 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14427 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14428 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14429 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14430 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14431 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14432 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14433 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14434 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14435 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14436 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14437 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14438 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14439 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14440 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14441 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14442 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14443 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14444 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14446 llvm_unreachable("Unhandled atomic-load-op opcode!");
14449 // Get opcode of the non-atomic one from the specified atomic instruction for
14450 // 64-bit data type on 32-bit target.
14451 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14453 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14454 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14455 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14456 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14457 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14458 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14459 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14460 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14461 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14462 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14464 llvm_unreachable("Unhandled atomic-load-op opcode!");
14467 // Get opcode of the non-atomic one from the specified atomic instruction for
14468 // 64-bit data type on 32-bit target with extra opcode.
14469 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14471 unsigned &ExtraOpc) {
14473 case X86::ATOMNAND6432:
14474 ExtraOpc = X86::NOT32r;
14475 HiOpc = X86::AND32rr;
14476 return X86::AND32rr;
14478 llvm_unreachable("Unhandled atomic-load-op opcode!");
14481 // Get pseudo CMOV opcode from the specified data type.
14482 static unsigned getPseudoCMOVOpc(EVT VT) {
14483 switch (VT.getSimpleVT().SimpleTy) {
14484 case MVT::i8: return X86::CMOV_GR8;
14485 case MVT::i16: return X86::CMOV_GR16;
14486 case MVT::i32: return X86::CMOV_GR32;
14490 llvm_unreachable("Unknown CMOV opcode!");
14493 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14494 // They will be translated into a spin-loop or compare-exchange loop from
14497 // dst = atomic-fetch-op MI.addr, MI.val
14503 // t1 = LOAD MI.addr
14505 // t4 = phi(t1, t3 / loop)
14506 // t2 = OP MI.val, t4
14508 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14514 MachineBasicBlock *
14515 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14516 MachineBasicBlock *MBB) const {
14517 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14518 DebugLoc DL = MI->getDebugLoc();
14520 MachineFunction *MF = MBB->getParent();
14521 MachineRegisterInfo &MRI = MF->getRegInfo();
14523 const BasicBlock *BB = MBB->getBasicBlock();
14524 MachineFunction::iterator I = MBB;
14527 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14528 "Unexpected number of operands");
14530 assert(MI->hasOneMemOperand() &&
14531 "Expected atomic-load-op to have one memoperand");
14533 // Memory Reference
14534 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14535 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14537 unsigned DstReg, SrcReg;
14538 unsigned MemOpndSlot;
14540 unsigned CurOp = 0;
14542 DstReg = MI->getOperand(CurOp++).getReg();
14543 MemOpndSlot = CurOp;
14544 CurOp += X86::AddrNumOperands;
14545 SrcReg = MI->getOperand(CurOp++).getReg();
14547 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14548 MVT::SimpleValueType VT = *RC->vt_begin();
14549 unsigned t1 = MRI.createVirtualRegister(RC);
14550 unsigned t2 = MRI.createVirtualRegister(RC);
14551 unsigned t3 = MRI.createVirtualRegister(RC);
14552 unsigned t4 = MRI.createVirtualRegister(RC);
14553 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14555 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14556 unsigned LOADOpc = getLoadOpcode(VT);
14558 // For the atomic load-arith operator, we generate
14561 // t1 = LOAD [MI.addr]
14563 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14564 // t1 = OP MI.val, EAX
14566 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14572 MachineBasicBlock *thisMBB = MBB;
14573 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14574 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14575 MF->insert(I, mainMBB);
14576 MF->insert(I, sinkMBB);
14578 MachineInstrBuilder MIB;
14580 // Transfer the remainder of BB and its successor edges to sinkMBB.
14581 sinkMBB->splice(sinkMBB->begin(), MBB,
14582 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14583 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14586 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14587 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14588 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14590 NewMO.setIsKill(false);
14591 MIB.addOperand(NewMO);
14593 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14594 unsigned flags = (*MMOI)->getFlags();
14595 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14596 MachineMemOperand *MMO =
14597 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14598 (*MMOI)->getSize(),
14599 (*MMOI)->getBaseAlignment(),
14600 (*MMOI)->getTBAAInfo(),
14601 (*MMOI)->getRanges());
14602 MIB.addMemOperand(MMO);
14605 thisMBB->addSuccessor(mainMBB);
14608 MachineBasicBlock *origMainMBB = mainMBB;
14611 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14612 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14614 unsigned Opc = MI->getOpcode();
14617 llvm_unreachable("Unhandled atomic-load-op opcode!");
14618 case X86::ATOMAND8:
14619 case X86::ATOMAND16:
14620 case X86::ATOMAND32:
14621 case X86::ATOMAND64:
14623 case X86::ATOMOR16:
14624 case X86::ATOMOR32:
14625 case X86::ATOMOR64:
14626 case X86::ATOMXOR8:
14627 case X86::ATOMXOR16:
14628 case X86::ATOMXOR32:
14629 case X86::ATOMXOR64: {
14630 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14631 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14635 case X86::ATOMNAND8:
14636 case X86::ATOMNAND16:
14637 case X86::ATOMNAND32:
14638 case X86::ATOMNAND64: {
14639 unsigned Tmp = MRI.createVirtualRegister(RC);
14641 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14642 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14644 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14647 case X86::ATOMMAX8:
14648 case X86::ATOMMAX16:
14649 case X86::ATOMMAX32:
14650 case X86::ATOMMAX64:
14651 case X86::ATOMMIN8:
14652 case X86::ATOMMIN16:
14653 case X86::ATOMMIN32:
14654 case X86::ATOMMIN64:
14655 case X86::ATOMUMAX8:
14656 case X86::ATOMUMAX16:
14657 case X86::ATOMUMAX32:
14658 case X86::ATOMUMAX64:
14659 case X86::ATOMUMIN8:
14660 case X86::ATOMUMIN16:
14661 case X86::ATOMUMIN32:
14662 case X86::ATOMUMIN64: {
14664 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14666 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14670 if (Subtarget->hasCMov()) {
14671 if (VT != MVT::i8) {
14673 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14677 // Promote i8 to i32 to use CMOV32
14678 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14679 const TargetRegisterClass *RC32 =
14680 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14681 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14682 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14683 unsigned Tmp = MRI.createVirtualRegister(RC32);
14685 unsigned Undef = MRI.createVirtualRegister(RC32);
14686 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14688 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14691 .addImm(X86::sub_8bit);
14692 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14695 .addImm(X86::sub_8bit);
14697 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14701 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14702 .addReg(Tmp, 0, X86::sub_8bit);
14705 // Use pseudo select and lower them.
14706 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14707 "Invalid atomic-load-op transformation!");
14708 unsigned SelOpc = getPseudoCMOVOpc(VT);
14709 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14710 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14711 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14712 .addReg(SrcReg).addReg(t4)
14714 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14715 // Replace the original PHI node as mainMBB is changed after CMOV
14717 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14718 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14719 Phi->eraseFromParent();
14725 // Copy PhyReg back from virtual register.
14726 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14729 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14730 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14731 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14733 NewMO.setIsKill(false);
14734 MIB.addOperand(NewMO);
14737 MIB.setMemRefs(MMOBegin, MMOEnd);
14739 // Copy PhyReg back to virtual register.
14740 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14743 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14745 mainMBB->addSuccessor(origMainMBB);
14746 mainMBB->addSuccessor(sinkMBB);
14749 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14750 TII->get(TargetOpcode::COPY), DstReg)
14753 MI->eraseFromParent();
14757 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14758 // instructions. They will be translated into a spin-loop or compare-exchange
14762 // dst = atomic-fetch-op MI.addr, MI.val
14768 // t1L = LOAD [MI.addr + 0]
14769 // t1H = LOAD [MI.addr + 4]
14771 // t4L = phi(t1L, t3L / loop)
14772 // t4H = phi(t1H, t3H / loop)
14773 // t2L = OP MI.val.lo, t4L
14774 // t2H = OP MI.val.hi, t4H
14779 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14787 MachineBasicBlock *
14788 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14789 MachineBasicBlock *MBB) const {
14790 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14791 DebugLoc DL = MI->getDebugLoc();
14793 MachineFunction *MF = MBB->getParent();
14794 MachineRegisterInfo &MRI = MF->getRegInfo();
14796 const BasicBlock *BB = MBB->getBasicBlock();
14797 MachineFunction::iterator I = MBB;
14800 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14801 "Unexpected number of operands");
14803 assert(MI->hasOneMemOperand() &&
14804 "Expected atomic-load-op32 to have one memoperand");
14806 // Memory Reference
14807 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14808 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14810 unsigned DstLoReg, DstHiReg;
14811 unsigned SrcLoReg, SrcHiReg;
14812 unsigned MemOpndSlot;
14814 unsigned CurOp = 0;
14816 DstLoReg = MI->getOperand(CurOp++).getReg();
14817 DstHiReg = MI->getOperand(CurOp++).getReg();
14818 MemOpndSlot = CurOp;
14819 CurOp += X86::AddrNumOperands;
14820 SrcLoReg = MI->getOperand(CurOp++).getReg();
14821 SrcHiReg = MI->getOperand(CurOp++).getReg();
14823 const TargetRegisterClass *RC = &X86::GR32RegClass;
14824 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14826 unsigned t1L = MRI.createVirtualRegister(RC);
14827 unsigned t1H = MRI.createVirtualRegister(RC);
14828 unsigned t2L = MRI.createVirtualRegister(RC);
14829 unsigned t2H = MRI.createVirtualRegister(RC);
14830 unsigned t3L = MRI.createVirtualRegister(RC);
14831 unsigned t3H = MRI.createVirtualRegister(RC);
14832 unsigned t4L = MRI.createVirtualRegister(RC);
14833 unsigned t4H = MRI.createVirtualRegister(RC);
14835 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14836 unsigned LOADOpc = X86::MOV32rm;
14838 // For the atomic load-arith operator, we generate
14841 // t1L = LOAD [MI.addr + 0]
14842 // t1H = LOAD [MI.addr + 4]
14844 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14845 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14846 // t2L = OP MI.val.lo, t4L
14847 // t2H = OP MI.val.hi, t4H
14850 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14858 MachineBasicBlock *thisMBB = MBB;
14859 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14860 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14861 MF->insert(I, mainMBB);
14862 MF->insert(I, sinkMBB);
14864 MachineInstrBuilder MIB;
14866 // Transfer the remainder of BB and its successor edges to sinkMBB.
14867 sinkMBB->splice(sinkMBB->begin(), MBB,
14868 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14869 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14873 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14874 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14875 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14877 NewMO.setIsKill(false);
14878 MIB.addOperand(NewMO);
14880 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14881 unsigned flags = (*MMOI)->getFlags();
14882 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14883 MachineMemOperand *MMO =
14884 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14885 (*MMOI)->getSize(),
14886 (*MMOI)->getBaseAlignment(),
14887 (*MMOI)->getTBAAInfo(),
14888 (*MMOI)->getRanges());
14889 MIB.addMemOperand(MMO);
14891 MachineInstr *LowMI = MIB;
14894 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14895 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14896 if (i == X86::AddrDisp) {
14897 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14899 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14901 NewMO.setIsKill(false);
14902 MIB.addOperand(NewMO);
14905 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14907 thisMBB->addSuccessor(mainMBB);
14910 MachineBasicBlock *origMainMBB = mainMBB;
14913 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14914 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14915 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14916 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14918 unsigned Opc = MI->getOpcode();
14921 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14922 case X86::ATOMAND6432:
14923 case X86::ATOMOR6432:
14924 case X86::ATOMXOR6432:
14925 case X86::ATOMADD6432:
14926 case X86::ATOMSUB6432: {
14928 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14929 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14931 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14935 case X86::ATOMNAND6432: {
14936 unsigned HiOpc, NOTOpc;
14937 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14938 unsigned TmpL = MRI.createVirtualRegister(RC);
14939 unsigned TmpH = MRI.createVirtualRegister(RC);
14940 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14942 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14944 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14945 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14948 case X86::ATOMMAX6432:
14949 case X86::ATOMMIN6432:
14950 case X86::ATOMUMAX6432:
14951 case X86::ATOMUMIN6432: {
14953 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14954 unsigned cL = MRI.createVirtualRegister(RC8);
14955 unsigned cH = MRI.createVirtualRegister(RC8);
14956 unsigned cL32 = MRI.createVirtualRegister(RC);
14957 unsigned cH32 = MRI.createVirtualRegister(RC);
14958 unsigned cc = MRI.createVirtualRegister(RC);
14959 // cl := cmp src_lo, lo
14960 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14961 .addReg(SrcLoReg).addReg(t4L);
14962 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14963 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14964 // ch := cmp src_hi, hi
14965 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14966 .addReg(SrcHiReg).addReg(t4H);
14967 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14968 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14969 // cc := if (src_hi == hi) ? cl : ch;
14970 if (Subtarget->hasCMov()) {
14971 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14972 .addReg(cH32).addReg(cL32);
14974 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14975 .addReg(cH32).addReg(cL32)
14976 .addImm(X86::COND_E);
14977 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14979 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14980 if (Subtarget->hasCMov()) {
14981 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14982 .addReg(SrcLoReg).addReg(t4L);
14983 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14984 .addReg(SrcHiReg).addReg(t4H);
14986 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14987 .addReg(SrcLoReg).addReg(t4L)
14988 .addImm(X86::COND_NE);
14989 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14990 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14991 // 2nd CMOV lowering.
14992 mainMBB->addLiveIn(X86::EFLAGS);
14993 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14994 .addReg(SrcHiReg).addReg(t4H)
14995 .addImm(X86::COND_NE);
14996 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14997 // Replace the original PHI node as mainMBB is changed after CMOV
14999 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
15000 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15001 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
15002 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15003 PhiL->eraseFromParent();
15004 PhiH->eraseFromParent();
15008 case X86::ATOMSWAP6432: {
15010 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15011 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
15012 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
15017 // Copy EDX:EAX back from HiReg:LoReg
15018 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
15019 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
15020 // Copy ECX:EBX from t1H:t1L
15021 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
15022 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
15024 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
15025 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15026 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15028 NewMO.setIsKill(false);
15029 MIB.addOperand(NewMO);
15031 MIB.setMemRefs(MMOBegin, MMOEnd);
15033 // Copy EDX:EAX back to t3H:t3L
15034 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
15035 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
15037 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15039 mainMBB->addSuccessor(origMainMBB);
15040 mainMBB->addSuccessor(sinkMBB);
15043 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15044 TII->get(TargetOpcode::COPY), DstLoReg)
15046 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15047 TII->get(TargetOpcode::COPY), DstHiReg)
15050 MI->eraseFromParent();
15054 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
15055 // or XMM0_V32I8 in AVX all of this code can be replaced with that
15056 // in the .td file.
15057 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
15058 const TargetInstrInfo *TII) {
15060 switch (MI->getOpcode()) {
15061 default: llvm_unreachable("illegal opcode!");
15062 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15063 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15064 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15065 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15066 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15067 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15068 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15069 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15072 DebugLoc dl = MI->getDebugLoc();
15073 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15075 unsigned NumArgs = MI->getNumOperands();
15076 for (unsigned i = 1; i < NumArgs; ++i) {
15077 MachineOperand &Op = MI->getOperand(i);
15078 if (!(Op.isReg() && Op.isImplicit()))
15079 MIB.addOperand(Op);
15081 if (MI->hasOneMemOperand())
15082 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15084 BuildMI(*BB, MI, dl,
15085 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15086 .addReg(X86::XMM0);
15088 MI->eraseFromParent();
15092 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15093 // defs in an instruction pattern
15094 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15095 const TargetInstrInfo *TII) {
15097 switch (MI->getOpcode()) {
15098 default: llvm_unreachable("illegal opcode!");
15099 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15100 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15101 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15102 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15103 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15104 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15105 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15106 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15109 DebugLoc dl = MI->getDebugLoc();
15110 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15112 unsigned NumArgs = MI->getNumOperands(); // remove the results
15113 for (unsigned i = 1; i < NumArgs; ++i) {
15114 MachineOperand &Op = MI->getOperand(i);
15115 if (!(Op.isReg() && Op.isImplicit()))
15116 MIB.addOperand(Op);
15118 if (MI->hasOneMemOperand())
15119 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15121 BuildMI(*BB, MI, dl,
15122 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15125 MI->eraseFromParent();
15129 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15130 const TargetInstrInfo *TII,
15131 const X86Subtarget* Subtarget) {
15132 DebugLoc dl = MI->getDebugLoc();
15134 // Address into RAX/EAX, other two args into ECX, EDX.
15135 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
15136 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15137 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15138 for (int i = 0; i < X86::AddrNumOperands; ++i)
15139 MIB.addOperand(MI->getOperand(i));
15141 unsigned ValOps = X86::AddrNumOperands;
15142 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15143 .addReg(MI->getOperand(ValOps).getReg());
15144 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15145 .addReg(MI->getOperand(ValOps+1).getReg());
15147 // The instruction doesn't actually take any operands though.
15148 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15150 MI->eraseFromParent(); // The pseudo is gone now.
15154 MachineBasicBlock *
15155 X86TargetLowering::EmitVAARG64WithCustomInserter(
15157 MachineBasicBlock *MBB) const {
15158 // Emit va_arg instruction on X86-64.
15160 // Operands to this pseudo-instruction:
15161 // 0 ) Output : destination address (reg)
15162 // 1-5) Input : va_list address (addr, i64mem)
15163 // 6 ) ArgSize : Size (in bytes) of vararg type
15164 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15165 // 8 ) Align : Alignment of type
15166 // 9 ) EFLAGS (implicit-def)
15168 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15169 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15171 unsigned DestReg = MI->getOperand(0).getReg();
15172 MachineOperand &Base = MI->getOperand(1);
15173 MachineOperand &Scale = MI->getOperand(2);
15174 MachineOperand &Index = MI->getOperand(3);
15175 MachineOperand &Disp = MI->getOperand(4);
15176 MachineOperand &Segment = MI->getOperand(5);
15177 unsigned ArgSize = MI->getOperand(6).getImm();
15178 unsigned ArgMode = MI->getOperand(7).getImm();
15179 unsigned Align = MI->getOperand(8).getImm();
15181 // Memory Reference
15182 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15183 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15184 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15186 // Machine Information
15187 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15188 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15189 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15190 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15191 DebugLoc DL = MI->getDebugLoc();
15193 // struct va_list {
15196 // i64 overflow_area (address)
15197 // i64 reg_save_area (address)
15199 // sizeof(va_list) = 24
15200 // alignment(va_list) = 8
15202 unsigned TotalNumIntRegs = 6;
15203 unsigned TotalNumXMMRegs = 8;
15204 bool UseGPOffset = (ArgMode == 1);
15205 bool UseFPOffset = (ArgMode == 2);
15206 unsigned MaxOffset = TotalNumIntRegs * 8 +
15207 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15209 /* Align ArgSize to a multiple of 8 */
15210 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15211 bool NeedsAlign = (Align > 8);
15213 MachineBasicBlock *thisMBB = MBB;
15214 MachineBasicBlock *overflowMBB;
15215 MachineBasicBlock *offsetMBB;
15216 MachineBasicBlock *endMBB;
15218 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15219 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15220 unsigned OffsetReg = 0;
15222 if (!UseGPOffset && !UseFPOffset) {
15223 // If we only pull from the overflow region, we don't create a branch.
15224 // We don't need to alter control flow.
15225 OffsetDestReg = 0; // unused
15226 OverflowDestReg = DestReg;
15229 overflowMBB = thisMBB;
15232 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15233 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15234 // If not, pull from overflow_area. (branch to overflowMBB)
15239 // offsetMBB overflowMBB
15244 // Registers for the PHI in endMBB
15245 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15246 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15248 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15249 MachineFunction *MF = MBB->getParent();
15250 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15251 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15252 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15254 MachineFunction::iterator MBBIter = MBB;
15257 // Insert the new basic blocks
15258 MF->insert(MBBIter, offsetMBB);
15259 MF->insert(MBBIter, overflowMBB);
15260 MF->insert(MBBIter, endMBB);
15262 // Transfer the remainder of MBB and its successor edges to endMBB.
15263 endMBB->splice(endMBB->begin(), thisMBB,
15264 llvm::next(MachineBasicBlock::iterator(MI)),
15266 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15268 // Make offsetMBB and overflowMBB successors of thisMBB
15269 thisMBB->addSuccessor(offsetMBB);
15270 thisMBB->addSuccessor(overflowMBB);
15272 // endMBB is a successor of both offsetMBB and overflowMBB
15273 offsetMBB->addSuccessor(endMBB);
15274 overflowMBB->addSuccessor(endMBB);
15276 // Load the offset value into a register
15277 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15278 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15282 .addDisp(Disp, UseFPOffset ? 4 : 0)
15283 .addOperand(Segment)
15284 .setMemRefs(MMOBegin, MMOEnd);
15286 // Check if there is enough room left to pull this argument.
15287 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15289 .addImm(MaxOffset + 8 - ArgSizeA8);
15291 // Branch to "overflowMBB" if offset >= max
15292 // Fall through to "offsetMBB" otherwise
15293 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15294 .addMBB(overflowMBB);
15297 // In offsetMBB, emit code to use the reg_save_area.
15299 assert(OffsetReg != 0);
15301 // Read the reg_save_area address.
15302 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15303 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15308 .addOperand(Segment)
15309 .setMemRefs(MMOBegin, MMOEnd);
15311 // Zero-extend the offset
15312 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15313 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15316 .addImm(X86::sub_32bit);
15318 // Add the offset to the reg_save_area to get the final address.
15319 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15320 .addReg(OffsetReg64)
15321 .addReg(RegSaveReg);
15323 // Compute the offset for the next argument
15324 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15325 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15327 .addImm(UseFPOffset ? 16 : 8);
15329 // Store it back into the va_list.
15330 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15334 .addDisp(Disp, UseFPOffset ? 4 : 0)
15335 .addOperand(Segment)
15336 .addReg(NextOffsetReg)
15337 .setMemRefs(MMOBegin, MMOEnd);
15340 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15345 // Emit code to use overflow area
15348 // Load the overflow_area address into a register.
15349 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15350 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15355 .addOperand(Segment)
15356 .setMemRefs(MMOBegin, MMOEnd);
15358 // If we need to align it, do so. Otherwise, just copy the address
15359 // to OverflowDestReg.
15361 // Align the overflow address
15362 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15363 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15365 // aligned_addr = (addr + (align-1)) & ~(align-1)
15366 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15367 .addReg(OverflowAddrReg)
15370 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15372 .addImm(~(uint64_t)(Align-1));
15374 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15375 .addReg(OverflowAddrReg);
15378 // Compute the next overflow address after this argument.
15379 // (the overflow address should be kept 8-byte aligned)
15380 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15381 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15382 .addReg(OverflowDestReg)
15383 .addImm(ArgSizeA8);
15385 // Store the new overflow address.
15386 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15391 .addOperand(Segment)
15392 .addReg(NextAddrReg)
15393 .setMemRefs(MMOBegin, MMOEnd);
15395 // If we branched, emit the PHI to the front of endMBB.
15397 BuildMI(*endMBB, endMBB->begin(), DL,
15398 TII->get(X86::PHI), DestReg)
15399 .addReg(OffsetDestReg).addMBB(offsetMBB)
15400 .addReg(OverflowDestReg).addMBB(overflowMBB);
15403 // Erase the pseudo instruction
15404 MI->eraseFromParent();
15409 MachineBasicBlock *
15410 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15412 MachineBasicBlock *MBB) const {
15413 // Emit code to save XMM registers to the stack. The ABI says that the
15414 // number of registers to save is given in %al, so it's theoretically
15415 // possible to do an indirect jump trick to avoid saving all of them,
15416 // however this code takes a simpler approach and just executes all
15417 // of the stores if %al is non-zero. It's less code, and it's probably
15418 // easier on the hardware branch predictor, and stores aren't all that
15419 // expensive anyway.
15421 // Create the new basic blocks. One block contains all the XMM stores,
15422 // and one block is the final destination regardless of whether any
15423 // stores were performed.
15424 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15425 MachineFunction *F = MBB->getParent();
15426 MachineFunction::iterator MBBIter = MBB;
15428 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15429 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15430 F->insert(MBBIter, XMMSaveMBB);
15431 F->insert(MBBIter, EndMBB);
15433 // Transfer the remainder of MBB and its successor edges to EndMBB.
15434 EndMBB->splice(EndMBB->begin(), MBB,
15435 llvm::next(MachineBasicBlock::iterator(MI)),
15437 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15439 // The original block will now fall through to the XMM save block.
15440 MBB->addSuccessor(XMMSaveMBB);
15441 // The XMMSaveMBB will fall through to the end block.
15442 XMMSaveMBB->addSuccessor(EndMBB);
15444 // Now add the instructions.
15445 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15446 DebugLoc DL = MI->getDebugLoc();
15448 unsigned CountReg = MI->getOperand(0).getReg();
15449 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15450 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15452 if (!Subtarget->isTargetWin64()) {
15453 // If %al is 0, branch around the XMM save block.
15454 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15455 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15456 MBB->addSuccessor(EndMBB);
15459 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
15460 // that was just emitted, but clearly shouldn't be "saved".
15461 assert((MI->getNumOperands() <= 3 ||
15462 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
15463 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
15464 && "Expected last argument to be EFLAGS");
15465 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15466 // In the XMM save block, save all the XMM argument registers.
15467 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
15468 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15469 MachineMemOperand *MMO =
15470 F->getMachineMemOperand(
15471 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15472 MachineMemOperand::MOStore,
15473 /*Size=*/16, /*Align=*/16);
15474 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15475 .addFrameIndex(RegSaveFrameIndex)
15476 .addImm(/*Scale=*/1)
15477 .addReg(/*IndexReg=*/0)
15478 .addImm(/*Disp=*/Offset)
15479 .addReg(/*Segment=*/0)
15480 .addReg(MI->getOperand(i).getReg())
15481 .addMemOperand(MMO);
15484 MI->eraseFromParent(); // The pseudo instruction is gone now.
15489 // The EFLAGS operand of SelectItr might be missing a kill marker
15490 // because there were multiple uses of EFLAGS, and ISel didn't know
15491 // which to mark. Figure out whether SelectItr should have had a
15492 // kill marker, and set it if it should. Returns the correct kill
15494 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15495 MachineBasicBlock* BB,
15496 const TargetRegisterInfo* TRI) {
15497 // Scan forward through BB for a use/def of EFLAGS.
15498 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15499 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15500 const MachineInstr& mi = *miI;
15501 if (mi.readsRegister(X86::EFLAGS))
15503 if (mi.definesRegister(X86::EFLAGS))
15504 break; // Should have kill-flag - update below.
15507 // If we hit the end of the block, check whether EFLAGS is live into a
15509 if (miI == BB->end()) {
15510 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15511 sEnd = BB->succ_end();
15512 sItr != sEnd; ++sItr) {
15513 MachineBasicBlock* succ = *sItr;
15514 if (succ->isLiveIn(X86::EFLAGS))
15519 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15520 // out. SelectMI should have a kill flag on EFLAGS.
15521 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15525 MachineBasicBlock *
15526 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15527 MachineBasicBlock *BB) const {
15528 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15529 DebugLoc DL = MI->getDebugLoc();
15531 // To "insert" a SELECT_CC instruction, we actually have to insert the
15532 // diamond control-flow pattern. The incoming instruction knows the
15533 // destination vreg to set, the condition code register to branch on, the
15534 // true/false values to select between, and a branch opcode to use.
15535 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15536 MachineFunction::iterator It = BB;
15542 // cmpTY ccX, r1, r2
15544 // fallthrough --> copy0MBB
15545 MachineBasicBlock *thisMBB = BB;
15546 MachineFunction *F = BB->getParent();
15547 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15548 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15549 F->insert(It, copy0MBB);
15550 F->insert(It, sinkMBB);
15552 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15553 // live into the sink and copy blocks.
15554 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15555 if (!MI->killsRegister(X86::EFLAGS) &&
15556 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15557 copy0MBB->addLiveIn(X86::EFLAGS);
15558 sinkMBB->addLiveIn(X86::EFLAGS);
15561 // Transfer the remainder of BB and its successor edges to sinkMBB.
15562 sinkMBB->splice(sinkMBB->begin(), BB,
15563 llvm::next(MachineBasicBlock::iterator(MI)),
15565 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15567 // Add the true and fallthrough blocks as its successors.
15568 BB->addSuccessor(copy0MBB);
15569 BB->addSuccessor(sinkMBB);
15571 // Create the conditional branch instruction.
15573 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15574 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15577 // %FalseValue = ...
15578 // # fallthrough to sinkMBB
15579 copy0MBB->addSuccessor(sinkMBB);
15582 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15584 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15585 TII->get(X86::PHI), MI->getOperand(0).getReg())
15586 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15587 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15589 MI->eraseFromParent(); // The pseudo instruction is gone now.
15593 MachineBasicBlock *
15594 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15595 bool Is64Bit) const {
15596 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15597 DebugLoc DL = MI->getDebugLoc();
15598 MachineFunction *MF = BB->getParent();
15599 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15601 assert(getTargetMachine().Options.EnableSegmentedStacks);
15603 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15604 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15607 // ... [Till the alloca]
15608 // If stacklet is not large enough, jump to mallocMBB
15611 // Allocate by subtracting from RSP
15612 // Jump to continueMBB
15615 // Allocate by call to runtime
15619 // [rest of original BB]
15622 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15623 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15624 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15626 MachineRegisterInfo &MRI = MF->getRegInfo();
15627 const TargetRegisterClass *AddrRegClass =
15628 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15630 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15631 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15632 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15633 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15634 sizeVReg = MI->getOperand(1).getReg(),
15635 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15637 MachineFunction::iterator MBBIter = BB;
15640 MF->insert(MBBIter, bumpMBB);
15641 MF->insert(MBBIter, mallocMBB);
15642 MF->insert(MBBIter, continueMBB);
15644 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15645 (MachineBasicBlock::iterator(MI)), BB->end());
15646 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15648 // Add code to the main basic block to check if the stack limit has been hit,
15649 // and if so, jump to mallocMBB otherwise to bumpMBB.
15650 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15651 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15652 .addReg(tmpSPVReg).addReg(sizeVReg);
15653 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15654 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15655 .addReg(SPLimitVReg);
15656 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15658 // bumpMBB simply decreases the stack pointer, since we know the current
15659 // stacklet has enough space.
15660 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15661 .addReg(SPLimitVReg);
15662 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15663 .addReg(SPLimitVReg);
15664 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15666 // Calls into a routine in libgcc to allocate more space from the heap.
15667 const uint32_t *RegMask =
15668 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15670 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15672 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15673 .addExternalSymbol("__morestack_allocate_stack_space")
15674 .addRegMask(RegMask)
15675 .addReg(X86::RDI, RegState::Implicit)
15676 .addReg(X86::RAX, RegState::ImplicitDefine);
15678 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15680 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15681 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15682 .addExternalSymbol("__morestack_allocate_stack_space")
15683 .addRegMask(RegMask)
15684 .addReg(X86::EAX, RegState::ImplicitDefine);
15688 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15691 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15692 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15693 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15695 // Set up the CFG correctly.
15696 BB->addSuccessor(bumpMBB);
15697 BB->addSuccessor(mallocMBB);
15698 mallocMBB->addSuccessor(continueMBB);
15699 bumpMBB->addSuccessor(continueMBB);
15701 // Take care of the PHI nodes.
15702 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15703 MI->getOperand(0).getReg())
15704 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15705 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15707 // Delete the original pseudo instruction.
15708 MI->eraseFromParent();
15711 return continueMBB;
15714 MachineBasicBlock *
15715 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15716 MachineBasicBlock *BB) const {
15717 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15718 DebugLoc DL = MI->getDebugLoc();
15720 assert(!Subtarget->isTargetMacho());
15722 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15723 // non-trivial part is impdef of ESP.
15725 if (Subtarget->isTargetWin64()) {
15726 if (Subtarget->isTargetCygMing()) {
15727 // ___chkstk(Mingw64):
15728 // Clobbers R10, R11, RAX and EFLAGS.
15730 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15731 .addExternalSymbol("___chkstk")
15732 .addReg(X86::RAX, RegState::Implicit)
15733 .addReg(X86::RSP, RegState::Implicit)
15734 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15735 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15736 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15738 // __chkstk(MSVCRT): does not update stack pointer.
15739 // Clobbers R10, R11 and EFLAGS.
15740 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15741 .addExternalSymbol("__chkstk")
15742 .addReg(X86::RAX, RegState::Implicit)
15743 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15744 // RAX has the offset to be subtracted from RSP.
15745 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15750 const char *StackProbeSymbol =
15751 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15753 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15754 .addExternalSymbol(StackProbeSymbol)
15755 .addReg(X86::EAX, RegState::Implicit)
15756 .addReg(X86::ESP, RegState::Implicit)
15757 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15758 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15759 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15762 MI->eraseFromParent(); // The pseudo instruction is gone now.
15766 MachineBasicBlock *
15767 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15768 MachineBasicBlock *BB) const {
15769 // This is pretty easy. We're taking the value that we received from
15770 // our load from the relocation, sticking it in either RDI (x86-64)
15771 // or EAX and doing an indirect call. The return value will then
15772 // be in the normal return register.
15773 const X86InstrInfo *TII
15774 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15775 DebugLoc DL = MI->getDebugLoc();
15776 MachineFunction *F = BB->getParent();
15778 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15779 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15781 // Get a register mask for the lowered call.
15782 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15783 // proper register mask.
15784 const uint32_t *RegMask =
15785 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15786 if (Subtarget->is64Bit()) {
15787 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15788 TII->get(X86::MOV64rm), X86::RDI)
15790 .addImm(0).addReg(0)
15791 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15792 MI->getOperand(3).getTargetFlags())
15794 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15795 addDirectMem(MIB, X86::RDI);
15796 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15797 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15798 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15799 TII->get(X86::MOV32rm), X86::EAX)
15801 .addImm(0).addReg(0)
15802 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15803 MI->getOperand(3).getTargetFlags())
15805 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15806 addDirectMem(MIB, X86::EAX);
15807 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15809 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15810 TII->get(X86::MOV32rm), X86::EAX)
15811 .addReg(TII->getGlobalBaseReg(F))
15812 .addImm(0).addReg(0)
15813 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15814 MI->getOperand(3).getTargetFlags())
15816 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15817 addDirectMem(MIB, X86::EAX);
15818 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15821 MI->eraseFromParent(); // The pseudo instruction is gone now.
15825 MachineBasicBlock *
15826 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15827 MachineBasicBlock *MBB) const {
15828 DebugLoc DL = MI->getDebugLoc();
15829 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15831 MachineFunction *MF = MBB->getParent();
15832 MachineRegisterInfo &MRI = MF->getRegInfo();
15834 const BasicBlock *BB = MBB->getBasicBlock();
15835 MachineFunction::iterator I = MBB;
15838 // Memory Reference
15839 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15840 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15843 unsigned MemOpndSlot = 0;
15845 unsigned CurOp = 0;
15847 DstReg = MI->getOperand(CurOp++).getReg();
15848 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15849 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15850 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15851 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15853 MemOpndSlot = CurOp;
15855 MVT PVT = getPointerTy();
15856 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15857 "Invalid Pointer Size!");
15859 // For v = setjmp(buf), we generate
15862 // buf[LabelOffset] = restoreMBB
15863 // SjLjSetup restoreMBB
15869 // v = phi(main, restore)
15874 MachineBasicBlock *thisMBB = MBB;
15875 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15876 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15877 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15878 MF->insert(I, mainMBB);
15879 MF->insert(I, sinkMBB);
15880 MF->push_back(restoreMBB);
15882 MachineInstrBuilder MIB;
15884 // Transfer the remainder of BB and its successor edges to sinkMBB.
15885 sinkMBB->splice(sinkMBB->begin(), MBB,
15886 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15887 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15890 unsigned PtrStoreOpc = 0;
15891 unsigned LabelReg = 0;
15892 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15893 Reloc::Model RM = getTargetMachine().getRelocationModel();
15894 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15895 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15897 // Prepare IP either in reg or imm.
15898 if (!UseImmLabel) {
15899 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15900 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15901 LabelReg = MRI.createVirtualRegister(PtrRC);
15902 if (Subtarget->is64Bit()) {
15903 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15907 .addMBB(restoreMBB)
15910 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15911 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15912 .addReg(XII->getGlobalBaseReg(MF))
15915 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15919 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15921 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15922 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15923 if (i == X86::AddrDisp)
15924 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15926 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15929 MIB.addReg(LabelReg);
15931 MIB.addMBB(restoreMBB);
15932 MIB.setMemRefs(MMOBegin, MMOEnd);
15934 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15935 .addMBB(restoreMBB);
15937 const X86RegisterInfo *RegInfo =
15938 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15939 MIB.addRegMask(RegInfo->getNoPreservedMask());
15940 thisMBB->addSuccessor(mainMBB);
15941 thisMBB->addSuccessor(restoreMBB);
15945 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15946 mainMBB->addSuccessor(sinkMBB);
15949 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15950 TII->get(X86::PHI), DstReg)
15951 .addReg(mainDstReg).addMBB(mainMBB)
15952 .addReg(restoreDstReg).addMBB(restoreMBB);
15955 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15956 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15957 restoreMBB->addSuccessor(sinkMBB);
15959 MI->eraseFromParent();
15963 MachineBasicBlock *
15964 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15965 MachineBasicBlock *MBB) const {
15966 DebugLoc DL = MI->getDebugLoc();
15967 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15969 MachineFunction *MF = MBB->getParent();
15970 MachineRegisterInfo &MRI = MF->getRegInfo();
15972 // Memory Reference
15973 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15974 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15976 MVT PVT = getPointerTy();
15977 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15978 "Invalid Pointer Size!");
15980 const TargetRegisterClass *RC =
15981 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15982 unsigned Tmp = MRI.createVirtualRegister(RC);
15983 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15984 const X86RegisterInfo *RegInfo =
15985 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15986 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15987 unsigned SP = RegInfo->getStackRegister();
15989 MachineInstrBuilder MIB;
15991 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15992 const int64_t SPOffset = 2 * PVT.getStoreSize();
15994 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15995 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15998 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15999 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
16000 MIB.addOperand(MI->getOperand(i));
16001 MIB.setMemRefs(MMOBegin, MMOEnd);
16003 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
16004 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16005 if (i == X86::AddrDisp)
16006 MIB.addDisp(MI->getOperand(i), LabelOffset);
16008 MIB.addOperand(MI->getOperand(i));
16010 MIB.setMemRefs(MMOBegin, MMOEnd);
16012 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
16013 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16014 if (i == X86::AddrDisp)
16015 MIB.addDisp(MI->getOperand(i), SPOffset);
16017 MIB.addOperand(MI->getOperand(i));
16019 MIB.setMemRefs(MMOBegin, MMOEnd);
16021 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
16023 MI->eraseFromParent();
16027 // Replace 213-type (isel default) FMA3 instructions with 231-type for
16028 // accumulator loops. Writing back to the accumulator allows the coalescer
16029 // to remove extra copies in the loop.
16030 MachineBasicBlock *
16031 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
16032 MachineBasicBlock *MBB) const {
16033 MachineOperand &AddendOp = MI->getOperand(3);
16035 // Bail out early if the addend isn't a register - we can't switch these.
16036 if (!AddendOp.isReg())
16039 MachineFunction &MF = *MBB->getParent();
16040 MachineRegisterInfo &MRI = MF.getRegInfo();
16042 // Check whether the addend is defined by a PHI:
16043 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
16044 MachineInstr &AddendDef = *MRI.def_begin(AddendOp.getReg());
16045 if (!AddendDef.isPHI())
16048 // Look for the following pattern:
16050 // %addend = phi [%entry, 0], [%loop, %result]
16052 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
16056 // %addend = phi [%entry, 0], [%loop, %result]
16058 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
16060 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
16061 assert(AddendDef.getOperand(i).isReg());
16062 MachineOperand PHISrcOp = AddendDef.getOperand(i);
16063 MachineInstr &PHISrcInst = *MRI.def_begin(PHISrcOp.getReg());
16064 if (&PHISrcInst == MI) {
16065 // Found a matching instruction.
16066 unsigned NewFMAOpc = 0;
16067 switch (MI->getOpcode()) {
16068 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
16069 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
16070 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
16071 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
16072 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
16073 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
16074 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
16075 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
16076 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
16077 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
16078 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
16079 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
16080 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
16081 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
16082 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
16083 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
16084 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
16085 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
16086 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
16087 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
16088 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
16089 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
16090 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
16091 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
16092 default: llvm_unreachable("Unrecognized FMA variant.");
16095 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
16096 MachineInstrBuilder MIB =
16097 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
16098 .addOperand(MI->getOperand(0))
16099 .addOperand(MI->getOperand(3))
16100 .addOperand(MI->getOperand(2))
16101 .addOperand(MI->getOperand(1));
16102 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
16103 MI->eraseFromParent();
16110 MachineBasicBlock *
16111 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
16112 MachineBasicBlock *BB) const {
16113 switch (MI->getOpcode()) {
16114 default: llvm_unreachable("Unexpected instr type to insert");
16115 case X86::TAILJMPd64:
16116 case X86::TAILJMPr64:
16117 case X86::TAILJMPm64:
16118 llvm_unreachable("TAILJMP64 would not be touched here.");
16119 case X86::TCRETURNdi64:
16120 case X86::TCRETURNri64:
16121 case X86::TCRETURNmi64:
16123 case X86::WIN_ALLOCA:
16124 return EmitLoweredWinAlloca(MI, BB);
16125 case X86::SEG_ALLOCA_32:
16126 return EmitLoweredSegAlloca(MI, BB, false);
16127 case X86::SEG_ALLOCA_64:
16128 return EmitLoweredSegAlloca(MI, BB, true);
16129 case X86::TLSCall_32:
16130 case X86::TLSCall_64:
16131 return EmitLoweredTLSCall(MI, BB);
16132 case X86::CMOV_GR8:
16133 case X86::CMOV_FR32:
16134 case X86::CMOV_FR64:
16135 case X86::CMOV_V4F32:
16136 case X86::CMOV_V2F64:
16137 case X86::CMOV_V2I64:
16138 case X86::CMOV_V8F32:
16139 case X86::CMOV_V4F64:
16140 case X86::CMOV_V4I64:
16141 case X86::CMOV_V16F32:
16142 case X86::CMOV_V8F64:
16143 case X86::CMOV_V8I64:
16144 case X86::CMOV_GR16:
16145 case X86::CMOV_GR32:
16146 case X86::CMOV_RFP32:
16147 case X86::CMOV_RFP64:
16148 case X86::CMOV_RFP80:
16149 return EmitLoweredSelect(MI, BB);
16151 case X86::FP32_TO_INT16_IN_MEM:
16152 case X86::FP32_TO_INT32_IN_MEM:
16153 case X86::FP32_TO_INT64_IN_MEM:
16154 case X86::FP64_TO_INT16_IN_MEM:
16155 case X86::FP64_TO_INT32_IN_MEM:
16156 case X86::FP64_TO_INT64_IN_MEM:
16157 case X86::FP80_TO_INT16_IN_MEM:
16158 case X86::FP80_TO_INT32_IN_MEM:
16159 case X86::FP80_TO_INT64_IN_MEM: {
16160 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16161 DebugLoc DL = MI->getDebugLoc();
16163 // Change the floating point control register to use "round towards zero"
16164 // mode when truncating to an integer value.
16165 MachineFunction *F = BB->getParent();
16166 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
16167 addFrameReference(BuildMI(*BB, MI, DL,
16168 TII->get(X86::FNSTCW16m)), CWFrameIdx);
16170 // Load the old value of the high byte of the control word...
16172 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
16173 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
16176 // Set the high part to be round to zero...
16177 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
16180 // Reload the modified control word now...
16181 addFrameReference(BuildMI(*BB, MI, DL,
16182 TII->get(X86::FLDCW16m)), CWFrameIdx);
16184 // Restore the memory image of control word to original value
16185 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
16188 // Get the X86 opcode to use.
16190 switch (MI->getOpcode()) {
16191 default: llvm_unreachable("illegal opcode!");
16192 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
16193 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
16194 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
16195 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
16196 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
16197 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
16198 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
16199 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
16200 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
16204 MachineOperand &Op = MI->getOperand(0);
16206 AM.BaseType = X86AddressMode::RegBase;
16207 AM.Base.Reg = Op.getReg();
16209 AM.BaseType = X86AddressMode::FrameIndexBase;
16210 AM.Base.FrameIndex = Op.getIndex();
16212 Op = MI->getOperand(1);
16214 AM.Scale = Op.getImm();
16215 Op = MI->getOperand(2);
16217 AM.IndexReg = Op.getImm();
16218 Op = MI->getOperand(3);
16219 if (Op.isGlobal()) {
16220 AM.GV = Op.getGlobal();
16222 AM.Disp = Op.getImm();
16224 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
16225 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16227 // Reload the original control word now.
16228 addFrameReference(BuildMI(*BB, MI, DL,
16229 TII->get(X86::FLDCW16m)), CWFrameIdx);
16231 MI->eraseFromParent(); // The pseudo instruction is gone now.
16234 // String/text processing lowering.
16235 case X86::PCMPISTRM128REG:
16236 case X86::VPCMPISTRM128REG:
16237 case X86::PCMPISTRM128MEM:
16238 case X86::VPCMPISTRM128MEM:
16239 case X86::PCMPESTRM128REG:
16240 case X86::VPCMPESTRM128REG:
16241 case X86::PCMPESTRM128MEM:
16242 case X86::VPCMPESTRM128MEM:
16243 assert(Subtarget->hasSSE42() &&
16244 "Target must have SSE4.2 or AVX features enabled");
16245 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16247 // String/text processing lowering.
16248 case X86::PCMPISTRIREG:
16249 case X86::VPCMPISTRIREG:
16250 case X86::PCMPISTRIMEM:
16251 case X86::VPCMPISTRIMEM:
16252 case X86::PCMPESTRIREG:
16253 case X86::VPCMPESTRIREG:
16254 case X86::PCMPESTRIMEM:
16255 case X86::VPCMPESTRIMEM:
16256 assert(Subtarget->hasSSE42() &&
16257 "Target must have SSE4.2 or AVX features enabled");
16258 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16260 // Thread synchronization.
16262 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16266 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16268 // Atomic Lowering.
16269 case X86::ATOMAND8:
16270 case X86::ATOMAND16:
16271 case X86::ATOMAND32:
16272 case X86::ATOMAND64:
16275 case X86::ATOMOR16:
16276 case X86::ATOMOR32:
16277 case X86::ATOMOR64:
16279 case X86::ATOMXOR16:
16280 case X86::ATOMXOR8:
16281 case X86::ATOMXOR32:
16282 case X86::ATOMXOR64:
16284 case X86::ATOMNAND8:
16285 case X86::ATOMNAND16:
16286 case X86::ATOMNAND32:
16287 case X86::ATOMNAND64:
16289 case X86::ATOMMAX8:
16290 case X86::ATOMMAX16:
16291 case X86::ATOMMAX32:
16292 case X86::ATOMMAX64:
16294 case X86::ATOMMIN8:
16295 case X86::ATOMMIN16:
16296 case X86::ATOMMIN32:
16297 case X86::ATOMMIN64:
16299 case X86::ATOMUMAX8:
16300 case X86::ATOMUMAX16:
16301 case X86::ATOMUMAX32:
16302 case X86::ATOMUMAX64:
16304 case X86::ATOMUMIN8:
16305 case X86::ATOMUMIN16:
16306 case X86::ATOMUMIN32:
16307 case X86::ATOMUMIN64:
16308 return EmitAtomicLoadArith(MI, BB);
16310 // This group does 64-bit operations on a 32-bit host.
16311 case X86::ATOMAND6432:
16312 case X86::ATOMOR6432:
16313 case X86::ATOMXOR6432:
16314 case X86::ATOMNAND6432:
16315 case X86::ATOMADD6432:
16316 case X86::ATOMSUB6432:
16317 case X86::ATOMMAX6432:
16318 case X86::ATOMMIN6432:
16319 case X86::ATOMUMAX6432:
16320 case X86::ATOMUMIN6432:
16321 case X86::ATOMSWAP6432:
16322 return EmitAtomicLoadArith6432(MI, BB);
16324 case X86::VASTART_SAVE_XMM_REGS:
16325 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16327 case X86::VAARG_64:
16328 return EmitVAARG64WithCustomInserter(MI, BB);
16330 case X86::EH_SjLj_SetJmp32:
16331 case X86::EH_SjLj_SetJmp64:
16332 return emitEHSjLjSetJmp(MI, BB);
16334 case X86::EH_SjLj_LongJmp32:
16335 case X86::EH_SjLj_LongJmp64:
16336 return emitEHSjLjLongJmp(MI, BB);
16338 case TargetOpcode::STACKMAP:
16339 case TargetOpcode::PATCHPOINT:
16340 return emitPatchPoint(MI, BB);
16342 case X86::VFMADDPDr213r:
16343 case X86::VFMADDPSr213r:
16344 case X86::VFMADDSDr213r:
16345 case X86::VFMADDSSr213r:
16346 case X86::VFMSUBPDr213r:
16347 case X86::VFMSUBPSr213r:
16348 case X86::VFMSUBSDr213r:
16349 case X86::VFMSUBSSr213r:
16350 case X86::VFNMADDPDr213r:
16351 case X86::VFNMADDPSr213r:
16352 case X86::VFNMADDSDr213r:
16353 case X86::VFNMADDSSr213r:
16354 case X86::VFNMSUBPDr213r:
16355 case X86::VFNMSUBPSr213r:
16356 case X86::VFNMSUBSDr213r:
16357 case X86::VFNMSUBSSr213r:
16358 case X86::VFMADDPDr213rY:
16359 case X86::VFMADDPSr213rY:
16360 case X86::VFMSUBPDr213rY:
16361 case X86::VFMSUBPSr213rY:
16362 case X86::VFNMADDPDr213rY:
16363 case X86::VFNMADDPSr213rY:
16364 case X86::VFNMSUBPDr213rY:
16365 case X86::VFNMSUBPSr213rY:
16366 return emitFMA3Instr(MI, BB);
16370 //===----------------------------------------------------------------------===//
16371 // X86 Optimization Hooks
16372 //===----------------------------------------------------------------------===//
16374 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16377 const SelectionDAG &DAG,
16378 unsigned Depth) const {
16379 unsigned BitWidth = KnownZero.getBitWidth();
16380 unsigned Opc = Op.getOpcode();
16381 assert((Opc >= ISD::BUILTIN_OP_END ||
16382 Opc == ISD::INTRINSIC_WO_CHAIN ||
16383 Opc == ISD::INTRINSIC_W_CHAIN ||
16384 Opc == ISD::INTRINSIC_VOID) &&
16385 "Should use MaskedValueIsZero if you don't know whether Op"
16386 " is a target node!");
16388 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16402 // These nodes' second result is a boolean.
16403 if (Op.getResNo() == 0)
16406 case X86ISD::SETCC:
16407 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16409 case ISD::INTRINSIC_WO_CHAIN: {
16410 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16411 unsigned NumLoBits = 0;
16414 case Intrinsic::x86_sse_movmsk_ps:
16415 case Intrinsic::x86_avx_movmsk_ps_256:
16416 case Intrinsic::x86_sse2_movmsk_pd:
16417 case Intrinsic::x86_avx_movmsk_pd_256:
16418 case Intrinsic::x86_mmx_pmovmskb:
16419 case Intrinsic::x86_sse2_pmovmskb_128:
16420 case Intrinsic::x86_avx2_pmovmskb: {
16421 // High bits of movmskp{s|d}, pmovmskb are known zero.
16423 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16424 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16425 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16426 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16427 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16428 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16429 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16430 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16432 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16441 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16442 unsigned Depth) const {
16443 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16444 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16445 return Op.getValueType().getScalarType().getSizeInBits();
16451 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16452 /// node is a GlobalAddress + offset.
16453 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16454 const GlobalValue* &GA,
16455 int64_t &Offset) const {
16456 if (N->getOpcode() == X86ISD::Wrapper) {
16457 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16458 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16459 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16463 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16466 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16467 /// same as extracting the high 128-bit part of 256-bit vector and then
16468 /// inserting the result into the low part of a new 256-bit vector
16469 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16470 EVT VT = SVOp->getValueType(0);
16471 unsigned NumElems = VT.getVectorNumElements();
16473 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16474 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16475 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16476 SVOp->getMaskElt(j) >= 0)
16482 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16483 /// same as extracting the low 128-bit part of 256-bit vector and then
16484 /// inserting the result into the high part of a new 256-bit vector
16485 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16486 EVT VT = SVOp->getValueType(0);
16487 unsigned NumElems = VT.getVectorNumElements();
16489 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16490 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16491 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16492 SVOp->getMaskElt(j) >= 0)
16498 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16499 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16500 TargetLowering::DAGCombinerInfo &DCI,
16501 const X86Subtarget* Subtarget) {
16503 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16504 SDValue V1 = SVOp->getOperand(0);
16505 SDValue V2 = SVOp->getOperand(1);
16506 EVT VT = SVOp->getValueType(0);
16507 unsigned NumElems = VT.getVectorNumElements();
16509 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16510 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16514 // V UNDEF BUILD_VECTOR UNDEF
16516 // CONCAT_VECTOR CONCAT_VECTOR
16519 // RESULT: V + zero extended
16521 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16522 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16523 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16526 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16529 // To match the shuffle mask, the first half of the mask should
16530 // be exactly the first vector, and all the rest a splat with the
16531 // first element of the second one.
16532 for (unsigned i = 0; i != NumElems/2; ++i)
16533 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16534 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16537 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16538 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16539 if (Ld->hasNUsesOfValue(1, 0)) {
16540 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16541 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16543 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16544 array_lengthof(Ops),
16546 Ld->getPointerInfo(),
16547 Ld->getAlignment(),
16548 false/*isVolatile*/, true/*ReadMem*/,
16549 false/*WriteMem*/);
16551 // Make sure the newly-created LOAD is in the same position as Ld in
16552 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16553 // and update uses of Ld's output chain to use the TokenFactor.
16554 if (Ld->hasAnyUseOfValue(1)) {
16555 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16556 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16557 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16558 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16559 SDValue(ResNode.getNode(), 1));
16562 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16566 // Emit a zeroed vector and insert the desired subvector on its
16568 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16569 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16570 return DCI.CombineTo(N, InsV);
16573 //===--------------------------------------------------------------------===//
16574 // Combine some shuffles into subvector extracts and inserts:
16577 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16578 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16579 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16580 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16581 return DCI.CombineTo(N, InsV);
16584 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16585 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16586 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16587 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16588 return DCI.CombineTo(N, InsV);
16594 /// PerformShuffleCombine - Performs several different shuffle combines.
16595 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16596 TargetLowering::DAGCombinerInfo &DCI,
16597 const X86Subtarget *Subtarget) {
16599 EVT VT = N->getValueType(0);
16601 // Don't create instructions with illegal types after legalize types has run.
16602 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16603 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16606 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16607 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16608 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16609 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16611 // Only handle 128 wide vector from here on.
16612 if (!VT.is128BitVector())
16615 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16616 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16617 // consecutive, non-overlapping, and in the right order.
16618 SmallVector<SDValue, 16> Elts;
16619 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16620 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16622 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
16625 /// PerformTruncateCombine - Converts truncate operation to
16626 /// a sequence of vector shuffle operations.
16627 /// It is possible when we truncate 256-bit vector to 128-bit vector
16628 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16629 TargetLowering::DAGCombinerInfo &DCI,
16630 const X86Subtarget *Subtarget) {
16634 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16635 /// specific shuffle of a load can be folded into a single element load.
16636 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16637 /// shuffles have been customed lowered so we need to handle those here.
16638 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16639 TargetLowering::DAGCombinerInfo &DCI) {
16640 if (DCI.isBeforeLegalizeOps())
16643 SDValue InVec = N->getOperand(0);
16644 SDValue EltNo = N->getOperand(1);
16646 if (!isa<ConstantSDNode>(EltNo))
16649 EVT VT = InVec.getValueType();
16651 bool HasShuffleIntoBitcast = false;
16652 if (InVec.getOpcode() == ISD::BITCAST) {
16653 // Don't duplicate a load with other uses.
16654 if (!InVec.hasOneUse())
16656 EVT BCVT = InVec.getOperand(0).getValueType();
16657 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16659 InVec = InVec.getOperand(0);
16660 HasShuffleIntoBitcast = true;
16663 if (!isTargetShuffle(InVec.getOpcode()))
16666 // Don't duplicate a load with other uses.
16667 if (!InVec.hasOneUse())
16670 SmallVector<int, 16> ShuffleMask;
16672 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16676 // Select the input vector, guarding against out of range extract vector.
16677 unsigned NumElems = VT.getVectorNumElements();
16678 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16679 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16680 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16681 : InVec.getOperand(1);
16683 // If inputs to shuffle are the same for both ops, then allow 2 uses
16684 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16686 if (LdNode.getOpcode() == ISD::BITCAST) {
16687 // Don't duplicate a load with other uses.
16688 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16691 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16692 LdNode = LdNode.getOperand(0);
16695 if (!ISD::isNormalLoad(LdNode.getNode()))
16698 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16700 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16703 if (HasShuffleIntoBitcast) {
16704 // If there's a bitcast before the shuffle, check if the load type and
16705 // alignment is valid.
16706 unsigned Align = LN0->getAlignment();
16707 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16708 unsigned NewAlign = TLI.getDataLayout()->
16709 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16711 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16715 // All checks match so transform back to vector_shuffle so that DAG combiner
16716 // can finish the job
16719 // Create shuffle node taking into account the case that its a unary shuffle
16720 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16721 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16722 InVec.getOperand(0), Shuffle,
16724 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16725 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16729 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16730 /// generation and convert it from being a bunch of shuffles and extracts
16731 /// to a simple store and scalar loads to extract the elements.
16732 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16733 TargetLowering::DAGCombinerInfo &DCI) {
16734 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16735 if (NewOp.getNode())
16738 SDValue InputVector = N->getOperand(0);
16740 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16741 // from mmx to v2i32 has a single usage.
16742 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16743 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16744 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16745 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16746 N->getValueType(0),
16747 InputVector.getNode()->getOperand(0));
16749 // Only operate on vectors of 4 elements, where the alternative shuffling
16750 // gets to be more expensive.
16751 if (InputVector.getValueType() != MVT::v4i32)
16754 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16755 // single use which is a sign-extend or zero-extend, and all elements are
16757 SmallVector<SDNode *, 4> Uses;
16758 unsigned ExtractedElements = 0;
16759 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16760 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16761 if (UI.getUse().getResNo() != InputVector.getResNo())
16764 SDNode *Extract = *UI;
16765 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16768 if (Extract->getValueType(0) != MVT::i32)
16770 if (!Extract->hasOneUse())
16772 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16773 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16775 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16778 // Record which element was extracted.
16779 ExtractedElements |=
16780 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16782 Uses.push_back(Extract);
16785 // If not all the elements were used, this may not be worthwhile.
16786 if (ExtractedElements != 15)
16789 // Ok, we've now decided to do the transformation.
16790 SDLoc dl(InputVector);
16792 // Store the value to a temporary stack slot.
16793 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16794 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16795 MachinePointerInfo(), false, false, 0);
16797 // Replace each use (extract) with a load of the appropriate element.
16798 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16799 UE = Uses.end(); UI != UE; ++UI) {
16800 SDNode *Extract = *UI;
16802 // cOMpute the element's address.
16803 SDValue Idx = Extract->getOperand(1);
16805 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16806 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16807 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16808 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16810 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16811 StackPtr, OffsetVal);
16813 // Load the scalar.
16814 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16815 ScalarAddr, MachinePointerInfo(),
16816 false, false, false, 0);
16818 // Replace the exact with the load.
16819 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16822 // The replacement was made in place; don't return anything.
16826 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16827 static std::pair<unsigned, bool>
16828 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16829 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16830 if (!VT.isVector())
16831 return std::make_pair(0, false);
16833 bool NeedSplit = false;
16834 switch (VT.getSimpleVT().SimpleTy) {
16835 default: return std::make_pair(0, false);
16839 if (!Subtarget->hasAVX2())
16841 if (!Subtarget->hasAVX())
16842 return std::make_pair(0, false);
16847 if (!Subtarget->hasSSE2())
16848 return std::make_pair(0, false);
16851 // SSE2 has only a small subset of the operations.
16852 bool hasUnsigned = Subtarget->hasSSE41() ||
16853 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16854 bool hasSigned = Subtarget->hasSSE41() ||
16855 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16857 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16860 // Check for x CC y ? x : y.
16861 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16862 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16867 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16870 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16873 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16876 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16878 // Check for x CC y ? y : x -- a min/max with reversed arms.
16879 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16880 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16885 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16888 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16891 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16894 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16898 return std::make_pair(Opc, NeedSplit);
16901 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16903 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16904 TargetLowering::DAGCombinerInfo &DCI,
16905 const X86Subtarget *Subtarget) {
16907 SDValue Cond = N->getOperand(0);
16908 // Get the LHS/RHS of the select.
16909 SDValue LHS = N->getOperand(1);
16910 SDValue RHS = N->getOperand(2);
16911 EVT VT = LHS.getValueType();
16912 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16914 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16915 // instructions match the semantics of the common C idiom x<y?x:y but not
16916 // x<=y?x:y, because of how they handle negative zero (which can be
16917 // ignored in unsafe-math mode).
16918 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16919 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16920 (Subtarget->hasSSE2() ||
16921 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16922 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16924 unsigned Opcode = 0;
16925 // Check for x CC y ? x : y.
16926 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16927 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16931 // Converting this to a min would handle NaNs incorrectly, and swapping
16932 // the operands would cause it to handle comparisons between positive
16933 // and negative zero incorrectly.
16934 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16935 if (!DAG.getTarget().Options.UnsafeFPMath &&
16936 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16938 std::swap(LHS, RHS);
16940 Opcode = X86ISD::FMIN;
16943 // Converting this to a min would handle comparisons between positive
16944 // and negative zero incorrectly.
16945 if (!DAG.getTarget().Options.UnsafeFPMath &&
16946 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16948 Opcode = X86ISD::FMIN;
16951 // Converting this to a min would handle both negative zeros and NaNs
16952 // incorrectly, but we can swap the operands to fix both.
16953 std::swap(LHS, RHS);
16957 Opcode = X86ISD::FMIN;
16961 // Converting this to a max would handle comparisons between positive
16962 // and negative zero incorrectly.
16963 if (!DAG.getTarget().Options.UnsafeFPMath &&
16964 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16966 Opcode = X86ISD::FMAX;
16969 // Converting this to a max would handle NaNs incorrectly, and swapping
16970 // the operands would cause it to handle comparisons between positive
16971 // and negative zero incorrectly.
16972 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16973 if (!DAG.getTarget().Options.UnsafeFPMath &&
16974 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16976 std::swap(LHS, RHS);
16978 Opcode = X86ISD::FMAX;
16981 // Converting this to a max would handle both negative zeros and NaNs
16982 // incorrectly, but we can swap the operands to fix both.
16983 std::swap(LHS, RHS);
16987 Opcode = X86ISD::FMAX;
16990 // Check for x CC y ? y : x -- a min/max with reversed arms.
16991 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16992 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16996 // Converting this to a min would handle comparisons between positive
16997 // and negative zero incorrectly, and swapping the operands would
16998 // cause it to handle NaNs incorrectly.
16999 if (!DAG.getTarget().Options.UnsafeFPMath &&
17000 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
17001 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17003 std::swap(LHS, RHS);
17005 Opcode = X86ISD::FMIN;
17008 // Converting this to a min would handle NaNs incorrectly.
17009 if (!DAG.getTarget().Options.UnsafeFPMath &&
17010 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
17012 Opcode = X86ISD::FMIN;
17015 // Converting this to a min would handle both negative zeros and NaNs
17016 // incorrectly, but we can swap the operands to fix both.
17017 std::swap(LHS, RHS);
17021 Opcode = X86ISD::FMIN;
17025 // Converting this to a max would handle NaNs incorrectly.
17026 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17028 Opcode = X86ISD::FMAX;
17031 // Converting this to a max would handle comparisons between positive
17032 // and negative zero incorrectly, and swapping the operands would
17033 // cause it to handle NaNs incorrectly.
17034 if (!DAG.getTarget().Options.UnsafeFPMath &&
17035 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
17036 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17038 std::swap(LHS, RHS);
17040 Opcode = X86ISD::FMAX;
17043 // Converting this to a max would handle both negative zeros and NaNs
17044 // incorrectly, but we can swap the operands to fix both.
17045 std::swap(LHS, RHS);
17049 Opcode = X86ISD::FMAX;
17055 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
17058 EVT CondVT = Cond.getValueType();
17059 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
17060 CondVT.getVectorElementType() == MVT::i1) {
17061 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
17062 // lowering on AVX-512. In this case we convert it to
17063 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
17064 // The same situation for all 128 and 256-bit vectors of i8 and i16
17065 EVT OpVT = LHS.getValueType();
17066 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
17067 (OpVT.getVectorElementType() == MVT::i8 ||
17068 OpVT.getVectorElementType() == MVT::i16)) {
17069 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
17070 DCI.AddToWorklist(Cond.getNode());
17071 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
17074 // If this is a select between two integer constants, try to do some
17076 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
17077 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
17078 // Don't do this for crazy integer types.
17079 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
17080 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
17081 // so that TrueC (the true value) is larger than FalseC.
17082 bool NeedsCondInvert = false;
17084 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
17085 // Efficiently invertible.
17086 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
17087 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
17088 isa<ConstantSDNode>(Cond.getOperand(1))))) {
17089 NeedsCondInvert = true;
17090 std::swap(TrueC, FalseC);
17093 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
17094 if (FalseC->getAPIntValue() == 0 &&
17095 TrueC->getAPIntValue().isPowerOf2()) {
17096 if (NeedsCondInvert) // Invert the condition if needed.
17097 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17098 DAG.getConstant(1, Cond.getValueType()));
17100 // Zero extend the condition if needed.
17101 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
17103 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17104 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
17105 DAG.getConstant(ShAmt, MVT::i8));
17108 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
17109 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17110 if (NeedsCondInvert) // Invert the condition if needed.
17111 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17112 DAG.getConstant(1, Cond.getValueType()));
17114 // Zero extend the condition if needed.
17115 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17116 FalseC->getValueType(0), Cond);
17117 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17118 SDValue(FalseC, 0));
17121 // Optimize cases that will turn into an LEA instruction. This requires
17122 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17123 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17124 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17125 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17127 bool isFastMultiplier = false;
17129 switch ((unsigned char)Diff) {
17131 case 1: // result = add base, cond
17132 case 2: // result = lea base( , cond*2)
17133 case 3: // result = lea base(cond, cond*2)
17134 case 4: // result = lea base( , cond*4)
17135 case 5: // result = lea base(cond, cond*4)
17136 case 8: // result = lea base( , cond*8)
17137 case 9: // result = lea base(cond, cond*8)
17138 isFastMultiplier = true;
17143 if (isFastMultiplier) {
17144 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17145 if (NeedsCondInvert) // Invert the condition if needed.
17146 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17147 DAG.getConstant(1, Cond.getValueType()));
17149 // Zero extend the condition if needed.
17150 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17152 // Scale the condition by the difference.
17154 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17155 DAG.getConstant(Diff, Cond.getValueType()));
17157 // Add the base if non-zero.
17158 if (FalseC->getAPIntValue() != 0)
17159 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17160 SDValue(FalseC, 0));
17167 // Canonicalize max and min:
17168 // (x > y) ? x : y -> (x >= y) ? x : y
17169 // (x < y) ? x : y -> (x <= y) ? x : y
17170 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
17171 // the need for an extra compare
17172 // against zero. e.g.
17173 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
17175 // testl %edi, %edi
17177 // cmovgl %edi, %eax
17181 // cmovsl %eax, %edi
17182 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
17183 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17184 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17185 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17190 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
17191 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
17192 Cond.getOperand(0), Cond.getOperand(1), NewCC);
17193 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
17198 // Early exit check
17199 if (!TLI.isTypeLegal(VT))
17202 // Match VSELECTs into subs with unsigned saturation.
17203 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17204 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
17205 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
17206 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
17207 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17209 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
17210 // left side invert the predicate to simplify logic below.
17212 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
17214 CC = ISD::getSetCCInverse(CC, true);
17215 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
17219 if (Other.getNode() && Other->getNumOperands() == 2 &&
17220 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
17221 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
17222 SDValue CondRHS = Cond->getOperand(1);
17224 // Look for a general sub with unsigned saturation first.
17225 // x >= y ? x-y : 0 --> subus x, y
17226 // x > y ? x-y : 0 --> subus x, y
17227 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
17228 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
17229 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17231 // If the RHS is a constant we have to reverse the const canonicalization.
17232 // x > C-1 ? x+-C : 0 --> subus x, C
17233 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
17234 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
17235 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17236 if (CondRHS.getConstantOperandVal(0) == -A-1)
17237 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
17238 DAG.getConstant(-A, VT));
17241 // Another special case: If C was a sign bit, the sub has been
17242 // canonicalized into a xor.
17243 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
17244 // it's safe to decanonicalize the xor?
17245 // x s< 0 ? x^C : 0 --> subus x, C
17246 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
17247 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
17248 isSplatVector(OpRHS.getNode())) {
17249 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17251 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17256 // Try to match a min/max vector operation.
17257 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17258 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17259 unsigned Opc = ret.first;
17260 bool NeedSplit = ret.second;
17262 if (Opc && NeedSplit) {
17263 unsigned NumElems = VT.getVectorNumElements();
17264 // Extract the LHS vectors
17265 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17266 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17268 // Extract the RHS vectors
17269 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17270 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17272 // Create min/max for each subvector
17273 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17274 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17276 // Merge the result
17277 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17279 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17282 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17283 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17284 // Check if SETCC has already been promoted
17285 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17286 // Check that condition value type matches vselect operand type
17289 assert(Cond.getValueType().isVector() &&
17290 "vector select expects a vector selector!");
17292 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17293 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17295 if (!TValIsAllOnes && !FValIsAllZeros) {
17296 // Try invert the condition if true value is not all 1s and false value
17298 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17299 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17301 if (TValIsAllZeros || FValIsAllOnes) {
17302 SDValue CC = Cond.getOperand(2);
17303 ISD::CondCode NewCC =
17304 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17305 Cond.getOperand(0).getValueType().isInteger());
17306 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17307 std::swap(LHS, RHS);
17308 TValIsAllOnes = FValIsAllOnes;
17309 FValIsAllZeros = TValIsAllZeros;
17313 if (TValIsAllOnes || FValIsAllZeros) {
17316 if (TValIsAllOnes && FValIsAllZeros)
17318 else if (TValIsAllOnes)
17319 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17320 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17321 else if (FValIsAllZeros)
17322 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17323 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17325 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17329 // Try to fold this VSELECT into a MOVSS/MOVSD
17330 if (N->getOpcode() == ISD::VSELECT &&
17331 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
17332 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
17333 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
17334 bool CanFold = false;
17335 unsigned NumElems = Cond.getNumOperands();
17339 if (isZero(Cond.getOperand(0))) {
17342 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
17343 // fold (vselect <0,-1> -> (movsd A, B)
17344 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17345 CanFold = isAllOnes(Cond.getOperand(i));
17346 } else if (isAllOnes(Cond.getOperand(0))) {
17350 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
17351 // fold (vselect <-1,0> -> (movsd B, A)
17352 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17353 CanFold = isZero(Cond.getOperand(i));
17357 if (VT == MVT::v4i32 || VT == MVT::v4f32)
17358 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
17359 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
17362 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
17363 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
17364 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
17365 // (v2i64 (bitcast B)))))
17367 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
17368 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
17369 // (v2f64 (bitcast B)))))
17371 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
17372 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
17373 // (v2i64 (bitcast A)))))
17375 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
17376 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
17377 // (v2f64 (bitcast A)))))
17379 CanFold = (isZero(Cond.getOperand(0)) &&
17380 isZero(Cond.getOperand(1)) &&
17381 isAllOnes(Cond.getOperand(2)) &&
17382 isAllOnes(Cond.getOperand(3)));
17384 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
17385 isAllOnes(Cond.getOperand(1)) &&
17386 isZero(Cond.getOperand(2)) &&
17387 isZero(Cond.getOperand(3))) {
17389 std::swap(LHS, RHS);
17393 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
17394 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
17395 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
17396 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
17398 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
17404 // If we know that this node is legal then we know that it is going to be
17405 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17406 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17407 // to simplify previous instructions.
17408 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17409 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17410 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17412 // Don't optimize vector selects that map to mask-registers.
17416 // Check all uses of that condition operand to check whether it will be
17417 // consumed by non-BLEND instructions, which may depend on all bits are set
17419 for (SDNode::use_iterator I = Cond->use_begin(),
17420 E = Cond->use_end(); I != E; ++I)
17421 if (I->getOpcode() != ISD::VSELECT)
17422 // TODO: Add other opcodes eventually lowered into BLEND.
17425 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17426 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17428 APInt KnownZero, KnownOne;
17429 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17430 DCI.isBeforeLegalizeOps());
17431 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17432 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17433 DCI.CommitTargetLoweringOpt(TLO);
17439 // Check whether a boolean test is testing a boolean value generated by
17440 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17443 // Simplify the following patterns:
17444 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17445 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17446 // to (Op EFLAGS Cond)
17448 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17449 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17450 // to (Op EFLAGS !Cond)
17452 // where Op could be BRCOND or CMOV.
17454 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17455 // Quit if not CMP and SUB with its value result used.
17456 if (Cmp.getOpcode() != X86ISD::CMP &&
17457 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17460 // Quit if not used as a boolean value.
17461 if (CC != X86::COND_E && CC != X86::COND_NE)
17464 // Check CMP operands. One of them should be 0 or 1 and the other should be
17465 // an SetCC or extended from it.
17466 SDValue Op1 = Cmp.getOperand(0);
17467 SDValue Op2 = Cmp.getOperand(1);
17470 const ConstantSDNode* C = 0;
17471 bool needOppositeCond = (CC == X86::COND_E);
17472 bool checkAgainstTrue = false; // Is it a comparison against 1?
17474 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17476 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17478 else // Quit if all operands are not constants.
17481 if (C->getZExtValue() == 1) {
17482 needOppositeCond = !needOppositeCond;
17483 checkAgainstTrue = true;
17484 } else if (C->getZExtValue() != 0)
17485 // Quit if the constant is neither 0 or 1.
17488 bool truncatedToBoolWithAnd = false;
17489 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17490 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17491 SetCC.getOpcode() == ISD::TRUNCATE ||
17492 SetCC.getOpcode() == ISD::AND) {
17493 if (SetCC.getOpcode() == ISD::AND) {
17495 ConstantSDNode *CS;
17496 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17497 CS->getZExtValue() == 1)
17499 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17500 CS->getZExtValue() == 1)
17504 SetCC = SetCC.getOperand(OpIdx);
17505 truncatedToBoolWithAnd = true;
17507 SetCC = SetCC.getOperand(0);
17510 switch (SetCC.getOpcode()) {
17511 case X86ISD::SETCC_CARRY:
17512 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17513 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17514 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17515 // truncated to i1 using 'and'.
17516 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17518 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17519 "Invalid use of SETCC_CARRY!");
17521 case X86ISD::SETCC:
17522 // Set the condition code or opposite one if necessary.
17523 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17524 if (needOppositeCond)
17525 CC = X86::GetOppositeBranchCondition(CC);
17526 return SetCC.getOperand(1);
17527 case X86ISD::CMOV: {
17528 // Check whether false/true value has canonical one, i.e. 0 or 1.
17529 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17530 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17531 // Quit if true value is not a constant.
17534 // Quit if false value is not a constant.
17536 SDValue Op = SetCC.getOperand(0);
17537 // Skip 'zext' or 'trunc' node.
17538 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17539 Op.getOpcode() == ISD::TRUNCATE)
17540 Op = Op.getOperand(0);
17541 // A special case for rdrand/rdseed, where 0 is set if false cond is
17543 if ((Op.getOpcode() != X86ISD::RDRAND &&
17544 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17547 // Quit if false value is not the constant 0 or 1.
17548 bool FValIsFalse = true;
17549 if (FVal && FVal->getZExtValue() != 0) {
17550 if (FVal->getZExtValue() != 1)
17552 // If FVal is 1, opposite cond is needed.
17553 needOppositeCond = !needOppositeCond;
17554 FValIsFalse = false;
17556 // Quit if TVal is not the constant opposite of FVal.
17557 if (FValIsFalse && TVal->getZExtValue() != 1)
17559 if (!FValIsFalse && TVal->getZExtValue() != 0)
17561 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17562 if (needOppositeCond)
17563 CC = X86::GetOppositeBranchCondition(CC);
17564 return SetCC.getOperand(3);
17571 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17572 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17573 TargetLowering::DAGCombinerInfo &DCI,
17574 const X86Subtarget *Subtarget) {
17577 // If the flag operand isn't dead, don't touch this CMOV.
17578 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17581 SDValue FalseOp = N->getOperand(0);
17582 SDValue TrueOp = N->getOperand(1);
17583 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17584 SDValue Cond = N->getOperand(3);
17586 if (CC == X86::COND_E || CC == X86::COND_NE) {
17587 switch (Cond.getOpcode()) {
17591 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17592 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17593 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17599 Flags = checkBoolTestSetCCCombine(Cond, CC);
17600 if (Flags.getNode() &&
17601 // Extra check as FCMOV only supports a subset of X86 cond.
17602 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17603 SDValue Ops[] = { FalseOp, TrueOp,
17604 DAG.getConstant(CC, MVT::i8), Flags };
17605 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17606 Ops, array_lengthof(Ops));
17609 // If this is a select between two integer constants, try to do some
17610 // optimizations. Note that the operands are ordered the opposite of SELECT
17612 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17613 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17614 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17615 // larger than FalseC (the false value).
17616 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17617 CC = X86::GetOppositeBranchCondition(CC);
17618 std::swap(TrueC, FalseC);
17619 std::swap(TrueOp, FalseOp);
17622 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17623 // This is efficient for any integer data type (including i8/i16) and
17625 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17626 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17627 DAG.getConstant(CC, MVT::i8), Cond);
17629 // Zero extend the condition if needed.
17630 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17632 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17633 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17634 DAG.getConstant(ShAmt, MVT::i8));
17635 if (N->getNumValues() == 2) // Dead flag value?
17636 return DCI.CombineTo(N, Cond, SDValue());
17640 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17641 // for any integer data type, including i8/i16.
17642 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17643 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17644 DAG.getConstant(CC, MVT::i8), Cond);
17646 // Zero extend the condition if needed.
17647 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17648 FalseC->getValueType(0), Cond);
17649 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17650 SDValue(FalseC, 0));
17652 if (N->getNumValues() == 2) // Dead flag value?
17653 return DCI.CombineTo(N, Cond, SDValue());
17657 // Optimize cases that will turn into an LEA instruction. This requires
17658 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17659 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17660 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17661 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17663 bool isFastMultiplier = false;
17665 switch ((unsigned char)Diff) {
17667 case 1: // result = add base, cond
17668 case 2: // result = lea base( , cond*2)
17669 case 3: // result = lea base(cond, cond*2)
17670 case 4: // result = lea base( , cond*4)
17671 case 5: // result = lea base(cond, cond*4)
17672 case 8: // result = lea base( , cond*8)
17673 case 9: // result = lea base(cond, cond*8)
17674 isFastMultiplier = true;
17679 if (isFastMultiplier) {
17680 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17681 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17682 DAG.getConstant(CC, MVT::i8), Cond);
17683 // Zero extend the condition if needed.
17684 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17686 // Scale the condition by the difference.
17688 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17689 DAG.getConstant(Diff, Cond.getValueType()));
17691 // Add the base if non-zero.
17692 if (FalseC->getAPIntValue() != 0)
17693 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17694 SDValue(FalseC, 0));
17695 if (N->getNumValues() == 2) // Dead flag value?
17696 return DCI.CombineTo(N, Cond, SDValue());
17703 // Handle these cases:
17704 // (select (x != c), e, c) -> select (x != c), e, x),
17705 // (select (x == c), c, e) -> select (x == c), x, e)
17706 // where the c is an integer constant, and the "select" is the combination
17707 // of CMOV and CMP.
17709 // The rationale for this change is that the conditional-move from a constant
17710 // needs two instructions, however, conditional-move from a register needs
17711 // only one instruction.
17713 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17714 // some instruction-combining opportunities. This opt needs to be
17715 // postponed as late as possible.
17717 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17718 // the DCI.xxxx conditions are provided to postpone the optimization as
17719 // late as possible.
17721 ConstantSDNode *CmpAgainst = 0;
17722 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17723 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17724 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17726 if (CC == X86::COND_NE &&
17727 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17728 CC = X86::GetOppositeBranchCondition(CC);
17729 std::swap(TrueOp, FalseOp);
17732 if (CC == X86::COND_E &&
17733 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17734 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17735 DAG.getConstant(CC, MVT::i8), Cond };
17736 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17737 array_lengthof(Ops));
17745 /// PerformMulCombine - Optimize a single multiply with constant into two
17746 /// in order to implement it with two cheaper instructions, e.g.
17747 /// LEA + SHL, LEA + LEA.
17748 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17749 TargetLowering::DAGCombinerInfo &DCI) {
17750 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17753 EVT VT = N->getValueType(0);
17754 if (VT != MVT::i64)
17757 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17760 uint64_t MulAmt = C->getZExtValue();
17761 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17764 uint64_t MulAmt1 = 0;
17765 uint64_t MulAmt2 = 0;
17766 if ((MulAmt % 9) == 0) {
17768 MulAmt2 = MulAmt / 9;
17769 } else if ((MulAmt % 5) == 0) {
17771 MulAmt2 = MulAmt / 5;
17772 } else if ((MulAmt % 3) == 0) {
17774 MulAmt2 = MulAmt / 3;
17777 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17780 if (isPowerOf2_64(MulAmt2) &&
17781 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17782 // If second multiplifer is pow2, issue it first. We want the multiply by
17783 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17785 std::swap(MulAmt1, MulAmt2);
17788 if (isPowerOf2_64(MulAmt1))
17789 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17790 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17792 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17793 DAG.getConstant(MulAmt1, VT));
17795 if (isPowerOf2_64(MulAmt2))
17796 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17797 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17799 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17800 DAG.getConstant(MulAmt2, VT));
17802 // Do not add new nodes to DAG combiner worklist.
17803 DCI.CombineTo(N, NewMul, false);
17808 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17809 SDValue N0 = N->getOperand(0);
17810 SDValue N1 = N->getOperand(1);
17811 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17812 EVT VT = N0.getValueType();
17814 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17815 // since the result of setcc_c is all zero's or all ones.
17816 if (VT.isInteger() && !VT.isVector() &&
17817 N1C && N0.getOpcode() == ISD::AND &&
17818 N0.getOperand(1).getOpcode() == ISD::Constant) {
17819 SDValue N00 = N0.getOperand(0);
17820 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17821 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17822 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17823 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17824 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17825 APInt ShAmt = N1C->getAPIntValue();
17826 Mask = Mask.shl(ShAmt);
17828 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17829 N00, DAG.getConstant(Mask, VT));
17833 // Hardware support for vector shifts is sparse which makes us scalarize the
17834 // vector operations in many cases. Also, on sandybridge ADD is faster than
17836 // (shl V, 1) -> add V,V
17837 if (isSplatVector(N1.getNode())) {
17838 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17840 // We shift all of the values by one. In many cases we do not have
17841 // hardware support for this operation. This is better expressed as an ADD
17843 if (N1C && (1 == N1C->getZExtValue())) {
17844 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17851 /// \brief Returns a vector of 0s if the node in input is a vector logical
17852 /// shift by a constant amount which is known to be bigger than or equal
17853 /// to the vector element size in bits.
17854 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17855 const X86Subtarget *Subtarget) {
17856 EVT VT = N->getValueType(0);
17858 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17859 (!Subtarget->hasInt256() ||
17860 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17863 SDValue Amt = N->getOperand(1);
17865 if (isSplatVector(Amt.getNode())) {
17866 SDValue SclrAmt = Amt->getOperand(0);
17867 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17868 APInt ShiftAmt = C->getAPIntValue();
17869 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17871 // SSE2/AVX2 logical shifts always return a vector of 0s
17872 // if the shift amount is bigger than or equal to
17873 // the element size. The constant shift amount will be
17874 // encoded as a 8-bit immediate.
17875 if (ShiftAmt.trunc(8).uge(MaxAmount))
17876 return getZeroVector(VT, Subtarget, DAG, DL);
17883 /// PerformShiftCombine - Combine shifts.
17884 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17885 TargetLowering::DAGCombinerInfo &DCI,
17886 const X86Subtarget *Subtarget) {
17887 if (N->getOpcode() == ISD::SHL) {
17888 SDValue V = PerformSHLCombine(N, DAG);
17889 if (V.getNode()) return V;
17892 if (N->getOpcode() != ISD::SRA) {
17893 // Try to fold this logical shift into a zero vector.
17894 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17895 if (V.getNode()) return V;
17901 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17902 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17903 // and friends. Likewise for OR -> CMPNEQSS.
17904 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17905 TargetLowering::DAGCombinerInfo &DCI,
17906 const X86Subtarget *Subtarget) {
17909 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17910 // we're requiring SSE2 for both.
17911 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17912 SDValue N0 = N->getOperand(0);
17913 SDValue N1 = N->getOperand(1);
17914 SDValue CMP0 = N0->getOperand(1);
17915 SDValue CMP1 = N1->getOperand(1);
17918 // The SETCCs should both refer to the same CMP.
17919 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17922 SDValue CMP00 = CMP0->getOperand(0);
17923 SDValue CMP01 = CMP0->getOperand(1);
17924 EVT VT = CMP00.getValueType();
17926 if (VT == MVT::f32 || VT == MVT::f64) {
17927 bool ExpectingFlags = false;
17928 // Check for any users that want flags:
17929 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17930 !ExpectingFlags && UI != UE; ++UI)
17931 switch (UI->getOpcode()) {
17936 ExpectingFlags = true;
17938 case ISD::CopyToReg:
17939 case ISD::SIGN_EXTEND:
17940 case ISD::ZERO_EXTEND:
17941 case ISD::ANY_EXTEND:
17945 if (!ExpectingFlags) {
17946 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17947 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17949 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17950 X86::CondCode tmp = cc0;
17955 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17956 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17957 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17958 // FIXME: need symbolic constants for these magic numbers.
17959 // See X86ATTInstPrinter.cpp:printSSECC().
17960 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17961 if (Subtarget->hasAVX512()) {
17962 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
17963 CMP01, DAG.getConstant(x86cc, MVT::i8));
17964 if (N->getValueType(0) != MVT::i1)
17965 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
17969 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
17970 CMP00.getValueType(), CMP00, CMP01,
17971 DAG.getConstant(x86cc, MVT::i8));
17972 MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
17973 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
17975 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
17976 DAG.getConstant(1, IntVT));
17977 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17978 return OneBitOfTruth;
17986 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17987 /// so it can be folded inside ANDNP.
17988 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17989 EVT VT = N->getValueType(0);
17991 // Match direct AllOnes for 128 and 256-bit vectors
17992 if (ISD::isBuildVectorAllOnes(N))
17995 // Look through a bit convert.
17996 if (N->getOpcode() == ISD::BITCAST)
17997 N = N->getOperand(0).getNode();
17999 // Sometimes the operand may come from a insert_subvector building a 256-bit
18001 if (VT.is256BitVector() &&
18002 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
18003 SDValue V1 = N->getOperand(0);
18004 SDValue V2 = N->getOperand(1);
18006 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
18007 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
18008 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
18009 ISD::isBuildVectorAllOnes(V2.getNode()))
18016 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
18017 // register. In most cases we actually compare or select YMM-sized registers
18018 // and mixing the two types creates horrible code. This method optimizes
18019 // some of the transition sequences.
18020 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
18021 TargetLowering::DAGCombinerInfo &DCI,
18022 const X86Subtarget *Subtarget) {
18023 EVT VT = N->getValueType(0);
18024 if (!VT.is256BitVector())
18027 assert((N->getOpcode() == ISD::ANY_EXTEND ||
18028 N->getOpcode() == ISD::ZERO_EXTEND ||
18029 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
18031 SDValue Narrow = N->getOperand(0);
18032 EVT NarrowVT = Narrow->getValueType(0);
18033 if (!NarrowVT.is128BitVector())
18036 if (Narrow->getOpcode() != ISD::XOR &&
18037 Narrow->getOpcode() != ISD::AND &&
18038 Narrow->getOpcode() != ISD::OR)
18041 SDValue N0 = Narrow->getOperand(0);
18042 SDValue N1 = Narrow->getOperand(1);
18045 // The Left side has to be a trunc.
18046 if (N0.getOpcode() != ISD::TRUNCATE)
18049 // The type of the truncated inputs.
18050 EVT WideVT = N0->getOperand(0)->getValueType(0);
18054 // The right side has to be a 'trunc' or a constant vector.
18055 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
18056 bool RHSConst = (isSplatVector(N1.getNode()) &&
18057 isa<ConstantSDNode>(N1->getOperand(0)));
18058 if (!RHSTrunc && !RHSConst)
18061 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18063 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
18066 // Set N0 and N1 to hold the inputs to the new wide operation.
18067 N0 = N0->getOperand(0);
18069 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
18070 N1->getOperand(0));
18071 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
18072 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
18073 } else if (RHSTrunc) {
18074 N1 = N1->getOperand(0);
18077 // Generate the wide operation.
18078 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
18079 unsigned Opcode = N->getOpcode();
18081 case ISD::ANY_EXTEND:
18083 case ISD::ZERO_EXTEND: {
18084 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
18085 APInt Mask = APInt::getAllOnesValue(InBits);
18086 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
18087 return DAG.getNode(ISD::AND, DL, VT,
18088 Op, DAG.getConstant(Mask, VT));
18090 case ISD::SIGN_EXTEND:
18091 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
18092 Op, DAG.getValueType(NarrowVT));
18094 llvm_unreachable("Unexpected opcode");
18098 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
18099 TargetLowering::DAGCombinerInfo &DCI,
18100 const X86Subtarget *Subtarget) {
18101 EVT VT = N->getValueType(0);
18102 if (DCI.isBeforeLegalizeOps())
18105 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18109 // Create BEXTR and BZHI instructions
18110 // BZHI is X & ((1 << Y) - 1)
18111 // BEXTR is ((X >> imm) & (2**size-1))
18112 if (VT == MVT::i32 || VT == MVT::i64) {
18113 SDValue N0 = N->getOperand(0);
18114 SDValue N1 = N->getOperand(1);
18117 if (Subtarget->hasBMI2()) {
18118 // Check for (and (add (shl 1, Y), -1), X)
18119 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
18120 SDValue N00 = N0.getOperand(0);
18121 if (N00.getOpcode() == ISD::SHL) {
18122 SDValue N001 = N00.getOperand(1);
18123 assert(N001.getValueType() == MVT::i8 && "unexpected type");
18124 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
18125 if (C && C->getZExtValue() == 1)
18126 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
18130 // Check for (and X, (add (shl 1, Y), -1))
18131 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
18132 SDValue N10 = N1.getOperand(0);
18133 if (N10.getOpcode() == ISD::SHL) {
18134 SDValue N101 = N10.getOperand(1);
18135 assert(N101.getValueType() == MVT::i8 && "unexpected type");
18136 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
18137 if (C && C->getZExtValue() == 1)
18138 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
18143 // Check for BEXTR.
18144 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
18145 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
18146 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
18147 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18148 if (MaskNode && ShiftNode) {
18149 uint64_t Mask = MaskNode->getZExtValue();
18150 uint64_t Shift = ShiftNode->getZExtValue();
18151 if (isMask_64(Mask)) {
18152 uint64_t MaskSize = CountPopulation_64(Mask);
18153 if (Shift + MaskSize <= VT.getSizeInBits())
18154 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
18155 DAG.getConstant(Shift | (MaskSize << 8), VT));
18163 // Want to form ANDNP nodes:
18164 // 1) In the hopes of then easily combining them with OR and AND nodes
18165 // to form PBLEND/PSIGN.
18166 // 2) To match ANDN packed intrinsics
18167 if (VT != MVT::v2i64 && VT != MVT::v4i64)
18170 SDValue N0 = N->getOperand(0);
18171 SDValue N1 = N->getOperand(1);
18174 // Check LHS for vnot
18175 if (N0.getOpcode() == ISD::XOR &&
18176 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
18177 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
18178 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
18180 // Check RHS for vnot
18181 if (N1.getOpcode() == ISD::XOR &&
18182 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
18183 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
18184 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
18189 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
18190 TargetLowering::DAGCombinerInfo &DCI,
18191 const X86Subtarget *Subtarget) {
18192 if (DCI.isBeforeLegalizeOps())
18195 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18199 SDValue N0 = N->getOperand(0);
18200 SDValue N1 = N->getOperand(1);
18201 EVT VT = N->getValueType(0);
18203 // look for psign/blend
18204 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
18205 if (!Subtarget->hasSSSE3() ||
18206 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
18209 // Canonicalize pandn to RHS
18210 if (N0.getOpcode() == X86ISD::ANDNP)
18212 // or (and (m, y), (pandn m, x))
18213 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
18214 SDValue Mask = N1.getOperand(0);
18215 SDValue X = N1.getOperand(1);
18217 if (N0.getOperand(0) == Mask)
18218 Y = N0.getOperand(1);
18219 if (N0.getOperand(1) == Mask)
18220 Y = N0.getOperand(0);
18222 // Check to see if the mask appeared in both the AND and ANDNP and
18226 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
18227 // Look through mask bitcast.
18228 if (Mask.getOpcode() == ISD::BITCAST)
18229 Mask = Mask.getOperand(0);
18230 if (X.getOpcode() == ISD::BITCAST)
18231 X = X.getOperand(0);
18232 if (Y.getOpcode() == ISD::BITCAST)
18233 Y = Y.getOperand(0);
18235 EVT MaskVT = Mask.getValueType();
18237 // Validate that the Mask operand is a vector sra node.
18238 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
18239 // there is no psrai.b
18240 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
18241 unsigned SraAmt = ~0;
18242 if (Mask.getOpcode() == ISD::SRA) {
18243 SDValue Amt = Mask.getOperand(1);
18244 if (isSplatVector(Amt.getNode())) {
18245 SDValue SclrAmt = Amt->getOperand(0);
18246 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
18247 SraAmt = C->getZExtValue();
18249 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
18250 SDValue SraC = Mask.getOperand(1);
18251 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
18253 if ((SraAmt + 1) != EltBits)
18258 // Now we know we at least have a plendvb with the mask val. See if
18259 // we can form a psignb/w/d.
18260 // psign = x.type == y.type == mask.type && y = sub(0, x);
18261 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
18262 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
18263 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
18264 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
18265 "Unsupported VT for PSIGN");
18266 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
18267 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18269 // PBLENDVB only available on SSE 4.1
18270 if (!Subtarget->hasSSE41())
18273 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
18275 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
18276 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
18277 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
18278 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
18279 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18283 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
18286 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
18287 MachineFunction &MF = DAG.getMachineFunction();
18288 bool OptForSize = MF.getFunction()->getAttributes().
18289 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
18291 // SHLD/SHRD instructions have lower register pressure, but on some
18292 // platforms they have higher latency than the equivalent
18293 // series of shifts/or that would otherwise be generated.
18294 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
18295 // have higher latencies and we are not optimizing for size.
18296 if (!OptForSize && Subtarget->isSHLDSlow())
18299 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
18301 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
18303 if (!N0.hasOneUse() || !N1.hasOneUse())
18306 SDValue ShAmt0 = N0.getOperand(1);
18307 if (ShAmt0.getValueType() != MVT::i8)
18309 SDValue ShAmt1 = N1.getOperand(1);
18310 if (ShAmt1.getValueType() != MVT::i8)
18312 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18313 ShAmt0 = ShAmt0.getOperand(0);
18314 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18315 ShAmt1 = ShAmt1.getOperand(0);
18318 unsigned Opc = X86ISD::SHLD;
18319 SDValue Op0 = N0.getOperand(0);
18320 SDValue Op1 = N1.getOperand(0);
18321 if (ShAmt0.getOpcode() == ISD::SUB) {
18322 Opc = X86ISD::SHRD;
18323 std::swap(Op0, Op1);
18324 std::swap(ShAmt0, ShAmt1);
18327 unsigned Bits = VT.getSizeInBits();
18328 if (ShAmt1.getOpcode() == ISD::SUB) {
18329 SDValue Sum = ShAmt1.getOperand(0);
18330 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18331 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18332 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18333 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18334 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18335 return DAG.getNode(Opc, DL, VT,
18337 DAG.getNode(ISD::TRUNCATE, DL,
18340 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18341 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18343 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18344 return DAG.getNode(Opc, DL, VT,
18345 N0.getOperand(0), N1.getOperand(0),
18346 DAG.getNode(ISD::TRUNCATE, DL,
18353 // Generate NEG and CMOV for integer abs.
18354 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18355 EVT VT = N->getValueType(0);
18357 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18358 // 8-bit integer abs to NEG and CMOV.
18359 if (VT.isInteger() && VT.getSizeInBits() == 8)
18362 SDValue N0 = N->getOperand(0);
18363 SDValue N1 = N->getOperand(1);
18366 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18367 // and change it to SUB and CMOV.
18368 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18369 N0.getOpcode() == ISD::ADD &&
18370 N0.getOperand(1) == N1 &&
18371 N1.getOpcode() == ISD::SRA &&
18372 N1.getOperand(0) == N0.getOperand(0))
18373 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18374 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18375 // Generate SUB & CMOV.
18376 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18377 DAG.getConstant(0, VT), N0.getOperand(0));
18379 SDValue Ops[] = { N0.getOperand(0), Neg,
18380 DAG.getConstant(X86::COND_GE, MVT::i8),
18381 SDValue(Neg.getNode(), 1) };
18382 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18383 Ops, array_lengthof(Ops));
18388 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18389 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18390 TargetLowering::DAGCombinerInfo &DCI,
18391 const X86Subtarget *Subtarget) {
18392 if (DCI.isBeforeLegalizeOps())
18395 if (Subtarget->hasCMov()) {
18396 SDValue RV = performIntegerAbsCombine(N, DAG);
18404 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18405 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18406 TargetLowering::DAGCombinerInfo &DCI,
18407 const X86Subtarget *Subtarget) {
18408 LoadSDNode *Ld = cast<LoadSDNode>(N);
18409 EVT RegVT = Ld->getValueType(0);
18410 EVT MemVT = Ld->getMemoryVT();
18412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18413 unsigned RegSz = RegVT.getSizeInBits();
18415 // On Sandybridge unaligned 256bit loads are inefficient.
18416 ISD::LoadExtType Ext = Ld->getExtensionType();
18417 unsigned Alignment = Ld->getAlignment();
18418 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18419 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18420 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18421 unsigned NumElems = RegVT.getVectorNumElements();
18425 SDValue Ptr = Ld->getBasePtr();
18426 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18428 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18430 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18431 Ld->getPointerInfo(), Ld->isVolatile(),
18432 Ld->isNonTemporal(), Ld->isInvariant(),
18434 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18435 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18436 Ld->getPointerInfo(), Ld->isVolatile(),
18437 Ld->isNonTemporal(), Ld->isInvariant(),
18438 std::min(16U, Alignment));
18439 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18441 Load2.getValue(1));
18443 SDValue NewVec = DAG.getUNDEF(RegVT);
18444 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18445 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18446 return DCI.CombineTo(N, NewVec, TF, true);
18449 // If this is a vector EXT Load then attempt to optimize it using a
18450 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18451 // expansion is still better than scalar code.
18452 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18453 // emit a shuffle and a arithmetic shift.
18454 // TODO: It is possible to support ZExt by zeroing the undef values
18455 // during the shuffle phase or after the shuffle.
18456 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18457 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18458 assert(MemVT != RegVT && "Cannot extend to the same type");
18459 assert(MemVT.isVector() && "Must load a vector from memory");
18461 unsigned NumElems = RegVT.getVectorNumElements();
18462 unsigned MemSz = MemVT.getSizeInBits();
18463 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18465 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18468 // All sizes must be a power of two.
18469 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18472 // Attempt to load the original value using scalar loads.
18473 // Find the largest scalar type that divides the total loaded size.
18474 MVT SclrLoadTy = MVT::i8;
18475 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18476 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18477 MVT Tp = (MVT::SimpleValueType)tp;
18478 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18483 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18484 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18486 SclrLoadTy = MVT::f64;
18488 // Calculate the number of scalar loads that we need to perform
18489 // in order to load our vector from memory.
18490 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18491 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18494 unsigned loadRegZize = RegSz;
18495 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18498 // Represent our vector as a sequence of elements which are the
18499 // largest scalar that we can load.
18500 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18501 loadRegZize/SclrLoadTy.getSizeInBits());
18503 // Represent the data using the same element type that is stored in
18504 // memory. In practice, we ''widen'' MemVT.
18506 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18507 loadRegZize/MemVT.getScalarType().getSizeInBits());
18509 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18510 "Invalid vector type");
18512 // We can't shuffle using an illegal type.
18513 if (!TLI.isTypeLegal(WideVecVT))
18516 SmallVector<SDValue, 8> Chains;
18517 SDValue Ptr = Ld->getBasePtr();
18518 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18519 TLI.getPointerTy());
18520 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18522 for (unsigned i = 0; i < NumLoads; ++i) {
18523 // Perform a single load.
18524 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18525 Ptr, Ld->getPointerInfo(),
18526 Ld->isVolatile(), Ld->isNonTemporal(),
18527 Ld->isInvariant(), Ld->getAlignment());
18528 Chains.push_back(ScalarLoad.getValue(1));
18529 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18530 // another round of DAGCombining.
18532 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18534 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18535 ScalarLoad, DAG.getIntPtrConstant(i));
18537 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18540 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18543 // Bitcast the loaded value to a vector of the original element type, in
18544 // the size of the target vector type.
18545 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18546 unsigned SizeRatio = RegSz/MemSz;
18548 if (Ext == ISD::SEXTLOAD) {
18549 // If we have SSE4.1 we can directly emit a VSEXT node.
18550 if (Subtarget->hasSSE41()) {
18551 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18552 return DCI.CombineTo(N, Sext, TF, true);
18555 // Otherwise we'll shuffle the small elements in the high bits of the
18556 // larger type and perform an arithmetic shift. If the shift is not legal
18557 // it's better to scalarize.
18558 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18561 // Redistribute the loaded elements into the different locations.
18562 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18563 for (unsigned i = 0; i != NumElems; ++i)
18564 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18566 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18567 DAG.getUNDEF(WideVecVT),
18570 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18572 // Build the arithmetic shift.
18573 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18574 MemVT.getVectorElementType().getSizeInBits();
18575 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18576 DAG.getConstant(Amt, RegVT));
18578 return DCI.CombineTo(N, Shuff, TF, true);
18581 // Redistribute the loaded elements into the different locations.
18582 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18583 for (unsigned i = 0; i != NumElems; ++i)
18584 ShuffleVec[i*SizeRatio] = i;
18586 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18587 DAG.getUNDEF(WideVecVT),
18590 // Bitcast to the requested type.
18591 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18592 // Replace the original load with the new sequence
18593 // and return the new chain.
18594 return DCI.CombineTo(N, Shuff, TF, true);
18600 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18601 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18602 const X86Subtarget *Subtarget) {
18603 StoreSDNode *St = cast<StoreSDNode>(N);
18604 EVT VT = St->getValue().getValueType();
18605 EVT StVT = St->getMemoryVT();
18607 SDValue StoredVal = St->getOperand(1);
18608 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18610 // If we are saving a concatenation of two XMM registers, perform two stores.
18611 // On Sandy Bridge, 256-bit memory operations are executed by two
18612 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18613 // memory operation.
18614 unsigned Alignment = St->getAlignment();
18615 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18616 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18617 StVT == VT && !IsAligned) {
18618 unsigned NumElems = VT.getVectorNumElements();
18622 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18623 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18625 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18626 SDValue Ptr0 = St->getBasePtr();
18627 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18629 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18630 St->getPointerInfo(), St->isVolatile(),
18631 St->isNonTemporal(), Alignment);
18632 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18633 St->getPointerInfo(), St->isVolatile(),
18634 St->isNonTemporal(),
18635 std::min(16U, Alignment));
18636 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18639 // Optimize trunc store (of multiple scalars) to shuffle and store.
18640 // First, pack all of the elements in one place. Next, store to memory
18641 // in fewer chunks.
18642 if (St->isTruncatingStore() && VT.isVector()) {
18643 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18644 unsigned NumElems = VT.getVectorNumElements();
18645 assert(StVT != VT && "Cannot truncate to the same type");
18646 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18647 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18649 // From, To sizes and ElemCount must be pow of two
18650 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18651 // We are going to use the original vector elt for storing.
18652 // Accumulated smaller vector elements must be a multiple of the store size.
18653 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18655 unsigned SizeRatio = FromSz / ToSz;
18657 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18659 // Create a type on which we perform the shuffle
18660 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18661 StVT.getScalarType(), NumElems*SizeRatio);
18663 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18665 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18666 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18667 for (unsigned i = 0; i != NumElems; ++i)
18668 ShuffleVec[i] = i * SizeRatio;
18670 // Can't shuffle using an illegal type.
18671 if (!TLI.isTypeLegal(WideVecVT))
18674 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18675 DAG.getUNDEF(WideVecVT),
18677 // At this point all of the data is stored at the bottom of the
18678 // register. We now need to save it to mem.
18680 // Find the largest store unit
18681 MVT StoreType = MVT::i8;
18682 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18683 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18684 MVT Tp = (MVT::SimpleValueType)tp;
18685 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18689 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18690 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18691 (64 <= NumElems * ToSz))
18692 StoreType = MVT::f64;
18694 // Bitcast the original vector into a vector of store-size units
18695 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18696 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18697 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18698 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18699 SmallVector<SDValue, 8> Chains;
18700 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18701 TLI.getPointerTy());
18702 SDValue Ptr = St->getBasePtr();
18704 // Perform one or more big stores into memory.
18705 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18706 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18707 StoreType, ShuffWide,
18708 DAG.getIntPtrConstant(i));
18709 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18710 St->getPointerInfo(), St->isVolatile(),
18711 St->isNonTemporal(), St->getAlignment());
18712 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18713 Chains.push_back(Ch);
18716 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18720 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18721 // the FP state in cases where an emms may be missing.
18722 // A preferable solution to the general problem is to figure out the right
18723 // places to insert EMMS. This qualifies as a quick hack.
18725 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18726 if (VT.getSizeInBits() != 64)
18729 const Function *F = DAG.getMachineFunction().getFunction();
18730 bool NoImplicitFloatOps = F->getAttributes().
18731 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18732 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18733 && Subtarget->hasSSE2();
18734 if ((VT.isVector() ||
18735 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18736 isa<LoadSDNode>(St->getValue()) &&
18737 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18738 St->getChain().hasOneUse() && !St->isVolatile()) {
18739 SDNode* LdVal = St->getValue().getNode();
18740 LoadSDNode *Ld = 0;
18741 int TokenFactorIndex = -1;
18742 SmallVector<SDValue, 8> Ops;
18743 SDNode* ChainVal = St->getChain().getNode();
18744 // Must be a store of a load. We currently handle two cases: the load
18745 // is a direct child, and it's under an intervening TokenFactor. It is
18746 // possible to dig deeper under nested TokenFactors.
18747 if (ChainVal == LdVal)
18748 Ld = cast<LoadSDNode>(St->getChain());
18749 else if (St->getValue().hasOneUse() &&
18750 ChainVal->getOpcode() == ISD::TokenFactor) {
18751 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18752 if (ChainVal->getOperand(i).getNode() == LdVal) {
18753 TokenFactorIndex = i;
18754 Ld = cast<LoadSDNode>(St->getValue());
18756 Ops.push_back(ChainVal->getOperand(i));
18760 if (!Ld || !ISD::isNormalLoad(Ld))
18763 // If this is not the MMX case, i.e. we are just turning i64 load/store
18764 // into f64 load/store, avoid the transformation if there are multiple
18765 // uses of the loaded value.
18766 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18771 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18772 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18774 if (Subtarget->is64Bit() || F64IsLegal) {
18775 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18776 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18777 Ld->getPointerInfo(), Ld->isVolatile(),
18778 Ld->isNonTemporal(), Ld->isInvariant(),
18779 Ld->getAlignment());
18780 SDValue NewChain = NewLd.getValue(1);
18781 if (TokenFactorIndex != -1) {
18782 Ops.push_back(NewChain);
18783 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18786 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18787 St->getPointerInfo(),
18788 St->isVolatile(), St->isNonTemporal(),
18789 St->getAlignment());
18792 // Otherwise, lower to two pairs of 32-bit loads / stores.
18793 SDValue LoAddr = Ld->getBasePtr();
18794 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18795 DAG.getConstant(4, MVT::i32));
18797 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18798 Ld->getPointerInfo(),
18799 Ld->isVolatile(), Ld->isNonTemporal(),
18800 Ld->isInvariant(), Ld->getAlignment());
18801 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18802 Ld->getPointerInfo().getWithOffset(4),
18803 Ld->isVolatile(), Ld->isNonTemporal(),
18805 MinAlign(Ld->getAlignment(), 4));
18807 SDValue NewChain = LoLd.getValue(1);
18808 if (TokenFactorIndex != -1) {
18809 Ops.push_back(LoLd);
18810 Ops.push_back(HiLd);
18811 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18815 LoAddr = St->getBasePtr();
18816 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18817 DAG.getConstant(4, MVT::i32));
18819 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18820 St->getPointerInfo(),
18821 St->isVolatile(), St->isNonTemporal(),
18822 St->getAlignment());
18823 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18824 St->getPointerInfo().getWithOffset(4),
18826 St->isNonTemporal(),
18827 MinAlign(St->getAlignment(), 4));
18828 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18833 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18834 /// and return the operands for the horizontal operation in LHS and RHS. A
18835 /// horizontal operation performs the binary operation on successive elements
18836 /// of its first operand, then on successive elements of its second operand,
18837 /// returning the resulting values in a vector. For example, if
18838 /// A = < float a0, float a1, float a2, float a3 >
18840 /// B = < float b0, float b1, float b2, float b3 >
18841 /// then the result of doing a horizontal operation on A and B is
18842 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18843 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18844 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18845 /// set to A, RHS to B, and the routine returns 'true'.
18846 /// Note that the binary operation should have the property that if one of the
18847 /// operands is UNDEF then the result is UNDEF.
18848 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18849 // Look for the following pattern: if
18850 // A = < float a0, float a1, float a2, float a3 >
18851 // B = < float b0, float b1, float b2, float b3 >
18853 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18854 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18855 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18856 // which is A horizontal-op B.
18858 // At least one of the operands should be a vector shuffle.
18859 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18860 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18863 MVT VT = LHS.getSimpleValueType();
18865 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18866 "Unsupported vector type for horizontal add/sub");
18868 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18869 // operate independently on 128-bit lanes.
18870 unsigned NumElts = VT.getVectorNumElements();
18871 unsigned NumLanes = VT.getSizeInBits()/128;
18872 unsigned NumLaneElts = NumElts / NumLanes;
18873 assert((NumLaneElts % 2 == 0) &&
18874 "Vector type should have an even number of elements in each lane");
18875 unsigned HalfLaneElts = NumLaneElts/2;
18877 // View LHS in the form
18878 // LHS = VECTOR_SHUFFLE A, B, LMask
18879 // If LHS is not a shuffle then pretend it is the shuffle
18880 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18881 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18884 SmallVector<int, 16> LMask(NumElts);
18885 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18886 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18887 A = LHS.getOperand(0);
18888 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18889 B = LHS.getOperand(1);
18890 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18891 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18893 if (LHS.getOpcode() != ISD::UNDEF)
18895 for (unsigned i = 0; i != NumElts; ++i)
18899 // Likewise, view RHS in the form
18900 // RHS = VECTOR_SHUFFLE C, D, RMask
18902 SmallVector<int, 16> RMask(NumElts);
18903 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18904 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18905 C = RHS.getOperand(0);
18906 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18907 D = RHS.getOperand(1);
18908 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18909 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18911 if (RHS.getOpcode() != ISD::UNDEF)
18913 for (unsigned i = 0; i != NumElts; ++i)
18917 // Check that the shuffles are both shuffling the same vectors.
18918 if (!(A == C && B == D) && !(A == D && B == C))
18921 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18922 if (!A.getNode() && !B.getNode())
18925 // If A and B occur in reverse order in RHS, then "swap" them (which means
18926 // rewriting the mask).
18928 CommuteVectorShuffleMask(RMask, NumElts);
18930 // At this point LHS and RHS are equivalent to
18931 // LHS = VECTOR_SHUFFLE A, B, LMask
18932 // RHS = VECTOR_SHUFFLE A, B, RMask
18933 // Check that the masks correspond to performing a horizontal operation.
18934 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18935 for (unsigned i = 0; i != NumLaneElts; ++i) {
18936 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18938 // Ignore any UNDEF components.
18939 if (LIdx < 0 || RIdx < 0 ||
18940 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18941 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18944 // Check that successive elements are being operated on. If not, this is
18945 // not a horizontal operation.
18946 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18947 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18948 if (!(LIdx == Index && RIdx == Index + 1) &&
18949 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18954 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18955 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18959 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18960 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18961 const X86Subtarget *Subtarget) {
18962 EVT VT = N->getValueType(0);
18963 SDValue LHS = N->getOperand(0);
18964 SDValue RHS = N->getOperand(1);
18966 // Try to synthesize horizontal adds from adds of shuffles.
18967 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18968 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18969 isHorizontalBinOp(LHS, RHS, true))
18970 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18974 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18975 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18976 const X86Subtarget *Subtarget) {
18977 EVT VT = N->getValueType(0);
18978 SDValue LHS = N->getOperand(0);
18979 SDValue RHS = N->getOperand(1);
18981 // Try to synthesize horizontal subs from subs of shuffles.
18982 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18983 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18984 isHorizontalBinOp(LHS, RHS, false))
18985 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18989 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18990 /// X86ISD::FXOR nodes.
18991 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18992 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18993 // F[X]OR(0.0, x) -> x
18994 // F[X]OR(x, 0.0) -> x
18995 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18996 if (C->getValueAPF().isPosZero())
18997 return N->getOperand(1);
18998 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18999 if (C->getValueAPF().isPosZero())
19000 return N->getOperand(0);
19004 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
19005 /// X86ISD::FMAX nodes.
19006 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
19007 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
19009 // Only perform optimizations if UnsafeMath is used.
19010 if (!DAG.getTarget().Options.UnsafeFPMath)
19013 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
19014 // into FMINC and FMAXC, which are Commutative operations.
19015 unsigned NewOp = 0;
19016 switch (N->getOpcode()) {
19017 default: llvm_unreachable("unknown opcode");
19018 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
19019 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
19022 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
19023 N->getOperand(0), N->getOperand(1));
19026 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
19027 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
19028 // FAND(0.0, x) -> 0.0
19029 // FAND(x, 0.0) -> 0.0
19030 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19031 if (C->getValueAPF().isPosZero())
19032 return N->getOperand(0);
19033 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19034 if (C->getValueAPF().isPosZero())
19035 return N->getOperand(1);
19039 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
19040 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
19041 // FANDN(x, 0.0) -> 0.0
19042 // FANDN(0.0, x) -> x
19043 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19044 if (C->getValueAPF().isPosZero())
19045 return N->getOperand(1);
19046 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19047 if (C->getValueAPF().isPosZero())
19048 return N->getOperand(1);
19052 static SDValue PerformBTCombine(SDNode *N,
19054 TargetLowering::DAGCombinerInfo &DCI) {
19055 // BT ignores high bits in the bit index operand.
19056 SDValue Op1 = N->getOperand(1);
19057 if (Op1.hasOneUse()) {
19058 unsigned BitWidth = Op1.getValueSizeInBits();
19059 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
19060 APInt KnownZero, KnownOne;
19061 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
19062 !DCI.isBeforeLegalizeOps());
19063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19064 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
19065 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
19066 DCI.CommitTargetLoweringOpt(TLO);
19071 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
19072 SDValue Op = N->getOperand(0);
19073 if (Op.getOpcode() == ISD::BITCAST)
19074 Op = Op.getOperand(0);
19075 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
19076 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
19077 VT.getVectorElementType().getSizeInBits() ==
19078 OpVT.getVectorElementType().getSizeInBits()) {
19079 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
19084 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
19085 const X86Subtarget *Subtarget) {
19086 EVT VT = N->getValueType(0);
19087 if (!VT.isVector())
19090 SDValue N0 = N->getOperand(0);
19091 SDValue N1 = N->getOperand(1);
19092 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
19095 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
19096 // both SSE and AVX2 since there is no sign-extended shift right
19097 // operation on a vector with 64-bit elements.
19098 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
19099 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
19100 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
19101 N0.getOpcode() == ISD::SIGN_EXTEND)) {
19102 SDValue N00 = N0.getOperand(0);
19104 // EXTLOAD has a better solution on AVX2,
19105 // it may be replaced with X86ISD::VSEXT node.
19106 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
19107 if (!ISD::isNormalLoad(N00.getNode()))
19110 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
19111 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
19113 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
19119 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
19120 TargetLowering::DAGCombinerInfo &DCI,
19121 const X86Subtarget *Subtarget) {
19122 if (!DCI.isBeforeLegalizeOps())
19125 if (!Subtarget->hasFp256())
19128 EVT VT = N->getValueType(0);
19129 if (VT.isVector() && VT.getSizeInBits() == 256) {
19130 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19138 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
19139 const X86Subtarget* Subtarget) {
19141 EVT VT = N->getValueType(0);
19143 // Let legalize expand this if it isn't a legal type yet.
19144 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19147 EVT ScalarVT = VT.getScalarType();
19148 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
19149 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
19152 SDValue A = N->getOperand(0);
19153 SDValue B = N->getOperand(1);
19154 SDValue C = N->getOperand(2);
19156 bool NegA = (A.getOpcode() == ISD::FNEG);
19157 bool NegB = (B.getOpcode() == ISD::FNEG);
19158 bool NegC = (C.getOpcode() == ISD::FNEG);
19160 // Negative multiplication when NegA xor NegB
19161 bool NegMul = (NegA != NegB);
19163 A = A.getOperand(0);
19165 B = B.getOperand(0);
19167 C = C.getOperand(0);
19171 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
19173 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
19175 return DAG.getNode(Opcode, dl, VT, A, B, C);
19178 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
19179 TargetLowering::DAGCombinerInfo &DCI,
19180 const X86Subtarget *Subtarget) {
19181 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
19182 // (and (i32 x86isd::setcc_carry), 1)
19183 // This eliminates the zext. This transformation is necessary because
19184 // ISD::SETCC is always legalized to i8.
19186 SDValue N0 = N->getOperand(0);
19187 EVT VT = N->getValueType(0);
19189 if (N0.getOpcode() == ISD::AND &&
19191 N0.getOperand(0).hasOneUse()) {
19192 SDValue N00 = N0.getOperand(0);
19193 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19194 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
19195 if (!C || C->getZExtValue() != 1)
19197 return DAG.getNode(ISD::AND, dl, VT,
19198 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19199 N00.getOperand(0), N00.getOperand(1)),
19200 DAG.getConstant(1, VT));
19204 if (N0.getOpcode() == ISD::TRUNCATE &&
19206 N0.getOperand(0).hasOneUse()) {
19207 SDValue N00 = N0.getOperand(0);
19208 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19209 return DAG.getNode(ISD::AND, dl, VT,
19210 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19211 N00.getOperand(0), N00.getOperand(1)),
19212 DAG.getConstant(1, VT));
19215 if (VT.is256BitVector()) {
19216 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19224 // Optimize x == -y --> x+y == 0
19225 // x != -y --> x+y != 0
19226 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
19227 const X86Subtarget* Subtarget) {
19228 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
19229 SDValue LHS = N->getOperand(0);
19230 SDValue RHS = N->getOperand(1);
19231 EVT VT = N->getValueType(0);
19234 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
19235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
19236 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
19237 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19238 LHS.getValueType(), RHS, LHS.getOperand(1));
19239 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19240 addV, DAG.getConstant(0, addV.getValueType()), CC);
19242 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
19243 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
19244 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
19245 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19246 RHS.getValueType(), LHS, RHS.getOperand(1));
19247 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19248 addV, DAG.getConstant(0, addV.getValueType()), CC);
19251 if (VT.getScalarType() == MVT::i1) {
19252 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
19253 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
19254 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
19255 if (!IsSEXT0 && !IsVZero0)
19257 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
19258 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
19259 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
19261 if (!IsSEXT1 && !IsVZero1)
19264 if (IsSEXT0 && IsVZero1) {
19265 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
19266 if (CC == ISD::SETEQ)
19267 return DAG.getNOT(DL, LHS.getOperand(0), VT);
19268 return LHS.getOperand(0);
19270 if (IsSEXT1 && IsVZero0) {
19271 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
19272 if (CC == ISD::SETEQ)
19273 return DAG.getNOT(DL, RHS.getOperand(0), VT);
19274 return RHS.getOperand(0);
19281 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
19282 // as "sbb reg,reg", since it can be extended without zext and produces
19283 // an all-ones bit which is more useful than 0/1 in some cases.
19284 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
19287 return DAG.getNode(ISD::AND, DL, VT,
19288 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19289 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
19290 DAG.getConstant(1, VT));
19291 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
19292 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
19293 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19294 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
19297 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
19298 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
19299 TargetLowering::DAGCombinerInfo &DCI,
19300 const X86Subtarget *Subtarget) {
19302 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
19303 SDValue EFLAGS = N->getOperand(1);
19305 if (CC == X86::COND_A) {
19306 // Try to convert COND_A into COND_B in an attempt to facilitate
19307 // materializing "setb reg".
19309 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
19310 // cannot take an immediate as its first operand.
19312 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
19313 EFLAGS.getValueType().isInteger() &&
19314 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
19315 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
19316 EFLAGS.getNode()->getVTList(),
19317 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
19318 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
19319 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
19323 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
19324 // a zext and produces an all-ones bit which is more useful than 0/1 in some
19326 if (CC == X86::COND_B)
19327 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
19331 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19332 if (Flags.getNode()) {
19333 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19334 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19340 // Optimize branch condition evaluation.
19342 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19343 TargetLowering::DAGCombinerInfo &DCI,
19344 const X86Subtarget *Subtarget) {
19346 SDValue Chain = N->getOperand(0);
19347 SDValue Dest = N->getOperand(1);
19348 SDValue EFLAGS = N->getOperand(3);
19349 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19353 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19354 if (Flags.getNode()) {
19355 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19356 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19363 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19364 const X86TargetLowering *XTLI) {
19365 SDValue Op0 = N->getOperand(0);
19366 EVT InVT = Op0->getValueType(0);
19368 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19369 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19371 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19372 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19373 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19376 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19377 // a 32-bit target where SSE doesn't support i64->FP operations.
19378 if (Op0.getOpcode() == ISD::LOAD) {
19379 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19380 EVT VT = Ld->getValueType(0);
19381 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19382 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19383 !XTLI->getSubtarget()->is64Bit() &&
19385 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19386 Ld->getChain(), Op0, DAG);
19387 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19394 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19395 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19396 X86TargetLowering::DAGCombinerInfo &DCI) {
19397 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19398 // the result is either zero or one (depending on the input carry bit).
19399 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19400 if (X86::isZeroNode(N->getOperand(0)) &&
19401 X86::isZeroNode(N->getOperand(1)) &&
19402 // We don't have a good way to replace an EFLAGS use, so only do this when
19404 SDValue(N, 1).use_empty()) {
19406 EVT VT = N->getValueType(0);
19407 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19408 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19409 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19410 DAG.getConstant(X86::COND_B,MVT::i8),
19412 DAG.getConstant(1, VT));
19413 return DCI.CombineTo(N, Res1, CarryOut);
19419 // fold (add Y, (sete X, 0)) -> adc 0, Y
19420 // (add Y, (setne X, 0)) -> sbb -1, Y
19421 // (sub (sete X, 0), Y) -> sbb 0, Y
19422 // (sub (setne X, 0), Y) -> adc -1, Y
19423 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19426 // Look through ZExts.
19427 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19428 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19431 SDValue SetCC = Ext.getOperand(0);
19432 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19435 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19436 if (CC != X86::COND_E && CC != X86::COND_NE)
19439 SDValue Cmp = SetCC.getOperand(1);
19440 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19441 !X86::isZeroNode(Cmp.getOperand(1)) ||
19442 !Cmp.getOperand(0).getValueType().isInteger())
19445 SDValue CmpOp0 = Cmp.getOperand(0);
19446 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19447 DAG.getConstant(1, CmpOp0.getValueType()));
19449 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19450 if (CC == X86::COND_NE)
19451 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19452 DL, OtherVal.getValueType(), OtherVal,
19453 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19454 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19455 DL, OtherVal.getValueType(), OtherVal,
19456 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19459 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19460 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19461 const X86Subtarget *Subtarget) {
19462 EVT VT = N->getValueType(0);
19463 SDValue Op0 = N->getOperand(0);
19464 SDValue Op1 = N->getOperand(1);
19466 // Try to synthesize horizontal adds from adds of shuffles.
19467 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19468 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19469 isHorizontalBinOp(Op0, Op1, true))
19470 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19472 return OptimizeConditionalInDecrement(N, DAG);
19475 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19476 const X86Subtarget *Subtarget) {
19477 SDValue Op0 = N->getOperand(0);
19478 SDValue Op1 = N->getOperand(1);
19480 // X86 can't encode an immediate LHS of a sub. See if we can push the
19481 // negation into a preceding instruction.
19482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19483 // If the RHS of the sub is a XOR with one use and a constant, invert the
19484 // immediate. Then add one to the LHS of the sub so we can turn
19485 // X-Y -> X+~Y+1, saving one register.
19486 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19487 isa<ConstantSDNode>(Op1.getOperand(1))) {
19488 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19489 EVT VT = Op0.getValueType();
19490 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19492 DAG.getConstant(~XorC, VT));
19493 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19494 DAG.getConstant(C->getAPIntValue()+1, VT));
19498 // Try to synthesize horizontal adds from adds of shuffles.
19499 EVT VT = N->getValueType(0);
19500 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19501 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19502 isHorizontalBinOp(Op0, Op1, true))
19503 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19505 return OptimizeConditionalInDecrement(N, DAG);
19508 /// performVZEXTCombine - Performs build vector combines
19509 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19510 TargetLowering::DAGCombinerInfo &DCI,
19511 const X86Subtarget *Subtarget) {
19512 // (vzext (bitcast (vzext (x)) -> (vzext x)
19513 SDValue In = N->getOperand(0);
19514 while (In.getOpcode() == ISD::BITCAST)
19515 In = In.getOperand(0);
19517 if (In.getOpcode() != X86ISD::VZEXT)
19520 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19524 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19525 DAGCombinerInfo &DCI) const {
19526 SelectionDAG &DAG = DCI.DAG;
19527 switch (N->getOpcode()) {
19529 case ISD::EXTRACT_VECTOR_ELT:
19530 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19532 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19533 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19534 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19535 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19536 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19537 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19540 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19541 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19542 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19543 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19544 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19545 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19546 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19547 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19548 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19550 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19552 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19553 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19554 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19555 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19556 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19557 case ISD::ANY_EXTEND:
19558 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19559 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19560 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19561 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19562 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
19563 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19564 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19565 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19566 case X86ISD::SHUFP: // Handle all target specific shuffles
19567 case X86ISD::PALIGNR:
19568 case X86ISD::UNPCKH:
19569 case X86ISD::UNPCKL:
19570 case X86ISD::MOVHLPS:
19571 case X86ISD::MOVLHPS:
19572 case X86ISD::PSHUFD:
19573 case X86ISD::PSHUFHW:
19574 case X86ISD::PSHUFLW:
19575 case X86ISD::MOVSS:
19576 case X86ISD::MOVSD:
19577 case X86ISD::VPERMILP:
19578 case X86ISD::VPERM2X128:
19579 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19580 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19586 /// isTypeDesirableForOp - Return true if the target has native support for
19587 /// the specified value type and it is 'desirable' to use the type for the
19588 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19589 /// instruction encodings are longer and some i16 instructions are slow.
19590 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19591 if (!isTypeLegal(VT))
19593 if (VT != MVT::i16)
19600 case ISD::SIGN_EXTEND:
19601 case ISD::ZERO_EXTEND:
19602 case ISD::ANY_EXTEND:
19615 /// IsDesirableToPromoteOp - This method query the target whether it is
19616 /// beneficial for dag combiner to promote the specified node. If true, it
19617 /// should return the desired promotion type by reference.
19618 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19619 EVT VT = Op.getValueType();
19620 if (VT != MVT::i16)
19623 bool Promote = false;
19624 bool Commute = false;
19625 switch (Op.getOpcode()) {
19628 LoadSDNode *LD = cast<LoadSDNode>(Op);
19629 // If the non-extending load has a single use and it's not live out, then it
19630 // might be folded.
19631 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19632 Op.hasOneUse()*/) {
19633 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19634 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19635 // The only case where we'd want to promote LOAD (rather then it being
19636 // promoted as an operand is when it's only use is liveout.
19637 if (UI->getOpcode() != ISD::CopyToReg)
19644 case ISD::SIGN_EXTEND:
19645 case ISD::ZERO_EXTEND:
19646 case ISD::ANY_EXTEND:
19651 SDValue N0 = Op.getOperand(0);
19652 // Look out for (store (shl (load), x)).
19653 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19666 SDValue N0 = Op.getOperand(0);
19667 SDValue N1 = Op.getOperand(1);
19668 if (!Commute && MayFoldLoad(N1))
19670 // Avoid disabling potential load folding opportunities.
19671 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19673 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19683 //===----------------------------------------------------------------------===//
19684 // X86 Inline Assembly Support
19685 //===----------------------------------------------------------------------===//
19688 // Helper to match a string separated by whitespace.
19689 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19690 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19692 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19693 StringRef piece(*args[i]);
19694 if (!s.startswith(piece)) // Check if the piece matches.
19697 s = s.substr(piece.size());
19698 StringRef::size_type pos = s.find_first_not_of(" \t");
19699 if (pos == 0) // We matched a prefix.
19707 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19710 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19712 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19713 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19714 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19715 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19717 if (AsmPieces.size() == 3)
19719 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19726 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19727 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19729 std::string AsmStr = IA->getAsmString();
19731 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19732 if (!Ty || Ty->getBitWidth() % 16 != 0)
19735 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19736 SmallVector<StringRef, 4> AsmPieces;
19737 SplitString(AsmStr, AsmPieces, ";\n");
19739 switch (AsmPieces.size()) {
19740 default: return false;
19742 // FIXME: this should verify that we are targeting a 486 or better. If not,
19743 // we will turn this bswap into something that will be lowered to logical
19744 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19745 // lower so don't worry about this.
19747 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19748 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19749 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19750 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19751 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19752 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19753 // No need to check constraints, nothing other than the equivalent of
19754 // "=r,0" would be valid here.
19755 return IntrinsicLowering::LowerToByteSwap(CI);
19758 // rorw $$8, ${0:w} --> llvm.bswap.i16
19759 if (CI->getType()->isIntegerTy(16) &&
19760 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19761 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19762 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19764 const std::string &ConstraintsStr = IA->getConstraintString();
19765 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19766 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19767 if (clobbersFlagRegisters(AsmPieces))
19768 return IntrinsicLowering::LowerToByteSwap(CI);
19772 if (CI->getType()->isIntegerTy(32) &&
19773 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19774 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19775 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19776 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19778 const std::string &ConstraintsStr = IA->getConstraintString();
19779 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19780 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19781 if (clobbersFlagRegisters(AsmPieces))
19782 return IntrinsicLowering::LowerToByteSwap(CI);
19785 if (CI->getType()->isIntegerTy(64)) {
19786 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19787 if (Constraints.size() >= 2 &&
19788 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19789 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19790 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19791 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19792 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19793 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19794 return IntrinsicLowering::LowerToByteSwap(CI);
19802 /// getConstraintType - Given a constraint letter, return the type of
19803 /// constraint it is for this target.
19804 X86TargetLowering::ConstraintType
19805 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19806 if (Constraint.size() == 1) {
19807 switch (Constraint[0]) {
19818 return C_RegisterClass;
19842 return TargetLowering::getConstraintType(Constraint);
19845 /// Examine constraint type and operand type and determine a weight value.
19846 /// This object must already have been set up with the operand type
19847 /// and the current alternative constraint selected.
19848 TargetLowering::ConstraintWeight
19849 X86TargetLowering::getSingleConstraintMatchWeight(
19850 AsmOperandInfo &info, const char *constraint) const {
19851 ConstraintWeight weight = CW_Invalid;
19852 Value *CallOperandVal = info.CallOperandVal;
19853 // If we don't have a value, we can't do a match,
19854 // but allow it at the lowest weight.
19855 if (CallOperandVal == NULL)
19857 Type *type = CallOperandVal->getType();
19858 // Look at the constraint type.
19859 switch (*constraint) {
19861 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19872 if (CallOperandVal->getType()->isIntegerTy())
19873 weight = CW_SpecificReg;
19878 if (type->isFloatingPointTy())
19879 weight = CW_SpecificReg;
19882 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19883 weight = CW_SpecificReg;
19887 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19888 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19889 weight = CW_Register;
19892 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19893 if (C->getZExtValue() <= 31)
19894 weight = CW_Constant;
19898 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19899 if (C->getZExtValue() <= 63)
19900 weight = CW_Constant;
19904 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19905 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19906 weight = CW_Constant;
19910 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19911 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19912 weight = CW_Constant;
19916 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19917 if (C->getZExtValue() <= 3)
19918 weight = CW_Constant;
19922 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19923 if (C->getZExtValue() <= 0xff)
19924 weight = CW_Constant;
19929 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19930 weight = CW_Constant;
19934 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19935 if ((C->getSExtValue() >= -0x80000000LL) &&
19936 (C->getSExtValue() <= 0x7fffffffLL))
19937 weight = CW_Constant;
19941 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19942 if (C->getZExtValue() <= 0xffffffff)
19943 weight = CW_Constant;
19950 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19951 /// with another that has more specific requirements based on the type of the
19952 /// corresponding operand.
19953 const char *X86TargetLowering::
19954 LowerXConstraint(EVT ConstraintVT) const {
19955 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19956 // 'f' like normal targets.
19957 if (ConstraintVT.isFloatingPoint()) {
19958 if (Subtarget->hasSSE2())
19960 if (Subtarget->hasSSE1())
19964 return TargetLowering::LowerXConstraint(ConstraintVT);
19967 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19968 /// vector. If it is invalid, don't add anything to Ops.
19969 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19970 std::string &Constraint,
19971 std::vector<SDValue>&Ops,
19972 SelectionDAG &DAG) const {
19973 SDValue Result(0, 0);
19975 // Only support length 1 constraints for now.
19976 if (Constraint.length() > 1) return;
19978 char ConstraintLetter = Constraint[0];
19979 switch (ConstraintLetter) {
19982 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19983 if (C->getZExtValue() <= 31) {
19984 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19990 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19991 if (C->getZExtValue() <= 63) {
19992 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19998 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19999 if (isInt<8>(C->getSExtValue())) {
20000 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20007 if (C->getZExtValue() <= 255) {
20008 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20014 // 32-bit signed value
20015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20016 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20017 C->getSExtValue())) {
20018 // Widen to 64 bits here to get it sign extended.
20019 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
20022 // FIXME gcc accepts some relocatable values here too, but only in certain
20023 // memory models; it's complicated.
20028 // 32-bit unsigned value
20029 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20030 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20031 C->getZExtValue())) {
20032 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20036 // FIXME gcc accepts some relocatable values here too, but only in certain
20037 // memory models; it's complicated.
20041 // Literal immediates are always ok.
20042 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
20043 // Widen to 64 bits here to get it sign extended.
20044 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
20048 // In any sort of PIC mode addresses need to be computed at runtime by
20049 // adding in a register or some sort of table lookup. These can't
20050 // be used as immediates.
20051 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
20054 // If we are in non-pic codegen mode, we allow the address of a global (with
20055 // an optional displacement) to be used with 'i'.
20056 GlobalAddressSDNode *GA = 0;
20057 int64_t Offset = 0;
20059 // Match either (GA), (GA+C), (GA+C1+C2), etc.
20061 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
20062 Offset += GA->getOffset();
20064 } else if (Op.getOpcode() == ISD::ADD) {
20065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20066 Offset += C->getZExtValue();
20067 Op = Op.getOperand(0);
20070 } else if (Op.getOpcode() == ISD::SUB) {
20071 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20072 Offset += -C->getZExtValue();
20073 Op = Op.getOperand(0);
20078 // Otherwise, this isn't something we can handle, reject it.
20082 const GlobalValue *GV = GA->getGlobal();
20083 // If we require an extra load to get this address, as in PIC mode, we
20084 // can't accept it.
20085 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
20086 getTargetMachine())))
20089 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
20090 GA->getValueType(0), Offset);
20095 if (Result.getNode()) {
20096 Ops.push_back(Result);
20099 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
20102 std::pair<unsigned, const TargetRegisterClass*>
20103 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
20105 // First, see if this is a constraint that directly corresponds to an LLVM
20107 if (Constraint.size() == 1) {
20108 // GCC Constraint Letters
20109 switch (Constraint[0]) {
20111 // TODO: Slight differences here in allocation order and leaving
20112 // RIP in the class. Do they matter any more here than they do
20113 // in the normal allocation?
20114 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
20115 if (Subtarget->is64Bit()) {
20116 if (VT == MVT::i32 || VT == MVT::f32)
20117 return std::make_pair(0U, &X86::GR32RegClass);
20118 if (VT == MVT::i16)
20119 return std::make_pair(0U, &X86::GR16RegClass);
20120 if (VT == MVT::i8 || VT == MVT::i1)
20121 return std::make_pair(0U, &X86::GR8RegClass);
20122 if (VT == MVT::i64 || VT == MVT::f64)
20123 return std::make_pair(0U, &X86::GR64RegClass);
20126 // 32-bit fallthrough
20127 case 'Q': // Q_REGS
20128 if (VT == MVT::i32 || VT == MVT::f32)
20129 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
20130 if (VT == MVT::i16)
20131 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
20132 if (VT == MVT::i8 || VT == MVT::i1)
20133 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
20134 if (VT == MVT::i64)
20135 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
20137 case 'r': // GENERAL_REGS
20138 case 'l': // INDEX_REGS
20139 if (VT == MVT::i8 || VT == MVT::i1)
20140 return std::make_pair(0U, &X86::GR8RegClass);
20141 if (VT == MVT::i16)
20142 return std::make_pair(0U, &X86::GR16RegClass);
20143 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
20144 return std::make_pair(0U, &X86::GR32RegClass);
20145 return std::make_pair(0U, &X86::GR64RegClass);
20146 case 'R': // LEGACY_REGS
20147 if (VT == MVT::i8 || VT == MVT::i1)
20148 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
20149 if (VT == MVT::i16)
20150 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
20151 if (VT == MVT::i32 || !Subtarget->is64Bit())
20152 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
20153 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
20154 case 'f': // FP Stack registers.
20155 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
20156 // value to the correct fpstack register class.
20157 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
20158 return std::make_pair(0U, &X86::RFP32RegClass);
20159 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
20160 return std::make_pair(0U, &X86::RFP64RegClass);
20161 return std::make_pair(0U, &X86::RFP80RegClass);
20162 case 'y': // MMX_REGS if MMX allowed.
20163 if (!Subtarget->hasMMX()) break;
20164 return std::make_pair(0U, &X86::VR64RegClass);
20165 case 'Y': // SSE_REGS if SSE2 allowed
20166 if (!Subtarget->hasSSE2()) break;
20168 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
20169 if (!Subtarget->hasSSE1()) break;
20171 switch (VT.SimpleTy) {
20173 // Scalar SSE types.
20176 return std::make_pair(0U, &X86::FR32RegClass);
20179 return std::make_pair(0U, &X86::FR64RegClass);
20187 return std::make_pair(0U, &X86::VR128RegClass);
20195 return std::make_pair(0U, &X86::VR256RegClass);
20200 return std::make_pair(0U, &X86::VR512RegClass);
20206 // Use the default implementation in TargetLowering to convert the register
20207 // constraint into a member of a register class.
20208 std::pair<unsigned, const TargetRegisterClass*> Res;
20209 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
20211 // Not found as a standard register?
20212 if (Res.second == 0) {
20213 // Map st(0) -> st(7) -> ST0
20214 if (Constraint.size() == 7 && Constraint[0] == '{' &&
20215 tolower(Constraint[1]) == 's' &&
20216 tolower(Constraint[2]) == 't' &&
20217 Constraint[3] == '(' &&
20218 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
20219 Constraint[5] == ')' &&
20220 Constraint[6] == '}') {
20222 Res.first = X86::ST0+Constraint[4]-'0';
20223 Res.second = &X86::RFP80RegClass;
20227 // GCC allows "st(0)" to be called just plain "st".
20228 if (StringRef("{st}").equals_lower(Constraint)) {
20229 Res.first = X86::ST0;
20230 Res.second = &X86::RFP80RegClass;
20235 if (StringRef("{flags}").equals_lower(Constraint)) {
20236 Res.first = X86::EFLAGS;
20237 Res.second = &X86::CCRRegClass;
20241 // 'A' means EAX + EDX.
20242 if (Constraint == "A") {
20243 Res.first = X86::EAX;
20244 Res.second = &X86::GR32_ADRegClass;
20250 // Otherwise, check to see if this is a register class of the wrong value
20251 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
20252 // turn into {ax},{dx}.
20253 if (Res.second->hasType(VT))
20254 return Res; // Correct type already, nothing to do.
20256 // All of the single-register GCC register classes map their values onto
20257 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
20258 // really want an 8-bit or 32-bit register, map to the appropriate register
20259 // class and return the appropriate register.
20260 if (Res.second == &X86::GR16RegClass) {
20261 if (VT == MVT::i8 || VT == MVT::i1) {
20262 unsigned DestReg = 0;
20263 switch (Res.first) {
20265 case X86::AX: DestReg = X86::AL; break;
20266 case X86::DX: DestReg = X86::DL; break;
20267 case X86::CX: DestReg = X86::CL; break;
20268 case X86::BX: DestReg = X86::BL; break;
20271 Res.first = DestReg;
20272 Res.second = &X86::GR8RegClass;
20274 } else if (VT == MVT::i32 || VT == MVT::f32) {
20275 unsigned DestReg = 0;
20276 switch (Res.first) {
20278 case X86::AX: DestReg = X86::EAX; break;
20279 case X86::DX: DestReg = X86::EDX; break;
20280 case X86::CX: DestReg = X86::ECX; break;
20281 case X86::BX: DestReg = X86::EBX; break;
20282 case X86::SI: DestReg = X86::ESI; break;
20283 case X86::DI: DestReg = X86::EDI; break;
20284 case X86::BP: DestReg = X86::EBP; break;
20285 case X86::SP: DestReg = X86::ESP; break;
20288 Res.first = DestReg;
20289 Res.second = &X86::GR32RegClass;
20291 } else if (VT == MVT::i64 || VT == MVT::f64) {
20292 unsigned DestReg = 0;
20293 switch (Res.first) {
20295 case X86::AX: DestReg = X86::RAX; break;
20296 case X86::DX: DestReg = X86::RDX; break;
20297 case X86::CX: DestReg = X86::RCX; break;
20298 case X86::BX: DestReg = X86::RBX; break;
20299 case X86::SI: DestReg = X86::RSI; break;
20300 case X86::DI: DestReg = X86::RDI; break;
20301 case X86::BP: DestReg = X86::RBP; break;
20302 case X86::SP: DestReg = X86::RSP; break;
20305 Res.first = DestReg;
20306 Res.second = &X86::GR64RegClass;
20309 } else if (Res.second == &X86::FR32RegClass ||
20310 Res.second == &X86::FR64RegClass ||
20311 Res.second == &X86::VR128RegClass ||
20312 Res.second == &X86::VR256RegClass ||
20313 Res.second == &X86::FR32XRegClass ||
20314 Res.second == &X86::FR64XRegClass ||
20315 Res.second == &X86::VR128XRegClass ||
20316 Res.second == &X86::VR256XRegClass ||
20317 Res.second == &X86::VR512RegClass) {
20318 // Handle references to XMM physical registers that got mapped into the
20319 // wrong class. This can happen with constraints like {xmm0} where the
20320 // target independent register mapper will just pick the first match it can
20321 // find, ignoring the required type.
20323 if (VT == MVT::f32 || VT == MVT::i32)
20324 Res.second = &X86::FR32RegClass;
20325 else if (VT == MVT::f64 || VT == MVT::i64)
20326 Res.second = &X86::FR64RegClass;
20327 else if (X86::VR128RegClass.hasType(VT))
20328 Res.second = &X86::VR128RegClass;
20329 else if (X86::VR256RegClass.hasType(VT))
20330 Res.second = &X86::VR256RegClass;
20331 else if (X86::VR512RegClass.hasType(VT))
20332 Res.second = &X86::VR512RegClass;