1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/CommandLine.h"
45 DisableMMX("disable-mmx", cl::Hidden);
47 // Forward declarations.
48 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
50 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
51 : TargetLowering(TM) {
52 Subtarget = &TM.getSubtarget<X86Subtarget>();
53 X86ScalarSSEf64 = Subtarget->hasSSE2();
54 X86ScalarSSEf32 = Subtarget->hasSSE1();
55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
59 RegInfo = TM.getRegisterInfo();
62 // Set up the TargetLowering object.
64 // X86 is weird, it always uses i8 for shift amounts and setcc results.
65 setShiftAmountType(MVT::i8);
66 setBooleanContents(ZeroOrOneBooleanContent);
67 setSchedulingPreference(SchedulingForRegPressure);
68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
119 if (X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
122 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
123 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
125 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
128 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
130 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
132 // SSE has no i16 to fp conversion, only i32
133 if (X86ScalarSSEf32) {
134 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
135 // f32 and f64 cases are Legal, f80 case is not
136 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
138 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
139 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
142 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
143 // are Legal, f80 is custom lowered.
144 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
145 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
147 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
149 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
152 if (X86ScalarSSEf32) {
153 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
154 // f32 and f64 cases are Legal, f80 case is not
155 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
157 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
158 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
161 // Handle FP_TO_UINT by promoting the destination to a larger signed
163 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
164 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
165 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
167 if (Subtarget->is64Bit()) {
168 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
169 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
171 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
172 // Expand FP_TO_UINT into a select.
173 // FIXME: We would like to use a Custom expander here eventually to do
174 // the optimal thing for SSE vs. the default expansion in the legalizer.
175 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
177 // With SSE3 we can use fisttpll to convert to a signed i64.
178 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
181 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
182 if (!X86ScalarSSEf64) {
183 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
184 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
187 // Scalar integer divide and remainder are lowered to use operations that
188 // produce two results, to match the available instructions. This exposes
189 // the two-result form to trivial CSE, which is able to combine x/y and x%y
190 // into a single instruction.
192 // Scalar integer multiply-high is also lowered to use two-result
193 // operations, to match the available instructions. However, plain multiply
194 // (low) operations are left as Legal, as there are single-result
195 // instructions for this in x86. Using the two-result multiply instructions
196 // when both high and low results are needed must be arranged by dagcombine.
197 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
198 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
199 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
200 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
201 setOperationAction(ISD::SREM , MVT::i8 , Expand);
202 setOperationAction(ISD::UREM , MVT::i8 , Expand);
203 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
204 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
205 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
206 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
207 setOperationAction(ISD::SREM , MVT::i16 , Expand);
208 setOperationAction(ISD::UREM , MVT::i16 , Expand);
209 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
210 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
211 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
212 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
213 setOperationAction(ISD::SREM , MVT::i32 , Expand);
214 setOperationAction(ISD::UREM , MVT::i32 , Expand);
215 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
216 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
217 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
218 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
219 setOperationAction(ISD::SREM , MVT::i64 , Expand);
220 setOperationAction(ISD::UREM , MVT::i64 , Expand);
222 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
223 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
224 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
225 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
226 if (Subtarget->is64Bit())
227 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
231 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
232 setOperationAction(ISD::FREM , MVT::f32 , Expand);
233 setOperationAction(ISD::FREM , MVT::f64 , Expand);
234 setOperationAction(ISD::FREM , MVT::f80 , Expand);
235 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
237 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
238 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
239 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
240 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
241 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
242 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
243 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
244 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
245 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
246 if (Subtarget->is64Bit()) {
247 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
248 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
249 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
252 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
253 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
255 // These should be promoted to a larger select which is supported.
256 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
257 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
258 // X86 wants to expand cmov itself.
259 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
260 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
261 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
262 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
263 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
264 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
265 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
266 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
267 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
268 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
269 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
270 if (Subtarget->is64Bit()) {
271 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
272 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
274 // X86 ret instruction may pop stack.
275 setOperationAction(ISD::RET , MVT::Other, Custom);
276 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
279 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
280 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
281 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
282 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
283 if (Subtarget->is64Bit())
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
286 if (Subtarget->is64Bit()) {
287 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
288 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
289 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
290 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
292 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
293 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
294 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
295 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
296 if (Subtarget->is64Bit()) {
297 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
298 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
299 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
302 if (Subtarget->hasSSE1())
303 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
305 if (!Subtarget->hasSSE2())
306 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
308 // Expand certain atomics
309 setOperationAction(ISD::ATOMIC_CMP_SWAP_8 , MVT::i8, Custom);
310 setOperationAction(ISD::ATOMIC_CMP_SWAP_16, MVT::i16, Custom);
311 setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
312 setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
314 setOperationAction(ISD::ATOMIC_LOAD_SUB_8 , MVT::i8, Custom);
315 setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Custom);
316 setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Custom);
317 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
319 if (!Subtarget->is64Bit()) {
320 setOperationAction(ISD::ATOMIC_LOAD_ADD_64, MVT::i64, Custom);
321 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_AND_64, MVT::i64, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_OR_64, MVT::i64, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_XOR_64, MVT::i64, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_NAND_64, MVT::i64, Custom);
326 setOperationAction(ISD::ATOMIC_SWAP_64, MVT::i64, Custom);
329 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
330 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
331 // FIXME - use subtarget debug flags
332 if (!Subtarget->isTargetDarwin() &&
333 !Subtarget->isTargetELF() &&
334 !Subtarget->isTargetCygMing()) {
335 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
336 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
339 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
340 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
341 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
342 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
343 if (Subtarget->is64Bit()) {
344 setExceptionPointerRegister(X86::RAX);
345 setExceptionSelectorRegister(X86::RDX);
347 setExceptionPointerRegister(X86::EAX);
348 setExceptionSelectorRegister(X86::EDX);
350 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
353 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
355 setOperationAction(ISD::TRAP, MVT::Other, Legal);
357 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
358 setOperationAction(ISD::VASTART , MVT::Other, Custom);
359 setOperationAction(ISD::VAEND , MVT::Other, Expand);
360 if (Subtarget->is64Bit()) {
361 setOperationAction(ISD::VAARG , MVT::Other, Custom);
362 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
364 setOperationAction(ISD::VAARG , MVT::Other, Expand);
365 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
368 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
369 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
372 if (Subtarget->isTargetCygMing())
373 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
375 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
377 if (X86ScalarSSEf64) {
378 // f32 and f64 use SSE.
379 // Set up the FP register classes.
380 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
381 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
383 // Use ANDPD to simulate FABS.
384 setOperationAction(ISD::FABS , MVT::f64, Custom);
385 setOperationAction(ISD::FABS , MVT::f32, Custom);
387 // Use XORP to simulate FNEG.
388 setOperationAction(ISD::FNEG , MVT::f64, Custom);
389 setOperationAction(ISD::FNEG , MVT::f32, Custom);
391 // Use ANDPD and ORPD to simulate FCOPYSIGN.
392 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
393 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
395 // We don't support sin/cos/fmod
396 setOperationAction(ISD::FSIN , MVT::f64, Expand);
397 setOperationAction(ISD::FCOS , MVT::f64, Expand);
398 setOperationAction(ISD::FSIN , MVT::f32, Expand);
399 setOperationAction(ISD::FCOS , MVT::f32, Expand);
401 // Expand FP immediates into loads from the stack, except for the special
403 addLegalFPImmediate(APFloat(+0.0)); // xorpd
404 addLegalFPImmediate(APFloat(+0.0f)); // xorps
406 // Floating truncations from f80 and extensions to f80 go through memory.
407 // If optimizing, we lie about this though and handle it in
408 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
410 setConvertAction(MVT::f32, MVT::f80, Expand);
411 setConvertAction(MVT::f64, MVT::f80, Expand);
412 setConvertAction(MVT::f80, MVT::f32, Expand);
413 setConvertAction(MVT::f80, MVT::f64, Expand);
415 } else if (X86ScalarSSEf32) {
416 // Use SSE for f32, x87 for f64.
417 // Set up the FP register classes.
418 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
419 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
421 // Use ANDPS to simulate FABS.
422 setOperationAction(ISD::FABS , MVT::f32, Custom);
424 // Use XORP to simulate FNEG.
425 setOperationAction(ISD::FNEG , MVT::f32, Custom);
427 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
429 // Use ANDPS and ORPS to simulate FCOPYSIGN.
430 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
431 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
433 // We don't support sin/cos/fmod
434 setOperationAction(ISD::FSIN , MVT::f32, Expand);
435 setOperationAction(ISD::FCOS , MVT::f32, Expand);
437 // Special cases we handle for FP constants.
438 addLegalFPImmediate(APFloat(+0.0f)); // xorps
439 addLegalFPImmediate(APFloat(+0.0)); // FLD0
440 addLegalFPImmediate(APFloat(+1.0)); // FLD1
441 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
442 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
444 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
445 // this though and handle it in InstructionSelectPreprocess so that
446 // dagcombine2 can hack on these.
448 setConvertAction(MVT::f32, MVT::f64, Expand);
449 setConvertAction(MVT::f32, MVT::f80, Expand);
450 setConvertAction(MVT::f80, MVT::f32, Expand);
451 setConvertAction(MVT::f64, MVT::f32, Expand);
452 // And x87->x87 truncations also.
453 setConvertAction(MVT::f80, MVT::f64, Expand);
457 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
458 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
461 // f32 and f64 in x87.
462 // Set up the FP register classes.
463 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
464 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
466 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
467 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
471 // Floating truncations go through memory. If optimizing, we lie about
472 // this though and handle it in InstructionSelectPreprocess so that
473 // dagcombine2 can hack on these.
475 setConvertAction(MVT::f80, MVT::f32, Expand);
476 setConvertAction(MVT::f64, MVT::f32, Expand);
477 setConvertAction(MVT::f80, MVT::f64, Expand);
481 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
482 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
484 addLegalFPImmediate(APFloat(+0.0)); // FLD0
485 addLegalFPImmediate(APFloat(+1.0)); // FLD1
486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
488 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
489 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
490 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
491 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
494 // Long double always uses X87.
495 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
496 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
497 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
500 APFloat TmpFlt(+0.0);
501 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
503 addLegalFPImmediate(TmpFlt); // FLD0
505 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
506 APFloat TmpFlt2(+1.0);
507 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
509 addLegalFPImmediate(TmpFlt2); // FLD1
510 TmpFlt2.changeSign();
511 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
515 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
516 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
519 // Always use a library call for pow.
520 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
521 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
522 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
524 setOperationAction(ISD::FLOG, MVT::f80, Expand);
525 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
526 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
527 setOperationAction(ISD::FEXP, MVT::f80, Expand);
528 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
530 // First set operation action for all vector types to either promote
531 // (for widening) or expand (for scalarization). Then we will selectively
532 // turn on ones that can be effectively codegen'd.
533 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
534 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
535 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
550 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
580 if (!DisableMMX && Subtarget->hasMMX()) {
581 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
582 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
585 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
587 // FIXME: add MMX packed arithmetics
589 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
590 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
591 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
592 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
594 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
595 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
596 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
597 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
599 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
600 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
602 setOperationAction(ISD::AND, MVT::v8i8, Promote);
603 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
604 setOperationAction(ISD::AND, MVT::v4i16, Promote);
605 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
606 setOperationAction(ISD::AND, MVT::v2i32, Promote);
607 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
608 setOperationAction(ISD::AND, MVT::v1i64, Legal);
610 setOperationAction(ISD::OR, MVT::v8i8, Promote);
611 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
612 setOperationAction(ISD::OR, MVT::v4i16, Promote);
613 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
614 setOperationAction(ISD::OR, MVT::v2i32, Promote);
615 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
616 setOperationAction(ISD::OR, MVT::v1i64, Legal);
618 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
619 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
620 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
621 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
622 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
623 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
624 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
626 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
627 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
628 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
629 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
630 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
631 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
632 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
633 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
634 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
636 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
639 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
640 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
655 if (Subtarget->hasSSE1()) {
656 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
658 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
659 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
660 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
661 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
662 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
663 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
664 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
665 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
667 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
668 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
669 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
672 if (Subtarget->hasSSE2()) {
673 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
674 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
675 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
676 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
677 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
679 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
680 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
681 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
682 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
683 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
684 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
685 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
686 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
687 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
688 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
689 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
690 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
691 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
692 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
693 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
695 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
696 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
697 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
698 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
700 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
701 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
702 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
703 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
704 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
706 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
707 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
708 MVT VT = (MVT::SimpleValueType)i;
709 // Do not attempt to custom lower non-power-of-2 vectors
710 if (!isPowerOf2_32(VT.getVectorNumElements()))
712 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
713 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
714 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
716 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
717 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
718 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
719 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
720 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
721 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
722 if (Subtarget->is64Bit()) {
723 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
727 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
728 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
729 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
730 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
731 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
732 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
733 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
734 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
735 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
736 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
737 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
738 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
741 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
743 // Custom lower v2i64 and v2f64 selects.
744 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
745 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
746 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
747 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
751 if (Subtarget->hasSSE41()) {
752 // FIXME: Do we need to handle scalar-to-vector here?
753 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
754 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
756 // i8 and i16 vectors are custom , because the source register and source
757 // source memory operand types are not the same width. f32 vectors are
758 // custom since the immediate controlling the insert encodes additional
760 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
761 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
762 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
763 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
765 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
766 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
767 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
768 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
770 if (Subtarget->is64Bit()) {
771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
776 if (Subtarget->hasSSE42()) {
777 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
780 // We want to custom lower some of our intrinsics.
781 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
783 // We have target-specific dag combine patterns for the following nodes:
784 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
785 setTargetDAGCombine(ISD::BUILD_VECTOR);
786 setTargetDAGCombine(ISD::SELECT);
787 setTargetDAGCombine(ISD::STORE);
789 computeRegisterProperties();
791 // FIXME: These should be based on subtarget info. Plus, the values should
792 // be smaller when we are in optimizing for size mode.
793 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
794 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
795 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
796 allowUnalignedMemoryAccesses = true; // x86 supports it!
797 setPrefLoopAlignment(16);
801 MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
806 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
807 /// the desired ByVal argument alignment.
808 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
811 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
812 if (VTy->getBitWidth() == 128)
814 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
815 unsigned EltAlign = 0;
816 getMaxByValAlign(ATy->getElementType(), EltAlign);
817 if (EltAlign > MaxAlign)
819 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
820 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
821 unsigned EltAlign = 0;
822 getMaxByValAlign(STy->getElementType(i), EltAlign);
823 if (EltAlign > MaxAlign)
832 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
833 /// function arguments in the caller parameter area. For X86, aggregates
834 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
835 /// are at 4-byte boundaries.
836 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
837 if (Subtarget->is64Bit()) {
838 // Max of 8 and alignment of type.
839 unsigned TyAlign = TD->getABITypeAlignment(Ty);
846 if (Subtarget->hasSSE1())
847 getMaxByValAlign(Ty, Align);
851 /// getOptimalMemOpType - Returns the target specific optimal type for load
852 /// and store operations as a result of memset, memcpy, and memmove
853 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
856 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
857 bool isSrcConst, bool isSrcStr) const {
858 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
859 // linux. This is because the stack realignment code can't handle certain
860 // cases like PR2962. This should be removed when PR2962 is fixed.
861 if (Subtarget->getStackAlignment() >= 16) {
862 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
864 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
867 if (Subtarget->is64Bit() && Size >= 8)
873 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
875 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
876 SelectionDAG &DAG) const {
877 if (usesGlobalOffsetTable())
878 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
879 if (!Subtarget->isPICStyleRIPRel())
880 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
884 //===----------------------------------------------------------------------===//
885 // Return Value Calling Convention Implementation
886 //===----------------------------------------------------------------------===//
888 #include "X86GenCallingConv.inc"
890 /// LowerRET - Lower an ISD::RET node.
891 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
892 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
894 SmallVector<CCValAssign, 16> RVLocs;
895 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
896 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
897 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
898 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
900 // If this is the first return lowered for this function, add the regs to the
901 // liveout set for the function.
902 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
903 for (unsigned i = 0; i != RVLocs.size(); ++i)
904 if (RVLocs[i].isRegLoc())
905 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
907 SDValue Chain = Op.getOperand(0);
909 // Handle tail call return.
910 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
911 if (Chain.getOpcode() == X86ISD::TAILCALL) {
912 SDValue TailCall = Chain;
913 SDValue TargetAddress = TailCall.getOperand(1);
914 SDValue StackAdjustment = TailCall.getOperand(2);
915 assert(((TargetAddress.getOpcode() == ISD::Register &&
916 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
917 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
918 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
919 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
920 "Expecting an global address, external symbol, or register");
921 assert(StackAdjustment.getOpcode() == ISD::Constant &&
922 "Expecting a const value");
924 SmallVector<SDValue,8> Operands;
925 Operands.push_back(Chain.getOperand(0));
926 Operands.push_back(TargetAddress);
927 Operands.push_back(StackAdjustment);
928 // Copy registers used by the call. Last operand is a flag so it is not
930 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
931 Operands.push_back(Chain.getOperand(i));
933 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
940 SmallVector<SDValue, 6> RetOps;
941 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
942 // Operand #1 = Bytes To Pop
943 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
945 // Copy the result values into the output registers.
946 for (unsigned i = 0; i != RVLocs.size(); ++i) {
947 CCValAssign &VA = RVLocs[i];
948 assert(VA.isRegLoc() && "Can only return in registers!");
949 SDValue ValToCopy = Op.getOperand(i*2+1);
951 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
952 // the RET instruction and handled by the FP Stackifier.
953 if (RVLocs[i].getLocReg() == X86::ST0 ||
954 RVLocs[i].getLocReg() == X86::ST1) {
955 // If this is a copy from an xmm register to ST(0), use an FPExtend to
956 // change the value to the FP stack register class.
957 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
958 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
959 RetOps.push_back(ValToCopy);
960 // Don't emit a copytoreg.
964 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
965 Flag = Chain.getValue(1);
968 // The x86-64 ABI for returning structs by value requires that we copy
969 // the sret argument into %rax for the return. We saved the argument into
970 // a virtual register in the entry block, so now we copy the value out
972 if (Subtarget->is64Bit() &&
973 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
974 MachineFunction &MF = DAG.getMachineFunction();
975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
976 unsigned Reg = FuncInfo->getSRetReturnReg();
978 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
979 FuncInfo->setSRetReturnReg(Reg);
981 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
983 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
984 Flag = Chain.getValue(1);
987 RetOps[0] = Chain; // Update chain.
989 // Add the flag if we have it.
991 RetOps.push_back(Flag);
993 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
997 /// LowerCallResult - Lower the result values of an ISD::CALL into the
998 /// appropriate copies out of appropriate physical registers. This assumes that
999 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1000 /// being lowered. The returns a SDNode with the same number of values as the
1002 SDNode *X86TargetLowering::
1003 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1004 unsigned CallingConv, SelectionDAG &DAG) {
1006 // Assign locations to each value returned by this call.
1007 SmallVector<CCValAssign, 16> RVLocs;
1008 bool isVarArg = TheCall->isVarArg();
1009 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1010 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1012 SmallVector<SDValue, 8> ResultVals;
1014 // Copy all of the result registers out of their specified physreg.
1015 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1016 MVT CopyVT = RVLocs[i].getValVT();
1018 // If this is a call to a function that returns an fp value on the floating
1019 // point stack, but where we prefer to use the value in xmm registers, copy
1020 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1021 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1022 RVLocs[i].getLocReg() == X86::ST1) &&
1023 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1027 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1028 CopyVT, InFlag).getValue(1);
1029 SDValue Val = Chain.getValue(0);
1030 InFlag = Chain.getValue(2);
1032 if (CopyVT != RVLocs[i].getValVT()) {
1033 // Round the F80 the right size, which also moves to the appropriate xmm
1035 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1036 // This truncation won't change the value.
1037 DAG.getIntPtrConstant(1));
1040 ResultVals.push_back(Val);
1043 // Merge everything together with a MERGE_VALUES node.
1044 ResultVals.push_back(Chain);
1045 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
1046 ResultVals.size()).getNode();
1050 //===----------------------------------------------------------------------===//
1051 // C & StdCall & Fast Calling Convention implementation
1052 //===----------------------------------------------------------------------===//
1053 // StdCall calling convention seems to be standard for many Windows' API
1054 // routines and around. It differs from C calling convention just a little:
1055 // callee should clean up the stack, not caller. Symbols should be also
1056 // decorated in some fancy way :) It doesn't support any vector arguments.
1057 // For info on fast calling convention see Fast Calling Convention (tail call)
1058 // implementation LowerX86_32FastCCCallTo.
1060 /// AddLiveIn - This helper function adds the specified physical register to the
1061 /// MachineFunction as a live in value. It also creates a corresponding virtual
1062 /// register for it.
1063 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1064 const TargetRegisterClass *RC) {
1065 assert(RC->contains(PReg) && "Not the correct regclass!");
1066 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1067 MF.getRegInfo().addLiveIn(PReg, VReg);
1071 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1073 static bool CallIsStructReturn(CallSDNode *TheCall) {
1074 unsigned NumOps = TheCall->getNumArgs();
1078 return TheCall->getArgFlags(0).isSRet();
1081 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1082 /// return semantics.
1083 static bool ArgsAreStructReturn(SDValue Op) {
1084 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1088 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1091 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1092 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1094 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1098 switch (CallingConv) {
1101 case CallingConv::X86_StdCall:
1102 return !Subtarget->is64Bit();
1103 case CallingConv::X86_FastCall:
1104 return !Subtarget->is64Bit();
1105 case CallingConv::Fast:
1106 return PerformTailCallOpt;
1110 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1111 /// given CallingConvention value.
1112 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1113 if (Subtarget->is64Bit()) {
1114 if (Subtarget->isTargetWin64())
1115 return CC_X86_Win64_C;
1116 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1117 return CC_X86_64_TailCall;
1122 if (CC == CallingConv::X86_FastCall)
1123 return CC_X86_32_FastCall;
1124 else if (CC == CallingConv::Fast)
1125 return CC_X86_32_FastCC;
1130 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1131 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1133 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1134 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1135 if (CC == CallingConv::X86_FastCall)
1137 else if (CC == CallingConv::X86_StdCall)
1143 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1144 /// in a register before calling.
1145 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1146 return !IsTailCall && !Is64Bit &&
1147 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1148 Subtarget->isPICStyleGOT();
1151 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1152 /// address to be loaded in a register.
1154 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1155 return !Is64Bit && IsTailCall &&
1156 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1157 Subtarget->isPICStyleGOT();
1160 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1161 /// by "Src" to address "Dst" with size and alignment information specified by
1162 /// the specific parameter attribute. The copy will be passed as a byval
1163 /// function parameter.
1165 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1166 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1167 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1168 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1169 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1172 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1173 const CCValAssign &VA,
1174 MachineFrameInfo *MFI,
1176 SDValue Root, unsigned i) {
1177 // Create the nodes corresponding to a load from this parameter slot.
1178 ISD::ArgFlagsTy Flags =
1179 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1180 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1181 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1183 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1184 // changed with more analysis.
1185 // In case of tail call optimization mark all arguments mutable. Since they
1186 // could be overwritten by lowering of arguments in case of a tail call.
1187 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1188 VA.getLocMemOffset(), isImmutable);
1189 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1190 if (Flags.isByVal())
1192 return DAG.getLoad(VA.getValVT(), Root, FIN,
1193 PseudoSourceValue::getFixedStack(FI), 0);
1197 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1198 MachineFunction &MF = DAG.getMachineFunction();
1199 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1201 const Function* Fn = MF.getFunction();
1202 if (Fn->hasExternalLinkage() &&
1203 Subtarget->isTargetCygMing() &&
1204 Fn->getName() == "main")
1205 FuncInfo->setForceFramePointer(true);
1207 // Decorate the function name.
1208 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1210 MachineFrameInfo *MFI = MF.getFrameInfo();
1211 SDValue Root = Op.getOperand(0);
1212 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1213 unsigned CC = MF.getFunction()->getCallingConv();
1214 bool Is64Bit = Subtarget->is64Bit();
1215 bool IsWin64 = Subtarget->isTargetWin64();
1217 assert(!(isVarArg && CC == CallingConv::Fast) &&
1218 "Var args not supported with calling convention fastcc");
1220 // Assign locations to all of the incoming arguments.
1221 SmallVector<CCValAssign, 16> ArgLocs;
1222 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1223 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1225 SmallVector<SDValue, 8> ArgValues;
1226 unsigned LastVal = ~0U;
1227 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1228 CCValAssign &VA = ArgLocs[i];
1229 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1231 assert(VA.getValNo() != LastVal &&
1232 "Don't support value assigned to multiple locs yet");
1233 LastVal = VA.getValNo();
1235 if (VA.isRegLoc()) {
1236 MVT RegVT = VA.getLocVT();
1237 TargetRegisterClass *RC;
1238 if (RegVT == MVT::i32)
1239 RC = X86::GR32RegisterClass;
1240 else if (Is64Bit && RegVT == MVT::i64)
1241 RC = X86::GR64RegisterClass;
1242 else if (RegVT == MVT::f32)
1243 RC = X86::FR32RegisterClass;
1244 else if (RegVT == MVT::f64)
1245 RC = X86::FR64RegisterClass;
1246 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1247 RC = X86::VR128RegisterClass;
1248 else if (RegVT.isVector()) {
1249 assert(RegVT.getSizeInBits() == 64);
1251 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1253 // Darwin calling convention passes MMX values in either GPRs or
1254 // XMMs in x86-64. Other targets pass them in memory.
1255 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1256 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1259 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1264 assert(0 && "Unknown argument type!");
1267 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1268 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1270 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1271 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1273 if (VA.getLocInfo() == CCValAssign::SExt)
1274 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1275 DAG.getValueType(VA.getValVT()));
1276 else if (VA.getLocInfo() == CCValAssign::ZExt)
1277 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1278 DAG.getValueType(VA.getValVT()));
1280 if (VA.getLocInfo() != CCValAssign::Full)
1281 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1283 // Handle MMX values passed in GPRs.
1284 if (Is64Bit && RegVT != VA.getLocVT()) {
1285 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1286 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1287 else if (RC == X86::VR128RegisterClass) {
1288 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1289 DAG.getConstant(0, MVT::i64));
1290 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1294 ArgValues.push_back(ArgValue);
1296 assert(VA.isMemLoc());
1297 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1301 // The x86-64 ABI for returning structs by value requires that we copy
1302 // the sret argument into %rax for the return. Save the argument into
1303 // a virtual register so that we can access it from the return points.
1304 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1305 MachineFunction &MF = DAG.getMachineFunction();
1306 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1307 unsigned Reg = FuncInfo->getSRetReturnReg();
1309 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1310 FuncInfo->setSRetReturnReg(Reg);
1312 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1313 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1316 unsigned StackSize = CCInfo.getNextStackOffset();
1317 // align stack specially for tail calls
1318 if (PerformTailCallOpt && CC == CallingConv::Fast)
1319 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1321 // If the function takes variable number of arguments, make a frame index for
1322 // the start of the first vararg value... for expansion of llvm.va_start.
1324 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1325 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1328 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1330 // FIXME: We should really autogenerate these arrays
1331 static const unsigned GPR64ArgRegsWin64[] = {
1332 X86::RCX, X86::RDX, X86::R8, X86::R9
1334 static const unsigned XMMArgRegsWin64[] = {
1335 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1337 static const unsigned GPR64ArgRegs64Bit[] = {
1338 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1340 static const unsigned XMMArgRegs64Bit[] = {
1341 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1342 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1344 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1347 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1348 GPR64ArgRegs = GPR64ArgRegsWin64;
1349 XMMArgRegs = XMMArgRegsWin64;
1351 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1352 GPR64ArgRegs = GPR64ArgRegs64Bit;
1353 XMMArgRegs = XMMArgRegs64Bit;
1355 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1357 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1360 // For X86-64, if there are vararg parameters that are passed via
1361 // registers, then we must store them to their spots on the stack so they
1362 // may be loaded by deferencing the result of va_next.
1363 VarArgsGPOffset = NumIntRegs * 8;
1364 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1365 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1366 TotalNumXMMRegs * 16, 16);
1368 // Store the integer parameter registers.
1369 SmallVector<SDValue, 8> MemOps;
1370 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1371 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1372 DAG.getIntPtrConstant(VarArgsGPOffset));
1373 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1374 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1375 X86::GR64RegisterClass);
1376 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1378 DAG.getStore(Val.getValue(1), Val, FIN,
1379 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1380 MemOps.push_back(Store);
1381 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1382 DAG.getIntPtrConstant(8));
1385 // Now store the XMM (fp + vector) parameter registers.
1386 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1387 DAG.getIntPtrConstant(VarArgsFPOffset));
1388 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1389 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1390 X86::VR128RegisterClass);
1391 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1393 DAG.getStore(Val.getValue(1), Val, FIN,
1394 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1395 MemOps.push_back(Store);
1396 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1397 DAG.getIntPtrConstant(16));
1399 if (!MemOps.empty())
1400 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1401 &MemOps[0], MemOps.size());
1405 ArgValues.push_back(Root);
1407 // Some CCs need callee pop.
1408 if (IsCalleePop(isVarArg, CC)) {
1409 BytesToPopOnReturn = StackSize; // Callee pops everything.
1410 BytesCallerReserves = 0;
1412 BytesToPopOnReturn = 0; // Callee pops nothing.
1413 // If this is an sret function, the return should pop the hidden pointer.
1414 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1415 BytesToPopOnReturn = 4;
1416 BytesCallerReserves = StackSize;
1420 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1421 if (CC == CallingConv::X86_FastCall)
1422 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1425 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1427 // Return the new list of results.
1428 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
1429 ArgValues.size()).getValue(Op.getResNo());
1433 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1434 const SDValue &StackPtr,
1435 const CCValAssign &VA,
1437 SDValue Arg, ISD::ArgFlagsTy Flags) {
1438 unsigned LocMemOffset = VA.getLocMemOffset();
1439 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1440 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1441 if (Flags.isByVal()) {
1442 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1444 return DAG.getStore(Chain, Arg, PtrOff,
1445 PseudoSourceValue::getStack(), LocMemOffset);
1448 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1449 /// optimization is performed and it is required.
1451 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1452 SDValue &OutRetAddr,
1457 if (!IsTailCall || FPDiff==0) return Chain;
1459 // Adjust the Return address stack slot.
1460 MVT VT = getPointerTy();
1461 OutRetAddr = getReturnAddressFrameIndex(DAG);
1462 // Load the "old" Return address.
1463 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1464 return SDValue(OutRetAddr.getNode(), 1);
1467 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1468 /// optimization is performed and it is required (FPDiff!=0).
1470 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1471 SDValue Chain, SDValue RetAddrFrIdx,
1472 bool Is64Bit, int FPDiff) {
1473 // Store the return address to the appropriate stack slot.
1474 if (!FPDiff) return Chain;
1475 // Calculate the new stack slot for the return address.
1476 int SlotSize = Is64Bit ? 8 : 4;
1477 int NewReturnAddrFI =
1478 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1479 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1480 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1481 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1482 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1486 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1487 MachineFunction &MF = DAG.getMachineFunction();
1488 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1489 SDValue Chain = TheCall->getChain();
1490 unsigned CC = TheCall->getCallingConv();
1491 bool isVarArg = TheCall->isVarArg();
1492 bool IsTailCall = TheCall->isTailCall() &&
1493 CC == CallingConv::Fast && PerformTailCallOpt;
1494 SDValue Callee = TheCall->getCallee();
1495 bool Is64Bit = Subtarget->is64Bit();
1496 bool IsStructRet = CallIsStructReturn(TheCall);
1498 assert(!(isVarArg && CC == CallingConv::Fast) &&
1499 "Var args not supported with calling convention fastcc");
1501 // Analyze operands of the call, assigning locations to each operand.
1502 SmallVector<CCValAssign, 16> ArgLocs;
1503 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1504 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1506 // Get a count of how many bytes are to be pushed on the stack.
1507 unsigned NumBytes = CCInfo.getNextStackOffset();
1508 if (PerformTailCallOpt && CC == CallingConv::Fast)
1509 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1513 // Lower arguments at fp - stackoffset + fpdiff.
1514 unsigned NumBytesCallerPushed =
1515 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1516 FPDiff = NumBytesCallerPushed - NumBytes;
1518 // Set the delta of movement of the returnaddr stackslot.
1519 // But only set if delta is greater than previous delta.
1520 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1521 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1524 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1526 SDValue RetAddrFrIdx;
1527 // Load return adress for tail calls.
1528 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1531 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1532 SmallVector<SDValue, 8> MemOpChains;
1535 // Walk the register/memloc assignments, inserting copies/loads. In the case
1536 // of tail call optimization arguments are handle later.
1537 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1538 CCValAssign &VA = ArgLocs[i];
1539 SDValue Arg = TheCall->getArg(i);
1540 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1541 bool isByVal = Flags.isByVal();
1543 // Promote the value if needed.
1544 switch (VA.getLocInfo()) {
1545 default: assert(0 && "Unknown loc info!");
1546 case CCValAssign::Full: break;
1547 case CCValAssign::SExt:
1548 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1550 case CCValAssign::ZExt:
1551 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1553 case CCValAssign::AExt:
1554 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1558 if (VA.isRegLoc()) {
1560 MVT RegVT = VA.getLocVT();
1561 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1562 switch (VA.getLocReg()) {
1565 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1567 // Special case: passing MMX values in GPR registers.
1568 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1571 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1572 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1573 // Special case: passing MMX values in XMM registers.
1574 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1575 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1576 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1577 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1578 getMOVLMask(2, DAG));
1583 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1585 if (!IsTailCall || (IsTailCall && isByVal)) {
1586 assert(VA.isMemLoc());
1587 if (StackPtr.getNode() == 0)
1588 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1590 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1591 Chain, Arg, Flags));
1596 if (!MemOpChains.empty())
1597 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1598 &MemOpChains[0], MemOpChains.size());
1600 // Build a sequence of copy-to-reg nodes chained together with token chain
1601 // and flag operands which copy the outgoing args into registers.
1603 // Tail call byval lowering might overwrite argument registers so in case of
1604 // tail call optimization the copies to registers are lowered later.
1606 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1607 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1609 InFlag = Chain.getValue(1);
1612 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1614 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1615 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1616 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1618 InFlag = Chain.getValue(1);
1620 // If we are tail calling and generating PIC/GOT style code load the address
1621 // of the callee into ecx. The value in ecx is used as target of the tail
1622 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1623 // calls on PIC/GOT architectures. Normally we would just put the address of
1624 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1625 // restored (since ebx is callee saved) before jumping to the target@PLT.
1626 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1627 // Note: The actual moving to ecx is done further down.
1628 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1629 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1630 !G->getGlobal()->hasProtectedVisibility())
1631 Callee = LowerGlobalAddress(Callee, DAG);
1632 else if (isa<ExternalSymbolSDNode>(Callee))
1633 Callee = LowerExternalSymbol(Callee,DAG);
1636 if (Is64Bit && isVarArg) {
1637 // From AMD64 ABI document:
1638 // For calls that may call functions that use varargs or stdargs
1639 // (prototype-less calls or calls to functions containing ellipsis (...) in
1640 // the declaration) %al is used as hidden argument to specify the number
1641 // of SSE registers used. The contents of %al do not need to match exactly
1642 // the number of registers, but must be an ubound on the number of SSE
1643 // registers used and is in the range 0 - 8 inclusive.
1645 // FIXME: Verify this on Win64
1646 // Count the number of XMM registers allocated.
1647 static const unsigned XMMArgRegs[] = {
1648 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1649 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1651 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1653 Chain = DAG.getCopyToReg(Chain, X86::AL,
1654 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1655 InFlag = Chain.getValue(1);
1659 // For tail calls lower the arguments to the 'real' stack slot.
1661 SmallVector<SDValue, 8> MemOpChains2;
1664 // Do not flag preceeding copytoreg stuff together with the following stuff.
1666 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1667 CCValAssign &VA = ArgLocs[i];
1668 if (!VA.isRegLoc()) {
1669 assert(VA.isMemLoc());
1670 SDValue Arg = TheCall->getArg(i);
1671 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1672 // Create frame index.
1673 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1674 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1675 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1676 FIN = DAG.getFrameIndex(FI, getPointerTy());
1678 if (Flags.isByVal()) {
1679 // Copy relative to framepointer.
1680 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1681 if (StackPtr.getNode() == 0)
1682 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1683 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1685 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1688 // Store relative to framepointer.
1689 MemOpChains2.push_back(
1690 DAG.getStore(Chain, Arg, FIN,
1691 PseudoSourceValue::getFixedStack(FI), 0));
1696 if (!MemOpChains2.empty())
1697 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1698 &MemOpChains2[0], MemOpChains2.size());
1700 // Copy arguments to their registers.
1701 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1702 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1704 InFlag = Chain.getValue(1);
1708 // Store the return address to the appropriate stack slot.
1709 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1713 // If the callee is a GlobalAddress node (quite common, every direct call is)
1714 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1715 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1716 // We should use extra load for direct calls to dllimported functions in
1718 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1719 getTargetMachine(), true))
1720 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1722 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1723 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1724 } else if (IsTailCall) {
1725 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1727 Chain = DAG.getCopyToReg(Chain,
1728 DAG.getRegister(Opc, getPointerTy()),
1730 Callee = DAG.getRegister(Opc, getPointerTy());
1731 // Add register as live out.
1732 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1735 // Returns a chain & a flag for retval copy to use.
1736 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1737 SmallVector<SDValue, 8> Ops;
1740 Ops.push_back(Chain);
1741 Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
1742 Ops.push_back(DAG.getIntPtrConstant(0, true));
1743 if (InFlag.getNode())
1744 Ops.push_back(InFlag);
1745 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1746 InFlag = Chain.getValue(1);
1748 // Returns a chain & a flag for retval copy to use.
1749 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1753 Ops.push_back(Chain);
1754 Ops.push_back(Callee);
1757 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1759 // Add argument registers to the end of the list so that they are known live
1761 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1762 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1763 RegsToPass[i].second.getValueType()));
1765 // Add an implicit use GOT pointer in EBX.
1766 if (!IsTailCall && !Is64Bit &&
1767 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1768 Subtarget->isPICStyleGOT())
1769 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1771 // Add an implicit use of AL for x86 vararg functions.
1772 if (Is64Bit && isVarArg)
1773 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1775 if (InFlag.getNode())
1776 Ops.push_back(InFlag);
1779 assert(InFlag.getNode() &&
1780 "Flag must be set. Depend on flag being set in LowerRET");
1781 Chain = DAG.getNode(X86ISD::TAILCALL,
1782 TheCall->getVTList(), &Ops[0], Ops.size());
1784 return SDValue(Chain.getNode(), Op.getResNo());
1787 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1788 InFlag = Chain.getValue(1);
1790 // Create the CALLSEQ_END node.
1791 unsigned NumBytesForCalleeToPush;
1792 if (IsCalleePop(isVarArg, CC))
1793 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1794 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1795 // If this is is a call to a struct-return function, the callee
1796 // pops the hidden struct pointer, so we have to push it back.
1797 // This is common for Darwin/X86, Linux & Mingw32 targets.
1798 NumBytesForCalleeToPush = 4;
1800 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1802 // Returns a flag for retval copy to use.
1803 Chain = DAG.getCALLSEQ_END(Chain,
1804 DAG.getIntPtrConstant(NumBytes, true),
1805 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1808 InFlag = Chain.getValue(1);
1810 // Handle result values, copying them out of physregs into vregs that we
1812 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1817 //===----------------------------------------------------------------------===//
1818 // Fast Calling Convention (tail call) implementation
1819 //===----------------------------------------------------------------------===//
1821 // Like std call, callee cleans arguments, convention except that ECX is
1822 // reserved for storing the tail called function address. Only 2 registers are
1823 // free for argument passing (inreg). Tail call optimization is performed
1825 // * tailcallopt is enabled
1826 // * caller/callee are fastcc
1827 // On X86_64 architecture with GOT-style position independent code only local
1828 // (within module) calls are supported at the moment.
1829 // To keep the stack aligned according to platform abi the function
1830 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1831 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1832 // If a tail called function callee has more arguments than the caller the
1833 // caller needs to make sure that there is room to move the RETADDR to. This is
1834 // achieved by reserving an area the size of the argument delta right after the
1835 // original REtADDR, but before the saved framepointer or the spilled registers
1836 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1848 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1849 /// for a 16 byte align requirement.
1850 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1851 SelectionDAG& DAG) {
1852 MachineFunction &MF = DAG.getMachineFunction();
1853 const TargetMachine &TM = MF.getTarget();
1854 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1855 unsigned StackAlignment = TFI.getStackAlignment();
1856 uint64_t AlignMask = StackAlignment - 1;
1857 int64_t Offset = StackSize;
1858 uint64_t SlotSize = TD->getPointerSize();
1859 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1860 // Number smaller than 12 so just add the difference.
1861 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1863 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1864 Offset = ((~AlignMask) & Offset) + StackAlignment +
1865 (StackAlignment-SlotSize);
1870 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1871 /// following the call is a return. A function is eligible if caller/callee
1872 /// calling conventions match, currently only fastcc supports tail calls, and
1873 /// the function CALL is immediatly followed by a RET.
1874 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1876 SelectionDAG& DAG) const {
1877 if (!PerformTailCallOpt)
1880 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1881 MachineFunction &MF = DAG.getMachineFunction();
1882 unsigned CallerCC = MF.getFunction()->getCallingConv();
1883 unsigned CalleeCC= TheCall->getCallingConv();
1884 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1885 SDValue Callee = TheCall->getCallee();
1886 // On x86/32Bit PIC/GOT tail calls are supported.
1887 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1888 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1891 // Can only do local tail calls (in same module, hidden or protected) on
1892 // x86_64 PIC/GOT at the moment.
1893 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1894 return G->getGlobal()->hasHiddenVisibility()
1895 || G->getGlobal()->hasProtectedVisibility();
1903 X86TargetLowering::createFastISel(MachineFunction &mf,
1904 MachineModuleInfo *mmo,
1905 DenseMap<const Value *, unsigned> &vm,
1906 DenseMap<const BasicBlock *,
1907 MachineBasicBlock *> &bm,
1908 DenseMap<const AllocaInst *, int> &am
1910 , SmallSet<Instruction*, 8> &cil
1913 return X86::createFastISel(mf, mmo, vm, bm, am
1921 //===----------------------------------------------------------------------===//
1922 // Other Lowering Hooks
1923 //===----------------------------------------------------------------------===//
1926 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1927 MachineFunction &MF = DAG.getMachineFunction();
1928 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1929 int ReturnAddrIndex = FuncInfo->getRAIndex();
1930 uint64_t SlotSize = TD->getPointerSize();
1932 if (ReturnAddrIndex == 0) {
1933 // Set up a frame object for the return address.
1934 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1935 FuncInfo->setRAIndex(ReturnAddrIndex);
1938 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1942 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1943 /// specific condition code. It returns a false if it cannot do a direct
1944 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1946 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1947 unsigned &X86CC, SDValue &LHS, SDValue &RHS,
1948 SelectionDAG &DAG) {
1949 X86CC = X86::COND_INVALID;
1951 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1952 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1953 // X > -1 -> X == 0, jump !sign.
1954 RHS = DAG.getConstant(0, RHS.getValueType());
1955 X86CC = X86::COND_NS;
1957 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1958 // X < 0 -> X == 0, jump on sign.
1959 X86CC = X86::COND_S;
1961 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1963 RHS = DAG.getConstant(0, RHS.getValueType());
1964 X86CC = X86::COND_LE;
1969 switch (SetCCOpcode) {
1971 case ISD::SETEQ: X86CC = X86::COND_E; break;
1972 case ISD::SETGT: X86CC = X86::COND_G; break;
1973 case ISD::SETGE: X86CC = X86::COND_GE; break;
1974 case ISD::SETLT: X86CC = X86::COND_L; break;
1975 case ISD::SETLE: X86CC = X86::COND_LE; break;
1976 case ISD::SETNE: X86CC = X86::COND_NE; break;
1977 case ISD::SETULT: X86CC = X86::COND_B; break;
1978 case ISD::SETUGT: X86CC = X86::COND_A; break;
1979 case ISD::SETULE: X86CC = X86::COND_BE; break;
1980 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1983 // First determine if it is required or is profitable to flip the operands.
1985 // If LHS is a foldable load, but RHS is not, flip the condition.
1986 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
1987 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
1988 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1989 std::swap(LHS, RHS);
1992 switch (SetCCOpcode) {
1998 std::swap(LHS, RHS);
2002 // On a floating point condition, the flags are set as follows:
2004 // 0 | 0 | 0 | X > Y
2005 // 0 | 0 | 1 | X < Y
2006 // 1 | 0 | 0 | X == Y
2007 // 1 | 1 | 1 | unordered
2008 switch (SetCCOpcode) {
2012 X86CC = X86::COND_E;
2014 case ISD::SETOLT: // flipped
2017 X86CC = X86::COND_A;
2019 case ISD::SETOLE: // flipped
2022 X86CC = X86::COND_AE;
2024 case ISD::SETUGT: // flipped
2027 X86CC = X86::COND_B;
2029 case ISD::SETUGE: // flipped
2032 X86CC = X86::COND_BE;
2036 X86CC = X86::COND_NE;
2039 X86CC = X86::COND_P;
2042 X86CC = X86::COND_NP;
2047 return X86CC != X86::COND_INVALID;
2050 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2051 /// code. Current x86 isa includes the following FP cmov instructions:
2052 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2053 static bool hasFPCMov(unsigned X86CC) {
2069 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2070 /// true if Op is undef or if its value falls within the specified range (L, H].
2071 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2072 if (Op.getOpcode() == ISD::UNDEF)
2075 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2076 return (Val >= Low && Val < Hi);
2079 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2080 /// true if Op is undef or if its value equal to the specified value.
2081 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2082 if (Op.getOpcode() == ISD::UNDEF)
2084 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2087 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2088 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2089 bool X86::isPSHUFDMask(SDNode *N) {
2090 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2092 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2095 // Check if the value doesn't reference the second vector.
2096 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2097 SDValue Arg = N->getOperand(i);
2098 if (Arg.getOpcode() == ISD::UNDEF) continue;
2099 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2100 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2107 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2108 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2109 bool X86::isPSHUFHWMask(SDNode *N) {
2110 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2112 if (N->getNumOperands() != 8)
2115 // Lower quadword copied in order.
2116 for (unsigned i = 0; i != 4; ++i) {
2117 SDValue Arg = N->getOperand(i);
2118 if (Arg.getOpcode() == ISD::UNDEF) continue;
2119 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2120 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2124 // Upper quadword shuffled.
2125 for (unsigned i = 4; i != 8; ++i) {
2126 SDValue Arg = N->getOperand(i);
2127 if (Arg.getOpcode() == ISD::UNDEF) continue;
2128 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2129 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2130 if (Val < 4 || Val > 7)
2137 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2138 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2139 bool X86::isPSHUFLWMask(SDNode *N) {
2140 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2142 if (N->getNumOperands() != 8)
2145 // Upper quadword copied in order.
2146 for (unsigned i = 4; i != 8; ++i)
2147 if (!isUndefOrEqual(N->getOperand(i), i))
2150 // Lower quadword shuffled.
2151 for (unsigned i = 0; i != 4; ++i)
2152 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2158 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2159 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2160 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2161 if (NumElems != 2 && NumElems != 4) return false;
2163 unsigned Half = NumElems / 2;
2164 for (unsigned i = 0; i < Half; ++i)
2165 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2167 for (unsigned i = Half; i < NumElems; ++i)
2168 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2174 bool X86::isSHUFPMask(SDNode *N) {
2175 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2176 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2179 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2180 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2181 /// half elements to come from vector 1 (which would equal the dest.) and
2182 /// the upper half to come from vector 2.
2183 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2184 if (NumOps != 2 && NumOps != 4) return false;
2186 unsigned Half = NumOps / 2;
2187 for (unsigned i = 0; i < Half; ++i)
2188 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2190 for (unsigned i = Half; i < NumOps; ++i)
2191 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2196 static bool isCommutedSHUFP(SDNode *N) {
2197 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2198 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2201 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2202 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2203 bool X86::isMOVHLPSMask(SDNode *N) {
2204 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2206 if (N->getNumOperands() != 4)
2209 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2210 return isUndefOrEqual(N->getOperand(0), 6) &&
2211 isUndefOrEqual(N->getOperand(1), 7) &&
2212 isUndefOrEqual(N->getOperand(2), 2) &&
2213 isUndefOrEqual(N->getOperand(3), 3);
2216 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2217 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2219 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2220 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2222 if (N->getNumOperands() != 4)
2225 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2226 return isUndefOrEqual(N->getOperand(0), 2) &&
2227 isUndefOrEqual(N->getOperand(1), 3) &&
2228 isUndefOrEqual(N->getOperand(2), 2) &&
2229 isUndefOrEqual(N->getOperand(3), 3);
2232 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2233 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2234 bool X86::isMOVLPMask(SDNode *N) {
2235 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2237 unsigned NumElems = N->getNumOperands();
2238 if (NumElems != 2 && NumElems != 4)
2241 for (unsigned i = 0; i < NumElems/2; ++i)
2242 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2245 for (unsigned i = NumElems/2; i < NumElems; ++i)
2246 if (!isUndefOrEqual(N->getOperand(i), i))
2252 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2253 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2255 bool X86::isMOVHPMask(SDNode *N) {
2256 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2258 unsigned NumElems = N->getNumOperands();
2259 if (NumElems != 2 && NumElems != 4)
2262 for (unsigned i = 0; i < NumElems/2; ++i)
2263 if (!isUndefOrEqual(N->getOperand(i), i))
2266 for (unsigned i = 0; i < NumElems/2; ++i) {
2267 SDValue Arg = N->getOperand(i + NumElems/2);
2268 if (!isUndefOrEqual(Arg, i + NumElems))
2275 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2276 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2277 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2278 bool V2IsSplat = false) {
2279 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2282 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2283 SDValue BitI = Elts[i];
2284 SDValue BitI1 = Elts[i+1];
2285 if (!isUndefOrEqual(BitI, j))
2288 if (isUndefOrEqual(BitI1, NumElts))
2291 if (!isUndefOrEqual(BitI1, j + NumElts))
2299 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2300 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2301 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2304 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2305 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2306 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2307 bool V2IsSplat = false) {
2308 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2311 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2312 SDValue BitI = Elts[i];
2313 SDValue BitI1 = Elts[i+1];
2314 if (!isUndefOrEqual(BitI, j + NumElts/2))
2317 if (isUndefOrEqual(BitI1, NumElts))
2320 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2328 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2329 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2330 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2333 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2334 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2336 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2337 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2339 unsigned NumElems = N->getNumOperands();
2340 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2343 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2344 SDValue BitI = N->getOperand(i);
2345 SDValue BitI1 = N->getOperand(i+1);
2347 if (!isUndefOrEqual(BitI, j))
2349 if (!isUndefOrEqual(BitI1, j))
2356 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2357 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2359 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2360 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2362 unsigned NumElems = N->getNumOperands();
2363 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2366 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2367 SDValue BitI = N->getOperand(i);
2368 SDValue BitI1 = N->getOperand(i + 1);
2370 if (!isUndefOrEqual(BitI, j))
2372 if (!isUndefOrEqual(BitI1, j))
2379 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2380 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2381 /// MOVSD, and MOVD, i.e. setting the lowest element.
2382 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2383 if (NumElts != 2 && NumElts != 4)
2386 if (!isUndefOrEqual(Elts[0], NumElts))
2389 for (unsigned i = 1; i < NumElts; ++i) {
2390 if (!isUndefOrEqual(Elts[i], i))
2397 bool X86::isMOVLMask(SDNode *N) {
2398 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2399 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2402 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2403 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2404 /// element of vector 2 and the other elements to come from vector 1 in order.
2405 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2406 bool V2IsSplat = false,
2407 bool V2IsUndef = false) {
2408 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2411 if (!isUndefOrEqual(Ops[0], 0))
2414 for (unsigned i = 1; i < NumOps; ++i) {
2415 SDValue Arg = Ops[i];
2416 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2417 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2418 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2425 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2426 bool V2IsUndef = false) {
2427 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2428 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2429 V2IsSplat, V2IsUndef);
2432 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2433 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2434 bool X86::isMOVSHDUPMask(SDNode *N) {
2435 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2437 if (N->getNumOperands() != 4)
2440 // Expect 1, 1, 3, 3
2441 for (unsigned i = 0; i < 2; ++i) {
2442 SDValue Arg = N->getOperand(i);
2443 if (Arg.getOpcode() == ISD::UNDEF) continue;
2444 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2445 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2446 if (Val != 1) return false;
2450 for (unsigned i = 2; i < 4; ++i) {
2451 SDValue Arg = N->getOperand(i);
2452 if (Arg.getOpcode() == ISD::UNDEF) continue;
2453 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2454 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2455 if (Val != 3) return false;
2459 // Don't use movshdup if it can be done with a shufps.
2463 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2464 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2465 bool X86::isMOVSLDUPMask(SDNode *N) {
2466 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2468 if (N->getNumOperands() != 4)
2471 // Expect 0, 0, 2, 2
2472 for (unsigned i = 0; i < 2; ++i) {
2473 SDValue Arg = N->getOperand(i);
2474 if (Arg.getOpcode() == ISD::UNDEF) continue;
2475 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2476 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2477 if (Val != 0) return false;
2481 for (unsigned i = 2; i < 4; ++i) {
2482 SDValue Arg = N->getOperand(i);
2483 if (Arg.getOpcode() == ISD::UNDEF) continue;
2484 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2485 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2486 if (Val != 2) return false;
2490 // Don't use movshdup if it can be done with a shufps.
2494 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2495 /// specifies a identity operation on the LHS or RHS.
2496 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2497 unsigned NumElems = N->getNumOperands();
2498 for (unsigned i = 0; i < NumElems; ++i)
2499 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2504 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2505 /// a splat of a single element.
2506 static bool isSplatMask(SDNode *N) {
2507 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2509 // This is a splat operation if each element of the permute is the same, and
2510 // if the value doesn't reference the second vector.
2511 unsigned NumElems = N->getNumOperands();
2512 SDValue ElementBase;
2514 for (; i != NumElems; ++i) {
2515 SDValue Elt = N->getOperand(i);
2516 if (isa<ConstantSDNode>(Elt)) {
2522 if (!ElementBase.getNode())
2525 for (; i != NumElems; ++i) {
2526 SDValue Arg = N->getOperand(i);
2527 if (Arg.getOpcode() == ISD::UNDEF) continue;
2528 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2529 if (Arg != ElementBase) return false;
2532 // Make sure it is a splat of the first vector operand.
2533 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2536 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2537 /// a splat of a single element and it's a 2 or 4 element mask.
2538 bool X86::isSplatMask(SDNode *N) {
2539 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2541 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2542 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2544 return ::isSplatMask(N);
2547 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2548 /// specifies a splat of zero element.
2549 bool X86::isSplatLoMask(SDNode *N) {
2550 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2552 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2553 if (!isUndefOrEqual(N->getOperand(i), 0))
2558 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2559 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2560 bool X86::isMOVDDUPMask(SDNode *N) {
2561 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2563 unsigned e = N->getNumOperands() / 2;
2564 for (unsigned i = 0; i < e; ++i)
2565 if (!isUndefOrEqual(N->getOperand(i), i))
2567 for (unsigned i = 0; i < e; ++i)
2568 if (!isUndefOrEqual(N->getOperand(e+i), i))
2573 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2574 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2576 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2577 unsigned NumOperands = N->getNumOperands();
2578 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2580 for (unsigned i = 0; i < NumOperands; ++i) {
2582 SDValue Arg = N->getOperand(NumOperands-i-1);
2583 if (Arg.getOpcode() != ISD::UNDEF)
2584 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2585 if (Val >= NumOperands) Val -= NumOperands;
2587 if (i != NumOperands - 1)
2594 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2595 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2597 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2599 // 8 nodes, but we only care about the last 4.
2600 for (unsigned i = 7; i >= 4; --i) {
2602 SDValue Arg = N->getOperand(i);
2603 if (Arg.getOpcode() != ISD::UNDEF)
2604 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2613 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2614 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2616 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2618 // 8 nodes, but we only care about the first 4.
2619 for (int i = 3; i >= 0; --i) {
2621 SDValue Arg = N->getOperand(i);
2622 if (Arg.getOpcode() != ISD::UNDEF)
2623 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2632 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2633 /// specifies a 8 element shuffle that can be broken into a pair of
2634 /// PSHUFHW and PSHUFLW.
2635 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2636 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2638 if (N->getNumOperands() != 8)
2641 // Lower quadword shuffled.
2642 for (unsigned i = 0; i != 4; ++i) {
2643 SDValue Arg = N->getOperand(i);
2644 if (Arg.getOpcode() == ISD::UNDEF) continue;
2645 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2646 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2651 // Upper quadword shuffled.
2652 for (unsigned i = 4; i != 8; ++i) {
2653 SDValue Arg = N->getOperand(i);
2654 if (Arg.getOpcode() == ISD::UNDEF) continue;
2655 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2656 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2657 if (Val < 4 || Val > 7)
2664 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2665 /// values in ther permute mask.
2666 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2667 SDValue &V2, SDValue &Mask,
2668 SelectionDAG &DAG) {
2669 MVT VT = Op.getValueType();
2670 MVT MaskVT = Mask.getValueType();
2671 MVT EltVT = MaskVT.getVectorElementType();
2672 unsigned NumElems = Mask.getNumOperands();
2673 SmallVector<SDValue, 8> MaskVec;
2675 for (unsigned i = 0; i != NumElems; ++i) {
2676 SDValue Arg = Mask.getOperand(i);
2677 if (Arg.getOpcode() == ISD::UNDEF) {
2678 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2681 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2682 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2684 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2686 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2690 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2691 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2694 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2695 /// the two vector operands have swapped position.
2697 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2698 MVT MaskVT = Mask.getValueType();
2699 MVT EltVT = MaskVT.getVectorElementType();
2700 unsigned NumElems = Mask.getNumOperands();
2701 SmallVector<SDValue, 8> MaskVec;
2702 for (unsigned i = 0; i != NumElems; ++i) {
2703 SDValue Arg = Mask.getOperand(i);
2704 if (Arg.getOpcode() == ISD::UNDEF) {
2705 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2708 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2709 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2711 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2713 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2715 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2719 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2720 /// match movhlps. The lower half elements should come from upper half of
2721 /// V1 (and in order), and the upper half elements should come from the upper
2722 /// half of V2 (and in order).
2723 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2724 unsigned NumElems = Mask->getNumOperands();
2727 for (unsigned i = 0, e = 2; i != e; ++i)
2728 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2730 for (unsigned i = 2; i != 4; ++i)
2731 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2736 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2737 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2739 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2740 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2742 N = N->getOperand(0).getNode();
2743 if (!ISD::isNON_EXTLoad(N))
2746 *LD = cast<LoadSDNode>(N);
2750 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2751 /// match movlp{s|d}. The lower half elements should come from lower half of
2752 /// V1 (and in order), and the upper half elements should come from the upper
2753 /// half of V2 (and in order). And since V1 will become the source of the
2754 /// MOVLP, it must be either a vector load or a scalar load to vector.
2755 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2756 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2758 // Is V2 is a vector load, don't do this transformation. We will try to use
2759 // load folding shufps op.
2760 if (ISD::isNON_EXTLoad(V2))
2763 unsigned NumElems = Mask->getNumOperands();
2764 if (NumElems != 2 && NumElems != 4)
2766 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2767 if (!isUndefOrEqual(Mask->getOperand(i), i))
2769 for (unsigned i = NumElems/2; i != NumElems; ++i)
2770 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2775 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2777 static bool isSplatVector(SDNode *N) {
2778 if (N->getOpcode() != ISD::BUILD_VECTOR)
2781 SDValue SplatValue = N->getOperand(0);
2782 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2783 if (N->getOperand(i) != SplatValue)
2788 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2790 static bool isUndefShuffle(SDNode *N) {
2791 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2794 SDValue V1 = N->getOperand(0);
2795 SDValue V2 = N->getOperand(1);
2796 SDValue Mask = N->getOperand(2);
2797 unsigned NumElems = Mask.getNumOperands();
2798 for (unsigned i = 0; i != NumElems; ++i) {
2799 SDValue Arg = Mask.getOperand(i);
2800 if (Arg.getOpcode() != ISD::UNDEF) {
2801 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2802 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2804 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2811 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2813 static inline bool isZeroNode(SDValue Elt) {
2814 return ((isa<ConstantSDNode>(Elt) &&
2815 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2816 (isa<ConstantFPSDNode>(Elt) &&
2817 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2820 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2821 /// to an zero vector.
2822 static bool isZeroShuffle(SDNode *N) {
2823 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2826 SDValue V1 = N->getOperand(0);
2827 SDValue V2 = N->getOperand(1);
2828 SDValue Mask = N->getOperand(2);
2829 unsigned NumElems = Mask.getNumOperands();
2830 for (unsigned i = 0; i != NumElems; ++i) {
2831 SDValue Arg = Mask.getOperand(i);
2832 if (Arg.getOpcode() == ISD::UNDEF)
2835 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2836 if (Idx < NumElems) {
2837 unsigned Opc = V1.getNode()->getOpcode();
2838 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2840 if (Opc != ISD::BUILD_VECTOR ||
2841 !isZeroNode(V1.getNode()->getOperand(Idx)))
2843 } else if (Idx >= NumElems) {
2844 unsigned Opc = V2.getNode()->getOpcode();
2845 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2847 if (Opc != ISD::BUILD_VECTOR ||
2848 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2855 /// getZeroVector - Returns a vector of specified type with all zero elements.
2857 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2858 assert(VT.isVector() && "Expected a vector type");
2860 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2861 // type. This ensures they get CSE'd.
2863 if (VT.getSizeInBits() == 64) { // MMX
2864 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2865 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2866 } else if (HasSSE2) { // SSE2
2867 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2868 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2870 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2871 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2873 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2876 /// getOnesVector - Returns a vector of specified type with all bits set.
2878 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2879 assert(VT.isVector() && "Expected a vector type");
2881 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2882 // type. This ensures they get CSE'd.
2883 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2885 if (VT.getSizeInBits() == 64) // MMX
2886 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2888 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2889 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2893 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2894 /// that point to V2 points to its first element.
2895 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2896 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2898 bool Changed = false;
2899 SmallVector<SDValue, 8> MaskVec;
2900 unsigned NumElems = Mask.getNumOperands();
2901 for (unsigned i = 0; i != NumElems; ++i) {
2902 SDValue Arg = Mask.getOperand(i);
2903 if (Arg.getOpcode() != ISD::UNDEF) {
2904 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2905 if (Val > NumElems) {
2906 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2910 MaskVec.push_back(Arg);
2914 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2915 &MaskVec[0], MaskVec.size());
2919 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2920 /// operation of specified width.
2921 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2922 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2923 MVT BaseVT = MaskVT.getVectorElementType();
2925 SmallVector<SDValue, 8> MaskVec;
2926 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2927 for (unsigned i = 1; i != NumElems; ++i)
2928 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2929 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2932 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2933 /// of specified width.
2934 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2935 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2936 MVT BaseVT = MaskVT.getVectorElementType();
2937 SmallVector<SDValue, 8> MaskVec;
2938 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2939 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2940 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2942 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2945 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2946 /// of specified width.
2947 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2948 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2949 MVT BaseVT = MaskVT.getVectorElementType();
2950 unsigned Half = NumElems/2;
2951 SmallVector<SDValue, 8> MaskVec;
2952 for (unsigned i = 0; i != Half; ++i) {
2953 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2954 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2956 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2959 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2960 /// element #0 of a vector with the specified index, leaving the rest of the
2961 /// elements in place.
2962 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2963 SelectionDAG &DAG) {
2964 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2965 MVT BaseVT = MaskVT.getVectorElementType();
2966 SmallVector<SDValue, 8> MaskVec;
2967 // Element #0 of the result gets the elt we are replacing.
2968 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2969 for (unsigned i = 1; i != NumElems; ++i)
2970 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2971 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2974 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2975 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
2976 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2977 MVT VT = Op.getValueType();
2980 SDValue V1 = Op.getOperand(0);
2981 SDValue Mask = Op.getOperand(2);
2982 unsigned NumElems = Mask.getNumOperands();
2983 // Special handling of v4f32 -> v4i32.
2984 if (VT != MVT::v4f32) {
2985 Mask = getUnpacklMask(NumElems, DAG);
2986 while (NumElems > 4) {
2987 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2990 Mask = getZeroVector(MVT::v4i32, true, DAG);
2993 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
2994 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
2995 DAG.getNode(ISD::UNDEF, PVT), Mask);
2996 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2999 /// isVectorLoad - Returns true if the node is a vector load, a scalar
3000 /// load that's promoted to vector, or a load bitcasted.
3001 static bool isVectorLoad(SDValue Op) {
3002 assert(Op.getValueType().isVector() && "Expected a vector type");
3003 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
3004 Op.getOpcode() == ISD::BIT_CONVERT) {
3005 return isa<LoadSDNode>(Op.getOperand(0));
3007 return isa<LoadSDNode>(Op);
3011 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3013 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3014 SelectionDAG &DAG, bool HasSSE3) {
3015 // If we have sse3 and shuffle has more than one use or input is a load, then
3016 // use movddup. Otherwise, use movlhps.
3017 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3018 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3019 MVT VT = Op.getValueType();
3022 unsigned NumElems = PVT.getVectorNumElements();
3023 if (NumElems == 2) {
3024 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3025 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
3027 assert(NumElems == 4);
3028 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3029 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3030 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1);
3033 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3034 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3035 DAG.getNode(ISD::UNDEF, PVT), Mask);
3036 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3039 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3040 /// vector of zero or undef vector. This produces a shuffle where the low
3041 /// element of V2 is swizzled into the zero/undef vector, landing at element
3042 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3043 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3044 bool isZero, bool HasSSE2,
3045 SelectionDAG &DAG) {
3046 MVT VT = V2.getValueType();
3048 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
3049 unsigned NumElems = V2.getValueType().getVectorNumElements();
3050 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3051 MVT EVT = MaskVT.getVectorElementType();
3052 SmallVector<SDValue, 16> MaskVec;
3053 for (unsigned i = 0; i != NumElems; ++i)
3054 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3055 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3057 MaskVec.push_back(DAG.getConstant(i, EVT));
3058 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3059 &MaskVec[0], MaskVec.size());
3060 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3063 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3064 /// a shuffle that is zero.
3066 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3067 unsigned NumElems, bool Low,
3068 SelectionDAG &DAG) {
3069 unsigned NumZeros = 0;
3070 for (unsigned i = 0; i < NumElems; ++i) {
3071 unsigned Index = Low ? i : NumElems-i-1;
3072 SDValue Idx = Mask.getOperand(Index);
3073 if (Idx.getOpcode() == ISD::UNDEF) {
3077 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3078 if (Elt.getNode() && isZeroNode(Elt))
3086 /// isVectorShift - Returns true if the shuffle can be implemented as a
3087 /// logical left or right shift of a vector.
3088 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3089 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3090 unsigned NumElems = Mask.getNumOperands();
3093 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3096 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3101 bool SeenV1 = false;
3102 bool SeenV2 = false;
3103 for (unsigned i = NumZeros; i < NumElems; ++i) {
3104 unsigned Val = isLeft ? (i - NumZeros) : i;
3105 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3106 if (Idx.getOpcode() == ISD::UNDEF)
3108 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3109 if (Index < NumElems)
3118 if (SeenV1 && SeenV2)
3121 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3127 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3129 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3130 unsigned NumNonZero, unsigned NumZero,
3131 SelectionDAG &DAG, TargetLowering &TLI) {
3137 for (unsigned i = 0; i < 16; ++i) {
3138 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3139 if (ThisIsNonZero && First) {
3141 V = getZeroVector(MVT::v8i16, true, DAG);
3143 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3148 SDValue ThisElt(0, 0), LastElt(0, 0);
3149 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3150 if (LastIsNonZero) {
3151 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3153 if (ThisIsNonZero) {
3154 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3155 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3156 ThisElt, DAG.getConstant(8, MVT::i8));
3158 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3162 if (ThisElt.getNode())
3163 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3164 DAG.getIntPtrConstant(i/2));
3168 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3171 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3173 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3174 unsigned NumNonZero, unsigned NumZero,
3175 SelectionDAG &DAG, TargetLowering &TLI) {
3181 for (unsigned i = 0; i < 8; ++i) {
3182 bool isNonZero = (NonZeros & (1 << i)) != 0;
3186 V = getZeroVector(MVT::v8i16, true, DAG);
3188 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3191 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3192 DAG.getIntPtrConstant(i));
3199 /// getVShift - Return a vector logical shift node.
3201 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3202 unsigned NumBits, SelectionDAG &DAG,
3203 const TargetLowering &TLI) {
3204 bool isMMX = VT.getSizeInBits() == 64;
3205 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3206 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3207 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3208 return DAG.getNode(ISD::BIT_CONVERT, VT,
3209 DAG.getNode(Opc, ShVT, SrcOp,
3210 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3214 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3215 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3216 if (ISD::isBuildVectorAllZeros(Op.getNode())
3217 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3218 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3219 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3220 // eliminated on x86-32 hosts.
3221 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3224 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3225 return getOnesVector(Op.getValueType(), DAG);
3226 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3229 MVT VT = Op.getValueType();
3230 MVT EVT = VT.getVectorElementType();
3231 unsigned EVTBits = EVT.getSizeInBits();
3233 unsigned NumElems = Op.getNumOperands();
3234 unsigned NumZero = 0;
3235 unsigned NumNonZero = 0;
3236 unsigned NonZeros = 0;
3237 bool IsAllConstants = true;
3238 SmallSet<SDValue, 8> Values;
3239 for (unsigned i = 0; i < NumElems; ++i) {
3240 SDValue Elt = Op.getOperand(i);
3241 if (Elt.getOpcode() == ISD::UNDEF)
3244 if (Elt.getOpcode() != ISD::Constant &&
3245 Elt.getOpcode() != ISD::ConstantFP)
3246 IsAllConstants = false;
3247 if (isZeroNode(Elt))
3250 NonZeros |= (1 << i);
3255 if (NumNonZero == 0) {
3256 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3257 return DAG.getNode(ISD::UNDEF, VT);
3260 // Special case for single non-zero, non-undef, element.
3261 if (NumNonZero == 1 && NumElems <= 4) {
3262 unsigned Idx = CountTrailingZeros_32(NonZeros);
3263 SDValue Item = Op.getOperand(Idx);
3265 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3266 // the value are obviously zero, truncate the value to i32 and do the
3267 // insertion that way. Only do this if the value is non-constant or if the
3268 // value is a constant being inserted into element 0. It is cheaper to do
3269 // a constant pool load than it is to do a movd + shuffle.
3270 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3271 (!IsAllConstants || Idx == 0)) {
3272 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3273 // Handle MMX and SSE both.
3274 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3275 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3277 // Truncate the value (which may itself be a constant) to i32, and
3278 // convert it to a vector with movd (S2V+shuffle to zero extend).
3279 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3280 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3281 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3282 Subtarget->hasSSE2(), DAG);
3284 // Now we have our 32-bit value zero extended in the low element of
3285 // a vector. If Idx != 0, swizzle it into place.
3288 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3289 getSwapEltZeroMask(VecElts, Idx, DAG)
3291 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3293 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3297 // If we have a constant or non-constant insertion into the low element of
3298 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3299 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3300 // depending on what the source datatype is. Because we can only get here
3301 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3303 // Don't do this for i64 values on x86-32.
3304 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3305 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3306 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3307 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3308 Subtarget->hasSSE2(), DAG);
3311 // Is it a vector logical left shift?
3312 if (NumElems == 2 && Idx == 1 &&
3313 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3314 unsigned NumBits = VT.getSizeInBits();
3315 return getVShift(true, VT,
3316 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3317 NumBits/2, DAG, *this);
3320 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3323 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3324 // is a non-constant being inserted into an element other than the low one,
3325 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3326 // movd/movss) to move this into the low element, then shuffle it into
3328 if (EVTBits == 32) {
3329 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3331 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3332 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3333 Subtarget->hasSSE2(), DAG);
3334 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3335 MVT MaskEVT = MaskVT.getVectorElementType();
3336 SmallVector<SDValue, 8> MaskVec;
3337 for (unsigned i = 0; i < NumElems; i++)
3338 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3339 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3340 &MaskVec[0], MaskVec.size());
3341 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3342 DAG.getNode(ISD::UNDEF, VT), Mask);
3346 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3347 if (Values.size() == 1)
3350 // A vector full of immediates; various special cases are already
3351 // handled, so this is best done with a single constant-pool load.
3355 // Let legalizer expand 2-wide build_vectors.
3356 if (EVTBits == 64) {
3357 if (NumNonZero == 1) {
3358 // One half is zero or undef.
3359 unsigned Idx = CountTrailingZeros_32(NonZeros);
3360 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3361 Op.getOperand(Idx));
3362 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3363 Subtarget->hasSSE2(), DAG);
3368 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3369 if (EVTBits == 8 && NumElems == 16) {
3370 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3372 if (V.getNode()) return V;
3375 if (EVTBits == 16 && NumElems == 8) {
3376 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3378 if (V.getNode()) return V;
3381 // If element VT is == 32 bits, turn it into a number of shuffles.
3382 SmallVector<SDValue, 8> V;
3384 if (NumElems == 4 && NumZero > 0) {
3385 for (unsigned i = 0; i < 4; ++i) {
3386 bool isZero = !(NonZeros & (1 << i));
3388 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3390 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3393 for (unsigned i = 0; i < 2; ++i) {
3394 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3397 V[i] = V[i*2]; // Must be a zero vector.
3400 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3401 getMOVLMask(NumElems, DAG));
3404 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3405 getMOVLMask(NumElems, DAG));
3408 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3409 getUnpacklMask(NumElems, DAG));
3414 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3415 MVT EVT = MaskVT.getVectorElementType();
3416 SmallVector<SDValue, 8> MaskVec;
3417 bool Reverse = (NonZeros & 0x3) == 2;
3418 for (unsigned i = 0; i < 2; ++i)
3420 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3422 MaskVec.push_back(DAG.getConstant(i, EVT));
3423 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3424 for (unsigned i = 0; i < 2; ++i)
3426 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3428 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3429 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3430 &MaskVec[0], MaskVec.size());
3431 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3434 if (Values.size() > 2) {
3435 // Expand into a number of unpckl*.
3437 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3438 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3439 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3440 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3441 for (unsigned i = 0; i < NumElems; ++i)
3442 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3444 while (NumElems != 0) {
3445 for (unsigned i = 0; i < NumElems; ++i)
3446 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3457 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3458 SDValue PermMask, SelectionDAG &DAG,
3459 TargetLowering &TLI) {
3461 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3462 MVT MaskEVT = MaskVT.getVectorElementType();
3463 MVT PtrVT = TLI.getPointerTy();
3464 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3465 PermMask.getNode()->op_end());
3467 // First record which half of which vector the low elements come from.
3468 SmallVector<unsigned, 4> LowQuad(4);
3469 for (unsigned i = 0; i < 4; ++i) {
3470 SDValue Elt = MaskElts[i];
3471 if (Elt.getOpcode() == ISD::UNDEF)
3473 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3474 int QuadIdx = EltIdx / 4;
3478 int BestLowQuad = -1;
3479 unsigned MaxQuad = 1;
3480 for (unsigned i = 0; i < 4; ++i) {
3481 if (LowQuad[i] > MaxQuad) {
3483 MaxQuad = LowQuad[i];
3487 // Record which half of which vector the high elements come from.
3488 SmallVector<unsigned, 4> HighQuad(4);
3489 for (unsigned i = 4; i < 8; ++i) {
3490 SDValue Elt = MaskElts[i];
3491 if (Elt.getOpcode() == ISD::UNDEF)
3493 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3494 int QuadIdx = EltIdx / 4;
3495 ++HighQuad[QuadIdx];
3498 int BestHighQuad = -1;
3500 for (unsigned i = 0; i < 4; ++i) {
3501 if (HighQuad[i] > MaxQuad) {
3503 MaxQuad = HighQuad[i];
3507 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3508 if (BestLowQuad != -1 || BestHighQuad != -1) {
3509 // First sort the 4 chunks in order using shufpd.
3510 SmallVector<SDValue, 8> MaskVec;
3512 if (BestLowQuad != -1)
3513 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3515 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3517 if (BestHighQuad != -1)
3518 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3520 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3522 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3523 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3524 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3525 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3526 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3528 // Now sort high and low parts separately.
3529 BitVector InOrder(8);
3530 if (BestLowQuad != -1) {
3531 // Sort lower half in order using PSHUFLW.
3533 bool AnyOutOrder = false;
3535 for (unsigned i = 0; i != 4; ++i) {
3536 SDValue Elt = MaskElts[i];
3537 if (Elt.getOpcode() == ISD::UNDEF) {
3538 MaskVec.push_back(Elt);
3541 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3545 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3547 // If this element is in the right place after this shuffle, then
3549 if ((int)(EltIdx / 4) == BestLowQuad)
3554 for (unsigned i = 4; i != 8; ++i)
3555 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3556 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3557 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3561 if (BestHighQuad != -1) {
3562 // Sort high half in order using PSHUFHW if possible.
3565 for (unsigned i = 0; i != 4; ++i)
3566 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3568 bool AnyOutOrder = false;
3569 for (unsigned i = 4; i != 8; ++i) {
3570 SDValue Elt = MaskElts[i];
3571 if (Elt.getOpcode() == ISD::UNDEF) {
3572 MaskVec.push_back(Elt);
3575 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3579 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3581 // If this element is in the right place after this shuffle, then
3583 if ((int)(EltIdx / 4) == BestHighQuad)
3589 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3590 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3594 // The other elements are put in the right place using pextrw and pinsrw.
3595 for (unsigned i = 0; i != 8; ++i) {
3598 SDValue Elt = MaskElts[i];
3599 if (Elt.getOpcode() == ISD::UNDEF)
3601 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3602 SDValue ExtOp = (EltIdx < 8)
3603 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3604 DAG.getConstant(EltIdx, PtrVT))
3605 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3606 DAG.getConstant(EltIdx - 8, PtrVT));
3607 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3608 DAG.getConstant(i, PtrVT));
3614 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3615 // few as possible. First, let's find out how many elements are already in the
3617 unsigned V1InOrder = 0;
3618 unsigned V1FromV1 = 0;
3619 unsigned V2InOrder = 0;
3620 unsigned V2FromV2 = 0;
3621 SmallVector<SDValue, 8> V1Elts;
3622 SmallVector<SDValue, 8> V2Elts;
3623 for (unsigned i = 0; i < 8; ++i) {
3624 SDValue Elt = MaskElts[i];
3625 if (Elt.getOpcode() == ISD::UNDEF) {
3626 V1Elts.push_back(Elt);
3627 V2Elts.push_back(Elt);
3632 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3634 V1Elts.push_back(Elt);
3635 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3637 } else if (EltIdx == i+8) {
3638 V1Elts.push_back(Elt);
3639 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3641 } else if (EltIdx < 8) {
3642 V1Elts.push_back(Elt);
3645 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3650 if (V2InOrder > V1InOrder) {
3651 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3653 std::swap(V1Elts, V2Elts);
3654 std::swap(V1FromV1, V2FromV2);
3657 if ((V1FromV1 + V1InOrder) != 8) {
3658 // Some elements are from V2.
3660 // If there are elements that are from V1 but out of place,
3661 // then first sort them in place
3662 SmallVector<SDValue, 8> MaskVec;
3663 for (unsigned i = 0; i < 8; ++i) {
3664 SDValue Elt = V1Elts[i];
3665 if (Elt.getOpcode() == ISD::UNDEF) {
3666 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3669 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3671 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3673 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3675 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3676 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3680 for (unsigned i = 0; i < 8; ++i) {
3681 SDValue Elt = V1Elts[i];
3682 if (Elt.getOpcode() == ISD::UNDEF)
3684 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3687 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3688 DAG.getConstant(EltIdx - 8, PtrVT));
3689 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3690 DAG.getConstant(i, PtrVT));
3694 // All elements are from V1.
3696 for (unsigned i = 0; i < 8; ++i) {
3697 SDValue Elt = V1Elts[i];
3698 if (Elt.getOpcode() == ISD::UNDEF)
3700 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3701 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3702 DAG.getConstant(EltIdx, PtrVT));
3703 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3704 DAG.getConstant(i, PtrVT));
3710 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3711 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3712 /// done when every pair / quad of shuffle mask elements point to elements in
3713 /// the right sequence. e.g.
3714 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3716 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3718 SDValue PermMask, SelectionDAG &DAG,
3719 TargetLowering &TLI) {
3720 unsigned NumElems = PermMask.getNumOperands();
3721 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3722 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3723 MVT MaskEltVT = MaskVT.getVectorElementType();
3725 switch (VT.getSimpleVT()) {
3726 default: assert(false && "Unexpected!");
3727 case MVT::v4f32: NewVT = MVT::v2f64; break;
3728 case MVT::v4i32: NewVT = MVT::v2i64; break;
3729 case MVT::v8i16: NewVT = MVT::v4i32; break;
3730 case MVT::v16i8: NewVT = MVT::v4i32; break;
3733 if (NewWidth == 2) {
3739 unsigned Scale = NumElems / NewWidth;
3740 SmallVector<SDValue, 8> MaskVec;
3741 for (unsigned i = 0; i < NumElems; i += Scale) {
3742 unsigned StartIdx = ~0U;
3743 for (unsigned j = 0; j < Scale; ++j) {
3744 SDValue Elt = PermMask.getOperand(i+j);
3745 if (Elt.getOpcode() == ISD::UNDEF)
3747 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3748 if (StartIdx == ~0U)
3749 StartIdx = EltIdx - (EltIdx % Scale);
3750 if (EltIdx != StartIdx + j)
3753 if (StartIdx == ~0U)
3754 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3756 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3759 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3760 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3761 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3762 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3763 &MaskVec[0], MaskVec.size()));
3766 /// getVZextMovL - Return a zero-extending vector move low node.
3768 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3769 SDValue SrcOp, SelectionDAG &DAG,
3770 const X86Subtarget *Subtarget) {
3771 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3772 LoadSDNode *LD = NULL;
3773 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3774 LD = dyn_cast<LoadSDNode>(SrcOp);
3776 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3778 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3779 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3780 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3781 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3782 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3784 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3785 return DAG.getNode(ISD::BIT_CONVERT, VT,
3786 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3787 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3794 return DAG.getNode(ISD::BIT_CONVERT, VT,
3795 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3796 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3799 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3802 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3803 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3804 MVT MaskVT = PermMask.getValueType();
3805 MVT MaskEVT = MaskVT.getVectorElementType();
3806 SmallVector<std::pair<int, int>, 8> Locs;
3808 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3811 for (unsigned i = 0; i != 4; ++i) {
3812 SDValue Elt = PermMask.getOperand(i);
3813 if (Elt.getOpcode() == ISD::UNDEF) {
3814 Locs[i] = std::make_pair(-1, -1);
3816 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3817 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3819 Locs[i] = std::make_pair(0, NumLo);
3823 Locs[i] = std::make_pair(1, NumHi);
3825 Mask1[2+NumHi] = Elt;
3831 if (NumLo <= 2 && NumHi <= 2) {
3832 // If no more than two elements come from either vector. This can be
3833 // implemented with two shuffles. First shuffle gather the elements.
3834 // The second shuffle, which takes the first shuffle as both of its
3835 // vector operands, put the elements into the right order.
3836 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3837 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3838 &Mask1[0], Mask1.size()));
3840 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3841 for (unsigned i = 0; i != 4; ++i) {
3842 if (Locs[i].first == -1)
3845 unsigned Idx = (i < 2) ? 0 : 4;
3846 Idx += Locs[i].first * 2 + Locs[i].second;
3847 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3851 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3852 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3853 &Mask2[0], Mask2.size()));
3854 } else if (NumLo == 3 || NumHi == 3) {
3855 // Otherwise, we must have three elements from one vector, call it X, and
3856 // one element from the other, call it Y. First, use a shufps to build an
3857 // intermediate vector with the one element from Y and the element from X
3858 // that will be in the same half in the final destination (the indexes don't
3859 // matter). Then, use a shufps to build the final vector, taking the half
3860 // containing the element from Y from the intermediate, and the other half
3863 // Normalize it so the 3 elements come from V1.
3864 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3868 // Find the element from V2.
3870 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3871 SDValue Elt = PermMask.getOperand(HiIndex);
3872 if (Elt.getOpcode() == ISD::UNDEF)
3874 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3879 Mask1[0] = PermMask.getOperand(HiIndex);
3880 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3881 Mask1[2] = PermMask.getOperand(HiIndex^1);
3882 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3883 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3884 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3887 Mask1[0] = PermMask.getOperand(0);
3888 Mask1[1] = PermMask.getOperand(1);
3889 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3890 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3891 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3892 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3894 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3895 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3896 Mask1[2] = PermMask.getOperand(2);
3897 Mask1[3] = PermMask.getOperand(3);
3898 if (Mask1[2].getOpcode() != ISD::UNDEF)
3900 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3902 if (Mask1[3].getOpcode() != ISD::UNDEF)
3904 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
3906 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3907 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3911 // Break it into (shuffle shuffle_hi, shuffle_lo).
3913 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3914 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3915 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3916 unsigned MaskIdx = 0;
3919 for (unsigned i = 0; i != 4; ++i) {
3926 SDValue Elt = PermMask.getOperand(i);
3927 if (Elt.getOpcode() == ISD::UNDEF) {
3928 Locs[i] = std::make_pair(-1, -1);
3929 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
3930 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3931 (*MaskPtr)[LoIdx] = Elt;
3934 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3935 (*MaskPtr)[HiIdx] = Elt;
3940 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3941 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3942 &LoMask[0], LoMask.size()));
3943 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3944 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3945 &HiMask[0], HiMask.size()));
3946 SmallVector<SDValue, 8> MaskOps;
3947 for (unsigned i = 0; i != 4; ++i) {
3948 if (Locs[i].first == -1) {
3949 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3951 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3952 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3955 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3956 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3957 &MaskOps[0], MaskOps.size()));
3961 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3962 SDValue V1 = Op.getOperand(0);
3963 SDValue V2 = Op.getOperand(1);
3964 SDValue PermMask = Op.getOperand(2);
3965 MVT VT = Op.getValueType();
3966 unsigned NumElems = PermMask.getNumOperands();
3967 bool isMMX = VT.getSizeInBits() == 64;
3968 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3969 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3970 bool V1IsSplat = false;
3971 bool V2IsSplat = false;
3973 if (isUndefShuffle(Op.getNode()))
3974 return DAG.getNode(ISD::UNDEF, VT);
3976 if (isZeroShuffle(Op.getNode()))
3977 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3979 if (isIdentityMask(PermMask.getNode()))
3981 else if (isIdentityMask(PermMask.getNode(), true))
3984 // Canonicalize movddup shuffles.
3985 if (V2IsUndef && Subtarget->hasSSE2() &&
3986 VT.getSizeInBits() == 128 &&
3987 X86::isMOVDDUPMask(PermMask.getNode()))
3988 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
3990 if (isSplatMask(PermMask.getNode())) {
3991 if (isMMX || NumElems < 4) return Op;
3992 // Promote it to a v4{if}32 splat.
3993 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
3996 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3998 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3999 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
4000 if (NewOp.getNode())
4001 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
4002 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4003 // FIXME: Figure out a cleaner way to do this.
4004 // Try to make use of movq to zero out the top part.
4005 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4006 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4008 if (NewOp.getNode()) {
4009 SDValue NewV1 = NewOp.getOperand(0);
4010 SDValue NewV2 = NewOp.getOperand(1);
4011 SDValue NewMask = NewOp.getOperand(2);
4012 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4013 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4014 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
4017 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4018 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4020 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4021 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4026 // Check if this can be converted into a logical shift.
4027 bool isLeft = false;
4030 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4031 if (isShift && ShVal.hasOneUse()) {
4032 // If the shifted value has multiple uses, it may be cheaper to use
4033 // v_set0 + movlhps or movhlps, etc.
4034 MVT EVT = VT.getVectorElementType();
4035 ShAmt *= EVT.getSizeInBits();
4036 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4039 if (X86::isMOVLMask(PermMask.getNode())) {
4042 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4043 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
4048 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4049 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4050 X86::isMOVHLPSMask(PermMask.getNode()) ||
4051 X86::isMOVHPMask(PermMask.getNode()) ||
4052 X86::isMOVLPMask(PermMask.getNode())))
4055 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4056 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4057 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4060 // No better options. Use a vshl / vsrl.
4061 MVT EVT = VT.getVectorElementType();
4062 ShAmt *= EVT.getSizeInBits();
4063 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4066 bool Commuted = false;
4067 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4068 // 1,1,1,1 -> v8i16 though.
4069 V1IsSplat = isSplatVector(V1.getNode());
4070 V2IsSplat = isSplatVector(V2.getNode());
4072 // Canonicalize the splat or undef, if present, to be on the RHS.
4073 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4074 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4075 std::swap(V1IsSplat, V2IsSplat);
4076 std::swap(V1IsUndef, V2IsUndef);
4080 // FIXME: Figure out a cleaner way to do this.
4081 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4082 if (V2IsUndef) return V1;
4083 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4085 // V2 is a splat, so the mask may be malformed. That is, it may point
4086 // to any V2 element. The instruction selectior won't like this. Get
4087 // a corrected mask and commute to form a proper MOVS{S|D}.
4088 SDValue NewMask = getMOVLMask(NumElems, DAG);
4089 if (NewMask.getNode() != PermMask.getNode())
4090 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4095 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4096 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4097 X86::isUNPCKLMask(PermMask.getNode()) ||
4098 X86::isUNPCKHMask(PermMask.getNode()))
4102 // Normalize mask so all entries that point to V2 points to its first
4103 // element then try to match unpck{h|l} again. If match, return a
4104 // new vector_shuffle with the corrected mask.
4105 SDValue NewMask = NormalizeMask(PermMask, DAG);
4106 if (NewMask.getNode() != PermMask.getNode()) {
4107 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
4108 SDValue NewMask = getUnpacklMask(NumElems, DAG);
4109 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4110 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
4111 SDValue NewMask = getUnpackhMask(NumElems, DAG);
4112 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4117 // Normalize the node to match x86 shuffle ops if needed
4118 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4119 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4122 // Commute is back and try unpck* again.
4123 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4124 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4125 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4126 X86::isUNPCKLMask(PermMask.getNode()) ||
4127 X86::isUNPCKHMask(PermMask.getNode()))
4131 // Try PSHUF* first, then SHUFP*.
4132 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4133 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4134 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4135 if (V2.getOpcode() != ISD::UNDEF)
4136 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4137 DAG.getNode(ISD::UNDEF, VT), PermMask);
4142 if (Subtarget->hasSSE2() &&
4143 (X86::isPSHUFDMask(PermMask.getNode()) ||
4144 X86::isPSHUFHWMask(PermMask.getNode()) ||
4145 X86::isPSHUFLWMask(PermMask.getNode()))) {
4147 if (VT == MVT::v4f32) {
4149 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4150 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4151 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4152 } else if (V2.getOpcode() != ISD::UNDEF)
4153 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4154 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4156 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4160 // Binary or unary shufps.
4161 if (X86::isSHUFPMask(PermMask.getNode()) ||
4162 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4166 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4167 if (VT == MVT::v8i16) {
4168 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4169 if (NewOp.getNode())
4173 // Handle all 4 wide cases with a number of shuffles except for MMX.
4174 if (NumElems == 4 && !isMMX)
4175 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4181 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4182 SelectionDAG &DAG) {
4183 MVT VT = Op.getValueType();
4184 if (VT.getSizeInBits() == 8) {
4185 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4186 Op.getOperand(0), Op.getOperand(1));
4187 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4188 DAG.getValueType(VT));
4189 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4190 } else if (VT.getSizeInBits() == 16) {
4191 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4192 Op.getOperand(0), Op.getOperand(1));
4193 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4194 DAG.getValueType(VT));
4195 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4196 } else if (VT == MVT::f32) {
4197 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4198 // the result back to FR32 register. It's only worth matching if the
4199 // result has a single use which is a store or a bitcast to i32. And in
4200 // the case of a store, it's not worth it if the index is a constant 0,
4201 // because a MOVSSmr can be used instead, which is smaller and faster.
4202 if (!Op.hasOneUse())
4204 SDNode *User = *Op.getNode()->use_begin();
4205 if ((User->getOpcode() != ISD::STORE ||
4206 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4207 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4208 (User->getOpcode() != ISD::BIT_CONVERT ||
4209 User->getValueType(0) != MVT::i32))
4211 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4212 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4214 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4221 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4222 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4225 if (Subtarget->hasSSE41()) {
4226 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4231 MVT VT = Op.getValueType();
4232 // TODO: handle v16i8.
4233 if (VT.getSizeInBits() == 16) {
4234 SDValue Vec = Op.getOperand(0);
4235 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4237 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4238 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4239 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4241 // Transform it so it match pextrw which produces a 32-bit result.
4242 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4243 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4244 Op.getOperand(0), Op.getOperand(1));
4245 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4246 DAG.getValueType(VT));
4247 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4248 } else if (VT.getSizeInBits() == 32) {
4249 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4252 // SHUFPS the element to the lowest double word, then movss.
4253 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4254 SmallVector<SDValue, 8> IdxVec;
4256 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4258 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4260 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4262 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4263 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4264 &IdxVec[0], IdxVec.size());
4265 SDValue Vec = Op.getOperand(0);
4266 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4267 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4268 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4269 DAG.getIntPtrConstant(0));
4270 } else if (VT.getSizeInBits() == 64) {
4271 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4272 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4273 // to match extract_elt for f64.
4274 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4278 // UNPCKHPD the element to the lowest double word, then movsd.
4279 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4280 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4281 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4282 SmallVector<SDValue, 8> IdxVec;
4283 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4285 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4286 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4287 &IdxVec[0], IdxVec.size());
4288 SDValue Vec = Op.getOperand(0);
4289 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4290 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4291 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4292 DAG.getIntPtrConstant(0));
4299 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4300 MVT VT = Op.getValueType();
4301 MVT EVT = VT.getVectorElementType();
4303 SDValue N0 = Op.getOperand(0);
4304 SDValue N1 = Op.getOperand(1);
4305 SDValue N2 = Op.getOperand(2);
4307 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4308 isa<ConstantSDNode>(N2)) {
4309 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4311 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4313 if (N1.getValueType() != MVT::i32)
4314 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4315 if (N2.getValueType() != MVT::i32)
4316 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4317 return DAG.getNode(Opc, VT, N0, N1, N2);
4318 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4319 // Bits [7:6] of the constant are the source select. This will always be
4320 // zero here. The DAG Combiner may combine an extract_elt index into these
4321 // bits. For example (insert (extract, 3), 2) could be matched by putting
4322 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4323 // Bits [5:4] of the constant are the destination select. This is the
4324 // value of the incoming immediate.
4325 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4326 // combine either bitwise AND or insert of float 0.0 to set these bits.
4327 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4328 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4334 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4335 MVT VT = Op.getValueType();
4336 MVT EVT = VT.getVectorElementType();
4338 if (Subtarget->hasSSE41())
4339 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4344 SDValue N0 = Op.getOperand(0);
4345 SDValue N1 = Op.getOperand(1);
4346 SDValue N2 = Op.getOperand(2);
4348 if (EVT.getSizeInBits() == 16) {
4349 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4350 // as its second argument.
4351 if (N1.getValueType() != MVT::i32)
4352 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4353 if (N2.getValueType() != MVT::i32)
4354 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4355 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4361 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4362 if (Op.getValueType() == MVT::v2f32)
4363 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4364 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4365 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4366 Op.getOperand(0))));
4368 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4369 MVT VT = MVT::v2i32;
4370 switch (Op.getValueType().getSimpleVT()) {
4377 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4378 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4381 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4382 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4383 // one of the above mentioned nodes. It has to be wrapped because otherwise
4384 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4385 // be used to form addressing mode. These wrapped nodes will be selected
4388 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4389 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4390 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4392 CP->getAlignment());
4393 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4394 // With PIC, the address is actually $g + Offset.
4395 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4396 !Subtarget->isPICStyleRIPRel()) {
4397 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4398 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4406 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV,
4408 SelectionDAG &DAG) const {
4409 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4410 bool ExtraLoadRequired =
4411 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4413 // Create the TargetGlobalAddress node, folding in the constant
4414 // offset if it is legal.
4416 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4417 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4420 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4421 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4423 // With PIC, the address is actually $g + Offset.
4424 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4425 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4426 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4430 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4431 // load the value at address GV, not the value of GV itself. This means that
4432 // the GlobalAddress must be in the base or index register of the address, not
4433 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4434 // The same applies for external symbols during PIC codegen
4435 if (ExtraLoadRequired)
4436 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4437 PseudoSourceValue::getGOT(), 0);
4439 // If there was a non-zero offset that we didn't fold, create an explicit
4442 Result = DAG.getNode(ISD::ADD, getPointerTy(), Result,
4443 DAG.getConstant(Offset, getPointerTy()));
4449 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4450 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4451 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4452 return LowerGlobalAddress(GV, Offset, DAG);
4455 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4457 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4460 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4461 DAG.getNode(X86ISD::GlobalBaseReg,
4463 InFlag = Chain.getValue(1);
4465 // emit leal symbol@TLSGD(,%ebx,1), %eax
4466 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4467 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4468 GA->getValueType(0),
4470 SDValue Ops[] = { Chain, TGA, InFlag };
4471 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4472 InFlag = Result.getValue(2);
4473 Chain = Result.getValue(1);
4475 // call ___tls_get_addr. This function receives its argument in
4476 // the register EAX.
4477 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4478 InFlag = Chain.getValue(1);
4480 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4481 SDValue Ops1[] = { Chain,
4482 DAG.getTargetExternalSymbol("___tls_get_addr",
4484 DAG.getRegister(X86::EAX, PtrVT),
4485 DAG.getRegister(X86::EBX, PtrVT),
4487 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4488 InFlag = Chain.getValue(1);
4490 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4493 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4495 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4497 SDValue InFlag, Chain;
4499 // emit leaq symbol@TLSGD(%rip), %rdi
4500 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4501 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4502 GA->getValueType(0),
4504 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4505 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4506 Chain = Result.getValue(1);
4507 InFlag = Result.getValue(2);
4509 // call __tls_get_addr. This function receives its argument in
4510 // the register RDI.
4511 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4512 InFlag = Chain.getValue(1);
4514 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4515 SDValue Ops1[] = { Chain,
4516 DAG.getTargetExternalSymbol("__tls_get_addr",
4518 DAG.getRegister(X86::RDI, PtrVT),
4520 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4521 InFlag = Chain.getValue(1);
4523 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4526 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4527 // "local exec" model.
4528 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4530 // Get the Thread Pointer
4531 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4532 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4534 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4535 GA->getValueType(0),
4537 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4539 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4540 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4541 PseudoSourceValue::getGOT(), 0);
4543 // The address of the thread local variable is the add of the thread
4544 // pointer with the offset of the variable.
4545 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4549 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4550 // TODO: implement the "local dynamic" model
4551 // TODO: implement the "initial exec"model for pic executables
4552 assert(Subtarget->isTargetELF() &&
4553 "TLS not implemented for non-ELF targets");
4554 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4555 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4556 // otherwise use the "Local Exec"TLS Model
4557 if (Subtarget->is64Bit()) {
4558 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4560 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4561 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4563 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4568 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4569 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4570 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4571 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4572 // With PIC, the address is actually $g + Offset.
4573 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4574 !Subtarget->isPICStyleRIPRel()) {
4575 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4576 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4583 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4584 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4585 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4586 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4587 // With PIC, the address is actually $g + Offset.
4588 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4589 !Subtarget->isPICStyleRIPRel()) {
4590 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4591 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4598 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4599 /// take a 2 x i32 value to shift plus a shift amount.
4600 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4601 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4602 MVT VT = Op.getValueType();
4603 unsigned VTBits = VT.getSizeInBits();
4604 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4605 SDValue ShOpLo = Op.getOperand(0);
4606 SDValue ShOpHi = Op.getOperand(1);
4607 SDValue ShAmt = Op.getOperand(2);
4608 SDValue Tmp1 = isSRA ?
4609 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4610 DAG.getConstant(0, VT);
4613 if (Op.getOpcode() == ISD::SHL_PARTS) {
4614 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4615 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4617 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4618 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4621 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4622 DAG.getConstant(VTBits, MVT::i8));
4623 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4624 AndNode, DAG.getConstant(0, MVT::i8));
4627 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4628 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4629 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4631 if (Op.getOpcode() == ISD::SHL_PARTS) {
4632 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4633 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4635 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4636 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4639 SDValue Ops[2] = { Lo, Hi };
4640 return DAG.getMergeValues(Ops, 2);
4643 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4644 MVT SrcVT = Op.getOperand(0).getValueType();
4645 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4646 "Unknown SINT_TO_FP to lower!");
4648 // These are really Legal; caller falls through into that case.
4649 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4651 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4652 Subtarget->is64Bit())
4655 unsigned Size = SrcVT.getSizeInBits()/8;
4656 MachineFunction &MF = DAG.getMachineFunction();
4657 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4658 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4659 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4661 PseudoSourceValue::getFixedStack(SSFI), 0);
4665 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4667 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4669 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4670 SmallVector<SDValue, 8> Ops;
4671 Ops.push_back(Chain);
4672 Ops.push_back(StackSlot);
4673 Ops.push_back(DAG.getValueType(SrcVT));
4674 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4675 Tys, &Ops[0], Ops.size());
4678 Chain = Result.getValue(1);
4679 SDValue InFlag = Result.getValue(2);
4681 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4682 // shouldn't be necessary except that RFP cannot be live across
4683 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4684 MachineFunction &MF = DAG.getMachineFunction();
4685 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4686 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4687 Tys = DAG.getVTList(MVT::Other);
4688 SmallVector<SDValue, 8> Ops;
4689 Ops.push_back(Chain);
4690 Ops.push_back(Result);
4691 Ops.push_back(StackSlot);
4692 Ops.push_back(DAG.getValueType(Op.getValueType()));
4693 Ops.push_back(InFlag);
4694 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4695 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4696 PseudoSourceValue::getFixedStack(SSFI), 0);
4702 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4703 MVT SrcVT = Op.getOperand(0).getValueType();
4704 assert(SrcVT.getSimpleVT() == MVT::i64 && "Unknown UINT_TO_FP to lower!");
4706 // We only handle SSE2 f64 target here; caller can handle the rest.
4707 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
4710 // This algorithm is not obvious. Here it is in C code, more or less:
4712 double uint64_to_double( uint32_t hi, uint32_t lo )
4714 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4715 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4717 // copy ints to xmm registers
4718 __m128i xh = _mm_cvtsi32_si128( hi );
4719 __m128i xl = _mm_cvtsi32_si128( lo );
4721 // combine into low half of a single xmm register
4722 __m128i x = _mm_unpacklo_epi32( xh, xl );
4726 // merge in appropriate exponents to give the integer bits the
4728 x = _mm_unpacklo_epi32( x, exp );
4730 // subtract away the biases to deal with the IEEE-754 double precision
4732 d = _mm_sub_pd( (__m128d) x, bias );
4734 // All conversions up to here are exact. The correctly rounded result is
4735 // calculated using the
4736 // current rounding mode using the following horizontal add.
4737 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4738 _mm_store_sd( &sd, d ); //since we are returning doubles in XMM, this
4739 // store doesn't really need to be here (except maybe to zero the other
4745 // Build some magic constants.
4746 std::vector<Constant*>CV0;
4747 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
4748 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
4749 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4750 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4751 Constant *C0 = ConstantVector::get(CV0);
4752 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4);
4754 std::vector<Constant*>CV1;
4755 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
4756 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
4757 Constant *C1 = ConstantVector::get(CV1);
4758 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4);
4760 SmallVector<SDValue, 4> MaskVec;
4761 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
4762 MaskVec.push_back(DAG.getConstant(4, MVT::i32));
4763 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
4764 MaskVec.push_back(DAG.getConstant(5, MVT::i32));
4765 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0],
4767 SmallVector<SDValue, 4> MaskVec2;
4768 MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
4769 MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
4770 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0],
4773 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4774 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4776 DAG.getIntPtrConstant(1)));
4777 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4778 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4780 DAG.getIntPtrConstant(0)));
4781 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4782 XR1, XR2, UnpcklMask);
4783 SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0,
4784 PseudoSourceValue::getConstantPool(), 0, false, 16);
4785 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4786 Unpck1, CLod0, UnpcklMask);
4787 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2);
4788 SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1,
4789 PseudoSourceValue::getConstantPool(), 0, false, 16);
4790 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1);
4791 // Add the halves; easiest way is to swap them into another reg first.
4792 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64,
4793 Sub, Sub, ShufMask);
4794 SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub);
4795 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add,
4796 DAG.getIntPtrConstant(0));
4799 std::pair<SDValue,SDValue> X86TargetLowering::
4800 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4801 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4802 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4803 "Unknown FP_TO_SINT to lower!");
4805 // These are really Legal.
4806 if (Op.getValueType() == MVT::i32 &&
4807 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4808 return std::make_pair(SDValue(), SDValue());
4809 if (Subtarget->is64Bit() &&
4810 Op.getValueType() == MVT::i64 &&
4811 Op.getOperand(0).getValueType() != MVT::f80)
4812 return std::make_pair(SDValue(), SDValue());
4814 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4816 MachineFunction &MF = DAG.getMachineFunction();
4817 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4818 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4819 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4821 switch (Op.getValueType().getSimpleVT()) {
4822 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4823 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4824 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4825 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4828 SDValue Chain = DAG.getEntryNode();
4829 SDValue Value = Op.getOperand(0);
4830 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4831 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4832 Chain = DAG.getStore(Chain, Value, StackSlot,
4833 PseudoSourceValue::getFixedStack(SSFI), 0);
4834 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4836 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4838 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4839 Chain = Value.getValue(1);
4840 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4841 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4844 // Build the FP_TO_INT*_IN_MEM
4845 SDValue Ops[] = { Chain, Value, StackSlot };
4846 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4848 return std::make_pair(FIST, StackSlot);
4851 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4852 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4853 SDValue FIST = Vals.first, StackSlot = Vals.second;
4854 if (FIST.getNode() == 0) return SDValue();
4857 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4860 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4861 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
4862 SDValue FIST = Vals.first, StackSlot = Vals.second;
4863 if (FIST.getNode() == 0) return 0;
4865 MVT VT = N->getValueType(0);
4867 // Return a load from the stack slot.
4868 SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
4870 // Use MERGE_VALUES to drop the chain result value and get a node with one
4871 // result. This requires turning off getMergeValues simplification, since
4872 // otherwise it will give us Res back.
4873 return DAG.getMergeValues(&Res, 1, false).getNode();
4876 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4877 MVT VT = Op.getValueType();
4880 EltVT = VT.getVectorElementType();
4881 std::vector<Constant*> CV;
4882 if (EltVT == MVT::f64) {
4883 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4887 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4893 Constant *C = ConstantVector::get(CV);
4894 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4895 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4896 PseudoSourceValue::getConstantPool(), 0,
4898 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4901 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
4902 MVT VT = Op.getValueType();
4904 unsigned EltNum = 1;
4905 if (VT.isVector()) {
4906 EltVT = VT.getVectorElementType();
4907 EltNum = VT.getVectorNumElements();
4909 std::vector<Constant*> CV;
4910 if (EltVT == MVT::f64) {
4911 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4915 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4921 Constant *C = ConstantVector::get(CV);
4922 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4923 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4924 PseudoSourceValue::getConstantPool(), 0,
4926 if (VT.isVector()) {
4927 return DAG.getNode(ISD::BIT_CONVERT, VT,
4928 DAG.getNode(ISD::XOR, MVT::v2i64,
4929 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4930 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4932 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4936 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
4937 SDValue Op0 = Op.getOperand(0);
4938 SDValue Op1 = Op.getOperand(1);
4939 MVT VT = Op.getValueType();
4940 MVT SrcVT = Op1.getValueType();
4942 // If second operand is smaller, extend it first.
4943 if (SrcVT.bitsLT(VT)) {
4944 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4947 // And if it is bigger, shrink it first.
4948 if (SrcVT.bitsGT(VT)) {
4949 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4953 // At this point the operands and the result should have the same
4954 // type, and that won't be f80 since that is not custom lowered.
4956 // First get the sign bit of second operand.
4957 std::vector<Constant*> CV;
4958 if (SrcVT == MVT::f64) {
4959 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4960 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4962 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4963 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4964 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4965 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4967 Constant *C = ConstantVector::get(CV);
4968 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4969 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4970 PseudoSourceValue::getConstantPool(), 0,
4972 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4974 // Shift sign bit right or left if the two operands have different types.
4975 if (SrcVT.bitsGT(VT)) {
4976 // Op0 is MVT::f32, Op1 is MVT::f64.
4977 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4978 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4979 DAG.getConstant(32, MVT::i32));
4980 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4981 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4982 DAG.getIntPtrConstant(0));
4985 // Clear first operand sign bit.
4987 if (VT == MVT::f64) {
4988 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4989 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4991 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4992 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4993 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4994 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4996 C = ConstantVector::get(CV);
4997 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4998 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4999 PseudoSourceValue::getConstantPool(), 0,
5001 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
5003 // Or the value with the sign bit.
5004 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
5007 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5008 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5010 SDValue Op0 = Op.getOperand(0);
5011 SDValue Op1 = Op.getOperand(1);
5012 SDValue CC = Op.getOperand(2);
5013 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5016 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
5018 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
5019 return DAG.getNode(X86ISD::SETCC, MVT::i8,
5020 DAG.getConstant(X86CC, MVT::i8), Cond);
5023 assert(0 && "Illegal SetCC!");
5027 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5029 SDValue Op0 = Op.getOperand(0);
5030 SDValue Op1 = Op.getOperand(1);
5031 SDValue CC = Op.getOperand(2);
5032 MVT VT = Op.getValueType();
5033 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5034 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5038 MVT VT0 = Op0.getValueType();
5039 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5040 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5043 switch (SetCCOpcode) {
5046 case ISD::SETEQ: SSECC = 0; break;
5048 case ISD::SETGT: Swap = true; // Fallthrough
5050 case ISD::SETOLT: SSECC = 1; break;
5052 case ISD::SETGE: Swap = true; // Fallthrough
5054 case ISD::SETOLE: SSECC = 2; break;
5055 case ISD::SETUO: SSECC = 3; break;
5057 case ISD::SETNE: SSECC = 4; break;
5058 case ISD::SETULE: Swap = true;
5059 case ISD::SETUGE: SSECC = 5; break;
5060 case ISD::SETULT: Swap = true;
5061 case ISD::SETUGT: SSECC = 6; break;
5062 case ISD::SETO: SSECC = 7; break;
5065 std::swap(Op0, Op1);
5067 // In the two special cases we can't handle, emit two comparisons.
5069 if (SetCCOpcode == ISD::SETUEQ) {
5071 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5072 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5073 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
5075 else if (SetCCOpcode == ISD::SETONE) {
5077 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5078 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5079 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
5081 assert(0 && "Illegal FP comparison");
5083 // Handle all other FP comparisons here.
5084 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5087 // We are handling one of the integer comparisons here. Since SSE only has
5088 // GT and EQ comparisons for integer, swapping operands and multiple
5089 // operations may be required for some comparisons.
5090 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5091 bool Swap = false, Invert = false, FlipSigns = false;
5093 switch (VT.getSimpleVT()) {
5095 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5096 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5097 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5098 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5101 switch (SetCCOpcode) {
5103 case ISD::SETNE: Invert = true;
5104 case ISD::SETEQ: Opc = EQOpc; break;
5105 case ISD::SETLT: Swap = true;
5106 case ISD::SETGT: Opc = GTOpc; break;
5107 case ISD::SETGE: Swap = true;
5108 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5109 case ISD::SETULT: Swap = true;
5110 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5111 case ISD::SETUGE: Swap = true;
5112 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5115 std::swap(Op0, Op1);
5117 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5118 // bits of the inputs before performing those operations.
5120 MVT EltVT = VT.getVectorElementType();
5121 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
5122 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5123 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
5125 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
5126 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
5129 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
5131 // If the logical-not of the result is required, perform that now.
5133 MVT EltVT = VT.getVectorElementType();
5134 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
5135 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
5136 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
5138 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
5143 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5144 bool addTest = true;
5145 SDValue Cond = Op.getOperand(0);
5148 if (Cond.getOpcode() == ISD::SETCC)
5149 Cond = LowerSETCC(Cond, DAG);
5151 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5152 // setting operand in place of the X86ISD::SETCC.
5153 if (Cond.getOpcode() == X86ISD::SETCC) {
5154 CC = Cond.getOperand(0);
5156 SDValue Cmp = Cond.getOperand(1);
5157 unsigned Opc = Cmp.getOpcode();
5158 MVT VT = Op.getValueType();
5160 bool IllegalFPCMov = false;
5161 if (VT.isFloatingPoint() && !VT.isVector() &&
5162 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5163 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5165 if ((Opc == X86ISD::CMP ||
5166 Opc == X86ISD::COMI ||
5167 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
5174 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5175 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5178 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5180 SmallVector<SDValue, 4> Ops;
5181 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5182 // condition is true.
5183 Ops.push_back(Op.getOperand(2));
5184 Ops.push_back(Op.getOperand(1));
5186 Ops.push_back(Cond);
5187 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
5190 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5191 bool addTest = true;
5192 SDValue Chain = Op.getOperand(0);
5193 SDValue Cond = Op.getOperand(1);
5194 SDValue Dest = Op.getOperand(2);
5197 if (Cond.getOpcode() == ISD::SETCC)
5198 Cond = LowerSETCC(Cond, DAG);
5200 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5201 // setting operand in place of the X86ISD::SETCC.
5202 if (Cond.getOpcode() == X86ISD::SETCC) {
5203 CC = Cond.getOperand(0);
5205 SDValue Cmp = Cond.getOperand(1);
5206 unsigned Opc = Cmp.getOpcode();
5207 if (Opc == X86ISD::CMP ||
5208 Opc == X86ISD::COMI ||
5209 Opc == X86ISD::UCOMI) {
5213 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5214 // two branches instead of an explicit OR instruction with a
5216 } else if (Cond.getOpcode() == ISD::OR &&
5218 Cond.getOperand(0).getOpcode() == X86ISD::SETCC &&
5219 Cond.getOperand(0).hasOneUse() &&
5220 Cond.getOperand(1).getOpcode() == X86ISD::SETCC &&
5221 Cond.getOperand(1).hasOneUse()) {
5222 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5223 unsigned Opc = Cmp.getOpcode();
5224 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5225 (Opc == X86ISD::CMP ||
5226 Opc == X86ISD::COMI ||
5227 Opc == X86ISD::UCOMI)) {
5228 CC = Cond.getOperand(0).getOperand(0);
5229 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5230 Chain, Dest, CC, Cmp);
5231 CC = Cond.getOperand(1).getOperand(0);
5235 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5236 // two branches instead of an explicit AND instruction with a
5237 // separate test. However, we only do this if this block doesn't
5238 // have a fall-through edge, because this requires an explicit
5239 // jmp when the condition is false.
5240 } else if (Cond.getOpcode() == ISD::AND &&
5242 Cond.getOperand(0).getOpcode() == X86ISD::SETCC &&
5243 Cond.getOperand(0).hasOneUse() &&
5244 Cond.getOperand(1).getOpcode() == X86ISD::SETCC &&
5245 Cond.getOperand(1).hasOneUse()) {
5246 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5247 unsigned Opc = Cmp.getOpcode();
5248 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5249 (Opc == X86ISD::CMP ||
5250 Opc == X86ISD::COMI ||
5251 Opc == X86ISD::UCOMI) &&
5252 Op.getNode()->hasOneUse()) {
5253 X86::CondCode CCode =
5254 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5255 CCode = X86::GetOppositeBranchCondition(CCode);
5256 CC = DAG.getConstant(CCode, MVT::i8);
5257 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5258 // Look for an unconditional branch following this conditional branch.
5259 // We need this because we need to reverse the successors in order
5260 // to implement FCMP_OEQ.
5261 if (User.getOpcode() == ISD::BR) {
5262 SDValue FalseBB = User.getOperand(1);
5264 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5265 assert(NewBR == User);
5268 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5269 Chain, Dest, CC, Cmp);
5270 X86::CondCode CCode =
5271 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5272 CCode = X86::GetOppositeBranchCondition(CCode);
5273 CC = DAG.getConstant(CCode, MVT::i8);
5281 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5282 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5284 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5285 Chain, Dest, CC, Cond);
5289 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5290 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5291 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5292 // that the guard pages used by the OS virtual memory manager are allocated in
5293 // correct sequence.
5295 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5296 SelectionDAG &DAG) {
5297 assert(Subtarget->isTargetCygMing() &&
5298 "This should be used only on Cygwin/Mingw targets");
5301 SDValue Chain = Op.getOperand(0);
5302 SDValue Size = Op.getOperand(1);
5303 // FIXME: Ensure alignment here
5307 MVT IntPtr = getPointerTy();
5308 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5310 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5312 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5313 Flag = Chain.getValue(1);
5315 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5316 SDValue Ops[] = { Chain,
5317 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5318 DAG.getRegister(X86::EAX, IntPtr),
5319 DAG.getRegister(X86StackPtr, SPTy),
5321 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5322 Flag = Chain.getValue(1);
5324 Chain = DAG.getCALLSEQ_END(Chain,
5325 DAG.getIntPtrConstant(0, true),
5326 DAG.getIntPtrConstant(0, true),
5329 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5331 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5332 return DAG.getMergeValues(Ops1, 2);
5336 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5338 SDValue Dst, SDValue Src,
5339 SDValue Size, unsigned Align,
5341 uint64_t DstSVOff) {
5342 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5344 // If not DWORD aligned or size is more than the threshold, call the library.
5345 // The libc version is likely to be faster for these cases. It can use the
5346 // address value and run time information about the CPU.
5347 if ((Align & 3) != 0 ||
5349 ConstantSize->getZExtValue() >
5350 getSubtarget()->getMaxInlineSizeThreshold()) {
5351 SDValue InFlag(0, 0);
5353 // Check to see if there is a specialized entry-point for memory zeroing.
5354 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5356 if (const char *bzeroEntry = V &&
5357 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5358 MVT IntPtr = getPointerTy();
5359 const Type *IntPtrTy = TD->getIntPtrType();
5360 TargetLowering::ArgListTy Args;
5361 TargetLowering::ArgListEntry Entry;
5363 Entry.Ty = IntPtrTy;
5364 Args.push_back(Entry);
5366 Args.push_back(Entry);
5367 std::pair<SDValue,SDValue> CallResult =
5368 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5369 CallingConv::C, false,
5370 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG);
5371 return CallResult.second;
5374 // Otherwise have the target-independent code call memset.
5378 uint64_t SizeVal = ConstantSize->getZExtValue();
5379 SDValue InFlag(0, 0);
5382 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5383 unsigned BytesLeft = 0;
5384 bool TwoRepStos = false;
5387 uint64_t Val = ValC->getZExtValue() & 255;
5389 // If the value is a constant, then we can potentially use larger sets.
5390 switch (Align & 3) {
5391 case 2: // WORD aligned
5394 Val = (Val << 8) | Val;
5396 case 0: // DWORD aligned
5399 Val = (Val << 8) | Val;
5400 Val = (Val << 16) | Val;
5401 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5404 Val = (Val << 32) | Val;
5407 default: // Byte aligned
5410 Count = DAG.getIntPtrConstant(SizeVal);
5414 if (AVT.bitsGT(MVT::i8)) {
5415 unsigned UBytes = AVT.getSizeInBits() / 8;
5416 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5417 BytesLeft = SizeVal % UBytes;
5420 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5422 InFlag = Chain.getValue(1);
5425 Count = DAG.getIntPtrConstant(SizeVal);
5426 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5427 InFlag = Chain.getValue(1);
5430 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5432 InFlag = Chain.getValue(1);
5433 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5435 InFlag = Chain.getValue(1);
5437 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5438 SmallVector<SDValue, 8> Ops;
5439 Ops.push_back(Chain);
5440 Ops.push_back(DAG.getValueType(AVT));
5441 Ops.push_back(InFlag);
5442 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5445 InFlag = Chain.getValue(1);
5447 MVT CVT = Count.getValueType();
5448 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5449 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5450 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5452 InFlag = Chain.getValue(1);
5453 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5455 Ops.push_back(Chain);
5456 Ops.push_back(DAG.getValueType(MVT::i8));
5457 Ops.push_back(InFlag);
5458 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5459 } else if (BytesLeft) {
5460 // Handle the last 1 - 7 bytes.
5461 unsigned Offset = SizeVal - BytesLeft;
5462 MVT AddrVT = Dst.getValueType();
5463 MVT SizeVT = Size.getValueType();
5465 Chain = DAG.getMemset(Chain,
5466 DAG.getNode(ISD::ADD, AddrVT, Dst,
5467 DAG.getConstant(Offset, AddrVT)),
5469 DAG.getConstant(BytesLeft, SizeVT),
5470 Align, DstSV, DstSVOff + Offset);
5473 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5478 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5479 SDValue Chain, SDValue Dst, SDValue Src,
5480 SDValue Size, unsigned Align,
5482 const Value *DstSV, uint64_t DstSVOff,
5483 const Value *SrcSV, uint64_t SrcSVOff) {
5484 // This requires the copy size to be a constant, preferrably
5485 // within a subtarget-specific limit.
5486 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5489 uint64_t SizeVal = ConstantSize->getZExtValue();
5490 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5493 /// If not DWORD aligned, call the library.
5494 if ((Align & 3) != 0)
5499 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5502 unsigned UBytes = AVT.getSizeInBits() / 8;
5503 unsigned CountVal = SizeVal / UBytes;
5504 SDValue Count = DAG.getIntPtrConstant(CountVal);
5505 unsigned BytesLeft = SizeVal % UBytes;
5507 SDValue InFlag(0, 0);
5508 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5510 InFlag = Chain.getValue(1);
5511 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5513 InFlag = Chain.getValue(1);
5514 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5516 InFlag = Chain.getValue(1);
5518 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5519 SmallVector<SDValue, 8> Ops;
5520 Ops.push_back(Chain);
5521 Ops.push_back(DAG.getValueType(AVT));
5522 Ops.push_back(InFlag);
5523 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5525 SmallVector<SDValue, 4> Results;
5526 Results.push_back(RepMovs);
5528 // Handle the last 1 - 7 bytes.
5529 unsigned Offset = SizeVal - BytesLeft;
5530 MVT DstVT = Dst.getValueType();
5531 MVT SrcVT = Src.getValueType();
5532 MVT SizeVT = Size.getValueType();
5533 Results.push_back(DAG.getMemcpy(Chain,
5534 DAG.getNode(ISD::ADD, DstVT, Dst,
5535 DAG.getConstant(Offset, DstVT)),
5536 DAG.getNode(ISD::ADD, SrcVT, Src,
5537 DAG.getConstant(Offset, SrcVT)),
5538 DAG.getConstant(BytesLeft, SizeVT),
5539 Align, AlwaysInline,
5540 DstSV, DstSVOff + Offset,
5541 SrcSV, SrcSVOff + Offset));
5544 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5547 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
5548 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
5549 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5550 SDValue TheChain = N->getOperand(0);
5551 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
5552 if (Subtarget->is64Bit()) {
5553 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
5554 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
5555 MVT::i64, rax.getValue(2));
5556 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
5557 DAG.getConstant(32, MVT::i8));
5559 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
5562 return DAG.getMergeValues(Ops, 2).getNode();
5565 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
5566 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
5567 MVT::i32, eax.getValue(2));
5568 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
5569 SDValue Ops[] = { eax, edx };
5570 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
5572 // Use a MERGE_VALUES to return the value and chain.
5573 Ops[1] = edx.getValue(1);
5574 return DAG.getMergeValues(Ops, 2).getNode();
5577 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5578 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5580 if (!Subtarget->is64Bit()) {
5581 // vastart just stores the address of the VarArgsFrameIndex slot into the
5582 // memory location argument.
5583 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5584 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5588 // gp_offset (0 - 6 * 8)
5589 // fp_offset (48 - 48 + 8 * 16)
5590 // overflow_arg_area (point to parameters coming in memory).
5592 SmallVector<SDValue, 8> MemOps;
5593 SDValue FIN = Op.getOperand(1);
5595 SDValue Store = DAG.getStore(Op.getOperand(0),
5596 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5598 MemOps.push_back(Store);
5601 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5602 Store = DAG.getStore(Op.getOperand(0),
5603 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5605 MemOps.push_back(Store);
5607 // Store ptr to overflow_arg_area
5608 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5609 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5610 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5611 MemOps.push_back(Store);
5613 // Store ptr to reg_save_area.
5614 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5615 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5616 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5617 MemOps.push_back(Store);
5618 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5621 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5622 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5623 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5624 SDValue Chain = Op.getOperand(0);
5625 SDValue SrcPtr = Op.getOperand(1);
5626 SDValue SrcSV = Op.getOperand(2);
5628 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5633 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5634 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5635 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5636 SDValue Chain = Op.getOperand(0);
5637 SDValue DstPtr = Op.getOperand(1);
5638 SDValue SrcPtr = Op.getOperand(2);
5639 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5640 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5642 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5643 DAG.getIntPtrConstant(24), 8, false,
5644 DstSV, 0, SrcSV, 0);
5648 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5649 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5651 default: return SDValue(); // Don't custom lower most intrinsics.
5652 // Comparison intrinsics.
5653 case Intrinsic::x86_sse_comieq_ss:
5654 case Intrinsic::x86_sse_comilt_ss:
5655 case Intrinsic::x86_sse_comile_ss:
5656 case Intrinsic::x86_sse_comigt_ss:
5657 case Intrinsic::x86_sse_comige_ss:
5658 case Intrinsic::x86_sse_comineq_ss:
5659 case Intrinsic::x86_sse_ucomieq_ss:
5660 case Intrinsic::x86_sse_ucomilt_ss:
5661 case Intrinsic::x86_sse_ucomile_ss:
5662 case Intrinsic::x86_sse_ucomigt_ss:
5663 case Intrinsic::x86_sse_ucomige_ss:
5664 case Intrinsic::x86_sse_ucomineq_ss:
5665 case Intrinsic::x86_sse2_comieq_sd:
5666 case Intrinsic::x86_sse2_comilt_sd:
5667 case Intrinsic::x86_sse2_comile_sd:
5668 case Intrinsic::x86_sse2_comigt_sd:
5669 case Intrinsic::x86_sse2_comige_sd:
5670 case Intrinsic::x86_sse2_comineq_sd:
5671 case Intrinsic::x86_sse2_ucomieq_sd:
5672 case Intrinsic::x86_sse2_ucomilt_sd:
5673 case Intrinsic::x86_sse2_ucomile_sd:
5674 case Intrinsic::x86_sse2_ucomigt_sd:
5675 case Intrinsic::x86_sse2_ucomige_sd:
5676 case Intrinsic::x86_sse2_ucomineq_sd: {
5678 ISD::CondCode CC = ISD::SETCC_INVALID;
5681 case Intrinsic::x86_sse_comieq_ss:
5682 case Intrinsic::x86_sse2_comieq_sd:
5686 case Intrinsic::x86_sse_comilt_ss:
5687 case Intrinsic::x86_sse2_comilt_sd:
5691 case Intrinsic::x86_sse_comile_ss:
5692 case Intrinsic::x86_sse2_comile_sd:
5696 case Intrinsic::x86_sse_comigt_ss:
5697 case Intrinsic::x86_sse2_comigt_sd:
5701 case Intrinsic::x86_sse_comige_ss:
5702 case Intrinsic::x86_sse2_comige_sd:
5706 case Intrinsic::x86_sse_comineq_ss:
5707 case Intrinsic::x86_sse2_comineq_sd:
5711 case Intrinsic::x86_sse_ucomieq_ss:
5712 case Intrinsic::x86_sse2_ucomieq_sd:
5713 Opc = X86ISD::UCOMI;
5716 case Intrinsic::x86_sse_ucomilt_ss:
5717 case Intrinsic::x86_sse2_ucomilt_sd:
5718 Opc = X86ISD::UCOMI;
5721 case Intrinsic::x86_sse_ucomile_ss:
5722 case Intrinsic::x86_sse2_ucomile_sd:
5723 Opc = X86ISD::UCOMI;
5726 case Intrinsic::x86_sse_ucomigt_ss:
5727 case Intrinsic::x86_sse2_ucomigt_sd:
5728 Opc = X86ISD::UCOMI;
5731 case Intrinsic::x86_sse_ucomige_ss:
5732 case Intrinsic::x86_sse2_ucomige_sd:
5733 Opc = X86ISD::UCOMI;
5736 case Intrinsic::x86_sse_ucomineq_ss:
5737 case Intrinsic::x86_sse2_ucomineq_sd:
5738 Opc = X86ISD::UCOMI;
5744 SDValue LHS = Op.getOperand(1);
5745 SDValue RHS = Op.getOperand(2);
5746 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5748 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5749 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5750 DAG.getConstant(X86CC, MVT::i8), Cond);
5751 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5754 // Fix vector shift instructions where the last operand is a non-immediate
5756 case Intrinsic::x86_sse2_pslli_w:
5757 case Intrinsic::x86_sse2_pslli_d:
5758 case Intrinsic::x86_sse2_pslli_q:
5759 case Intrinsic::x86_sse2_psrli_w:
5760 case Intrinsic::x86_sse2_psrli_d:
5761 case Intrinsic::x86_sse2_psrli_q:
5762 case Intrinsic::x86_sse2_psrai_w:
5763 case Intrinsic::x86_sse2_psrai_d:
5764 case Intrinsic::x86_mmx_pslli_w:
5765 case Intrinsic::x86_mmx_pslli_d:
5766 case Intrinsic::x86_mmx_pslli_q:
5767 case Intrinsic::x86_mmx_psrli_w:
5768 case Intrinsic::x86_mmx_psrli_d:
5769 case Intrinsic::x86_mmx_psrli_q:
5770 case Intrinsic::x86_mmx_psrai_w:
5771 case Intrinsic::x86_mmx_psrai_d: {
5772 SDValue ShAmt = Op.getOperand(2);
5773 if (isa<ConstantSDNode>(ShAmt))
5776 unsigned NewIntNo = 0;
5777 MVT ShAmtVT = MVT::v4i32;
5779 case Intrinsic::x86_sse2_pslli_w:
5780 NewIntNo = Intrinsic::x86_sse2_psll_w;
5782 case Intrinsic::x86_sse2_pslli_d:
5783 NewIntNo = Intrinsic::x86_sse2_psll_d;
5785 case Intrinsic::x86_sse2_pslli_q:
5786 NewIntNo = Intrinsic::x86_sse2_psll_q;
5788 case Intrinsic::x86_sse2_psrli_w:
5789 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5791 case Intrinsic::x86_sse2_psrli_d:
5792 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5794 case Intrinsic::x86_sse2_psrli_q:
5795 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5797 case Intrinsic::x86_sse2_psrai_w:
5798 NewIntNo = Intrinsic::x86_sse2_psra_w;
5800 case Intrinsic::x86_sse2_psrai_d:
5801 NewIntNo = Intrinsic::x86_sse2_psra_d;
5804 ShAmtVT = MVT::v2i32;
5806 case Intrinsic::x86_mmx_pslli_w:
5807 NewIntNo = Intrinsic::x86_mmx_psll_w;
5809 case Intrinsic::x86_mmx_pslli_d:
5810 NewIntNo = Intrinsic::x86_mmx_psll_d;
5812 case Intrinsic::x86_mmx_pslli_q:
5813 NewIntNo = Intrinsic::x86_mmx_psll_q;
5815 case Intrinsic::x86_mmx_psrli_w:
5816 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5818 case Intrinsic::x86_mmx_psrli_d:
5819 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5821 case Intrinsic::x86_mmx_psrli_q:
5822 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5824 case Intrinsic::x86_mmx_psrai_w:
5825 NewIntNo = Intrinsic::x86_mmx_psra_w;
5827 case Intrinsic::x86_mmx_psrai_d:
5828 NewIntNo = Intrinsic::x86_mmx_psra_d;
5830 default: abort(); // Can't reach here.
5835 MVT VT = Op.getValueType();
5836 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5837 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5838 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5839 DAG.getConstant(NewIntNo, MVT::i32),
5840 Op.getOperand(1), ShAmt);
5845 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5846 // Depths > 0 not supported yet!
5847 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5850 // Just load the return address
5851 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5852 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5855 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5856 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5857 MFI->setFrameAddressIsTaken(true);
5858 MVT VT = Op.getValueType();
5859 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5860 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
5861 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT);
5863 FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0);
5867 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
5868 SelectionDAG &DAG) {
5869 return DAG.getIntPtrConstant(2*TD->getPointerSize());
5872 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
5874 MachineFunction &MF = DAG.getMachineFunction();
5875 SDValue Chain = Op.getOperand(0);
5876 SDValue Offset = Op.getOperand(1);
5877 SDValue Handler = Op.getOperand(2);
5879 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
5881 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
5883 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5884 DAG.getIntPtrConstant(-TD->getPointerSize()));
5885 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5886 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5887 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
5888 MF.getRegInfo().addLiveOut(StoreAddrReg);
5890 return DAG.getNode(X86ISD::EH_RETURN,
5892 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
5895 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
5896 SelectionDAG &DAG) {
5897 SDValue Root = Op.getOperand(0);
5898 SDValue Trmp = Op.getOperand(1); // trampoline
5899 SDValue FPtr = Op.getOperand(2); // nested function
5900 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
5902 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5904 const X86InstrInfo *TII =
5905 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5907 if (Subtarget->is64Bit()) {
5908 SDValue OutChains[6];
5910 // Large code-model.
5912 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5913 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5915 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5916 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5918 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5920 // Load the pointer to the nested function into R11.
5921 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5922 SDValue Addr = Trmp;
5923 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5926 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5927 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5929 // Load the 'nest' parameter value into R10.
5930 // R10 is specified in X86CallingConv.td
5931 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5932 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5933 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5936 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5937 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5939 // Jump to the nested function.
5940 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5941 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5942 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5945 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5946 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5947 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5951 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5952 return DAG.getMergeValues(Ops, 2);
5954 const Function *Func =
5955 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5956 unsigned CC = Func->getCallingConv();
5961 assert(0 && "Unsupported calling convention");
5962 case CallingConv::C:
5963 case CallingConv::X86_StdCall: {
5964 // Pass 'nest' parameter in ECX.
5965 // Must be kept in sync with X86CallingConv.td
5968 // Check that ECX wasn't needed by an 'inreg' parameter.
5969 const FunctionType *FTy = Func->getFunctionType();
5970 const AttrListPtr &Attrs = Func->getAttributes();
5972 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5973 unsigned InRegCount = 0;
5976 for (FunctionType::param_iterator I = FTy->param_begin(),
5977 E = FTy->param_end(); I != E; ++I, ++Idx)
5978 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
5979 // FIXME: should only count parameters that are lowered to integers.
5980 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
5982 if (InRegCount > 2) {
5983 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5989 case CallingConv::X86_FastCall:
5990 case CallingConv::Fast:
5991 // Pass 'nest' parameter in EAX.
5992 // Must be kept in sync with X86CallingConv.td
5997 SDValue OutChains[4];
6000 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
6001 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
6003 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6004 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6005 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6008 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
6009 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
6011 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6012 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
6013 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
6014 TrmpAddr, 5, false, 1);
6016 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
6017 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
6020 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
6021 return DAG.getMergeValues(Ops, 2);
6025 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6027 The rounding mode is in bits 11:10 of FPSR, and has the following
6034 FLT_ROUNDS, on the other hand, expects the following:
6041 To perform the conversion, we do:
6042 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6045 MachineFunction &MF = DAG.getMachineFunction();
6046 const TargetMachine &TM = MF.getTarget();
6047 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6048 unsigned StackAlignment = TFI.getStackAlignment();
6049 MVT VT = Op.getValueType();
6051 // Save FP Control Word to stack slot
6052 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6053 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6055 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
6056 DAG.getEntryNode(), StackSlot);
6058 // Load FP Control Word from stack slot
6059 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
6061 // Transform as necessary
6063 DAG.getNode(ISD::SRL, MVT::i16,
6064 DAG.getNode(ISD::AND, MVT::i16,
6065 CWD, DAG.getConstant(0x800, MVT::i16)),
6066 DAG.getConstant(11, MVT::i8));
6068 DAG.getNode(ISD::SRL, MVT::i16,
6069 DAG.getNode(ISD::AND, MVT::i16,
6070 CWD, DAG.getConstant(0x400, MVT::i16)),
6071 DAG.getConstant(9, MVT::i8));
6074 DAG.getNode(ISD::AND, MVT::i16,
6075 DAG.getNode(ISD::ADD, MVT::i16,
6076 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
6077 DAG.getConstant(1, MVT::i16)),
6078 DAG.getConstant(3, MVT::i16));
6081 return DAG.getNode((VT.getSizeInBits() < 16 ?
6082 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
6085 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6086 MVT VT = Op.getValueType();
6088 unsigned NumBits = VT.getSizeInBits();
6090 Op = Op.getOperand(0);
6091 if (VT == MVT::i8) {
6092 // Zero extend to i32 since there is not an i8 bsr.
6094 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6097 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6098 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6099 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
6101 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6102 SmallVector<SDValue, 4> Ops;
6104 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6105 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6106 Ops.push_back(Op.getValue(1));
6107 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6109 // Finally xor with NumBits-1.
6110 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6113 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6117 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6118 MVT VT = Op.getValueType();
6120 unsigned NumBits = VT.getSizeInBits();
6122 Op = Op.getOperand(0);
6123 if (VT == MVT::i8) {
6125 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6128 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6129 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6130 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
6132 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6133 SmallVector<SDValue, 4> Ops;
6135 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6136 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6137 Ops.push_back(Op.getValue(1));
6138 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6141 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6145 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6146 MVT T = Op.getValueType();
6149 switch(T.getSimpleVT()) {
6151 assert(false && "Invalid value type!");
6152 case MVT::i8: Reg = X86::AL; size = 1; break;
6153 case MVT::i16: Reg = X86::AX; size = 2; break;
6154 case MVT::i32: Reg = X86::EAX; size = 4; break;
6156 if (Subtarget->is64Bit()) {
6157 Reg = X86::RAX; size = 8;
6158 } else //Should go away when LegalizeType stuff lands
6159 return SDValue(ExpandATOMIC_CMP_SWAP(Op.getNode(), DAG), 0);
6162 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
6163 Op.getOperand(2), SDValue());
6164 SDValue Ops[] = { cpIn.getValue(0),
6167 DAG.getTargetConstant(size, MVT::i8),
6169 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6170 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
6172 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
6176 SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op,
6177 SelectionDAG &DAG) {
6178 MVT T = Op->getValueType(0);
6179 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6180 SDValue cpInL, cpInH;
6181 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
6182 DAG.getConstant(0, MVT::i32));
6183 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
6184 DAG.getConstant(1, MVT::i32));
6185 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
6187 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
6188 cpInH, cpInL.getValue(1));
6189 SDValue swapInL, swapInH;
6190 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
6191 DAG.getConstant(0, MVT::i32));
6192 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
6193 DAG.getConstant(1, MVT::i32));
6194 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
6195 swapInL, cpInH.getValue(1));
6196 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
6197 swapInH, swapInL.getValue(1));
6198 SDValue Ops[] = { swapInH.getValue(0),
6200 swapInH.getValue(1) };
6201 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6202 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
6203 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
6204 Result.getValue(1));
6205 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
6206 cpOutL.getValue(2));
6207 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6208 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
6209 SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
6210 return DAG.getMergeValues(Vals, 2).getNode();
6213 SDValue X86TargetLowering::LowerATOMIC_BINARY_64(SDValue Op,
6216 SDNode *Node = Op.getNode();
6217 MVT T = Node->getValueType(0);
6218 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6220 SDValue Chain = Node->getOperand(0);
6221 SDValue In1 = Node->getOperand(1);
6222 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6223 Node->getOperand(2), DAG.getIntPtrConstant(0));
6224 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6225 Node->getOperand(2), DAG.getIntPtrConstant(1));
6226 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6227 // have a MemOperand. Pass the info through as a normal operand.
6228 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6229 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6230 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6231 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
6232 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6233 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
6234 SDValue Vals[2] = { ResultVal, Result.getValue(2) };
6235 return SDValue(DAG.getMergeValues(Vals, 2).getNode(), 0);
6238 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6239 SDNode *Node = Op.getNode();
6240 MVT T = Node->getValueType(0);
6241 SDValue negOp = DAG.getNode(ISD::SUB, T,
6242 DAG.getConstant(0, T), Node->getOperand(2));
6243 return DAG.getAtomic((Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_8 ?
6244 ISD::ATOMIC_LOAD_ADD_8 :
6245 Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_16 ?
6246 ISD::ATOMIC_LOAD_ADD_16 :
6247 Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_32 ?
6248 ISD::ATOMIC_LOAD_ADD_32 :
6249 ISD::ATOMIC_LOAD_ADD_64),
6250 Node->getOperand(0),
6251 Node->getOperand(1), negOp,
6252 cast<AtomicSDNode>(Node)->getSrcValue(),
6253 cast<AtomicSDNode>(Node)->getAlignment());
6256 /// LowerOperation - Provide custom lowering hooks for some operations.
6258 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6259 switch (Op.getOpcode()) {
6260 default: assert(0 && "Should not custom lower this!");
6261 case ISD::ATOMIC_CMP_SWAP_8:
6262 case ISD::ATOMIC_CMP_SWAP_16:
6263 case ISD::ATOMIC_CMP_SWAP_32:
6264 case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
6265 case ISD::ATOMIC_LOAD_SUB_8:
6266 case ISD::ATOMIC_LOAD_SUB_16:
6267 case ISD::ATOMIC_LOAD_SUB_32: return LowerLOAD_SUB(Op,DAG);
6268 case ISD::ATOMIC_LOAD_SUB_64: return (Subtarget->is64Bit()) ?
6269 LowerLOAD_SUB(Op,DAG) :
6270 LowerATOMIC_BINARY_64(Op,DAG,
6271 X86ISD::ATOMSUB64_DAG);
6272 case ISD::ATOMIC_LOAD_AND_64: return LowerATOMIC_BINARY_64(Op,DAG,
6273 X86ISD::ATOMAND64_DAG);
6274 case ISD::ATOMIC_LOAD_OR_64: return LowerATOMIC_BINARY_64(Op, DAG,
6275 X86ISD::ATOMOR64_DAG);
6276 case ISD::ATOMIC_LOAD_XOR_64: return LowerATOMIC_BINARY_64(Op,DAG,
6277 X86ISD::ATOMXOR64_DAG);
6278 case ISD::ATOMIC_LOAD_NAND_64:return LowerATOMIC_BINARY_64(Op,DAG,
6279 X86ISD::ATOMNAND64_DAG);
6280 case ISD::ATOMIC_LOAD_ADD_64: return LowerATOMIC_BINARY_64(Op,DAG,
6281 X86ISD::ATOMADD64_DAG);
6282 case ISD::ATOMIC_SWAP_64: return LowerATOMIC_BINARY_64(Op,DAG,
6283 X86ISD::ATOMSWAP64_DAG);
6284 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6285 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6286 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6287 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6288 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6289 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6290 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6291 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6292 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6293 case ISD::SHL_PARTS:
6294 case ISD::SRA_PARTS:
6295 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6296 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6297 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6298 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6299 case ISD::FABS: return LowerFABS(Op, DAG);
6300 case ISD::FNEG: return LowerFNEG(Op, DAG);
6301 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6302 case ISD::SETCC: return LowerSETCC(Op, DAG);
6303 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6304 case ISD::SELECT: return LowerSELECT(Op, DAG);
6305 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6306 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6307 case ISD::CALL: return LowerCALL(Op, DAG);
6308 case ISD::RET: return LowerRET(Op, DAG);
6309 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6310 case ISD::VASTART: return LowerVASTART(Op, DAG);
6311 case ISD::VAARG: return LowerVAARG(Op, DAG);
6312 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6313 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6314 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6315 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6316 case ISD::FRAME_TO_ARGS_OFFSET:
6317 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6318 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6319 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6320 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6321 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6322 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6323 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6325 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
6326 case ISD::READCYCLECOUNTER:
6327 return SDValue(ExpandREADCYCLECOUNTER(Op.getNode(), DAG), 0);
6331 /// ReplaceNodeResults - Replace a node with an illegal result type
6332 /// with a new node built out of custom code.
6333 SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
6334 switch (N->getOpcode()) {
6336 return X86TargetLowering::LowerOperation(SDValue (N, 0), DAG).getNode();
6337 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
6338 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
6339 case ISD::ATOMIC_CMP_SWAP_64: return ExpandATOMIC_CMP_SWAP(N, DAG);
6343 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6345 default: return NULL;
6346 case X86ISD::BSF: return "X86ISD::BSF";
6347 case X86ISD::BSR: return "X86ISD::BSR";
6348 case X86ISD::SHLD: return "X86ISD::SHLD";
6349 case X86ISD::SHRD: return "X86ISD::SHRD";
6350 case X86ISD::FAND: return "X86ISD::FAND";
6351 case X86ISD::FOR: return "X86ISD::FOR";
6352 case X86ISD::FXOR: return "X86ISD::FXOR";
6353 case X86ISD::FSRL: return "X86ISD::FSRL";
6354 case X86ISD::FILD: return "X86ISD::FILD";
6355 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6356 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6357 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6358 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6359 case X86ISD::FLD: return "X86ISD::FLD";
6360 case X86ISD::FST: return "X86ISD::FST";
6361 case X86ISD::CALL: return "X86ISD::CALL";
6362 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6363 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6364 case X86ISD::CMP: return "X86ISD::CMP";
6365 case X86ISD::COMI: return "X86ISD::COMI";
6366 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6367 case X86ISD::SETCC: return "X86ISD::SETCC";
6368 case X86ISD::CMOV: return "X86ISD::CMOV";
6369 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6370 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6371 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6372 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6373 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6374 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6375 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6376 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6377 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6378 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6379 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6380 case X86ISD::FMAX: return "X86ISD::FMAX";
6381 case X86ISD::FMIN: return "X86ISD::FMIN";
6382 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6383 case X86ISD::FRCP: return "X86ISD::FRCP";
6384 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6385 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6386 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6387 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6388 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6389 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6390 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6391 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6392 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6393 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6394 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6395 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6396 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
6397 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6398 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6399 case X86ISD::VSHL: return "X86ISD::VSHL";
6400 case X86ISD::VSRL: return "X86ISD::VSRL";
6401 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6402 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6403 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6404 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6405 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6406 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6407 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6408 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6409 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6410 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6414 // isLegalAddressingMode - Return true if the addressing mode represented
6415 // by AM is legal for this target, for a load/store of the specified type.
6416 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6417 const Type *Ty) const {
6418 // X86 supports extremely general addressing modes.
6420 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6421 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6425 // We can only fold this if we don't need an extra load.
6426 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6429 // X86-64 only supports addr of globals in small code model.
6430 if (Subtarget->is64Bit()) {
6431 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6433 // If lower 4G is not available, then we must use rip-relative addressing.
6434 if (AM.BaseOffs || AM.Scale > 1)
6445 // These scales always work.
6450 // These scales are formed with basereg+scalereg. Only accept if there is
6455 default: // Other stuff never works.
6463 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6464 if (!Ty1->isInteger() || !Ty2->isInteger())
6466 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6467 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6468 if (NumBits1 <= NumBits2)
6470 return Subtarget->is64Bit() || NumBits1 < 64;
6473 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6474 if (!VT1.isInteger() || !VT2.isInteger())
6476 unsigned NumBits1 = VT1.getSizeInBits();
6477 unsigned NumBits2 = VT2.getSizeInBits();
6478 if (NumBits1 <= NumBits2)
6480 return Subtarget->is64Bit() || NumBits1 < 64;
6483 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6484 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6485 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6486 /// are assumed to be legal.
6488 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6489 // Only do shuffles on 128-bit vector types for now.
6490 if (VT.getSizeInBits() == 64) return false;
6491 return (Mask.getNode()->getNumOperands() <= 4 ||
6492 isIdentityMask(Mask.getNode()) ||
6493 isIdentityMask(Mask.getNode(), true) ||
6494 isSplatMask(Mask.getNode()) ||
6495 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6496 X86::isUNPCKLMask(Mask.getNode()) ||
6497 X86::isUNPCKHMask(Mask.getNode()) ||
6498 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6499 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6503 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6504 MVT EVT, SelectionDAG &DAG) const {
6505 unsigned NumElts = BVOps.size();
6506 // Only do shuffles on 128-bit vector types for now.
6507 if (EVT.getSizeInBits() * NumElts == 64) return false;
6508 if (NumElts == 2) return true;
6510 return (isMOVLMask(&BVOps[0], 4) ||
6511 isCommutedMOVL(&BVOps[0], 4, true) ||
6512 isSHUFPMask(&BVOps[0], 4) ||
6513 isCommutedSHUFP(&BVOps[0], 4));
6518 //===----------------------------------------------------------------------===//
6519 // X86 Scheduler Hooks
6520 //===----------------------------------------------------------------------===//
6522 // private utility function
6524 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6525 MachineBasicBlock *MBB,
6533 TargetRegisterClass *RC,
6535 // For the atomic bitwise operator, we generate
6538 // ld t1 = [bitinstr.addr]
6539 // op t2 = t1, [bitinstr.val]
6541 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6543 // fallthrough -->nextMBB
6544 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6545 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6546 MachineFunction::iterator MBBIter = MBB;
6549 /// First build the CFG
6550 MachineFunction *F = MBB->getParent();
6551 MachineBasicBlock *thisMBB = MBB;
6552 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6553 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6554 F->insert(MBBIter, newMBB);
6555 F->insert(MBBIter, nextMBB);
6557 // Move all successors to thisMBB to nextMBB
6558 nextMBB->transferSuccessors(thisMBB);
6560 // Update thisMBB to fall through to newMBB
6561 thisMBB->addSuccessor(newMBB);
6563 // newMBB jumps to itself and fall through to nextMBB
6564 newMBB->addSuccessor(nextMBB);
6565 newMBB->addSuccessor(newMBB);
6567 // Insert instructions into newMBB based on incoming instruction
6568 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6569 MachineOperand& destOper = bInstr->getOperand(0);
6570 MachineOperand* argOpers[6];
6571 int numArgs = bInstr->getNumOperands() - 1;
6572 for (int i=0; i < numArgs; ++i)
6573 argOpers[i] = &bInstr->getOperand(i+1);
6575 // x86 address has 4 operands: base, index, scale, and displacement
6576 int lastAddrIndx = 3; // [0,3]
6579 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6580 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6581 for (int i=0; i <= lastAddrIndx; ++i)
6582 (*MIB).addOperand(*argOpers[i]);
6584 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6586 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6591 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6592 assert((argOpers[valArgIndx]->isReg() ||
6593 argOpers[valArgIndx]->isImm()) &&
6595 if (argOpers[valArgIndx]->isReg())
6596 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6598 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6600 (*MIB).addOperand(*argOpers[valArgIndx]);
6602 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6605 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6606 for (int i=0; i <= lastAddrIndx; ++i)
6607 (*MIB).addOperand(*argOpers[i]);
6609 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6610 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6612 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6616 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6618 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6622 // private utility function: 64 bit atomics on 32 bit host.
6624 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
6625 MachineBasicBlock *MBB,
6631 // For the atomic bitwise operator, we generate
6632 // thisMBB (instructions are in pairs, except cmpxchg8b)
6633 // ld t1,t2 = [bitinstr.addr]
6635 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
6636 // op t5, t6 <- out1, out2, [bitinstr.val]
6637 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
6638 // mov ECX, EBX <- t5, t6
6639 // mov EAX, EDX <- t1, t2
6640 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
6641 // mov t3, t4 <- EAX, EDX
6643 // result in out1, out2
6644 // fallthrough -->nextMBB
6646 const TargetRegisterClass *RC = X86::GR32RegisterClass;
6647 const unsigned LoadOpc = X86::MOV32rm;
6648 const unsigned copyOpc = X86::MOV32rr;
6649 const unsigned NotOpc = X86::NOT32r;
6650 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6651 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6652 MachineFunction::iterator MBBIter = MBB;
6655 /// First build the CFG
6656 MachineFunction *F = MBB->getParent();
6657 MachineBasicBlock *thisMBB = MBB;
6658 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6659 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6660 F->insert(MBBIter, newMBB);
6661 F->insert(MBBIter, nextMBB);
6663 // Move all successors to thisMBB to nextMBB
6664 nextMBB->transferSuccessors(thisMBB);
6666 // Update thisMBB to fall through to newMBB
6667 thisMBB->addSuccessor(newMBB);
6669 // newMBB jumps to itself and fall through to nextMBB
6670 newMBB->addSuccessor(nextMBB);
6671 newMBB->addSuccessor(newMBB);
6673 // Insert instructions into newMBB based on incoming instruction
6674 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
6675 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
6676 MachineOperand& dest1Oper = bInstr->getOperand(0);
6677 MachineOperand& dest2Oper = bInstr->getOperand(1);
6678 MachineOperand* argOpers[6];
6679 for (int i=0; i < 6; ++i)
6680 argOpers[i] = &bInstr->getOperand(i+2);
6682 // x86 address has 4 operands: base, index, scale, and displacement
6683 int lastAddrIndx = 3; // [0,3]
6685 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6686 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1);
6687 for (int i=0; i <= lastAddrIndx; ++i)
6688 (*MIB).addOperand(*argOpers[i]);
6689 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6690 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
6691 // add 4 to displacement.
6692 for (int i=0; i <= lastAddrIndx-1; ++i)
6693 (*MIB).addOperand(*argOpers[i]);
6694 MachineOperand newOp3 = *(argOpers[3]);
6696 newOp3.setImm(newOp3.getImm()+4);
6698 newOp3.setOffset(newOp3.getOffset()+4);
6699 (*MIB).addOperand(newOp3);
6701 // t3/4 are defined later, at the bottom of the loop
6702 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
6703 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
6704 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg())
6705 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
6706 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg())
6707 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
6709 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
6710 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
6712 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1);
6713 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2);
6719 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
6721 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
6722 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
6723 if (argOpers[4]->isReg())
6724 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
6726 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
6727 if (regOpcL != X86::MOV32rr)
6729 (*MIB).addOperand(*argOpers[4]);
6730 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
6731 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
6732 if (argOpers[5]->isReg())
6733 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
6735 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
6736 if (regOpcH != X86::MOV32rr)
6738 (*MIB).addOperand(*argOpers[5]);
6740 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
6742 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX);
6745 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX);
6747 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX);
6750 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B));
6751 for (int i=0; i <= lastAddrIndx; ++i)
6752 (*MIB).addOperand(*argOpers[i]);
6754 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6755 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6757 MIB = BuildMI(newMBB, TII->get(copyOpc), t3);
6758 MIB.addReg(X86::EAX);
6759 MIB = BuildMI(newMBB, TII->get(copyOpc), t4);
6760 MIB.addReg(X86::EDX);
6763 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6765 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6769 // private utility function
6771 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6772 MachineBasicBlock *MBB,
6774 // For the atomic min/max operator, we generate
6777 // ld t1 = [min/max.addr]
6778 // mov t2 = [min/max.val]
6780 // cmov[cond] t2 = t1
6782 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6784 // fallthrough -->nextMBB
6786 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6787 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6788 MachineFunction::iterator MBBIter = MBB;
6791 /// First build the CFG
6792 MachineFunction *F = MBB->getParent();
6793 MachineBasicBlock *thisMBB = MBB;
6794 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6795 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6796 F->insert(MBBIter, newMBB);
6797 F->insert(MBBIter, nextMBB);
6799 // Move all successors to thisMBB to nextMBB
6800 nextMBB->transferSuccessors(thisMBB);
6802 // Update thisMBB to fall through to newMBB
6803 thisMBB->addSuccessor(newMBB);
6805 // newMBB jumps to newMBB and fall through to nextMBB
6806 newMBB->addSuccessor(nextMBB);
6807 newMBB->addSuccessor(newMBB);
6809 // Insert instructions into newMBB based on incoming instruction
6810 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6811 MachineOperand& destOper = mInstr->getOperand(0);
6812 MachineOperand* argOpers[6];
6813 int numArgs = mInstr->getNumOperands() - 1;
6814 for (int i=0; i < numArgs; ++i)
6815 argOpers[i] = &mInstr->getOperand(i+1);
6817 // x86 address has 4 operands: base, index, scale, and displacement
6818 int lastAddrIndx = 3; // [0,3]
6821 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6822 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6823 for (int i=0; i <= lastAddrIndx; ++i)
6824 (*MIB).addOperand(*argOpers[i]);
6826 // We only support register and immediate values
6827 assert((argOpers[valArgIndx]->isReg() ||
6828 argOpers[valArgIndx]->isImm()) &&
6831 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6832 if (argOpers[valArgIndx]->isReg())
6833 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6835 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6836 (*MIB).addOperand(*argOpers[valArgIndx]);
6838 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6841 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6846 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6847 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6851 // Cmp and exchange if none has modified the memory location
6852 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6853 for (int i=0; i <= lastAddrIndx; ++i)
6854 (*MIB).addOperand(*argOpers[i]);
6856 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6857 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
6859 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6860 MIB.addReg(X86::EAX);
6863 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6865 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
6871 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6872 MachineBasicBlock *BB) {
6873 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6874 switch (MI->getOpcode()) {
6875 default: assert(false && "Unexpected instr type to insert");
6876 case X86::CMOV_FR32:
6877 case X86::CMOV_FR64:
6878 case X86::CMOV_V4F32:
6879 case X86::CMOV_V2F64:
6880 case X86::CMOV_V2I64: {
6881 // To "insert" a SELECT_CC instruction, we actually have to insert the
6882 // diamond control-flow pattern. The incoming instruction knows the
6883 // destination vreg to set, the condition code register to branch on, the
6884 // true/false values to select between, and a branch opcode to use.
6885 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6886 MachineFunction::iterator It = BB;
6892 // cmpTY ccX, r1, r2
6894 // fallthrough --> copy0MBB
6895 MachineBasicBlock *thisMBB = BB;
6896 MachineFunction *F = BB->getParent();
6897 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6898 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6900 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6901 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6902 F->insert(It, copy0MBB);
6903 F->insert(It, sinkMBB);
6904 // Update machine-CFG edges by transferring all successors of the current
6905 // block to the new block which will contain the Phi node for the select.
6906 sinkMBB->transferSuccessors(BB);
6908 // Add the true and fallthrough blocks as its successors.
6909 BB->addSuccessor(copy0MBB);
6910 BB->addSuccessor(sinkMBB);
6913 // %FalseValue = ...
6914 // # fallthrough to sinkMBB
6917 // Update machine-CFG edges
6918 BB->addSuccessor(sinkMBB);
6921 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6924 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
6925 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6926 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6928 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6932 case X86::FP32_TO_INT16_IN_MEM:
6933 case X86::FP32_TO_INT32_IN_MEM:
6934 case X86::FP32_TO_INT64_IN_MEM:
6935 case X86::FP64_TO_INT16_IN_MEM:
6936 case X86::FP64_TO_INT32_IN_MEM:
6937 case X86::FP64_TO_INT64_IN_MEM:
6938 case X86::FP80_TO_INT16_IN_MEM:
6939 case X86::FP80_TO_INT32_IN_MEM:
6940 case X86::FP80_TO_INT64_IN_MEM: {
6941 // Change the floating point control register to use "round towards zero"
6942 // mode when truncating to an integer value.
6943 MachineFunction *F = BB->getParent();
6944 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
6945 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
6947 // Load the old value of the high byte of the control word...
6949 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
6950 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
6952 // Set the high part to be round to zero...
6953 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6956 // Reload the modified control word now...
6957 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6959 // Restore the memory image of control word to original value
6960 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6963 // Get the X86 opcode to use.
6965 switch (MI->getOpcode()) {
6966 default: assert(0 && "illegal opcode!");
6967 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6968 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6969 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6970 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6971 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6972 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
6973 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6974 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6975 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
6979 MachineOperand &Op = MI->getOperand(0);
6981 AM.BaseType = X86AddressMode::RegBase;
6982 AM.Base.Reg = Op.getReg();
6984 AM.BaseType = X86AddressMode::FrameIndexBase;
6985 AM.Base.FrameIndex = Op.getIndex();
6987 Op = MI->getOperand(1);
6989 AM.Scale = Op.getImm();
6990 Op = MI->getOperand(2);
6992 AM.IndexReg = Op.getImm();
6993 Op = MI->getOperand(3);
6994 if (Op.isGlobal()) {
6995 AM.GV = Op.getGlobal();
6997 AM.Disp = Op.getImm();
6999 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
7000 .addReg(MI->getOperand(4).getReg());
7002 // Reload the original control word now.
7003 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7005 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7008 case X86::ATOMAND32:
7009 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7010 X86::AND32ri, X86::MOV32rm,
7011 X86::LCMPXCHG32, X86::MOV32rr,
7012 X86::NOT32r, X86::EAX,
7013 X86::GR32RegisterClass);
7015 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7016 X86::OR32ri, X86::MOV32rm,
7017 X86::LCMPXCHG32, X86::MOV32rr,
7018 X86::NOT32r, X86::EAX,
7019 X86::GR32RegisterClass);
7020 case X86::ATOMXOR32:
7021 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7022 X86::XOR32ri, X86::MOV32rm,
7023 X86::LCMPXCHG32, X86::MOV32rr,
7024 X86::NOT32r, X86::EAX,
7025 X86::GR32RegisterClass);
7026 case X86::ATOMNAND32:
7027 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7028 X86::AND32ri, X86::MOV32rm,
7029 X86::LCMPXCHG32, X86::MOV32rr,
7030 X86::NOT32r, X86::EAX,
7031 X86::GR32RegisterClass, true);
7032 case X86::ATOMMIN32:
7033 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7034 case X86::ATOMMAX32:
7035 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7036 case X86::ATOMUMIN32:
7037 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7038 case X86::ATOMUMAX32:
7039 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7041 case X86::ATOMAND16:
7042 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7043 X86::AND16ri, X86::MOV16rm,
7044 X86::LCMPXCHG16, X86::MOV16rr,
7045 X86::NOT16r, X86::AX,
7046 X86::GR16RegisterClass);
7048 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7049 X86::OR16ri, X86::MOV16rm,
7050 X86::LCMPXCHG16, X86::MOV16rr,
7051 X86::NOT16r, X86::AX,
7052 X86::GR16RegisterClass);
7053 case X86::ATOMXOR16:
7054 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7055 X86::XOR16ri, X86::MOV16rm,
7056 X86::LCMPXCHG16, X86::MOV16rr,
7057 X86::NOT16r, X86::AX,
7058 X86::GR16RegisterClass);
7059 case X86::ATOMNAND16:
7060 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7061 X86::AND16ri, X86::MOV16rm,
7062 X86::LCMPXCHG16, X86::MOV16rr,
7063 X86::NOT16r, X86::AX,
7064 X86::GR16RegisterClass, true);
7065 case X86::ATOMMIN16:
7066 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7067 case X86::ATOMMAX16:
7068 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7069 case X86::ATOMUMIN16:
7070 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7071 case X86::ATOMUMAX16:
7072 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7075 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7076 X86::AND8ri, X86::MOV8rm,
7077 X86::LCMPXCHG8, X86::MOV8rr,
7078 X86::NOT8r, X86::AL,
7079 X86::GR8RegisterClass);
7081 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7082 X86::OR8ri, X86::MOV8rm,
7083 X86::LCMPXCHG8, X86::MOV8rr,
7084 X86::NOT8r, X86::AL,
7085 X86::GR8RegisterClass);
7087 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7088 X86::XOR8ri, X86::MOV8rm,
7089 X86::LCMPXCHG8, X86::MOV8rr,
7090 X86::NOT8r, X86::AL,
7091 X86::GR8RegisterClass);
7092 case X86::ATOMNAND8:
7093 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7094 X86::AND8ri, X86::MOV8rm,
7095 X86::LCMPXCHG8, X86::MOV8rr,
7096 X86::NOT8r, X86::AL,
7097 X86::GR8RegisterClass, true);
7098 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7099 // This group is for 64-bit host.
7100 case X86::ATOMAND64:
7101 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7102 X86::AND64ri32, X86::MOV64rm,
7103 X86::LCMPXCHG64, X86::MOV64rr,
7104 X86::NOT64r, X86::RAX,
7105 X86::GR64RegisterClass);
7107 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7108 X86::OR64ri32, X86::MOV64rm,
7109 X86::LCMPXCHG64, X86::MOV64rr,
7110 X86::NOT64r, X86::RAX,
7111 X86::GR64RegisterClass);
7112 case X86::ATOMXOR64:
7113 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7114 X86::XOR64ri32, X86::MOV64rm,
7115 X86::LCMPXCHG64, X86::MOV64rr,
7116 X86::NOT64r, X86::RAX,
7117 X86::GR64RegisterClass);
7118 case X86::ATOMNAND64:
7119 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7120 X86::AND64ri32, X86::MOV64rm,
7121 X86::LCMPXCHG64, X86::MOV64rr,
7122 X86::NOT64r, X86::RAX,
7123 X86::GR64RegisterClass, true);
7124 case X86::ATOMMIN64:
7125 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7126 case X86::ATOMMAX64:
7127 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7128 case X86::ATOMUMIN64:
7129 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7130 case X86::ATOMUMAX64:
7131 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7133 // This group does 64-bit operations on a 32-bit host.
7134 case X86::ATOMAND6432:
7135 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7136 X86::AND32rr, X86::AND32rr,
7137 X86::AND32ri, X86::AND32ri,
7139 case X86::ATOMOR6432:
7140 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7141 X86::OR32rr, X86::OR32rr,
7142 X86::OR32ri, X86::OR32ri,
7144 case X86::ATOMXOR6432:
7145 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7146 X86::XOR32rr, X86::XOR32rr,
7147 X86::XOR32ri, X86::XOR32ri,
7149 case X86::ATOMNAND6432:
7150 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7151 X86::AND32rr, X86::AND32rr,
7152 X86::AND32ri, X86::AND32ri,
7154 case X86::ATOMADD6432:
7155 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7156 X86::ADD32rr, X86::ADC32rr,
7157 X86::ADD32ri, X86::ADC32ri,
7159 case X86::ATOMSUB6432:
7160 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7161 X86::SUB32rr, X86::SBB32rr,
7162 X86::SUB32ri, X86::SBB32ri,
7164 case X86::ATOMSWAP6432:
7165 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7166 X86::MOV32rr, X86::MOV32rr,
7167 X86::MOV32ri, X86::MOV32ri,
7172 //===----------------------------------------------------------------------===//
7173 // X86 Optimization Hooks
7174 //===----------------------------------------------------------------------===//
7176 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7180 const SelectionDAG &DAG,
7181 unsigned Depth) const {
7182 unsigned Opc = Op.getOpcode();
7183 assert((Opc >= ISD::BUILTIN_OP_END ||
7184 Opc == ISD::INTRINSIC_WO_CHAIN ||
7185 Opc == ISD::INTRINSIC_W_CHAIN ||
7186 Opc == ISD::INTRINSIC_VOID) &&
7187 "Should use MaskedValueIsZero if you don't know whether Op"
7188 " is a target node!");
7190 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7194 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7195 Mask.getBitWidth() - 1);
7200 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7201 /// node is a GlobalAddress + offset.
7202 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7203 GlobalValue* &GA, int64_t &Offset) const{
7204 if (N->getOpcode() == X86ISD::Wrapper) {
7205 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7206 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7207 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7211 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7214 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7215 const TargetLowering &TLI) {
7218 if (TLI.isGAPlusOffset(Base, GV, Offset))
7219 return (GV->getAlignment() >= N && (Offset % N) == 0);
7220 // DAG combine handles the stack object case.
7224 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
7225 unsigned NumElems, MVT EVT,
7227 SelectionDAG &DAG, MachineFrameInfo *MFI,
7228 const TargetLowering &TLI) {
7230 for (unsigned i = 0; i < NumElems; ++i) {
7231 SDValue Idx = PermMask.getOperand(i);
7232 if (Idx.getOpcode() == ISD::UNDEF) {
7238 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7239 if (!Elt.getNode() ||
7240 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7243 Base = Elt.getNode();
7244 if (Base->getOpcode() == ISD::UNDEF)
7248 if (Elt.getOpcode() == ISD::UNDEF)
7251 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
7252 EVT.getSizeInBits()/8, i, MFI))
7258 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7259 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7260 /// if the load addresses are consecutive, non-overlapping, and in the right
7262 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7263 const TargetLowering &TLI) {
7264 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7265 MVT VT = N->getValueType(0);
7266 MVT EVT = VT.getVectorElementType();
7267 SDValue PermMask = N->getOperand(2);
7268 unsigned NumElems = PermMask.getNumOperands();
7269 SDNode *Base = NULL;
7270 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
7274 LoadSDNode *LD = cast<LoadSDNode>(Base);
7275 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
7276 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7277 LD->getSrcValueOffset(), LD->isVolatile());
7278 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7279 LD->getSrcValueOffset(), LD->isVolatile(),
7280 LD->getAlignment());
7283 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
7284 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
7285 const X86Subtarget *Subtarget,
7286 const TargetLowering &TLI) {
7287 unsigned NumOps = N->getNumOperands();
7289 // Ignore single operand BUILD_VECTOR.
7293 MVT VT = N->getValueType(0);
7294 MVT EVT = VT.getVectorElementType();
7295 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
7296 // We are looking for load i64 and zero extend. We want to transform
7297 // it before legalizer has a chance to expand it. Also look for i64
7298 // BUILD_PAIR bit casted to f64.
7300 // This must be an insertion into a zero vector.
7301 SDValue HighElt = N->getOperand(1);
7302 if (!isZeroNode(HighElt))
7305 // Value must be a load.
7306 SDNode *Base = N->getOperand(0).getNode();
7307 if (!isa<LoadSDNode>(Base)) {
7308 if (Base->getOpcode() != ISD::BIT_CONVERT)
7310 Base = Base->getOperand(0).getNode();
7311 if (!isa<LoadSDNode>(Base))
7315 // Transform it into VZEXT_LOAD addr.
7316 LoadSDNode *LD = cast<LoadSDNode>(Base);
7318 // Load must not be an extload.
7319 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
7322 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
7323 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7324 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
7325 DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
7329 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7330 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7331 const X86Subtarget *Subtarget) {
7332 SDValue Cond = N->getOperand(0);
7334 // If we have SSE[12] support, try to form min/max nodes.
7335 if (Subtarget->hasSSE2() &&
7336 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
7337 if (Cond.getOpcode() == ISD::SETCC) {
7338 // Get the LHS/RHS of the select.
7339 SDValue LHS = N->getOperand(1);
7340 SDValue RHS = N->getOperand(2);
7341 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7343 unsigned Opcode = 0;
7344 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7347 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7350 if (!UnsafeFPMath) break;
7352 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7354 Opcode = X86ISD::FMIN;
7357 case ISD::SETOGT: // (X > Y) ? X : Y -> max
7360 if (!UnsafeFPMath) break;
7362 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
7364 Opcode = X86ISD::FMAX;
7367 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
7370 case ISD::SETOGT: // (X > Y) ? Y : X -> min
7373 if (!UnsafeFPMath) break;
7375 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
7377 Opcode = X86ISD::FMIN;
7380 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
7383 if (!UnsafeFPMath) break;
7385 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
7387 Opcode = X86ISD::FMAX;
7393 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
7401 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
7402 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
7403 const X86Subtarget *Subtarget) {
7404 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
7405 // the FP state in cases where an emms may be missing.
7406 // A preferable solution to the general problem is to figure out the right
7407 // places to insert EMMS. This qualifies as a quick hack.
7408 StoreSDNode *St = cast<StoreSDNode>(N);
7409 if (St->getValue().getValueType().isVector() &&
7410 St->getValue().getValueType().getSizeInBits() == 64 &&
7411 isa<LoadSDNode>(St->getValue()) &&
7412 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
7413 St->getChain().hasOneUse() && !St->isVolatile()) {
7414 SDNode* LdVal = St->getValue().getNode();
7416 int TokenFactorIndex = -1;
7417 SmallVector<SDValue, 8> Ops;
7418 SDNode* ChainVal = St->getChain().getNode();
7419 // Must be a store of a load. We currently handle two cases: the load
7420 // is a direct child, and it's under an intervening TokenFactor. It is
7421 // possible to dig deeper under nested TokenFactors.
7422 if (ChainVal == LdVal)
7423 Ld = cast<LoadSDNode>(St->getChain());
7424 else if (St->getValue().hasOneUse() &&
7425 ChainVal->getOpcode() == ISD::TokenFactor) {
7426 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
7427 if (ChainVal->getOperand(i).getNode() == LdVal) {
7428 TokenFactorIndex = i;
7429 Ld = cast<LoadSDNode>(St->getValue());
7431 Ops.push_back(ChainVal->getOperand(i));
7435 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
7436 if (Subtarget->is64Bit()) {
7437 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
7438 Ld->getBasePtr(), Ld->getSrcValue(),
7439 Ld->getSrcValueOffset(), Ld->isVolatile(),
7440 Ld->getAlignment());
7441 SDValue NewChain = NewLd.getValue(1);
7442 if (TokenFactorIndex != -1) {
7443 Ops.push_back(NewChain);
7444 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7447 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
7448 St->getSrcValue(), St->getSrcValueOffset(),
7449 St->isVolatile(), St->getAlignment());
7452 // Otherwise, lower to two 32-bit copies.
7453 SDValue LoAddr = Ld->getBasePtr();
7454 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7455 DAG.getConstant(4, MVT::i32));
7457 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
7458 Ld->getSrcValue(), Ld->getSrcValueOffset(),
7459 Ld->isVolatile(), Ld->getAlignment());
7460 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
7461 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
7463 MinAlign(Ld->getAlignment(), 4));
7465 SDValue NewChain = LoLd.getValue(1);
7466 if (TokenFactorIndex != -1) {
7467 Ops.push_back(LoLd);
7468 Ops.push_back(HiLd);
7469 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7473 LoAddr = St->getBasePtr();
7474 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7475 DAG.getConstant(4, MVT::i32));
7477 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
7478 St->getSrcValue(), St->getSrcValueOffset(),
7479 St->isVolatile(), St->getAlignment());
7480 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
7482 St->getSrcValueOffset() + 4,
7484 MinAlign(St->getAlignment(), 4));
7485 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
7491 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
7492 /// X86ISD::FXOR nodes.
7493 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
7494 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
7495 // F[X]OR(0.0, x) -> x
7496 // F[X]OR(x, 0.0) -> x
7497 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7498 if (C->getValueAPF().isPosZero())
7499 return N->getOperand(1);
7500 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7501 if (C->getValueAPF().isPosZero())
7502 return N->getOperand(0);
7506 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
7507 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
7508 // FAND(0.0, x) -> 0.0
7509 // FAND(x, 0.0) -> 0.0
7510 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7511 if (C->getValueAPF().isPosZero())
7512 return N->getOperand(0);
7513 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7514 if (C->getValueAPF().isPosZero())
7515 return N->getOperand(1);
7520 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
7521 DAGCombinerInfo &DCI) const {
7522 SelectionDAG &DAG = DCI.DAG;
7523 switch (N->getOpcode()) {
7525 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7526 case ISD::BUILD_VECTOR:
7527 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
7528 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
7529 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
7531 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7532 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7538 //===----------------------------------------------------------------------===//
7539 // X86 Inline Assembly Support
7540 //===----------------------------------------------------------------------===//
7542 /// getConstraintType - Given a constraint letter, return the type of
7543 /// constraint it is for this target.
7544 X86TargetLowering::ConstraintType
7545 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7546 if (Constraint.size() == 1) {
7547 switch (Constraint[0]) {
7559 return C_RegisterClass;
7564 return TargetLowering::getConstraintType(Constraint);
7567 /// LowerXConstraint - try to replace an X constraint, which matches anything,
7568 /// with another that has more specific requirements based on the type of the
7569 /// corresponding operand.
7570 const char *X86TargetLowering::
7571 LowerXConstraint(MVT ConstraintVT) const {
7572 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7573 // 'f' like normal targets.
7574 if (ConstraintVT.isFloatingPoint()) {
7575 if (Subtarget->hasSSE2())
7577 if (Subtarget->hasSSE1())
7581 return TargetLowering::LowerXConstraint(ConstraintVT);
7584 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7585 /// vector. If it is invalid, don't add anything to Ops.
7586 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7589 std::vector<SDValue>&Ops,
7590 SelectionDAG &DAG) const {
7591 SDValue Result(0, 0);
7593 switch (Constraint) {
7596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7597 if (C->getZExtValue() <= 31) {
7598 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7604 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7605 if (C->getZExtValue() <= 63) {
7606 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7612 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7613 if (C->getZExtValue() <= 255) {
7614 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7620 // Literal immediates are always ok.
7621 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
7622 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
7626 // If we are in non-pic codegen mode, we allow the address of a global (with
7627 // an optional displacement) to be used with 'i'.
7628 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7631 // Match either (GA) or (GA+C)
7633 Offset = GA->getOffset();
7634 } else if (Op.getOpcode() == ISD::ADD) {
7635 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7636 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7638 Offset = GA->getOffset()+C->getZExtValue();
7640 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7641 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7643 Offset = GA->getOffset()+C->getZExtValue();
7651 Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG);
7653 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
7659 // Otherwise, not valid for this mode.
7664 if (Result.getNode()) {
7665 Ops.push_back(Result);
7668 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
7672 std::vector<unsigned> X86TargetLowering::
7673 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7675 if (Constraint.size() == 1) {
7676 // FIXME: not handling fp-stack yet!
7677 switch (Constraint[0]) { // GCC X86 Constraint Letters
7678 default: break; // Unknown constraint letter
7679 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
7682 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
7683 else if (VT == MVT::i16)
7684 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
7685 else if (VT == MVT::i8)
7686 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
7687 else if (VT == MVT::i64)
7688 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
7693 return std::vector<unsigned>();
7696 std::pair<unsigned, const TargetRegisterClass*>
7697 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7699 // First, see if this is a constraint that directly corresponds to an LLVM
7701 if (Constraint.size() == 1) {
7702 // GCC Constraint Letters
7703 switch (Constraint[0]) {
7705 case 'r': // GENERAL_REGS
7706 case 'R': // LEGACY_REGS
7707 case 'l': // INDEX_REGS
7709 return std::make_pair(0U, X86::GR8RegisterClass);
7711 return std::make_pair(0U, X86::GR16RegisterClass);
7712 if (VT == MVT::i32 || !Subtarget->is64Bit())
7713 return std::make_pair(0U, X86::GR32RegisterClass);
7714 return std::make_pair(0U, X86::GR64RegisterClass);
7715 case 'f': // FP Stack registers.
7716 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
7717 // value to the correct fpstack register class.
7718 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
7719 return std::make_pair(0U, X86::RFP32RegisterClass);
7720 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
7721 return std::make_pair(0U, X86::RFP64RegisterClass);
7722 return std::make_pair(0U, X86::RFP80RegisterClass);
7723 case 'y': // MMX_REGS if MMX allowed.
7724 if (!Subtarget->hasMMX()) break;
7725 return std::make_pair(0U, X86::VR64RegisterClass);
7726 case 'Y': // SSE_REGS if SSE2 allowed
7727 if (!Subtarget->hasSSE2()) break;
7729 case 'x': // SSE_REGS if SSE1 allowed
7730 if (!Subtarget->hasSSE1()) break;
7732 switch (VT.getSimpleVT()) {
7734 // Scalar SSE types.
7737 return std::make_pair(0U, X86::FR32RegisterClass);
7740 return std::make_pair(0U, X86::FR64RegisterClass);
7748 return std::make_pair(0U, X86::VR128RegisterClass);
7754 // Use the default implementation in TargetLowering to convert the register
7755 // constraint into a member of a register class.
7756 std::pair<unsigned, const TargetRegisterClass*> Res;
7757 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7759 // Not found as a standard register?
7760 if (Res.second == 0) {
7761 // GCC calls "st(0)" just plain "st".
7762 if (StringsEqualNoCase("{st}", Constraint)) {
7763 Res.first = X86::ST0;
7764 Res.second = X86::RFP80RegisterClass;
7766 // 'A' means EAX + EDX.
7767 if (Constraint == "A") {
7768 Res.first = X86::EAX;
7769 Res.second = X86::GRADRegisterClass;
7774 // Otherwise, check to see if this is a register class of the wrong value
7775 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
7776 // turn into {ax},{dx}.
7777 if (Res.second->hasType(VT))
7778 return Res; // Correct type already, nothing to do.
7780 // All of the single-register GCC register classes map their values onto
7781 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
7782 // really want an 8-bit or 32-bit register, map to the appropriate register
7783 // class and return the appropriate register.
7784 if (Res.second == X86::GR16RegisterClass) {
7785 if (VT == MVT::i8) {
7786 unsigned DestReg = 0;
7787 switch (Res.first) {
7789 case X86::AX: DestReg = X86::AL; break;
7790 case X86::DX: DestReg = X86::DL; break;
7791 case X86::CX: DestReg = X86::CL; break;
7792 case X86::BX: DestReg = X86::BL; break;
7795 Res.first = DestReg;
7796 Res.second = Res.second = X86::GR8RegisterClass;
7798 } else if (VT == MVT::i32) {
7799 unsigned DestReg = 0;
7800 switch (Res.first) {
7802 case X86::AX: DestReg = X86::EAX; break;
7803 case X86::DX: DestReg = X86::EDX; break;
7804 case X86::CX: DestReg = X86::ECX; break;
7805 case X86::BX: DestReg = X86::EBX; break;
7806 case X86::SI: DestReg = X86::ESI; break;
7807 case X86::DI: DestReg = X86::EDI; break;
7808 case X86::BP: DestReg = X86::EBP; break;
7809 case X86::SP: DestReg = X86::ESP; break;
7812 Res.first = DestReg;
7813 Res.second = Res.second = X86::GR32RegisterClass;
7815 } else if (VT == MVT::i64) {
7816 unsigned DestReg = 0;
7817 switch (Res.first) {
7819 case X86::AX: DestReg = X86::RAX; break;
7820 case X86::DX: DestReg = X86::RDX; break;
7821 case X86::CX: DestReg = X86::RCX; break;
7822 case X86::BX: DestReg = X86::RBX; break;
7823 case X86::SI: DestReg = X86::RSI; break;
7824 case X86::DI: DestReg = X86::RDI; break;
7825 case X86::BP: DestReg = X86::RBP; break;
7826 case X86::SP: DestReg = X86::RSP; break;
7829 Res.first = DestReg;
7830 Res.second = Res.second = X86::GR64RegisterClass;
7833 } else if (Res.second == X86::FR32RegisterClass ||
7834 Res.second == X86::FR64RegisterClass ||
7835 Res.second == X86::VR128RegisterClass) {
7836 // Handle references to XMM physical registers that got mapped into the
7837 // wrong class. This can happen with constraints like {xmm0} where the
7838 // target independent register mapper will just pick the first match it can
7839 // find, ignoring the required type.
7841 Res.second = X86::FR32RegisterClass;
7842 else if (VT == MVT::f64)
7843 Res.second = X86::FR64RegisterClass;
7844 else if (X86::VR128RegisterClass->hasType(VT))
7845 Res.second = X86::VR128RegisterClass;
7851 //===----------------------------------------------------------------------===//
7852 // X86 Widen vector type
7853 //===----------------------------------------------------------------------===//
7855 /// getWidenVectorType: given a vector type, returns the type to widen
7856 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
7857 /// If there is no vector type that we want to widen to, returns MVT::Other
7858 /// When and where to widen is target dependent based on the cost of
7859 /// scalarizing vs using the wider vector type.
7861 MVT X86TargetLowering::getWidenVectorType(MVT VT) {
7862 assert(VT.isVector());
7863 if (isTypeLegal(VT))
7866 // TODO: In computeRegisterProperty, we can compute the list of legal vector
7867 // type based on element type. This would speed up our search (though
7868 // it may not be worth it since the size of the list is relatively
7870 MVT EltVT = VT.getVectorElementType();
7871 unsigned NElts = VT.getVectorNumElements();
7873 // On X86, it make sense to widen any vector wider than 1
7877 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
7878 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
7879 MVT SVT = (MVT::SimpleValueType)nVT;
7881 if (isTypeLegal(SVT) &&
7882 SVT.getVectorElementType() == EltVT &&
7883 SVT.getVectorNumElements() > NElts)