1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
168 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
169 } else if (!Subtarget->useSoftFloat()) {
170 // We have an algorithm for SSE2->double, and we turn this into a
171 // 64-bit FILD followed by conditional FADD for other targets.
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 // We have an algorithm for SSE2, and we turn this into a 64-bit
174 // FILD for other targets.
175 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
178 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
180 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
183 if (!Subtarget->useSoftFloat()) {
184 // SSE has no i16 to fp conversion, only i32
185 if (X86ScalarSSEf32) {
186 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
187 // f32 and f64 cases are Legal, f80 case is not
188 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
191 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
198 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
199 // are Legal, f80 is custom lowered.
200 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
203 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
205 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
206 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
208 if (X86ScalarSSEf32) {
209 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
210 // f32 and f64 cases are Legal, f80 case is not
211 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
214 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 // Handle FP_TO_UINT by promoting the destination to a larger signed
219 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
220 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
221 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
223 if (Subtarget->is64Bit()) {
224 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
225 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
226 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
227 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
229 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
232 } else if (!Subtarget->useSoftFloat()) {
233 // Since AVX is a superset of SSE3, only check for SSE here.
234 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
235 // Expand FP_TO_UINT into a select.
236 // FIXME: We would like to use a Custom expander here eventually to do
237 // the optimal thing for SSE vs. the default expansion in the legalizer.
238 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
240 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
241 // With SSE3 we can use fisttpll to convert to a signed i64; without
242 // SSE, we're stuck with a fistpll.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
245 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
248 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
249 if (!X86ScalarSSEf64) {
250 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
251 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
252 if (Subtarget->is64Bit()) {
253 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
254 // Without SSE, i64->f64 goes through memory.
255 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
259 // Scalar integer divide and remainder are lowered to use operations that
260 // produce two results, to match the available instructions. This exposes
261 // the two-result form to trivial CSE, which is able to combine x/y and x%y
262 // into a single instruction.
264 // Scalar integer multiply-high is also lowered to use two-result
265 // operations, to match the available instructions. However, plain multiply
266 // (low) operations are left as Legal, as there are single-result
267 // instructions for this in x86. Using the two-result multiply instructions
268 // when both high and low results are needed must be arranged by dagcombine.
269 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
271 setOperationAction(ISD::MULHS, VT, Expand);
272 setOperationAction(ISD::MULHU, VT, Expand);
273 setOperationAction(ISD::SDIV, VT, Expand);
274 setOperationAction(ISD::UDIV, VT, Expand);
275 setOperationAction(ISD::SREM, VT, Expand);
276 setOperationAction(ISD::UREM, VT, Expand);
278 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
279 setOperationAction(ISD::ADDC, VT, Custom);
280 setOperationAction(ISD::ADDE, VT, Custom);
281 setOperationAction(ISD::SUBC, VT, Custom);
282 setOperationAction(ISD::SUBE, VT, Custom);
285 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
286 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
287 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
288 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
289 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
290 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
291 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
292 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
293 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
294 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
295 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
296 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
297 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
301 if (Subtarget->is64Bit())
302 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
303 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
304 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
305 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
306 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
308 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
309 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
310 // is. We should promote the value to 64-bits to solve this.
311 // This is what the CRT headers do - `fmodf` is an inline header
312 // function casting to f64 and calling `fmod`.
313 setOperationAction(ISD::FREM , MVT::f32 , Promote);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
318 setOperationAction(ISD::FREM , MVT::f64 , Expand);
319 setOperationAction(ISD::FREM , MVT::f80 , Expand);
320 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
322 // Promote the i8 variants and force them on up to i32 which has a shorter
324 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
326 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
327 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
328 if (Subtarget->hasBMI()) {
329 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
331 if (Subtarget->is64Bit())
332 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
334 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
335 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
336 if (Subtarget->is64Bit())
337 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
340 if (Subtarget->hasLZCNT()) {
341 // When promoting the i8 variants, force them to i32 for a shorter
343 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
346 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
347 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
349 if (Subtarget->is64Bit())
350 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
352 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
353 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
354 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
358 if (Subtarget->is64Bit()) {
359 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
364 // Special handling for half-precision floating point conversions.
365 // If we don't have F16C support, then lower half float conversions
366 // into library calls.
367 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
368 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
369 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
372 // There's never any support for operations beyond MVT::f32.
373 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
374 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
375 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
376 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
379 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
380 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
382 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
383 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
385 if (Subtarget->hasPOPCNT()) {
386 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
388 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
389 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
390 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
391 if (Subtarget->is64Bit())
392 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
395 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
397 if (!Subtarget->hasMOVBE())
398 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
400 // These should be promoted to a larger select which is supported.
401 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
402 // X86 wants to expand cmov itself.
403 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
404 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
405 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
407 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
410 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
413 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
417 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
419 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
420 setOperationAction(ISD::CATCHRET , MVT::Other, Custom);
421 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
422 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
423 // support continuation, user-level threading, and etc.. As a result, no
424 // other SjLj exception interfaces are implemented and please don't build
425 // your own exception handling based on them.
426 // LLVM/Clang supports zero-cost DWARF exception handling.
427 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
428 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
431 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
432 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
433 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
434 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
435 if (Subtarget->is64Bit())
436 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
437 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
438 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
439 if (Subtarget->is64Bit()) {
440 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
441 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
442 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
443 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
444 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
446 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
447 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
448 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
449 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
450 if (Subtarget->is64Bit()) {
451 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
452 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
453 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
456 if (Subtarget->hasSSE1())
457 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
459 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
461 // Expand certain atomics
462 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
464 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
465 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
466 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
469 if (Subtarget->hasCmpxchg16b()) {
470 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
473 // FIXME - use subtarget debug flags
474 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
475 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
476 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
479 if (Subtarget->isTarget64BitLP64()) {
480 setExceptionPointerRegister(X86::RAX);
481 setExceptionSelectorRegister(X86::RDX);
483 setExceptionPointerRegister(X86::EAX);
484 setExceptionSelectorRegister(X86::EDX);
486 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
487 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
489 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
490 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
492 setOperationAction(ISD::TRAP, MVT::Other, Legal);
493 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
495 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
496 setOperationAction(ISD::VASTART , MVT::Other, Custom);
497 setOperationAction(ISD::VAEND , MVT::Other, Expand);
498 if (Subtarget->is64Bit()) {
499 setOperationAction(ISD::VAARG , MVT::Other, Custom);
500 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
502 // TargetInfo::CharPtrBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Expand);
504 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
507 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
508 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
510 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
512 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
513 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
514 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
516 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!Subtarget->useSoftFloat()) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!Subtarget->useSoftFloat()) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
750 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
751 // split/scalarized right now.
752 if (VT.getVectorElementType() == MVT::f16)
753 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
757 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
758 // with -msoft-float, disable use of MMX as well.
759 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
760 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
761 // No operations on x86mmx supported, everything uses intrinsics.
764 // MMX-sized vectors (other than x86mmx) are expected to be expanded
765 // into smaller operations.
766 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
767 setOperationAction(ISD::MULHS, MMXTy, Expand);
768 setOperationAction(ISD::AND, MMXTy, Expand);
769 setOperationAction(ISD::OR, MMXTy, Expand);
770 setOperationAction(ISD::XOR, MMXTy, Expand);
771 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
772 setOperationAction(ISD::SELECT, MMXTy, Expand);
773 setOperationAction(ISD::BITCAST, MMXTy, Expand);
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
777 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
778 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
780 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
781 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
782 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
783 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
785 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
786 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
787 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
789 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
790 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
792 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
793 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
796 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
797 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
799 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
800 // registers cannot be used even for integer operations.
801 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
802 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
803 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
804 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
806 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
807 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
808 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
809 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
810 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
811 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
812 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
813 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
814 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
815 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
816 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
818 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
819 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
820 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
821 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
822 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
823 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
824 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
825 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
827 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
828 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
830 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
832 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
833 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
835 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
836 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
837 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
838 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
841 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
848 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
851 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
852 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
853 MVT VT = (MVT::SimpleValueType)i;
854 // Do not attempt to custom lower non-power-of-2 vectors
855 if (!isPowerOf2_32(VT.getVectorNumElements()))
857 // Do not attempt to custom lower non-128-bit vectors
858 if (!VT.is128BitVector())
860 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
861 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
862 setOperationAction(ISD::VSELECT, VT, Custom);
863 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
866 // We support custom legalizing of sext and anyext loads for specific
867 // memory vector types which we can load as a scalar (or sequence of
868 // scalars) and extend in-register to a legal 128-bit vector type. For sext
869 // loads these must work with a single scalar load.
870 for (MVT VT : MVT::integer_vector_valuetypes()) {
871 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
872 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
874 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
882 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
883 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
884 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
885 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
886 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
887 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
888 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
889 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
891 if (Subtarget->is64Bit()) {
892 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
893 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
896 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
897 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
898 MVT VT = (MVT::SimpleValueType)i;
900 // Do not attempt to promote non-128-bit vectors
901 if (!VT.is128BitVector())
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1042 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1043 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1044 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1045 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1046 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1047 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1049 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1050 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1051 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1053 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1054 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1056 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1057 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1058 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1059 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1060 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1062 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1063 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1064 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1066 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1067 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1069 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1070 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1071 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1072 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1073 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1075 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1076 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1077 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1079 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1080 // even though v8i16 is a legal type.
1081 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1082 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1083 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1085 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1086 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1087 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1089 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1090 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1092 for (MVT VT : MVT::fp_vector_valuetypes())
1093 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1095 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1096 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1098 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1099 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1101 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1102 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1104 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1106 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1109 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1110 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1113 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1115 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1116 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1117 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1118 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1119 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1120 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1121 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1122 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1123 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1124 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1126 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1127 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1128 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1129 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1131 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1132 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1134 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1135 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1136 setOperationAction(ISD::FMA, MVT::f32, Legal);
1137 setOperationAction(ISD::FMA, MVT::f64, Legal);
1140 if (Subtarget->hasInt256()) {
1141 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1142 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1143 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1144 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1146 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1147 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1148 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1149 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1151 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1152 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1153 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1154 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1156 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1157 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1158 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1159 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1161 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1162 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1163 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1164 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1165 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1166 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1167 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1168 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1170 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1171 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1172 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1174 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1175 // when we have a 256bit-wide blend with immediate.
1176 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1178 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1179 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1180 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1181 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1182 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1183 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1184 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1186 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1187 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1188 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1189 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1190 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1191 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1193 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1194 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1195 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1196 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1198 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1199 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1200 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1201 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1203 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1204 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1205 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1206 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1208 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1209 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1210 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1211 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1212 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1213 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1214 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1215 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1216 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1217 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1218 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1219 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1222 // In the customized shift lowering, the legal cases in AVX2 will be
1224 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1227 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1228 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1233 // Custom lower several nodes for 256-bit types.
1234 for (MVT VT : MVT::vector_valuetypes()) {
1235 if (VT.getScalarSizeInBits() >= 32) {
1236 setOperationAction(ISD::MLOAD, VT, Legal);
1237 setOperationAction(ISD::MSTORE, VT, Legal);
1239 // Extract subvector is special because the value type
1240 // (result) is 128-bit but the source is 256-bit wide.
1241 if (VT.is128BitVector()) {
1242 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1244 // Do not attempt to custom lower other non-256-bit vectors
1245 if (!VT.is256BitVector())
1248 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1249 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1250 setOperationAction(ISD::VSELECT, VT, Custom);
1251 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1252 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1253 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1254 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1255 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1258 if (Subtarget->hasInt256())
1259 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1262 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1263 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1264 MVT VT = (MVT::SimpleValueType)i;
1266 // Do not attempt to promote non-256-bit vectors
1267 if (!VT.is256BitVector())
1270 setOperationAction(ISD::AND, VT, Promote);
1271 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1272 setOperationAction(ISD::OR, VT, Promote);
1273 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1274 setOperationAction(ISD::XOR, VT, Promote);
1275 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1276 setOperationAction(ISD::LOAD, VT, Promote);
1277 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1278 setOperationAction(ISD::SELECT, VT, Promote);
1279 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1283 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1284 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1285 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1286 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1287 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1289 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1290 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1291 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1293 for (MVT VT : MVT::fp_vector_valuetypes())
1294 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1296 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1297 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1298 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1299 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1300 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1301 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1302 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1303 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1304 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1305 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1306 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1307 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1309 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1310 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1311 setOperationAction(ISD::XOR, MVT::i1, Legal);
1312 setOperationAction(ISD::OR, MVT::i1, Legal);
1313 setOperationAction(ISD::AND, MVT::i1, Legal);
1314 setOperationAction(ISD::SUB, MVT::i1, Custom);
1315 setOperationAction(ISD::ADD, MVT::i1, Custom);
1316 setOperationAction(ISD::MUL, MVT::i1, Custom);
1317 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1318 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1319 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1323 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1330 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1332 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1336 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1339 // FIXME: [US]INT_TO_FP are not legal for f80.
1340 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1341 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1342 if (Subtarget->is64Bit()) {
1343 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1346 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1347 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1348 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1349 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1350 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1351 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1352 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1354 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1355 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1356 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1359 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1360 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1361 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1363 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1364 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1365 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1366 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1367 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1368 if (Subtarget->hasVLX()){
1369 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1370 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1371 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1372 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1373 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1375 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1376 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1377 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1378 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1379 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1381 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1382 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1383 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1384 if (Subtarget->hasDQI()) {
1385 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1386 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1388 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1389 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1390 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1391 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1392 if (Subtarget->hasVLX()) {
1393 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1394 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1395 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1396 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1397 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1399 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1403 if (Subtarget->hasVLX()) {
1404 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1407 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1409 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1410 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1413 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1414 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1415 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1416 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1417 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1418 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1419 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1420 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1421 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1422 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1423 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1424 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1425 if (Subtarget->hasDQI()) {
1426 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1427 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1429 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1430 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1431 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1432 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1433 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1434 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1435 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1436 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1437 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1438 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1446 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1447 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1449 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1461 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1463 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1464 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1465 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1466 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1467 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1469 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1470 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1472 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1473 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1475 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1476 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1478 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1481 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1483 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1484 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1486 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1487 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1489 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1490 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1491 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1492 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1493 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1494 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1496 if (Subtarget->hasCDI()) {
1497 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1498 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1502 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1503 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1504 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1505 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1506 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1512 if (Subtarget->hasDQI()) {
1513 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1514 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1515 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1517 // Custom lower several nodes.
1518 for (MVT VT : MVT::vector_valuetypes()) {
1519 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1521 setOperationAction(ISD::AND, VT, Legal);
1522 setOperationAction(ISD::OR, VT, Legal);
1523 setOperationAction(ISD::XOR, VT, Legal);
1525 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1526 setOperationAction(ISD::MGATHER, VT, Custom);
1527 setOperationAction(ISD::MSCATTER, VT, Custom);
1529 // Extract subvector is special because the value type
1530 // (result) is 256/128-bit but the source is 512-bit wide.
1531 if (VT.is128BitVector() || VT.is256BitVector()) {
1532 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1534 if (VT.getVectorElementType() == MVT::i1)
1535 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1537 // Do not attempt to custom lower other non-512-bit vectors
1538 if (!VT.is512BitVector())
1541 if (EltSize >= 32) {
1542 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1543 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1544 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1545 setOperationAction(ISD::VSELECT, VT, Legal);
1546 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1547 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1548 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1549 setOperationAction(ISD::MLOAD, VT, Legal);
1550 setOperationAction(ISD::MSTORE, VT, Legal);
1553 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1554 MVT VT = (MVT::SimpleValueType)i;
1556 // Do not attempt to promote non-512-bit vectors.
1557 if (!VT.is512BitVector())
1560 setOperationAction(ISD::SELECT, VT, Promote);
1561 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1565 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1566 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1567 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1569 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1570 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1572 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1573 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1574 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1575 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1576 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1577 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1578 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1579 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1580 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1581 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1582 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1583 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1584 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1585 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1586 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1587 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1588 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1589 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1590 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1591 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1592 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1593 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1594 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1595 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1596 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1597 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1598 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1599 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1600 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1601 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1602 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1604 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1606 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1607 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1608 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1609 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1610 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1611 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1613 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1614 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1615 if (Subtarget->hasVLX())
1616 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1618 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1619 const MVT VT = (MVT::SimpleValueType)i;
1621 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1623 // Do not attempt to promote non-512-bit vectors.
1624 if (!VT.is512BitVector())
1628 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1629 setOperationAction(ISD::VSELECT, VT, Legal);
1634 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1635 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1636 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1638 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1639 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1640 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1641 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1642 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1644 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1645 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1646 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1647 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1649 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1650 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1651 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1652 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1653 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1654 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1655 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1656 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1658 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1659 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1660 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1661 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1662 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1663 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1664 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1665 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1668 // We want to custom lower some of our intrinsics.
1669 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1670 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1671 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1672 if (!Subtarget->is64Bit())
1673 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1675 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1676 // handle type legalization for these operations here.
1678 // FIXME: We really should do custom legalization for addition and
1679 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1680 // than generic legalization for 64-bit multiplication-with-overflow, though.
1681 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1682 // Add/Sub/Mul with overflow operations are custom lowered.
1684 setOperationAction(ISD::SADDO, VT, Custom);
1685 setOperationAction(ISD::UADDO, VT, Custom);
1686 setOperationAction(ISD::SSUBO, VT, Custom);
1687 setOperationAction(ISD::USUBO, VT, Custom);
1688 setOperationAction(ISD::SMULO, VT, Custom);
1689 setOperationAction(ISD::UMULO, VT, Custom);
1693 if (!Subtarget->is64Bit()) {
1694 // These libcalls are not available in 32-bit.
1695 setLibcallName(RTLIB::SHL_I128, nullptr);
1696 setLibcallName(RTLIB::SRL_I128, nullptr);
1697 setLibcallName(RTLIB::SRA_I128, nullptr);
1700 // Combine sin / cos into one node or libcall if possible.
1701 if (Subtarget->hasSinCos()) {
1702 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1703 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1704 if (Subtarget->isTargetDarwin()) {
1705 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1706 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1707 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1708 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1712 if (Subtarget->isTargetWin64()) {
1713 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1714 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1715 setOperationAction(ISD::SREM, MVT::i128, Custom);
1716 setOperationAction(ISD::UREM, MVT::i128, Custom);
1717 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1718 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1721 // We have target-specific dag combine patterns for the following nodes:
1722 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1723 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1724 setTargetDAGCombine(ISD::BITCAST);
1725 setTargetDAGCombine(ISD::VSELECT);
1726 setTargetDAGCombine(ISD::SELECT);
1727 setTargetDAGCombine(ISD::SHL);
1728 setTargetDAGCombine(ISD::SRA);
1729 setTargetDAGCombine(ISD::SRL);
1730 setTargetDAGCombine(ISD::OR);
1731 setTargetDAGCombine(ISD::AND);
1732 setTargetDAGCombine(ISD::ADD);
1733 setTargetDAGCombine(ISD::FADD);
1734 setTargetDAGCombine(ISD::FSUB);
1735 setTargetDAGCombine(ISD::FMA);
1736 setTargetDAGCombine(ISD::SUB);
1737 setTargetDAGCombine(ISD::LOAD);
1738 setTargetDAGCombine(ISD::MLOAD);
1739 setTargetDAGCombine(ISD::STORE);
1740 setTargetDAGCombine(ISD::MSTORE);
1741 setTargetDAGCombine(ISD::ZERO_EXTEND);
1742 setTargetDAGCombine(ISD::ANY_EXTEND);
1743 setTargetDAGCombine(ISD::SIGN_EXTEND);
1744 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1745 setTargetDAGCombine(ISD::SINT_TO_FP);
1746 setTargetDAGCombine(ISD::UINT_TO_FP);
1747 setTargetDAGCombine(ISD::SETCC);
1748 setTargetDAGCombine(ISD::BUILD_VECTOR);
1749 setTargetDAGCombine(ISD::MUL);
1750 setTargetDAGCombine(ISD::XOR);
1752 computeRegisterProperties(Subtarget->getRegisterInfo());
1754 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1755 MaxStoresPerMemsetOptSize = 8;
1756 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1757 MaxStoresPerMemcpyOptSize = 4;
1758 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1759 MaxStoresPerMemmoveOptSize = 4;
1760 setPrefLoopAlignment(4); // 2^4 bytes.
1762 // Predictable cmov don't hurt on atom because it's in-order.
1763 PredictableSelectIsExpensive = !Subtarget->isAtom();
1764 EnableExtLdPromotion = true;
1765 setPrefFunctionAlignment(4); // 2^4 bytes.
1767 verifyIntrinsicTables();
1770 // This has so far only been implemented for 64-bit MachO.
1771 bool X86TargetLowering::useLoadStackGuardNode() const {
1772 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1775 TargetLoweringBase::LegalizeTypeAction
1776 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1777 if (ExperimentalVectorWideningLegalization &&
1778 VT.getVectorNumElements() != 1 &&
1779 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1780 return TypeWidenVector;
1782 return TargetLoweringBase::getPreferredVectorAction(VT);
1785 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1788 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1790 const unsigned NumElts = VT.getVectorNumElements();
1791 const EVT EltVT = VT.getVectorElementType();
1792 if (VT.is512BitVector()) {
1793 if (Subtarget->hasAVX512())
1794 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1795 EltVT == MVT::f32 || EltVT == MVT::f64)
1797 case 8: return MVT::v8i1;
1798 case 16: return MVT::v16i1;
1800 if (Subtarget->hasBWI())
1801 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1803 case 32: return MVT::v32i1;
1804 case 64: return MVT::v64i1;
1808 if (VT.is256BitVector() || VT.is128BitVector()) {
1809 if (Subtarget->hasVLX())
1810 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1811 EltVT == MVT::f32 || EltVT == MVT::f64)
1813 case 2: return MVT::v2i1;
1814 case 4: return MVT::v4i1;
1815 case 8: return MVT::v8i1;
1817 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1818 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1820 case 8: return MVT::v8i1;
1821 case 16: return MVT::v16i1;
1822 case 32: return MVT::v32i1;
1826 return VT.changeVectorElementTypeToInteger();
1829 /// Helper for getByValTypeAlignment to determine
1830 /// the desired ByVal argument alignment.
1831 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1834 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1835 if (VTy->getBitWidth() == 128)
1837 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1838 unsigned EltAlign = 0;
1839 getMaxByValAlign(ATy->getElementType(), EltAlign);
1840 if (EltAlign > MaxAlign)
1841 MaxAlign = EltAlign;
1842 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1843 for (auto *EltTy : STy->elements()) {
1844 unsigned EltAlign = 0;
1845 getMaxByValAlign(EltTy, EltAlign);
1846 if (EltAlign > MaxAlign)
1847 MaxAlign = EltAlign;
1854 /// Return the desired alignment for ByVal aggregate
1855 /// function arguments in the caller parameter area. For X86, aggregates
1856 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1857 /// are at 4-byte boundaries.
1858 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1859 const DataLayout &DL) const {
1860 if (Subtarget->is64Bit()) {
1861 // Max of 8 and alignment of type.
1862 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1869 if (Subtarget->hasSSE1())
1870 getMaxByValAlign(Ty, Align);
1874 /// Returns the target specific optimal type for load
1875 /// and store operations as a result of memset, memcpy, and memmove
1876 /// lowering. If DstAlign is zero that means it's safe to destination
1877 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1878 /// means there isn't a need to check it against alignment requirement,
1879 /// probably because the source does not need to be loaded. If 'IsMemset' is
1880 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1881 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1882 /// source is constant so it does not need to be loaded.
1883 /// It returns EVT::Other if the type should be determined using generic
1884 /// target-independent logic.
1886 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1887 unsigned DstAlign, unsigned SrcAlign,
1888 bool IsMemset, bool ZeroMemset,
1890 MachineFunction &MF) const {
1891 const Function *F = MF.getFunction();
1892 if ((!IsMemset || ZeroMemset) &&
1893 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1895 (!Subtarget->isUnalignedMem16Slow() ||
1896 ((DstAlign == 0 || DstAlign >= 16) &&
1897 (SrcAlign == 0 || SrcAlign >= 16)))) {
1899 // FIXME: Check if unaligned 32-byte accesses are slow.
1900 if (Subtarget->hasInt256())
1902 if (Subtarget->hasFp256())
1905 if (Subtarget->hasSSE2())
1907 if (Subtarget->hasSSE1())
1909 } else if (!MemcpyStrSrc && Size >= 8 &&
1910 !Subtarget->is64Bit() &&
1911 Subtarget->hasSSE2()) {
1912 // Do not use f64 to lower memcpy if source is string constant. It's
1913 // better to use i32 to avoid the loads.
1917 // This is a compromise. If we reach here, unaligned accesses may be slow on
1918 // this target. However, creating smaller, aligned accesses could be even
1919 // slower and would certainly be a lot more code.
1920 if (Subtarget->is64Bit() && Size >= 8)
1925 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1927 return X86ScalarSSEf32;
1928 else if (VT == MVT::f64)
1929 return X86ScalarSSEf64;
1934 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1939 switch (VT.getSizeInBits()) {
1941 // 8-byte and under are always assumed to be fast.
1945 *Fast = !Subtarget->isUnalignedMem16Slow();
1948 *Fast = !Subtarget->isUnalignedMem32Slow();
1950 // TODO: What about AVX-512 (512-bit) accesses?
1953 // Misaligned accesses of any size are always allowed.
1957 /// Return the entry encoding for a jump table in the
1958 /// current function. The returned value is a member of the
1959 /// MachineJumpTableInfo::JTEntryKind enum.
1960 unsigned X86TargetLowering::getJumpTableEncoding() const {
1961 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1963 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1964 Subtarget->isPICStyleGOT())
1965 return MachineJumpTableInfo::EK_Custom32;
1967 // Otherwise, use the normal jump table encoding heuristics.
1968 return TargetLowering::getJumpTableEncoding();
1971 bool X86TargetLowering::useSoftFloat() const {
1972 return Subtarget->useSoftFloat();
1976 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1977 const MachineBasicBlock *MBB,
1978 unsigned uid,MCContext &Ctx) const{
1979 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1980 Subtarget->isPICStyleGOT());
1981 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1983 return MCSymbolRefExpr::create(MBB->getSymbol(),
1984 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1987 /// Returns relocation base for the given PIC jumptable.
1988 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1989 SelectionDAG &DAG) const {
1990 if (!Subtarget->is64Bit())
1991 // This doesn't have SDLoc associated with it, but is not really the
1992 // same as a Register.
1993 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
1994 getPointerTy(DAG.getDataLayout()));
1998 /// This returns the relocation base for the given PIC jumptable,
1999 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2000 const MCExpr *X86TargetLowering::
2001 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2002 MCContext &Ctx) const {
2003 // X86-64 uses RIP relative addressing based on the jump table label.
2004 if (Subtarget->isPICStyleRIPRel())
2005 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2007 // Otherwise, the reference is relative to the PIC base.
2008 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2011 std::pair<const TargetRegisterClass *, uint8_t>
2012 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2014 const TargetRegisterClass *RRC = nullptr;
2016 switch (VT.SimpleTy) {
2018 return TargetLowering::findRepresentativeClass(TRI, VT);
2019 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2020 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2023 RRC = &X86::VR64RegClass;
2025 case MVT::f32: case MVT::f64:
2026 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2027 case MVT::v4f32: case MVT::v2f64:
2028 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2030 RRC = &X86::VR128RegClass;
2033 return std::make_pair(RRC, Cost);
2036 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2037 unsigned &Offset) const {
2038 if (!Subtarget->isTargetLinux())
2041 if (Subtarget->is64Bit()) {
2042 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2044 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2056 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2057 unsigned DestAS) const {
2058 assert(SrcAS != DestAS && "Expected different address spaces!");
2060 return SrcAS < 256 && DestAS < 256;
2063 //===----------------------------------------------------------------------===//
2064 // Return Value Calling Convention Implementation
2065 //===----------------------------------------------------------------------===//
2067 #include "X86GenCallingConv.inc"
2070 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2071 MachineFunction &MF, bool isVarArg,
2072 const SmallVectorImpl<ISD::OutputArg> &Outs,
2073 LLVMContext &Context) const {
2074 SmallVector<CCValAssign, 16> RVLocs;
2075 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2076 return CCInfo.CheckReturn(Outs, RetCC_X86);
2079 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2080 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2085 X86TargetLowering::LowerReturn(SDValue Chain,
2086 CallingConv::ID CallConv, bool isVarArg,
2087 const SmallVectorImpl<ISD::OutputArg> &Outs,
2088 const SmallVectorImpl<SDValue> &OutVals,
2089 SDLoc dl, SelectionDAG &DAG) const {
2090 MachineFunction &MF = DAG.getMachineFunction();
2091 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2093 SmallVector<CCValAssign, 16> RVLocs;
2094 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2095 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2098 SmallVector<SDValue, 6> RetOps;
2099 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2100 // Operand #1 = Bytes To Pop
2101 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2104 // Copy the result values into the output registers.
2105 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2106 CCValAssign &VA = RVLocs[i];
2107 assert(VA.isRegLoc() && "Can only return in registers!");
2108 SDValue ValToCopy = OutVals[i];
2109 EVT ValVT = ValToCopy.getValueType();
2111 // Promote values to the appropriate types.
2112 if (VA.getLocInfo() == CCValAssign::SExt)
2113 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2114 else if (VA.getLocInfo() == CCValAssign::ZExt)
2115 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2116 else if (VA.getLocInfo() == CCValAssign::AExt) {
2117 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2118 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2120 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2122 else if (VA.getLocInfo() == CCValAssign::BCvt)
2123 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2125 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2126 "Unexpected FP-extend for return value.");
2128 // If this is x86-64, and we disabled SSE, we can't return FP values,
2129 // or SSE or MMX vectors.
2130 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2131 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2132 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2133 report_fatal_error("SSE register return with SSE disabled");
2135 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2136 // llvm-gcc has never done it right and no one has noticed, so this
2137 // should be OK for now.
2138 if (ValVT == MVT::f64 &&
2139 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2140 report_fatal_error("SSE2 register return with SSE2 disabled");
2142 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2143 // the RET instruction and handled by the FP Stackifier.
2144 if (VA.getLocReg() == X86::FP0 ||
2145 VA.getLocReg() == X86::FP1) {
2146 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2147 // change the value to the FP stack register class.
2148 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2149 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2150 RetOps.push_back(ValToCopy);
2151 // Don't emit a copytoreg.
2155 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2156 // which is returned in RAX / RDX.
2157 if (Subtarget->is64Bit()) {
2158 if (ValVT == MVT::x86mmx) {
2159 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2160 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2161 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2163 // If we don't have SSE2 available, convert to v4f32 so the generated
2164 // register is legal.
2165 if (!Subtarget->hasSSE2())
2166 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2171 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2172 Flag = Chain.getValue(1);
2173 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2176 // All x86 ABIs require that for returning structs by value we copy
2177 // the sret argument into %rax/%eax (depending on ABI) for the return.
2178 // We saved the argument into a virtual register in the entry block,
2179 // so now we copy the value out and into %rax/%eax.
2181 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2182 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2183 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2184 // either case FuncInfo->setSRetReturnReg() will have been called.
2185 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2186 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2187 getPointerTy(MF.getDataLayout()));
2190 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2191 X86::RAX : X86::EAX;
2192 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2193 Flag = Chain.getValue(1);
2195 // RAX/EAX now acts like a return value.
2197 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2200 RetOps[0] = Chain; // Update chain.
2202 // Add the flag if we have it.
2204 RetOps.push_back(Flag);
2206 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2209 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2210 if (N->getNumValues() != 1)
2212 if (!N->hasNUsesOfValue(1, 0))
2215 SDValue TCChain = Chain;
2216 SDNode *Copy = *N->use_begin();
2217 if (Copy->getOpcode() == ISD::CopyToReg) {
2218 // If the copy has a glue operand, we conservatively assume it isn't safe to
2219 // perform a tail call.
2220 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2222 TCChain = Copy->getOperand(0);
2223 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2226 bool HasRet = false;
2227 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2229 if (UI->getOpcode() != X86ISD::RET_FLAG)
2231 // If we are returning more than one value, we can definitely
2232 // not make a tail call see PR19530
2233 if (UI->getNumOperands() > 4)
2235 if (UI->getNumOperands() == 4 &&
2236 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2249 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2250 ISD::NodeType ExtendKind) const {
2252 // TODO: Is this also valid on 32-bit?
2253 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2254 ReturnMVT = MVT::i8;
2256 ReturnMVT = MVT::i32;
2258 EVT MinVT = getRegisterType(Context, ReturnMVT);
2259 return VT.bitsLT(MinVT) ? MinVT : VT;
2262 /// Lower the result values of a call into the
2263 /// appropriate copies out of appropriate physical registers.
2266 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2267 CallingConv::ID CallConv, bool isVarArg,
2268 const SmallVectorImpl<ISD::InputArg> &Ins,
2269 SDLoc dl, SelectionDAG &DAG,
2270 SmallVectorImpl<SDValue> &InVals) const {
2272 // Assign locations to each value returned by this call.
2273 SmallVector<CCValAssign, 16> RVLocs;
2274 bool Is64Bit = Subtarget->is64Bit();
2275 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2277 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2279 // Copy all of the result registers out of their specified physreg.
2280 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2281 CCValAssign &VA = RVLocs[i];
2282 EVT CopyVT = VA.getLocVT();
2284 // If this is x86-64, and we disabled SSE, we can't return FP values
2285 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2286 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2287 report_fatal_error("SSE register return with SSE disabled");
2290 // If we prefer to use the value in xmm registers, copy it out as f80 and
2291 // use a truncate to move it from fp stack reg to xmm reg.
2292 bool RoundAfterCopy = false;
2293 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2294 isScalarFPTypeInSSEReg(VA.getValVT())) {
2296 RoundAfterCopy = (CopyVT != VA.getLocVT());
2299 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2300 CopyVT, InFlag).getValue(1);
2301 SDValue Val = Chain.getValue(0);
2304 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2305 // This truncation won't change the value.
2306 DAG.getIntPtrConstant(1, dl));
2308 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2309 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2311 InFlag = Chain.getValue(2);
2312 InVals.push_back(Val);
2318 //===----------------------------------------------------------------------===//
2319 // C & StdCall & Fast Calling Convention implementation
2320 //===----------------------------------------------------------------------===//
2321 // StdCall calling convention seems to be standard for many Windows' API
2322 // routines and around. It differs from C calling convention just a little:
2323 // callee should clean up the stack, not caller. Symbols should be also
2324 // decorated in some fancy way :) It doesn't support any vector arguments.
2325 // For info on fast calling convention see Fast Calling Convention (tail call)
2326 // implementation LowerX86_32FastCCCallTo.
2328 /// CallIsStructReturn - Determines whether a call uses struct return
2330 enum StructReturnType {
2335 static StructReturnType
2336 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2338 return NotStructReturn;
2340 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2341 if (!Flags.isSRet())
2342 return NotStructReturn;
2343 if (Flags.isInReg())
2344 return RegStructReturn;
2345 return StackStructReturn;
2348 /// Determines whether a function uses struct return semantics.
2349 static StructReturnType
2350 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2352 return NotStructReturn;
2354 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2355 if (!Flags.isSRet())
2356 return NotStructReturn;
2357 if (Flags.isInReg())
2358 return RegStructReturn;
2359 return StackStructReturn;
2362 /// Make a copy of an aggregate at address specified by "Src" to address
2363 /// "Dst" with size and alignment information specified by the specific
2364 /// parameter attribute. The copy will be passed as a byval function parameter.
2366 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2367 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2369 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2371 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2372 /*isVolatile*/false, /*AlwaysInline=*/true,
2373 /*isTailCall*/false,
2374 MachinePointerInfo(), MachinePointerInfo());
2377 /// Return true if the calling convention is one that
2378 /// supports tail call optimization.
2379 static bool IsTailCallConvention(CallingConv::ID CC) {
2380 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2381 CC == CallingConv::HiPE);
2384 /// \brief Return true if the calling convention is a C calling convention.
2385 static bool IsCCallConvention(CallingConv::ID CC) {
2386 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2387 CC == CallingConv::X86_64_SysV);
2390 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2392 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2393 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2397 CallingConv::ID CalleeCC = CS.getCallingConv();
2398 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2404 /// Return true if the function is being made into
2405 /// a tailcall target by changing its ABI.
2406 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2407 bool GuaranteedTailCallOpt) {
2408 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2412 X86TargetLowering::LowerMemArgument(SDValue Chain,
2413 CallingConv::ID CallConv,
2414 const SmallVectorImpl<ISD::InputArg> &Ins,
2415 SDLoc dl, SelectionDAG &DAG,
2416 const CCValAssign &VA,
2417 MachineFrameInfo *MFI,
2419 // Create the nodes corresponding to a load from this parameter slot.
2420 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2421 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2422 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2423 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2426 // If value is passed by pointer we have address passed instead of the value
2428 bool ExtendedInMem = VA.isExtInLoc() &&
2429 VA.getValVT().getScalarType() == MVT::i1;
2431 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2432 ValVT = VA.getLocVT();
2434 ValVT = VA.getValVT();
2436 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2437 // changed with more analysis.
2438 // In case of tail call optimization mark all arguments mutable. Since they
2439 // could be overwritten by lowering of arguments in case of a tail call.
2440 if (Flags.isByVal()) {
2441 unsigned Bytes = Flags.getByValSize();
2442 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2443 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2444 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2446 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2447 VA.getLocMemOffset(), isImmutable);
2448 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2449 SDValue Val = DAG.getLoad(
2450 ValVT, dl, Chain, FIN,
2451 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2453 return ExtendedInMem ?
2454 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2458 // FIXME: Get this from tablegen.
2459 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2460 const X86Subtarget *Subtarget) {
2461 assert(Subtarget->is64Bit());
2463 if (Subtarget->isCallingConvWin64(CallConv)) {
2464 static const MCPhysReg GPR64ArgRegsWin64[] = {
2465 X86::RCX, X86::RDX, X86::R8, X86::R9
2467 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2470 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2471 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2473 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2476 // FIXME: Get this from tablegen.
2477 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2478 CallingConv::ID CallConv,
2479 const X86Subtarget *Subtarget) {
2480 assert(Subtarget->is64Bit());
2481 if (Subtarget->isCallingConvWin64(CallConv)) {
2482 // The XMM registers which might contain var arg parameters are shadowed
2483 // in their paired GPR. So we only need to save the GPR to their home
2485 // TODO: __vectorcall will change this.
2489 const Function *Fn = MF.getFunction();
2490 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2491 bool isSoftFloat = Subtarget->useSoftFloat();
2492 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2493 "SSE register cannot be used when SSE is disabled!");
2494 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2495 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2499 static const MCPhysReg XMMArgRegs64Bit[] = {
2500 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2501 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2503 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2507 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2508 CallingConv::ID CallConv,
2510 const SmallVectorImpl<ISD::InputArg> &Ins,
2513 SmallVectorImpl<SDValue> &InVals)
2515 MachineFunction &MF = DAG.getMachineFunction();
2516 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2517 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2519 const Function* Fn = MF.getFunction();
2520 if (Fn->hasExternalLinkage() &&
2521 Subtarget->isTargetCygMing() &&
2522 Fn->getName() == "main")
2523 FuncInfo->setForceFramePointer(true);
2525 MachineFrameInfo *MFI = MF.getFrameInfo();
2526 bool Is64Bit = Subtarget->is64Bit();
2527 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2529 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2530 "Var args not supported with calling convention fastcc, ghc or hipe");
2532 // Assign locations to all of the incoming arguments.
2533 SmallVector<CCValAssign, 16> ArgLocs;
2534 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2536 // Allocate shadow area for Win64
2538 CCInfo.AllocateStack(32, 8);
2540 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2542 unsigned LastVal = ~0U;
2544 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2545 CCValAssign &VA = ArgLocs[i];
2546 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2548 assert(VA.getValNo() != LastVal &&
2549 "Don't support value assigned to multiple locs yet");
2551 LastVal = VA.getValNo();
2553 if (VA.isRegLoc()) {
2554 EVT RegVT = VA.getLocVT();
2555 const TargetRegisterClass *RC;
2556 if (RegVT == MVT::i32)
2557 RC = &X86::GR32RegClass;
2558 else if (Is64Bit && RegVT == MVT::i64)
2559 RC = &X86::GR64RegClass;
2560 else if (RegVT == MVT::f32)
2561 RC = &X86::FR32RegClass;
2562 else if (RegVT == MVT::f64)
2563 RC = &X86::FR64RegClass;
2564 else if (RegVT.is512BitVector())
2565 RC = &X86::VR512RegClass;
2566 else if (RegVT.is256BitVector())
2567 RC = &X86::VR256RegClass;
2568 else if (RegVT.is128BitVector())
2569 RC = &X86::VR128RegClass;
2570 else if (RegVT == MVT::x86mmx)
2571 RC = &X86::VR64RegClass;
2572 else if (RegVT == MVT::i1)
2573 RC = &X86::VK1RegClass;
2574 else if (RegVT == MVT::v8i1)
2575 RC = &X86::VK8RegClass;
2576 else if (RegVT == MVT::v16i1)
2577 RC = &X86::VK16RegClass;
2578 else if (RegVT == MVT::v32i1)
2579 RC = &X86::VK32RegClass;
2580 else if (RegVT == MVT::v64i1)
2581 RC = &X86::VK64RegClass;
2583 llvm_unreachable("Unknown argument type!");
2585 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2586 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2588 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2589 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2591 if (VA.getLocInfo() == CCValAssign::SExt)
2592 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2593 DAG.getValueType(VA.getValVT()));
2594 else if (VA.getLocInfo() == CCValAssign::ZExt)
2595 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2596 DAG.getValueType(VA.getValVT()));
2597 else if (VA.getLocInfo() == CCValAssign::BCvt)
2598 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2600 if (VA.isExtInLoc()) {
2601 // Handle MMX values passed in XMM regs.
2602 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2603 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2605 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2608 assert(VA.isMemLoc());
2609 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2612 // If value is passed via pointer - do a load.
2613 if (VA.getLocInfo() == CCValAssign::Indirect)
2614 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2615 MachinePointerInfo(), false, false, false, 0);
2617 InVals.push_back(ArgValue);
2620 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2621 // All x86 ABIs require that for returning structs by value we copy the
2622 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2623 // the argument into a virtual register so that we can access it from the
2625 if (Ins[i].Flags.isSRet()) {
2626 unsigned Reg = FuncInfo->getSRetReturnReg();
2628 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2629 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2630 FuncInfo->setSRetReturnReg(Reg);
2632 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2633 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2638 unsigned StackSize = CCInfo.getNextStackOffset();
2639 // Align stack specially for tail calls.
2640 if (FuncIsMadeTailCallSafe(CallConv,
2641 MF.getTarget().Options.GuaranteedTailCallOpt))
2642 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2644 // If the function takes variable number of arguments, make a frame index for
2645 // the start of the first vararg value... for expansion of llvm.va_start. We
2646 // can skip this if there are no va_start calls.
2647 if (MFI->hasVAStart() &&
2648 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2649 CallConv != CallingConv::X86_ThisCall))) {
2650 FuncInfo->setVarArgsFrameIndex(
2651 MFI->CreateFixedObject(1, StackSize, true));
2654 MachineModuleInfo &MMI = MF.getMMI();
2655 const Function *WinEHParent = nullptr;
2656 if (MMI.hasWinEHFuncInfo(Fn))
2657 WinEHParent = MMI.getWinEHParent(Fn);
2658 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2659 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2661 // Figure out if XMM registers are in use.
2662 assert(!(Subtarget->useSoftFloat() &&
2663 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2664 "SSE register cannot be used when SSE is disabled!");
2666 // 64-bit calling conventions support varargs and register parameters, so we
2667 // have to do extra work to spill them in the prologue.
2668 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2669 // Find the first unallocated argument registers.
2670 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2671 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2672 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2673 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2674 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2675 "SSE register cannot be used when SSE is disabled!");
2677 // Gather all the live in physical registers.
2678 SmallVector<SDValue, 6> LiveGPRs;
2679 SmallVector<SDValue, 8> LiveXMMRegs;
2681 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2682 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2684 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2686 if (!ArgXMMs.empty()) {
2687 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2688 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2689 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2690 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2691 LiveXMMRegs.push_back(
2692 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2697 // Get to the caller-allocated home save location. Add 8 to account
2698 // for the return address.
2699 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2700 FuncInfo->setRegSaveFrameIndex(
2701 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2702 // Fixup to set vararg frame on shadow area (4 x i64).
2704 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2706 // For X86-64, if there are vararg parameters that are passed via
2707 // registers, then we must store them to their spots on the stack so
2708 // they may be loaded by deferencing the result of va_next.
2709 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2710 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2711 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2712 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2715 // Store the integer parameter registers.
2716 SmallVector<SDValue, 8> MemOps;
2717 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2718 getPointerTy(DAG.getDataLayout()));
2719 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2720 for (SDValue Val : LiveGPRs) {
2721 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2722 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2724 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2725 MachinePointerInfo::getFixedStack(
2726 DAG.getMachineFunction(),
2727 FuncInfo->getRegSaveFrameIndex(), Offset),
2729 MemOps.push_back(Store);
2733 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2734 // Now store the XMM (fp + vector) parameter registers.
2735 SmallVector<SDValue, 12> SaveXMMOps;
2736 SaveXMMOps.push_back(Chain);
2737 SaveXMMOps.push_back(ALVal);
2738 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2739 FuncInfo->getRegSaveFrameIndex(), dl));
2740 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2741 FuncInfo->getVarArgsFPOffset(), dl));
2742 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2744 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2745 MVT::Other, SaveXMMOps));
2748 if (!MemOps.empty())
2749 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2750 } else if (IsWin64 && IsWinEHOutlined) {
2751 // Get to the caller-allocated home save location. Add 8 to account
2752 // for the return address.
2753 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2754 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2755 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2757 MMI.getWinEHFuncInfo(Fn)
2758 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2759 FuncInfo->getRegSaveFrameIndex();
2761 // Store the second integer parameter (rdx) into rsp+16 relative to the
2762 // stack pointer at the entry of the function.
2763 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2764 getPointerTy(DAG.getDataLayout()));
2765 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2766 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2767 Chain = DAG.getStore(
2768 Val.getValue(1), dl, Val, RSFIN,
2769 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(),
2770 FuncInfo->getRegSaveFrameIndex()),
2771 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2774 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2775 // Find the largest legal vector type.
2776 MVT VecVT = MVT::Other;
2777 // FIXME: Only some x86_32 calling conventions support AVX512.
2778 if (Subtarget->hasAVX512() &&
2779 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2780 CallConv == CallingConv::Intel_OCL_BI)))
2781 VecVT = MVT::v16f32;
2782 else if (Subtarget->hasAVX())
2784 else if (Subtarget->hasSSE2())
2787 // We forward some GPRs and some vector types.
2788 SmallVector<MVT, 2> RegParmTypes;
2789 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2790 RegParmTypes.push_back(IntVT);
2791 if (VecVT != MVT::Other)
2792 RegParmTypes.push_back(VecVT);
2794 // Compute the set of forwarded registers. The rest are scratch.
2795 SmallVectorImpl<ForwardedRegister> &Forwards =
2796 FuncInfo->getForwardedMustTailRegParms();
2797 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2799 // Conservatively forward AL on x86_64, since it might be used for varargs.
2800 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2801 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2802 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2805 // Copy all forwards from physical to virtual registers.
2806 for (ForwardedRegister &F : Forwards) {
2807 // FIXME: Can we use a less constrained schedule?
2808 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2809 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2810 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2814 // Some CCs need callee pop.
2815 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2816 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2817 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2819 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2820 // If this is an sret function, the return should pop the hidden pointer.
2821 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2822 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2823 argsAreStructReturn(Ins) == StackStructReturn)
2824 FuncInfo->setBytesToPopOnReturn(4);
2828 // RegSaveFrameIndex is X86-64 only.
2829 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2830 if (CallConv == CallingConv::X86_FastCall ||
2831 CallConv == CallingConv::X86_ThisCall)
2832 // fastcc functions can't have varargs.
2833 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2836 FuncInfo->setArgumentStackSize(StackSize);
2838 if (IsWinEHParent) {
2840 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2841 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2842 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2843 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2844 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2845 MachinePointerInfo::getFixedStack(
2846 DAG.getMachineFunction(), UnwindHelpFI),
2847 /*isVolatile=*/true,
2848 /*isNonTemporal=*/false, /*Alignment=*/0);
2850 // Functions using Win32 EH are considered to have opaque SP adjustments
2851 // to force local variables to be addressed from the frame or base
2853 MFI->setHasOpaqueSPAdjustment(true);
2861 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2862 SDValue StackPtr, SDValue Arg,
2863 SDLoc dl, SelectionDAG &DAG,
2864 const CCValAssign &VA,
2865 ISD::ArgFlagsTy Flags) const {
2866 unsigned LocMemOffset = VA.getLocMemOffset();
2867 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2868 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2870 if (Flags.isByVal())
2871 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2873 return DAG.getStore(
2874 Chain, dl, Arg, PtrOff,
2875 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2879 /// Emit a load of return address if tail call
2880 /// optimization is performed and it is required.
2882 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2883 SDValue &OutRetAddr, SDValue Chain,
2884 bool IsTailCall, bool Is64Bit,
2885 int FPDiff, SDLoc dl) const {
2886 // Adjust the Return address stack slot.
2887 EVT VT = getPointerTy(DAG.getDataLayout());
2888 OutRetAddr = getReturnAddressFrameIndex(DAG);
2890 // Load the "old" Return address.
2891 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2892 false, false, false, 0);
2893 return SDValue(OutRetAddr.getNode(), 1);
2896 /// Emit a store of the return address if tail call
2897 /// optimization is performed and it is required (FPDiff!=0).
2898 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2899 SDValue Chain, SDValue RetAddrFrIdx,
2900 EVT PtrVT, unsigned SlotSize,
2901 int FPDiff, SDLoc dl) {
2902 // Store the return address to the appropriate stack slot.
2903 if (!FPDiff) return Chain;
2904 // Calculate the new stack slot for the return address.
2905 int NewReturnAddrFI =
2906 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2908 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2909 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2910 MachinePointerInfo::getFixedStack(
2911 DAG.getMachineFunction(), NewReturnAddrFI),
2916 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2917 /// operation of specified width.
2918 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2920 unsigned NumElems = VT.getVectorNumElements();
2921 SmallVector<int, 8> Mask;
2922 Mask.push_back(NumElems);
2923 for (unsigned i = 1; i != NumElems; ++i)
2925 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2929 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2930 SmallVectorImpl<SDValue> &InVals) const {
2931 SelectionDAG &DAG = CLI.DAG;
2933 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2934 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2935 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2936 SDValue Chain = CLI.Chain;
2937 SDValue Callee = CLI.Callee;
2938 CallingConv::ID CallConv = CLI.CallConv;
2939 bool &isTailCall = CLI.IsTailCall;
2940 bool isVarArg = CLI.IsVarArg;
2942 MachineFunction &MF = DAG.getMachineFunction();
2943 bool Is64Bit = Subtarget->is64Bit();
2944 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2945 StructReturnType SR = callIsStructReturn(Outs);
2946 bool IsSibcall = false;
2947 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2948 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2950 if (Attr.getValueAsString() == "true")
2953 if (Subtarget->isPICStyleGOT() &&
2954 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2955 // If we are using a GOT, disable tail calls to external symbols with
2956 // default visibility. Tail calling such a symbol requires using a GOT
2957 // relocation, which forces early binding of the symbol. This breaks code
2958 // that require lazy function symbol resolution. Using musttail or
2959 // GuaranteedTailCallOpt will override this.
2960 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2961 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2962 G->getGlobal()->hasDefaultVisibility()))
2966 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2968 // Force this to be a tail call. The verifier rules are enough to ensure
2969 // that we can lower this successfully without moving the return address
2972 } else if (isTailCall) {
2973 // Check if it's really possible to do a tail call.
2974 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2975 isVarArg, SR != NotStructReturn,
2976 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2977 Outs, OutVals, Ins, DAG);
2979 // Sibcalls are automatically detected tailcalls which do not require
2981 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2988 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2989 "Var args not supported with calling convention fastcc, ghc or hipe");
2991 // Analyze operands of the call, assigning locations to each operand.
2992 SmallVector<CCValAssign, 16> ArgLocs;
2993 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2995 // Allocate shadow area for Win64
2997 CCInfo.AllocateStack(32, 8);
2999 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3001 // Get a count of how many bytes are to be pushed on the stack.
3002 unsigned NumBytes = CCInfo.getNextStackOffset();
3004 // This is a sibcall. The memory operands are available in caller's
3005 // own caller's stack.
3007 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3008 IsTailCallConvention(CallConv))
3009 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3012 if (isTailCall && !IsSibcall && !IsMustTail) {
3013 // Lower arguments at fp - stackoffset + fpdiff.
3014 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3016 FPDiff = NumBytesCallerPushed - NumBytes;
3018 // Set the delta of movement of the returnaddr stackslot.
3019 // But only set if delta is greater than previous delta.
3020 if (FPDiff < X86Info->getTCReturnAddrDelta())
3021 X86Info->setTCReturnAddrDelta(FPDiff);
3024 unsigned NumBytesToPush = NumBytes;
3025 unsigned NumBytesToPop = NumBytes;
3027 // If we have an inalloca argument, all stack space has already been allocated
3028 // for us and be right at the top of the stack. We don't support multiple
3029 // arguments passed in memory when using inalloca.
3030 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3032 if (!ArgLocs.back().isMemLoc())
3033 report_fatal_error("cannot use inalloca attribute on a register "
3035 if (ArgLocs.back().getLocMemOffset() != 0)
3036 report_fatal_error("any parameter with the inalloca attribute must be "
3037 "the only memory argument");
3041 Chain = DAG.getCALLSEQ_START(
3042 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3044 SDValue RetAddrFrIdx;
3045 // Load return address for tail calls.
3046 if (isTailCall && FPDiff)
3047 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3048 Is64Bit, FPDiff, dl);
3050 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3051 SmallVector<SDValue, 8> MemOpChains;
3054 // Walk the register/memloc assignments, inserting copies/loads. In the case
3055 // of tail call optimization arguments are handle later.
3056 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3057 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3058 // Skip inalloca arguments, they have already been written.
3059 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3060 if (Flags.isInAlloca())
3063 CCValAssign &VA = ArgLocs[i];
3064 EVT RegVT = VA.getLocVT();
3065 SDValue Arg = OutVals[i];
3066 bool isByVal = Flags.isByVal();
3068 // Promote the value if needed.
3069 switch (VA.getLocInfo()) {
3070 default: llvm_unreachable("Unknown loc info!");
3071 case CCValAssign::Full: break;
3072 case CCValAssign::SExt:
3073 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3075 case CCValAssign::ZExt:
3076 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3078 case CCValAssign::AExt:
3079 if (Arg.getValueType().isVector() &&
3080 Arg.getValueType().getScalarType() == MVT::i1)
3081 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3082 else if (RegVT.is128BitVector()) {
3083 // Special case: passing MMX values in XMM registers.
3084 Arg = DAG.getBitcast(MVT::i64, Arg);
3085 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3086 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3088 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3090 case CCValAssign::BCvt:
3091 Arg = DAG.getBitcast(RegVT, Arg);
3093 case CCValAssign::Indirect: {
3094 // Store the argument.
3095 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3096 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3097 Chain = DAG.getStore(
3098 Chain, dl, Arg, SpillSlot,
3099 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3106 if (VA.isRegLoc()) {
3107 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3108 if (isVarArg && IsWin64) {
3109 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3110 // shadow reg if callee is a varargs function.
3111 unsigned ShadowReg = 0;
3112 switch (VA.getLocReg()) {
3113 case X86::XMM0: ShadowReg = X86::RCX; break;
3114 case X86::XMM1: ShadowReg = X86::RDX; break;
3115 case X86::XMM2: ShadowReg = X86::R8; break;
3116 case X86::XMM3: ShadowReg = X86::R9; break;
3119 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3121 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3122 assert(VA.isMemLoc());
3123 if (!StackPtr.getNode())
3124 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3125 getPointerTy(DAG.getDataLayout()));
3126 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3127 dl, DAG, VA, Flags));
3131 if (!MemOpChains.empty())
3132 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3134 if (Subtarget->isPICStyleGOT()) {
3135 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3138 RegsToPass.push_back(std::make_pair(
3139 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3140 getPointerTy(DAG.getDataLayout()))));
3142 // If we are tail calling and generating PIC/GOT style code load the
3143 // address of the callee into ECX. The value in ecx is used as target of
3144 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3145 // for tail calls on PIC/GOT architectures. Normally we would just put the
3146 // address of GOT into ebx and then call target@PLT. But for tail calls
3147 // ebx would be restored (since ebx is callee saved) before jumping to the
3150 // Note: The actual moving to ECX is done further down.
3151 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3152 if (G && !G->getGlobal()->hasLocalLinkage() &&
3153 G->getGlobal()->hasDefaultVisibility())
3154 Callee = LowerGlobalAddress(Callee, DAG);
3155 else if (isa<ExternalSymbolSDNode>(Callee))
3156 Callee = LowerExternalSymbol(Callee, DAG);
3160 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3161 // From AMD64 ABI document:
3162 // For calls that may call functions that use varargs or stdargs
3163 // (prototype-less calls or calls to functions containing ellipsis (...) in
3164 // the declaration) %al is used as hidden argument to specify the number
3165 // of SSE registers used. The contents of %al do not need to match exactly
3166 // the number of registers, but must be an ubound on the number of SSE
3167 // registers used and is in the range 0 - 8 inclusive.
3169 // Count the number of XMM registers allocated.
3170 static const MCPhysReg XMMArgRegs[] = {
3171 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3172 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3174 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3175 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3176 && "SSE registers cannot be used when SSE is disabled");
3178 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3179 DAG.getConstant(NumXMMRegs, dl,
3183 if (isVarArg && IsMustTail) {
3184 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3185 for (const auto &F : Forwards) {
3186 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3187 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3191 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3192 // don't need this because the eligibility check rejects calls that require
3193 // shuffling arguments passed in memory.
3194 if (!IsSibcall && isTailCall) {
3195 // Force all the incoming stack arguments to be loaded from the stack
3196 // before any new outgoing arguments are stored to the stack, because the
3197 // outgoing stack slots may alias the incoming argument stack slots, and
3198 // the alias isn't otherwise explicit. This is slightly more conservative
3199 // than necessary, because it means that each store effectively depends
3200 // on every argument instead of just those arguments it would clobber.
3201 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3203 SmallVector<SDValue, 8> MemOpChains2;
3206 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3207 CCValAssign &VA = ArgLocs[i];
3210 assert(VA.isMemLoc());
3211 SDValue Arg = OutVals[i];
3212 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3213 // Skip inalloca arguments. They don't require any work.
3214 if (Flags.isInAlloca())
3216 // Create frame index.
3217 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3218 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3219 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3220 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3222 if (Flags.isByVal()) {
3223 // Copy relative to framepointer.
3224 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3225 if (!StackPtr.getNode())
3226 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3227 getPointerTy(DAG.getDataLayout()));
3228 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3231 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3235 // Store relative to framepointer.
3236 MemOpChains2.push_back(DAG.getStore(
3237 ArgChain, dl, Arg, FIN,
3238 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3243 if (!MemOpChains2.empty())
3244 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3246 // Store the return address to the appropriate stack slot.
3247 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3248 getPointerTy(DAG.getDataLayout()),
3249 RegInfo->getSlotSize(), FPDiff, dl);
3252 // Build a sequence of copy-to-reg nodes chained together with token chain
3253 // and flag operands which copy the outgoing args into registers.
3255 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3256 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3257 RegsToPass[i].second, InFlag);
3258 InFlag = Chain.getValue(1);
3261 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3262 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3263 // In the 64-bit large code model, we have to make all calls
3264 // through a register, since the call instruction's 32-bit
3265 // pc-relative offset may not be large enough to hold the whole
3267 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3268 // If the callee is a GlobalAddress node (quite common, every direct call
3269 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3271 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3273 // We should use extra load for direct calls to dllimported functions in
3275 const GlobalValue *GV = G->getGlobal();
3276 if (!GV->hasDLLImportStorageClass()) {
3277 unsigned char OpFlags = 0;
3278 bool ExtraLoad = false;
3279 unsigned WrapperKind = ISD::DELETED_NODE;
3281 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3282 // external symbols most go through the PLT in PIC mode. If the symbol
3283 // has hidden or protected visibility, or if it is static or local, then
3284 // we don't need to use the PLT - we can directly call it.
3285 if (Subtarget->isTargetELF() &&
3286 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3287 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3288 OpFlags = X86II::MO_PLT;
3289 } else if (Subtarget->isPICStyleStubAny() &&
3290 !GV->isStrongDefinitionForLinker() &&
3291 (!Subtarget->getTargetTriple().isMacOSX() ||
3292 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3293 // PC-relative references to external symbols should go through $stub,
3294 // unless we're building with the leopard linker or later, which
3295 // automatically synthesizes these stubs.
3296 OpFlags = X86II::MO_DARWIN_STUB;
3297 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3298 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3299 // If the function is marked as non-lazy, generate an indirect call
3300 // which loads from the GOT directly. This avoids runtime overhead
3301 // at the cost of eager binding (and one extra byte of encoding).
3302 OpFlags = X86II::MO_GOTPCREL;
3303 WrapperKind = X86ISD::WrapperRIP;
3307 Callee = DAG.getTargetGlobalAddress(
3308 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3310 // Add a wrapper if needed.
3311 if (WrapperKind != ISD::DELETED_NODE)
3312 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3313 getPointerTy(DAG.getDataLayout()), Callee);
3314 // Add extra indirection if needed.
3316 Callee = DAG.getLoad(
3317 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3318 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3321 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3322 unsigned char OpFlags = 0;
3324 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3325 // external symbols should go through the PLT.
3326 if (Subtarget->isTargetELF() &&
3327 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3328 OpFlags = X86II::MO_PLT;
3329 } else if (Subtarget->isPICStyleStubAny() &&
3330 (!Subtarget->getTargetTriple().isMacOSX() ||
3331 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3332 // PC-relative references to external symbols should go through $stub,
3333 // unless we're building with the leopard linker or later, which
3334 // automatically synthesizes these stubs.
3335 OpFlags = X86II::MO_DARWIN_STUB;
3338 Callee = DAG.getTargetExternalSymbol(
3339 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3340 } else if (Subtarget->isTarget64BitILP32() &&
3341 Callee->getValueType(0) == MVT::i32) {
3342 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3343 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3346 // Returns a chain & a flag for retval copy to use.
3347 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3348 SmallVector<SDValue, 8> Ops;
3350 if (!IsSibcall && isTailCall) {
3351 Chain = DAG.getCALLSEQ_END(Chain,
3352 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3353 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3354 InFlag = Chain.getValue(1);
3357 Ops.push_back(Chain);
3358 Ops.push_back(Callee);
3361 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3363 // Add argument registers to the end of the list so that they are known live
3365 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3366 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3367 RegsToPass[i].second.getValueType()));
3369 // Add a register mask operand representing the call-preserved registers.
3370 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3371 assert(Mask && "Missing call preserved mask for calling convention");
3373 // If this is an invoke in a 32-bit function using an MSVC personality, assume
3374 // the function clobbers all registers. If an exception is thrown, the runtime
3375 // will not restore CSRs.
3376 // FIXME: Model this more precisely so that we can register allocate across
3377 // the normal edge and spill and fill across the exceptional edge.
3378 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3379 const Function *CallerFn = MF.getFunction();
3380 EHPersonality Pers =
3381 CallerFn->hasPersonalityFn()
3382 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3383 : EHPersonality::Unknown;
3384 if (isMSVCEHPersonality(Pers))
3385 Mask = RegInfo->getNoPreservedMask();
3388 Ops.push_back(DAG.getRegisterMask(Mask));
3390 if (InFlag.getNode())
3391 Ops.push_back(InFlag);
3395 //// If this is the first return lowered for this function, add the regs
3396 //// to the liveout set for the function.
3397 // This isn't right, although it's probably harmless on x86; liveouts
3398 // should be computed from returns not tail calls. Consider a void
3399 // function making a tail call to a function returning int.
3400 MF.getFrameInfo()->setHasTailCall();
3401 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3404 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3405 InFlag = Chain.getValue(1);
3407 // Create the CALLSEQ_END node.
3408 unsigned NumBytesForCalleeToPop;
3409 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3410 DAG.getTarget().Options.GuaranteedTailCallOpt))
3411 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3412 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3413 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3414 SR == StackStructReturn)
3415 // If this is a call to a struct-return function, the callee
3416 // pops the hidden struct pointer, so we have to push it back.
3417 // This is common for Darwin/X86, Linux & Mingw32 targets.
3418 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3419 NumBytesForCalleeToPop = 4;
3421 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3423 // Returns a flag for retval copy to use.
3425 Chain = DAG.getCALLSEQ_END(Chain,
3426 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3427 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3430 InFlag = Chain.getValue(1);
3433 // Handle result values, copying them out of physregs into vregs that we
3435 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3436 Ins, dl, DAG, InVals);
3439 //===----------------------------------------------------------------------===//
3440 // Fast Calling Convention (tail call) implementation
3441 //===----------------------------------------------------------------------===//
3443 // Like std call, callee cleans arguments, convention except that ECX is
3444 // reserved for storing the tail called function address. Only 2 registers are
3445 // free for argument passing (inreg). Tail call optimization is performed
3447 // * tailcallopt is enabled
3448 // * caller/callee are fastcc
3449 // On X86_64 architecture with GOT-style position independent code only local
3450 // (within module) calls are supported at the moment.
3451 // To keep the stack aligned according to platform abi the function
3452 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3453 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3454 // If a tail called function callee has more arguments than the caller the
3455 // caller needs to make sure that there is room to move the RETADDR to. This is
3456 // achieved by reserving an area the size of the argument delta right after the
3457 // original RETADDR, but before the saved framepointer or the spilled registers
3458 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3470 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3473 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3474 SelectionDAG& DAG) const {
3475 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3476 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3477 unsigned StackAlignment = TFI.getStackAlignment();
3478 uint64_t AlignMask = StackAlignment - 1;
3479 int64_t Offset = StackSize;
3480 unsigned SlotSize = RegInfo->getSlotSize();
3481 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3482 // Number smaller than 12 so just add the difference.
3483 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3485 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3486 Offset = ((~AlignMask) & Offset) + StackAlignment +
3487 (StackAlignment-SlotSize);
3492 /// Return true if the given stack call argument is already available in the
3493 /// same position (relatively) of the caller's incoming argument stack.
3495 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3496 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3497 const X86InstrInfo *TII) {
3498 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3500 if (Arg.getOpcode() == ISD::CopyFromReg) {
3501 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3502 if (!TargetRegisterInfo::isVirtualRegister(VR))
3504 MachineInstr *Def = MRI->getVRegDef(VR);
3507 if (!Flags.isByVal()) {
3508 if (!TII->isLoadFromStackSlot(Def, FI))
3511 unsigned Opcode = Def->getOpcode();
3512 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3513 Opcode == X86::LEA64_32r) &&
3514 Def->getOperand(1).isFI()) {
3515 FI = Def->getOperand(1).getIndex();
3516 Bytes = Flags.getByValSize();
3520 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3521 if (Flags.isByVal())
3522 // ByVal argument is passed in as a pointer but it's now being
3523 // dereferenced. e.g.
3524 // define @foo(%struct.X* %A) {
3525 // tail call @bar(%struct.X* byval %A)
3528 SDValue Ptr = Ld->getBasePtr();
3529 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3532 FI = FINode->getIndex();
3533 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3534 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3535 FI = FINode->getIndex();
3536 Bytes = Flags.getByValSize();
3540 assert(FI != INT_MAX);
3541 if (!MFI->isFixedObjectIndex(FI))
3543 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3546 /// Check whether the call is eligible for tail call optimization. Targets
3547 /// that want to do tail call optimization should implement this function.
3549 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3550 CallingConv::ID CalleeCC,
3552 bool isCalleeStructRet,
3553 bool isCallerStructRet,
3555 const SmallVectorImpl<ISD::OutputArg> &Outs,
3556 const SmallVectorImpl<SDValue> &OutVals,
3557 const SmallVectorImpl<ISD::InputArg> &Ins,
3558 SelectionDAG &DAG) const {
3559 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3562 // If -tailcallopt is specified, make fastcc functions tail-callable.
3563 const MachineFunction &MF = DAG.getMachineFunction();
3564 const Function *CallerF = MF.getFunction();
3566 // If the function return type is x86_fp80 and the callee return type is not,
3567 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3568 // perform a tailcall optimization here.
3569 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3572 CallingConv::ID CallerCC = CallerF->getCallingConv();
3573 bool CCMatch = CallerCC == CalleeCC;
3574 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3575 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3577 // Win64 functions have extra shadow space for argument homing. Don't do the
3578 // sibcall if the caller and callee have mismatched expectations for this
3580 if (IsCalleeWin64 != IsCallerWin64)
3583 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3584 if (IsTailCallConvention(CalleeCC) && CCMatch)
3589 // Look for obvious safe cases to perform tail call optimization that do not
3590 // require ABI changes. This is what gcc calls sibcall.
3592 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3593 // emit a special epilogue.
3594 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3595 if (RegInfo->needsStackRealignment(MF))
3598 // Also avoid sibcall optimization if either caller or callee uses struct
3599 // return semantics.
3600 if (isCalleeStructRet || isCallerStructRet)
3603 // An stdcall/thiscall caller is expected to clean up its arguments; the
3604 // callee isn't going to do that.
3605 // FIXME: this is more restrictive than needed. We could produce a tailcall
3606 // when the stack adjustment matches. For example, with a thiscall that takes
3607 // only one argument.
3608 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3609 CallerCC == CallingConv::X86_ThisCall))
3612 // Do not sibcall optimize vararg calls unless all arguments are passed via
3614 if (isVarArg && !Outs.empty()) {
3616 // Optimizing for varargs on Win64 is unlikely to be safe without
3617 // additional testing.
3618 if (IsCalleeWin64 || IsCallerWin64)
3621 SmallVector<CCValAssign, 16> ArgLocs;
3622 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3625 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3626 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3627 if (!ArgLocs[i].isRegLoc())
3631 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3632 // stack. Therefore, if it's not used by the call it is not safe to optimize
3633 // this into a sibcall.
3634 bool Unused = false;
3635 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3642 SmallVector<CCValAssign, 16> RVLocs;
3643 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3645 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3646 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3647 CCValAssign &VA = RVLocs[i];
3648 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3653 // If the calling conventions do not match, then we'd better make sure the
3654 // results are returned in the same way as what the caller expects.
3656 SmallVector<CCValAssign, 16> RVLocs1;
3657 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3659 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3661 SmallVector<CCValAssign, 16> RVLocs2;
3662 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3664 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3666 if (RVLocs1.size() != RVLocs2.size())
3668 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3669 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3671 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3673 if (RVLocs1[i].isRegLoc()) {
3674 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3677 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3683 // If the callee takes no arguments then go on to check the results of the
3685 if (!Outs.empty()) {
3686 // Check if stack adjustment is needed. For now, do not do this if any
3687 // argument is passed on the stack.
3688 SmallVector<CCValAssign, 16> ArgLocs;
3689 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3692 // Allocate shadow area for Win64
3694 CCInfo.AllocateStack(32, 8);
3696 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3697 if (CCInfo.getNextStackOffset()) {
3698 MachineFunction &MF = DAG.getMachineFunction();
3699 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3702 // Check if the arguments are already laid out in the right way as
3703 // the caller's fixed stack objects.
3704 MachineFrameInfo *MFI = MF.getFrameInfo();
3705 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3706 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3707 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3708 CCValAssign &VA = ArgLocs[i];
3709 SDValue Arg = OutVals[i];
3710 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3711 if (VA.getLocInfo() == CCValAssign::Indirect)
3713 if (!VA.isRegLoc()) {
3714 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3721 // If the tailcall address may be in a register, then make sure it's
3722 // possible to register allocate for it. In 32-bit, the call address can
3723 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3724 // callee-saved registers are restored. These happen to be the same
3725 // registers used to pass 'inreg' arguments so watch out for those.
3726 if (!Subtarget->is64Bit() &&
3727 ((!isa<GlobalAddressSDNode>(Callee) &&
3728 !isa<ExternalSymbolSDNode>(Callee)) ||
3729 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3730 unsigned NumInRegs = 0;
3731 // In PIC we need an extra register to formulate the address computation
3733 unsigned MaxInRegs =
3734 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3736 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3737 CCValAssign &VA = ArgLocs[i];
3740 unsigned Reg = VA.getLocReg();
3743 case X86::EAX: case X86::EDX: case X86::ECX:
3744 if (++NumInRegs == MaxInRegs)
3756 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3757 const TargetLibraryInfo *libInfo) const {
3758 return X86::createFastISel(funcInfo, libInfo);
3761 //===----------------------------------------------------------------------===//
3762 // Other Lowering Hooks
3763 //===----------------------------------------------------------------------===//
3765 static bool MayFoldLoad(SDValue Op) {
3766 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3769 static bool MayFoldIntoStore(SDValue Op) {
3770 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3773 static bool isTargetShuffle(unsigned Opcode) {
3775 default: return false;
3776 case X86ISD::BLENDI:
3777 case X86ISD::PSHUFB:
3778 case X86ISD::PSHUFD:
3779 case X86ISD::PSHUFHW:
3780 case X86ISD::PSHUFLW:
3782 case X86ISD::PALIGNR:
3783 case X86ISD::MOVLHPS:
3784 case X86ISD::MOVLHPD:
3785 case X86ISD::MOVHLPS:
3786 case X86ISD::MOVLPS:
3787 case X86ISD::MOVLPD:
3788 case X86ISD::MOVSHDUP:
3789 case X86ISD::MOVSLDUP:
3790 case X86ISD::MOVDDUP:
3793 case X86ISD::UNPCKL:
3794 case X86ISD::UNPCKH:
3795 case X86ISD::VPERMILPI:
3796 case X86ISD::VPERM2X128:
3797 case X86ISD::VPERMI:
3798 case X86ISD::VPERMV:
3799 case X86ISD::VPERMV3:
3804 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3805 SDValue V1, unsigned TargetMask,
3806 SelectionDAG &DAG) {
3808 default: llvm_unreachable("Unknown x86 shuffle node");
3809 case X86ISD::PSHUFD:
3810 case X86ISD::PSHUFHW:
3811 case X86ISD::PSHUFLW:
3812 case X86ISD::VPERMILPI:
3813 case X86ISD::VPERMI:
3814 return DAG.getNode(Opc, dl, VT, V1,
3815 DAG.getConstant(TargetMask, dl, MVT::i8));
3819 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3820 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3822 default: llvm_unreachable("Unknown x86 shuffle node");
3823 case X86ISD::MOVLHPS:
3824 case X86ISD::MOVLHPD:
3825 case X86ISD::MOVHLPS:
3826 case X86ISD::MOVLPS:
3827 case X86ISD::MOVLPD:
3830 case X86ISD::UNPCKL:
3831 case X86ISD::UNPCKH:
3832 return DAG.getNode(Opc, dl, VT, V1, V2);
3836 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3837 MachineFunction &MF = DAG.getMachineFunction();
3838 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3839 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3840 int ReturnAddrIndex = FuncInfo->getRAIndex();
3842 if (ReturnAddrIndex == 0) {
3843 // Set up a frame object for the return address.
3844 unsigned SlotSize = RegInfo->getSlotSize();
3845 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3848 FuncInfo->setRAIndex(ReturnAddrIndex);
3851 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3854 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3855 bool hasSymbolicDisplacement) {
3856 // Offset should fit into 32 bit immediate field.
3857 if (!isInt<32>(Offset))
3860 // If we don't have a symbolic displacement - we don't have any extra
3862 if (!hasSymbolicDisplacement)
3865 // FIXME: Some tweaks might be needed for medium code model.
3866 if (M != CodeModel::Small && M != CodeModel::Kernel)
3869 // For small code model we assume that latest object is 16MB before end of 31
3870 // bits boundary. We may also accept pretty large negative constants knowing
3871 // that all objects are in the positive half of address space.
3872 if (M == CodeModel::Small && Offset < 16*1024*1024)
3875 // For kernel code model we know that all object resist in the negative half
3876 // of 32bits address space. We may not accept negative offsets, since they may
3877 // be just off and we may accept pretty large positive ones.
3878 if (M == CodeModel::Kernel && Offset >= 0)
3884 /// Determines whether the callee is required to pop its own arguments.
3885 /// Callee pop is necessary to support tail calls.
3886 bool X86::isCalleePop(CallingConv::ID CallingConv,
3887 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3888 switch (CallingConv) {
3891 case CallingConv::X86_StdCall:
3892 case CallingConv::X86_FastCall:
3893 case CallingConv::X86_ThisCall:
3895 case CallingConv::Fast:
3896 case CallingConv::GHC:
3897 case CallingConv::HiPE:
3904 /// \brief Return true if the condition is an unsigned comparison operation.
3905 static bool isX86CCUnsigned(unsigned X86CC) {
3907 default: llvm_unreachable("Invalid integer condition!");
3908 case X86::COND_E: return true;
3909 case X86::COND_G: return false;
3910 case X86::COND_GE: return false;
3911 case X86::COND_L: return false;
3912 case X86::COND_LE: return false;
3913 case X86::COND_NE: return true;
3914 case X86::COND_B: return true;
3915 case X86::COND_A: return true;
3916 case X86::COND_BE: return true;
3917 case X86::COND_AE: return true;
3919 llvm_unreachable("covered switch fell through?!");
3922 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3923 /// condition code, returning the condition code and the LHS/RHS of the
3924 /// comparison to make.
3925 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3926 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3928 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3929 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3930 // X > -1 -> X == 0, jump !sign.
3931 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3932 return X86::COND_NS;
3934 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3935 // X < 0 -> X == 0, jump on sign.
3938 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3940 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3941 return X86::COND_LE;
3945 switch (SetCCOpcode) {
3946 default: llvm_unreachable("Invalid integer condition!");
3947 case ISD::SETEQ: return X86::COND_E;
3948 case ISD::SETGT: return X86::COND_G;
3949 case ISD::SETGE: return X86::COND_GE;
3950 case ISD::SETLT: return X86::COND_L;
3951 case ISD::SETLE: return X86::COND_LE;
3952 case ISD::SETNE: return X86::COND_NE;
3953 case ISD::SETULT: return X86::COND_B;
3954 case ISD::SETUGT: return X86::COND_A;
3955 case ISD::SETULE: return X86::COND_BE;
3956 case ISD::SETUGE: return X86::COND_AE;
3960 // First determine if it is required or is profitable to flip the operands.
3962 // If LHS is a foldable load, but RHS is not, flip the condition.
3963 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3964 !ISD::isNON_EXTLoad(RHS.getNode())) {
3965 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3966 std::swap(LHS, RHS);
3969 switch (SetCCOpcode) {
3975 std::swap(LHS, RHS);
3979 // On a floating point condition, the flags are set as follows:
3981 // 0 | 0 | 0 | X > Y
3982 // 0 | 0 | 1 | X < Y
3983 // 1 | 0 | 0 | X == Y
3984 // 1 | 1 | 1 | unordered
3985 switch (SetCCOpcode) {
3986 default: llvm_unreachable("Condcode should be pre-legalized away");
3988 case ISD::SETEQ: return X86::COND_E;
3989 case ISD::SETOLT: // flipped
3991 case ISD::SETGT: return X86::COND_A;
3992 case ISD::SETOLE: // flipped
3994 case ISD::SETGE: return X86::COND_AE;
3995 case ISD::SETUGT: // flipped
3997 case ISD::SETLT: return X86::COND_B;
3998 case ISD::SETUGE: // flipped
4000 case ISD::SETLE: return X86::COND_BE;
4002 case ISD::SETNE: return X86::COND_NE;
4003 case ISD::SETUO: return X86::COND_P;
4004 case ISD::SETO: return X86::COND_NP;
4006 case ISD::SETUNE: return X86::COND_INVALID;
4010 /// Is there a floating point cmov for the specific X86 condition code?
4011 /// Current x86 isa includes the following FP cmov instructions:
4012 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4013 static bool hasFPCMov(unsigned X86CC) {
4029 /// Returns true if the target can instruction select the
4030 /// specified FP immediate natively. If false, the legalizer will
4031 /// materialize the FP immediate as a load from a constant pool.
4032 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4033 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4034 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4040 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4041 ISD::LoadExtType ExtTy,
4043 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4044 // relocation target a movq or addq instruction: don't let the load shrink.
4045 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4046 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4047 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4048 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4052 /// \brief Returns true if it is beneficial to convert a load of a constant
4053 /// to just the constant itself.
4054 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4056 assert(Ty->isIntegerTy());
4058 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4059 if (BitSize == 0 || BitSize > 64)
4064 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4065 unsigned Index) const {
4066 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4069 return (Index == 0 || Index == ResVT.getVectorNumElements());
4072 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4073 // Speculate cttz only if we can directly use TZCNT.
4074 return Subtarget->hasBMI();
4077 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4078 // Speculate ctlz only if we can directly use LZCNT.
4079 return Subtarget->hasLZCNT();
4082 /// Return true if every element in Mask, beginning
4083 /// from position Pos and ending in Pos+Size is undef.
4084 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4085 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4091 /// Return true if Val is undef or if its value falls within the
4092 /// specified range (L, H].
4093 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4094 return (Val < 0) || (Val >= Low && Val < Hi);
4097 /// Val is either less than zero (undef) or equal to the specified value.
4098 static bool isUndefOrEqual(int Val, int CmpVal) {
4099 return (Val < 0 || Val == CmpVal);
4102 /// Return true if every element in Mask, beginning
4103 /// from position Pos and ending in Pos+Size, falls within the specified
4104 /// sequential range (Low, Low+Size]. or is undef.
4105 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4106 unsigned Pos, unsigned Size, int Low) {
4107 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4108 if (!isUndefOrEqual(Mask[i], Low))
4113 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4114 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4115 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4116 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4117 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4120 // The index should be aligned on a vecWidth-bit boundary.
4122 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4124 MVT VT = N->getSimpleValueType(0);
4125 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4126 bool Result = (Index * ElSize) % vecWidth == 0;
4131 /// Return true if the specified INSERT_SUBVECTOR
4132 /// operand specifies a subvector insert that is suitable for input to
4133 /// insertion of 128 or 256-bit subvectors
4134 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4135 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4136 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4138 // The index should be aligned on a vecWidth-bit boundary.
4140 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4142 MVT VT = N->getSimpleValueType(0);
4143 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4144 bool Result = (Index * ElSize) % vecWidth == 0;
4149 bool X86::isVINSERT128Index(SDNode *N) {
4150 return isVINSERTIndex(N, 128);
4153 bool X86::isVINSERT256Index(SDNode *N) {
4154 return isVINSERTIndex(N, 256);
4157 bool X86::isVEXTRACT128Index(SDNode *N) {
4158 return isVEXTRACTIndex(N, 128);
4161 bool X86::isVEXTRACT256Index(SDNode *N) {
4162 return isVEXTRACTIndex(N, 256);
4165 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4166 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4167 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4168 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4171 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4173 MVT VecVT = N->getOperand(0).getSimpleValueType();
4174 MVT ElVT = VecVT.getVectorElementType();
4176 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4177 return Index / NumElemsPerChunk;
4180 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4181 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4182 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4183 llvm_unreachable("Illegal insert subvector for VINSERT");
4186 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4188 MVT VecVT = N->getSimpleValueType(0);
4189 MVT ElVT = VecVT.getVectorElementType();
4191 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4192 return Index / NumElemsPerChunk;
4195 /// Return the appropriate immediate to extract the specified
4196 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4197 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4198 return getExtractVEXTRACTImmediate(N, 128);
4201 /// Return the appropriate immediate to extract the specified
4202 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4203 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4204 return getExtractVEXTRACTImmediate(N, 256);
4207 /// Return the appropriate immediate to insert at the specified
4208 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4209 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4210 return getInsertVINSERTImmediate(N, 128);
4213 /// Return the appropriate immediate to insert at the specified
4214 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4215 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4216 return getInsertVINSERTImmediate(N, 256);
4219 /// Returns true if Elt is a constant integer zero
4220 static bool isZero(SDValue V) {
4221 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4222 return C && C->isNullValue();
4225 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4226 bool X86::isZeroNode(SDValue Elt) {
4229 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4230 return CFP->getValueAPF().isPosZero();
4234 /// Returns a vector of specified type with all zero elements.
4235 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4236 SelectionDAG &DAG, SDLoc dl) {
4237 assert(VT.isVector() && "Expected a vector type");
4239 // Always build SSE zero vectors as <4 x i32> bitcasted
4240 // to their dest type. This ensures they get CSE'd.
4242 if (VT.is128BitVector()) { // SSE
4243 if (Subtarget->hasSSE2()) { // SSE2
4244 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4245 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4247 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4248 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4250 } else if (VT.is256BitVector()) { // AVX
4251 if (Subtarget->hasInt256()) { // AVX2
4252 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4253 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4254 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4256 // 256-bit logic and arithmetic instructions in AVX are all
4257 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4258 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4259 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4260 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4262 } else if (VT.is512BitVector()) { // AVX-512
4263 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4264 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4265 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4266 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4267 } else if (VT.getScalarType() == MVT::i1) {
4269 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4270 && "Unexpected vector type");
4271 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4272 && "Unexpected vector type");
4273 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4274 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4275 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4277 llvm_unreachable("Unexpected vector type");
4279 return DAG.getBitcast(VT, Vec);
4282 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4283 SelectionDAG &DAG, SDLoc dl,
4284 unsigned vectorWidth) {
4285 assert((vectorWidth == 128 || vectorWidth == 256) &&
4286 "Unsupported vector width");
4287 EVT VT = Vec.getValueType();
4288 EVT ElVT = VT.getVectorElementType();
4289 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4290 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4291 VT.getVectorNumElements()/Factor);
4293 // Extract from UNDEF is UNDEF.
4294 if (Vec.getOpcode() == ISD::UNDEF)
4295 return DAG.getUNDEF(ResultVT);
4297 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4298 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4300 // This is the index of the first element of the vectorWidth-bit chunk
4302 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4305 // If the input is a buildvector just emit a smaller one.
4306 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4307 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4308 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4311 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4312 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4315 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4316 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4317 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4318 /// instructions or a simple subregister reference. Idx is an index in the
4319 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4320 /// lowering EXTRACT_VECTOR_ELT operations easier.
4321 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4322 SelectionDAG &DAG, SDLoc dl) {
4323 assert((Vec.getValueType().is256BitVector() ||
4324 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4325 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4328 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4329 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4330 SelectionDAG &DAG, SDLoc dl) {
4331 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4332 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4335 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4336 unsigned IdxVal, SelectionDAG &DAG,
4337 SDLoc dl, unsigned vectorWidth) {
4338 assert((vectorWidth == 128 || vectorWidth == 256) &&
4339 "Unsupported vector width");
4340 // Inserting UNDEF is Result
4341 if (Vec.getOpcode() == ISD::UNDEF)
4343 EVT VT = Vec.getValueType();
4344 EVT ElVT = VT.getVectorElementType();
4345 EVT ResultVT = Result.getValueType();
4347 // Insert the relevant vectorWidth bits.
4348 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4350 // This is the index of the first element of the vectorWidth-bit chunk
4352 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4355 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4356 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4359 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4360 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4361 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4362 /// simple superregister reference. Idx is an index in the 128 bits
4363 /// we want. It need not be aligned to a 128-bit boundary. That makes
4364 /// lowering INSERT_VECTOR_ELT operations easier.
4365 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4366 SelectionDAG &DAG, SDLoc dl) {
4367 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4369 // For insertion into the zero index (low half) of a 256-bit vector, it is
4370 // more efficient to generate a blend with immediate instead of an insert*128.
4371 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4372 // extend the subvector to the size of the result vector. Make sure that
4373 // we are not recursing on that node by checking for undef here.
4374 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4375 Result.getOpcode() != ISD::UNDEF) {
4376 EVT ResultVT = Result.getValueType();
4377 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4378 SDValue Undef = DAG.getUNDEF(ResultVT);
4379 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4382 // The blend instruction, and therefore its mask, depend on the data type.
4383 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4384 if (ScalarType.isFloatingPoint()) {
4385 // Choose either vblendps (float) or vblendpd (double).
4386 unsigned ScalarSize = ScalarType.getSizeInBits();
4387 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4388 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4389 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4390 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4393 const X86Subtarget &Subtarget =
4394 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4396 // AVX2 is needed for 256-bit integer blend support.
4397 // Integers must be cast to 32-bit because there is only vpblendd;
4398 // vpblendw can't be used for this because it has a handicapped mask.
4400 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4401 // is still more efficient than using the wrong domain vinsertf128 that
4402 // will be created by InsertSubVector().
4403 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4405 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4406 Vec256 = DAG.getBitcast(CastVT, Vec256);
4407 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4408 return DAG.getBitcast(ResultVT, Vec256);
4411 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4414 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4415 SelectionDAG &DAG, SDLoc dl) {
4416 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4417 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4420 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4421 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4422 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4423 /// large BUILD_VECTORS.
4424 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4425 unsigned NumElems, SelectionDAG &DAG,
4427 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4428 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4431 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4432 unsigned NumElems, SelectionDAG &DAG,
4434 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4435 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4438 /// Returns a vector of specified type with all bits set.
4439 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4440 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4441 /// Then bitcast to their original type, ensuring they get CSE'd.
4442 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4444 assert(VT.isVector() && "Expected a vector type");
4446 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4448 if (VT.is256BitVector()) {
4449 if (HasInt256) { // AVX2
4450 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4451 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4453 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4454 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4456 } else if (VT.is128BitVector()) {
4457 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4459 llvm_unreachable("Unexpected vector type");
4461 return DAG.getBitcast(VT, Vec);
4464 /// Returns a vector_shuffle node for an unpackl operation.
4465 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4467 unsigned NumElems = VT.getVectorNumElements();
4468 SmallVector<int, 8> Mask;
4469 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4471 Mask.push_back(i + NumElems);
4473 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4476 /// Returns a vector_shuffle node for an unpackh operation.
4477 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4479 unsigned NumElems = VT.getVectorNumElements();
4480 SmallVector<int, 8> Mask;
4481 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4482 Mask.push_back(i + Half);
4483 Mask.push_back(i + NumElems + Half);
4485 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4488 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4489 /// This produces a shuffle where the low element of V2 is swizzled into the
4490 /// zero/undef vector, landing at element Idx.
4491 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4492 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4494 const X86Subtarget *Subtarget,
4495 SelectionDAG &DAG) {
4496 MVT VT = V2.getSimpleValueType();
4498 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4499 unsigned NumElems = VT.getVectorNumElements();
4500 SmallVector<int, 16> MaskVec;
4501 for (unsigned i = 0; i != NumElems; ++i)
4502 // If this is the insertion idx, put the low elt of V2 here.
4503 MaskVec.push_back(i == Idx ? NumElems : i);
4504 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4507 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4508 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4509 /// uses one source. Note that this will set IsUnary for shuffles which use a
4510 /// single input multiple times, and in those cases it will
4511 /// adjust the mask to only have indices within that single input.
4512 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4513 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4514 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4515 unsigned NumElems = VT.getVectorNumElements();
4519 bool IsFakeUnary = false;
4520 switch(N->getOpcode()) {
4521 case X86ISD::BLENDI:
4522 ImmN = N->getOperand(N->getNumOperands()-1);
4523 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4526 ImmN = N->getOperand(N->getNumOperands()-1);
4527 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4528 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4530 case X86ISD::UNPCKH:
4531 DecodeUNPCKHMask(VT, Mask);
4532 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4534 case X86ISD::UNPCKL:
4535 DecodeUNPCKLMask(VT, Mask);
4536 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4538 case X86ISD::MOVHLPS:
4539 DecodeMOVHLPSMask(NumElems, Mask);
4540 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4542 case X86ISD::MOVLHPS:
4543 DecodeMOVLHPSMask(NumElems, Mask);
4544 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4546 case X86ISD::PALIGNR:
4547 ImmN = N->getOperand(N->getNumOperands()-1);
4548 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4550 case X86ISD::PSHUFD:
4551 case X86ISD::VPERMILPI:
4552 ImmN = N->getOperand(N->getNumOperands()-1);
4553 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4556 case X86ISD::PSHUFHW:
4557 ImmN = N->getOperand(N->getNumOperands()-1);
4558 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4561 case X86ISD::PSHUFLW:
4562 ImmN = N->getOperand(N->getNumOperands()-1);
4563 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4566 case X86ISD::PSHUFB: {
4568 SDValue MaskNode = N->getOperand(1);
4569 while (MaskNode->getOpcode() == ISD::BITCAST)
4570 MaskNode = MaskNode->getOperand(0);
4572 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4573 // If we have a build-vector, then things are easy.
4574 EVT VT = MaskNode.getValueType();
4575 assert(VT.isVector() &&
4576 "Can't produce a non-vector with a build_vector!");
4577 if (!VT.isInteger())
4580 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4582 SmallVector<uint64_t, 32> RawMask;
4583 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4584 SDValue Op = MaskNode->getOperand(i);
4585 if (Op->getOpcode() == ISD::UNDEF) {
4586 RawMask.push_back((uint64_t)SM_SentinelUndef);
4589 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4592 APInt MaskElement = CN->getAPIntValue();
4594 // We now have to decode the element which could be any integer size and
4595 // extract each byte of it.
4596 for (int j = 0; j < NumBytesPerElement; ++j) {
4597 // Note that this is x86 and so always little endian: the low byte is
4598 // the first byte of the mask.
4599 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4600 MaskElement = MaskElement.lshr(8);
4603 DecodePSHUFBMask(RawMask, Mask);
4607 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4611 SDValue Ptr = MaskLoad->getBasePtr();
4612 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4613 Ptr->getOpcode() == X86ISD::WrapperRIP)
4614 Ptr = Ptr->getOperand(0);
4616 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4617 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4620 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4621 DecodePSHUFBMask(C, Mask);
4629 case X86ISD::VPERMI:
4630 ImmN = N->getOperand(N->getNumOperands()-1);
4631 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4636 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4638 case X86ISD::VPERM2X128:
4639 ImmN = N->getOperand(N->getNumOperands()-1);
4640 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4641 if (Mask.empty()) return false;
4642 // Mask only contains negative index if an element is zero.
4643 if (std::any_of(Mask.begin(), Mask.end(),
4644 [](int M){ return M == SM_SentinelZero; }))
4647 case X86ISD::MOVSLDUP:
4648 DecodeMOVSLDUPMask(VT, Mask);
4651 case X86ISD::MOVSHDUP:
4652 DecodeMOVSHDUPMask(VT, Mask);
4655 case X86ISD::MOVDDUP:
4656 DecodeMOVDDUPMask(VT, Mask);
4659 case X86ISD::MOVLHPD:
4660 case X86ISD::MOVLPD:
4661 case X86ISD::MOVLPS:
4662 // Not yet implemented
4664 case X86ISD::VPERMV: {
4666 SDValue MaskNode = N->getOperand(0);
4667 while (MaskNode->getOpcode() == ISD::BITCAST)
4668 MaskNode = MaskNode->getOperand(0);
4670 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4671 SmallVector<uint64_t, 32> RawMask;
4672 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4673 // If we have a build-vector, then things are easy.
4674 assert(MaskNode.getValueType().isInteger() &&
4675 MaskNode.getValueType().getVectorNumElements() ==
4676 VT.getVectorNumElements());
4678 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4679 SDValue Op = MaskNode->getOperand(i);
4680 if (Op->getOpcode() == ISD::UNDEF)
4681 RawMask.push_back((uint64_t)SM_SentinelUndef);
4682 else if (isa<ConstantSDNode>(Op)) {
4683 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4684 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4688 DecodeVPERMVMask(RawMask, Mask);
4691 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4692 unsigned NumEltsInMask = MaskNode->getNumOperands();
4693 MaskNode = MaskNode->getOperand(0);
4694 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4696 APInt MaskEltValue = CN->getAPIntValue();
4697 for (unsigned i = 0; i < NumEltsInMask; ++i)
4698 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4699 DecodeVPERMVMask(RawMask, Mask);
4702 // It may be a scalar load
4705 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4709 SDValue Ptr = MaskLoad->getBasePtr();
4710 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4711 Ptr->getOpcode() == X86ISD::WrapperRIP)
4712 Ptr = Ptr->getOperand(0);
4714 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4715 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4718 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4720 DecodeVPERMVMask(C, VT, Mask);
4727 case X86ISD::VPERMV3: {
4729 SDValue MaskNode = N->getOperand(1);
4730 while (MaskNode->getOpcode() == ISD::BITCAST)
4731 MaskNode = MaskNode->getOperand(1);
4733 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4734 // If we have a build-vector, then things are easy.
4735 assert(MaskNode.getValueType().isInteger() &&
4736 MaskNode.getValueType().getVectorNumElements() ==
4737 VT.getVectorNumElements());
4739 SmallVector<uint64_t, 32> RawMask;
4740 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4742 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4743 SDValue Op = MaskNode->getOperand(i);
4744 if (Op->getOpcode() == ISD::UNDEF)
4745 RawMask.push_back((uint64_t)SM_SentinelUndef);
4747 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4750 APInt MaskElement = CN->getAPIntValue();
4751 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4754 DecodeVPERMV3Mask(RawMask, Mask);
4758 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4762 SDValue Ptr = MaskLoad->getBasePtr();
4763 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4764 Ptr->getOpcode() == X86ISD::WrapperRIP)
4765 Ptr = Ptr->getOperand(0);
4767 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4768 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4771 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4773 DecodeVPERMV3Mask(C, VT, Mask);
4780 default: llvm_unreachable("unknown target shuffle node");
4783 // If we have a fake unary shuffle, the shuffle mask is spread across two
4784 // inputs that are actually the same node. Re-map the mask to always point
4785 // into the first input.
4788 if (M >= (int)Mask.size())
4794 /// Returns the scalar element that will make up the ith
4795 /// element of the result of the vector shuffle.
4796 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4799 return SDValue(); // Limit search depth.
4801 SDValue V = SDValue(N, 0);
4802 EVT VT = V.getValueType();
4803 unsigned Opcode = V.getOpcode();
4805 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4806 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4807 int Elt = SV->getMaskElt(Index);
4810 return DAG.getUNDEF(VT.getVectorElementType());
4812 unsigned NumElems = VT.getVectorNumElements();
4813 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4814 : SV->getOperand(1);
4815 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4818 // Recurse into target specific vector shuffles to find scalars.
4819 if (isTargetShuffle(Opcode)) {
4820 MVT ShufVT = V.getSimpleValueType();
4821 unsigned NumElems = ShufVT.getVectorNumElements();
4822 SmallVector<int, 16> ShuffleMask;
4825 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4828 int Elt = ShuffleMask[Index];
4830 return DAG.getUNDEF(ShufVT.getVectorElementType());
4832 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4834 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4838 // Actual nodes that may contain scalar elements
4839 if (Opcode == ISD::BITCAST) {
4840 V = V.getOperand(0);
4841 EVT SrcVT = V.getValueType();
4842 unsigned NumElems = VT.getVectorNumElements();
4844 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4848 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4849 return (Index == 0) ? V.getOperand(0)
4850 : DAG.getUNDEF(VT.getVectorElementType());
4852 if (V.getOpcode() == ISD::BUILD_VECTOR)
4853 return V.getOperand(Index);
4858 /// Custom lower build_vector of v16i8.
4859 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4860 unsigned NumNonZero, unsigned NumZero,
4862 const X86Subtarget* Subtarget,
4863 const TargetLowering &TLI) {
4871 // SSE4.1 - use PINSRB to insert each byte directly.
4872 if (Subtarget->hasSSE41()) {
4873 for (unsigned i = 0; i < 16; ++i) {
4874 bool isNonZero = (NonZeros & (1 << i)) != 0;
4878 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4880 V = DAG.getUNDEF(MVT::v16i8);
4883 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4884 MVT::v16i8, V, Op.getOperand(i),
4885 DAG.getIntPtrConstant(i, dl));
4892 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4893 for (unsigned i = 0; i < 16; ++i) {
4894 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4895 if (ThisIsNonZero && First) {
4897 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4899 V = DAG.getUNDEF(MVT::v8i16);
4904 SDValue ThisElt, LastElt;
4905 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4906 if (LastIsNonZero) {
4907 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4908 MVT::i16, Op.getOperand(i-1));
4910 if (ThisIsNonZero) {
4911 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4912 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4913 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4915 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4919 if (ThisElt.getNode())
4920 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4921 DAG.getIntPtrConstant(i/2, dl));
4925 return DAG.getBitcast(MVT::v16i8, V);
4928 /// Custom lower build_vector of v8i16.
4929 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4930 unsigned NumNonZero, unsigned NumZero,
4932 const X86Subtarget* Subtarget,
4933 const TargetLowering &TLI) {
4940 for (unsigned i = 0; i < 8; ++i) {
4941 bool isNonZero = (NonZeros & (1 << i)) != 0;
4945 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4947 V = DAG.getUNDEF(MVT::v8i16);
4950 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4951 MVT::v8i16, V, Op.getOperand(i),
4952 DAG.getIntPtrConstant(i, dl));
4959 /// Custom lower build_vector of v4i32 or v4f32.
4960 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4961 const X86Subtarget *Subtarget,
4962 const TargetLowering &TLI) {
4963 // Find all zeroable elements.
4964 std::bitset<4> Zeroable;
4965 for (int i=0; i < 4; ++i) {
4966 SDValue Elt = Op->getOperand(i);
4967 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4969 assert(Zeroable.size() - Zeroable.count() > 1 &&
4970 "We expect at least two non-zero elements!");
4972 // We only know how to deal with build_vector nodes where elements are either
4973 // zeroable or extract_vector_elt with constant index.
4974 SDValue FirstNonZero;
4975 unsigned FirstNonZeroIdx;
4976 for (unsigned i=0; i < 4; ++i) {
4979 SDValue Elt = Op->getOperand(i);
4980 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4981 !isa<ConstantSDNode>(Elt.getOperand(1)))
4983 // Make sure that this node is extracting from a 128-bit vector.
4984 MVT VT = Elt.getOperand(0).getSimpleValueType();
4985 if (!VT.is128BitVector())
4987 if (!FirstNonZero.getNode()) {
4989 FirstNonZeroIdx = i;
4993 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4994 SDValue V1 = FirstNonZero.getOperand(0);
4995 MVT VT = V1.getSimpleValueType();
4997 // See if this build_vector can be lowered as a blend with zero.
4999 unsigned EltMaskIdx, EltIdx;
5001 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5002 if (Zeroable[EltIdx]) {
5003 // The zero vector will be on the right hand side.
5004 Mask[EltIdx] = EltIdx+4;
5008 Elt = Op->getOperand(EltIdx);
5009 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5010 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5011 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5013 Mask[EltIdx] = EltIdx;
5017 // Let the shuffle legalizer deal with blend operations.
5018 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5019 if (V1.getSimpleValueType() != VT)
5020 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5021 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5024 // See if we can lower this build_vector to a INSERTPS.
5025 if (!Subtarget->hasSSE41())
5028 SDValue V2 = Elt.getOperand(0);
5029 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5032 bool CanFold = true;
5033 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5037 SDValue Current = Op->getOperand(i);
5038 SDValue SrcVector = Current->getOperand(0);
5041 CanFold = SrcVector == V1 &&
5042 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5048 assert(V1.getNode() && "Expected at least two non-zero elements!");
5049 if (V1.getSimpleValueType() != MVT::v4f32)
5050 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5051 if (V2.getSimpleValueType() != MVT::v4f32)
5052 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5054 // Ok, we can emit an INSERTPS instruction.
5055 unsigned ZMask = Zeroable.to_ulong();
5057 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5058 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5060 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5061 DAG.getIntPtrConstant(InsertPSMask, DL));
5062 return DAG.getBitcast(VT, Result);
5065 /// Return a vector logical shift node.
5066 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5067 unsigned NumBits, SelectionDAG &DAG,
5068 const TargetLowering &TLI, SDLoc dl) {
5069 assert(VT.is128BitVector() && "Unknown type for VShift");
5070 MVT ShVT = MVT::v2i64;
5071 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5072 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5073 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5074 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5075 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5076 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5080 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5082 // Check if the scalar load can be widened into a vector load. And if
5083 // the address is "base + cst" see if the cst can be "absorbed" into
5084 // the shuffle mask.
5085 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5086 SDValue Ptr = LD->getBasePtr();
5087 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5089 EVT PVT = LD->getValueType(0);
5090 if (PVT != MVT::i32 && PVT != MVT::f32)
5095 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5096 FI = FINode->getIndex();
5098 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5099 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5100 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5101 Offset = Ptr.getConstantOperandVal(1);
5102 Ptr = Ptr.getOperand(0);
5107 // FIXME: 256-bit vector instructions don't require a strict alignment,
5108 // improve this code to support it better.
5109 unsigned RequiredAlign = VT.getSizeInBits()/8;
5110 SDValue Chain = LD->getChain();
5111 // Make sure the stack object alignment is at least 16 or 32.
5112 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5113 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5114 if (MFI->isFixedObjectIndex(FI)) {
5115 // Can't change the alignment. FIXME: It's possible to compute
5116 // the exact stack offset and reference FI + adjust offset instead.
5117 // If someone *really* cares about this. That's the way to implement it.
5120 MFI->setObjectAlignment(FI, RequiredAlign);
5124 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5125 // Ptr + (Offset & ~15).
5128 if ((Offset % RequiredAlign) & 3)
5130 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5133 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5134 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5137 int EltNo = (Offset - StartOffset) >> 2;
5138 unsigned NumElems = VT.getVectorNumElements();
5140 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5141 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5142 LD->getPointerInfo().getWithOffset(StartOffset),
5143 false, false, false, 0);
5145 SmallVector<int, 8> Mask(NumElems, EltNo);
5147 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5153 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5154 /// elements can be replaced by a single large load which has the same value as
5155 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5157 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5159 /// FIXME: we'd also like to handle the case where the last elements are zero
5160 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5161 /// There's even a handy isZeroNode for that purpose.
5162 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5163 SDLoc &DL, SelectionDAG &DAG,
5164 bool isAfterLegalize) {
5165 unsigned NumElems = Elts.size();
5167 LoadSDNode *LDBase = nullptr;
5168 unsigned LastLoadedElt = -1U;
5170 // For each element in the initializer, see if we've found a load or an undef.
5171 // If we don't find an initial load element, or later load elements are
5172 // non-consecutive, bail out.
5173 for (unsigned i = 0; i < NumElems; ++i) {
5174 SDValue Elt = Elts[i];
5175 // Look through a bitcast.
5176 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5177 Elt = Elt.getOperand(0);
5178 if (!Elt.getNode() ||
5179 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5182 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5184 LDBase = cast<LoadSDNode>(Elt.getNode());
5188 if (Elt.getOpcode() == ISD::UNDEF)
5191 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5192 EVT LdVT = Elt.getValueType();
5193 // Each loaded element must be the correct fractional portion of the
5194 // requested vector load.
5195 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5197 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5202 // If we have found an entire vector of loads and undefs, then return a large
5203 // load of the entire vector width starting at the base pointer. If we found
5204 // consecutive loads for the low half, generate a vzext_load node.
5205 if (LastLoadedElt == NumElems - 1) {
5206 assert(LDBase && "Did not find base load for merging consecutive loads");
5207 EVT EltVT = LDBase->getValueType(0);
5208 // Ensure that the input vector size for the merged loads matches the
5209 // cumulative size of the input elements.
5210 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5213 if (isAfterLegalize &&
5214 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5217 SDValue NewLd = SDValue();
5219 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5220 LDBase->getPointerInfo(), LDBase->isVolatile(),
5221 LDBase->isNonTemporal(), LDBase->isInvariant(),
5222 LDBase->getAlignment());
5224 if (LDBase->hasAnyUseOfValue(1)) {
5225 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5227 SDValue(NewLd.getNode(), 1));
5228 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5229 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5230 SDValue(NewLd.getNode(), 1));
5236 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5237 //of a v4i32 / v4f32. It's probably worth generalizing.
5238 EVT EltVT = VT.getVectorElementType();
5239 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5240 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5241 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5242 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5244 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5245 LDBase->getPointerInfo(),
5246 LDBase->getAlignment(),
5247 false/*isVolatile*/, true/*ReadMem*/,
5250 // Make sure the newly-created LOAD is in the same position as LDBase in
5251 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5252 // update uses of LDBase's output chain to use the TokenFactor.
5253 if (LDBase->hasAnyUseOfValue(1)) {
5254 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5255 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5256 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5257 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5258 SDValue(ResNode.getNode(), 1));
5261 return DAG.getBitcast(VT, ResNode);
5266 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5267 /// to generate a splat value for the following cases:
5268 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5269 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5270 /// a scalar load, or a constant.
5271 /// The VBROADCAST node is returned when a pattern is found,
5272 /// or SDValue() otherwise.
5273 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5274 SelectionDAG &DAG) {
5275 // VBROADCAST requires AVX.
5276 // TODO: Splats could be generated for non-AVX CPUs using SSE
5277 // instructions, but there's less potential gain for only 128-bit vectors.
5278 if (!Subtarget->hasAVX())
5281 MVT VT = Op.getSimpleValueType();
5284 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5285 "Unsupported vector type for broadcast.");
5290 switch (Op.getOpcode()) {
5292 // Unknown pattern found.
5295 case ISD::BUILD_VECTOR: {
5296 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5297 BitVector UndefElements;
5298 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5300 // We need a splat of a single value to use broadcast, and it doesn't
5301 // make any sense if the value is only in one element of the vector.
5302 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5306 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5307 Ld.getOpcode() == ISD::ConstantFP);
5309 // Make sure that all of the users of a non-constant load are from the
5310 // BUILD_VECTOR node.
5311 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5316 case ISD::VECTOR_SHUFFLE: {
5317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5319 // Shuffles must have a splat mask where the first element is
5321 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5324 SDValue Sc = Op.getOperand(0);
5325 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5326 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5328 if (!Subtarget->hasInt256())
5331 // Use the register form of the broadcast instruction available on AVX2.
5332 if (VT.getSizeInBits() >= 256)
5333 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5334 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5337 Ld = Sc.getOperand(0);
5338 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5339 Ld.getOpcode() == ISD::ConstantFP);
5341 // The scalar_to_vector node and the suspected
5342 // load node must have exactly one user.
5343 // Constants may have multiple users.
5345 // AVX-512 has register version of the broadcast
5346 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5347 Ld.getValueType().getSizeInBits() >= 32;
5348 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5355 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5356 bool IsGE256 = (VT.getSizeInBits() >= 256);
5358 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5359 // instruction to save 8 or more bytes of constant pool data.
5360 // TODO: If multiple splats are generated to load the same constant,
5361 // it may be detrimental to overall size. There needs to be a way to detect
5362 // that condition to know if this is truly a size win.
5363 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5365 // Handle broadcasting a single constant scalar from the constant pool
5367 // On Sandybridge (no AVX2), it is still better to load a constant vector
5368 // from the constant pool and not to broadcast it from a scalar.
5369 // But override that restriction when optimizing for size.
5370 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5371 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5372 EVT CVT = Ld.getValueType();
5373 assert(!CVT.isVector() && "Must not broadcast a vector type");
5375 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5376 // For size optimization, also splat v2f64 and v2i64, and for size opt
5377 // with AVX2, also splat i8 and i16.
5378 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5379 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5380 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5381 const Constant *C = nullptr;
5382 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5383 C = CI->getConstantIntValue();
5384 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5385 C = CF->getConstantFPValue();
5387 assert(C && "Invalid constant type");
5389 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5391 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5392 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5394 CVT, dl, DAG.getEntryNode(), CP,
5395 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5396 false, false, Alignment);
5398 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5402 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5404 // Handle AVX2 in-register broadcasts.
5405 if (!IsLoad && Subtarget->hasInt256() &&
5406 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5407 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5409 // The scalar source must be a normal load.
5413 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5414 (Subtarget->hasVLX() && ScalarSize == 64))
5415 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5417 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5418 // double since there is no vbroadcastsd xmm
5419 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5420 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5421 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5424 // Unsupported broadcast.
5428 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5429 /// underlying vector and index.
5431 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5433 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5435 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5436 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5439 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5441 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5443 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5444 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5447 // In this case the vector is the extract_subvector expression and the index
5448 // is 2, as specified by the shuffle.
5449 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5450 SDValue ShuffleVec = SVOp->getOperand(0);
5451 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5452 assert(ShuffleVecVT.getVectorElementType() ==
5453 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5455 int ShuffleIdx = SVOp->getMaskElt(Idx);
5456 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5457 ExtractedFromVec = ShuffleVec;
5463 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5464 MVT VT = Op.getSimpleValueType();
5466 // Skip if insert_vec_elt is not supported.
5467 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5468 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5472 unsigned NumElems = Op.getNumOperands();
5476 SmallVector<unsigned, 4> InsertIndices;
5477 SmallVector<int, 8> Mask(NumElems, -1);
5479 for (unsigned i = 0; i != NumElems; ++i) {
5480 unsigned Opc = Op.getOperand(i).getOpcode();
5482 if (Opc == ISD::UNDEF)
5485 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5486 // Quit if more than 1 elements need inserting.
5487 if (InsertIndices.size() > 1)
5490 InsertIndices.push_back(i);
5494 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5495 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5496 // Quit if non-constant index.
5497 if (!isa<ConstantSDNode>(ExtIdx))
5499 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5501 // Quit if extracted from vector of different type.
5502 if (ExtractedFromVec.getValueType() != VT)
5505 if (!VecIn1.getNode())
5506 VecIn1 = ExtractedFromVec;
5507 else if (VecIn1 != ExtractedFromVec) {
5508 if (!VecIn2.getNode())
5509 VecIn2 = ExtractedFromVec;
5510 else if (VecIn2 != ExtractedFromVec)
5511 // Quit if more than 2 vectors to shuffle
5515 if (ExtractedFromVec == VecIn1)
5517 else if (ExtractedFromVec == VecIn2)
5518 Mask[i] = Idx + NumElems;
5521 if (!VecIn1.getNode())
5524 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5525 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5526 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5527 unsigned Idx = InsertIndices[i];
5528 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5529 DAG.getIntPtrConstant(Idx, DL));
5535 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5536 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5537 Op.getScalarValueSizeInBits() == 1 &&
5538 "Can not convert non-constant vector");
5539 uint64_t Immediate = 0;
5540 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5541 SDValue In = Op.getOperand(idx);
5542 if (In.getOpcode() != ISD::UNDEF)
5543 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5547 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5548 return DAG.getConstant(Immediate, dl, VT);
5550 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5552 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5554 MVT VT = Op.getSimpleValueType();
5555 assert((VT.getVectorElementType() == MVT::i1) &&
5556 "Unexpected type in LowerBUILD_VECTORvXi1!");
5559 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5560 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5561 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5562 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5565 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5566 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5567 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5568 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5571 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5572 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5573 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5574 return DAG.getBitcast(VT, Imm);
5575 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5576 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5577 DAG.getIntPtrConstant(0, dl));
5580 // Vector has one or more non-const elements
5581 uint64_t Immediate = 0;
5582 SmallVector<unsigned, 16> NonConstIdx;
5583 bool IsSplat = true;
5584 bool HasConstElts = false;
5586 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5587 SDValue In = Op.getOperand(idx);
5588 if (In.getOpcode() == ISD::UNDEF)
5590 if (!isa<ConstantSDNode>(In))
5591 NonConstIdx.push_back(idx);
5593 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5594 HasConstElts = true;
5598 else if (In != Op.getOperand(SplatIdx))
5602 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5604 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5605 DAG.getConstant(1, dl, VT),
5606 DAG.getConstant(0, dl, VT));
5608 // insert elements one by one
5612 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5613 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5615 else if (HasConstElts)
5616 Imm = DAG.getConstant(0, dl, VT);
5618 Imm = DAG.getUNDEF(VT);
5619 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5620 DstVec = DAG.getBitcast(VT, Imm);
5622 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5623 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5624 DAG.getIntPtrConstant(0, dl));
5627 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5628 unsigned InsertIdx = NonConstIdx[i];
5629 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5630 Op.getOperand(InsertIdx),
5631 DAG.getIntPtrConstant(InsertIdx, dl));
5636 /// \brief Return true if \p N implements a horizontal binop and return the
5637 /// operands for the horizontal binop into V0 and V1.
5639 /// This is a helper function of LowerToHorizontalOp().
5640 /// This function checks that the build_vector \p N in input implements a
5641 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5642 /// operation to match.
5643 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5644 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5645 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5648 /// This function only analyzes elements of \p N whose indices are
5649 /// in range [BaseIdx, LastIdx).
5650 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5652 unsigned BaseIdx, unsigned LastIdx,
5653 SDValue &V0, SDValue &V1) {
5654 EVT VT = N->getValueType(0);
5656 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5657 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5658 "Invalid Vector in input!");
5660 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5661 bool CanFold = true;
5662 unsigned ExpectedVExtractIdx = BaseIdx;
5663 unsigned NumElts = LastIdx - BaseIdx;
5664 V0 = DAG.getUNDEF(VT);
5665 V1 = DAG.getUNDEF(VT);
5667 // Check if N implements a horizontal binop.
5668 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5669 SDValue Op = N->getOperand(i + BaseIdx);
5672 if (Op->getOpcode() == ISD::UNDEF) {
5673 // Update the expected vector extract index.
5674 if (i * 2 == NumElts)
5675 ExpectedVExtractIdx = BaseIdx;
5676 ExpectedVExtractIdx += 2;
5680 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5685 SDValue Op0 = Op.getOperand(0);
5686 SDValue Op1 = Op.getOperand(1);
5688 // Try to match the following pattern:
5689 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5690 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5691 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5692 Op0.getOperand(0) == Op1.getOperand(0) &&
5693 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5694 isa<ConstantSDNode>(Op1.getOperand(1)));
5698 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5699 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5701 if (i * 2 < NumElts) {
5702 if (V0.getOpcode() == ISD::UNDEF) {
5703 V0 = Op0.getOperand(0);
5704 if (V0.getValueType() != VT)
5708 if (V1.getOpcode() == ISD::UNDEF) {
5709 V1 = Op0.getOperand(0);
5710 if (V1.getValueType() != VT)
5713 if (i * 2 == NumElts)
5714 ExpectedVExtractIdx = BaseIdx;
5717 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5718 if (I0 == ExpectedVExtractIdx)
5719 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5720 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5721 // Try to match the following dag sequence:
5722 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5723 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5727 ExpectedVExtractIdx += 2;
5733 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5734 /// a concat_vector.
5736 /// This is a helper function of LowerToHorizontalOp().
5737 /// This function expects two 256-bit vectors called V0 and V1.
5738 /// At first, each vector is split into two separate 128-bit vectors.
5739 /// Then, the resulting 128-bit vectors are used to implement two
5740 /// horizontal binary operations.
5742 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5744 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5745 /// the two new horizontal binop.
5746 /// When Mode is set, the first horizontal binop dag node would take as input
5747 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5748 /// horizontal binop dag node would take as input the lower 128-bit of V1
5749 /// and the upper 128-bit of V1.
5751 /// HADD V0_LO, V0_HI
5752 /// HADD V1_LO, V1_HI
5754 /// Otherwise, the first horizontal binop dag node takes as input the lower
5755 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5756 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5758 /// HADD V0_LO, V1_LO
5759 /// HADD V0_HI, V1_HI
5761 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5762 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5763 /// the upper 128-bits of the result.
5764 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5765 SDLoc DL, SelectionDAG &DAG,
5766 unsigned X86Opcode, bool Mode,
5767 bool isUndefLO, bool isUndefHI) {
5768 EVT VT = V0.getValueType();
5769 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5770 "Invalid nodes in input!");
5772 unsigned NumElts = VT.getVectorNumElements();
5773 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5774 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5775 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5776 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5777 EVT NewVT = V0_LO.getValueType();
5779 SDValue LO = DAG.getUNDEF(NewVT);
5780 SDValue HI = DAG.getUNDEF(NewVT);
5783 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5784 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5785 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5786 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5787 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5789 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5790 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5791 V1_LO->getOpcode() != ISD::UNDEF))
5792 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5794 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5795 V1_HI->getOpcode() != ISD::UNDEF))
5796 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5799 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5802 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5804 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5805 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5806 EVT VT = BV->getValueType(0);
5807 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5808 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5812 unsigned NumElts = VT.getVectorNumElements();
5813 SDValue InVec0 = DAG.getUNDEF(VT);
5814 SDValue InVec1 = DAG.getUNDEF(VT);
5816 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5817 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5819 // Odd-numbered elements in the input build vector are obtained from
5820 // adding two integer/float elements.
5821 // Even-numbered elements in the input build vector are obtained from
5822 // subtracting two integer/float elements.
5823 unsigned ExpectedOpcode = ISD::FSUB;
5824 unsigned NextExpectedOpcode = ISD::FADD;
5825 bool AddFound = false;
5826 bool SubFound = false;
5828 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5829 SDValue Op = BV->getOperand(i);
5831 // Skip 'undef' values.
5832 unsigned Opcode = Op.getOpcode();
5833 if (Opcode == ISD::UNDEF) {
5834 std::swap(ExpectedOpcode, NextExpectedOpcode);
5838 // Early exit if we found an unexpected opcode.
5839 if (Opcode != ExpectedOpcode)
5842 SDValue Op0 = Op.getOperand(0);
5843 SDValue Op1 = Op.getOperand(1);
5845 // Try to match the following pattern:
5846 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5847 // Early exit if we cannot match that sequence.
5848 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5849 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5850 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5851 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5852 Op0.getOperand(1) != Op1.getOperand(1))
5855 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5859 // We found a valid add/sub node. Update the information accordingly.
5865 // Update InVec0 and InVec1.
5866 if (InVec0.getOpcode() == ISD::UNDEF) {
5867 InVec0 = Op0.getOperand(0);
5868 if (InVec0.getValueType() != VT)
5871 if (InVec1.getOpcode() == ISD::UNDEF) {
5872 InVec1 = Op1.getOperand(0);
5873 if (InVec1.getValueType() != VT)
5877 // Make sure that operands in input to each add/sub node always
5878 // come from a same pair of vectors.
5879 if (InVec0 != Op0.getOperand(0)) {
5880 if (ExpectedOpcode == ISD::FSUB)
5883 // FADD is commutable. Try to commute the operands
5884 // and then test again.
5885 std::swap(Op0, Op1);
5886 if (InVec0 != Op0.getOperand(0))
5890 if (InVec1 != Op1.getOperand(0))
5893 // Update the pair of expected opcodes.
5894 std::swap(ExpectedOpcode, NextExpectedOpcode);
5897 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5898 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5899 InVec1.getOpcode() != ISD::UNDEF)
5900 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5905 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5906 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5907 const X86Subtarget *Subtarget,
5908 SelectionDAG &DAG) {
5909 EVT VT = BV->getValueType(0);
5910 unsigned NumElts = VT.getVectorNumElements();
5911 unsigned NumUndefsLO = 0;
5912 unsigned NumUndefsHI = 0;
5913 unsigned Half = NumElts/2;
5915 // Count the number of UNDEF operands in the build_vector in input.
5916 for (unsigned i = 0, e = Half; i != e; ++i)
5917 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5920 for (unsigned i = Half, e = NumElts; i != e; ++i)
5921 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5924 // Early exit if this is either a build_vector of all UNDEFs or all the
5925 // operands but one are UNDEF.
5926 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5930 SDValue InVec0, InVec1;
5931 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5932 // Try to match an SSE3 float HADD/HSUB.
5933 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5934 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5936 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5937 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5938 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5939 // Try to match an SSSE3 integer HADD/HSUB.
5940 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5941 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5943 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5944 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5947 if (!Subtarget->hasAVX())
5950 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5951 // Try to match an AVX horizontal add/sub of packed single/double
5952 // precision floating point values from 256-bit vectors.
5953 SDValue InVec2, InVec3;
5954 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5955 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5956 ((InVec0.getOpcode() == ISD::UNDEF ||
5957 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5958 ((InVec1.getOpcode() == ISD::UNDEF ||
5959 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5960 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5962 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5963 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5964 ((InVec0.getOpcode() == ISD::UNDEF ||
5965 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5966 ((InVec1.getOpcode() == ISD::UNDEF ||
5967 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5968 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5969 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5970 // Try to match an AVX2 horizontal add/sub of signed integers.
5971 SDValue InVec2, InVec3;
5973 bool CanFold = true;
5975 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5976 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5977 ((InVec0.getOpcode() == ISD::UNDEF ||
5978 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5979 ((InVec1.getOpcode() == ISD::UNDEF ||
5980 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5981 X86Opcode = X86ISD::HADD;
5982 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5983 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5984 ((InVec0.getOpcode() == ISD::UNDEF ||
5985 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5986 ((InVec1.getOpcode() == ISD::UNDEF ||
5987 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5988 X86Opcode = X86ISD::HSUB;
5993 // Fold this build_vector into a single horizontal add/sub.
5994 // Do this only if the target has AVX2.
5995 if (Subtarget->hasAVX2())
5996 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5998 // Do not try to expand this build_vector into a pair of horizontal
5999 // add/sub if we can emit a pair of scalar add/sub.
6000 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6003 // Convert this build_vector into a pair of horizontal binop followed by
6005 bool isUndefLO = NumUndefsLO == Half;
6006 bool isUndefHI = NumUndefsHI == Half;
6007 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6008 isUndefLO, isUndefHI);
6012 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6013 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6015 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6016 X86Opcode = X86ISD::HADD;
6017 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6018 X86Opcode = X86ISD::HSUB;
6019 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6020 X86Opcode = X86ISD::FHADD;
6021 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6022 X86Opcode = X86ISD::FHSUB;
6026 // Don't try to expand this build_vector into a pair of horizontal add/sub
6027 // if we can simply emit a pair of scalar add/sub.
6028 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6031 // Convert this build_vector into two horizontal add/sub followed by
6033 bool isUndefLO = NumUndefsLO == Half;
6034 bool isUndefHI = NumUndefsHI == Half;
6035 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6036 isUndefLO, isUndefHI);
6043 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6046 MVT VT = Op.getSimpleValueType();
6047 MVT ExtVT = VT.getVectorElementType();
6048 unsigned NumElems = Op.getNumOperands();
6050 // Generate vectors for predicate vectors.
6051 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6052 return LowerBUILD_VECTORvXi1(Op, DAG);
6054 // Vectors containing all zeros can be matched by pxor and xorps later
6055 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6056 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6057 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6058 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6061 return getZeroVector(VT, Subtarget, DAG, dl);
6064 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6065 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6066 // vpcmpeqd on 256-bit vectors.
6067 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6068 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6071 if (!VT.is512BitVector())
6072 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6075 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6076 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6078 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6079 return HorizontalOp;
6080 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6083 unsigned EVTBits = ExtVT.getSizeInBits();
6085 unsigned NumZero = 0;
6086 unsigned NumNonZero = 0;
6087 unsigned NonZeros = 0;
6088 bool IsAllConstants = true;
6089 SmallSet<SDValue, 8> Values;
6090 for (unsigned i = 0; i < NumElems; ++i) {
6091 SDValue Elt = Op.getOperand(i);
6092 if (Elt.getOpcode() == ISD::UNDEF)
6095 if (Elt.getOpcode() != ISD::Constant &&
6096 Elt.getOpcode() != ISD::ConstantFP)
6097 IsAllConstants = false;
6098 if (X86::isZeroNode(Elt))
6101 NonZeros |= (1 << i);
6106 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6107 if (NumNonZero == 0)
6108 return DAG.getUNDEF(VT);
6110 // Special case for single non-zero, non-undef, element.
6111 if (NumNonZero == 1) {
6112 unsigned Idx = countTrailingZeros(NonZeros);
6113 SDValue Item = Op.getOperand(Idx);
6115 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6116 // the value are obviously zero, truncate the value to i32 and do the
6117 // insertion that way. Only do this if the value is non-constant or if the
6118 // value is a constant being inserted into element 0. It is cheaper to do
6119 // a constant pool load than it is to do a movd + shuffle.
6120 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6121 (!IsAllConstants || Idx == 0)) {
6122 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6124 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6125 EVT VecVT = MVT::v4i32;
6127 // Truncate the value (which may itself be a constant) to i32, and
6128 // convert it to a vector with movd (S2V+shuffle to zero extend).
6129 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6130 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6131 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6132 Item, Idx * 2, true, Subtarget, DAG));
6136 // If we have a constant or non-constant insertion into the low element of
6137 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6138 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6139 // depending on what the source datatype is.
6142 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6144 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6145 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6146 if (VT.is512BitVector()) {
6147 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6148 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6149 Item, DAG.getIntPtrConstant(0, dl));
6151 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6152 "Expected an SSE value type!");
6153 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6154 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6155 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6158 // We can't directly insert an i8 or i16 into a vector, so zero extend
6160 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6161 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6162 if (VT.is256BitVector()) {
6163 if (Subtarget->hasAVX()) {
6164 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6165 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6167 // Without AVX, we need to extend to a 128-bit vector and then
6168 // insert into the 256-bit vector.
6169 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6170 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6171 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6174 assert(VT.is128BitVector() && "Expected an SSE value type!");
6175 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6176 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6178 return DAG.getBitcast(VT, Item);
6182 // Is it a vector logical left shift?
6183 if (NumElems == 2 && Idx == 1 &&
6184 X86::isZeroNode(Op.getOperand(0)) &&
6185 !X86::isZeroNode(Op.getOperand(1))) {
6186 unsigned NumBits = VT.getSizeInBits();
6187 return getVShift(true, VT,
6188 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6189 VT, Op.getOperand(1)),
6190 NumBits/2, DAG, *this, dl);
6193 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6196 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6197 // is a non-constant being inserted into an element other than the low one,
6198 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6199 // movd/movss) to move this into the low element, then shuffle it into
6201 if (EVTBits == 32) {
6202 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6203 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6207 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6208 if (Values.size() == 1) {
6209 if (EVTBits == 32) {
6210 // Instead of a shuffle like this:
6211 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6212 // Check if it's possible to issue this instead.
6213 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6214 unsigned Idx = countTrailingZeros(NonZeros);
6215 SDValue Item = Op.getOperand(Idx);
6216 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6217 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6222 // A vector full of immediates; various special cases are already
6223 // handled, so this is best done with a single constant-pool load.
6227 // For AVX-length vectors, see if we can use a vector load to get all of the
6228 // elements, otherwise build the individual 128-bit pieces and use
6229 // shuffles to put them in place.
6230 if (VT.is256BitVector() || VT.is512BitVector()) {
6231 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6233 // Check for a build vector of consecutive loads.
6234 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6237 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6239 // Build both the lower and upper subvector.
6240 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6241 makeArrayRef(&V[0], NumElems/2));
6242 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6243 makeArrayRef(&V[NumElems / 2], NumElems/2));
6245 // Recreate the wider vector with the lower and upper part.
6246 if (VT.is256BitVector())
6247 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6248 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6251 // Let legalizer expand 2-wide build_vectors.
6252 if (EVTBits == 64) {
6253 if (NumNonZero == 1) {
6254 // One half is zero or undef.
6255 unsigned Idx = countTrailingZeros(NonZeros);
6256 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6257 Op.getOperand(Idx));
6258 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6263 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6264 if (EVTBits == 8 && NumElems == 16)
6265 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6269 if (EVTBits == 16 && NumElems == 8)
6270 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6274 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6275 if (EVTBits == 32 && NumElems == 4)
6276 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6279 // If element VT is == 32 bits, turn it into a number of shuffles.
6280 SmallVector<SDValue, 8> V(NumElems);
6281 if (NumElems == 4 && NumZero > 0) {
6282 for (unsigned i = 0; i < 4; ++i) {
6283 bool isZero = !(NonZeros & (1 << i));
6285 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6287 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6290 for (unsigned i = 0; i < 2; ++i) {
6291 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6294 V[i] = V[i*2]; // Must be a zero vector.
6297 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6300 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6303 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6308 bool Reverse1 = (NonZeros & 0x3) == 2;
6309 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6313 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6314 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6316 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6319 if (Values.size() > 1 && VT.is128BitVector()) {
6320 // Check for a build vector of consecutive loads.
6321 for (unsigned i = 0; i < NumElems; ++i)
6322 V[i] = Op.getOperand(i);
6324 // Check for elements which are consecutive loads.
6325 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6328 // Check for a build vector from mostly shuffle plus few inserting.
6329 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6332 // For SSE 4.1, use insertps to put the high elements into the low element.
6333 if (Subtarget->hasSSE41()) {
6335 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6336 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6338 Result = DAG.getUNDEF(VT);
6340 for (unsigned i = 1; i < NumElems; ++i) {
6341 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6342 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6343 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6348 // Otherwise, expand into a number of unpckl*, start by extending each of
6349 // our (non-undef) elements to the full vector width with the element in the
6350 // bottom slot of the vector (which generates no code for SSE).
6351 for (unsigned i = 0; i < NumElems; ++i) {
6352 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6353 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6355 V[i] = DAG.getUNDEF(VT);
6358 // Next, we iteratively mix elements, e.g. for v4f32:
6359 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6360 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6361 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6362 unsigned EltStride = NumElems >> 1;
6363 while (EltStride != 0) {
6364 for (unsigned i = 0; i < EltStride; ++i) {
6365 // If V[i+EltStride] is undef and this is the first round of mixing,
6366 // then it is safe to just drop this shuffle: V[i] is already in the
6367 // right place, the one element (since it's the first round) being
6368 // inserted as undef can be dropped. This isn't safe for successive
6369 // rounds because they will permute elements within both vectors.
6370 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6371 EltStride == NumElems/2)
6374 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6383 // 256-bit AVX can use the vinsertf128 instruction
6384 // to create 256-bit vectors from two other 128-bit ones.
6385 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6387 MVT ResVT = Op.getSimpleValueType();
6389 assert((ResVT.is256BitVector() ||
6390 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6392 SDValue V1 = Op.getOperand(0);
6393 SDValue V2 = Op.getOperand(1);
6394 unsigned NumElems = ResVT.getVectorNumElements();
6395 if (ResVT.is256BitVector())
6396 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6398 if (Op.getNumOperands() == 4) {
6399 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6400 ResVT.getVectorNumElements()/2);
6401 SDValue V3 = Op.getOperand(2);
6402 SDValue V4 = Op.getOperand(3);
6403 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6404 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6406 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6409 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6410 const X86Subtarget *Subtarget,
6411 SelectionDAG & DAG) {
6413 MVT ResVT = Op.getSimpleValueType();
6414 unsigned NumOfOperands = Op.getNumOperands();
6416 assert(isPowerOf2_32(NumOfOperands) &&
6417 "Unexpected number of operands in CONCAT_VECTORS");
6419 if (NumOfOperands > 2) {
6420 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6421 ResVT.getVectorNumElements()/2);
6422 SmallVector<SDValue, 2> Ops;
6423 for (unsigned i = 0; i < NumOfOperands/2; i++)
6424 Ops.push_back(Op.getOperand(i));
6425 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6427 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6428 Ops.push_back(Op.getOperand(i));
6429 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6430 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6433 SDValue V1 = Op.getOperand(0);
6434 SDValue V2 = Op.getOperand(1);
6435 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6436 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6438 if (IsZeroV1 && IsZeroV2)
6439 return getZeroVector(ResVT, Subtarget, DAG, dl);
6441 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6442 SDValue Undef = DAG.getUNDEF(ResVT);
6443 unsigned NumElems = ResVT.getVectorNumElements();
6444 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6446 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6447 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6451 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6452 // Zero the upper bits of V1
6453 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6454 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6457 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6460 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6461 const X86Subtarget *Subtarget,
6462 SelectionDAG &DAG) {
6463 MVT VT = Op.getSimpleValueType();
6464 if (VT.getVectorElementType() == MVT::i1)
6465 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6467 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6468 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6469 Op.getNumOperands() == 4)));
6471 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6472 // from two other 128-bit ones.
6474 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6475 return LowerAVXCONCAT_VECTORS(Op, DAG);
6479 //===----------------------------------------------------------------------===//
6480 // Vector shuffle lowering
6482 // This is an experimental code path for lowering vector shuffles on x86. It is
6483 // designed to handle arbitrary vector shuffles and blends, gracefully
6484 // degrading performance as necessary. It works hard to recognize idiomatic
6485 // shuffles and lower them to optimal instruction patterns without leaving
6486 // a framework that allows reasonably efficient handling of all vector shuffle
6488 //===----------------------------------------------------------------------===//
6490 /// \brief Tiny helper function to identify a no-op mask.
6492 /// This is a somewhat boring predicate function. It checks whether the mask
6493 /// array input, which is assumed to be a single-input shuffle mask of the kind
6494 /// used by the X86 shuffle instructions (not a fully general
6495 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6496 /// in-place shuffle are 'no-op's.
6497 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6498 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6499 if (Mask[i] != -1 && Mask[i] != i)
6504 /// \brief Helper function to classify a mask as a single-input mask.
6506 /// This isn't a generic single-input test because in the vector shuffle
6507 /// lowering we canonicalize single inputs to be the first input operand. This
6508 /// means we can more quickly test for a single input by only checking whether
6509 /// an input from the second operand exists. We also assume that the size of
6510 /// mask corresponds to the size of the input vectors which isn't true in the
6511 /// fully general case.
6512 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6514 if (M >= (int)Mask.size())
6519 /// \brief Test whether there are elements crossing 128-bit lanes in this
6522 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6523 /// and we routinely test for these.
6524 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6525 int LaneSize = 128 / VT.getScalarSizeInBits();
6526 int Size = Mask.size();
6527 for (int i = 0; i < Size; ++i)
6528 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6533 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6535 /// This checks a shuffle mask to see if it is performing the same
6536 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6537 /// that it is also not lane-crossing. It may however involve a blend from the
6538 /// same lane of a second vector.
6540 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6541 /// non-trivial to compute in the face of undef lanes. The representation is
6542 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6543 /// entries from both V1 and V2 inputs to the wider mask.
6545 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6546 SmallVectorImpl<int> &RepeatedMask) {
6547 int LaneSize = 128 / VT.getScalarSizeInBits();
6548 RepeatedMask.resize(LaneSize, -1);
6549 int Size = Mask.size();
6550 for (int i = 0; i < Size; ++i) {
6553 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6554 // This entry crosses lanes, so there is no way to model this shuffle.
6557 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6558 if (RepeatedMask[i % LaneSize] == -1)
6559 // This is the first non-undef entry in this slot of a 128-bit lane.
6560 RepeatedMask[i % LaneSize] =
6561 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6562 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6563 // Found a mismatch with the repeated mask.
6569 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6572 /// This is a fast way to test a shuffle mask against a fixed pattern:
6574 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6576 /// It returns true if the mask is exactly as wide as the argument list, and
6577 /// each element of the mask is either -1 (signifying undef) or the value given
6578 /// in the argument.
6579 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6580 ArrayRef<int> ExpectedMask) {
6581 if (Mask.size() != ExpectedMask.size())
6584 int Size = Mask.size();
6586 // If the values are build vectors, we can look through them to find
6587 // equivalent inputs that make the shuffles equivalent.
6588 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6589 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6591 for (int i = 0; i < Size; ++i)
6592 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6593 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6594 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6595 if (!MaskBV || !ExpectedBV ||
6596 MaskBV->getOperand(Mask[i] % Size) !=
6597 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6604 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6606 /// This helper function produces an 8-bit shuffle immediate corresponding to
6607 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6608 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6611 /// NB: We rely heavily on "undef" masks preserving the input lane.
6612 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6613 SelectionDAG &DAG) {
6614 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6615 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6616 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6617 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6618 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6621 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6622 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6623 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6624 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6625 return DAG.getConstant(Imm, DL, MVT::i8);
6628 /// \brief Compute whether each element of a shuffle is zeroable.
6630 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6631 /// Either it is an undef element in the shuffle mask, the element of the input
6632 /// referenced is undef, or the element of the input referenced is known to be
6633 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6634 /// as many lanes with this technique as possible to simplify the remaining
6636 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6637 SDValue V1, SDValue V2) {
6638 SmallBitVector Zeroable(Mask.size(), false);
6640 while (V1.getOpcode() == ISD::BITCAST)
6641 V1 = V1->getOperand(0);
6642 while (V2.getOpcode() == ISD::BITCAST)
6643 V2 = V2->getOperand(0);
6645 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6646 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6648 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6650 // Handle the easy cases.
6651 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6656 // If this is an index into a build_vector node (which has the same number
6657 // of elements), dig out the input value and use it.
6658 SDValue V = M < Size ? V1 : V2;
6659 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6662 SDValue Input = V.getOperand(M % Size);
6663 // The UNDEF opcode check really should be dead code here, but not quite
6664 // worth asserting on (it isn't invalid, just unexpected).
6665 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6672 /// \brief Try to emit a bitmask instruction for a shuffle.
6674 /// This handles cases where we can model a blend exactly as a bitmask due to
6675 /// one of the inputs being zeroable.
6676 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6677 SDValue V2, ArrayRef<int> Mask,
6678 SelectionDAG &DAG) {
6679 MVT EltVT = VT.getScalarType();
6680 int NumEltBits = EltVT.getSizeInBits();
6681 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6682 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6683 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6685 if (EltVT.isFloatingPoint()) {
6686 Zero = DAG.getBitcast(EltVT, Zero);
6687 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6689 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6690 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6692 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6695 if (Mask[i] % Size != i)
6696 return SDValue(); // Not a blend.
6698 V = Mask[i] < Size ? V1 : V2;
6699 else if (V != (Mask[i] < Size ? V1 : V2))
6700 return SDValue(); // Can only let one input through the mask.
6702 VMaskOps[i] = AllOnes;
6705 return SDValue(); // No non-zeroable elements!
6707 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6708 V = DAG.getNode(VT.isFloatingPoint()
6709 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6714 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6716 /// This is used as a fallback approach when first class blend instructions are
6717 /// unavailable. Currently it is only suitable for integer vectors, but could
6718 /// be generalized for floating point vectors if desirable.
6719 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6720 SDValue V2, ArrayRef<int> Mask,
6721 SelectionDAG &DAG) {
6722 assert(VT.isInteger() && "Only supports integer vector types!");
6723 MVT EltVT = VT.getScalarType();
6724 int NumEltBits = EltVT.getSizeInBits();
6725 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6726 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6728 SmallVector<SDValue, 16> MaskOps;
6729 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6730 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6731 return SDValue(); // Shuffled input!
6732 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6735 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6736 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6737 // We have to cast V2 around.
6738 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6739 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6740 DAG.getBitcast(MaskVT, V1Mask),
6741 DAG.getBitcast(MaskVT, V2)));
6742 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6745 /// \brief Try to emit a blend instruction for a shuffle.
6747 /// This doesn't do any checks for the availability of instructions for blending
6748 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6749 /// be matched in the backend with the type given. What it does check for is
6750 /// that the shuffle mask is in fact a blend.
6751 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6752 SDValue V2, ArrayRef<int> Mask,
6753 const X86Subtarget *Subtarget,
6754 SelectionDAG &DAG) {
6755 unsigned BlendMask = 0;
6756 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6757 if (Mask[i] >= Size) {
6758 if (Mask[i] != i + Size)
6759 return SDValue(); // Shuffled V2 input!
6760 BlendMask |= 1u << i;
6763 if (Mask[i] >= 0 && Mask[i] != i)
6764 return SDValue(); // Shuffled V1 input!
6766 switch (VT.SimpleTy) {
6771 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6772 DAG.getConstant(BlendMask, DL, MVT::i8));
6776 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6780 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6781 // that instruction.
6782 if (Subtarget->hasAVX2()) {
6783 // Scale the blend by the number of 32-bit dwords per element.
6784 int Scale = VT.getScalarSizeInBits() / 32;
6786 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6787 if (Mask[i] >= Size)
6788 for (int j = 0; j < Scale; ++j)
6789 BlendMask |= 1u << (i * Scale + j);
6791 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6792 V1 = DAG.getBitcast(BlendVT, V1);
6793 V2 = DAG.getBitcast(BlendVT, V2);
6794 return DAG.getBitcast(
6795 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6796 DAG.getConstant(BlendMask, DL, MVT::i8)));
6800 // For integer shuffles we need to expand the mask and cast the inputs to
6801 // v8i16s prior to blending.
6802 int Scale = 8 / VT.getVectorNumElements();
6804 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6805 if (Mask[i] >= Size)
6806 for (int j = 0; j < Scale; ++j)
6807 BlendMask |= 1u << (i * Scale + j);
6809 V1 = DAG.getBitcast(MVT::v8i16, V1);
6810 V2 = DAG.getBitcast(MVT::v8i16, V2);
6811 return DAG.getBitcast(VT,
6812 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6813 DAG.getConstant(BlendMask, DL, MVT::i8)));
6817 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6818 SmallVector<int, 8> RepeatedMask;
6819 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6820 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6821 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6823 for (int i = 0; i < 8; ++i)
6824 if (RepeatedMask[i] >= 16)
6825 BlendMask |= 1u << i;
6826 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6827 DAG.getConstant(BlendMask, DL, MVT::i8));
6833 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6834 "256-bit byte-blends require AVX2 support!");
6836 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6837 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6840 // Scale the blend by the number of bytes per element.
6841 int Scale = VT.getScalarSizeInBits() / 8;
6843 // This form of blend is always done on bytes. Compute the byte vector
6845 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6847 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6848 // mix of LLVM's code generator and the x86 backend. We tell the code
6849 // generator that boolean values in the elements of an x86 vector register
6850 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6851 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6852 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6853 // of the element (the remaining are ignored) and 0 in that high bit would
6854 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6855 // the LLVM model for boolean values in vector elements gets the relevant
6856 // bit set, it is set backwards and over constrained relative to x86's
6858 SmallVector<SDValue, 32> VSELECTMask;
6859 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6860 for (int j = 0; j < Scale; ++j)
6861 VSELECTMask.push_back(
6862 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6863 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6866 V1 = DAG.getBitcast(BlendVT, V1);
6867 V2 = DAG.getBitcast(BlendVT, V2);
6868 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6869 DAG.getNode(ISD::BUILD_VECTOR, DL,
6870 BlendVT, VSELECTMask),
6875 llvm_unreachable("Not a supported integer vector type!");
6879 /// \brief Try to lower as a blend of elements from two inputs followed by
6880 /// a single-input permutation.
6882 /// This matches the pattern where we can blend elements from two inputs and
6883 /// then reduce the shuffle to a single-input permutation.
6884 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6887 SelectionDAG &DAG) {
6888 // We build up the blend mask while checking whether a blend is a viable way
6889 // to reduce the shuffle.
6890 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6891 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6893 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6897 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6899 if (BlendMask[Mask[i] % Size] == -1)
6900 BlendMask[Mask[i] % Size] = Mask[i];
6901 else if (BlendMask[Mask[i] % Size] != Mask[i])
6902 return SDValue(); // Can't blend in the needed input!
6904 PermuteMask[i] = Mask[i] % Size;
6907 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6908 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6911 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6912 /// blends and permutes.
6914 /// This matches the extremely common pattern for handling combined
6915 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6916 /// operations. It will try to pick the best arrangement of shuffles and
6918 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6922 SelectionDAG &DAG) {
6923 // Shuffle the input elements into the desired positions in V1 and V2 and
6924 // blend them together.
6925 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6926 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6927 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6928 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6929 if (Mask[i] >= 0 && Mask[i] < Size) {
6930 V1Mask[i] = Mask[i];
6932 } else if (Mask[i] >= Size) {
6933 V2Mask[i] = Mask[i] - Size;
6934 BlendMask[i] = i + Size;
6937 // Try to lower with the simpler initial blend strategy unless one of the
6938 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6939 // shuffle may be able to fold with a load or other benefit. However, when
6940 // we'll have to do 2x as many shuffles in order to achieve this, blending
6941 // first is a better strategy.
6942 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6943 if (SDValue BlendPerm =
6944 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6947 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6948 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6949 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6952 /// \brief Try to lower a vector shuffle as a byte rotation.
6954 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6955 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6956 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6957 /// try to generically lower a vector shuffle through such an pattern. It
6958 /// does not check for the profitability of lowering either as PALIGNR or
6959 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6960 /// This matches shuffle vectors that look like:
6962 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6964 /// Essentially it concatenates V1 and V2, shifts right by some number of
6965 /// elements, and takes the low elements as the result. Note that while this is
6966 /// specified as a *right shift* because x86 is little-endian, it is a *left
6967 /// rotate* of the vector lanes.
6968 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6971 const X86Subtarget *Subtarget,
6972 SelectionDAG &DAG) {
6973 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6975 int NumElts = Mask.size();
6976 int NumLanes = VT.getSizeInBits() / 128;
6977 int NumLaneElts = NumElts / NumLanes;
6979 // We need to detect various ways of spelling a rotation:
6980 // [11, 12, 13, 14, 15, 0, 1, 2]
6981 // [-1, 12, 13, 14, -1, -1, 1, -1]
6982 // [-1, -1, -1, -1, -1, -1, 1, 2]
6983 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6984 // [-1, 4, 5, 6, -1, -1, 9, -1]
6985 // [-1, 4, 5, 6, -1, -1, -1, -1]
6988 for (int l = 0; l < NumElts; l += NumLaneElts) {
6989 for (int i = 0; i < NumLaneElts; ++i) {
6990 if (Mask[l + i] == -1)
6992 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6994 // Get the mod-Size index and lane correct it.
6995 int LaneIdx = (Mask[l + i] % NumElts) - l;
6996 // Make sure it was in this lane.
6997 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7000 // Determine where a rotated vector would have started.
7001 int StartIdx = i - LaneIdx;
7003 // The identity rotation isn't interesting, stop.
7006 // If we found the tail of a vector the rotation must be the missing
7007 // front. If we found the head of a vector, it must be how much of the
7009 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7012 Rotation = CandidateRotation;
7013 else if (Rotation != CandidateRotation)
7014 // The rotations don't match, so we can't match this mask.
7017 // Compute which value this mask is pointing at.
7018 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7020 // Compute which of the two target values this index should be assigned
7021 // to. This reflects whether the high elements are remaining or the low
7022 // elements are remaining.
7023 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7025 // Either set up this value if we've not encountered it before, or check
7026 // that it remains consistent.
7029 else if (TargetV != MaskV)
7030 // This may be a rotation, but it pulls from the inputs in some
7031 // unsupported interleaving.
7036 // Check that we successfully analyzed the mask, and normalize the results.
7037 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7038 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7044 // The actual rotate instruction rotates bytes, so we need to scale the
7045 // rotation based on how many bytes are in the vector lane.
7046 int Scale = 16 / NumLaneElts;
7048 // SSSE3 targets can use the palignr instruction.
7049 if (Subtarget->hasSSSE3()) {
7050 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7051 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7052 Lo = DAG.getBitcast(AlignVT, Lo);
7053 Hi = DAG.getBitcast(AlignVT, Hi);
7055 return DAG.getBitcast(
7056 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7057 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7060 assert(VT.getSizeInBits() == 128 &&
7061 "Rotate-based lowering only supports 128-bit lowering!");
7062 assert(Mask.size() <= 16 &&
7063 "Can shuffle at most 16 bytes in a 128-bit vector!");
7065 // Default SSE2 implementation
7066 int LoByteShift = 16 - Rotation * Scale;
7067 int HiByteShift = Rotation * Scale;
7069 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7070 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7071 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7073 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7074 DAG.getConstant(LoByteShift, DL, MVT::i8));
7075 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7076 DAG.getConstant(HiByteShift, DL, MVT::i8));
7077 return DAG.getBitcast(VT,
7078 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7081 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7083 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7084 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7085 /// matches elements from one of the input vectors shuffled to the left or
7086 /// right with zeroable elements 'shifted in'. It handles both the strictly
7087 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7090 /// PSHL : (little-endian) left bit shift.
7091 /// [ zz, 0, zz, 2 ]
7092 /// [ -1, 4, zz, -1 ]
7093 /// PSRL : (little-endian) right bit shift.
7095 /// [ -1, -1, 7, zz]
7096 /// PSLLDQ : (little-endian) left byte shift
7097 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7098 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7099 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7100 /// PSRLDQ : (little-endian) right byte shift
7101 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7102 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7103 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7104 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7105 SDValue V2, ArrayRef<int> Mask,
7106 SelectionDAG &DAG) {
7107 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7109 int Size = Mask.size();
7110 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7112 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7113 for (int i = 0; i < Size; i += Scale)
7114 for (int j = 0; j < Shift; ++j)
7115 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7121 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7122 for (int i = 0; i != Size; i += Scale) {
7123 unsigned Pos = Left ? i + Shift : i;
7124 unsigned Low = Left ? i : i + Shift;
7125 unsigned Len = Scale - Shift;
7126 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7127 Low + (V == V1 ? 0 : Size)))
7131 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7132 bool ByteShift = ShiftEltBits > 64;
7133 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7134 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7135 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7137 // Normalize the scale for byte shifts to still produce an i64 element
7139 Scale = ByteShift ? Scale / 2 : Scale;
7141 // We need to round trip through the appropriate type for the shift.
7142 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7143 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7144 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7145 "Illegal integer vector type");
7146 V = DAG.getBitcast(ShiftVT, V);
7148 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7149 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7150 return DAG.getBitcast(VT, V);
7153 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7154 // keep doubling the size of the integer elements up to that. We can
7155 // then shift the elements of the integer vector by whole multiples of
7156 // their width within the elements of the larger integer vector. Test each
7157 // multiple to see if we can find a match with the moved element indices
7158 // and that the shifted in elements are all zeroable.
7159 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7160 for (int Shift = 1; Shift != Scale; ++Shift)
7161 for (bool Left : {true, false})
7162 if (CheckZeros(Shift, Scale, Left))
7163 for (SDValue V : {V1, V2})
7164 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7171 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7172 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7173 SDValue V2, ArrayRef<int> Mask,
7174 SelectionDAG &DAG) {
7175 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7176 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7178 int Size = Mask.size();
7179 int HalfSize = Size / 2;
7180 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7182 // Upper half must be undefined.
7183 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7186 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7187 // Remainder of lower half result is zero and upper half is all undef.
7188 auto LowerAsEXTRQ = [&]() {
7189 // Determine the extraction length from the part of the
7190 // lower half that isn't zeroable.
7192 for (; Len >= 0; --Len)
7193 if (!Zeroable[Len - 1])
7195 assert(Len > 0 && "Zeroable shuffle mask");
7197 // Attempt to match first Len sequential elements from the lower half.
7200 for (int i = 0; i != Len; ++i) {
7204 SDValue &V = (M < Size ? V1 : V2);
7207 // All mask elements must be in the lower half.
7211 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7222 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7223 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7224 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7225 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7226 DAG.getConstant(BitLen, DL, MVT::i8),
7227 DAG.getConstant(BitIdx, DL, MVT::i8));
7230 if (SDValue ExtrQ = LowerAsEXTRQ())
7233 // INSERTQ: Extract lowest Len elements from lower half of second source and
7234 // insert over first source, starting at Idx.
7235 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7236 auto LowerAsInsertQ = [&]() {
7237 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7240 // Attempt to match first source from mask before insertion point.
7241 if (isUndefInRange(Mask, 0, Idx)) {
7243 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7245 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7251 // Extend the extraction length looking to match both the insertion of
7252 // the second source and the remaining elements of the first.
7253 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7258 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7260 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7266 // Match the remaining elements of the lower half.
7267 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7269 } else if ((!Base || (Base == V1)) &&
7270 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7272 } else if ((!Base || (Base == V2)) &&
7273 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7280 // We may not have a base (first source) - this can safely be undefined.
7282 Base = DAG.getUNDEF(VT);
7284 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7285 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7286 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7287 DAG.getConstant(BitLen, DL, MVT::i8),
7288 DAG.getConstant(BitIdx, DL, MVT::i8));
7295 if (SDValue InsertQ = LowerAsInsertQ())
7301 /// \brief Lower a vector shuffle as a zero or any extension.
7303 /// Given a specific number of elements, element bit width, and extension
7304 /// stride, produce either a zero or any extension based on the available
7305 /// features of the subtarget.
7306 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7307 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
7308 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7309 assert(Scale > 1 && "Need a scale to extend.");
7310 int NumElements = VT.getVectorNumElements();
7311 int EltBits = VT.getScalarSizeInBits();
7312 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7313 "Only 8, 16, and 32 bit elements can be extended.");
7314 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7316 // Found a valid zext mask! Try various lowering strategies based on the
7317 // input type and available ISA extensions.
7318 if (Subtarget->hasSSE41()) {
7319 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7320 NumElements / Scale);
7321 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7324 // For any extends we can cheat for larger element sizes and use shuffle
7325 // instructions that can fold with a load and/or copy.
7326 if (AnyExt && EltBits == 32) {
7327 int PSHUFDMask[4] = {0, -1, 1, -1};
7328 return DAG.getBitcast(
7329 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7330 DAG.getBitcast(MVT::v4i32, InputV),
7331 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7333 if (AnyExt && EltBits == 16 && Scale > 2) {
7334 int PSHUFDMask[4] = {0, -1, 0, -1};
7335 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7336 DAG.getBitcast(MVT::v4i32, InputV),
7337 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7338 int PSHUFHWMask[4] = {1, -1, -1, -1};
7339 return DAG.getBitcast(
7340 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7341 DAG.getBitcast(MVT::v8i16, InputV),
7342 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
7345 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7347 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7348 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7349 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7351 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7352 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7353 DAG.getConstant(EltBits, DL, MVT::i8),
7354 DAG.getConstant(0, DL, MVT::i8)));
7355 if (isUndefInRange(Mask, NumElements/2, NumElements/2))
7356 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7359 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7360 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7361 DAG.getConstant(EltBits, DL, MVT::i8),
7362 DAG.getConstant(EltBits, DL, MVT::i8)));
7363 return DAG.getNode(ISD::BITCAST, DL, VT,
7364 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7367 // If this would require more than 2 unpack instructions to expand, use
7368 // pshufb when available. We can only use more than 2 unpack instructions
7369 // when zero extending i8 elements which also makes it easier to use pshufb.
7370 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7371 assert(NumElements == 16 && "Unexpected byte vector width!");
7372 SDValue PSHUFBMask[16];
7373 for (int i = 0; i < 16; ++i)
7375 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
7376 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7377 return DAG.getBitcast(VT,
7378 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7379 DAG.getNode(ISD::BUILD_VECTOR, DL,
7380 MVT::v16i8, PSHUFBMask)));
7383 // Otherwise emit a sequence of unpacks.
7385 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7386 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7387 : getZeroVector(InputVT, Subtarget, DAG, DL);
7388 InputV = DAG.getBitcast(InputVT, InputV);
7389 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7393 } while (Scale > 1);
7394 return DAG.getBitcast(VT, InputV);
7397 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7399 /// This routine will try to do everything in its power to cleverly lower
7400 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7401 /// check for the profitability of this lowering, it tries to aggressively
7402 /// match this pattern. It will use all of the micro-architectural details it
7403 /// can to emit an efficient lowering. It handles both blends with all-zero
7404 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7405 /// masking out later).
7407 /// The reason we have dedicated lowering for zext-style shuffles is that they
7408 /// are both incredibly common and often quite performance sensitive.
7409 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7410 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7411 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7412 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7414 int Bits = VT.getSizeInBits();
7415 int NumElements = VT.getVectorNumElements();
7416 assert(VT.getScalarSizeInBits() <= 32 &&
7417 "Exceeds 32-bit integer zero extension limit");
7418 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7420 // Define a helper function to check a particular ext-scale and lower to it if
7422 auto Lower = [&](int Scale) -> SDValue {
7425 for (int i = 0; i < NumElements; ++i) {
7427 continue; // Valid anywhere but doesn't tell us anything.
7428 if (i % Scale != 0) {
7429 // Each of the extended elements need to be zeroable.
7433 // We no longer are in the anyext case.
7438 // Each of the base elements needs to be consecutive indices into the
7439 // same input vector.
7440 SDValue V = Mask[i] < NumElements ? V1 : V2;
7443 else if (InputV != V)
7444 return SDValue(); // Flip-flopping inputs.
7446 if (Mask[i] % NumElements != i / Scale)
7447 return SDValue(); // Non-consecutive strided elements.
7450 // If we fail to find an input, we have a zero-shuffle which should always
7451 // have already been handled.
7452 // FIXME: Maybe handle this here in case during blending we end up with one?
7456 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7457 DL, VT, Scale, AnyExt, InputV, Mask, Subtarget, DAG);
7460 // The widest scale possible for extending is to a 64-bit integer.
7461 assert(Bits % 64 == 0 &&
7462 "The number of bits in a vector must be divisible by 64 on x86!");
7463 int NumExtElements = Bits / 64;
7465 // Each iteration, try extending the elements half as much, but into twice as
7467 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7468 assert(NumElements % NumExtElements == 0 &&
7469 "The input vector size must be divisible by the extended size.");
7470 if (SDValue V = Lower(NumElements / NumExtElements))
7474 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7478 // Returns one of the source operands if the shuffle can be reduced to a
7479 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7480 auto CanZExtLowHalf = [&]() {
7481 for (int i = NumElements / 2; i != NumElements; ++i)
7484 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7486 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7491 if (SDValue V = CanZExtLowHalf()) {
7492 V = DAG.getBitcast(MVT::v2i64, V);
7493 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7494 return DAG.getBitcast(VT, V);
7497 // No viable ext lowering found.
7501 /// \brief Try to get a scalar value for a specific element of a vector.
7503 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7504 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7505 SelectionDAG &DAG) {
7506 MVT VT = V.getSimpleValueType();
7507 MVT EltVT = VT.getVectorElementType();
7508 while (V.getOpcode() == ISD::BITCAST)
7509 V = V.getOperand(0);
7510 // If the bitcasts shift the element size, we can't extract an equivalent
7512 MVT NewVT = V.getSimpleValueType();
7513 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7516 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7517 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7518 // Ensure the scalar operand is the same size as the destination.
7519 // FIXME: Add support for scalar truncation where possible.
7520 SDValue S = V.getOperand(Idx);
7521 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7522 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7528 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7530 /// This is particularly important because the set of instructions varies
7531 /// significantly based on whether the operand is a load or not.
7532 static bool isShuffleFoldableLoad(SDValue V) {
7533 while (V.getOpcode() == ISD::BITCAST)
7534 V = V.getOperand(0);
7536 return ISD::isNON_EXTLoad(V.getNode());
7539 /// \brief Try to lower insertion of a single element into a zero vector.
7541 /// This is a common pattern that we have especially efficient patterns to lower
7542 /// across all subtarget feature sets.
7543 static SDValue lowerVectorShuffleAsElementInsertion(
7544 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7545 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7546 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7548 MVT EltVT = VT.getVectorElementType();
7550 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7551 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7553 bool IsV1Zeroable = true;
7554 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7555 if (i != V2Index && !Zeroable[i]) {
7556 IsV1Zeroable = false;
7560 // Check for a single input from a SCALAR_TO_VECTOR node.
7561 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7562 // all the smarts here sunk into that routine. However, the current
7563 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7564 // vector shuffle lowering is dead.
7565 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7567 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7568 // We need to zext the scalar if it is smaller than an i32.
7569 V2S = DAG.getBitcast(EltVT, V2S);
7570 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7571 // Using zext to expand a narrow element won't work for non-zero
7576 // Zero-extend directly to i32.
7578 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7580 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7581 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7582 EltVT == MVT::i16) {
7583 // Either not inserting from the low element of the input or the input
7584 // element size is too small to use VZEXT_MOVL to clear the high bits.
7588 if (!IsV1Zeroable) {
7589 // If V1 can't be treated as a zero vector we have fewer options to lower
7590 // this. We can't support integer vectors or non-zero targets cheaply, and
7591 // the V1 elements can't be permuted in any way.
7592 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7593 if (!VT.isFloatingPoint() || V2Index != 0)
7595 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7596 V1Mask[V2Index] = -1;
7597 if (!isNoopShuffleMask(V1Mask))
7599 // This is essentially a special case blend operation, but if we have
7600 // general purpose blend operations, they are always faster. Bail and let
7601 // the rest of the lowering handle these as blends.
7602 if (Subtarget->hasSSE41())
7605 // Otherwise, use MOVSD or MOVSS.
7606 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7607 "Only two types of floating point element types to handle!");
7608 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7612 // This lowering only works for the low element with floating point vectors.
7613 if (VT.isFloatingPoint() && V2Index != 0)
7616 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7618 V2 = DAG.getBitcast(VT, V2);
7621 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7622 // the desired position. Otherwise it is more efficient to do a vector
7623 // shift left. We know that we can do a vector shift left because all
7624 // the inputs are zero.
7625 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7626 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7627 V2Shuffle[V2Index] = 0;
7628 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7630 V2 = DAG.getBitcast(MVT::v2i64, V2);
7632 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7633 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7634 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7635 DAG.getDataLayout(), VT)));
7636 V2 = DAG.getBitcast(VT, V2);
7642 /// \brief Try to lower broadcast of a single element.
7644 /// For convenience, this code also bundles all of the subtarget feature set
7645 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7646 /// a convenient way to factor it out.
7647 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7649 const X86Subtarget *Subtarget,
7650 SelectionDAG &DAG) {
7651 if (!Subtarget->hasAVX())
7653 if (VT.isInteger() && !Subtarget->hasAVX2())
7656 // Check that the mask is a broadcast.
7657 int BroadcastIdx = -1;
7659 if (M >= 0 && BroadcastIdx == -1)
7661 else if (M >= 0 && M != BroadcastIdx)
7664 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7665 "a sorted mask where the broadcast "
7668 // Go up the chain of (vector) values to find a scalar load that we can
7669 // combine with the broadcast.
7671 switch (V.getOpcode()) {
7672 case ISD::CONCAT_VECTORS: {
7673 int OperandSize = Mask.size() / V.getNumOperands();
7674 V = V.getOperand(BroadcastIdx / OperandSize);
7675 BroadcastIdx %= OperandSize;
7679 case ISD::INSERT_SUBVECTOR: {
7680 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7681 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7685 int BeginIdx = (int)ConstantIdx->getZExtValue();
7687 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7688 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7689 BroadcastIdx -= BeginIdx;
7700 // Check if this is a broadcast of a scalar. We special case lowering
7701 // for scalars so that we can more effectively fold with loads.
7702 // First, look through bitcast: if the original value has a larger element
7703 // type than the shuffle, the broadcast element is in essence truncated.
7704 // Make that explicit to ease folding.
7705 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7706 EVT EltVT = VT.getVectorElementType();
7707 SDValue V0 = V.getOperand(0);
7708 EVT V0VT = V0.getValueType();
7710 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7711 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7712 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7713 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7718 // Also check the simpler case, where we can directly reuse the scalar.
7719 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7720 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7721 V = V.getOperand(BroadcastIdx);
7723 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7724 // Only AVX2 has register broadcasts.
7725 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7727 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7728 // We can't broadcast from a vector register without AVX2, and we can only
7729 // broadcast from the zero-element of a vector register.
7733 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7736 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7737 // INSERTPS when the V1 elements are already in the correct locations
7738 // because otherwise we can just always use two SHUFPS instructions which
7739 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7740 // perform INSERTPS if a single V1 element is out of place and all V2
7741 // elements are zeroable.
7742 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7744 SelectionDAG &DAG) {
7745 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7746 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7747 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7748 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7750 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7753 int V1DstIndex = -1;
7754 int V2DstIndex = -1;
7755 bool V1UsedInPlace = false;
7757 for (int i = 0; i < 4; ++i) {
7758 // Synthesize a zero mask from the zeroable elements (includes undefs).
7764 // Flag if we use any V1 inputs in place.
7766 V1UsedInPlace = true;
7770 // We can only insert a single non-zeroable element.
7771 if (V1DstIndex != -1 || V2DstIndex != -1)
7775 // V1 input out of place for insertion.
7778 // V2 input for insertion.
7783 // Don't bother if we have no (non-zeroable) element for insertion.
7784 if (V1DstIndex == -1 && V2DstIndex == -1)
7787 // Determine element insertion src/dst indices. The src index is from the
7788 // start of the inserted vector, not the start of the concatenated vector.
7789 unsigned V2SrcIndex = 0;
7790 if (V1DstIndex != -1) {
7791 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7792 // and don't use the original V2 at all.
7793 V2SrcIndex = Mask[V1DstIndex];
7794 V2DstIndex = V1DstIndex;
7797 V2SrcIndex = Mask[V2DstIndex] - 4;
7800 // If no V1 inputs are used in place, then the result is created only from
7801 // the zero mask and the V2 insertion - so remove V1 dependency.
7803 V1 = DAG.getUNDEF(MVT::v4f32);
7805 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7806 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7808 // Insert the V2 element into the desired position.
7810 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7811 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7814 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7815 /// UNPCK instruction.
7817 /// This specifically targets cases where we end up with alternating between
7818 /// the two inputs, and so can permute them into something that feeds a single
7819 /// UNPCK instruction. Note that this routine only targets integer vectors
7820 /// because for floating point vectors we have a generalized SHUFPS lowering
7821 /// strategy that handles everything that doesn't *exactly* match an unpack,
7822 /// making this clever lowering unnecessary.
7823 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7824 SDValue V2, ArrayRef<int> Mask,
7825 SelectionDAG &DAG) {
7826 assert(!VT.isFloatingPoint() &&
7827 "This routine only supports integer vectors.");
7828 assert(!isSingleInputShuffleMask(Mask) &&
7829 "This routine should only be used when blending two inputs.");
7830 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7832 int Size = Mask.size();
7834 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7835 return M >= 0 && M % Size < Size / 2;
7837 int NumHiInputs = std::count_if(
7838 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7840 bool UnpackLo = NumLoInputs >= NumHiInputs;
7842 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7843 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7844 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7846 for (int i = 0; i < Size; ++i) {
7850 // Each element of the unpack contains Scale elements from this mask.
7851 int UnpackIdx = i / Scale;
7853 // We only handle the case where V1 feeds the first slots of the unpack.
7854 // We rely on canonicalization to ensure this is the case.
7855 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7858 // Setup the mask for this input. The indexing is tricky as we have to
7859 // handle the unpack stride.
7860 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7861 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7865 // If we will have to shuffle both inputs to use the unpack, check whether
7866 // we can just unpack first and shuffle the result. If so, skip this unpack.
7867 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7868 !isNoopShuffleMask(V2Mask))
7871 // Shuffle the inputs into place.
7872 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7873 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7875 // Cast the inputs to the type we will use to unpack them.
7876 V1 = DAG.getBitcast(UnpackVT, V1);
7877 V2 = DAG.getBitcast(UnpackVT, V2);
7879 // Unpack the inputs and cast the result back to the desired type.
7880 return DAG.getBitcast(
7881 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7885 // We try each unpack from the largest to the smallest to try and find one
7886 // that fits this mask.
7887 int OrigNumElements = VT.getVectorNumElements();
7888 int OrigScalarSize = VT.getScalarSizeInBits();
7889 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7890 int Scale = ScalarSize / OrigScalarSize;
7891 int NumElements = OrigNumElements / Scale;
7892 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7893 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7897 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7899 if (NumLoInputs == 0 || NumHiInputs == 0) {
7900 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7901 "We have to have *some* inputs!");
7902 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7904 // FIXME: We could consider the total complexity of the permute of each
7905 // possible unpacking. Or at the least we should consider how many
7906 // half-crossings are created.
7907 // FIXME: We could consider commuting the unpacks.
7909 SmallVector<int, 32> PermMask;
7910 PermMask.assign(Size, -1);
7911 for (int i = 0; i < Size; ++i) {
7915 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7918 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7920 return DAG.getVectorShuffle(
7921 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7923 DAG.getUNDEF(VT), PermMask);
7929 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7931 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7932 /// support for floating point shuffles but not integer shuffles. These
7933 /// instructions will incur a domain crossing penalty on some chips though so
7934 /// it is better to avoid lowering through this for integer vectors where
7936 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7937 const X86Subtarget *Subtarget,
7938 SelectionDAG &DAG) {
7940 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7941 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7942 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7943 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7944 ArrayRef<int> Mask = SVOp->getMask();
7945 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7947 if (isSingleInputShuffleMask(Mask)) {
7948 // Use low duplicate instructions for masks that match their pattern.
7949 if (Subtarget->hasSSE3())
7950 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7951 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7953 // Straight shuffle of a single input vector. Simulate this by using the
7954 // single input as both of the "inputs" to this instruction..
7955 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7957 if (Subtarget->hasAVX()) {
7958 // If we have AVX, we can use VPERMILPS which will allow folding a load
7959 // into the shuffle.
7960 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7961 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7964 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7965 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7967 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7968 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7970 // If we have a single input, insert that into V1 if we can do so cheaply.
7971 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7972 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7973 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7975 // Try inverting the insertion since for v2 masks it is easy to do and we
7976 // can't reliably sort the mask one way or the other.
7977 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7978 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7979 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7980 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7984 // Try to use one of the special instruction patterns to handle two common
7985 // blend patterns if a zero-blend above didn't work.
7986 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7987 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7988 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7989 // We can either use a special instruction to load over the low double or
7990 // to move just the low double.
7992 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7994 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7996 if (Subtarget->hasSSE41())
7997 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8001 // Use dedicated unpack instructions for masks that match their pattern.
8002 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8003 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8004 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8005 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8007 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8008 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8009 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8012 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8014 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8015 /// the integer unit to minimize domain crossing penalties. However, for blends
8016 /// it falls back to the floating point shuffle operation with appropriate bit
8018 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8019 const X86Subtarget *Subtarget,
8020 SelectionDAG &DAG) {
8022 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8023 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8024 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8025 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8026 ArrayRef<int> Mask = SVOp->getMask();
8027 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8029 if (isSingleInputShuffleMask(Mask)) {
8030 // Check for being able to broadcast a single element.
8031 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8032 Mask, Subtarget, DAG))
8035 // Straight shuffle of a single input vector. For everything from SSE2
8036 // onward this has a single fast instruction with no scary immediates.
8037 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8038 V1 = DAG.getBitcast(MVT::v4i32, V1);
8039 int WidenedMask[4] = {
8040 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8041 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8042 return DAG.getBitcast(
8044 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8045 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8047 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8048 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8049 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8050 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8052 // If we have a blend of two PACKUS operations an the blend aligns with the
8053 // low and half halves, we can just merge the PACKUS operations. This is
8054 // particularly important as it lets us merge shuffles that this routine itself
8056 auto GetPackNode = [](SDValue V) {
8057 while (V.getOpcode() == ISD::BITCAST)
8058 V = V.getOperand(0);
8060 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8062 if (SDValue V1Pack = GetPackNode(V1))
8063 if (SDValue V2Pack = GetPackNode(V2))
8064 return DAG.getBitcast(MVT::v2i64,
8065 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8066 Mask[0] == 0 ? V1Pack.getOperand(0)
8067 : V1Pack.getOperand(1),
8068 Mask[1] == 2 ? V2Pack.getOperand(0)
8069 : V2Pack.getOperand(1)));
8071 // Try to use shift instructions.
8073 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8076 // When loading a scalar and then shuffling it into a vector we can often do
8077 // the insertion cheaply.
8078 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8079 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8081 // Try inverting the insertion since for v2 masks it is easy to do and we
8082 // can't reliably sort the mask one way or the other.
8083 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8084 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8085 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8088 // We have different paths for blend lowering, but they all must use the
8089 // *exact* same predicate.
8090 bool IsBlendSupported = Subtarget->hasSSE41();
8091 if (IsBlendSupported)
8092 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8096 // Use dedicated unpack instructions for masks that match their pattern.
8097 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8098 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8099 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8100 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8102 // Try to use byte rotation instructions.
8103 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8104 if (Subtarget->hasSSSE3())
8105 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8106 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8109 // If we have direct support for blends, we should lower by decomposing into
8110 // a permute. That will be faster than the domain cross.
8111 if (IsBlendSupported)
8112 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8115 // We implement this with SHUFPD which is pretty lame because it will likely
8116 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8117 // However, all the alternatives are still more cycles and newer chips don't
8118 // have this problem. It would be really nice if x86 had better shuffles here.
8119 V1 = DAG.getBitcast(MVT::v2f64, V1);
8120 V2 = DAG.getBitcast(MVT::v2f64, V2);
8121 return DAG.getBitcast(MVT::v2i64,
8122 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8125 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8127 /// This is used to disable more specialized lowerings when the shufps lowering
8128 /// will happen to be efficient.
8129 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8130 // This routine only handles 128-bit shufps.
8131 assert(Mask.size() == 4 && "Unsupported mask size!");
8133 // To lower with a single SHUFPS we need to have the low half and high half
8134 // each requiring a single input.
8135 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8137 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8143 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8145 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8146 /// It makes no assumptions about whether this is the *best* lowering, it simply
8148 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8149 ArrayRef<int> Mask, SDValue V1,
8150 SDValue V2, SelectionDAG &DAG) {
8151 SDValue LowV = V1, HighV = V2;
8152 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8155 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8157 if (NumV2Elements == 1) {
8159 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8162 // Compute the index adjacent to V2Index and in the same half by toggling
8164 int V2AdjIndex = V2Index ^ 1;
8166 if (Mask[V2AdjIndex] == -1) {
8167 // Handles all the cases where we have a single V2 element and an undef.
8168 // This will only ever happen in the high lanes because we commute the
8169 // vector otherwise.
8171 std::swap(LowV, HighV);
8172 NewMask[V2Index] -= 4;
8174 // Handle the case where the V2 element ends up adjacent to a V1 element.
8175 // To make this work, blend them together as the first step.
8176 int V1Index = V2AdjIndex;
8177 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8178 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8179 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8181 // Now proceed to reconstruct the final blend as we have the necessary
8182 // high or low half formed.
8189 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8190 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8192 } else if (NumV2Elements == 2) {
8193 if (Mask[0] < 4 && Mask[1] < 4) {
8194 // Handle the easy case where we have V1 in the low lanes and V2 in the
8198 } else if (Mask[2] < 4 && Mask[3] < 4) {
8199 // We also handle the reversed case because this utility may get called
8200 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8201 // arrange things in the right direction.
8207 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8208 // trying to place elements directly, just blend them and set up the final
8209 // shuffle to place them.
8211 // The first two blend mask elements are for V1, the second two are for
8213 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8214 Mask[2] < 4 ? Mask[2] : Mask[3],
8215 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8216 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8217 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8218 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8220 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8223 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8224 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8225 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8226 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8229 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8230 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8233 /// \brief Lower 4-lane 32-bit floating point shuffles.
8235 /// Uses instructions exclusively from the floating point unit to minimize
8236 /// domain crossing penalties, as these are sufficient to implement all v4f32
8238 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8239 const X86Subtarget *Subtarget,
8240 SelectionDAG &DAG) {
8242 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8243 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8244 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8245 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8246 ArrayRef<int> Mask = SVOp->getMask();
8247 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8250 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8252 if (NumV2Elements == 0) {
8253 // Check for being able to broadcast a single element.
8254 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8255 Mask, Subtarget, DAG))
8258 // Use even/odd duplicate instructions for masks that match their pattern.
8259 if (Subtarget->hasSSE3()) {
8260 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8261 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8262 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8263 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8266 if (Subtarget->hasAVX()) {
8267 // If we have AVX, we can use VPERMILPS which will allow folding a load
8268 // into the shuffle.
8269 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8270 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8273 // Otherwise, use a straight shuffle of a single input vector. We pass the
8274 // input vector to both operands to simulate this with a SHUFPS.
8275 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8276 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8279 // There are special ways we can lower some single-element blends. However, we
8280 // have custom ways we can lower more complex single-element blends below that
8281 // we defer to if both this and BLENDPS fail to match, so restrict this to
8282 // when the V2 input is targeting element 0 of the mask -- that is the fast
8284 if (NumV2Elements == 1 && Mask[0] >= 4)
8285 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8286 Mask, Subtarget, DAG))
8289 if (Subtarget->hasSSE41()) {
8290 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8294 // Use INSERTPS if we can complete the shuffle efficiently.
8295 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8298 if (!isSingleSHUFPSMask(Mask))
8299 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8300 DL, MVT::v4f32, V1, V2, Mask, DAG))
8304 // Use dedicated unpack instructions for masks that match their pattern.
8305 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8306 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8307 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8308 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8309 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8310 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8311 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8312 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8314 // Otherwise fall back to a SHUFPS lowering strategy.
8315 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8318 /// \brief Lower 4-lane i32 vector shuffles.
8320 /// We try to handle these with integer-domain shuffles where we can, but for
8321 /// blends we use the floating point domain blend instructions.
8322 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8323 const X86Subtarget *Subtarget,
8324 SelectionDAG &DAG) {
8326 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8327 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8328 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8330 ArrayRef<int> Mask = SVOp->getMask();
8331 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8333 // Whenever we can lower this as a zext, that instruction is strictly faster
8334 // than any alternative. It also allows us to fold memory operands into the
8335 // shuffle in many cases.
8336 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8337 Mask, Subtarget, DAG))
8341 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8343 if (NumV2Elements == 0) {
8344 // Check for being able to broadcast a single element.
8345 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8346 Mask, Subtarget, DAG))
8349 // Straight shuffle of a single input vector. For everything from SSE2
8350 // onward this has a single fast instruction with no scary immediates.
8351 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8352 // but we aren't actually going to use the UNPCK instruction because doing
8353 // so prevents folding a load into this instruction or making a copy.
8354 const int UnpackLoMask[] = {0, 0, 1, 1};
8355 const int UnpackHiMask[] = {2, 2, 3, 3};
8356 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8357 Mask = UnpackLoMask;
8358 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8359 Mask = UnpackHiMask;
8361 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8362 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8365 // Try to use shift instructions.
8367 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8370 // There are special ways we can lower some single-element blends.
8371 if (NumV2Elements == 1)
8372 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8373 Mask, Subtarget, DAG))
8376 // We have different paths for blend lowering, but they all must use the
8377 // *exact* same predicate.
8378 bool IsBlendSupported = Subtarget->hasSSE41();
8379 if (IsBlendSupported)
8380 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8384 if (SDValue Masked =
8385 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8388 // Use dedicated unpack instructions for masks that match their pattern.
8389 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8390 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8391 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8392 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8393 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8394 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8395 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8396 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8398 // Try to use byte rotation instructions.
8399 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8400 if (Subtarget->hasSSSE3())
8401 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8402 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8405 // If we have direct support for blends, we should lower by decomposing into
8406 // a permute. That will be faster than the domain cross.
8407 if (IsBlendSupported)
8408 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8411 // Try to lower by permuting the inputs into an unpack instruction.
8412 if (SDValue Unpack =
8413 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
8416 // We implement this with SHUFPS because it can blend from two vectors.
8417 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8418 // up the inputs, bypassing domain shift penalties that we would encur if we
8419 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8421 return DAG.getBitcast(
8423 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8424 DAG.getBitcast(MVT::v4f32, V2), Mask));
8427 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8428 /// shuffle lowering, and the most complex part.
8430 /// The lowering strategy is to try to form pairs of input lanes which are
8431 /// targeted at the same half of the final vector, and then use a dword shuffle
8432 /// to place them onto the right half, and finally unpack the paired lanes into
8433 /// their final position.
8435 /// The exact breakdown of how to form these dword pairs and align them on the
8436 /// correct sides is really tricky. See the comments within the function for
8437 /// more of the details.
8439 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8440 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8441 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8442 /// vector, form the analogous 128-bit 8-element Mask.
8443 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8444 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8445 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8446 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8447 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8449 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8450 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8451 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8453 SmallVector<int, 4> LoInputs;
8454 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8455 [](int M) { return M >= 0; });
8456 std::sort(LoInputs.begin(), LoInputs.end());
8457 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8458 SmallVector<int, 4> HiInputs;
8459 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8460 [](int M) { return M >= 0; });
8461 std::sort(HiInputs.begin(), HiInputs.end());
8462 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8464 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8465 int NumHToL = LoInputs.size() - NumLToL;
8467 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8468 int NumHToH = HiInputs.size() - NumLToH;
8469 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8470 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8471 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8472 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8474 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8475 // such inputs we can swap two of the dwords across the half mark and end up
8476 // with <=2 inputs to each half in each half. Once there, we can fall through
8477 // to the generic code below. For example:
8479 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8480 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8482 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8483 // and an existing 2-into-2 on the other half. In this case we may have to
8484 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8485 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8486 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8487 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8488 // half than the one we target for fixing) will be fixed when we re-enter this
8489 // path. We will also combine away any sequence of PSHUFD instructions that
8490 // result into a single instruction. Here is an example of the tricky case:
8492 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8493 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8495 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8497 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8498 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8500 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8501 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8503 // The result is fine to be handled by the generic logic.
8504 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8505 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8506 int AOffset, int BOffset) {
8507 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8508 "Must call this with A having 3 or 1 inputs from the A half.");
8509 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8510 "Must call this with B having 1 or 3 inputs from the B half.");
8511 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8512 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8514 bool ThreeAInputs = AToAInputs.size() == 3;
8516 // Compute the index of dword with only one word among the three inputs in
8517 // a half by taking the sum of the half with three inputs and subtracting
8518 // the sum of the actual three inputs. The difference is the remaining
8521 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8522 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8523 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8524 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8525 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8526 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8527 int TripleNonInputIdx =
8528 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8529 TripleDWord = TripleNonInputIdx / 2;
8531 // We use xor with one to compute the adjacent DWord to whichever one the
8533 OneInputDWord = (OneInput / 2) ^ 1;
8535 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8536 // and BToA inputs. If there is also such a problem with the BToB and AToB
8537 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8538 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8539 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8540 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8541 // Compute how many inputs will be flipped by swapping these DWords. We
8543 // to balance this to ensure we don't form a 3-1 shuffle in the other
8545 int NumFlippedAToBInputs =
8546 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8547 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8548 int NumFlippedBToBInputs =
8549 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8550 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8551 if ((NumFlippedAToBInputs == 1 &&
8552 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8553 (NumFlippedBToBInputs == 1 &&
8554 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8555 // We choose whether to fix the A half or B half based on whether that
8556 // half has zero flipped inputs. At zero, we may not be able to fix it
8557 // with that half. We also bias towards fixing the B half because that
8558 // will more commonly be the high half, and we have to bias one way.
8559 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8560 ArrayRef<int> Inputs) {
8561 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8562 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8563 PinnedIdx ^ 1) != Inputs.end();
8564 // Determine whether the free index is in the flipped dword or the
8565 // unflipped dword based on where the pinned index is. We use this bit
8566 // in an xor to conditionally select the adjacent dword.
8567 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8568 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8569 FixFreeIdx) != Inputs.end();
8570 if (IsFixIdxInput == IsFixFreeIdxInput)
8572 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8573 FixFreeIdx) != Inputs.end();
8574 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8575 "We need to be changing the number of flipped inputs!");
8576 int PSHUFHalfMask[] = {0, 1, 2, 3};
8577 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8578 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8580 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8583 if (M != -1 && M == FixIdx)
8585 else if (M != -1 && M == FixFreeIdx)
8588 if (NumFlippedBToBInputs != 0) {
8590 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8591 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8593 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8594 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8595 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8600 int PSHUFDMask[] = {0, 1, 2, 3};
8601 PSHUFDMask[ADWord] = BDWord;
8602 PSHUFDMask[BDWord] = ADWord;
8605 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8606 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8608 // Adjust the mask to match the new locations of A and B.
8610 if (M != -1 && M/2 == ADWord)
8611 M = 2 * BDWord + M % 2;
8612 else if (M != -1 && M/2 == BDWord)
8613 M = 2 * ADWord + M % 2;
8615 // Recurse back into this routine to re-compute state now that this isn't
8616 // a 3 and 1 problem.
8617 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8620 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8621 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8622 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8623 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8625 // At this point there are at most two inputs to the low and high halves from
8626 // each half. That means the inputs can always be grouped into dwords and
8627 // those dwords can then be moved to the correct half with a dword shuffle.
8628 // We use at most one low and one high word shuffle to collect these paired
8629 // inputs into dwords, and finally a dword shuffle to place them.
8630 int PSHUFLMask[4] = {-1, -1, -1, -1};
8631 int PSHUFHMask[4] = {-1, -1, -1, -1};
8632 int PSHUFDMask[4] = {-1, -1, -1, -1};
8634 // First fix the masks for all the inputs that are staying in their
8635 // original halves. This will then dictate the targets of the cross-half
8637 auto fixInPlaceInputs =
8638 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8639 MutableArrayRef<int> SourceHalfMask,
8640 MutableArrayRef<int> HalfMask, int HalfOffset) {
8641 if (InPlaceInputs.empty())
8643 if (InPlaceInputs.size() == 1) {
8644 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8645 InPlaceInputs[0] - HalfOffset;
8646 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8649 if (IncomingInputs.empty()) {
8650 // Just fix all of the in place inputs.
8651 for (int Input : InPlaceInputs) {
8652 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8653 PSHUFDMask[Input / 2] = Input / 2;
8658 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8659 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8660 InPlaceInputs[0] - HalfOffset;
8661 // Put the second input next to the first so that they are packed into
8662 // a dword. We find the adjacent index by toggling the low bit.
8663 int AdjIndex = InPlaceInputs[0] ^ 1;
8664 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8665 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8666 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8668 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8669 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8671 // Now gather the cross-half inputs and place them into a free dword of
8672 // their target half.
8673 // FIXME: This operation could almost certainly be simplified dramatically to
8674 // look more like the 3-1 fixing operation.
8675 auto moveInputsToRightHalf = [&PSHUFDMask](
8676 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8677 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8678 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8680 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8681 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8683 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8685 int LowWord = Word & ~1;
8686 int HighWord = Word | 1;
8687 return isWordClobbered(SourceHalfMask, LowWord) ||
8688 isWordClobbered(SourceHalfMask, HighWord);
8691 if (IncomingInputs.empty())
8694 if (ExistingInputs.empty()) {
8695 // Map any dwords with inputs from them into the right half.
8696 for (int Input : IncomingInputs) {
8697 // If the source half mask maps over the inputs, turn those into
8698 // swaps and use the swapped lane.
8699 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8700 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8701 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8702 Input - SourceOffset;
8703 // We have to swap the uses in our half mask in one sweep.
8704 for (int &M : HalfMask)
8705 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8707 else if (M == Input)
8708 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8710 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8711 Input - SourceOffset &&
8712 "Previous placement doesn't match!");
8714 // Note that this correctly re-maps both when we do a swap and when
8715 // we observe the other side of the swap above. We rely on that to
8716 // avoid swapping the members of the input list directly.
8717 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8720 // Map the input's dword into the correct half.
8721 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8722 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8724 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8726 "Previous placement doesn't match!");
8729 // And just directly shift any other-half mask elements to be same-half
8730 // as we will have mirrored the dword containing the element into the
8731 // same position within that half.
8732 for (int &M : HalfMask)
8733 if (M >= SourceOffset && M < SourceOffset + 4) {
8734 M = M - SourceOffset + DestOffset;
8735 assert(M >= 0 && "This should never wrap below zero!");
8740 // Ensure we have the input in a viable dword of its current half. This
8741 // is particularly tricky because the original position may be clobbered
8742 // by inputs being moved and *staying* in that half.
8743 if (IncomingInputs.size() == 1) {
8744 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8745 int InputFixed = std::find(std::begin(SourceHalfMask),
8746 std::end(SourceHalfMask), -1) -
8747 std::begin(SourceHalfMask) + SourceOffset;
8748 SourceHalfMask[InputFixed - SourceOffset] =
8749 IncomingInputs[0] - SourceOffset;
8750 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8752 IncomingInputs[0] = InputFixed;
8754 } else if (IncomingInputs.size() == 2) {
8755 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8756 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8757 // We have two non-adjacent or clobbered inputs we need to extract from
8758 // the source half. To do this, we need to map them into some adjacent
8759 // dword slot in the source mask.
8760 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8761 IncomingInputs[1] - SourceOffset};
8763 // If there is a free slot in the source half mask adjacent to one of
8764 // the inputs, place the other input in it. We use (Index XOR 1) to
8765 // compute an adjacent index.
8766 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8767 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8768 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8769 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8770 InputsFixed[1] = InputsFixed[0] ^ 1;
8771 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8772 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8773 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8774 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8775 InputsFixed[0] = InputsFixed[1] ^ 1;
8776 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8777 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8778 // The two inputs are in the same DWord but it is clobbered and the
8779 // adjacent DWord isn't used at all. Move both inputs to the free
8781 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8782 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8783 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8784 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8786 // The only way we hit this point is if there is no clobbering
8787 // (because there are no off-half inputs to this half) and there is no
8788 // free slot adjacent to one of the inputs. In this case, we have to
8789 // swap an input with a non-input.
8790 for (int i = 0; i < 4; ++i)
8791 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8792 "We can't handle any clobbers here!");
8793 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8794 "Cannot have adjacent inputs here!");
8796 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8797 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8799 // We also have to update the final source mask in this case because
8800 // it may need to undo the above swap.
8801 for (int &M : FinalSourceHalfMask)
8802 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8803 M = InputsFixed[1] + SourceOffset;
8804 else if (M == InputsFixed[1] + SourceOffset)
8805 M = (InputsFixed[0] ^ 1) + SourceOffset;
8807 InputsFixed[1] = InputsFixed[0] ^ 1;
8810 // Point everything at the fixed inputs.
8811 for (int &M : HalfMask)
8812 if (M == IncomingInputs[0])
8813 M = InputsFixed[0] + SourceOffset;
8814 else if (M == IncomingInputs[1])
8815 M = InputsFixed[1] + SourceOffset;
8817 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8818 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8821 llvm_unreachable("Unhandled input size!");
8824 // Now hoist the DWord down to the right half.
8825 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8826 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8827 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8828 for (int &M : HalfMask)
8829 for (int Input : IncomingInputs)
8831 M = FreeDWord * 2 + Input % 2;
8833 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8834 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8835 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8836 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8838 // Now enact all the shuffles we've computed to move the inputs into their
8840 if (!isNoopShuffleMask(PSHUFLMask))
8841 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8842 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8843 if (!isNoopShuffleMask(PSHUFHMask))
8844 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8845 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8846 if (!isNoopShuffleMask(PSHUFDMask))
8849 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8850 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8852 // At this point, each half should contain all its inputs, and we can then
8853 // just shuffle them into their final position.
8854 assert(std::count_if(LoMask.begin(), LoMask.end(),
8855 [](int M) { return M >= 4; }) == 0 &&
8856 "Failed to lift all the high half inputs to the low mask!");
8857 assert(std::count_if(HiMask.begin(), HiMask.end(),
8858 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8859 "Failed to lift all the low half inputs to the high mask!");
8861 // Do a half shuffle for the low mask.
8862 if (!isNoopShuffleMask(LoMask))
8863 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8864 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8866 // Do a half shuffle with the high mask after shifting its values down.
8867 for (int &M : HiMask)
8870 if (!isNoopShuffleMask(HiMask))
8871 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8872 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8877 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8878 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8879 SDValue V2, ArrayRef<int> Mask,
8880 SelectionDAG &DAG, bool &V1InUse,
8882 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8888 int Size = Mask.size();
8889 int Scale = 16 / Size;
8890 for (int i = 0; i < 16; ++i) {
8891 if (Mask[i / Scale] == -1) {
8892 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8894 const int ZeroMask = 0x80;
8895 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8897 int V2Idx = Mask[i / Scale] < Size
8899 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8900 if (Zeroable[i / Scale])
8901 V1Idx = V2Idx = ZeroMask;
8902 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8903 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8904 V1InUse |= (ZeroMask != V1Idx);
8905 V2InUse |= (ZeroMask != V2Idx);
8910 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8911 DAG.getBitcast(MVT::v16i8, V1),
8912 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8914 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8915 DAG.getBitcast(MVT::v16i8, V2),
8916 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8918 // If we need shuffled inputs from both, blend the two.
8920 if (V1InUse && V2InUse)
8921 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8923 V = V1InUse ? V1 : V2;
8925 // Cast the result back to the correct type.
8926 return DAG.getBitcast(VT, V);
8929 /// \brief Generic lowering of 8-lane i16 shuffles.
8931 /// This handles both single-input shuffles and combined shuffle/blends with
8932 /// two inputs. The single input shuffles are immediately delegated to
8933 /// a dedicated lowering routine.
8935 /// The blends are lowered in one of three fundamental ways. If there are few
8936 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8937 /// of the input is significantly cheaper when lowered as an interleaving of
8938 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8939 /// halves of the inputs separately (making them have relatively few inputs)
8940 /// and then concatenate them.
8941 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8942 const X86Subtarget *Subtarget,
8943 SelectionDAG &DAG) {
8945 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8946 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8947 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8948 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8949 ArrayRef<int> OrigMask = SVOp->getMask();
8950 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8951 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8952 MutableArrayRef<int> Mask(MaskStorage);
8954 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8956 // Whenever we can lower this as a zext, that instruction is strictly faster
8957 // than any alternative.
8958 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8959 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8962 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8964 auto isV2 = [](int M) { return M >= 8; };
8966 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8968 if (NumV2Inputs == 0) {
8969 // Check for being able to broadcast a single element.
8970 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8971 Mask, Subtarget, DAG))
8974 // Try to use shift instructions.
8976 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8979 // Use dedicated unpack instructions for masks that match their pattern.
8980 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8981 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8982 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8983 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8985 // Try to use byte rotation instructions.
8986 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8987 Mask, Subtarget, DAG))
8990 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8994 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8995 "All single-input shuffles should be canonicalized to be V1-input "
8998 // Try to use shift instructions.
9000 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9003 // See if we can use SSE4A Extraction / Insertion.
9004 if (Subtarget->hasSSE4A())
9005 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9008 // There are special ways we can lower some single-element blends.
9009 if (NumV2Inputs == 1)
9010 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9011 Mask, Subtarget, DAG))
9014 // We have different paths for blend lowering, but they all must use the
9015 // *exact* same predicate.
9016 bool IsBlendSupported = Subtarget->hasSSE41();
9017 if (IsBlendSupported)
9018 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9022 if (SDValue Masked =
9023 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9026 // Use dedicated unpack instructions for masks that match their pattern.
9027 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9028 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9029 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9030 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9032 // Try to use byte rotation instructions.
9033 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9034 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9037 if (SDValue BitBlend =
9038 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9041 if (SDValue Unpack =
9042 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
9045 // If we can't directly blend but can use PSHUFB, that will be better as it
9046 // can both shuffle and set up the inefficient blend.
9047 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9048 bool V1InUse, V2InUse;
9049 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9053 // We can always bit-blend if we have to so the fallback strategy is to
9054 // decompose into single-input permutes and blends.
9055 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9059 /// \brief Check whether a compaction lowering can be done by dropping even
9060 /// elements and compute how many times even elements must be dropped.
9062 /// This handles shuffles which take every Nth element where N is a power of
9063 /// two. Example shuffle masks:
9065 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9066 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9067 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9068 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9069 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9070 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9072 /// Any of these lanes can of course be undef.
9074 /// This routine only supports N <= 3.
9075 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9078 /// \returns N above, or the number of times even elements must be dropped if
9079 /// there is such a number. Otherwise returns zero.
9080 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9081 // Figure out whether we're looping over two inputs or just one.
9082 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9084 // The modulus for the shuffle vector entries is based on whether this is
9085 // a single input or not.
9086 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9087 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9088 "We should only be called with masks with a power-of-2 size!");
9090 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9092 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9093 // and 2^3 simultaneously. This is because we may have ambiguity with
9094 // partially undef inputs.
9095 bool ViableForN[3] = {true, true, true};
9097 for (int i = 0, e = Mask.size(); i < e; ++i) {
9098 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9103 bool IsAnyViable = false;
9104 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9105 if (ViableForN[j]) {
9108 // The shuffle mask must be equal to (i * 2^N) % M.
9109 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9112 ViableForN[j] = false;
9114 // Early exit if we exhaust the possible powers of two.
9119 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9123 // Return 0 as there is no viable power of two.
9127 /// \brief Generic lowering of v16i8 shuffles.
9129 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9130 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9131 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9132 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9134 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9135 const X86Subtarget *Subtarget,
9136 SelectionDAG &DAG) {
9138 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9139 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9140 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9141 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9142 ArrayRef<int> Mask = SVOp->getMask();
9143 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9145 // Try to use shift instructions.
9147 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9150 // Try to use byte rotation instructions.
9151 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9152 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9155 // Try to use a zext lowering.
9156 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9157 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9160 // See if we can use SSE4A Extraction / Insertion.
9161 if (Subtarget->hasSSE4A())
9162 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9166 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9168 // For single-input shuffles, there are some nicer lowering tricks we can use.
9169 if (NumV2Elements == 0) {
9170 // Check for being able to broadcast a single element.
9171 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9172 Mask, Subtarget, DAG))
9175 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9176 // Notably, this handles splat and partial-splat shuffles more efficiently.
9177 // However, it only makes sense if the pre-duplication shuffle simplifies
9178 // things significantly. Currently, this means we need to be able to
9179 // express the pre-duplication shuffle as an i16 shuffle.
9181 // FIXME: We should check for other patterns which can be widened into an
9182 // i16 shuffle as well.
9183 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9184 for (int i = 0; i < 16; i += 2)
9185 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9190 auto tryToWidenViaDuplication = [&]() -> SDValue {
9191 if (!canWidenViaDuplication(Mask))
9193 SmallVector<int, 4> LoInputs;
9194 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9195 [](int M) { return M >= 0 && M < 8; });
9196 std::sort(LoInputs.begin(), LoInputs.end());
9197 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9199 SmallVector<int, 4> HiInputs;
9200 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9201 [](int M) { return M >= 8; });
9202 std::sort(HiInputs.begin(), HiInputs.end());
9203 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9206 bool TargetLo = LoInputs.size() >= HiInputs.size();
9207 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9208 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9210 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9211 SmallDenseMap<int, int, 8> LaneMap;
9212 for (int I : InPlaceInputs) {
9213 PreDupI16Shuffle[I/2] = I/2;
9216 int j = TargetLo ? 0 : 4, je = j + 4;
9217 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9218 // Check if j is already a shuffle of this input. This happens when
9219 // there are two adjacent bytes after we move the low one.
9220 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9221 // If we haven't yet mapped the input, search for a slot into which
9223 while (j < je && PreDupI16Shuffle[j] != -1)
9227 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9230 // Map this input with the i16 shuffle.
9231 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9234 // Update the lane map based on the mapping we ended up with.
9235 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9237 V1 = DAG.getBitcast(
9239 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9240 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9242 // Unpack the bytes to form the i16s that will be shuffled into place.
9243 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9244 MVT::v16i8, V1, V1);
9246 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9247 for (int i = 0; i < 16; ++i)
9248 if (Mask[i] != -1) {
9249 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9250 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9251 if (PostDupI16Shuffle[i / 2] == -1)
9252 PostDupI16Shuffle[i / 2] = MappedMask;
9254 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9255 "Conflicting entrties in the original shuffle!");
9257 return DAG.getBitcast(
9259 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9260 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9262 if (SDValue V = tryToWidenViaDuplication())
9266 if (SDValue Masked =
9267 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9270 // Use dedicated unpack instructions for masks that match their pattern.
9271 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9272 0, 16, 1, 17, 2, 18, 3, 19,
9274 4, 20, 5, 21, 6, 22, 7, 23}))
9275 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9276 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9277 8, 24, 9, 25, 10, 26, 11, 27,
9279 12, 28, 13, 29, 14, 30, 15, 31}))
9280 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9282 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9283 // with PSHUFB. It is important to do this before we attempt to generate any
9284 // blends but after all of the single-input lowerings. If the single input
9285 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9286 // want to preserve that and we can DAG combine any longer sequences into
9287 // a PSHUFB in the end. But once we start blending from multiple inputs,
9288 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9289 // and there are *very* few patterns that would actually be faster than the
9290 // PSHUFB approach because of its ability to zero lanes.
9292 // FIXME: The only exceptions to the above are blends which are exact
9293 // interleavings with direct instructions supporting them. We currently don't
9294 // handle those well here.
9295 if (Subtarget->hasSSSE3()) {
9296 bool V1InUse = false;
9297 bool V2InUse = false;
9299 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9300 DAG, V1InUse, V2InUse);
9302 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9303 // do so. This avoids using them to handle blends-with-zero which is
9304 // important as a single pshufb is significantly faster for that.
9305 if (V1InUse && V2InUse) {
9306 if (Subtarget->hasSSE41())
9307 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9308 Mask, Subtarget, DAG))
9311 // We can use an unpack to do the blending rather than an or in some
9312 // cases. Even though the or may be (very minorly) more efficient, we
9313 // preference this lowering because there are common cases where part of
9314 // the complexity of the shuffles goes away when we do the final blend as
9316 // FIXME: It might be worth trying to detect if the unpack-feeding
9317 // shuffles will both be pshufb, in which case we shouldn't bother with
9319 if (SDValue Unpack =
9320 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
9327 // There are special ways we can lower some single-element blends.
9328 if (NumV2Elements == 1)
9329 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9330 Mask, Subtarget, DAG))
9333 if (SDValue BitBlend =
9334 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9337 // Check whether a compaction lowering can be done. This handles shuffles
9338 // which take every Nth element for some even N. See the helper function for
9341 // We special case these as they can be particularly efficiently handled with
9342 // the PACKUSB instruction on x86 and they show up in common patterns of
9343 // rearranging bytes to truncate wide elements.
9344 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9345 // NumEvenDrops is the power of two stride of the elements. Another way of
9346 // thinking about it is that we need to drop the even elements this many
9347 // times to get the original input.
9348 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9350 // First we need to zero all the dropped bytes.
9351 assert(NumEvenDrops <= 3 &&
9352 "No support for dropping even elements more than 3 times.");
9353 // We use the mask type to pick which bytes are preserved based on how many
9354 // elements are dropped.
9355 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9356 SDValue ByteClearMask = DAG.getBitcast(
9357 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9358 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9360 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9362 // Now pack things back together.
9363 V1 = DAG.getBitcast(MVT::v8i16, V1);
9364 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9365 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9366 for (int i = 1; i < NumEvenDrops; ++i) {
9367 Result = DAG.getBitcast(MVT::v8i16, Result);
9368 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9374 // Handle multi-input cases by blending single-input shuffles.
9375 if (NumV2Elements > 0)
9376 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9379 // The fallback path for single-input shuffles widens this into two v8i16
9380 // vectors with unpacks, shuffles those, and then pulls them back together
9384 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9385 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9386 for (int i = 0; i < 16; ++i)
9388 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9390 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9392 SDValue VLoHalf, VHiHalf;
9393 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9394 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9396 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9397 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9398 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9399 [](int M) { return M >= 0 && M % 2 == 1; })) {
9400 // Use a mask to drop the high bytes.
9401 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9402 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9403 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9405 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9406 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9408 // Squash the masks to point directly into VLoHalf.
9409 for (int &M : LoBlendMask)
9412 for (int &M : HiBlendMask)
9416 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9417 // VHiHalf so that we can blend them as i16s.
9418 VLoHalf = DAG.getBitcast(
9419 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9420 VHiHalf = DAG.getBitcast(
9421 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9424 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9425 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9427 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9430 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9432 /// This routine breaks down the specific type of 128-bit shuffle and
9433 /// dispatches to the lowering routines accordingly.
9434 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9435 MVT VT, const X86Subtarget *Subtarget,
9436 SelectionDAG &DAG) {
9437 switch (VT.SimpleTy) {
9439 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9441 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9443 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9445 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9447 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9449 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9452 llvm_unreachable("Unimplemented!");
9456 /// \brief Helper function to test whether a shuffle mask could be
9457 /// simplified by widening the elements being shuffled.
9459 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9460 /// leaves it in an unspecified state.
9462 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9463 /// shuffle masks. The latter have the special property of a '-2' representing
9464 /// a zero-ed lane of a vector.
9465 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9466 SmallVectorImpl<int> &WidenedMask) {
9467 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9468 // If both elements are undef, its trivial.
9469 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9470 WidenedMask.push_back(SM_SentinelUndef);
9474 // Check for an undef mask and a mask value properly aligned to fit with
9475 // a pair of values. If we find such a case, use the non-undef mask's value.
9476 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9477 WidenedMask.push_back(Mask[i + 1] / 2);
9480 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9481 WidenedMask.push_back(Mask[i] / 2);
9485 // When zeroing, we need to spread the zeroing across both lanes to widen.
9486 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9487 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9488 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9489 WidenedMask.push_back(SM_SentinelZero);
9495 // Finally check if the two mask values are adjacent and aligned with
9497 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9498 WidenedMask.push_back(Mask[i] / 2);
9502 // Otherwise we can't safely widen the elements used in this shuffle.
9505 assert(WidenedMask.size() == Mask.size() / 2 &&
9506 "Incorrect size of mask after widening the elements!");
9511 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9513 /// This routine just extracts two subvectors, shuffles them independently, and
9514 /// then concatenates them back together. This should work effectively with all
9515 /// AVX vector shuffle types.
9516 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9517 SDValue V2, ArrayRef<int> Mask,
9518 SelectionDAG &DAG) {
9519 assert(VT.getSizeInBits() >= 256 &&
9520 "Only for 256-bit or wider vector shuffles!");
9521 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9522 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9524 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9525 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9527 int NumElements = VT.getVectorNumElements();
9528 int SplitNumElements = NumElements / 2;
9529 MVT ScalarVT = VT.getScalarType();
9530 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9532 // Rather than splitting build-vectors, just build two narrower build
9533 // vectors. This helps shuffling with splats and zeros.
9534 auto SplitVector = [&](SDValue V) {
9535 while (V.getOpcode() == ISD::BITCAST)
9536 V = V->getOperand(0);
9538 MVT OrigVT = V.getSimpleValueType();
9539 int OrigNumElements = OrigVT.getVectorNumElements();
9540 int OrigSplitNumElements = OrigNumElements / 2;
9541 MVT OrigScalarVT = OrigVT.getScalarType();
9542 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9546 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9548 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9549 DAG.getIntPtrConstant(0, DL));
9550 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9551 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9554 SmallVector<SDValue, 16> LoOps, HiOps;
9555 for (int i = 0; i < OrigSplitNumElements; ++i) {
9556 LoOps.push_back(BV->getOperand(i));
9557 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9559 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9560 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9562 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9563 DAG.getBitcast(SplitVT, HiV));
9566 SDValue LoV1, HiV1, LoV2, HiV2;
9567 std::tie(LoV1, HiV1) = SplitVector(V1);
9568 std::tie(LoV2, HiV2) = SplitVector(V2);
9570 // Now create two 4-way blends of these half-width vectors.
9571 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9572 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9573 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9574 for (int i = 0; i < SplitNumElements; ++i) {
9575 int M = HalfMask[i];
9576 if (M >= NumElements) {
9577 if (M >= NumElements + SplitNumElements)
9581 V2BlendMask.push_back(M - NumElements);
9582 V1BlendMask.push_back(-1);
9583 BlendMask.push_back(SplitNumElements + i);
9584 } else if (M >= 0) {
9585 if (M >= SplitNumElements)
9589 V2BlendMask.push_back(-1);
9590 V1BlendMask.push_back(M);
9591 BlendMask.push_back(i);
9593 V2BlendMask.push_back(-1);
9594 V1BlendMask.push_back(-1);
9595 BlendMask.push_back(-1);
9599 // Because the lowering happens after all combining takes place, we need to
9600 // manually combine these blend masks as much as possible so that we create
9601 // a minimal number of high-level vector shuffle nodes.
9603 // First try just blending the halves of V1 or V2.
9604 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9605 return DAG.getUNDEF(SplitVT);
9606 if (!UseLoV2 && !UseHiV2)
9607 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9608 if (!UseLoV1 && !UseHiV1)
9609 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9611 SDValue V1Blend, V2Blend;
9612 if (UseLoV1 && UseHiV1) {
9614 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9616 // We only use half of V1 so map the usage down into the final blend mask.
9617 V1Blend = UseLoV1 ? LoV1 : HiV1;
9618 for (int i = 0; i < SplitNumElements; ++i)
9619 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9620 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9622 if (UseLoV2 && UseHiV2) {
9624 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9626 // We only use half of V2 so map the usage down into the final blend mask.
9627 V2Blend = UseLoV2 ? LoV2 : HiV2;
9628 for (int i = 0; i < SplitNumElements; ++i)
9629 if (BlendMask[i] >= SplitNumElements)
9630 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9632 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9634 SDValue Lo = HalfBlend(LoMask);
9635 SDValue Hi = HalfBlend(HiMask);
9636 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9639 /// \brief Either split a vector in halves or decompose the shuffles and the
9642 /// This is provided as a good fallback for many lowerings of non-single-input
9643 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9644 /// between splitting the shuffle into 128-bit components and stitching those
9645 /// back together vs. extracting the single-input shuffles and blending those
9647 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9648 SDValue V2, ArrayRef<int> Mask,
9649 SelectionDAG &DAG) {
9650 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9651 "lower single-input shuffles as it "
9652 "could then recurse on itself.");
9653 int Size = Mask.size();
9655 // If this can be modeled as a broadcast of two elements followed by a blend,
9656 // prefer that lowering. This is especially important because broadcasts can
9657 // often fold with memory operands.
9658 auto DoBothBroadcast = [&] {
9659 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9662 if (V2BroadcastIdx == -1)
9663 V2BroadcastIdx = M - Size;
9664 else if (M - Size != V2BroadcastIdx)
9666 } else if (M >= 0) {
9667 if (V1BroadcastIdx == -1)
9669 else if (M != V1BroadcastIdx)
9674 if (DoBothBroadcast())
9675 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9678 // If the inputs all stem from a single 128-bit lane of each input, then we
9679 // split them rather than blending because the split will decompose to
9680 // unusually few instructions.
9681 int LaneCount = VT.getSizeInBits() / 128;
9682 int LaneSize = Size / LaneCount;
9683 SmallBitVector LaneInputs[2];
9684 LaneInputs[0].resize(LaneCount, false);
9685 LaneInputs[1].resize(LaneCount, false);
9686 for (int i = 0; i < Size; ++i)
9688 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9689 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9690 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9692 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9693 // that the decomposed single-input shuffles don't end up here.
9694 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9697 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9698 /// a permutation and blend of those lanes.
9700 /// This essentially blends the out-of-lane inputs to each lane into the lane
9701 /// from a permuted copy of the vector. This lowering strategy results in four
9702 /// instructions in the worst case for a single-input cross lane shuffle which
9703 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9704 /// of. Special cases for each particular shuffle pattern should be handled
9705 /// prior to trying this lowering.
9706 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9707 SDValue V1, SDValue V2,
9709 SelectionDAG &DAG) {
9710 // FIXME: This should probably be generalized for 512-bit vectors as well.
9711 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9712 int LaneSize = Mask.size() / 2;
9714 // If there are only inputs from one 128-bit lane, splitting will in fact be
9715 // less expensive. The flags track whether the given lane contains an element
9716 // that crosses to another lane.
9717 bool LaneCrossing[2] = {false, false};
9718 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9719 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9720 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9721 if (!LaneCrossing[0] || !LaneCrossing[1])
9722 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9724 if (isSingleInputShuffleMask(Mask)) {
9725 SmallVector<int, 32> FlippedBlendMask;
9726 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9727 FlippedBlendMask.push_back(
9728 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9730 : Mask[i] % LaneSize +
9731 (i / LaneSize) * LaneSize + Size));
9733 // Flip the vector, and blend the results which should now be in-lane. The
9734 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9735 // 5 for the high source. The value 3 selects the high half of source 2 and
9736 // the value 2 selects the low half of source 2. We only use source 2 to
9737 // allow folding it into a memory operand.
9738 unsigned PERMMask = 3 | 2 << 4;
9739 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9740 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9741 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9744 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9745 // will be handled by the above logic and a blend of the results, much like
9746 // other patterns in AVX.
9747 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9750 /// \brief Handle lowering 2-lane 128-bit shuffles.
9751 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9752 SDValue V2, ArrayRef<int> Mask,
9753 const X86Subtarget *Subtarget,
9754 SelectionDAG &DAG) {
9755 // TODO: If minimizing size and one of the inputs is a zero vector and the
9756 // the zero vector has only one use, we could use a VPERM2X128 to save the
9757 // instruction bytes needed to explicitly generate the zero vector.
9759 // Blends are faster and handle all the non-lane-crossing cases.
9760 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9764 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9765 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9767 // If either input operand is a zero vector, use VPERM2X128 because its mask
9768 // allows us to replace the zero input with an implicit zero.
9769 if (!IsV1Zero && !IsV2Zero) {
9770 // Check for patterns which can be matched with a single insert of a 128-bit
9772 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9773 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9774 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9775 VT.getVectorNumElements() / 2);
9776 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9777 DAG.getIntPtrConstant(0, DL));
9778 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9779 OnlyUsesV1 ? V1 : V2,
9780 DAG.getIntPtrConstant(0, DL));
9781 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9785 // Otherwise form a 128-bit permutation. After accounting for undefs,
9786 // convert the 64-bit shuffle mask selection values into 128-bit
9787 // selection bits by dividing the indexes by 2 and shifting into positions
9788 // defined by a vperm2*128 instruction's immediate control byte.
9790 // The immediate permute control byte looks like this:
9791 // [1:0] - select 128 bits from sources for low half of destination
9793 // [3] - zero low half of destination
9794 // [5:4] - select 128 bits from sources for high half of destination
9796 // [7] - zero high half of destination
9798 int MaskLO = Mask[0];
9799 if (MaskLO == SM_SentinelUndef)
9800 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9802 int MaskHI = Mask[2];
9803 if (MaskHI == SM_SentinelUndef)
9804 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9806 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9808 // If either input is a zero vector, replace it with an undef input.
9809 // Shuffle mask values < 4 are selecting elements of V1.
9810 // Shuffle mask values >= 4 are selecting elements of V2.
9811 // Adjust each half of the permute mask by clearing the half that was
9812 // selecting the zero vector and setting the zero mask bit.
9814 V1 = DAG.getUNDEF(VT);
9816 PermMask = (PermMask & 0xf0) | 0x08;
9818 PermMask = (PermMask & 0x0f) | 0x80;
9821 V2 = DAG.getUNDEF(VT);
9823 PermMask = (PermMask & 0xf0) | 0x08;
9825 PermMask = (PermMask & 0x0f) | 0x80;
9828 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9829 DAG.getConstant(PermMask, DL, MVT::i8));
9832 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9833 /// shuffling each lane.
9835 /// This will only succeed when the result of fixing the 128-bit lanes results
9836 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9837 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9838 /// the lane crosses early and then use simpler shuffles within each lane.
9840 /// FIXME: It might be worthwhile at some point to support this without
9841 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9842 /// in x86 only floating point has interesting non-repeating shuffles, and even
9843 /// those are still *marginally* more expensive.
9844 static SDValue lowerVectorShuffleByMerging128BitLanes(
9845 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9846 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9847 assert(!isSingleInputShuffleMask(Mask) &&
9848 "This is only useful with multiple inputs.");
9850 int Size = Mask.size();
9851 int LaneSize = 128 / VT.getScalarSizeInBits();
9852 int NumLanes = Size / LaneSize;
9853 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9855 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9856 // check whether the in-128-bit lane shuffles share a repeating pattern.
9857 SmallVector<int, 4> Lanes;
9858 Lanes.resize(NumLanes, -1);
9859 SmallVector<int, 4> InLaneMask;
9860 InLaneMask.resize(LaneSize, -1);
9861 for (int i = 0; i < Size; ++i) {
9865 int j = i / LaneSize;
9868 // First entry we've seen for this lane.
9869 Lanes[j] = Mask[i] / LaneSize;
9870 } else if (Lanes[j] != Mask[i] / LaneSize) {
9871 // This doesn't match the lane selected previously!
9875 // Check that within each lane we have a consistent shuffle mask.
9876 int k = i % LaneSize;
9877 if (InLaneMask[k] < 0) {
9878 InLaneMask[k] = Mask[i] % LaneSize;
9879 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9880 // This doesn't fit a repeating in-lane mask.
9885 // First shuffle the lanes into place.
9886 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9887 VT.getSizeInBits() / 64);
9888 SmallVector<int, 8> LaneMask;
9889 LaneMask.resize(NumLanes * 2, -1);
9890 for (int i = 0; i < NumLanes; ++i)
9891 if (Lanes[i] >= 0) {
9892 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9893 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9896 V1 = DAG.getBitcast(LaneVT, V1);
9897 V2 = DAG.getBitcast(LaneVT, V2);
9898 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9900 // Cast it back to the type we actually want.
9901 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9903 // Now do a simple shuffle that isn't lane crossing.
9904 SmallVector<int, 8> NewMask;
9905 NewMask.resize(Size, -1);
9906 for (int i = 0; i < Size; ++i)
9908 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9909 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9910 "Must not introduce lane crosses at this point!");
9912 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9915 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9918 /// This returns true if the elements from a particular input are already in the
9919 /// slot required by the given mask and require no permutation.
9920 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9921 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9922 int Size = Mask.size();
9923 for (int i = 0; i < Size; ++i)
9924 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9930 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9931 ArrayRef<int> Mask, SDValue V1,
9932 SDValue V2, SelectionDAG &DAG) {
9934 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9935 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9936 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9937 int NumElts = VT.getVectorNumElements();
9938 bool ShufpdMask = true;
9939 bool CommutableMask = true;
9940 unsigned Immediate = 0;
9941 for (int i = 0; i < NumElts; ++i) {
9944 int Val = (i & 6) + NumElts * (i & 1);
9945 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9946 if (Mask[i] < Val || Mask[i] > Val + 1)
9948 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9949 CommutableMask = false;
9950 Immediate |= (Mask[i] % 2) << i;
9953 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9954 DAG.getConstant(Immediate, DL, MVT::i8));
9956 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9957 DAG.getConstant(Immediate, DL, MVT::i8));
9961 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9963 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9964 /// isn't available.
9965 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9966 const X86Subtarget *Subtarget,
9967 SelectionDAG &DAG) {
9969 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9970 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9971 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9972 ArrayRef<int> Mask = SVOp->getMask();
9973 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9975 SmallVector<int, 4> WidenedMask;
9976 if (canWidenShuffleElements(Mask, WidenedMask))
9977 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9980 if (isSingleInputShuffleMask(Mask)) {
9981 // Check for being able to broadcast a single element.
9982 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9983 Mask, Subtarget, DAG))
9986 // Use low duplicate instructions for masks that match their pattern.
9987 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9988 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9990 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9991 // Non-half-crossing single input shuffles can be lowerid with an
9992 // interleaved permutation.
9993 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9994 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9995 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9996 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9999 // With AVX2 we have direct support for this permutation.
10000 if (Subtarget->hasAVX2())
10001 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10002 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10004 // Otherwise, fall back.
10005 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10009 // X86 has dedicated unpack instructions that can handle specific blend
10010 // operations: UNPCKH and UNPCKL.
10011 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10012 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10013 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10014 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10015 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10016 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10017 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10018 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10020 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10024 // Check if the blend happens to exactly fit that of SHUFPD.
10026 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10029 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10030 // shuffle. However, if we have AVX2 and either inputs are already in place,
10031 // we will be able to shuffle even across lanes the other input in a single
10032 // instruction so skip this pattern.
10033 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10034 isShuffleMaskInputInPlace(1, Mask))))
10035 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10036 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10039 // If we have AVX2 then we always want to lower with a blend because an v4 we
10040 // can fully permute the elements.
10041 if (Subtarget->hasAVX2())
10042 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10045 // Otherwise fall back on generic lowering.
10046 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10049 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10051 /// This routine is only called when we have AVX2 and thus a reasonable
10052 /// instruction set for v4i64 shuffling..
10053 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10054 const X86Subtarget *Subtarget,
10055 SelectionDAG &DAG) {
10057 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10058 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10059 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10060 ArrayRef<int> Mask = SVOp->getMask();
10061 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10062 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10064 SmallVector<int, 4> WidenedMask;
10065 if (canWidenShuffleElements(Mask, WidenedMask))
10066 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10069 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10073 // Check for being able to broadcast a single element.
10074 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10075 Mask, Subtarget, DAG))
10078 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10079 // use lower latency instructions that will operate on both 128-bit lanes.
10080 SmallVector<int, 2> RepeatedMask;
10081 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10082 if (isSingleInputShuffleMask(Mask)) {
10083 int PSHUFDMask[] = {-1, -1, -1, -1};
10084 for (int i = 0; i < 2; ++i)
10085 if (RepeatedMask[i] >= 0) {
10086 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10087 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10089 return DAG.getBitcast(
10091 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10092 DAG.getBitcast(MVT::v8i32, V1),
10093 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10097 // AVX2 provides a direct instruction for permuting a single input across
10099 if (isSingleInputShuffleMask(Mask))
10100 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10101 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10103 // Try to use shift instructions.
10104 if (SDValue Shift =
10105 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10108 // Use dedicated unpack instructions for masks that match their pattern.
10109 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10110 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10111 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10112 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10113 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10114 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10115 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10116 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10118 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10119 // shuffle. However, if we have AVX2 and either inputs are already in place,
10120 // we will be able to shuffle even across lanes the other input in a single
10121 // instruction so skip this pattern.
10122 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10123 isShuffleMaskInputInPlace(1, Mask))))
10124 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10125 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10128 // Otherwise fall back on generic blend lowering.
10129 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10133 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10135 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10136 /// isn't available.
10137 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10138 const X86Subtarget *Subtarget,
10139 SelectionDAG &DAG) {
10141 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10142 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10143 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10144 ArrayRef<int> Mask = SVOp->getMask();
10145 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10147 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10151 // Check for being able to broadcast a single element.
10152 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10153 Mask, Subtarget, DAG))
10156 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10157 // options to efficiently lower the shuffle.
10158 SmallVector<int, 4> RepeatedMask;
10159 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10160 assert(RepeatedMask.size() == 4 &&
10161 "Repeated masks must be half the mask width!");
10163 // Use even/odd duplicate instructions for masks that match their pattern.
10164 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10165 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10166 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10167 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10169 if (isSingleInputShuffleMask(Mask))
10170 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10171 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10173 // Use dedicated unpack instructions for masks that match their pattern.
10174 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10175 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10176 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10177 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10178 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10179 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10180 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10181 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10183 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10184 // have already handled any direct blends. We also need to squash the
10185 // repeated mask into a simulated v4f32 mask.
10186 for (int i = 0; i < 4; ++i)
10187 if (RepeatedMask[i] >= 8)
10188 RepeatedMask[i] -= 4;
10189 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10192 // If we have a single input shuffle with different shuffle patterns in the
10193 // two 128-bit lanes use the variable mask to VPERMILPS.
10194 if (isSingleInputShuffleMask(Mask)) {
10195 SDValue VPermMask[8];
10196 for (int i = 0; i < 8; ++i)
10197 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10198 : DAG.getConstant(Mask[i], DL, MVT::i32);
10199 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10200 return DAG.getNode(
10201 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10202 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10204 if (Subtarget->hasAVX2())
10205 return DAG.getNode(
10206 X86ISD::VPERMV, DL, MVT::v8f32,
10207 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10208 MVT::v8i32, VPermMask)),
10211 // Otherwise, fall back.
10212 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10216 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10218 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10219 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10222 // If we have AVX2 then we always want to lower with a blend because at v8 we
10223 // can fully permute the elements.
10224 if (Subtarget->hasAVX2())
10225 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10228 // Otherwise fall back on generic lowering.
10229 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10232 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10234 /// This routine is only called when we have AVX2 and thus a reasonable
10235 /// instruction set for v8i32 shuffling..
10236 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10237 const X86Subtarget *Subtarget,
10238 SelectionDAG &DAG) {
10240 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10241 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10242 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10243 ArrayRef<int> Mask = SVOp->getMask();
10244 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10245 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10247 // Whenever we can lower this as a zext, that instruction is strictly faster
10248 // than any alternative. It also allows us to fold memory operands into the
10249 // shuffle in many cases.
10250 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10251 Mask, Subtarget, DAG))
10254 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10258 // Check for being able to broadcast a single element.
10259 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10260 Mask, Subtarget, DAG))
10263 // If the shuffle mask is repeated in each 128-bit lane we can use more
10264 // efficient instructions that mirror the shuffles across the two 128-bit
10266 SmallVector<int, 4> RepeatedMask;
10267 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10268 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10269 if (isSingleInputShuffleMask(Mask))
10270 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10271 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10273 // Use dedicated unpack instructions for masks that match their pattern.
10274 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10275 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10276 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10277 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10278 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10279 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10280 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10281 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10284 // Try to use shift instructions.
10285 if (SDValue Shift =
10286 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10289 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10290 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10293 // If the shuffle patterns aren't repeated but it is a single input, directly
10294 // generate a cross-lane VPERMD instruction.
10295 if (isSingleInputShuffleMask(Mask)) {
10296 SDValue VPermMask[8];
10297 for (int i = 0; i < 8; ++i)
10298 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10299 : DAG.getConstant(Mask[i], DL, MVT::i32);
10300 return DAG.getNode(
10301 X86ISD::VPERMV, DL, MVT::v8i32,
10302 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10305 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10307 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10308 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10311 // Otherwise fall back on generic blend lowering.
10312 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10316 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10318 /// This routine is only called when we have AVX2 and thus a reasonable
10319 /// instruction set for v16i16 shuffling..
10320 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10321 const X86Subtarget *Subtarget,
10322 SelectionDAG &DAG) {
10324 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10325 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10326 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10327 ArrayRef<int> Mask = SVOp->getMask();
10328 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10329 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10331 // Whenever we can lower this as a zext, that instruction is strictly faster
10332 // than any alternative. It also allows us to fold memory operands into the
10333 // shuffle in many cases.
10334 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10335 Mask, Subtarget, DAG))
10338 // Check for being able to broadcast a single element.
10339 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10340 Mask, Subtarget, DAG))
10343 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10347 // Use dedicated unpack instructions for masks that match their pattern.
10348 if (isShuffleEquivalent(V1, V2, Mask,
10349 {// First 128-bit lane:
10350 0, 16, 1, 17, 2, 18, 3, 19,
10351 // Second 128-bit lane:
10352 8, 24, 9, 25, 10, 26, 11, 27}))
10353 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10354 if (isShuffleEquivalent(V1, V2, Mask,
10355 {// First 128-bit lane:
10356 4, 20, 5, 21, 6, 22, 7, 23,
10357 // Second 128-bit lane:
10358 12, 28, 13, 29, 14, 30, 15, 31}))
10359 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10361 // Try to use shift instructions.
10362 if (SDValue Shift =
10363 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10366 // Try to use byte rotation instructions.
10367 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10368 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10371 if (isSingleInputShuffleMask(Mask)) {
10372 // There are no generalized cross-lane shuffle operations available on i16
10374 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10375 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10378 SmallVector<int, 8> RepeatedMask;
10379 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10380 // As this is a single-input shuffle, the repeated mask should be
10381 // a strictly valid v8i16 mask that we can pass through to the v8i16
10382 // lowering to handle even the v16 case.
10383 return lowerV8I16GeneralSingleInputVectorShuffle(
10384 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10387 SDValue PSHUFBMask[32];
10388 for (int i = 0; i < 16; ++i) {
10389 if (Mask[i] == -1) {
10390 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10394 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10395 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10396 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10397 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10399 return DAG.getBitcast(MVT::v16i16,
10400 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10401 DAG.getBitcast(MVT::v32i8, V1),
10402 DAG.getNode(ISD::BUILD_VECTOR, DL,
10403 MVT::v32i8, PSHUFBMask)));
10406 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10408 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10409 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10412 // Otherwise fall back on generic lowering.
10413 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10416 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10418 /// This routine is only called when we have AVX2 and thus a reasonable
10419 /// instruction set for v32i8 shuffling..
10420 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10421 const X86Subtarget *Subtarget,
10422 SelectionDAG &DAG) {
10424 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10425 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10426 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10427 ArrayRef<int> Mask = SVOp->getMask();
10428 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10429 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10431 // Whenever we can lower this as a zext, that instruction is strictly faster
10432 // than any alternative. It also allows us to fold memory operands into the
10433 // shuffle in many cases.
10434 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10435 Mask, Subtarget, DAG))
10438 // Check for being able to broadcast a single element.
10439 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10440 Mask, Subtarget, DAG))
10443 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10447 // Use dedicated unpack instructions for masks that match their pattern.
10448 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10450 if (isShuffleEquivalent(
10452 {// First 128-bit lane:
10453 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10454 // Second 128-bit lane:
10455 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10456 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10457 if (isShuffleEquivalent(
10459 {// First 128-bit lane:
10460 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10461 // Second 128-bit lane:
10462 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10463 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10465 // Try to use shift instructions.
10466 if (SDValue Shift =
10467 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10470 // Try to use byte rotation instructions.
10471 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10472 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10475 if (isSingleInputShuffleMask(Mask)) {
10476 // There are no generalized cross-lane shuffle operations available on i8
10478 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10479 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10482 SDValue PSHUFBMask[32];
10483 for (int i = 0; i < 32; ++i)
10486 ? DAG.getUNDEF(MVT::i8)
10487 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10490 return DAG.getNode(
10491 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10492 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10495 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10497 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10498 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10501 // Otherwise fall back on generic lowering.
10502 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10505 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10507 /// This routine either breaks down the specific type of a 256-bit x86 vector
10508 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10509 /// together based on the available instructions.
10510 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10511 MVT VT, const X86Subtarget *Subtarget,
10512 SelectionDAG &DAG) {
10514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10515 ArrayRef<int> Mask = SVOp->getMask();
10517 // If we have a single input to the zero element, insert that into V1 if we
10518 // can do so cheaply.
10519 int NumElts = VT.getVectorNumElements();
10520 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10521 return M >= NumElts;
10524 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10525 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10526 DL, VT, V1, V2, Mask, Subtarget, DAG))
10529 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10530 // check for those subtargets here and avoid much of the subtarget querying in
10531 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10532 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10533 // floating point types there eventually, just immediately cast everything to
10534 // a float and operate entirely in that domain.
10535 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10536 int ElementBits = VT.getScalarSizeInBits();
10537 if (ElementBits < 32)
10538 // No floating point type available, decompose into 128-bit vectors.
10539 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10541 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10542 VT.getVectorNumElements());
10543 V1 = DAG.getBitcast(FpVT, V1);
10544 V2 = DAG.getBitcast(FpVT, V2);
10545 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10548 switch (VT.SimpleTy) {
10550 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10552 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10554 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10556 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10558 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10560 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10563 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10567 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10568 ArrayRef<int> Mask, SDValue V1,
10569 SDValue V2, SelectionDAG &DAG) {
10571 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10573 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10574 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10576 SmallVector<SDValue, 32> VPermMask;
10577 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10578 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10579 DAG.getConstant(Mask[i], DL, MaskEltVT));
10580 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10582 if (isSingleInputShuffleMask(Mask))
10583 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10585 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10588 // X86 has dedicated unpack instructions that can handle specific blend
10589 // operations: UNPCKH and UNPCKL.
10590 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT,
10591 ArrayRef<int> Mask, SDValue V1,
10592 SDValue V2, SelectionDAG &DAG) {
10593 int NumElts = VT.getVectorNumElements();
10594 bool Unpckl = true;
10595 bool Unpckh = true;
10596 bool UnpcklSwapped = true;
10597 bool UnpckhSwapped = true;
10598 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
10600 for (int i = 0; i < NumElts ; ++i) {
10601 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
10603 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
10604 int HiPos = LoPos + NumEltsInLane / 2;
10605 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
10606 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
10610 if (Mask[i] != LoPos)
10612 if (Mask[i] != HiPos)
10614 if (Mask[i] != LoPosSwapped)
10615 UnpcklSwapped = false;
10616 if (Mask[i] != HiPosSwapped)
10617 UnpckhSwapped = false;
10618 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
10622 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
10624 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
10626 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
10628 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
10630 llvm_unreachable("Unexpected result of UNPCK mask analysis");
10634 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10635 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10636 const X86Subtarget *Subtarget,
10637 SelectionDAG &DAG) {
10639 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10640 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10641 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10642 ArrayRef<int> Mask = SVOp->getMask();
10643 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10645 SDValue UnpckNode =
10646 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG);
10650 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10653 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10654 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10655 const X86Subtarget *Subtarget,
10656 SelectionDAG &DAG) {
10658 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10659 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10660 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10661 ArrayRef<int> Mask = SVOp->getMask();
10662 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10664 SDValue UnpckNode =
10665 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG);
10669 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10672 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10673 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10674 const X86Subtarget *Subtarget,
10675 SelectionDAG &DAG) {
10677 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10678 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10679 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10680 ArrayRef<int> Mask = SVOp->getMask();
10681 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10683 SDValue UnpckNode =
10684 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG);
10688 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10691 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10692 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10693 const X86Subtarget *Subtarget,
10694 SelectionDAG &DAG) {
10696 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10697 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10698 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10699 ArrayRef<int> Mask = SVOp->getMask();
10700 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10702 SDValue UnpckNode =
10703 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG);
10707 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10710 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10711 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10712 const X86Subtarget *Subtarget,
10713 SelectionDAG &DAG) {
10715 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10716 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10717 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10718 ArrayRef<int> Mask = SVOp->getMask();
10719 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10720 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10722 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10725 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10726 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10727 const X86Subtarget *Subtarget,
10728 SelectionDAG &DAG) {
10730 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10731 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10732 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10733 ArrayRef<int> Mask = SVOp->getMask();
10734 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10735 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10737 // FIXME: Implement direct support for this type!
10738 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10741 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10743 /// This routine either breaks down the specific type of a 512-bit x86 vector
10744 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10745 /// together based on the available instructions.
10746 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10747 MVT VT, const X86Subtarget *Subtarget,
10748 SelectionDAG &DAG) {
10750 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10751 ArrayRef<int> Mask = SVOp->getMask();
10752 assert(Subtarget->hasAVX512() &&
10753 "Cannot lower 512-bit vectors w/ basic ISA!");
10755 // Check for being able to broadcast a single element.
10756 if (SDValue Broadcast =
10757 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10760 // Dispatch to each element type for lowering. If we don't have supprot for
10761 // specific element type shuffles at 512 bits, immediately split them and
10762 // lower them. Each lowering routine of a given type is allowed to assume that
10763 // the requisite ISA extensions for that element type are available.
10764 switch (VT.SimpleTy) {
10766 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10768 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10770 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10772 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10774 if (Subtarget->hasBWI())
10775 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10778 if (Subtarget->hasBWI())
10779 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10783 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10786 // Otherwise fall back on splitting.
10787 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10790 /// \brief Top-level lowering for x86 vector shuffles.
10792 /// This handles decomposition, canonicalization, and lowering of all x86
10793 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10794 /// above in helper routines. The canonicalization attempts to widen shuffles
10795 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10796 /// s.t. only one of the two inputs needs to be tested, etc.
10797 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10798 SelectionDAG &DAG) {
10799 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10800 ArrayRef<int> Mask = SVOp->getMask();
10801 SDValue V1 = Op.getOperand(0);
10802 SDValue V2 = Op.getOperand(1);
10803 MVT VT = Op.getSimpleValueType();
10804 int NumElements = VT.getVectorNumElements();
10807 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10809 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10810 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10811 if (V1IsUndef && V2IsUndef)
10812 return DAG.getUNDEF(VT);
10814 // When we create a shuffle node we put the UNDEF node to second operand,
10815 // but in some cases the first operand may be transformed to UNDEF.
10816 // In this case we should just commute the node.
10818 return DAG.getCommutedVectorShuffle(*SVOp);
10820 // Check for non-undef masks pointing at an undef vector and make the masks
10821 // undef as well. This makes it easier to match the shuffle based solely on
10825 if (M >= NumElements) {
10826 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10827 for (int &M : NewMask)
10828 if (M >= NumElements)
10830 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10833 // We actually see shuffles that are entirely re-arrangements of a set of
10834 // zero inputs. This mostly happens while decomposing complex shuffles into
10835 // simple ones. Directly lower these as a buildvector of zeros.
10836 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10837 if (Zeroable.all())
10838 return getZeroVector(VT, Subtarget, DAG, dl);
10840 // Try to collapse shuffles into using a vector type with fewer elements but
10841 // wider element types. We cap this to not form integers or floating point
10842 // elements wider than 64 bits, but it might be interesting to form i128
10843 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10844 SmallVector<int, 16> WidenedMask;
10845 if (VT.getScalarSizeInBits() < 64 &&
10846 canWidenShuffleElements(Mask, WidenedMask)) {
10847 MVT NewEltVT = VT.isFloatingPoint()
10848 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10849 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10850 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10851 // Make sure that the new vector type is legal. For example, v2f64 isn't
10853 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10854 V1 = DAG.getBitcast(NewVT, V1);
10855 V2 = DAG.getBitcast(NewVT, V2);
10856 return DAG.getBitcast(
10857 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10861 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10862 for (int M : SVOp->getMask())
10864 ++NumUndefElements;
10865 else if (M < NumElements)
10870 // Commute the shuffle as needed such that more elements come from V1 than
10871 // V2. This allows us to match the shuffle pattern strictly on how many
10872 // elements come from V1 without handling the symmetric cases.
10873 if (NumV2Elements > NumV1Elements)
10874 return DAG.getCommutedVectorShuffle(*SVOp);
10876 // When the number of V1 and V2 elements are the same, try to minimize the
10877 // number of uses of V2 in the low half of the vector. When that is tied,
10878 // ensure that the sum of indices for V1 is equal to or lower than the sum
10879 // indices for V2. When those are equal, try to ensure that the number of odd
10880 // indices for V1 is lower than the number of odd indices for V2.
10881 if (NumV1Elements == NumV2Elements) {
10882 int LowV1Elements = 0, LowV2Elements = 0;
10883 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10884 if (M >= NumElements)
10888 if (LowV2Elements > LowV1Elements) {
10889 return DAG.getCommutedVectorShuffle(*SVOp);
10890 } else if (LowV2Elements == LowV1Elements) {
10891 int SumV1Indices = 0, SumV2Indices = 0;
10892 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10893 if (SVOp->getMask()[i] >= NumElements)
10895 else if (SVOp->getMask()[i] >= 0)
10897 if (SumV2Indices < SumV1Indices) {
10898 return DAG.getCommutedVectorShuffle(*SVOp);
10899 } else if (SumV2Indices == SumV1Indices) {
10900 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10901 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10902 if (SVOp->getMask()[i] >= NumElements)
10903 NumV2OddIndices += i % 2;
10904 else if (SVOp->getMask()[i] >= 0)
10905 NumV1OddIndices += i % 2;
10906 if (NumV2OddIndices < NumV1OddIndices)
10907 return DAG.getCommutedVectorShuffle(*SVOp);
10912 // For each vector width, delegate to a specialized lowering routine.
10913 if (VT.getSizeInBits() == 128)
10914 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10916 if (VT.getSizeInBits() == 256)
10917 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10919 // Force AVX-512 vectors to be scalarized for now.
10920 // FIXME: Implement AVX-512 support!
10921 if (VT.getSizeInBits() == 512)
10922 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10924 llvm_unreachable("Unimplemented!");
10927 // This function assumes its argument is a BUILD_VECTOR of constants or
10928 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10930 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10931 unsigned &MaskValue) {
10933 unsigned NumElems = BuildVector->getNumOperands();
10934 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10935 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10936 unsigned NumElemsInLane = NumElems / NumLanes;
10938 // Blend for v16i16 should be symmetric for the both lanes.
10939 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10940 SDValue EltCond = BuildVector->getOperand(i);
10941 SDValue SndLaneEltCond =
10942 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10944 int Lane1Cond = -1, Lane2Cond = -1;
10945 if (isa<ConstantSDNode>(EltCond))
10946 Lane1Cond = !isZero(EltCond);
10947 if (isa<ConstantSDNode>(SndLaneEltCond))
10948 Lane2Cond = !isZero(SndLaneEltCond);
10950 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10951 // Lane1Cond != 0, means we want the first argument.
10952 // Lane1Cond == 0, means we want the second argument.
10953 // The encoding of this argument is 0 for the first argument, 1
10954 // for the second. Therefore, invert the condition.
10955 MaskValue |= !Lane1Cond << i;
10956 else if (Lane1Cond < 0)
10957 MaskValue |= !Lane2Cond << i;
10964 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10965 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10966 const X86Subtarget *Subtarget,
10967 SelectionDAG &DAG) {
10968 SDValue Cond = Op.getOperand(0);
10969 SDValue LHS = Op.getOperand(1);
10970 SDValue RHS = Op.getOperand(2);
10972 MVT VT = Op.getSimpleValueType();
10974 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10976 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10978 // Only non-legal VSELECTs reach this lowering, convert those into generic
10979 // shuffles and re-use the shuffle lowering path for blends.
10980 SmallVector<int, 32> Mask;
10981 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10982 SDValue CondElt = CondBV->getOperand(i);
10984 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10986 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10989 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10990 // A vselect where all conditions and data are constants can be optimized into
10991 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10992 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10993 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10994 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10997 // Try to lower this to a blend-style vector shuffle. This can handle all
10998 // constant condition cases.
10999 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11002 // Variable blends are only legal from SSE4.1 onward.
11003 if (!Subtarget->hasSSE41())
11006 // Only some types will be legal on some subtargets. If we can emit a legal
11007 // VSELECT-matching blend, return Op, and but if we need to expand, return
11009 switch (Op.getSimpleValueType().SimpleTy) {
11011 // Most of the vector types have blends past SSE4.1.
11015 // The byte blends for AVX vectors were introduced only in AVX2.
11016 if (Subtarget->hasAVX2())
11023 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11024 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11027 // FIXME: We should custom lower this by fixing the condition and using i8
11033 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11034 MVT VT = Op.getSimpleValueType();
11037 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11040 if (VT.getSizeInBits() == 8) {
11041 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11042 Op.getOperand(0), Op.getOperand(1));
11043 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11044 DAG.getValueType(VT));
11045 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11048 if (VT.getSizeInBits() == 16) {
11049 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11050 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11052 return DAG.getNode(
11053 ISD::TRUNCATE, dl, MVT::i16,
11054 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11055 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11056 Op.getOperand(1)));
11057 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11058 Op.getOperand(0), Op.getOperand(1));
11059 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11060 DAG.getValueType(VT));
11061 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11064 if (VT == MVT::f32) {
11065 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11066 // the result back to FR32 register. It's only worth matching if the
11067 // result has a single use which is a store or a bitcast to i32. And in
11068 // the case of a store, it's not worth it if the index is a constant 0,
11069 // because a MOVSSmr can be used instead, which is smaller and faster.
11070 if (!Op.hasOneUse())
11072 SDNode *User = *Op.getNode()->use_begin();
11073 if ((User->getOpcode() != ISD::STORE ||
11074 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11075 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11076 (User->getOpcode() != ISD::BITCAST ||
11077 User->getValueType(0) != MVT::i32))
11079 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11080 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11082 return DAG.getBitcast(MVT::f32, Extract);
11085 if (VT == MVT::i32 || VT == MVT::i64) {
11086 // ExtractPS/pextrq works with constant index.
11087 if (isa<ConstantSDNode>(Op.getOperand(1)))
11093 /// Extract one bit from mask vector, like v16i1 or v8i1.
11094 /// AVX-512 feature.
11096 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11097 SDValue Vec = Op.getOperand(0);
11099 MVT VecVT = Vec.getSimpleValueType();
11100 SDValue Idx = Op.getOperand(1);
11101 MVT EltVT = Op.getSimpleValueType();
11103 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11104 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11105 "Unexpected vector type in ExtractBitFromMaskVector");
11107 // variable index can't be handled in mask registers,
11108 // extend vector to VR512
11109 if (!isa<ConstantSDNode>(Idx)) {
11110 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11111 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11112 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11113 ExtVT.getVectorElementType(), Ext, Idx);
11114 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11118 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11119 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11120 rc = getRegClassFor(MVT::v16i1);
11121 unsigned MaxSift = rc->getSize()*8 - 1;
11122 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11123 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11124 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11125 DAG.getConstant(MaxSift, dl, MVT::i8));
11126 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11127 DAG.getIntPtrConstant(0, dl));
11131 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11132 SelectionDAG &DAG) const {
11134 SDValue Vec = Op.getOperand(0);
11135 MVT VecVT = Vec.getSimpleValueType();
11136 SDValue Idx = Op.getOperand(1);
11138 if (Op.getSimpleValueType() == MVT::i1)
11139 return ExtractBitFromMaskVector(Op, DAG);
11141 if (!isa<ConstantSDNode>(Idx)) {
11142 if (VecVT.is512BitVector() ||
11143 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11144 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11147 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11148 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11149 MaskEltVT.getSizeInBits());
11151 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11152 auto PtrVT = getPointerTy(DAG.getDataLayout());
11153 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11154 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11155 DAG.getConstant(0, dl, PtrVT));
11156 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11157 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11158 DAG.getConstant(0, dl, PtrVT));
11163 // If this is a 256-bit vector result, first extract the 128-bit vector and
11164 // then extract the element from the 128-bit vector.
11165 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11167 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11168 // Get the 128-bit vector.
11169 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11170 MVT EltVT = VecVT.getVectorElementType();
11172 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11174 //if (IdxVal >= NumElems/2)
11175 // IdxVal -= NumElems/2;
11176 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11177 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11178 DAG.getConstant(IdxVal, dl, MVT::i32));
11181 assert(VecVT.is128BitVector() && "Unexpected vector length");
11183 if (Subtarget->hasSSE41())
11184 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11187 MVT VT = Op.getSimpleValueType();
11188 // TODO: handle v16i8.
11189 if (VT.getSizeInBits() == 16) {
11190 SDValue Vec = Op.getOperand(0);
11191 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11193 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11194 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11195 DAG.getBitcast(MVT::v4i32, Vec),
11196 Op.getOperand(1)));
11197 // Transform it so it match pextrw which produces a 32-bit result.
11198 MVT EltVT = MVT::i32;
11199 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11200 Op.getOperand(0), Op.getOperand(1));
11201 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11202 DAG.getValueType(VT));
11203 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11206 if (VT.getSizeInBits() == 32) {
11207 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11211 // SHUFPS the element to the lowest double word, then movss.
11212 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11213 MVT VVT = Op.getOperand(0).getSimpleValueType();
11214 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11215 DAG.getUNDEF(VVT), Mask);
11216 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11217 DAG.getIntPtrConstant(0, dl));
11220 if (VT.getSizeInBits() == 64) {
11221 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11222 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11223 // to match extract_elt for f64.
11224 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11228 // UNPCKHPD the element to the lowest double word, then movsd.
11229 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11230 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11231 int Mask[2] = { 1, -1 };
11232 MVT VVT = Op.getOperand(0).getSimpleValueType();
11233 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11234 DAG.getUNDEF(VVT), Mask);
11235 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11236 DAG.getIntPtrConstant(0, dl));
11242 /// Insert one bit to mask vector, like v16i1 or v8i1.
11243 /// AVX-512 feature.
11245 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11247 SDValue Vec = Op.getOperand(0);
11248 SDValue Elt = Op.getOperand(1);
11249 SDValue Idx = Op.getOperand(2);
11250 MVT VecVT = Vec.getSimpleValueType();
11252 if (!isa<ConstantSDNode>(Idx)) {
11253 // Non constant index. Extend source and destination,
11254 // insert element and then truncate the result.
11255 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11256 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11257 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11258 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11259 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11260 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11263 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11264 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11266 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11267 DAG.getConstant(IdxVal, dl, MVT::i8));
11268 if (Vec.getOpcode() == ISD::UNDEF)
11270 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11273 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11274 SelectionDAG &DAG) const {
11275 MVT VT = Op.getSimpleValueType();
11276 MVT EltVT = VT.getVectorElementType();
11278 if (EltVT == MVT::i1)
11279 return InsertBitToMaskVector(Op, DAG);
11282 SDValue N0 = Op.getOperand(0);
11283 SDValue N1 = Op.getOperand(1);
11284 SDValue N2 = Op.getOperand(2);
11285 if (!isa<ConstantSDNode>(N2))
11287 auto *N2C = cast<ConstantSDNode>(N2);
11288 unsigned IdxVal = N2C->getZExtValue();
11290 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11291 // into that, and then insert the subvector back into the result.
11292 if (VT.is256BitVector() || VT.is512BitVector()) {
11293 // With a 256-bit vector, we can insert into the zero element efficiently
11294 // using a blend if we have AVX or AVX2 and the right data type.
11295 if (VT.is256BitVector() && IdxVal == 0) {
11296 // TODO: It is worthwhile to cast integer to floating point and back
11297 // and incur a domain crossing penalty if that's what we'll end up
11298 // doing anyway after extracting to a 128-bit vector.
11299 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11300 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11301 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11302 N2 = DAG.getIntPtrConstant(1, dl);
11303 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11307 // Get the desired 128-bit vector chunk.
11308 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11310 // Insert the element into the desired chunk.
11311 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11312 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11314 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11315 DAG.getConstant(IdxIn128, dl, MVT::i32));
11317 // Insert the changed part back into the bigger vector
11318 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11320 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11322 if (Subtarget->hasSSE41()) {
11323 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11325 if (VT == MVT::v8i16) {
11326 Opc = X86ISD::PINSRW;
11328 assert(VT == MVT::v16i8);
11329 Opc = X86ISD::PINSRB;
11332 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11334 if (N1.getValueType() != MVT::i32)
11335 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11336 if (N2.getValueType() != MVT::i32)
11337 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11338 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11341 if (EltVT == MVT::f32) {
11342 // Bits [7:6] of the constant are the source select. This will always be
11343 // zero here. The DAG Combiner may combine an extract_elt index into
11344 // these bits. For example (insert (extract, 3), 2) could be matched by
11345 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11346 // Bits [5:4] of the constant are the destination select. This is the
11347 // value of the incoming immediate.
11348 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11349 // combine either bitwise AND or insert of float 0.0 to set these bits.
11351 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11352 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11353 // If this is an insertion of 32-bits into the low 32-bits of
11354 // a vector, we prefer to generate a blend with immediate rather
11355 // than an insertps. Blends are simpler operations in hardware and so
11356 // will always have equal or better performance than insertps.
11357 // But if optimizing for size and there's a load folding opportunity,
11358 // generate insertps because blendps does not have a 32-bit memory
11360 N2 = DAG.getIntPtrConstant(1, dl);
11361 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11362 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11364 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11365 // Create this as a scalar to vector..
11366 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11367 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11370 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11371 // PINSR* works with constant index.
11376 if (EltVT == MVT::i8)
11379 if (EltVT.getSizeInBits() == 16) {
11380 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11381 // as its second argument.
11382 if (N1.getValueType() != MVT::i32)
11383 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11384 if (N2.getValueType() != MVT::i32)
11385 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11386 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11391 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11393 MVT OpVT = Op.getSimpleValueType();
11395 // If this is a 256-bit vector result, first insert into a 128-bit
11396 // vector and then insert into the 256-bit vector.
11397 if (!OpVT.is128BitVector()) {
11398 // Insert into a 128-bit vector.
11399 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11400 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11401 OpVT.getVectorNumElements() / SizeFactor);
11403 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11405 // Insert the 128-bit vector.
11406 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11409 if (OpVT == MVT::v1i64 &&
11410 Op.getOperand(0).getValueType() == MVT::i64)
11411 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11413 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11414 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11415 return DAG.getBitcast(
11416 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11419 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11420 // a simple subregister reference or explicit instructions to grab
11421 // upper bits of a vector.
11422 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11423 SelectionDAG &DAG) {
11425 SDValue In = Op.getOperand(0);
11426 SDValue Idx = Op.getOperand(1);
11427 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11428 MVT ResVT = Op.getSimpleValueType();
11429 MVT InVT = In.getSimpleValueType();
11431 if (Subtarget->hasFp256()) {
11432 if (ResVT.is128BitVector() &&
11433 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11434 isa<ConstantSDNode>(Idx)) {
11435 return Extract128BitVector(In, IdxVal, DAG, dl);
11437 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11438 isa<ConstantSDNode>(Idx)) {
11439 return Extract256BitVector(In, IdxVal, DAG, dl);
11445 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11446 // simple superregister reference or explicit instructions to insert
11447 // the upper bits of a vector.
11448 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11449 SelectionDAG &DAG) {
11450 if (!Subtarget->hasAVX())
11454 SDValue Vec = Op.getOperand(0);
11455 SDValue SubVec = Op.getOperand(1);
11456 SDValue Idx = Op.getOperand(2);
11458 if (!isa<ConstantSDNode>(Idx))
11461 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11462 MVT OpVT = Op.getSimpleValueType();
11463 MVT SubVecVT = SubVec.getSimpleValueType();
11465 // Fold two 16-byte subvector loads into one 32-byte load:
11466 // (insert_subvector (insert_subvector undef, (load addr), 0),
11467 // (load addr + 16), Elts/2)
11469 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11470 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11471 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11472 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11473 if (Idx2 && Idx2->getZExtValue() == 0) {
11474 SDValue SubVec2 = Vec.getOperand(1);
11475 // If needed, look through a bitcast to get to the load.
11476 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11477 SubVec2 = SubVec2.getOperand(0);
11479 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11481 unsigned Alignment = FirstLd->getAlignment();
11482 unsigned AS = FirstLd->getAddressSpace();
11483 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11484 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11485 OpVT, AS, Alignment, &Fast) && Fast) {
11486 SDValue Ops[] = { SubVec2, SubVec };
11487 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11494 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11495 SubVecVT.is128BitVector())
11496 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11498 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11499 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11501 if (OpVT.getVectorElementType() == MVT::i1) {
11502 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11504 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11505 SDValue Undef = DAG.getUNDEF(OpVT);
11506 unsigned NumElems = OpVT.getVectorNumElements();
11507 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11509 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11510 // Zero upper bits of the Vec
11511 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11512 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11514 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11516 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11517 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11520 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11522 // Zero upper bits of the Vec2
11523 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11524 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11525 // Zero lower bits of the Vec
11526 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11527 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11528 // Merge them together
11529 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11535 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11536 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11537 // one of the above mentioned nodes. It has to be wrapped because otherwise
11538 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11539 // be used to form addressing mode. These wrapped nodes will be selected
11542 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11543 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11545 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11546 // global base reg.
11547 unsigned char OpFlag = 0;
11548 unsigned WrapperKind = X86ISD::Wrapper;
11549 CodeModel::Model M = DAG.getTarget().getCodeModel();
11551 if (Subtarget->isPICStyleRIPRel() &&
11552 (M == CodeModel::Small || M == CodeModel::Kernel))
11553 WrapperKind = X86ISD::WrapperRIP;
11554 else if (Subtarget->isPICStyleGOT())
11555 OpFlag = X86II::MO_GOTOFF;
11556 else if (Subtarget->isPICStyleStubPIC())
11557 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11559 auto PtrVT = getPointerTy(DAG.getDataLayout());
11560 SDValue Result = DAG.getTargetConstantPool(
11561 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11563 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11564 // With PIC, the address is actually $g + Offset.
11567 DAG.getNode(ISD::ADD, DL, PtrVT,
11568 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11574 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11575 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11577 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11578 // global base reg.
11579 unsigned char OpFlag = 0;
11580 unsigned WrapperKind = X86ISD::Wrapper;
11581 CodeModel::Model M = DAG.getTarget().getCodeModel();
11583 if (Subtarget->isPICStyleRIPRel() &&
11584 (M == CodeModel::Small || M == CodeModel::Kernel))
11585 WrapperKind = X86ISD::WrapperRIP;
11586 else if (Subtarget->isPICStyleGOT())
11587 OpFlag = X86II::MO_GOTOFF;
11588 else if (Subtarget->isPICStyleStubPIC())
11589 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11591 auto PtrVT = getPointerTy(DAG.getDataLayout());
11592 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11594 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11596 // With PIC, the address is actually $g + Offset.
11599 DAG.getNode(ISD::ADD, DL, PtrVT,
11600 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11606 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11607 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11609 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11610 // global base reg.
11611 unsigned char OpFlag = 0;
11612 unsigned WrapperKind = X86ISD::Wrapper;
11613 CodeModel::Model M = DAG.getTarget().getCodeModel();
11615 if (Subtarget->isPICStyleRIPRel() &&
11616 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11617 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11618 OpFlag = X86II::MO_GOTPCREL;
11619 WrapperKind = X86ISD::WrapperRIP;
11620 } else if (Subtarget->isPICStyleGOT()) {
11621 OpFlag = X86II::MO_GOT;
11622 } else if (Subtarget->isPICStyleStubPIC()) {
11623 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11624 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11625 OpFlag = X86II::MO_DARWIN_NONLAZY;
11628 auto PtrVT = getPointerTy(DAG.getDataLayout());
11629 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11632 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11634 // With PIC, the address is actually $g + Offset.
11635 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11636 !Subtarget->is64Bit()) {
11638 DAG.getNode(ISD::ADD, DL, PtrVT,
11639 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11642 // For symbols that require a load from a stub to get the address, emit the
11644 if (isGlobalStubReference(OpFlag))
11645 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11646 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11647 false, false, false, 0);
11653 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11654 // Create the TargetBlockAddressAddress node.
11655 unsigned char OpFlags =
11656 Subtarget->ClassifyBlockAddressReference();
11657 CodeModel::Model M = DAG.getTarget().getCodeModel();
11658 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11659 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11661 auto PtrVT = getPointerTy(DAG.getDataLayout());
11662 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11664 if (Subtarget->isPICStyleRIPRel() &&
11665 (M == CodeModel::Small || M == CodeModel::Kernel))
11666 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11668 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11670 // With PIC, the address is actually $g + Offset.
11671 if (isGlobalRelativeToPICBase(OpFlags)) {
11672 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11673 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11680 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11681 int64_t Offset, SelectionDAG &DAG) const {
11682 // Create the TargetGlobalAddress node, folding in the constant
11683 // offset if it is legal.
11684 unsigned char OpFlags =
11685 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11686 CodeModel::Model M = DAG.getTarget().getCodeModel();
11687 auto PtrVT = getPointerTy(DAG.getDataLayout());
11689 if (OpFlags == X86II::MO_NO_FLAG &&
11690 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11691 // A direct static reference to a global.
11692 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11695 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11698 if (Subtarget->isPICStyleRIPRel() &&
11699 (M == CodeModel::Small || M == CodeModel::Kernel))
11700 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11702 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11704 // With PIC, the address is actually $g + Offset.
11705 if (isGlobalRelativeToPICBase(OpFlags)) {
11706 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11707 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11710 // For globals that require a load from a stub to get the address, emit the
11712 if (isGlobalStubReference(OpFlags))
11713 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11714 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11715 false, false, false, 0);
11717 // If there was a non-zero offset that we didn't fold, create an explicit
11718 // addition for it.
11720 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11721 DAG.getConstant(Offset, dl, PtrVT));
11727 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11728 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11729 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11730 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11734 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11735 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11736 unsigned char OperandFlags, bool LocalDynamic = false) {
11737 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11738 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11740 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11741 GA->getValueType(0),
11745 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11749 SDValue Ops[] = { Chain, TGA, *InFlag };
11750 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11752 SDValue Ops[] = { Chain, TGA };
11753 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11756 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11757 MFI->setAdjustsStack(true);
11758 MFI->setHasCalls(true);
11760 SDValue Flag = Chain.getValue(1);
11761 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11764 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11766 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11769 SDLoc dl(GA); // ? function entry point might be better
11770 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11771 DAG.getNode(X86ISD::GlobalBaseReg,
11772 SDLoc(), PtrVT), InFlag);
11773 InFlag = Chain.getValue(1);
11775 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11778 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11780 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11782 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11783 X86::RAX, X86II::MO_TLSGD);
11786 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11792 // Get the start address of the TLS block for this module.
11793 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11794 .getInfo<X86MachineFunctionInfo>();
11795 MFI->incNumLocalDynamicTLSAccesses();
11799 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11800 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11803 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11804 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11805 InFlag = Chain.getValue(1);
11806 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11807 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11810 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11814 unsigned char OperandFlags = X86II::MO_DTPOFF;
11815 unsigned WrapperKind = X86ISD::Wrapper;
11816 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11817 GA->getValueType(0),
11818 GA->getOffset(), OperandFlags);
11819 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11821 // Add x@dtpoff with the base.
11822 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11825 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11826 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11827 const EVT PtrVT, TLSModel::Model model,
11828 bool is64Bit, bool isPIC) {
11831 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11832 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11833 is64Bit ? 257 : 256));
11835 SDValue ThreadPointer =
11836 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11837 MachinePointerInfo(Ptr), false, false, false, 0);
11839 unsigned char OperandFlags = 0;
11840 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11842 unsigned WrapperKind = X86ISD::Wrapper;
11843 if (model == TLSModel::LocalExec) {
11844 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11845 } else if (model == TLSModel::InitialExec) {
11847 OperandFlags = X86II::MO_GOTTPOFF;
11848 WrapperKind = X86ISD::WrapperRIP;
11850 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11853 llvm_unreachable("Unexpected model");
11856 // emit "addl x@ntpoff,%eax" (local exec)
11857 // or "addl x@indntpoff,%eax" (initial exec)
11858 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11860 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11861 GA->getOffset(), OperandFlags);
11862 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11864 if (model == TLSModel::InitialExec) {
11865 if (isPIC && !is64Bit) {
11866 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11867 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11871 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11872 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11873 false, false, false, 0);
11876 // The address of the thread local variable is the add of the thread
11877 // pointer with the offset of the variable.
11878 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11882 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11884 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11885 const GlobalValue *GV = GA->getGlobal();
11886 auto PtrVT = getPointerTy(DAG.getDataLayout());
11888 if (Subtarget->isTargetELF()) {
11889 if (DAG.getTarget().Options.EmulatedTLS)
11890 return LowerToTLSEmulatedModel(GA, DAG);
11891 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11893 case TLSModel::GeneralDynamic:
11894 if (Subtarget->is64Bit())
11895 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
11896 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
11897 case TLSModel::LocalDynamic:
11898 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
11899 Subtarget->is64Bit());
11900 case TLSModel::InitialExec:
11901 case TLSModel::LocalExec:
11902 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
11903 DAG.getTarget().getRelocationModel() ==
11906 llvm_unreachable("Unknown TLS model.");
11909 if (Subtarget->isTargetDarwin()) {
11910 // Darwin only has one model of TLS. Lower to that.
11911 unsigned char OpFlag = 0;
11912 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11913 X86ISD::WrapperRIP : X86ISD::Wrapper;
11915 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11916 // global base reg.
11917 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11918 !Subtarget->is64Bit();
11920 OpFlag = X86II::MO_TLVP_PIC_BASE;
11922 OpFlag = X86II::MO_TLVP;
11924 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11925 GA->getValueType(0),
11926 GA->getOffset(), OpFlag);
11927 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11929 // With PIC32, the address is actually $g + Offset.
11931 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
11932 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11935 // Lowering the machine isd will make sure everything is in the right
11937 SDValue Chain = DAG.getEntryNode();
11938 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11939 SDValue Args[] = { Chain, Offset };
11940 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11942 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11943 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11944 MFI->setAdjustsStack(true);
11946 // And our return value (tls address) is in the standard call return value
11948 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11949 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
11952 if (Subtarget->isTargetKnownWindowsMSVC() ||
11953 Subtarget->isTargetWindowsGNU()) {
11954 // Just use the implicit TLS architecture
11955 // Need to generate someting similar to:
11956 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11958 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11959 // mov rcx, qword [rdx+rcx*8]
11960 // mov eax, .tls$:tlsvar
11961 // [rax+rcx] contains the address
11962 // Windows 64bit: gs:0x58
11963 // Windows 32bit: fs:__tls_array
11966 SDValue Chain = DAG.getEntryNode();
11968 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11969 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11970 // use its literal value of 0x2C.
11971 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11972 ? Type::getInt8PtrTy(*DAG.getContext(),
11974 : Type::getInt32PtrTy(*DAG.getContext(),
11977 SDValue TlsArray = Subtarget->is64Bit()
11978 ? DAG.getIntPtrConstant(0x58, dl)
11979 : (Subtarget->isTargetWindowsGNU()
11980 ? DAG.getIntPtrConstant(0x2C, dl)
11981 : DAG.getExternalSymbol("_tls_array", PtrVT));
11983 SDValue ThreadPointer =
11984 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
11988 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11989 res = ThreadPointer;
11991 // Load the _tls_index variable
11992 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
11993 if (Subtarget->is64Bit())
11994 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
11995 MachinePointerInfo(), MVT::i32, false, false,
11998 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12001 auto &DL = DAG.getDataLayout();
12003 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12004 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12006 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12009 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12012 // Get the offset of start of .tls section
12013 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12014 GA->getValueType(0),
12015 GA->getOffset(), X86II::MO_SECREL);
12016 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12018 // The address of the thread local variable is the add of the thread
12019 // pointer with the offset of the variable.
12020 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12023 llvm_unreachable("TLS not implemented for this target.");
12026 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12027 /// and take a 2 x i32 value to shift plus a shift amount.
12028 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12029 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12030 MVT VT = Op.getSimpleValueType();
12031 unsigned VTBits = VT.getSizeInBits();
12033 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12034 SDValue ShOpLo = Op.getOperand(0);
12035 SDValue ShOpHi = Op.getOperand(1);
12036 SDValue ShAmt = Op.getOperand(2);
12037 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12038 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12040 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12041 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12042 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12043 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12044 : DAG.getConstant(0, dl, VT);
12046 SDValue Tmp2, Tmp3;
12047 if (Op.getOpcode() == ISD::SHL_PARTS) {
12048 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12049 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12051 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12052 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12055 // If the shift amount is larger or equal than the width of a part we can't
12056 // rely on the results of shld/shrd. Insert a test and select the appropriate
12057 // values for large shift amounts.
12058 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12059 DAG.getConstant(VTBits, dl, MVT::i8));
12060 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12061 AndNode, DAG.getConstant(0, dl, MVT::i8));
12064 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12065 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12066 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12068 if (Op.getOpcode() == ISD::SHL_PARTS) {
12069 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12070 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12072 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12073 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12076 SDValue Ops[2] = { Lo, Hi };
12077 return DAG.getMergeValues(Ops, dl);
12080 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12081 SelectionDAG &DAG) const {
12082 SDValue Src = Op.getOperand(0);
12083 MVT SrcVT = Src.getSimpleValueType();
12084 MVT VT = Op.getSimpleValueType();
12087 if (SrcVT.isVector()) {
12088 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12089 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12090 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12091 DAG.getUNDEF(SrcVT)));
12093 if (SrcVT.getVectorElementType() == MVT::i1) {
12094 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12095 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12096 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12101 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12102 "Unknown SINT_TO_FP to lower!");
12104 // These are really Legal; return the operand so the caller accepts it as
12106 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12108 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12109 Subtarget->is64Bit()) {
12113 unsigned Size = SrcVT.getSizeInBits()/8;
12114 MachineFunction &MF = DAG.getMachineFunction();
12115 auto PtrVT = getPointerTy(MF.getDataLayout());
12116 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12117 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12118 SDValue Chain = DAG.getStore(
12119 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12120 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12122 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12125 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12127 SelectionDAG &DAG) const {
12131 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12133 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12135 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12137 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12139 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12140 MachineMemOperand *MMO;
12142 int SSFI = FI->getIndex();
12143 MMO = DAG.getMachineFunction().getMachineMemOperand(
12144 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12145 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12147 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12148 StackSlot = StackSlot.getOperand(1);
12150 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12151 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12153 Tys, Ops, SrcVT, MMO);
12156 Chain = Result.getValue(1);
12157 SDValue InFlag = Result.getValue(2);
12159 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12160 // shouldn't be necessary except that RFP cannot be live across
12161 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12162 MachineFunction &MF = DAG.getMachineFunction();
12163 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12164 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12165 auto PtrVT = getPointerTy(MF.getDataLayout());
12166 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12167 Tys = DAG.getVTList(MVT::Other);
12169 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12171 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12172 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12173 MachineMemOperand::MOStore, SSFISize, SSFISize);
12175 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12176 Ops, Op.getValueType(), MMO);
12177 Result = DAG.getLoad(
12178 Op.getValueType(), DL, Chain, StackSlot,
12179 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12180 false, false, false, 0);
12186 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12187 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12188 SelectionDAG &DAG) const {
12189 // This algorithm is not obvious. Here it is what we're trying to output:
12192 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12193 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12195 haddpd %xmm0, %xmm0
12197 pshufd $0x4e, %xmm0, %xmm1
12203 LLVMContext *Context = DAG.getContext();
12205 // Build some magic constants.
12206 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12207 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12208 auto PtrVT = getPointerTy(DAG.getDataLayout());
12209 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12211 SmallVector<Constant*,2> CV1;
12213 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12214 APInt(64, 0x4330000000000000ULL))));
12216 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12217 APInt(64, 0x4530000000000000ULL))));
12218 Constant *C1 = ConstantVector::get(CV1);
12219 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12221 // Load the 64-bit value into an XMM register.
12222 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12225 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12226 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12227 false, false, false, 16);
12229 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12232 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12233 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12234 false, false, false, 16);
12235 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12236 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12239 if (Subtarget->hasSSE3()) {
12240 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12241 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12243 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12244 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12246 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12247 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12250 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12251 DAG.getIntPtrConstant(0, dl));
12254 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12255 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12256 SelectionDAG &DAG) const {
12258 // FP constant to bias correct the final result.
12259 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12262 // Load the 32-bit value into an XMM register.
12263 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12266 // Zero out the upper parts of the register.
12267 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12269 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12270 DAG.getBitcast(MVT::v2f64, Load),
12271 DAG.getIntPtrConstant(0, dl));
12273 // Or the load with the bias.
12274 SDValue Or = DAG.getNode(
12275 ISD::OR, dl, MVT::v2i64,
12276 DAG.getBitcast(MVT::v2i64,
12277 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12278 DAG.getBitcast(MVT::v2i64,
12279 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12281 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12282 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12284 // Subtract the bias.
12285 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12287 // Handle final rounding.
12288 EVT DestVT = Op.getValueType();
12290 if (DestVT.bitsLT(MVT::f64))
12291 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12292 DAG.getIntPtrConstant(0, dl));
12293 if (DestVT.bitsGT(MVT::f64))
12294 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12296 // Handle final rounding.
12300 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12301 const X86Subtarget &Subtarget) {
12302 // The algorithm is the following:
12303 // #ifdef __SSE4_1__
12304 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12305 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12306 // (uint4) 0x53000000, 0xaa);
12308 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12309 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12311 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12312 // return (float4) lo + fhi;
12315 SDValue V = Op->getOperand(0);
12316 EVT VecIntVT = V.getValueType();
12317 bool Is128 = VecIntVT == MVT::v4i32;
12318 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12319 // If we convert to something else than the supported type, e.g., to v4f64,
12321 if (VecFloatVT != Op->getValueType(0))
12324 unsigned NumElts = VecIntVT.getVectorNumElements();
12325 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12326 "Unsupported custom type");
12327 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12329 // In the #idef/#else code, we have in common:
12330 // - The vector of constants:
12336 // Create the splat vector for 0x4b000000.
12337 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12338 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12339 CstLow, CstLow, CstLow, CstLow};
12340 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12341 makeArrayRef(&CstLowArray[0], NumElts));
12342 // Create the splat vector for 0x53000000.
12343 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12344 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12345 CstHigh, CstHigh, CstHigh, CstHigh};
12346 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12347 makeArrayRef(&CstHighArray[0], NumElts));
12349 // Create the right shift.
12350 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12351 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12352 CstShift, CstShift, CstShift, CstShift};
12353 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12354 makeArrayRef(&CstShiftArray[0], NumElts));
12355 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12358 if (Subtarget.hasSSE41()) {
12359 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12360 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12361 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12362 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12363 // Low will be bitcasted right away, so do not bother bitcasting back to its
12365 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12366 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12367 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12368 // (uint4) 0x53000000, 0xaa);
12369 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12370 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12371 // High will be bitcasted right away, so do not bother bitcasting back to
12372 // its original type.
12373 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12374 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12376 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12377 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12378 CstMask, CstMask, CstMask);
12379 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12380 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12381 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12383 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12384 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12387 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12388 SDValue CstFAdd = DAG.getConstantFP(
12389 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12390 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12391 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12392 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12393 makeArrayRef(&CstFAddArray[0], NumElts));
12395 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12396 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12398 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12399 // return (float4) lo + fhi;
12400 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12401 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12404 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12405 SelectionDAG &DAG) const {
12406 SDValue N0 = Op.getOperand(0);
12407 MVT SVT = N0.getSimpleValueType();
12410 switch (SVT.SimpleTy) {
12412 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12417 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12418 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12419 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12423 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12426 if (Subtarget->hasAVX512())
12427 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12428 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12430 llvm_unreachable(nullptr);
12433 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12434 SelectionDAG &DAG) const {
12435 SDValue N0 = Op.getOperand(0);
12437 auto PtrVT = getPointerTy(DAG.getDataLayout());
12439 if (Op.getValueType().isVector())
12440 return lowerUINT_TO_FP_vec(Op, DAG);
12442 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12443 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12444 // the optimization here.
12445 if (DAG.SignBitIsZero(N0))
12446 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12448 MVT SrcVT = N0.getSimpleValueType();
12449 MVT DstVT = Op.getSimpleValueType();
12450 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12451 return LowerUINT_TO_FP_i64(Op, DAG);
12452 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12453 return LowerUINT_TO_FP_i32(Op, DAG);
12454 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12457 // Make a 64-bit buffer, and use it to build an FILD.
12458 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12459 if (SrcVT == MVT::i32) {
12460 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12461 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12462 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12463 StackSlot, MachinePointerInfo(),
12465 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12466 OffsetSlot, MachinePointerInfo(),
12468 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12472 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12473 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12474 StackSlot, MachinePointerInfo(),
12476 // For i64 source, we need to add the appropriate power of 2 if the input
12477 // was negative. This is the same as the optimization in
12478 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12479 // we must be careful to do the computation in x87 extended precision, not
12480 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12481 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12482 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12483 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12484 MachineMemOperand::MOLoad, 8, 8);
12486 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12487 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12488 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12491 APInt FF(32, 0x5F800000ULL);
12493 // Check whether the sign bit is set.
12494 SDValue SignSet = DAG.getSetCC(
12495 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12496 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12498 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12499 SDValue FudgePtr = DAG.getConstantPool(
12500 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12502 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12503 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12504 SDValue Four = DAG.getIntPtrConstant(4, dl);
12505 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12507 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12509 // Load the value out, extending it from f32 to f80.
12510 // FIXME: Avoid the extend by constructing the right constant pool?
12511 SDValue Fudge = DAG.getExtLoad(
12512 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12513 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12514 false, false, false, 4);
12515 // Extend everything to 80 bits to force it to be done on x87.
12516 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12517 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12518 DAG.getIntPtrConstant(0, dl));
12521 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12522 // is legal, or has an f16 source (which needs to be promoted to f32),
12523 // just return an <SDValue(), SDValue()> pair.
12524 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12525 // to i16, i32 or i64, and we lower it to a legal sequence.
12526 // If lowered to the final integer result we return a <result, SDValue()> pair.
12527 // Otherwise we lower it to a sequence ending with a FIST, return a
12528 // <FIST, StackSlot> pair, and the caller is responsible for loading
12529 // the final integer result from StackSlot.
12530 std::pair<SDValue,SDValue>
12531 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12532 bool IsSigned, bool IsReplace) const {
12535 EVT DstTy = Op.getValueType();
12536 EVT TheVT = Op.getOperand(0).getValueType();
12537 auto PtrVT = getPointerTy(DAG.getDataLayout());
12539 if (TheVT == MVT::f16)
12540 // We need to promote the f16 to f32 before using the lowering
12541 // in this routine.
12542 return std::make_pair(SDValue(), SDValue());
12544 assert((TheVT == MVT::f32 ||
12545 TheVT == MVT::f64 ||
12546 TheVT == MVT::f80) &&
12547 "Unexpected FP operand type in FP_TO_INTHelper");
12549 // If using FIST to compute an unsigned i64, we'll need some fixup
12550 // to handle values above the maximum signed i64. A FIST is always
12551 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12552 bool UnsignedFixup = !IsSigned &&
12553 DstTy == MVT::i64 &&
12554 (!Subtarget->is64Bit() ||
12555 !isScalarFPTypeInSSEReg(TheVT));
12557 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12558 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12559 // The low 32 bits of the fist result will have the correct uint32 result.
12560 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12564 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12565 DstTy.getSimpleVT() >= MVT::i16 &&
12566 "Unknown FP_TO_INT to lower!");
12568 // These are really Legal.
12569 if (DstTy == MVT::i32 &&
12570 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12571 return std::make_pair(SDValue(), SDValue());
12572 if (Subtarget->is64Bit() &&
12573 DstTy == MVT::i64 &&
12574 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12575 return std::make_pair(SDValue(), SDValue());
12577 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12579 MachineFunction &MF = DAG.getMachineFunction();
12580 unsigned MemSize = DstTy.getSizeInBits()/8;
12581 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12582 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12585 switch (DstTy.getSimpleVT().SimpleTy) {
12586 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12587 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12588 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12589 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12592 SDValue Chain = DAG.getEntryNode();
12593 SDValue Value = Op.getOperand(0);
12594 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12596 if (UnsignedFixup) {
12598 // Conversion to unsigned i64 is implemented with a select,
12599 // depending on whether the source value fits in the range
12600 // of a signed i64. Let Thresh be the FP equivalent of
12601 // 0x8000000000000000ULL.
12603 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12604 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12605 // Fist-to-mem64 FistSrc
12606 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12607 // to XOR'ing the high 32 bits with Adjust.
12609 // Being a power of 2, Thresh is exactly representable in all FP formats.
12610 // For X87 we'd like to use the smallest FP type for this constant, but
12611 // for DAG type consistency we have to match the FP operand type.
12613 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12614 APFloat::opStatus Status = APFloat::opOK;
12615 bool LosesInfo = false;
12616 if (TheVT == MVT::f64)
12617 // The rounding mode is irrelevant as the conversion should be exact.
12618 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12620 else if (TheVT == MVT::f80)
12621 Status = Thresh.convert(APFloat::x87DoubleExtended,
12622 APFloat::rmNearestTiesToEven, &LosesInfo);
12624 assert(Status == APFloat::opOK && !LosesInfo &&
12625 "FP conversion should have been exact");
12627 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12629 SDValue Cmp = DAG.getSetCC(DL,
12630 getSetCCResultType(DAG.getDataLayout(),
12631 *DAG.getContext(), TheVT),
12632 Value, ThreshVal, ISD::SETLT);
12633 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12634 DAG.getConstant(0, DL, MVT::i32),
12635 DAG.getConstant(0x80000000, DL, MVT::i32));
12636 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12637 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12638 *DAG.getContext(), TheVT),
12639 Value, ThreshVal, ISD::SETLT);
12640 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12643 // FIXME This causes a redundant load/store if the SSE-class value is already
12644 // in memory, such as if it is on the callstack.
12645 if (isScalarFPTypeInSSEReg(TheVT)) {
12646 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12647 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12648 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12650 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12652 Chain, StackSlot, DAG.getValueType(TheVT)
12655 MachineMemOperand *MMO =
12656 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12657 MachineMemOperand::MOLoad, MemSize, MemSize);
12658 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12659 Chain = Value.getValue(1);
12660 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12661 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12664 MachineMemOperand *MMO =
12665 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12666 MachineMemOperand::MOStore, MemSize, MemSize);
12668 if (UnsignedFixup) {
12670 // Insert the FIST, load its result as two i32's,
12671 // and XOR the high i32 with Adjust.
12673 SDValue FistOps[] = { Chain, Value, StackSlot };
12674 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12675 FistOps, DstTy, MMO);
12677 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12678 MachinePointerInfo(),
12679 false, false, false, 0);
12680 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12681 DAG.getConstant(4, DL, PtrVT));
12683 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12684 MachinePointerInfo(),
12685 false, false, false, 0);
12686 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12688 if (Subtarget->is64Bit()) {
12689 // Join High32 and Low32 into a 64-bit result.
12690 // (High32 << 32) | Low32
12691 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12692 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12693 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12694 DAG.getConstant(32, DL, MVT::i8));
12695 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12696 return std::make_pair(Result, SDValue());
12699 SDValue ResultOps[] = { Low32, High32 };
12701 SDValue pair = IsReplace
12702 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12703 : DAG.getMergeValues(ResultOps, DL);
12704 return std::make_pair(pair, SDValue());
12706 // Build the FP_TO_INT*_IN_MEM
12707 SDValue Ops[] = { Chain, Value, StackSlot };
12708 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12710 return std::make_pair(FIST, StackSlot);
12714 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12715 const X86Subtarget *Subtarget) {
12716 MVT VT = Op->getSimpleValueType(0);
12717 SDValue In = Op->getOperand(0);
12718 MVT InVT = In.getSimpleValueType();
12721 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12722 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12724 // Optimize vectors in AVX mode:
12727 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12728 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12729 // Concat upper and lower parts.
12732 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12733 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12734 // Concat upper and lower parts.
12737 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12738 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12739 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12742 if (Subtarget->hasInt256())
12743 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12745 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12746 SDValue Undef = DAG.getUNDEF(InVT);
12747 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12748 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12749 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12751 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12752 VT.getVectorNumElements()/2);
12754 OpLo = DAG.getBitcast(HVT, OpLo);
12755 OpHi = DAG.getBitcast(HVT, OpHi);
12757 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12760 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12761 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12762 MVT VT = Op->getSimpleValueType(0);
12763 SDValue In = Op->getOperand(0);
12764 MVT InVT = In.getSimpleValueType();
12766 unsigned int NumElts = VT.getVectorNumElements();
12767 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12770 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12771 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12773 assert(InVT.getVectorElementType() == MVT::i1);
12774 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12776 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12778 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12780 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12781 if (VT.is512BitVector())
12783 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12786 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12787 SelectionDAG &DAG) {
12788 if (Subtarget->hasFp256())
12789 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12795 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12796 SelectionDAG &DAG) {
12798 MVT VT = Op.getSimpleValueType();
12799 SDValue In = Op.getOperand(0);
12800 MVT SVT = In.getSimpleValueType();
12802 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12803 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12805 if (Subtarget->hasFp256())
12806 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12809 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12810 VT.getVectorNumElements() != SVT.getVectorNumElements());
12814 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12816 MVT VT = Op.getSimpleValueType();
12817 SDValue In = Op.getOperand(0);
12818 MVT InVT = In.getSimpleValueType();
12820 if (VT == MVT::i1) {
12821 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12822 "Invalid scalar TRUNCATE operation");
12823 if (InVT.getSizeInBits() >= 32)
12825 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12826 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12828 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12829 "Invalid TRUNCATE operation");
12831 // move vector to mask - truncate solution for SKX
12832 if (VT.getVectorElementType() == MVT::i1) {
12833 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12834 Subtarget->hasBWI())
12835 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12836 if ((InVT.is256BitVector() || InVT.is128BitVector())
12837 && InVT.getScalarSizeInBits() <= 16 &&
12838 Subtarget->hasBWI() && Subtarget->hasVLX())
12839 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12840 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12841 Subtarget->hasDQI())
12842 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12843 if ((InVT.is256BitVector() || InVT.is128BitVector())
12844 && InVT.getScalarSizeInBits() >= 32 &&
12845 Subtarget->hasDQI() && Subtarget->hasVLX())
12846 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12849 if (VT.getVectorElementType() == MVT::i1) {
12850 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12851 unsigned NumElts = InVT.getVectorNumElements();
12852 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12853 if (InVT.getSizeInBits() < 512) {
12854 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12855 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12860 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12861 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12862 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12865 // vpmovqb/w/d, vpmovdb/w, vpmovwb
12866 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
12867 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
12868 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12870 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12871 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12872 if (Subtarget->hasInt256()) {
12873 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12874 In = DAG.getBitcast(MVT::v8i32, In);
12875 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12877 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12878 DAG.getIntPtrConstant(0, DL));
12881 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12882 DAG.getIntPtrConstant(0, DL));
12883 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12884 DAG.getIntPtrConstant(2, DL));
12885 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12886 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12887 static const int ShufMask[] = {0, 2, 4, 6};
12888 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12891 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12892 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12893 if (Subtarget->hasInt256()) {
12894 In = DAG.getBitcast(MVT::v32i8, In);
12896 SmallVector<SDValue,32> pshufbMask;
12897 for (unsigned i = 0; i < 2; ++i) {
12898 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12899 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12900 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12901 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12902 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12903 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12904 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12905 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12906 for (unsigned j = 0; j < 8; ++j)
12907 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12909 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12910 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12911 In = DAG.getBitcast(MVT::v4i64, In);
12913 static const int ShufMask[] = {0, 2, -1, -1};
12914 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12916 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12917 DAG.getIntPtrConstant(0, DL));
12918 return DAG.getBitcast(VT, In);
12921 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12922 DAG.getIntPtrConstant(0, DL));
12924 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12925 DAG.getIntPtrConstant(4, DL));
12927 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12928 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12930 // The PSHUFB mask:
12931 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12932 -1, -1, -1, -1, -1, -1, -1, -1};
12934 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12935 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12936 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12938 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12939 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12941 // The MOVLHPS Mask:
12942 static const int ShufMask2[] = {0, 1, 4, 5};
12943 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12944 return DAG.getBitcast(MVT::v8i16, res);
12947 // Handle truncation of V256 to V128 using shuffles.
12948 if (!VT.is128BitVector() || !InVT.is256BitVector())
12951 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12953 unsigned NumElems = VT.getVectorNumElements();
12954 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12956 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12957 // Prepare truncation shuffle mask
12958 for (unsigned i = 0; i != NumElems; ++i)
12959 MaskVec[i] = i * 2;
12960 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12961 DAG.getUNDEF(NVT), &MaskVec[0]);
12962 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12963 DAG.getIntPtrConstant(0, DL));
12966 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12967 SelectionDAG &DAG) const {
12968 assert(!Op.getSimpleValueType().isVector());
12970 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12971 /*IsSigned=*/ true, /*IsReplace=*/ false);
12972 SDValue FIST = Vals.first, StackSlot = Vals.second;
12973 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12974 if (!FIST.getNode())
12977 if (StackSlot.getNode())
12978 // Load the result.
12979 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12980 FIST, StackSlot, MachinePointerInfo(),
12981 false, false, false, 0);
12983 // The node is the result.
12987 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12988 SelectionDAG &DAG) const {
12989 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12990 /*IsSigned=*/ false, /*IsReplace=*/ false);
12991 SDValue FIST = Vals.first, StackSlot = Vals.second;
12992 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12993 if (!FIST.getNode())
12996 if (StackSlot.getNode())
12997 // Load the result.
12998 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12999 FIST, StackSlot, MachinePointerInfo(),
13000 false, false, false, 0);
13002 // The node is the result.
13006 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13008 MVT VT = Op.getSimpleValueType();
13009 SDValue In = Op.getOperand(0);
13010 MVT SVT = In.getSimpleValueType();
13012 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13014 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13015 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13016 In, DAG.getUNDEF(SVT)));
13019 /// The only differences between FABS and FNEG are the mask and the logic op.
13020 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13021 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13022 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13023 "Wrong opcode for lowering FABS or FNEG.");
13025 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13027 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13028 // into an FNABS. We'll lower the FABS after that if it is still in use.
13030 for (SDNode *User : Op->uses())
13031 if (User->getOpcode() == ISD::FNEG)
13035 MVT VT = Op.getSimpleValueType();
13037 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13038 // decide if we should generate a 16-byte constant mask when we only need 4 or
13039 // 8 bytes for the scalar case.
13045 if (VT.isVector()) {
13047 EltVT = VT.getVectorElementType();
13048 NumElts = VT.getVectorNumElements();
13050 // There are no scalar bitwise logical SSE/AVX instructions, so we
13051 // generate a 16-byte vector constant and logic op even for the scalar case.
13052 // Using a 16-byte mask allows folding the load of the mask with
13053 // the logic op, so it can save (~4 bytes) on code size.
13054 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13056 NumElts = (VT == MVT::f64) ? 2 : 4;
13059 unsigned EltBits = EltVT.getSizeInBits();
13060 LLVMContext *Context = DAG.getContext();
13061 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13063 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13064 Constant *C = ConstantInt::get(*Context, MaskElt);
13065 C = ConstantVector::getSplat(NumElts, C);
13066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13067 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13068 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13070 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13071 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13072 false, false, false, Alignment);
13074 SDValue Op0 = Op.getOperand(0);
13075 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13077 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13078 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13081 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13083 // For the scalar case extend to a 128-bit vector, perform the logic op,
13084 // and extract the scalar result back out.
13085 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13086 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13087 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13088 DAG.getIntPtrConstant(0, dl));
13091 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13092 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13093 LLVMContext *Context = DAG.getContext();
13094 SDValue Op0 = Op.getOperand(0);
13095 SDValue Op1 = Op.getOperand(1);
13097 MVT VT = Op.getSimpleValueType();
13098 MVT SrcVT = Op1.getSimpleValueType();
13100 // If second operand is smaller, extend it first.
13101 if (SrcVT.bitsLT(VT)) {
13102 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13105 // And if it is bigger, shrink it first.
13106 if (SrcVT.bitsGT(VT)) {
13107 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13111 // At this point the operands and the result should have the same
13112 // type, and that won't be f80 since that is not custom lowered.
13114 const fltSemantics &Sem =
13115 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13116 const unsigned SizeInBits = VT.getSizeInBits();
13118 SmallVector<Constant *, 4> CV(
13119 VT == MVT::f64 ? 2 : 4,
13120 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13122 // First, clear all bits but the sign bit from the second operand (sign).
13123 CV[0] = ConstantFP::get(*Context,
13124 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13125 Constant *C = ConstantVector::get(CV);
13126 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13127 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13129 // Perform all logic operations as 16-byte vectors because there are no
13130 // scalar FP logic instructions in SSE. This allows load folding of the
13131 // constants into the logic instructions.
13132 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13134 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13135 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13136 false, false, false, 16);
13137 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13138 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13140 // Next, clear the sign bit from the first operand (magnitude).
13141 // If it's a constant, we can clear it here.
13142 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13143 APFloat APF = Op0CN->getValueAPF();
13144 // If the magnitude is a positive zero, the sign bit alone is enough.
13145 if (APF.isPosZero())
13146 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13147 DAG.getIntPtrConstant(0, dl));
13149 CV[0] = ConstantFP::get(*Context, APF);
13151 CV[0] = ConstantFP::get(
13153 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13155 C = ConstantVector::get(CV);
13156 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13158 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13159 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13160 false, false, false, 16);
13161 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13162 if (!isa<ConstantFPSDNode>(Op0)) {
13163 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13164 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13166 // OR the magnitude value with the sign bit.
13167 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13168 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13169 DAG.getIntPtrConstant(0, dl));
13172 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13173 SDValue N0 = Op.getOperand(0);
13175 MVT VT = Op.getSimpleValueType();
13177 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13178 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13179 DAG.getConstant(1, dl, VT));
13180 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13183 // Check whether an OR'd tree is PTEST-able.
13184 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13185 SelectionDAG &DAG) {
13186 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13188 if (!Subtarget->hasSSE41())
13191 if (!Op->hasOneUse())
13194 SDNode *N = Op.getNode();
13197 SmallVector<SDValue, 8> Opnds;
13198 DenseMap<SDValue, unsigned> VecInMap;
13199 SmallVector<SDValue, 8> VecIns;
13200 EVT VT = MVT::Other;
13202 // Recognize a special case where a vector is casted into wide integer to
13204 Opnds.push_back(N->getOperand(0));
13205 Opnds.push_back(N->getOperand(1));
13207 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13208 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13209 // BFS traverse all OR'd operands.
13210 if (I->getOpcode() == ISD::OR) {
13211 Opnds.push_back(I->getOperand(0));
13212 Opnds.push_back(I->getOperand(1));
13213 // Re-evaluate the number of nodes to be traversed.
13214 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13218 // Quit if a non-EXTRACT_VECTOR_ELT
13219 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13222 // Quit if without a constant index.
13223 SDValue Idx = I->getOperand(1);
13224 if (!isa<ConstantSDNode>(Idx))
13227 SDValue ExtractedFromVec = I->getOperand(0);
13228 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13229 if (M == VecInMap.end()) {
13230 VT = ExtractedFromVec.getValueType();
13231 // Quit if not 128/256-bit vector.
13232 if (!VT.is128BitVector() && !VT.is256BitVector())
13234 // Quit if not the same type.
13235 if (VecInMap.begin() != VecInMap.end() &&
13236 VT != VecInMap.begin()->first.getValueType())
13238 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13239 VecIns.push_back(ExtractedFromVec);
13241 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13244 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13245 "Not extracted from 128-/256-bit vector.");
13247 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13249 for (DenseMap<SDValue, unsigned>::const_iterator
13250 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13251 // Quit if not all elements are used.
13252 if (I->second != FullMask)
13256 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13258 // Cast all vectors into TestVT for PTEST.
13259 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13260 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13262 // If more than one full vectors are evaluated, OR them first before PTEST.
13263 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13264 // Each iteration will OR 2 nodes and append the result until there is only
13265 // 1 node left, i.e. the final OR'd value of all vectors.
13266 SDValue LHS = VecIns[Slot];
13267 SDValue RHS = VecIns[Slot + 1];
13268 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13271 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13272 VecIns.back(), VecIns.back());
13275 /// \brief return true if \c Op has a use that doesn't just read flags.
13276 static bool hasNonFlagsUse(SDValue Op) {
13277 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13279 SDNode *User = *UI;
13280 unsigned UOpNo = UI.getOperandNo();
13281 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13282 // Look pass truncate.
13283 UOpNo = User->use_begin().getOperandNo();
13284 User = *User->use_begin();
13287 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13288 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13294 /// Emit nodes that will be selected as "test Op0,Op0", or something
13296 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13297 SelectionDAG &DAG) const {
13298 if (Op.getValueType() == MVT::i1) {
13299 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13300 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13301 DAG.getConstant(0, dl, MVT::i8));
13303 // CF and OF aren't always set the way we want. Determine which
13304 // of these we need.
13305 bool NeedCF = false;
13306 bool NeedOF = false;
13309 case X86::COND_A: case X86::COND_AE:
13310 case X86::COND_B: case X86::COND_BE:
13313 case X86::COND_G: case X86::COND_GE:
13314 case X86::COND_L: case X86::COND_LE:
13315 case X86::COND_O: case X86::COND_NO: {
13316 // Check if we really need to set the
13317 // Overflow flag. If NoSignedWrap is present
13318 // that is not actually needed.
13319 switch (Op->getOpcode()) {
13324 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13325 if (BinNode->Flags.hasNoSignedWrap())
13335 // See if we can use the EFLAGS value from the operand instead of
13336 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13337 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13338 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13339 // Emit a CMP with 0, which is the TEST pattern.
13340 //if (Op.getValueType() == MVT::i1)
13341 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13342 // DAG.getConstant(0, MVT::i1));
13343 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13344 DAG.getConstant(0, dl, Op.getValueType()));
13346 unsigned Opcode = 0;
13347 unsigned NumOperands = 0;
13349 // Truncate operations may prevent the merge of the SETCC instruction
13350 // and the arithmetic instruction before it. Attempt to truncate the operands
13351 // of the arithmetic instruction and use a reduced bit-width instruction.
13352 bool NeedTruncation = false;
13353 SDValue ArithOp = Op;
13354 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13355 SDValue Arith = Op->getOperand(0);
13356 // Both the trunc and the arithmetic op need to have one user each.
13357 if (Arith->hasOneUse())
13358 switch (Arith.getOpcode()) {
13365 NeedTruncation = true;
13371 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13372 // which may be the result of a CAST. We use the variable 'Op', which is the
13373 // non-casted variable when we check for possible users.
13374 switch (ArithOp.getOpcode()) {
13376 // Due to an isel shortcoming, be conservative if this add is likely to be
13377 // selected as part of a load-modify-store instruction. When the root node
13378 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13379 // uses of other nodes in the match, such as the ADD in this case. This
13380 // leads to the ADD being left around and reselected, with the result being
13381 // two adds in the output. Alas, even if none our users are stores, that
13382 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13383 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13384 // climbing the DAG back to the root, and it doesn't seem to be worth the
13386 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13387 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13388 if (UI->getOpcode() != ISD::CopyToReg &&
13389 UI->getOpcode() != ISD::SETCC &&
13390 UI->getOpcode() != ISD::STORE)
13393 if (ConstantSDNode *C =
13394 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13395 // An add of one will be selected as an INC.
13396 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13397 Opcode = X86ISD::INC;
13402 // An add of negative one (subtract of one) will be selected as a DEC.
13403 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13404 Opcode = X86ISD::DEC;
13410 // Otherwise use a regular EFLAGS-setting add.
13411 Opcode = X86ISD::ADD;
13416 // If we have a constant logical shift that's only used in a comparison
13417 // against zero turn it into an equivalent AND. This allows turning it into
13418 // a TEST instruction later.
13419 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13420 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13421 EVT VT = Op.getValueType();
13422 unsigned BitWidth = VT.getSizeInBits();
13423 unsigned ShAmt = Op->getConstantOperandVal(1);
13424 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13426 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13427 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13428 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13429 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13431 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13432 DAG.getConstant(Mask, dl, VT));
13433 DAG.ReplaceAllUsesWith(Op, New);
13439 // If the primary and result isn't used, don't bother using X86ISD::AND,
13440 // because a TEST instruction will be better.
13441 if (!hasNonFlagsUse(Op))
13447 // Due to the ISEL shortcoming noted above, be conservative if this op is
13448 // likely to be selected as part of a load-modify-store instruction.
13449 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13450 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13451 if (UI->getOpcode() == ISD::STORE)
13454 // Otherwise use a regular EFLAGS-setting instruction.
13455 switch (ArithOp.getOpcode()) {
13456 default: llvm_unreachable("unexpected operator!");
13457 case ISD::SUB: Opcode = X86ISD::SUB; break;
13458 case ISD::XOR: Opcode = X86ISD::XOR; break;
13459 case ISD::AND: Opcode = X86ISD::AND; break;
13461 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13462 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13463 if (EFLAGS.getNode())
13466 Opcode = X86ISD::OR;
13480 return SDValue(Op.getNode(), 1);
13486 // If we found that truncation is beneficial, perform the truncation and
13488 if (NeedTruncation) {
13489 EVT VT = Op.getValueType();
13490 SDValue WideVal = Op->getOperand(0);
13491 EVT WideVT = WideVal.getValueType();
13492 unsigned ConvertedOp = 0;
13493 // Use a target machine opcode to prevent further DAGCombine
13494 // optimizations that may separate the arithmetic operations
13495 // from the setcc node.
13496 switch (WideVal.getOpcode()) {
13498 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13499 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13500 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13501 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13502 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13506 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13507 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13508 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13509 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13510 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13516 // Emit a CMP with 0, which is the TEST pattern.
13517 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13518 DAG.getConstant(0, dl, Op.getValueType()));
13520 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13521 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13523 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13524 DAG.ReplaceAllUsesWith(Op, New);
13525 return SDValue(New.getNode(), 1);
13528 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13530 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13531 SDLoc dl, SelectionDAG &DAG) const {
13532 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13533 if (C->getAPIntValue() == 0)
13534 return EmitTest(Op0, X86CC, dl, DAG);
13536 if (Op0.getValueType() == MVT::i1)
13537 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13540 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13541 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13542 // Do the comparison at i32 if it's smaller, besides the Atom case.
13543 // This avoids subregister aliasing issues. Keep the smaller reference
13544 // if we're optimizing for size, however, as that'll allow better folding
13545 // of memory operations.
13546 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13547 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13548 !Subtarget->isAtom()) {
13549 unsigned ExtendOp =
13550 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13551 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13552 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13554 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13555 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13556 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13558 return SDValue(Sub.getNode(), 1);
13560 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13563 /// Convert a comparison if required by the subtarget.
13564 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13565 SelectionDAG &DAG) const {
13566 // If the subtarget does not support the FUCOMI instruction, floating-point
13567 // comparisons have to be converted.
13568 if (Subtarget->hasCMov() ||
13569 Cmp.getOpcode() != X86ISD::CMP ||
13570 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13571 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13574 // The instruction selector will select an FUCOM instruction instead of
13575 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13576 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13577 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13579 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13580 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13581 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13582 DAG.getConstant(8, dl, MVT::i8));
13583 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13584 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13587 /// The minimum architected relative accuracy is 2^-12. We need one
13588 /// Newton-Raphson step to have a good float result (24 bits of precision).
13589 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13590 DAGCombinerInfo &DCI,
13591 unsigned &RefinementSteps,
13592 bool &UseOneConstNR) const {
13593 EVT VT = Op.getValueType();
13594 const char *RecipOp;
13596 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13597 // TODO: Add support for AVX512 (v16f32).
13598 // It is likely not profitable to do this for f64 because a double-precision
13599 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13600 // instructions: convert to single, rsqrtss, convert back to double, refine
13601 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13602 // along with FMA, this could be a throughput win.
13603 if (VT == MVT::f32 && Subtarget->hasSSE1())
13605 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13606 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13607 RecipOp = "vec-sqrtf";
13611 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13612 if (!Recips.isEnabled(RecipOp))
13615 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13616 UseOneConstNR = false;
13617 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13620 /// The minimum architected relative accuracy is 2^-12. We need one
13621 /// Newton-Raphson step to have a good float result (24 bits of precision).
13622 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13623 DAGCombinerInfo &DCI,
13624 unsigned &RefinementSteps) const {
13625 EVT VT = Op.getValueType();
13626 const char *RecipOp;
13628 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13629 // TODO: Add support for AVX512 (v16f32).
13630 // It is likely not profitable to do this for f64 because a double-precision
13631 // reciprocal estimate with refinement on x86 prior to FMA requires
13632 // 15 instructions: convert to single, rcpss, convert back to double, refine
13633 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13634 // along with FMA, this could be a throughput win.
13635 if (VT == MVT::f32 && Subtarget->hasSSE1())
13637 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13638 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13639 RecipOp = "vec-divf";
13643 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13644 if (!Recips.isEnabled(RecipOp))
13647 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13648 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13651 /// If we have at least two divisions that use the same divisor, convert to
13652 /// multplication by a reciprocal. This may need to be adjusted for a given
13653 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13654 /// This is because we still need one division to calculate the reciprocal and
13655 /// then we need two multiplies by that reciprocal as replacements for the
13656 /// original divisions.
13657 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13661 static bool isAllOnes(SDValue V) {
13662 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13663 return C && C->isAllOnesValue();
13666 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13667 /// if it's possible.
13668 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13669 SDLoc dl, SelectionDAG &DAG) const {
13670 SDValue Op0 = And.getOperand(0);
13671 SDValue Op1 = And.getOperand(1);
13672 if (Op0.getOpcode() == ISD::TRUNCATE)
13673 Op0 = Op0.getOperand(0);
13674 if (Op1.getOpcode() == ISD::TRUNCATE)
13675 Op1 = Op1.getOperand(0);
13678 if (Op1.getOpcode() == ISD::SHL)
13679 std::swap(Op0, Op1);
13680 if (Op0.getOpcode() == ISD::SHL) {
13681 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13682 if (And00C->getZExtValue() == 1) {
13683 // If we looked past a truncate, check that it's only truncating away
13685 unsigned BitWidth = Op0.getValueSizeInBits();
13686 unsigned AndBitWidth = And.getValueSizeInBits();
13687 if (BitWidth > AndBitWidth) {
13689 DAG.computeKnownBits(Op0, Zeros, Ones);
13690 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13694 RHS = Op0.getOperand(1);
13696 } else if (Op1.getOpcode() == ISD::Constant) {
13697 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13698 uint64_t AndRHSVal = AndRHS->getZExtValue();
13699 SDValue AndLHS = Op0;
13701 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13702 LHS = AndLHS.getOperand(0);
13703 RHS = AndLHS.getOperand(1);
13706 // Use BT if the immediate can't be encoded in a TEST instruction.
13707 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13709 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13713 if (LHS.getNode()) {
13714 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13715 // instruction. Since the shift amount is in-range-or-undefined, we know
13716 // that doing a bittest on the i32 value is ok. We extend to i32 because
13717 // the encoding for the i16 version is larger than the i32 version.
13718 // Also promote i16 to i32 for performance / code size reason.
13719 if (LHS.getValueType() == MVT::i8 ||
13720 LHS.getValueType() == MVT::i16)
13721 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13723 // If the operand types disagree, extend the shift amount to match. Since
13724 // BT ignores high bits (like shifts) we can use anyextend.
13725 if (LHS.getValueType() != RHS.getValueType())
13726 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13728 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13729 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13730 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13731 DAG.getConstant(Cond, dl, MVT::i8), BT);
13737 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13739 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13744 // SSE Condition code mapping:
13753 switch (SetCCOpcode) {
13754 default: llvm_unreachable("Unexpected SETCC condition");
13756 case ISD::SETEQ: SSECC = 0; break;
13758 case ISD::SETGT: Swap = true; // Fallthrough
13760 case ISD::SETOLT: SSECC = 1; break;
13762 case ISD::SETGE: Swap = true; // Fallthrough
13764 case ISD::SETOLE: SSECC = 2; break;
13765 case ISD::SETUO: SSECC = 3; break;
13767 case ISD::SETNE: SSECC = 4; break;
13768 case ISD::SETULE: Swap = true; // Fallthrough
13769 case ISD::SETUGE: SSECC = 5; break;
13770 case ISD::SETULT: Swap = true; // Fallthrough
13771 case ISD::SETUGT: SSECC = 6; break;
13772 case ISD::SETO: SSECC = 7; break;
13774 case ISD::SETONE: SSECC = 8; break;
13777 std::swap(Op0, Op1);
13782 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13783 // ones, and then concatenate the result back.
13784 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13785 MVT VT = Op.getSimpleValueType();
13787 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13788 "Unsupported value type for operation");
13790 unsigned NumElems = VT.getVectorNumElements();
13792 SDValue CC = Op.getOperand(2);
13794 // Extract the LHS vectors
13795 SDValue LHS = Op.getOperand(0);
13796 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13797 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13799 // Extract the RHS vectors
13800 SDValue RHS = Op.getOperand(1);
13801 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13802 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13804 // Issue the operation on the smaller types and concatenate the result back
13805 MVT EltVT = VT.getVectorElementType();
13806 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13807 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13808 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13809 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13812 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13813 SDValue Op0 = Op.getOperand(0);
13814 SDValue Op1 = Op.getOperand(1);
13815 SDValue CC = Op.getOperand(2);
13816 MVT VT = Op.getSimpleValueType();
13819 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13820 "Unexpected type for boolean compare operation");
13821 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13822 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13823 DAG.getConstant(-1, dl, VT));
13824 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13825 DAG.getConstant(-1, dl, VT));
13826 switch (SetCCOpcode) {
13827 default: llvm_unreachable("Unexpected SETCC condition");
13829 // (x == y) -> ~(x ^ y)
13830 return DAG.getNode(ISD::XOR, dl, VT,
13831 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13832 DAG.getConstant(-1, dl, VT));
13834 // (x != y) -> (x ^ y)
13835 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13838 // (x > y) -> (x & ~y)
13839 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13842 // (x < y) -> (~x & y)
13843 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13846 // (x <= y) -> (~x | y)
13847 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13850 // (x >=y) -> (x | ~y)
13851 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13855 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13856 const X86Subtarget *Subtarget) {
13857 SDValue Op0 = Op.getOperand(0);
13858 SDValue Op1 = Op.getOperand(1);
13859 SDValue CC = Op.getOperand(2);
13860 MVT VT = Op.getSimpleValueType();
13863 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13864 Op.getValueType().getScalarType() == MVT::i1 &&
13865 "Cannot set masked compare for this operation");
13867 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13869 bool Unsigned = false;
13872 switch (SetCCOpcode) {
13873 default: llvm_unreachable("Unexpected SETCC condition");
13874 case ISD::SETNE: SSECC = 4; break;
13875 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13876 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13877 case ISD::SETLT: Swap = true; //fall-through
13878 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13879 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13880 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13881 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13882 case ISD::SETULE: Unsigned = true; //fall-through
13883 case ISD::SETLE: SSECC = 2; break;
13887 std::swap(Op0, Op1);
13889 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13890 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13891 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13892 DAG.getConstant(SSECC, dl, MVT::i8));
13895 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13896 /// operand \p Op1. If non-trivial (for example because it's not constant)
13897 /// return an empty value.
13898 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13900 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13904 MVT VT = Op1.getSimpleValueType();
13905 MVT EVT = VT.getVectorElementType();
13906 unsigned n = VT.getVectorNumElements();
13907 SmallVector<SDValue, 8> ULTOp1;
13909 for (unsigned i = 0; i < n; ++i) {
13910 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13911 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13914 // Avoid underflow.
13915 APInt Val = Elt->getAPIntValue();
13919 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13922 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13925 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13926 SelectionDAG &DAG) {
13927 SDValue Op0 = Op.getOperand(0);
13928 SDValue Op1 = Op.getOperand(1);
13929 SDValue CC = Op.getOperand(2);
13930 MVT VT = Op.getSimpleValueType();
13931 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13932 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13937 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13938 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13941 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13942 unsigned Opc = X86ISD::CMPP;
13943 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13944 assert(VT.getVectorNumElements() <= 16);
13945 Opc = X86ISD::CMPM;
13947 // In the two special cases we can't handle, emit two comparisons.
13950 unsigned CombineOpc;
13951 if (SetCCOpcode == ISD::SETUEQ) {
13952 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13954 assert(SetCCOpcode == ISD::SETONE);
13955 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13958 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13959 DAG.getConstant(CC0, dl, MVT::i8));
13960 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13961 DAG.getConstant(CC1, dl, MVT::i8));
13962 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13964 // Handle all other FP comparisons here.
13965 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13966 DAG.getConstant(SSECC, dl, MVT::i8));
13969 // Break 256-bit integer vector compare into smaller ones.
13970 if (VT.is256BitVector() && !Subtarget->hasInt256())
13971 return Lower256IntVSETCC(Op, DAG);
13973 EVT OpVT = Op1.getValueType();
13974 if (OpVT.getVectorElementType() == MVT::i1)
13975 return LowerBoolVSETCC_AVX512(Op, DAG);
13977 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13978 if (Subtarget->hasAVX512()) {
13979 if (Op1.getValueType().is512BitVector() ||
13980 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13981 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13982 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13984 // In AVX-512 architecture setcc returns mask with i1 elements,
13985 // But there is no compare instruction for i8 and i16 elements in KNL.
13986 // We are not talking about 512-bit operands in this case, these
13987 // types are illegal.
13989 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13990 OpVT.getVectorElementType().getSizeInBits() >= 8))
13991 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13992 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13995 // We are handling one of the integer comparisons here. Since SSE only has
13996 // GT and EQ comparisons for integer, swapping operands and multiple
13997 // operations may be required for some comparisons.
13999 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14000 bool Subus = false;
14002 switch (SetCCOpcode) {
14003 default: llvm_unreachable("Unexpected SETCC condition");
14004 case ISD::SETNE: Invert = true;
14005 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14006 case ISD::SETLT: Swap = true;
14007 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14008 case ISD::SETGE: Swap = true;
14009 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14010 Invert = true; break;
14011 case ISD::SETULT: Swap = true;
14012 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14013 FlipSigns = true; break;
14014 case ISD::SETUGE: Swap = true;
14015 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14016 FlipSigns = true; Invert = true; break;
14019 // Special case: Use min/max operations for SETULE/SETUGE
14020 MVT VET = VT.getVectorElementType();
14022 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14023 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14026 switch (SetCCOpcode) {
14028 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14029 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14032 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14035 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14036 if (!MinMax && hasSubus) {
14037 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14039 // t = psubus Op0, Op1
14040 // pcmpeq t, <0..0>
14041 switch (SetCCOpcode) {
14043 case ISD::SETULT: {
14044 // If the comparison is against a constant we can turn this into a
14045 // setule. With psubus, setule does not require a swap. This is
14046 // beneficial because the constant in the register is no longer
14047 // destructed as the destination so it can be hoisted out of a loop.
14048 // Only do this pre-AVX since vpcmp* is no longer destructive.
14049 if (Subtarget->hasAVX())
14051 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14052 if (ULEOp1.getNode()) {
14054 Subus = true; Invert = false; Swap = false;
14058 // Psubus is better than flip-sign because it requires no inversion.
14059 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14060 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14064 Opc = X86ISD::SUBUS;
14070 std::swap(Op0, Op1);
14072 // Check that the operation in question is available (most are plain SSE2,
14073 // but PCMPGTQ and PCMPEQQ have different requirements).
14074 if (VT == MVT::v2i64) {
14075 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14076 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14078 // First cast everything to the right type.
14079 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14080 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14082 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14083 // bits of the inputs before performing those operations. The lower
14084 // compare is always unsigned.
14087 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14089 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14090 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14091 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14092 Sign, Zero, Sign, Zero);
14094 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14095 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14097 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14098 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14099 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14101 // Create masks for only the low parts/high parts of the 64 bit integers.
14102 static const int MaskHi[] = { 1, 1, 3, 3 };
14103 static const int MaskLo[] = { 0, 0, 2, 2 };
14104 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14105 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14106 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14108 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14109 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14112 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14114 return DAG.getBitcast(VT, Result);
14117 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14118 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14119 // pcmpeqd + pshufd + pand.
14120 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14122 // First cast everything to the right type.
14123 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14124 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14127 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14129 // Make sure the lower and upper halves are both all-ones.
14130 static const int Mask[] = { 1, 0, 3, 2 };
14131 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14132 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14135 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14137 return DAG.getBitcast(VT, Result);
14141 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14142 // bits of the inputs before performing those operations.
14144 EVT EltVT = VT.getVectorElementType();
14145 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14147 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14148 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14151 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14153 // If the logical-not of the result is required, perform that now.
14155 Result = DAG.getNOT(dl, Result, VT);
14158 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14161 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14162 getZeroVector(VT, Subtarget, DAG, dl));
14167 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14169 MVT VT = Op.getSimpleValueType();
14171 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14173 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14174 && "SetCC type must be 8-bit or 1-bit integer");
14175 SDValue Op0 = Op.getOperand(0);
14176 SDValue Op1 = Op.getOperand(1);
14178 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14180 // Optimize to BT if possible.
14181 // Lower (X & (1 << N)) == 0 to BT(X, N).
14182 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14183 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14184 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14185 Op1.getOpcode() == ISD::Constant &&
14186 cast<ConstantSDNode>(Op1)->isNullValue() &&
14187 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14188 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14189 if (NewSetCC.getNode()) {
14191 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14196 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14198 if (Op1.getOpcode() == ISD::Constant &&
14199 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14200 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14201 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14203 // If the input is a setcc, then reuse the input setcc or use a new one with
14204 // the inverted condition.
14205 if (Op0.getOpcode() == X86ISD::SETCC) {
14206 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14207 bool Invert = (CC == ISD::SETNE) ^
14208 cast<ConstantSDNode>(Op1)->isNullValue();
14212 CCode = X86::GetOppositeBranchCondition(CCode);
14213 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14214 DAG.getConstant(CCode, dl, MVT::i8),
14215 Op0.getOperand(1));
14217 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14221 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14222 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14223 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14225 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14226 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14229 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14230 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14231 if (X86CC == X86::COND_INVALID)
14234 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14235 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14236 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14237 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14239 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14243 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14244 static bool isX86LogicalCmp(SDValue Op) {
14245 unsigned Opc = Op.getNode()->getOpcode();
14246 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14247 Opc == X86ISD::SAHF)
14249 if (Op.getResNo() == 1 &&
14250 (Opc == X86ISD::ADD ||
14251 Opc == X86ISD::SUB ||
14252 Opc == X86ISD::ADC ||
14253 Opc == X86ISD::SBB ||
14254 Opc == X86ISD::SMUL ||
14255 Opc == X86ISD::UMUL ||
14256 Opc == X86ISD::INC ||
14257 Opc == X86ISD::DEC ||
14258 Opc == X86ISD::OR ||
14259 Opc == X86ISD::XOR ||
14260 Opc == X86ISD::AND))
14263 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14269 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14270 if (V.getOpcode() != ISD::TRUNCATE)
14273 SDValue VOp0 = V.getOperand(0);
14274 unsigned InBits = VOp0.getValueSizeInBits();
14275 unsigned Bits = V.getValueSizeInBits();
14276 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14279 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14280 bool addTest = true;
14281 SDValue Cond = Op.getOperand(0);
14282 SDValue Op1 = Op.getOperand(1);
14283 SDValue Op2 = Op.getOperand(2);
14285 EVT VT = Op1.getValueType();
14288 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14289 // are available or VBLENDV if AVX is available.
14290 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14291 if (Cond.getOpcode() == ISD::SETCC &&
14292 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14293 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14294 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14295 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14296 int SSECC = translateX86FSETCC(
14297 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14300 if (Subtarget->hasAVX512()) {
14301 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14302 DAG.getConstant(SSECC, DL, MVT::i8));
14303 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14306 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14307 DAG.getConstant(SSECC, DL, MVT::i8));
14309 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14310 // of 3 logic instructions for size savings and potentially speed.
14311 // Unfortunately, there is no scalar form of VBLENDV.
14313 // If either operand is a constant, don't try this. We can expect to
14314 // optimize away at least one of the logic instructions later in that
14315 // case, so that sequence would be faster than a variable blend.
14317 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14318 // uses XMM0 as the selection register. That may need just as many
14319 // instructions as the AND/ANDN/OR sequence due to register moves, so
14322 if (Subtarget->hasAVX() &&
14323 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14325 // Convert to vectors, do a VSELECT, and convert back to scalar.
14326 // All of the conversions should be optimized away.
14328 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14329 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14330 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14331 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14333 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14334 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14336 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14338 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14339 VSel, DAG.getIntPtrConstant(0, DL));
14341 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14342 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14343 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14347 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14349 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14350 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14351 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14352 Op1Scalar = Op1.getOperand(0);
14354 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14355 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14356 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14357 Op2Scalar = Op2.getOperand(0);
14358 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14359 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14360 Op1Scalar.getValueType(),
14361 Cond, Op1Scalar, Op2Scalar);
14362 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14363 return DAG.getBitcast(VT, newSelect);
14364 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14365 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14366 DAG.getIntPtrConstant(0, DL));
14370 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14371 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14372 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14373 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14374 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14375 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14376 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14378 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14381 if (Cond.getOpcode() == ISD::SETCC) {
14382 SDValue NewCond = LowerSETCC(Cond, DAG);
14383 if (NewCond.getNode())
14387 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14388 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14389 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14390 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14391 if (Cond.getOpcode() == X86ISD::SETCC &&
14392 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14393 isZero(Cond.getOperand(1).getOperand(1))) {
14394 SDValue Cmp = Cond.getOperand(1);
14396 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14398 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14399 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14400 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14402 SDValue CmpOp0 = Cmp.getOperand(0);
14403 // Apply further optimizations for special cases
14404 // (select (x != 0), -1, 0) -> neg & sbb
14405 // (select (x == 0), 0, -1) -> neg & sbb
14406 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14407 if (YC->isNullValue() &&
14408 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14409 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14410 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14411 DAG.getConstant(0, DL,
14412 CmpOp0.getValueType()),
14414 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14415 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14416 SDValue(Neg.getNode(), 1));
14420 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14421 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14422 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14424 SDValue Res = // Res = 0 or -1.
14425 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14426 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14428 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14429 Res = DAG.getNOT(DL, Res, Res.getValueType());
14431 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14432 if (!N2C || !N2C->isNullValue())
14433 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14438 // Look past (and (setcc_carry (cmp ...)), 1).
14439 if (Cond.getOpcode() == ISD::AND &&
14440 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14441 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14442 if (C && C->getAPIntValue() == 1)
14443 Cond = Cond.getOperand(0);
14446 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14447 // setting operand in place of the X86ISD::SETCC.
14448 unsigned CondOpcode = Cond.getOpcode();
14449 if (CondOpcode == X86ISD::SETCC ||
14450 CondOpcode == X86ISD::SETCC_CARRY) {
14451 CC = Cond.getOperand(0);
14453 SDValue Cmp = Cond.getOperand(1);
14454 unsigned Opc = Cmp.getOpcode();
14455 MVT VT = Op.getSimpleValueType();
14457 bool IllegalFPCMov = false;
14458 if (VT.isFloatingPoint() && !VT.isVector() &&
14459 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14460 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14462 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14463 Opc == X86ISD::BT) { // FIXME
14467 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14468 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14469 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14470 Cond.getOperand(0).getValueType() != MVT::i8)) {
14471 SDValue LHS = Cond.getOperand(0);
14472 SDValue RHS = Cond.getOperand(1);
14473 unsigned X86Opcode;
14476 switch (CondOpcode) {
14477 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14478 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14479 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14480 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14481 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14482 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14483 default: llvm_unreachable("unexpected overflowing operator");
14485 if (CondOpcode == ISD::UMULO)
14486 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14489 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14491 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14493 if (CondOpcode == ISD::UMULO)
14494 Cond = X86Op.getValue(2);
14496 Cond = X86Op.getValue(1);
14498 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14503 // Look past the truncate if the high bits are known zero.
14504 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14505 Cond = Cond.getOperand(0);
14507 // We know the result of AND is compared against zero. Try to match
14509 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14510 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14511 if (NewSetCC.getNode()) {
14512 CC = NewSetCC.getOperand(0);
14513 Cond = NewSetCC.getOperand(1);
14520 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14521 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14524 // a < b ? -1 : 0 -> RES = ~setcc_carry
14525 // a < b ? 0 : -1 -> RES = setcc_carry
14526 // a >= b ? -1 : 0 -> RES = setcc_carry
14527 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14528 if (Cond.getOpcode() == X86ISD::SUB) {
14529 Cond = ConvertCmpIfNecessary(Cond, DAG);
14530 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14532 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14533 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14534 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14535 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14537 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14538 return DAG.getNOT(DL, Res, Res.getValueType());
14543 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14544 // widen the cmov and push the truncate through. This avoids introducing a new
14545 // branch during isel and doesn't add any extensions.
14546 if (Op.getValueType() == MVT::i8 &&
14547 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14548 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14549 if (T1.getValueType() == T2.getValueType() &&
14550 // Blacklist CopyFromReg to avoid partial register stalls.
14551 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14552 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14553 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14554 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14558 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14559 // condition is true.
14560 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14561 SDValue Ops[] = { Op2, Op1, CC, Cond };
14562 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14565 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14566 const X86Subtarget *Subtarget,
14567 SelectionDAG &DAG) {
14568 MVT VT = Op->getSimpleValueType(0);
14569 SDValue In = Op->getOperand(0);
14570 MVT InVT = In.getSimpleValueType();
14571 MVT VTElt = VT.getVectorElementType();
14572 MVT InVTElt = InVT.getVectorElementType();
14576 if ((InVTElt == MVT::i1) &&
14577 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14578 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14580 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14581 VTElt.getSizeInBits() <= 16)) ||
14583 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14584 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14586 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14587 VTElt.getSizeInBits() >= 32))))
14588 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14590 unsigned int NumElts = VT.getVectorNumElements();
14592 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14595 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14596 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14597 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14598 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14601 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14602 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14604 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14607 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14609 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14610 if (VT.is512BitVector())
14612 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14615 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14616 const X86Subtarget *Subtarget,
14617 SelectionDAG &DAG) {
14618 SDValue In = Op->getOperand(0);
14619 MVT VT = Op->getSimpleValueType(0);
14620 MVT InVT = In.getSimpleValueType();
14621 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14623 MVT InSVT = InVT.getScalarType();
14624 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14626 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14628 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14633 // SSE41 targets can use the pmovsx* instructions directly.
14634 if (Subtarget->hasSSE41())
14635 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14637 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14641 // As SRAI is only available on i16/i32 types, we expand only up to i32
14642 // and handle i64 separately.
14643 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14644 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14645 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14646 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14647 Curr = DAG.getBitcast(CurrVT, Curr);
14650 SDValue SignExt = Curr;
14651 if (CurrVT != InVT) {
14652 unsigned SignExtShift =
14653 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14654 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14655 DAG.getConstant(SignExtShift, dl, MVT::i8));
14661 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14662 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14663 DAG.getConstant(31, dl, MVT::i8));
14664 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14665 return DAG.getBitcast(VT, Ext);
14671 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14672 SelectionDAG &DAG) {
14673 MVT VT = Op->getSimpleValueType(0);
14674 SDValue In = Op->getOperand(0);
14675 MVT InVT = In.getSimpleValueType();
14678 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14679 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14681 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14682 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14683 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14686 if (Subtarget->hasInt256())
14687 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14689 // Optimize vectors in AVX mode
14690 // Sign extend v8i16 to v8i32 and
14693 // Divide input vector into two parts
14694 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14695 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14696 // concat the vectors to original VT
14698 unsigned NumElems = InVT.getVectorNumElements();
14699 SDValue Undef = DAG.getUNDEF(InVT);
14701 SmallVector<int,8> ShufMask1(NumElems, -1);
14702 for (unsigned i = 0; i != NumElems/2; ++i)
14705 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14707 SmallVector<int,8> ShufMask2(NumElems, -1);
14708 for (unsigned i = 0; i != NumElems/2; ++i)
14709 ShufMask2[i] = i + NumElems/2;
14711 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14713 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14714 VT.getVectorNumElements()/2);
14716 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14717 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14719 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14722 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14723 // may emit an illegal shuffle but the expansion is still better than scalar
14724 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14725 // we'll emit a shuffle and a arithmetic shift.
14726 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14727 // TODO: It is possible to support ZExt by zeroing the undef values during
14728 // the shuffle phase or after the shuffle.
14729 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14730 SelectionDAG &DAG) {
14731 MVT RegVT = Op.getSimpleValueType();
14732 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14733 assert(RegVT.isInteger() &&
14734 "We only custom lower integer vector sext loads.");
14736 // Nothing useful we can do without SSE2 shuffles.
14737 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14739 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14741 EVT MemVT = Ld->getMemoryVT();
14742 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14743 unsigned RegSz = RegVT.getSizeInBits();
14745 ISD::LoadExtType Ext = Ld->getExtensionType();
14747 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14748 && "Only anyext and sext are currently implemented.");
14749 assert(MemVT != RegVT && "Cannot extend to the same type");
14750 assert(MemVT.isVector() && "Must load a vector from memory");
14752 unsigned NumElems = RegVT.getVectorNumElements();
14753 unsigned MemSz = MemVT.getSizeInBits();
14754 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14756 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14757 // The only way in which we have a legal 256-bit vector result but not the
14758 // integer 256-bit operations needed to directly lower a sextload is if we
14759 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14760 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14761 // correctly legalized. We do this late to allow the canonical form of
14762 // sextload to persist throughout the rest of the DAG combiner -- it wants
14763 // to fold together any extensions it can, and so will fuse a sign_extend
14764 // of an sextload into a sextload targeting a wider value.
14766 if (MemSz == 128) {
14767 // Just switch this to a normal load.
14768 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14769 "it must be a legal 128-bit vector "
14771 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14772 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14773 Ld->isInvariant(), Ld->getAlignment());
14775 assert(MemSz < 128 &&
14776 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14777 // Do an sext load to a 128-bit vector type. We want to use the same
14778 // number of elements, but elements half as wide. This will end up being
14779 // recursively lowered by this routine, but will succeed as we definitely
14780 // have all the necessary features if we're using AVX1.
14782 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14783 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14785 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14786 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14787 Ld->isNonTemporal(), Ld->isInvariant(),
14788 Ld->getAlignment());
14791 // Replace chain users with the new chain.
14792 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14793 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14795 // Finally, do a normal sign-extend to the desired register.
14796 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14799 // All sizes must be a power of two.
14800 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14801 "Non-power-of-two elements are not custom lowered!");
14803 // Attempt to load the original value using scalar loads.
14804 // Find the largest scalar type that divides the total loaded size.
14805 MVT SclrLoadTy = MVT::i8;
14806 for (MVT Tp : MVT::integer_valuetypes()) {
14807 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14812 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14813 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14815 SclrLoadTy = MVT::f64;
14817 // Calculate the number of scalar loads that we need to perform
14818 // in order to load our vector from memory.
14819 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14821 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14822 "Can only lower sext loads with a single scalar load!");
14824 unsigned loadRegZize = RegSz;
14825 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14828 // Represent our vector as a sequence of elements which are the
14829 // largest scalar that we can load.
14830 EVT LoadUnitVecVT = EVT::getVectorVT(
14831 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14833 // Represent the data using the same element type that is stored in
14834 // memory. In practice, we ''widen'' MemVT.
14836 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14837 loadRegZize / MemVT.getScalarType().getSizeInBits());
14839 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14840 "Invalid vector type");
14842 // We can't shuffle using an illegal type.
14843 assert(TLI.isTypeLegal(WideVecVT) &&
14844 "We only lower types that form legal widened vector types");
14846 SmallVector<SDValue, 8> Chains;
14847 SDValue Ptr = Ld->getBasePtr();
14848 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
14849 TLI.getPointerTy(DAG.getDataLayout()));
14850 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14852 for (unsigned i = 0; i < NumLoads; ++i) {
14853 // Perform a single load.
14854 SDValue ScalarLoad =
14855 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14856 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14857 Ld->getAlignment());
14858 Chains.push_back(ScalarLoad.getValue(1));
14859 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14860 // another round of DAGCombining.
14862 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14864 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14865 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14867 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14870 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14872 // Bitcast the loaded value to a vector of the original element type, in
14873 // the size of the target vector type.
14874 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14875 unsigned SizeRatio = RegSz / MemSz;
14877 if (Ext == ISD::SEXTLOAD) {
14878 // If we have SSE4.1, we can directly emit a VSEXT node.
14879 if (Subtarget->hasSSE41()) {
14880 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14881 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14885 // Otherwise we'll shuffle the small elements in the high bits of the
14886 // larger type and perform an arithmetic shift. If the shift is not legal
14887 // it's better to scalarize.
14888 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14889 "We can't implement a sext load without an arithmetic right shift!");
14891 // Redistribute the loaded elements into the different locations.
14892 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14893 for (unsigned i = 0; i != NumElems; ++i)
14894 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14896 SDValue Shuff = DAG.getVectorShuffle(
14897 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14899 Shuff = DAG.getBitcast(RegVT, Shuff);
14901 // Build the arithmetic shift.
14902 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14903 MemVT.getVectorElementType().getSizeInBits();
14905 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14906 DAG.getConstant(Amt, dl, RegVT));
14908 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14912 // Redistribute the loaded elements into the different locations.
14913 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14914 for (unsigned i = 0; i != NumElems; ++i)
14915 ShuffleVec[i * SizeRatio] = i;
14917 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14918 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14920 // Bitcast to the requested type.
14921 Shuff = DAG.getBitcast(RegVT, Shuff);
14922 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14926 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14927 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14928 // from the AND / OR.
14929 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14930 Opc = Op.getOpcode();
14931 if (Opc != ISD::OR && Opc != ISD::AND)
14933 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14934 Op.getOperand(0).hasOneUse() &&
14935 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14936 Op.getOperand(1).hasOneUse());
14939 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14940 // 1 and that the SETCC node has a single use.
14941 static bool isXor1OfSetCC(SDValue Op) {
14942 if (Op.getOpcode() != ISD::XOR)
14944 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14945 if (N1C && N1C->getAPIntValue() == 1) {
14946 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14947 Op.getOperand(0).hasOneUse();
14952 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14953 bool addTest = true;
14954 SDValue Chain = Op.getOperand(0);
14955 SDValue Cond = Op.getOperand(1);
14956 SDValue Dest = Op.getOperand(2);
14959 bool Inverted = false;
14961 if (Cond.getOpcode() == ISD::SETCC) {
14962 // Check for setcc([su]{add,sub,mul}o == 0).
14963 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14964 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14965 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14966 Cond.getOperand(0).getResNo() == 1 &&
14967 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14968 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14969 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14970 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14971 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14972 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14974 Cond = Cond.getOperand(0);
14976 SDValue NewCond = LowerSETCC(Cond, DAG);
14977 if (NewCond.getNode())
14982 // FIXME: LowerXALUO doesn't handle these!!
14983 else if (Cond.getOpcode() == X86ISD::ADD ||
14984 Cond.getOpcode() == X86ISD::SUB ||
14985 Cond.getOpcode() == X86ISD::SMUL ||
14986 Cond.getOpcode() == X86ISD::UMUL)
14987 Cond = LowerXALUO(Cond, DAG);
14990 // Look pass (and (setcc_carry (cmp ...)), 1).
14991 if (Cond.getOpcode() == ISD::AND &&
14992 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14993 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14994 if (C && C->getAPIntValue() == 1)
14995 Cond = Cond.getOperand(0);
14998 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14999 // setting operand in place of the X86ISD::SETCC.
15000 unsigned CondOpcode = Cond.getOpcode();
15001 if (CondOpcode == X86ISD::SETCC ||
15002 CondOpcode == X86ISD::SETCC_CARRY) {
15003 CC = Cond.getOperand(0);
15005 SDValue Cmp = Cond.getOperand(1);
15006 unsigned Opc = Cmp.getOpcode();
15007 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15008 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15012 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15016 // These can only come from an arithmetic instruction with overflow,
15017 // e.g. SADDO, UADDO.
15018 Cond = Cond.getNode()->getOperand(1);
15024 CondOpcode = Cond.getOpcode();
15025 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15026 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15027 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15028 Cond.getOperand(0).getValueType() != MVT::i8)) {
15029 SDValue LHS = Cond.getOperand(0);
15030 SDValue RHS = Cond.getOperand(1);
15031 unsigned X86Opcode;
15034 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15035 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15037 switch (CondOpcode) {
15038 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15040 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15042 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15045 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15046 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15050 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15053 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15054 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15055 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15056 default: llvm_unreachable("unexpected overflowing operator");
15059 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15060 if (CondOpcode == ISD::UMULO)
15061 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15064 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15066 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15068 if (CondOpcode == ISD::UMULO)
15069 Cond = X86Op.getValue(2);
15071 Cond = X86Op.getValue(1);
15073 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15077 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15078 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15079 if (CondOpc == ISD::OR) {
15080 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15081 // two branches instead of an explicit OR instruction with a
15083 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15084 isX86LogicalCmp(Cmp)) {
15085 CC = Cond.getOperand(0).getOperand(0);
15086 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15087 Chain, Dest, CC, Cmp);
15088 CC = Cond.getOperand(1).getOperand(0);
15092 } else { // ISD::AND
15093 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15094 // two branches instead of an explicit AND instruction with a
15095 // separate test. However, we only do this if this block doesn't
15096 // have a fall-through edge, because this requires an explicit
15097 // jmp when the condition is false.
15098 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15099 isX86LogicalCmp(Cmp) &&
15100 Op.getNode()->hasOneUse()) {
15101 X86::CondCode CCode =
15102 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15103 CCode = X86::GetOppositeBranchCondition(CCode);
15104 CC = DAG.getConstant(CCode, dl, MVT::i8);
15105 SDNode *User = *Op.getNode()->use_begin();
15106 // Look for an unconditional branch following this conditional branch.
15107 // We need this because we need to reverse the successors in order
15108 // to implement FCMP_OEQ.
15109 if (User->getOpcode() == ISD::BR) {
15110 SDValue FalseBB = User->getOperand(1);
15112 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15113 assert(NewBR == User);
15117 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15118 Chain, Dest, CC, Cmp);
15119 X86::CondCode CCode =
15120 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15121 CCode = X86::GetOppositeBranchCondition(CCode);
15122 CC = DAG.getConstant(CCode, dl, MVT::i8);
15128 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15129 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15130 // It should be transformed during dag combiner except when the condition
15131 // is set by a arithmetics with overflow node.
15132 X86::CondCode CCode =
15133 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15134 CCode = X86::GetOppositeBranchCondition(CCode);
15135 CC = DAG.getConstant(CCode, dl, MVT::i8);
15136 Cond = Cond.getOperand(0).getOperand(1);
15138 } else if (Cond.getOpcode() == ISD::SETCC &&
15139 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15140 // For FCMP_OEQ, we can emit
15141 // two branches instead of an explicit AND instruction with a
15142 // separate test. However, we only do this if this block doesn't
15143 // have a fall-through edge, because this requires an explicit
15144 // jmp when the condition is false.
15145 if (Op.getNode()->hasOneUse()) {
15146 SDNode *User = *Op.getNode()->use_begin();
15147 // Look for an unconditional branch following this conditional branch.
15148 // We need this because we need to reverse the successors in order
15149 // to implement FCMP_OEQ.
15150 if (User->getOpcode() == ISD::BR) {
15151 SDValue FalseBB = User->getOperand(1);
15153 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15154 assert(NewBR == User);
15158 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15159 Cond.getOperand(0), Cond.getOperand(1));
15160 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15161 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15162 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15163 Chain, Dest, CC, Cmp);
15164 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15169 } else if (Cond.getOpcode() == ISD::SETCC &&
15170 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15171 // For FCMP_UNE, we can emit
15172 // two branches instead of an explicit AND instruction with a
15173 // separate test. However, we only do this if this block doesn't
15174 // have a fall-through edge, because this requires an explicit
15175 // jmp when the condition is false.
15176 if (Op.getNode()->hasOneUse()) {
15177 SDNode *User = *Op.getNode()->use_begin();
15178 // Look for an unconditional branch following this conditional branch.
15179 // We need this because we need to reverse the successors in order
15180 // to implement FCMP_UNE.
15181 if (User->getOpcode() == ISD::BR) {
15182 SDValue FalseBB = User->getOperand(1);
15184 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15185 assert(NewBR == User);
15188 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15189 Cond.getOperand(0), Cond.getOperand(1));
15190 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15191 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15192 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15193 Chain, Dest, CC, Cmp);
15194 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15204 // Look pass the truncate if the high bits are known zero.
15205 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15206 Cond = Cond.getOperand(0);
15208 // We know the result of AND is compared against zero. Try to match
15210 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15211 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15212 if (NewSetCC.getNode()) {
15213 CC = NewSetCC.getOperand(0);
15214 Cond = NewSetCC.getOperand(1);
15221 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15222 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15223 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15225 Cond = ConvertCmpIfNecessary(Cond, DAG);
15226 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15227 Chain, Dest, CC, Cond);
15230 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15231 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15232 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15233 // that the guard pages used by the OS virtual memory manager are allocated in
15234 // correct sequence.
15236 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15237 SelectionDAG &DAG) const {
15238 MachineFunction &MF = DAG.getMachineFunction();
15239 bool SplitStack = MF.shouldSplitStack();
15240 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15246 SDNode* Node = Op.getNode();
15248 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15249 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15250 " not tell us which reg is the stack pointer!");
15251 EVT VT = Node->getValueType(0);
15252 SDValue Tmp1 = SDValue(Node, 0);
15253 SDValue Tmp2 = SDValue(Node, 1);
15254 SDValue Tmp3 = Node->getOperand(2);
15255 SDValue Chain = Tmp1.getOperand(0);
15257 // Chain the dynamic stack allocation so that it doesn't modify the stack
15258 // pointer when other instructions are using the stack.
15259 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15262 SDValue Size = Tmp2.getOperand(1);
15263 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15264 Chain = SP.getValue(1);
15265 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15266 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15267 unsigned StackAlign = TFI.getStackAlignment();
15268 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15269 if (Align > StackAlign)
15270 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15271 DAG.getConstant(-(uint64_t)Align, dl, VT));
15272 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15274 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15275 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15278 SDValue Ops[2] = { Tmp1, Tmp2 };
15279 return DAG.getMergeValues(Ops, dl);
15283 SDValue Chain = Op.getOperand(0);
15284 SDValue Size = Op.getOperand(1);
15285 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15286 EVT VT = Op.getNode()->getValueType(0);
15288 bool Is64Bit = Subtarget->is64Bit();
15289 MVT SPTy = getPointerTy(DAG.getDataLayout());
15292 MachineRegisterInfo &MRI = MF.getRegInfo();
15295 // The 64 bit implementation of segmented stacks needs to clobber both r10
15296 // r11. This makes it impossible to use it along with nested parameters.
15297 const Function *F = MF.getFunction();
15299 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15301 if (I->hasNestAttr())
15302 report_fatal_error("Cannot use segmented stacks with functions that "
15303 "have nested arguments.");
15306 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15307 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15308 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15309 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15310 DAG.getRegister(Vreg, SPTy));
15311 SDValue Ops1[2] = { Value, Chain };
15312 return DAG.getMergeValues(Ops1, dl);
15315 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15317 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15318 Flag = Chain.getValue(1);
15319 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15321 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15323 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15324 unsigned SPReg = RegInfo->getStackRegister();
15325 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15326 Chain = SP.getValue(1);
15329 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15330 DAG.getConstant(-(uint64_t)Align, dl, VT));
15331 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15334 SDValue Ops1[2] = { SP, Chain };
15335 return DAG.getMergeValues(Ops1, dl);
15339 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15340 MachineFunction &MF = DAG.getMachineFunction();
15341 auto PtrVT = getPointerTy(MF.getDataLayout());
15342 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15344 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15347 if (!Subtarget->is64Bit() ||
15348 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15349 // vastart just stores the address of the VarArgsFrameIndex slot into the
15350 // memory location argument.
15351 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15352 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15353 MachinePointerInfo(SV), false, false, 0);
15357 // gp_offset (0 - 6 * 8)
15358 // fp_offset (48 - 48 + 8 * 16)
15359 // overflow_arg_area (point to parameters coming in memory).
15361 SmallVector<SDValue, 8> MemOps;
15362 SDValue FIN = Op.getOperand(1);
15364 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15365 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15367 FIN, MachinePointerInfo(SV), false, false, 0);
15368 MemOps.push_back(Store);
15371 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15372 Store = DAG.getStore(Op.getOperand(0), DL,
15373 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15375 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15376 MemOps.push_back(Store);
15378 // Store ptr to overflow_arg_area
15379 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15380 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15381 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15382 MachinePointerInfo(SV, 8),
15384 MemOps.push_back(Store);
15386 // Store ptr to reg_save_area.
15387 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(8, DL));
15388 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15389 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15390 MachinePointerInfo(SV, 16), false, false, 0);
15391 MemOps.push_back(Store);
15392 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15395 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15396 assert(Subtarget->is64Bit() &&
15397 "LowerVAARG only handles 64-bit va_arg!");
15398 assert(Op.getNode()->getNumOperands() == 4);
15400 MachineFunction &MF = DAG.getMachineFunction();
15401 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15402 // The Win64 ABI uses char* instead of a structure.
15403 return DAG.expandVAArg(Op.getNode());
15405 SDValue Chain = Op.getOperand(0);
15406 SDValue SrcPtr = Op.getOperand(1);
15407 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15408 unsigned Align = Op.getConstantOperandVal(3);
15411 EVT ArgVT = Op.getNode()->getValueType(0);
15412 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15413 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15416 // Decide which area this value should be read from.
15417 // TODO: Implement the AMD64 ABI in its entirety. This simple
15418 // selection mechanism works only for the basic types.
15419 if (ArgVT == MVT::f80) {
15420 llvm_unreachable("va_arg for f80 not yet implemented");
15421 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15422 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15423 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15424 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15426 llvm_unreachable("Unhandled argument type in LowerVAARG");
15429 if (ArgMode == 2) {
15430 // Sanity Check: Make sure using fp_offset makes sense.
15431 assert(!Subtarget->useSoftFloat() &&
15432 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15433 Subtarget->hasSSE1());
15436 // Insert VAARG_64 node into the DAG
15437 // VAARG_64 returns two values: Variable Argument Address, Chain
15438 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15439 DAG.getConstant(ArgMode, dl, MVT::i8),
15440 DAG.getConstant(Align, dl, MVT::i32)};
15441 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15442 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15443 VTs, InstOps, MVT::i64,
15444 MachinePointerInfo(SV),
15446 /*Volatile=*/false,
15448 /*WriteMem=*/true);
15449 Chain = VAARG.getValue(1);
15451 // Load the next argument and return it
15452 return DAG.getLoad(ArgVT, dl,
15455 MachinePointerInfo(),
15456 false, false, false, 0);
15459 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15460 SelectionDAG &DAG) {
15461 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15462 // where a va_list is still an i8*.
15463 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15464 if (Subtarget->isCallingConvWin64(
15465 DAG.getMachineFunction().getFunction()->getCallingConv()))
15466 // Probably a Win64 va_copy.
15467 return DAG.expandVACopy(Op.getNode());
15469 SDValue Chain = Op.getOperand(0);
15470 SDValue DstPtr = Op.getOperand(1);
15471 SDValue SrcPtr = Op.getOperand(2);
15472 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15473 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15476 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15477 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15479 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15482 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15483 // amount is a constant. Takes immediate version of shift as input.
15484 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15485 SDValue SrcOp, uint64_t ShiftAmt,
15486 SelectionDAG &DAG) {
15487 MVT ElementType = VT.getVectorElementType();
15489 // Fold this packed shift into its first operand if ShiftAmt is 0.
15493 // Check for ShiftAmt >= element width
15494 if (ShiftAmt >= ElementType.getSizeInBits()) {
15495 if (Opc == X86ISD::VSRAI)
15496 ShiftAmt = ElementType.getSizeInBits() - 1;
15498 return DAG.getConstant(0, dl, VT);
15501 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15502 && "Unknown target vector shift-by-constant node");
15504 // Fold this packed vector shift into a build vector if SrcOp is a
15505 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15506 if (VT == SrcOp.getSimpleValueType() &&
15507 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15508 SmallVector<SDValue, 8> Elts;
15509 unsigned NumElts = SrcOp->getNumOperands();
15510 ConstantSDNode *ND;
15513 default: llvm_unreachable(nullptr);
15514 case X86ISD::VSHLI:
15515 for (unsigned i=0; i!=NumElts; ++i) {
15516 SDValue CurrentOp = SrcOp->getOperand(i);
15517 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15518 Elts.push_back(CurrentOp);
15521 ND = cast<ConstantSDNode>(CurrentOp);
15522 const APInt &C = ND->getAPIntValue();
15523 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15526 case X86ISD::VSRLI:
15527 for (unsigned i=0; i!=NumElts; ++i) {
15528 SDValue CurrentOp = SrcOp->getOperand(i);
15529 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15530 Elts.push_back(CurrentOp);
15533 ND = cast<ConstantSDNode>(CurrentOp);
15534 const APInt &C = ND->getAPIntValue();
15535 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15538 case X86ISD::VSRAI:
15539 for (unsigned i=0; i!=NumElts; ++i) {
15540 SDValue CurrentOp = SrcOp->getOperand(i);
15541 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15542 Elts.push_back(CurrentOp);
15545 ND = cast<ConstantSDNode>(CurrentOp);
15546 const APInt &C = ND->getAPIntValue();
15547 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15552 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15555 return DAG.getNode(Opc, dl, VT, SrcOp,
15556 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15559 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15560 // may or may not be a constant. Takes immediate version of shift as input.
15561 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15562 SDValue SrcOp, SDValue ShAmt,
15563 SelectionDAG &DAG) {
15564 MVT SVT = ShAmt.getSimpleValueType();
15565 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15567 // Catch shift-by-constant.
15568 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15569 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15570 CShAmt->getZExtValue(), DAG);
15572 // Change opcode to non-immediate version
15574 default: llvm_unreachable("Unknown target vector shift node");
15575 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15576 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15577 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15580 const X86Subtarget &Subtarget =
15581 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15582 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15583 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15584 // Let the shuffle legalizer expand this shift amount node.
15585 SDValue Op0 = ShAmt.getOperand(0);
15586 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15587 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15589 // Need to build a vector containing shift amount.
15590 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15591 SmallVector<SDValue, 4> ShOps;
15592 ShOps.push_back(ShAmt);
15593 if (SVT == MVT::i32) {
15594 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15595 ShOps.push_back(DAG.getUNDEF(SVT));
15597 ShOps.push_back(DAG.getUNDEF(SVT));
15599 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15600 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15603 // The return type has to be a 128-bit type with the same element
15604 // type as the input type.
15605 MVT EltVT = VT.getVectorElementType();
15606 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15608 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15609 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15612 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15613 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15614 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15615 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15616 SDValue PreservedSrc,
15617 const X86Subtarget *Subtarget,
15618 SelectionDAG &DAG) {
15619 EVT VT = Op.getValueType();
15620 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15621 MVT::i1, VT.getVectorNumElements());
15622 SDValue VMask = SDValue();
15623 unsigned OpcodeSelect = ISD::VSELECT;
15626 assert(MaskVT.isSimple() && "invalid mask type");
15628 if (isAllOnes(Mask))
15631 if (MaskVT.bitsGT(Mask.getValueType())) {
15632 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15633 MaskVT.getSizeInBits());
15634 VMask = DAG.getBitcast(MaskVT,
15635 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15637 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15638 Mask.getValueType().getSizeInBits());
15639 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15640 // are extracted by EXTRACT_SUBVECTOR.
15641 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15642 DAG.getBitcast(BitcastVT, Mask),
15643 DAG.getIntPtrConstant(0, dl));
15646 switch (Op.getOpcode()) {
15648 case X86ISD::PCMPEQM:
15649 case X86ISD::PCMPGTM:
15651 case X86ISD::CMPMU:
15652 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15653 case X86ISD::VTRUNC:
15654 case X86ISD::VTRUNCS:
15655 case X86ISD::VTRUNCUS:
15656 // We can't use ISD::VSELECT here because it is not always "Legal"
15657 // for the destination type. For example vpmovqb require only AVX512
15658 // and vselect that can operate on byte element type require BWI
15659 OpcodeSelect = X86ISD::SELECT;
15662 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15663 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15664 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15667 /// \brief Creates an SDNode for a predicated scalar operation.
15668 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15669 /// The mask is coming as MVT::i8 and it should be truncated
15670 /// to MVT::i1 while lowering masking intrinsics.
15671 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15672 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15673 /// for a scalar instruction.
15674 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15675 SDValue PreservedSrc,
15676 const X86Subtarget *Subtarget,
15677 SelectionDAG &DAG) {
15678 if (isAllOnes(Mask))
15681 EVT VT = Op.getValueType();
15683 // The mask should be of type MVT::i1
15684 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15686 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15687 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15688 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15691 static int getSEHRegistrationNodeSize(const Function *Fn) {
15692 if (!Fn->hasPersonalityFn())
15693 report_fatal_error(
15694 "querying registration node size for function without personality");
15695 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15696 // WinEHStatePass for the full struct definition.
15697 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15698 case EHPersonality::MSVC_X86SEH: return 24;
15699 case EHPersonality::MSVC_CXX: return 16;
15702 report_fatal_error("can only recover FP for MSVC EH personality functions");
15705 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15706 /// function or when returning to a parent frame after catching an exception, we
15707 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15708 /// Here's the math:
15709 /// RegNodeBase = EntryEBP - RegNodeSize
15710 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15711 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15712 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15713 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15714 SDValue EntryEBP) {
15715 MachineFunction &MF = DAG.getMachineFunction();
15718 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15719 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15721 // It's possible that the parent function no longer has a personality function
15722 // if the exceptional code was optimized away, in which case we just return
15723 // the incoming EBP.
15724 if (!Fn->hasPersonalityFn())
15727 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15729 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15731 MCSymbol *OffsetSym =
15732 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15733 GlobalValue::getRealLinkageName(Fn->getName()));
15734 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15735 SDValue RegNodeFrameOffset =
15736 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15738 // RegNodeBase = EntryEBP - RegNodeSize
15739 // ParentFP = RegNodeBase - RegNodeFrameOffset
15740 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15741 DAG.getConstant(RegNodeSize, dl, PtrVT));
15742 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15745 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15746 SelectionDAG &DAG) {
15748 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15749 EVT VT = Op.getValueType();
15750 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15752 switch(IntrData->Type) {
15753 case INTR_TYPE_1OP:
15754 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15755 case INTR_TYPE_2OP:
15756 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15758 case INTR_TYPE_2OP_IMM8:
15759 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15760 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15761 case INTR_TYPE_3OP:
15762 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15763 Op.getOperand(2), Op.getOperand(3));
15764 case INTR_TYPE_4OP:
15765 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15766 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15767 case INTR_TYPE_1OP_MASK_RM: {
15768 SDValue Src = Op.getOperand(1);
15769 SDValue PassThru = Op.getOperand(2);
15770 SDValue Mask = Op.getOperand(3);
15771 SDValue RoundingMode;
15772 // We allways add rounding mode to the Node.
15773 // If the rounding mode is not specified, we add the
15774 // "current direction" mode.
15775 if (Op.getNumOperands() == 4)
15777 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15779 RoundingMode = Op.getOperand(4);
15780 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15781 if (IntrWithRoundingModeOpcode != 0)
15782 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15783 X86::STATIC_ROUNDING::CUR_DIRECTION)
15784 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15785 dl, Op.getValueType(), Src, RoundingMode),
15786 Mask, PassThru, Subtarget, DAG);
15787 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15789 Mask, PassThru, Subtarget, DAG);
15791 case INTR_TYPE_1OP_MASK: {
15792 SDValue Src = Op.getOperand(1);
15793 SDValue PassThru = Op.getOperand(2);
15794 SDValue Mask = Op.getOperand(3);
15795 // We add rounding mode to the Node when
15796 // - RM Opcode is specified and
15797 // - RM is not "current direction".
15798 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15799 if (IntrWithRoundingModeOpcode != 0) {
15800 SDValue Rnd = Op.getOperand(4);
15801 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15802 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15803 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15804 dl, Op.getValueType(),
15806 Mask, PassThru, Subtarget, DAG);
15809 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15810 Mask, PassThru, Subtarget, DAG);
15812 case INTR_TYPE_SCALAR_MASK_RM: {
15813 SDValue Src1 = Op.getOperand(1);
15814 SDValue Src2 = Op.getOperand(2);
15815 SDValue Src0 = Op.getOperand(3);
15816 SDValue Mask = Op.getOperand(4);
15817 // There are 2 kinds of intrinsics in this group:
15818 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
15819 // (2) With rounding mode and sae - 7 operands.
15820 if (Op.getNumOperands() == 6) {
15821 SDValue Sae = Op.getOperand(5);
15822 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15823 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15825 Mask, Src0, Subtarget, DAG);
15827 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15828 SDValue RoundingMode = Op.getOperand(5);
15829 SDValue Sae = Op.getOperand(6);
15830 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15831 RoundingMode, Sae),
15832 Mask, Src0, Subtarget, DAG);
15834 case INTR_TYPE_2OP_MASK: {
15835 SDValue Src1 = Op.getOperand(1);
15836 SDValue Src2 = Op.getOperand(2);
15837 SDValue PassThru = Op.getOperand(3);
15838 SDValue Mask = Op.getOperand(4);
15839 // We specify 2 possible opcodes for intrinsics with rounding modes.
15840 // First, we check if the intrinsic may have non-default rounding mode,
15841 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15842 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15843 if (IntrWithRoundingModeOpcode != 0) {
15844 SDValue Rnd = Op.getOperand(5);
15845 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15846 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15847 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15848 dl, Op.getValueType(),
15850 Mask, PassThru, Subtarget, DAG);
15853 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15855 Mask, PassThru, Subtarget, DAG);
15857 case INTR_TYPE_2OP_MASK_RM: {
15858 SDValue Src1 = Op.getOperand(1);
15859 SDValue Src2 = Op.getOperand(2);
15860 SDValue PassThru = Op.getOperand(3);
15861 SDValue Mask = Op.getOperand(4);
15862 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15863 // First, we check if the intrinsic have rounding mode (6 operands),
15864 // if not, we set rounding mode to "current".
15866 if (Op.getNumOperands() == 6)
15867 Rnd = Op.getOperand(5);
15869 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15870 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15872 Mask, PassThru, Subtarget, DAG);
15874 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
15875 SDValue Src1 = Op.getOperand(1);
15876 SDValue Src2 = Op.getOperand(2);
15877 SDValue Src3 = Op.getOperand(3);
15878 SDValue PassThru = Op.getOperand(4);
15879 SDValue Mask = Op.getOperand(5);
15880 SDValue Sae = Op.getOperand(6);
15882 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
15884 Mask, PassThru, Subtarget, DAG);
15886 case INTR_TYPE_3OP_MASK_RM: {
15887 SDValue Src1 = Op.getOperand(1);
15888 SDValue Src2 = Op.getOperand(2);
15889 SDValue Imm = Op.getOperand(3);
15890 SDValue PassThru = Op.getOperand(4);
15891 SDValue Mask = Op.getOperand(5);
15892 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15893 // First, we check if the intrinsic have rounding mode (7 operands),
15894 // if not, we set rounding mode to "current".
15896 if (Op.getNumOperands() == 7)
15897 Rnd = Op.getOperand(6);
15899 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15900 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15901 Src1, Src2, Imm, Rnd),
15902 Mask, PassThru, Subtarget, DAG);
15904 case INTR_TYPE_3OP_IMM8_MASK:
15905 case INTR_TYPE_3OP_MASK: {
15906 SDValue Src1 = Op.getOperand(1);
15907 SDValue Src2 = Op.getOperand(2);
15908 SDValue Src3 = Op.getOperand(3);
15909 SDValue PassThru = Op.getOperand(4);
15910 SDValue Mask = Op.getOperand(5);
15912 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
15913 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
15914 // We specify 2 possible opcodes for intrinsics with rounding modes.
15915 // First, we check if the intrinsic may have non-default rounding mode,
15916 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15917 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15918 if (IntrWithRoundingModeOpcode != 0) {
15919 SDValue Rnd = Op.getOperand(6);
15920 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15921 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15922 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15923 dl, Op.getValueType(),
15924 Src1, Src2, Src3, Rnd),
15925 Mask, PassThru, Subtarget, DAG);
15928 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15930 Mask, PassThru, Subtarget, DAG);
15932 case VPERM_3OP_MASKZ:
15933 case VPERM_3OP_MASK:
15936 case FMA_OP_MASK: {
15937 SDValue Src1 = Op.getOperand(1);
15938 SDValue Src2 = Op.getOperand(2);
15939 SDValue Src3 = Op.getOperand(3);
15940 SDValue Mask = Op.getOperand(4);
15941 EVT VT = Op.getValueType();
15942 SDValue PassThru = SDValue();
15944 // set PassThru element
15945 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15946 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15947 else if (IntrData->Type == FMA_OP_MASK3)
15952 // We specify 2 possible opcodes for intrinsics with rounding modes.
15953 // First, we check if the intrinsic may have non-default rounding mode,
15954 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15955 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15956 if (IntrWithRoundingModeOpcode != 0) {
15957 SDValue Rnd = Op.getOperand(5);
15958 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15959 X86::STATIC_ROUNDING::CUR_DIRECTION)
15960 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15961 dl, Op.getValueType(),
15962 Src1, Src2, Src3, Rnd),
15963 Mask, PassThru, Subtarget, DAG);
15965 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15966 dl, Op.getValueType(),
15968 Mask, PassThru, Subtarget, DAG);
15971 case CMP_MASK_CC: {
15972 // Comparison intrinsics with masks.
15973 // Example of transformation:
15974 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15975 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15977 // (v8i1 (insert_subvector undef,
15978 // (v2i1 (and (PCMPEQM %a, %b),
15979 // (extract_subvector
15980 // (v8i1 (bitcast %mask)), 0))), 0))))
15981 EVT VT = Op.getOperand(1).getValueType();
15982 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15983 VT.getVectorNumElements());
15984 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15985 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15986 Mask.getValueType().getSizeInBits());
15988 if (IntrData->Type == CMP_MASK_CC) {
15989 SDValue CC = Op.getOperand(3);
15990 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15991 // We specify 2 possible opcodes for intrinsics with rounding modes.
15992 // First, we check if the intrinsic may have non-default rounding mode,
15993 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15994 if (IntrData->Opc1 != 0) {
15995 SDValue Rnd = Op.getOperand(5);
15996 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15997 X86::STATIC_ROUNDING::CUR_DIRECTION)
15998 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15999 Op.getOperand(2), CC, Rnd);
16001 //default rounding mode
16003 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16004 Op.getOperand(2), CC);
16007 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16008 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16011 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16012 DAG.getTargetConstant(0, dl,
16015 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16016 DAG.getUNDEF(BitcastVT), CmpMask,
16017 DAG.getIntPtrConstant(0, dl));
16018 return DAG.getBitcast(Op.getValueType(), Res);
16020 case COMI: { // Comparison intrinsics
16021 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16022 SDValue LHS = Op.getOperand(1);
16023 SDValue RHS = Op.getOperand(2);
16024 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16025 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16026 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16027 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16028 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16029 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16032 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16033 Op.getOperand(1), Op.getOperand(2), DAG);
16035 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16036 Op.getSimpleValueType(),
16038 Op.getOperand(2), DAG),
16039 Op.getOperand(4), Op.getOperand(3), Subtarget,
16041 case COMPRESS_EXPAND_IN_REG: {
16042 SDValue Mask = Op.getOperand(3);
16043 SDValue DataToCompress = Op.getOperand(1);
16044 SDValue PassThru = Op.getOperand(2);
16045 if (isAllOnes(Mask)) // return data as is
16046 return Op.getOperand(1);
16048 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16050 Mask, PassThru, Subtarget, DAG);
16053 SDValue Mask = Op.getOperand(3);
16054 EVT VT = Op.getValueType();
16055 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16056 VT.getVectorNumElements());
16057 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16058 Mask.getValueType().getSizeInBits());
16060 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16061 DAG.getBitcast(BitcastVT, Mask),
16062 DAG.getIntPtrConstant(0, dl));
16063 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16072 default: return SDValue(); // Don't custom lower most intrinsics.
16074 case Intrinsic::x86_avx2_permd:
16075 case Intrinsic::x86_avx2_permps:
16076 // Operands intentionally swapped. Mask is last operand to intrinsic,
16077 // but second operand for node/instruction.
16078 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16079 Op.getOperand(2), Op.getOperand(1));
16081 // ptest and testp intrinsics. The intrinsic these come from are designed to
16082 // return an integer value, not just an instruction so lower it to the ptest
16083 // or testp pattern and a setcc for the result.
16084 case Intrinsic::x86_sse41_ptestz:
16085 case Intrinsic::x86_sse41_ptestc:
16086 case Intrinsic::x86_sse41_ptestnzc:
16087 case Intrinsic::x86_avx_ptestz_256:
16088 case Intrinsic::x86_avx_ptestc_256:
16089 case Intrinsic::x86_avx_ptestnzc_256:
16090 case Intrinsic::x86_avx_vtestz_ps:
16091 case Intrinsic::x86_avx_vtestc_ps:
16092 case Intrinsic::x86_avx_vtestnzc_ps:
16093 case Intrinsic::x86_avx_vtestz_pd:
16094 case Intrinsic::x86_avx_vtestc_pd:
16095 case Intrinsic::x86_avx_vtestnzc_pd:
16096 case Intrinsic::x86_avx_vtestz_ps_256:
16097 case Intrinsic::x86_avx_vtestc_ps_256:
16098 case Intrinsic::x86_avx_vtestnzc_ps_256:
16099 case Intrinsic::x86_avx_vtestz_pd_256:
16100 case Intrinsic::x86_avx_vtestc_pd_256:
16101 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16102 bool IsTestPacked = false;
16105 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16106 case Intrinsic::x86_avx_vtestz_ps:
16107 case Intrinsic::x86_avx_vtestz_pd:
16108 case Intrinsic::x86_avx_vtestz_ps_256:
16109 case Intrinsic::x86_avx_vtestz_pd_256:
16110 IsTestPacked = true; // Fallthrough
16111 case Intrinsic::x86_sse41_ptestz:
16112 case Intrinsic::x86_avx_ptestz_256:
16114 X86CC = X86::COND_E;
16116 case Intrinsic::x86_avx_vtestc_ps:
16117 case Intrinsic::x86_avx_vtestc_pd:
16118 case Intrinsic::x86_avx_vtestc_ps_256:
16119 case Intrinsic::x86_avx_vtestc_pd_256:
16120 IsTestPacked = true; // Fallthrough
16121 case Intrinsic::x86_sse41_ptestc:
16122 case Intrinsic::x86_avx_ptestc_256:
16124 X86CC = X86::COND_B;
16126 case Intrinsic::x86_avx_vtestnzc_ps:
16127 case Intrinsic::x86_avx_vtestnzc_pd:
16128 case Intrinsic::x86_avx_vtestnzc_ps_256:
16129 case Intrinsic::x86_avx_vtestnzc_pd_256:
16130 IsTestPacked = true; // Fallthrough
16131 case Intrinsic::x86_sse41_ptestnzc:
16132 case Intrinsic::x86_avx_ptestnzc_256:
16134 X86CC = X86::COND_A;
16138 SDValue LHS = Op.getOperand(1);
16139 SDValue RHS = Op.getOperand(2);
16140 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16141 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16142 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16143 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16144 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16146 case Intrinsic::x86_avx512_kortestz_w:
16147 case Intrinsic::x86_avx512_kortestc_w: {
16148 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16149 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16150 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16151 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16152 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16153 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16154 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16157 case Intrinsic::x86_sse42_pcmpistria128:
16158 case Intrinsic::x86_sse42_pcmpestria128:
16159 case Intrinsic::x86_sse42_pcmpistric128:
16160 case Intrinsic::x86_sse42_pcmpestric128:
16161 case Intrinsic::x86_sse42_pcmpistrio128:
16162 case Intrinsic::x86_sse42_pcmpestrio128:
16163 case Intrinsic::x86_sse42_pcmpistris128:
16164 case Intrinsic::x86_sse42_pcmpestris128:
16165 case Intrinsic::x86_sse42_pcmpistriz128:
16166 case Intrinsic::x86_sse42_pcmpestriz128: {
16170 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16171 case Intrinsic::x86_sse42_pcmpistria128:
16172 Opcode = X86ISD::PCMPISTRI;
16173 X86CC = X86::COND_A;
16175 case Intrinsic::x86_sse42_pcmpestria128:
16176 Opcode = X86ISD::PCMPESTRI;
16177 X86CC = X86::COND_A;
16179 case Intrinsic::x86_sse42_pcmpistric128:
16180 Opcode = X86ISD::PCMPISTRI;
16181 X86CC = X86::COND_B;
16183 case Intrinsic::x86_sse42_pcmpestric128:
16184 Opcode = X86ISD::PCMPESTRI;
16185 X86CC = X86::COND_B;
16187 case Intrinsic::x86_sse42_pcmpistrio128:
16188 Opcode = X86ISD::PCMPISTRI;
16189 X86CC = X86::COND_O;
16191 case Intrinsic::x86_sse42_pcmpestrio128:
16192 Opcode = X86ISD::PCMPESTRI;
16193 X86CC = X86::COND_O;
16195 case Intrinsic::x86_sse42_pcmpistris128:
16196 Opcode = X86ISD::PCMPISTRI;
16197 X86CC = X86::COND_S;
16199 case Intrinsic::x86_sse42_pcmpestris128:
16200 Opcode = X86ISD::PCMPESTRI;
16201 X86CC = X86::COND_S;
16203 case Intrinsic::x86_sse42_pcmpistriz128:
16204 Opcode = X86ISD::PCMPISTRI;
16205 X86CC = X86::COND_E;
16207 case Intrinsic::x86_sse42_pcmpestriz128:
16208 Opcode = X86ISD::PCMPESTRI;
16209 X86CC = X86::COND_E;
16212 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16213 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16214 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16215 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16216 DAG.getConstant(X86CC, dl, MVT::i8),
16217 SDValue(PCMP.getNode(), 1));
16218 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16221 case Intrinsic::x86_sse42_pcmpistri128:
16222 case Intrinsic::x86_sse42_pcmpestri128: {
16224 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16225 Opcode = X86ISD::PCMPISTRI;
16227 Opcode = X86ISD::PCMPESTRI;
16229 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16230 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16231 return DAG.getNode(Opcode, dl, VTs, NewOps);
16234 case Intrinsic::x86_seh_lsda: {
16235 // Compute the symbol for the LSDA. We know it'll get emitted later.
16236 MachineFunction &MF = DAG.getMachineFunction();
16237 SDValue Op1 = Op.getOperand(1);
16238 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16239 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16240 GlobalValue::getRealLinkageName(Fn->getName()));
16242 // Generate a simple absolute symbol reference. This intrinsic is only
16243 // supported on 32-bit Windows, which isn't PIC.
16244 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16245 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16248 case Intrinsic::x86_seh_recoverfp: {
16249 SDValue FnOp = Op.getOperand(1);
16250 SDValue IncomingFPOp = Op.getOperand(2);
16251 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16252 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16254 report_fatal_error(
16255 "llvm.x86.seh.recoverfp must take a function as the first argument");
16256 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16259 case Intrinsic::localaddress: {
16260 // Returns one of the stack, base, or frame pointer registers, depending on
16261 // which is used to reference local variables.
16262 MachineFunction &MF = DAG.getMachineFunction();
16263 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16265 if (RegInfo->hasBasePointer(MF))
16266 Reg = RegInfo->getBaseRegister();
16267 else // This function handles the SP or FP case.
16268 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16269 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16274 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16275 SDValue Src, SDValue Mask, SDValue Base,
16276 SDValue Index, SDValue ScaleOp, SDValue Chain,
16277 const X86Subtarget * Subtarget) {
16279 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16281 llvm_unreachable("Invalid scale type");
16282 unsigned ScaleVal = C->getZExtValue();
16283 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16284 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16286 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16287 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16288 Index.getSimpleValueType().getVectorNumElements());
16290 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16292 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16294 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16295 Mask.getValueType().getSizeInBits());
16297 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16298 // are extracted by EXTRACT_SUBVECTOR.
16299 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16300 DAG.getBitcast(BitcastVT, Mask),
16301 DAG.getIntPtrConstant(0, dl));
16303 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16304 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16305 SDValue Segment = DAG.getRegister(0, MVT::i32);
16306 if (Src.getOpcode() == ISD::UNDEF)
16307 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16308 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16309 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16310 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16311 return DAG.getMergeValues(RetOps, dl);
16314 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16315 SDValue Src, SDValue Mask, SDValue Base,
16316 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16318 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16320 llvm_unreachable("Invalid scale type");
16321 unsigned ScaleVal = C->getZExtValue();
16322 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16323 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16325 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16326 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16327 SDValue Segment = DAG.getRegister(0, MVT::i32);
16328 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16329 Index.getSimpleValueType().getVectorNumElements());
16331 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16333 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16335 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16336 Mask.getValueType().getSizeInBits());
16338 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16339 // are extracted by EXTRACT_SUBVECTOR.
16340 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16341 DAG.getBitcast(BitcastVT, Mask),
16342 DAG.getIntPtrConstant(0, dl));
16344 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16345 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16346 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16347 return SDValue(Res, 1);
16350 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16351 SDValue Mask, SDValue Base, SDValue Index,
16352 SDValue ScaleOp, SDValue Chain) {
16354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16355 assert(C && "Invalid scale type");
16356 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16357 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16358 SDValue Segment = DAG.getRegister(0, MVT::i32);
16360 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16362 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16364 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16366 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16367 //SDVTList VTs = DAG.getVTList(MVT::Other);
16368 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16369 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16370 return SDValue(Res, 0);
16373 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16374 // read performance monitor counters (x86_rdpmc).
16375 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16376 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16377 SmallVectorImpl<SDValue> &Results) {
16378 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16379 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16382 // The ECX register is used to select the index of the performance counter
16384 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16386 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16388 // Reads the content of a 64-bit performance counter and returns it in the
16389 // registers EDX:EAX.
16390 if (Subtarget->is64Bit()) {
16391 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16392 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16395 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16396 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16399 Chain = HI.getValue(1);
16401 if (Subtarget->is64Bit()) {
16402 // The EAX register is loaded with the low-order 32 bits. The EDX register
16403 // is loaded with the supported high-order bits of the counter.
16404 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16405 DAG.getConstant(32, DL, MVT::i8));
16406 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16407 Results.push_back(Chain);
16411 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16412 SDValue Ops[] = { LO, HI };
16413 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16414 Results.push_back(Pair);
16415 Results.push_back(Chain);
16418 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16419 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16420 // also used to custom lower READCYCLECOUNTER nodes.
16421 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16422 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16423 SmallVectorImpl<SDValue> &Results) {
16424 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16425 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16428 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16429 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16430 // and the EAX register is loaded with the low-order 32 bits.
16431 if (Subtarget->is64Bit()) {
16432 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16433 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16436 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16437 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16440 SDValue Chain = HI.getValue(1);
16442 if (Opcode == X86ISD::RDTSCP_DAG) {
16443 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16445 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16446 // the ECX register. Add 'ecx' explicitly to the chain.
16447 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16449 // Explicitly store the content of ECX at the location passed in input
16450 // to the 'rdtscp' intrinsic.
16451 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16452 MachinePointerInfo(), false, false, 0);
16455 if (Subtarget->is64Bit()) {
16456 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16457 // the EAX register is loaded with the low-order 32 bits.
16458 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16459 DAG.getConstant(32, DL, MVT::i8));
16460 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16461 Results.push_back(Chain);
16465 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16466 SDValue Ops[] = { LO, HI };
16467 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16468 Results.push_back(Pair);
16469 Results.push_back(Chain);
16472 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16473 SelectionDAG &DAG) {
16474 SmallVector<SDValue, 2> Results;
16476 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16478 return DAG.getMergeValues(Results, DL);
16481 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16482 SelectionDAG &DAG) {
16483 MachineFunction &MF = DAG.getMachineFunction();
16484 const Function *Fn = MF.getFunction();
16486 SDValue Chain = Op.getOperand(0);
16488 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16489 "using llvm.x86.seh.restoreframe requires a frame pointer");
16491 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16492 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16494 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16495 unsigned FrameReg =
16496 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16497 unsigned SPReg = RegInfo->getStackRegister();
16498 unsigned SlotSize = RegInfo->getSlotSize();
16500 // Get incoming EBP.
16501 SDValue IncomingEBP =
16502 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16504 // SP is saved in the first field of every registration node, so load
16505 // [EBP-RegNodeSize] into SP.
16506 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16507 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16508 DAG.getConstant(-RegNodeSize, dl, VT));
16510 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16511 false, VT.getScalarSizeInBits() / 8);
16512 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16514 if (!RegInfo->needsStackRealignment(MF)) {
16515 // Adjust EBP to point back to the original frame position.
16516 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16517 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16519 assert(RegInfo->hasBasePointer(MF) &&
16520 "functions with Win32 EH must use frame or base pointer register");
16522 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16523 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16524 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16526 // Reload the spilled EBP value, now that the stack and base pointers are
16528 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16529 X86FI->setHasSEHFramePtrSave(true);
16530 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16531 X86FI->setSEHFramePtrSaveIndex(FI);
16532 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16533 MachinePointerInfo(), false, false, false,
16534 VT.getScalarSizeInBits() / 8);
16535 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16541 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16542 /// return truncate Store/MaskedStore Node
16543 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16547 SDValue Mask = Op.getOperand(4);
16548 SDValue DataToTruncate = Op.getOperand(3);
16549 SDValue Addr = Op.getOperand(2);
16550 SDValue Chain = Op.getOperand(0);
16552 EVT VT = DataToTruncate.getValueType();
16553 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16554 ElementType, VT.getVectorNumElements());
16556 if (isAllOnes(Mask)) // return just a truncate store
16557 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16558 MachinePointerInfo(), SVT, false, false,
16559 SVT.getScalarSizeInBits()/8);
16561 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16562 MVT::i1, VT.getVectorNumElements());
16563 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16564 Mask.getValueType().getSizeInBits());
16565 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16566 // are extracted by EXTRACT_SUBVECTOR.
16567 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16568 DAG.getBitcast(BitcastVT, Mask),
16569 DAG.getIntPtrConstant(0, dl));
16571 MachineMemOperand *MMO = DAG.getMachineFunction().
16572 getMachineMemOperand(MachinePointerInfo(),
16573 MachineMemOperand::MOStore, SVT.getStoreSize(),
16574 SVT.getScalarSizeInBits()/8);
16576 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16577 VMask, SVT, MMO, true);
16580 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16581 SelectionDAG &DAG) {
16582 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16584 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16586 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16587 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16592 switch(IntrData->Type) {
16594 llvm_unreachable("Unknown Intrinsic Type");
16598 // Emit the node with the right value type.
16599 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16600 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16602 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16603 // Otherwise return the value from Rand, which is always 0, casted to i32.
16604 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16605 DAG.getConstant(1, dl, Op->getValueType(1)),
16606 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16607 SDValue(Result.getNode(), 1) };
16608 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16609 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16612 // Return { result, isValid, chain }.
16613 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16614 SDValue(Result.getNode(), 2));
16617 //gather(v1, mask, index, base, scale);
16618 SDValue Chain = Op.getOperand(0);
16619 SDValue Src = Op.getOperand(2);
16620 SDValue Base = Op.getOperand(3);
16621 SDValue Index = Op.getOperand(4);
16622 SDValue Mask = Op.getOperand(5);
16623 SDValue Scale = Op.getOperand(6);
16624 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16628 //scatter(base, mask, index, v1, scale);
16629 SDValue Chain = Op.getOperand(0);
16630 SDValue Base = Op.getOperand(2);
16631 SDValue Mask = Op.getOperand(3);
16632 SDValue Index = Op.getOperand(4);
16633 SDValue Src = Op.getOperand(5);
16634 SDValue Scale = Op.getOperand(6);
16635 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16639 SDValue Hint = Op.getOperand(6);
16640 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16641 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16642 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16643 SDValue Chain = Op.getOperand(0);
16644 SDValue Mask = Op.getOperand(2);
16645 SDValue Index = Op.getOperand(3);
16646 SDValue Base = Op.getOperand(4);
16647 SDValue Scale = Op.getOperand(5);
16648 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16650 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16652 SmallVector<SDValue, 2> Results;
16653 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16655 return DAG.getMergeValues(Results, dl);
16657 // Read Performance Monitoring Counters.
16659 SmallVector<SDValue, 2> Results;
16660 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16661 return DAG.getMergeValues(Results, dl);
16663 // XTEST intrinsics.
16665 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16666 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16667 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16668 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16670 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16671 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16672 Ret, SDValue(InTrans.getNode(), 1));
16676 SmallVector<SDValue, 2> Results;
16677 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16678 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16679 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16680 DAG.getConstant(-1, dl, MVT::i8));
16681 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16682 Op.getOperand(4), GenCF.getValue(1));
16683 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16684 Op.getOperand(5), MachinePointerInfo(),
16686 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16687 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16689 Results.push_back(SetCC);
16690 Results.push_back(Store);
16691 return DAG.getMergeValues(Results, dl);
16693 case COMPRESS_TO_MEM: {
16695 SDValue Mask = Op.getOperand(4);
16696 SDValue DataToCompress = Op.getOperand(3);
16697 SDValue Addr = Op.getOperand(2);
16698 SDValue Chain = Op.getOperand(0);
16700 EVT VT = DataToCompress.getValueType();
16701 if (isAllOnes(Mask)) // return just a store
16702 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16703 MachinePointerInfo(), false, false,
16704 VT.getScalarSizeInBits()/8);
16706 SDValue Compressed =
16707 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16708 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16709 return DAG.getStore(Chain, dl, Compressed, Addr,
16710 MachinePointerInfo(), false, false,
16711 VT.getScalarSizeInBits()/8);
16713 case TRUNCATE_TO_MEM_VI8:
16714 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16715 case TRUNCATE_TO_MEM_VI16:
16716 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16717 case TRUNCATE_TO_MEM_VI32:
16718 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16719 case EXPAND_FROM_MEM: {
16721 SDValue Mask = Op.getOperand(4);
16722 SDValue PassThru = Op.getOperand(3);
16723 SDValue Addr = Op.getOperand(2);
16724 SDValue Chain = Op.getOperand(0);
16725 EVT VT = Op.getValueType();
16727 if (isAllOnes(Mask)) // return just a load
16728 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16729 false, VT.getScalarSizeInBits()/8);
16731 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16732 false, false, false,
16733 VT.getScalarSizeInBits()/8);
16735 SDValue Results[] = {
16736 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16737 Mask, PassThru, Subtarget, DAG), Chain};
16738 return DAG.getMergeValues(Results, dl);
16743 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16744 SelectionDAG &DAG) const {
16745 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16746 MFI->setReturnAddressIsTaken(true);
16748 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16751 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16753 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16756 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16757 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16758 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16759 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16760 DAG.getNode(ISD::ADD, dl, PtrVT,
16761 FrameAddr, Offset),
16762 MachinePointerInfo(), false, false, false, 0);
16765 // Just load the return address.
16766 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16767 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16768 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16771 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16772 MachineFunction &MF = DAG.getMachineFunction();
16773 MachineFrameInfo *MFI = MF.getFrameInfo();
16774 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16775 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16776 EVT VT = Op.getValueType();
16778 MFI->setFrameAddressIsTaken(true);
16780 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
16781 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
16782 // is not possible to crawl up the stack without looking at the unwind codes
16784 int FrameAddrIndex = FuncInfo->getFAIndex();
16785 if (!FrameAddrIndex) {
16786 // Set up a frame object for the return address.
16787 unsigned SlotSize = RegInfo->getSlotSize();
16788 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
16789 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
16790 FuncInfo->setFAIndex(FrameAddrIndex);
16792 return DAG.getFrameIndex(FrameAddrIndex, VT);
16795 unsigned FrameReg =
16796 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16797 SDLoc dl(Op); // FIXME probably not meaningful
16798 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16799 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16800 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16801 "Invalid Frame Register!");
16802 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16804 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16805 MachinePointerInfo(),
16806 false, false, false, 0);
16810 // FIXME? Maybe this could be a TableGen attribute on some registers and
16811 // this table could be generated automatically from RegInfo.
16812 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
16813 SelectionDAG &DAG) const {
16814 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16815 const MachineFunction &MF = DAG.getMachineFunction();
16817 unsigned Reg = StringSwitch<unsigned>(RegName)
16818 .Case("esp", X86::ESP)
16819 .Case("rsp", X86::RSP)
16820 .Case("ebp", X86::EBP)
16821 .Case("rbp", X86::RBP)
16824 if (Reg == X86::EBP || Reg == X86::RBP) {
16825 if (!TFI.hasFP(MF))
16826 report_fatal_error("register " + StringRef(RegName) +
16827 " is allocatable: function has no frame pointer");
16830 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16831 unsigned FrameReg =
16832 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16833 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
16834 "Invalid Frame Register!");
16842 report_fatal_error("Invalid register name global variable");
16845 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16846 SelectionDAG &DAG) const {
16847 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16848 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16851 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16852 SDValue Chain = Op.getOperand(0);
16853 SDValue Offset = Op.getOperand(1);
16854 SDValue Handler = Op.getOperand(2);
16857 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16858 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16859 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16860 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16861 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16862 "Invalid Frame Register!");
16863 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16864 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16866 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16867 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16869 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16870 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16872 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16874 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16875 DAG.getRegister(StoreAddrReg, PtrVT));
16878 SDValue X86TargetLowering::LowerCATCHRET(SDValue Op, SelectionDAG &DAG) const {
16879 SDValue Chain = Op.getOperand(0);
16880 SDValue Dest = Op.getOperand(1);
16883 MVT PtrVT = getPointerTy(DAG.getDataLayout());
16884 unsigned ReturnReg = (PtrVT == MVT::i64 ? X86::RAX : X86::EAX);
16886 // Load the address of the destination block.
16887 MachineBasicBlock *DestMBB = cast<BasicBlockSDNode>(Dest)->getBasicBlock();
16888 SDValue BlockPtr = DAG.getMCSymbol(DestMBB->getSymbol(), PtrVT);
16889 unsigned WrapperKind =
16890 Subtarget->isPICStyleRIPRel() ? X86ISD::WrapperRIP : X86ISD::Wrapper;
16891 SDValue WrappedPtr = DAG.getNode(WrapperKind, DL, PtrVT, BlockPtr);
16892 Chain = DAG.getCopyToReg(Chain, DL, ReturnReg, WrappedPtr);
16893 return DAG.getNode(X86ISD::CATCHRET, DL, MVT::Other, Chain,
16894 DAG.getRegister(ReturnReg, PtrVT));
16897 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16898 SelectionDAG &DAG) const {
16900 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16901 DAG.getVTList(MVT::i32, MVT::Other),
16902 Op.getOperand(0), Op.getOperand(1));
16905 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16906 SelectionDAG &DAG) const {
16908 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16909 Op.getOperand(0), Op.getOperand(1));
16912 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16913 return Op.getOperand(0);
16916 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16917 SelectionDAG &DAG) const {
16918 SDValue Root = Op.getOperand(0);
16919 SDValue Trmp = Op.getOperand(1); // trampoline
16920 SDValue FPtr = Op.getOperand(2); // nested function
16921 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16924 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16925 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16927 if (Subtarget->is64Bit()) {
16928 SDValue OutChains[6];
16930 // Large code-model.
16931 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16932 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16934 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16935 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16937 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16939 // Load the pointer to the nested function into R11.
16940 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16941 SDValue Addr = Trmp;
16942 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16943 Addr, MachinePointerInfo(TrmpAddr),
16946 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16947 DAG.getConstant(2, dl, MVT::i64));
16948 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16949 MachinePointerInfo(TrmpAddr, 2),
16952 // Load the 'nest' parameter value into R10.
16953 // R10 is specified in X86CallingConv.td
16954 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16955 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16956 DAG.getConstant(10, dl, MVT::i64));
16957 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16958 Addr, MachinePointerInfo(TrmpAddr, 10),
16961 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16962 DAG.getConstant(12, dl, MVT::i64));
16963 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16964 MachinePointerInfo(TrmpAddr, 12),
16967 // Jump to the nested function.
16968 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16969 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16970 DAG.getConstant(20, dl, MVT::i64));
16971 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16972 Addr, MachinePointerInfo(TrmpAddr, 20),
16975 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16976 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16977 DAG.getConstant(22, dl, MVT::i64));
16978 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16979 Addr, MachinePointerInfo(TrmpAddr, 22),
16982 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16984 const Function *Func =
16985 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16986 CallingConv::ID CC = Func->getCallingConv();
16991 llvm_unreachable("Unsupported calling convention");
16992 case CallingConv::C:
16993 case CallingConv::X86_StdCall: {
16994 // Pass 'nest' parameter in ECX.
16995 // Must be kept in sync with X86CallingConv.td
16996 NestReg = X86::ECX;
16998 // Check that ECX wasn't needed by an 'inreg' parameter.
16999 FunctionType *FTy = Func->getFunctionType();
17000 const AttributeSet &Attrs = Func->getAttributes();
17002 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17003 unsigned InRegCount = 0;
17006 for (FunctionType::param_iterator I = FTy->param_begin(),
17007 E = FTy->param_end(); I != E; ++I, ++Idx)
17008 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17009 auto &DL = DAG.getDataLayout();
17010 // FIXME: should only count parameters that are lowered to integers.
17011 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17014 if (InRegCount > 2) {
17015 report_fatal_error("Nest register in use - reduce number of inreg"
17021 case CallingConv::X86_FastCall:
17022 case CallingConv::X86_ThisCall:
17023 case CallingConv::Fast:
17024 // Pass 'nest' parameter in EAX.
17025 // Must be kept in sync with X86CallingConv.td
17026 NestReg = X86::EAX;
17030 SDValue OutChains[4];
17031 SDValue Addr, Disp;
17033 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17034 DAG.getConstant(10, dl, MVT::i32));
17035 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17037 // This is storing the opcode for MOV32ri.
17038 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17039 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17040 OutChains[0] = DAG.getStore(Root, dl,
17041 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17042 Trmp, MachinePointerInfo(TrmpAddr),
17045 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17046 DAG.getConstant(1, dl, MVT::i32));
17047 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17048 MachinePointerInfo(TrmpAddr, 1),
17051 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17052 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17053 DAG.getConstant(5, dl, MVT::i32));
17054 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17055 Addr, MachinePointerInfo(TrmpAddr, 5),
17058 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17059 DAG.getConstant(6, dl, MVT::i32));
17060 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17061 MachinePointerInfo(TrmpAddr, 6),
17064 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17068 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17069 SelectionDAG &DAG) const {
17071 The rounding mode is in bits 11:10 of FPSR, and has the following
17073 00 Round to nearest
17078 FLT_ROUNDS, on the other hand, expects the following:
17085 To perform the conversion, we do:
17086 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17089 MachineFunction &MF = DAG.getMachineFunction();
17090 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17091 unsigned StackAlignment = TFI.getStackAlignment();
17092 MVT VT = Op.getSimpleValueType();
17095 // Save FP Control Word to stack slot
17096 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17097 SDValue StackSlot =
17098 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17100 MachineMemOperand *MMO =
17101 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17102 MachineMemOperand::MOStore, 2, 2);
17104 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17105 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17106 DAG.getVTList(MVT::Other),
17107 Ops, MVT::i16, MMO);
17109 // Load FP Control Word from stack slot
17110 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17111 MachinePointerInfo(), false, false, false, 0);
17113 // Transform as necessary
17115 DAG.getNode(ISD::SRL, DL, MVT::i16,
17116 DAG.getNode(ISD::AND, DL, MVT::i16,
17117 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17118 DAG.getConstant(11, DL, MVT::i8));
17120 DAG.getNode(ISD::SRL, DL, MVT::i16,
17121 DAG.getNode(ISD::AND, DL, MVT::i16,
17122 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17123 DAG.getConstant(9, DL, MVT::i8));
17126 DAG.getNode(ISD::AND, DL, MVT::i16,
17127 DAG.getNode(ISD::ADD, DL, MVT::i16,
17128 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17129 DAG.getConstant(1, DL, MVT::i16)),
17130 DAG.getConstant(3, DL, MVT::i16));
17132 return DAG.getNode((VT.getSizeInBits() < 16 ?
17133 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17136 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17137 MVT VT = Op.getSimpleValueType();
17139 unsigned NumBits = VT.getSizeInBits();
17142 Op = Op.getOperand(0);
17143 if (VT == MVT::i8) {
17144 // Zero extend to i32 since there is not an i8 bsr.
17146 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17149 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17150 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17151 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17153 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17156 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17157 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17160 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17162 // Finally xor with NumBits-1.
17163 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17164 DAG.getConstant(NumBits - 1, dl, OpVT));
17167 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17171 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17172 MVT VT = Op.getSimpleValueType();
17174 unsigned NumBits = VT.getSizeInBits();
17177 Op = Op.getOperand(0);
17178 if (VT == MVT::i8) {
17179 // Zero extend to i32 since there is not an i8 bsr.
17181 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17184 // Issue a bsr (scan bits in reverse).
17185 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17186 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17188 // And xor with NumBits-1.
17189 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17190 DAG.getConstant(NumBits - 1, dl, OpVT));
17193 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17197 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17198 MVT VT = Op.getSimpleValueType();
17199 unsigned NumBits = VT.getSizeInBits();
17201 Op = Op.getOperand(0);
17203 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17204 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17205 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17207 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17210 DAG.getConstant(NumBits, dl, VT),
17211 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17214 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17217 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17218 // ones, and then concatenate the result back.
17219 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17220 MVT VT = Op.getSimpleValueType();
17222 assert(VT.is256BitVector() && VT.isInteger() &&
17223 "Unsupported value type for operation");
17225 unsigned NumElems = VT.getVectorNumElements();
17228 // Extract the LHS vectors
17229 SDValue LHS = Op.getOperand(0);
17230 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17231 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17233 // Extract the RHS vectors
17234 SDValue RHS = Op.getOperand(1);
17235 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17236 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17238 MVT EltVT = VT.getVectorElementType();
17239 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17241 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17242 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17243 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17246 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17247 if (Op.getValueType() == MVT::i1)
17248 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17249 Op.getOperand(0), Op.getOperand(1));
17250 assert(Op.getSimpleValueType().is256BitVector() &&
17251 Op.getSimpleValueType().isInteger() &&
17252 "Only handle AVX 256-bit vector integer operation");
17253 return Lower256IntArith(Op, DAG);
17256 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17257 if (Op.getValueType() == MVT::i1)
17258 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17259 Op.getOperand(0), Op.getOperand(1));
17260 assert(Op.getSimpleValueType().is256BitVector() &&
17261 Op.getSimpleValueType().isInteger() &&
17262 "Only handle AVX 256-bit vector integer operation");
17263 return Lower256IntArith(Op, DAG);
17266 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17267 assert(Op.getSimpleValueType().is256BitVector() &&
17268 Op.getSimpleValueType().isInteger() &&
17269 "Only handle AVX 256-bit vector integer operation");
17270 return Lower256IntArith(Op, DAG);
17273 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17274 SelectionDAG &DAG) {
17276 MVT VT = Op.getSimpleValueType();
17279 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17281 // Decompose 256-bit ops into smaller 128-bit ops.
17282 if (VT.is256BitVector() && !Subtarget->hasInt256())
17283 return Lower256IntArith(Op, DAG);
17285 SDValue A = Op.getOperand(0);
17286 SDValue B = Op.getOperand(1);
17288 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17289 // pairs, multiply and truncate.
17290 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17291 if (Subtarget->hasInt256()) {
17292 if (VT == MVT::v32i8) {
17293 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17294 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17295 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17296 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17297 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17298 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17299 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17300 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17301 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17302 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17305 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17306 return DAG.getNode(
17307 ISD::TRUNCATE, dl, VT,
17308 DAG.getNode(ISD::MUL, dl, ExVT,
17309 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17310 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17313 assert(VT == MVT::v16i8 &&
17314 "Pre-AVX2 support only supports v16i8 multiplication");
17315 MVT ExVT = MVT::v8i16;
17317 // Extract the lo parts and sign extend to i16
17319 if (Subtarget->hasSSE41()) {
17320 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17321 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17323 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17324 -1, 4, -1, 5, -1, 6, -1, 7};
17325 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17326 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17327 ALo = DAG.getBitcast(ExVT, ALo);
17328 BLo = DAG.getBitcast(ExVT, BLo);
17329 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17330 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17333 // Extract the hi parts and sign extend to i16
17335 if (Subtarget->hasSSE41()) {
17336 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17337 -1, -1, -1, -1, -1, -1, -1, -1};
17338 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17339 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17340 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17341 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17343 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17344 -1, 12, -1, 13, -1, 14, -1, 15};
17345 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17346 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17347 AHi = DAG.getBitcast(ExVT, AHi);
17348 BHi = DAG.getBitcast(ExVT, BHi);
17349 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17350 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17353 // Multiply, mask the lower 8bits of the lo/hi results and pack
17354 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17355 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17356 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17357 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17358 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17361 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17362 if (VT == MVT::v4i32) {
17363 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17364 "Should not custom lower when pmuldq is available!");
17366 // Extract the odd parts.
17367 static const int UnpackMask[] = { 1, -1, 3, -1 };
17368 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17369 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17371 // Multiply the even parts.
17372 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17373 // Now multiply odd parts.
17374 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17376 Evens = DAG.getBitcast(VT, Evens);
17377 Odds = DAG.getBitcast(VT, Odds);
17379 // Merge the two vectors back together with a shuffle. This expands into 2
17381 static const int ShufMask[] = { 0, 4, 2, 6 };
17382 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17385 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17386 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17388 // Ahi = psrlqi(a, 32);
17389 // Bhi = psrlqi(b, 32);
17391 // AloBlo = pmuludq(a, b);
17392 // AloBhi = pmuludq(a, Bhi);
17393 // AhiBlo = pmuludq(Ahi, b);
17395 // AloBhi = psllqi(AloBhi, 32);
17396 // AhiBlo = psllqi(AhiBlo, 32);
17397 // return AloBlo + AloBhi + AhiBlo;
17399 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17400 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17402 SDValue AhiBlo = Ahi;
17403 SDValue AloBhi = Bhi;
17404 // Bit cast to 32-bit vectors for MULUDQ
17405 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17406 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17407 A = DAG.getBitcast(MulVT, A);
17408 B = DAG.getBitcast(MulVT, B);
17409 Ahi = DAG.getBitcast(MulVT, Ahi);
17410 Bhi = DAG.getBitcast(MulVT, Bhi);
17412 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17413 // After shifting right const values the result may be all-zero.
17414 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17415 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17416 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17418 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17419 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17420 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17423 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17424 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17427 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17428 assert(Subtarget->isTargetWin64() && "Unexpected target");
17429 EVT VT = Op.getValueType();
17430 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17431 "Unexpected return type for lowering");
17435 switch (Op->getOpcode()) {
17436 default: llvm_unreachable("Unexpected request for libcall!");
17437 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17438 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17439 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17440 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17441 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17442 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17446 SDValue InChain = DAG.getEntryNode();
17448 TargetLowering::ArgListTy Args;
17449 TargetLowering::ArgListEntry Entry;
17450 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17451 EVT ArgVT = Op->getOperand(i).getValueType();
17452 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17453 "Unexpected argument type for lowering");
17454 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17455 Entry.Node = StackPtr;
17456 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17458 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17459 Entry.Ty = PointerType::get(ArgTy,0);
17460 Entry.isSExt = false;
17461 Entry.isZExt = false;
17462 Args.push_back(Entry);
17465 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17466 getPointerTy(DAG.getDataLayout()));
17468 TargetLowering::CallLoweringInfo CLI(DAG);
17469 CLI.setDebugLoc(dl).setChain(InChain)
17470 .setCallee(getLibcallCallingConv(LC),
17471 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17472 Callee, std::move(Args), 0)
17473 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17475 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17476 return DAG.getBitcast(VT, CallInfo.first);
17479 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17480 SelectionDAG &DAG) {
17481 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17482 EVT VT = Op0.getValueType();
17485 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17486 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17488 // PMULxD operations multiply each even value (starting at 0) of LHS with
17489 // the related value of RHS and produce a widen result.
17490 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17491 // => <2 x i64> <ae|cg>
17493 // In other word, to have all the results, we need to perform two PMULxD:
17494 // 1. one with the even values.
17495 // 2. one with the odd values.
17496 // To achieve #2, with need to place the odd values at an even position.
17498 // Place the odd value at an even position (basically, shift all values 1
17499 // step to the left):
17500 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17501 // <a|b|c|d> => <b|undef|d|undef>
17502 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17503 // <e|f|g|h> => <f|undef|h|undef>
17504 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17506 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17508 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17509 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17511 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17512 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17513 // => <2 x i64> <ae|cg>
17514 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17515 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17516 // => <2 x i64> <bf|dh>
17517 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17519 // Shuffle it back into the right order.
17520 SDValue Highs, Lows;
17521 if (VT == MVT::v8i32) {
17522 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17523 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17524 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17525 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17527 const int HighMask[] = {1, 5, 3, 7};
17528 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17529 const int LowMask[] = {0, 4, 2, 6};
17530 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17533 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17534 // unsigned multiply.
17535 if (IsSigned && !Subtarget->hasSSE41()) {
17536 SDValue ShAmt = DAG.getConstant(
17538 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17539 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17540 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17541 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17542 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17544 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17545 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17548 // The first result of MUL_LOHI is actually the low value, followed by the
17550 SDValue Ops[] = {Lows, Highs};
17551 return DAG.getMergeValues(Ops, dl);
17554 // Return true if the required (according to Opcode) shift-imm form is natively
17555 // supported by the Subtarget
17556 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17558 if (VT.getScalarSizeInBits() < 16)
17561 if (VT.is512BitVector() &&
17562 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17565 bool LShift = VT.is128BitVector() ||
17566 (VT.is256BitVector() && Subtarget->hasInt256());
17568 bool AShift = LShift && (Subtarget->hasVLX() ||
17569 (VT != MVT::v2i64 && VT != MVT::v4i64));
17570 return (Opcode == ISD::SRA) ? AShift : LShift;
17573 // The shift amount is a variable, but it is the same for all vector lanes.
17574 // These instructions are defined together with shift-immediate.
17576 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17578 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17581 // Return true if the required (according to Opcode) variable-shift form is
17582 // natively supported by the Subtarget
17583 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17586 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17589 // vXi16 supported only on AVX-512, BWI
17590 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17593 if (VT.is512BitVector() || Subtarget->hasVLX())
17596 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17597 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17598 return (Opcode == ISD::SRA) ? AShift : LShift;
17601 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17602 const X86Subtarget *Subtarget) {
17603 MVT VT = Op.getSimpleValueType();
17605 SDValue R = Op.getOperand(0);
17606 SDValue Amt = Op.getOperand(1);
17608 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17609 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17611 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17612 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17613 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17614 SDValue Ex = DAG.getBitcast(ExVT, R);
17616 if (ShiftAmt >= 32) {
17617 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17619 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17620 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17621 ShiftAmt - 32, DAG);
17622 if (VT == MVT::v2i64)
17623 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17624 if (VT == MVT::v4i64)
17625 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17626 {9, 1, 11, 3, 13, 5, 15, 7});
17628 // SRA upper i32, SHL whole i64 and select lower i32.
17629 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17632 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17633 Lower = DAG.getBitcast(ExVT, Lower);
17634 if (VT == MVT::v2i64)
17635 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17636 if (VT == MVT::v4i64)
17637 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17638 {8, 1, 10, 3, 12, 5, 14, 7});
17640 return DAG.getBitcast(VT, Ex);
17643 // Optimize shl/srl/sra with constant shift amount.
17644 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17645 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17646 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17648 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17649 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17651 // i64 SRA needs to be performed as partial shifts.
17652 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17653 Op.getOpcode() == ISD::SRA)
17654 return ArithmeticShiftRight64(ShiftAmt);
17656 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17657 unsigned NumElts = VT.getVectorNumElements();
17658 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17660 if (Op.getOpcode() == ISD::SHL) {
17661 // Simple i8 add case
17663 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17665 // Make a large shift.
17666 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17668 SHL = DAG.getBitcast(VT, SHL);
17669 // Zero out the rightmost bits.
17670 SmallVector<SDValue, 32> V(
17671 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17672 return DAG.getNode(ISD::AND, dl, VT, SHL,
17673 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17675 if (Op.getOpcode() == ISD::SRL) {
17676 // Make a large shift.
17677 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17679 SRL = DAG.getBitcast(VT, SRL);
17680 // Zero out the leftmost bits.
17681 SmallVector<SDValue, 32> V(
17682 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17683 return DAG.getNode(ISD::AND, dl, VT, SRL,
17684 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17686 if (Op.getOpcode() == ISD::SRA) {
17687 if (ShiftAmt == 7) {
17688 // ashr(R, 7) === cmp_slt(R, 0)
17689 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17690 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17693 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17694 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17695 SmallVector<SDValue, 32> V(NumElts,
17696 DAG.getConstant(128 >> ShiftAmt, dl,
17698 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17699 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17700 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17703 llvm_unreachable("Unknown shift opcode.");
17708 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17709 if (!Subtarget->is64Bit() &&
17710 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17712 // Peek through any splat that was introduced for i64 shift vectorization.
17713 int SplatIndex = -1;
17714 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17715 if (SVN->isSplat()) {
17716 SplatIndex = SVN->getSplatIndex();
17717 Amt = Amt.getOperand(0);
17718 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17719 "Splat shuffle referencing second operand");
17722 if (Amt.getOpcode() != ISD::BITCAST ||
17723 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17726 Amt = Amt.getOperand(0);
17727 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17728 VT.getVectorNumElements();
17729 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17730 uint64_t ShiftAmt = 0;
17731 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17732 for (unsigned i = 0; i != Ratio; ++i) {
17733 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17737 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17740 // Check remaining shift amounts (if not a splat).
17741 if (SplatIndex < 0) {
17742 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17743 uint64_t ShAmt = 0;
17744 for (unsigned j = 0; j != Ratio; ++j) {
17745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17749 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17751 if (ShAmt != ShiftAmt)
17756 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17757 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17759 if (Op.getOpcode() == ISD::SRA)
17760 return ArithmeticShiftRight64(ShiftAmt);
17766 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17767 const X86Subtarget* Subtarget) {
17768 MVT VT = Op.getSimpleValueType();
17770 SDValue R = Op.getOperand(0);
17771 SDValue Amt = Op.getOperand(1);
17773 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17774 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17776 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
17777 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
17779 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
17781 EVT EltVT = VT.getVectorElementType();
17783 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
17784 // Check if this build_vector node is doing a splat.
17785 // If so, then set BaseShAmt equal to the splat value.
17786 BaseShAmt = BV->getSplatValue();
17787 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
17788 BaseShAmt = SDValue();
17790 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17791 Amt = Amt.getOperand(0);
17793 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
17794 if (SVN && SVN->isSplat()) {
17795 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
17796 SDValue InVec = Amt.getOperand(0);
17797 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17798 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
17799 "Unexpected shuffle index found!");
17800 BaseShAmt = InVec.getOperand(SplatIdx);
17801 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17802 if (ConstantSDNode *C =
17803 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17804 if (C->getZExtValue() == SplatIdx)
17805 BaseShAmt = InVec.getOperand(1);
17810 // Avoid introducing an extract element from a shuffle.
17811 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
17812 DAG.getIntPtrConstant(SplatIdx, dl));
17816 if (BaseShAmt.getNode()) {
17817 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
17818 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
17819 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
17820 else if (EltVT.bitsLT(MVT::i32))
17821 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17823 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
17827 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17828 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
17829 Amt.getOpcode() == ISD::BITCAST &&
17830 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17831 Amt = Amt.getOperand(0);
17832 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17833 VT.getVectorNumElements();
17834 std::vector<SDValue> Vals(Ratio);
17835 for (unsigned i = 0; i != Ratio; ++i)
17836 Vals[i] = Amt.getOperand(i);
17837 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17838 for (unsigned j = 0; j != Ratio; ++j)
17839 if (Vals[j] != Amt.getOperand(i + j))
17843 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
17844 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
17849 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17850 SelectionDAG &DAG) {
17851 MVT VT = Op.getSimpleValueType();
17853 SDValue R = Op.getOperand(0);
17854 SDValue Amt = Op.getOperand(1);
17856 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17857 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17859 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
17862 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
17865 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
17868 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
17869 // shifts per-lane and then shuffle the partial results back together.
17870 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
17871 // Splat the shift amounts so the scalar shifts above will catch it.
17872 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
17873 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
17874 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
17875 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
17876 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
17879 // i64 vector arithmetic shift can be emulated with the transform:
17880 // M = lshr(SIGN_BIT, Amt)
17881 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
17882 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
17883 Op.getOpcode() == ISD::SRA) {
17884 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
17885 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
17886 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17887 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
17888 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
17892 // If possible, lower this packed shift into a vector multiply instead of
17893 // expanding it into a sequence of scalar shifts.
17894 // Do this only if the vector shift count is a constant build_vector.
17895 if (Op.getOpcode() == ISD::SHL &&
17896 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17897 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17898 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17899 SmallVector<SDValue, 8> Elts;
17900 EVT SVT = VT.getScalarType();
17901 unsigned SVTBits = SVT.getSizeInBits();
17902 const APInt &One = APInt(SVTBits, 1);
17903 unsigned NumElems = VT.getVectorNumElements();
17905 for (unsigned i=0; i !=NumElems; ++i) {
17906 SDValue Op = Amt->getOperand(i);
17907 if (Op->getOpcode() == ISD::UNDEF) {
17908 Elts.push_back(Op);
17912 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17913 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17914 uint64_t ShAmt = C.getZExtValue();
17915 if (ShAmt >= SVTBits) {
17916 Elts.push_back(DAG.getUNDEF(SVT));
17919 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
17921 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17922 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17925 // Lower SHL with variable shift amount.
17926 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17927 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
17929 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
17930 DAG.getConstant(0x3f800000U, dl, VT));
17931 Op = DAG.getBitcast(MVT::v4f32, Op);
17932 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17933 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17936 // If possible, lower this shift as a sequence of two shifts by
17937 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17939 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17941 // Could be rewritten as:
17942 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17944 // The advantage is that the two shifts from the example would be
17945 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17946 // the vector shift into four scalar shifts plus four pairs of vector
17948 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17949 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17950 unsigned TargetOpcode = X86ISD::MOVSS;
17951 bool CanBeSimplified;
17952 // The splat value for the first packed shift (the 'X' from the example).
17953 SDValue Amt1 = Amt->getOperand(0);
17954 // The splat value for the second packed shift (the 'Y' from the example).
17955 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17956 Amt->getOperand(2);
17958 // See if it is possible to replace this node with a sequence of
17959 // two shifts followed by a MOVSS/MOVSD
17960 if (VT == MVT::v4i32) {
17961 // Check if it is legal to use a MOVSS.
17962 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17963 Amt2 == Amt->getOperand(3);
17964 if (!CanBeSimplified) {
17965 // Otherwise, check if we can still simplify this node using a MOVSD.
17966 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17967 Amt->getOperand(2) == Amt->getOperand(3);
17968 TargetOpcode = X86ISD::MOVSD;
17969 Amt2 = Amt->getOperand(2);
17972 // Do similar checks for the case where the machine value type
17974 CanBeSimplified = Amt1 == Amt->getOperand(1);
17975 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17976 CanBeSimplified = Amt2 == Amt->getOperand(i);
17978 if (!CanBeSimplified) {
17979 TargetOpcode = X86ISD::MOVSD;
17980 CanBeSimplified = true;
17981 Amt2 = Amt->getOperand(4);
17982 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17983 CanBeSimplified = Amt1 == Amt->getOperand(i);
17984 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17985 CanBeSimplified = Amt2 == Amt->getOperand(j);
17989 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17990 isa<ConstantSDNode>(Amt2)) {
17991 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17992 EVT CastVT = MVT::v4i32;
17994 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17995 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17997 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17998 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17999 if (TargetOpcode == X86ISD::MOVSD)
18000 CastVT = MVT::v2i64;
18001 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18002 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18003 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18005 return DAG.getBitcast(VT, Result);
18009 // v4i32 Non Uniform Shifts.
18010 // If the shift amount is constant we can shift each lane using the SSE2
18011 // immediate shifts, else we need to zero-extend each lane to the lower i64
18012 // and shift using the SSE2 variable shifts.
18013 // The separate results can then be blended together.
18014 if (VT == MVT::v4i32) {
18015 unsigned Opc = Op.getOpcode();
18016 SDValue Amt0, Amt1, Amt2, Amt3;
18017 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18018 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18019 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18020 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18021 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18023 // ISD::SHL is handled above but we include it here for completeness.
18026 llvm_unreachable("Unknown target vector shift node");
18028 Opc = X86ISD::VSHL;
18031 Opc = X86ISD::VSRL;
18034 Opc = X86ISD::VSRA;
18037 // The SSE2 shifts use the lower i64 as the same shift amount for
18038 // all lanes and the upper i64 is ignored. These shuffle masks
18039 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18040 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18041 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18042 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18043 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18044 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18047 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18048 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18049 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18050 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18051 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18052 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18053 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18056 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
18057 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18058 unsigned ShiftOpcode = Op->getOpcode();
18060 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18061 // On SSE41 targets we make use of the fact that VSELECT lowers
18062 // to PBLENDVB which selects bytes based just on the sign bit.
18063 if (Subtarget->hasSSE41()) {
18064 V0 = DAG.getBitcast(VT, V0);
18065 V1 = DAG.getBitcast(VT, V1);
18066 Sel = DAG.getBitcast(VT, Sel);
18067 return DAG.getBitcast(SelVT,
18068 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18070 // On pre-SSE41 targets we test for the sign bit by comparing to
18071 // zero - a negative value will set all bits of the lanes to true
18072 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18073 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18074 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18075 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18078 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18079 // We can safely do this using i16 shifts as we're only interested in
18080 // the 3 lower bits of each byte.
18081 Amt = DAG.getBitcast(ExtVT, Amt);
18082 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18083 Amt = DAG.getBitcast(VT, Amt);
18085 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18086 // r = VSELECT(r, shift(r, 4), a);
18088 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18089 R = SignBitSelect(VT, Amt, M, R);
18092 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18094 // r = VSELECT(r, shift(r, 2), a);
18095 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18096 R = SignBitSelect(VT, Amt, M, R);
18099 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18101 // return VSELECT(r, shift(r, 1), a);
18102 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18103 R = SignBitSelect(VT, Amt, M, R);
18107 if (Op->getOpcode() == ISD::SRA) {
18108 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18109 // so we can correctly sign extend. We don't care what happens to the
18111 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18112 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18113 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18114 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18115 ALo = DAG.getBitcast(ExtVT, ALo);
18116 AHi = DAG.getBitcast(ExtVT, AHi);
18117 RLo = DAG.getBitcast(ExtVT, RLo);
18118 RHi = DAG.getBitcast(ExtVT, RHi);
18120 // r = VSELECT(r, shift(r, 4), a);
18121 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18122 DAG.getConstant(4, dl, ExtVT));
18123 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18124 DAG.getConstant(4, dl, ExtVT));
18125 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18126 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18129 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18130 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18132 // r = VSELECT(r, shift(r, 2), a);
18133 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18134 DAG.getConstant(2, dl, ExtVT));
18135 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18136 DAG.getConstant(2, dl, ExtVT));
18137 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18138 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18141 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18142 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18144 // r = VSELECT(r, shift(r, 1), a);
18145 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18146 DAG.getConstant(1, dl, ExtVT));
18147 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18148 DAG.getConstant(1, dl, ExtVT));
18149 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18150 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18152 // Logical shift the result back to the lower byte, leaving a zero upper
18154 // meaning that we can safely pack with PACKUSWB.
18156 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18158 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18159 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18163 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18164 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18165 // solution better.
18166 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18167 MVT ExtVT = MVT::v8i32;
18169 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18170 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18171 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18172 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18173 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18176 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
18177 MVT ExtVT = MVT::v8i32;
18178 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18179 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18180 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18181 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18182 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18183 ALo = DAG.getBitcast(ExtVT, ALo);
18184 AHi = DAG.getBitcast(ExtVT, AHi);
18185 RLo = DAG.getBitcast(ExtVT, RLo);
18186 RHi = DAG.getBitcast(ExtVT, RHi);
18187 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18188 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18189 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18190 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18191 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18194 if (VT == MVT::v8i16) {
18195 unsigned ShiftOpcode = Op->getOpcode();
18197 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18198 // On SSE41 targets we make use of the fact that VSELECT lowers
18199 // to PBLENDVB which selects bytes based just on the sign bit.
18200 if (Subtarget->hasSSE41()) {
18201 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18202 V0 = DAG.getBitcast(ExtVT, V0);
18203 V1 = DAG.getBitcast(ExtVT, V1);
18204 Sel = DAG.getBitcast(ExtVT, Sel);
18205 return DAG.getBitcast(
18206 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18208 // On pre-SSE41 targets we splat the sign bit - a negative value will
18209 // set all bits of the lanes to true and VSELECT uses that in
18210 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18212 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18213 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18216 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18217 if (Subtarget->hasSSE41()) {
18218 // On SSE41 targets we need to replicate the shift mask in both
18219 // bytes for PBLENDVB.
18222 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18223 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18225 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18228 // r = VSELECT(r, shift(r, 8), a);
18229 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18230 R = SignBitSelect(Amt, M, R);
18233 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18235 // r = VSELECT(r, shift(r, 4), a);
18236 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18237 R = SignBitSelect(Amt, M, R);
18240 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18242 // r = VSELECT(r, shift(r, 2), a);
18243 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18244 R = SignBitSelect(Amt, M, R);
18247 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18249 // return VSELECT(r, shift(r, 1), a);
18250 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18251 R = SignBitSelect(Amt, M, R);
18255 // Decompose 256-bit shifts into smaller 128-bit shifts.
18256 if (VT.is256BitVector()) {
18257 unsigned NumElems = VT.getVectorNumElements();
18258 MVT EltVT = VT.getVectorElementType();
18259 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18261 // Extract the two vectors
18262 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18263 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18265 // Recreate the shift amount vectors
18266 SDValue Amt1, Amt2;
18267 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18268 // Constant shift amount
18269 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18270 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18271 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18273 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18274 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18276 // Variable shift amount
18277 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18278 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18281 // Issue new vector shifts for the smaller types
18282 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18283 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18285 // Concatenate the result back
18286 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18292 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18293 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18294 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18295 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18296 // has only one use.
18297 SDNode *N = Op.getNode();
18298 SDValue LHS = N->getOperand(0);
18299 SDValue RHS = N->getOperand(1);
18300 unsigned BaseOp = 0;
18303 switch (Op.getOpcode()) {
18304 default: llvm_unreachable("Unknown ovf instruction!");
18306 // A subtract of one will be selected as a INC. Note that INC doesn't
18307 // set CF, so we can't do this for UADDO.
18308 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18310 BaseOp = X86ISD::INC;
18311 Cond = X86::COND_O;
18314 BaseOp = X86ISD::ADD;
18315 Cond = X86::COND_O;
18318 BaseOp = X86ISD::ADD;
18319 Cond = X86::COND_B;
18322 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18323 // set CF, so we can't do this for USUBO.
18324 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18326 BaseOp = X86ISD::DEC;
18327 Cond = X86::COND_O;
18330 BaseOp = X86ISD::SUB;
18331 Cond = X86::COND_O;
18334 BaseOp = X86ISD::SUB;
18335 Cond = X86::COND_B;
18338 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18339 Cond = X86::COND_O;
18341 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18342 if (N->getValueType(0) == MVT::i8) {
18343 BaseOp = X86ISD::UMUL8;
18344 Cond = X86::COND_O;
18347 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18349 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18352 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18353 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18354 SDValue(Sum.getNode(), 2));
18356 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18360 // Also sets EFLAGS.
18361 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18362 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18365 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18366 DAG.getConstant(Cond, DL, MVT::i32),
18367 SDValue(Sum.getNode(), 1));
18369 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18372 /// Returns true if the operand type is exactly twice the native width, and
18373 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18374 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18375 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18376 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18377 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18380 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18381 else if (OpWidth == 128)
18382 return Subtarget->hasCmpxchg16b();
18387 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18388 return needsCmpXchgNb(SI->getValueOperand()->getType());
18391 // Note: this turns large loads into lock cmpxchg8b/16b.
18392 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18393 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18394 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18395 return needsCmpXchgNb(PTy->getElementType());
18398 TargetLoweringBase::AtomicRMWExpansionKind
18399 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18400 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18401 Type *MemType = AI->getType();
18403 // If the operand is too big, we must see if cmpxchg8/16b is available
18404 // and default to library calls otherwise.
18405 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18406 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
18407 : AtomicRMWExpansionKind::None;
18410 AtomicRMWInst::BinOp Op = AI->getOperation();
18413 llvm_unreachable("Unknown atomic operation");
18414 case AtomicRMWInst::Xchg:
18415 case AtomicRMWInst::Add:
18416 case AtomicRMWInst::Sub:
18417 // It's better to use xadd, xsub or xchg for these in all cases.
18418 return AtomicRMWExpansionKind::None;
18419 case AtomicRMWInst::Or:
18420 case AtomicRMWInst::And:
18421 case AtomicRMWInst::Xor:
18422 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18423 // prefix to a normal instruction for these operations.
18424 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
18425 : AtomicRMWExpansionKind::None;
18426 case AtomicRMWInst::Nand:
18427 case AtomicRMWInst::Max:
18428 case AtomicRMWInst::Min:
18429 case AtomicRMWInst::UMax:
18430 case AtomicRMWInst::UMin:
18431 // These always require a non-trivial set of data operations on x86. We must
18432 // use a cmpxchg loop.
18433 return AtomicRMWExpansionKind::CmpXChg;
18437 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18438 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18439 // no-sse2). There isn't any reason to disable it if the target processor
18441 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18445 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18446 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18447 Type *MemType = AI->getType();
18448 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18449 // there is no benefit in turning such RMWs into loads, and it is actually
18450 // harmful as it introduces a mfence.
18451 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18454 auto Builder = IRBuilder<>(AI);
18455 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18456 auto SynchScope = AI->getSynchScope();
18457 // We must restrict the ordering to avoid generating loads with Release or
18458 // ReleaseAcquire orderings.
18459 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18460 auto Ptr = AI->getPointerOperand();
18462 // Before the load we need a fence. Here is an example lifted from
18463 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18466 // x.store(1, relaxed);
18467 // r1 = y.fetch_add(0, release);
18469 // y.fetch_add(42, acquire);
18470 // r2 = x.load(relaxed);
18471 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18472 // lowered to just a load without a fence. A mfence flushes the store buffer,
18473 // making the optimization clearly correct.
18474 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18475 // otherwise, we might be able to be more aggressive on relaxed idempotent
18476 // rmw. In practice, they do not look useful, so we don't try to be
18477 // especially clever.
18478 if (SynchScope == SingleThread)
18479 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18480 // the IR level, so we must wrap it in an intrinsic.
18483 if (!hasMFENCE(*Subtarget))
18484 // FIXME: it might make sense to use a locked operation here but on a
18485 // different cache-line to prevent cache-line bouncing. In practice it
18486 // is probably a small win, and x86 processors without mfence are rare
18487 // enough that we do not bother.
18491 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18492 Builder.CreateCall(MFence, {});
18494 // Finally we can emit the atomic load.
18495 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18496 AI->getType()->getPrimitiveSizeInBits());
18497 Loaded->setAtomic(Order, SynchScope);
18498 AI->replaceAllUsesWith(Loaded);
18499 AI->eraseFromParent();
18503 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18504 SelectionDAG &DAG) {
18506 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18507 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18508 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18509 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18511 // The only fence that needs an instruction is a sequentially-consistent
18512 // cross-thread fence.
18513 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18514 if (hasMFENCE(*Subtarget))
18515 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18517 SDValue Chain = Op.getOperand(0);
18518 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18520 DAG.getRegister(X86::ESP, MVT::i32), // Base
18521 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18522 DAG.getRegister(0, MVT::i32), // Index
18523 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18524 DAG.getRegister(0, MVT::i32), // Segment.
18528 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18529 return SDValue(Res, 0);
18532 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18533 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18536 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18537 SelectionDAG &DAG) {
18538 MVT T = Op.getSimpleValueType();
18542 switch(T.SimpleTy) {
18543 default: llvm_unreachable("Invalid value type!");
18544 case MVT::i8: Reg = X86::AL; size = 1; break;
18545 case MVT::i16: Reg = X86::AX; size = 2; break;
18546 case MVT::i32: Reg = X86::EAX; size = 4; break;
18548 assert(Subtarget->is64Bit() && "Node not type legal!");
18549 Reg = X86::RAX; size = 8;
18552 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18553 Op.getOperand(2), SDValue());
18554 SDValue Ops[] = { cpIn.getValue(0),
18557 DAG.getTargetConstant(size, DL, MVT::i8),
18558 cpIn.getValue(1) };
18559 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18560 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18561 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18565 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18566 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18567 MVT::i32, cpOut.getValue(2));
18568 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18569 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18572 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18573 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18574 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18578 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18579 SelectionDAG &DAG) {
18580 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18581 MVT DstVT = Op.getSimpleValueType();
18583 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18584 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18585 if (DstVT != MVT::f64)
18586 // This conversion needs to be expanded.
18589 SDValue InVec = Op->getOperand(0);
18591 unsigned NumElts = SrcVT.getVectorNumElements();
18592 EVT SVT = SrcVT.getVectorElementType();
18594 // Widen the vector in input in the case of MVT::v2i32.
18595 // Example: from MVT::v2i32 to MVT::v4i32.
18596 SmallVector<SDValue, 16> Elts;
18597 for (unsigned i = 0, e = NumElts; i != e; ++i)
18598 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18599 DAG.getIntPtrConstant(i, dl)));
18601 // Explicitly mark the extra elements as Undef.
18602 Elts.append(NumElts, DAG.getUNDEF(SVT));
18604 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18605 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18606 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18607 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18608 DAG.getIntPtrConstant(0, dl));
18611 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18612 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18613 assert((DstVT == MVT::i64 ||
18614 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18615 "Unexpected custom BITCAST");
18616 // i64 <=> MMX conversions are Legal.
18617 if (SrcVT==MVT::i64 && DstVT.isVector())
18619 if (DstVT==MVT::i64 && SrcVT.isVector())
18621 // MMX <=> MMX conversions are Legal.
18622 if (SrcVT.isVector() && DstVT.isVector())
18624 // All other conversions need to be expanded.
18628 /// Compute the horizontal sum of bytes in V for the elements of VT.
18630 /// Requires V to be a byte vector and VT to be an integer vector type with
18631 /// wider elements than V's type. The width of the elements of VT determines
18632 /// how many bytes of V are summed horizontally to produce each element of the
18634 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18635 const X86Subtarget *Subtarget,
18636 SelectionDAG &DAG) {
18638 MVT ByteVecVT = V.getSimpleValueType();
18639 MVT EltVT = VT.getVectorElementType();
18640 int NumElts = VT.getVectorNumElements();
18641 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18642 "Expected value to have byte element type.");
18643 assert(EltVT != MVT::i8 &&
18644 "Horizontal byte sum only makes sense for wider elements!");
18645 unsigned VecSize = VT.getSizeInBits();
18646 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18648 // PSADBW instruction horizontally add all bytes and leave the result in i64
18649 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18650 if (EltVT == MVT::i64) {
18651 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18652 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18653 return DAG.getBitcast(VT, V);
18656 if (EltVT == MVT::i32) {
18657 // We unpack the low half and high half into i32s interleaved with zeros so
18658 // that we can use PSADBW to horizontally sum them. The most useful part of
18659 // this is that it lines up the results of two PSADBW instructions to be
18660 // two v2i64 vectors which concatenated are the 4 population counts. We can
18661 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18662 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18663 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18664 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18666 // Do the horizontal sums into two v2i64s.
18667 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18668 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18669 DAG.getBitcast(ByteVecVT, Low), Zeros);
18670 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18671 DAG.getBitcast(ByteVecVT, High), Zeros);
18673 // Merge them together.
18674 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18675 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18676 DAG.getBitcast(ShortVecVT, Low),
18677 DAG.getBitcast(ShortVecVT, High));
18679 return DAG.getBitcast(VT, V);
18682 // The only element type left is i16.
18683 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18685 // To obtain pop count for each i16 element starting from the pop count for
18686 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18687 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18688 // directly supported.
18689 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18690 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18691 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18692 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18693 DAG.getBitcast(ByteVecVT, V));
18694 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18697 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18698 const X86Subtarget *Subtarget,
18699 SelectionDAG &DAG) {
18700 MVT VT = Op.getSimpleValueType();
18701 MVT EltVT = VT.getVectorElementType();
18702 unsigned VecSize = VT.getSizeInBits();
18704 // Implement a lookup table in register by using an algorithm based on:
18705 // http://wm.ite.pl/articles/sse-popcount.html
18707 // The general idea is that every lower byte nibble in the input vector is an
18708 // index into a in-register pre-computed pop count table. We then split up the
18709 // input vector in two new ones: (1) a vector with only the shifted-right
18710 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18711 // masked out higher ones) for each byte. PSHUB is used separately with both
18712 // to index the in-register table. Next, both are added and the result is a
18713 // i8 vector where each element contains the pop count for input byte.
18715 // To obtain the pop count for elements != i8, we follow up with the same
18716 // approach and use additional tricks as described below.
18718 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18719 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18720 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18721 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18723 int NumByteElts = VecSize / 8;
18724 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18725 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18726 SmallVector<SDValue, 16> LUTVec;
18727 for (int i = 0; i < NumByteElts; ++i)
18728 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18729 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18730 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18731 DAG.getConstant(0x0F, DL, MVT::i8));
18732 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18735 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18736 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18737 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18740 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18742 // The input vector is used as the shuffle mask that index elements into the
18743 // LUT. After counting low and high nibbles, add the vector to obtain the
18744 // final pop count per i8 element.
18745 SDValue HighPopCnt =
18746 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18747 SDValue LowPopCnt =
18748 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18749 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18751 if (EltVT == MVT::i8)
18754 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
18757 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
18758 const X86Subtarget *Subtarget,
18759 SelectionDAG &DAG) {
18760 MVT VT = Op.getSimpleValueType();
18761 assert(VT.is128BitVector() &&
18762 "Only 128-bit vector bitmath lowering supported.");
18764 int VecSize = VT.getSizeInBits();
18765 MVT EltVT = VT.getVectorElementType();
18766 int Len = EltVT.getSizeInBits();
18768 // This is the vectorized version of the "best" algorithm from
18769 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
18770 // with a minor tweak to use a series of adds + shifts instead of vector
18771 // multiplications. Implemented for all integer vector types. We only use
18772 // this when we don't have SSSE3 which allows a LUT-based lowering that is
18773 // much faster, even faster than using native popcnt instructions.
18775 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
18776 MVT VT = V.getSimpleValueType();
18777 SmallVector<SDValue, 32> Shifters(
18778 VT.getVectorNumElements(),
18779 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
18780 return DAG.getNode(OpCode, DL, VT, V,
18781 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
18783 auto GetMask = [&](SDValue V, APInt Mask) {
18784 MVT VT = V.getSimpleValueType();
18785 SmallVector<SDValue, 32> Masks(
18786 VT.getVectorNumElements(),
18787 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
18788 return DAG.getNode(ISD::AND, DL, VT, V,
18789 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
18792 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
18793 // x86, so set the SRL type to have elements at least i16 wide. This is
18794 // correct because all of our SRLs are followed immediately by a mask anyways
18795 // that handles any bits that sneak into the high bits of the byte elements.
18796 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
18800 // v = v - ((v >> 1) & 0x55555555...)
18802 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
18803 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
18804 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
18806 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
18807 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
18808 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
18809 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
18810 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
18812 // v = (v + (v >> 4)) & 0x0F0F0F0F...
18813 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
18814 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
18815 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
18817 // At this point, V contains the byte-wise population count, and we are
18818 // merely doing a horizontal sum if necessary to get the wider element
18820 if (EltVT == MVT::i8)
18823 return LowerHorizontalByteSum(
18824 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
18828 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18829 SelectionDAG &DAG) {
18830 MVT VT = Op.getSimpleValueType();
18831 // FIXME: Need to add AVX-512 support here!
18832 assert((VT.is256BitVector() || VT.is128BitVector()) &&
18833 "Unknown CTPOP type to handle");
18834 SDLoc DL(Op.getNode());
18835 SDValue Op0 = Op.getOperand(0);
18837 if (!Subtarget->hasSSSE3()) {
18838 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
18839 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
18840 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
18843 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
18844 unsigned NumElems = VT.getVectorNumElements();
18846 // Extract each 128-bit vector, compute pop count and concat the result.
18847 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
18848 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
18850 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
18851 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
18852 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
18855 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
18858 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18859 SelectionDAG &DAG) {
18860 assert(Op.getValueType().isVector() &&
18861 "We only do custom lowering for vector population count.");
18862 return LowerVectorCTPOP(Op, Subtarget, DAG);
18865 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18866 SDNode *Node = Op.getNode();
18868 EVT T = Node->getValueType(0);
18869 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18870 DAG.getConstant(0, dl, T), Node->getOperand(2));
18871 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18872 cast<AtomicSDNode>(Node)->getMemoryVT(),
18873 Node->getOperand(0),
18874 Node->getOperand(1), negOp,
18875 cast<AtomicSDNode>(Node)->getMemOperand(),
18876 cast<AtomicSDNode>(Node)->getOrdering(),
18877 cast<AtomicSDNode>(Node)->getSynchScope());
18880 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18881 SDNode *Node = Op.getNode();
18883 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18885 // Convert seq_cst store -> xchg
18886 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18887 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18888 // (The only way to get a 16-byte store is cmpxchg16b)
18889 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18890 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18891 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18892 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18893 cast<AtomicSDNode>(Node)->getMemoryVT(),
18894 Node->getOperand(0),
18895 Node->getOperand(1), Node->getOperand(2),
18896 cast<AtomicSDNode>(Node)->getMemOperand(),
18897 cast<AtomicSDNode>(Node)->getOrdering(),
18898 cast<AtomicSDNode>(Node)->getSynchScope());
18899 return Swap.getValue(1);
18901 // Other atomic stores have a simple pattern.
18905 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18906 EVT VT = Op.getNode()->getSimpleValueType(0);
18908 // Let legalize expand this if it isn't a legal type yet.
18909 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18912 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18915 bool ExtraOp = false;
18916 switch (Op.getOpcode()) {
18917 default: llvm_unreachable("Invalid code");
18918 case ISD::ADDC: Opc = X86ISD::ADD; break;
18919 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18920 case ISD::SUBC: Opc = X86ISD::SUB; break;
18921 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18925 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18927 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18928 Op.getOperand(1), Op.getOperand(2));
18931 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18932 SelectionDAG &DAG) {
18933 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18935 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18936 // which returns the values as { float, float } (in XMM0) or
18937 // { double, double } (which is returned in XMM0, XMM1).
18939 SDValue Arg = Op.getOperand(0);
18940 EVT ArgVT = Arg.getValueType();
18941 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18943 TargetLowering::ArgListTy Args;
18944 TargetLowering::ArgListEntry Entry;
18948 Entry.isSExt = false;
18949 Entry.isZExt = false;
18950 Args.push_back(Entry);
18952 bool isF64 = ArgVT == MVT::f64;
18953 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18954 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18955 // the results are returned via SRet in memory.
18956 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18957 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18959 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
18961 Type *RetTy = isF64
18962 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
18963 : (Type*)VectorType::get(ArgTy, 4);
18965 TargetLowering::CallLoweringInfo CLI(DAG);
18966 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18967 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18969 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18972 // Returned in xmm0 and xmm1.
18973 return CallResult.first;
18975 // Returned in bits 0:31 and 32:64 xmm0.
18976 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18977 CallResult.first, DAG.getIntPtrConstant(0, dl));
18978 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18979 CallResult.first, DAG.getIntPtrConstant(1, dl));
18980 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18981 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18984 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
18985 SelectionDAG &DAG) {
18986 assert(Subtarget->hasAVX512() &&
18987 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18989 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
18990 EVT VT = N->getValue().getValueType();
18991 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
18994 // X86 scatter kills mask register, so its type should be added to
18995 // the list of return values
18996 if (N->getNumValues() == 1) {
18997 SDValue Index = N->getIndex();
18998 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18999 !Index.getValueType().is512BitVector())
19000 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19002 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19003 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19004 N->getOperand(3), Index };
19006 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19007 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19008 return SDValue(NewScatter.getNode(), 0);
19013 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19014 SelectionDAG &DAG) {
19015 assert(Subtarget->hasAVX512() &&
19016 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19018 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19019 EVT VT = Op.getValueType();
19020 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19023 SDValue Index = N->getIndex();
19024 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19025 !Index.getValueType().is512BitVector()) {
19026 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19027 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19028 N->getOperand(3), Index };
19029 DAG.UpdateNodeOperands(N, Ops);
19034 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19035 SelectionDAG &DAG) const {
19036 // TODO: Eventually, the lowering of these nodes should be informed by or
19037 // deferred to the GC strategy for the function in which they appear. For
19038 // now, however, they must be lowered to something. Since they are logically
19039 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19040 // require special handling for these nodes), lower them as literal NOOPs for
19042 SmallVector<SDValue, 2> Ops;
19044 Ops.push_back(Op.getOperand(0));
19045 if (Op->getGluedNode())
19046 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19049 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19050 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19055 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19056 SelectionDAG &DAG) const {
19057 // TODO: Eventually, the lowering of these nodes should be informed by or
19058 // deferred to the GC strategy for the function in which they appear. For
19059 // now, however, they must be lowered to something. Since they are logically
19060 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19061 // require special handling for these nodes), lower them as literal NOOPs for
19063 SmallVector<SDValue, 2> Ops;
19065 Ops.push_back(Op.getOperand(0));
19066 if (Op->getGluedNode())
19067 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19070 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19071 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19076 /// LowerOperation - Provide custom lowering hooks for some operations.
19078 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19079 switch (Op.getOpcode()) {
19080 default: llvm_unreachable("Should not custom lower this!");
19081 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19082 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19083 return LowerCMP_SWAP(Op, Subtarget, DAG);
19084 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19085 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19086 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19087 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19088 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19089 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19090 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19091 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19092 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19093 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19094 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19095 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19096 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19097 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19098 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19099 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19100 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19101 case ISD::SHL_PARTS:
19102 case ISD::SRA_PARTS:
19103 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19104 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19105 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19106 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19107 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19108 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19109 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19110 case ISD::SIGN_EXTEND_VECTOR_INREG:
19111 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19112 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19113 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19114 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19115 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19117 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19118 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19119 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19120 case ISD::SETCC: return LowerSETCC(Op, DAG);
19121 case ISD::SELECT: return LowerSELECT(Op, DAG);
19122 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19123 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19124 case ISD::VASTART: return LowerVASTART(Op, DAG);
19125 case ISD::VAARG: return LowerVAARG(Op, DAG);
19126 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19127 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19128 case ISD::INTRINSIC_VOID:
19129 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19130 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19131 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19132 case ISD::FRAME_TO_ARGS_OFFSET:
19133 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19134 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19135 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19136 case ISD::CATCHRET: return LowerCATCHRET(Op, DAG);
19137 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19138 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19139 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19140 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19141 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19142 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19143 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19144 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19145 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19146 case ISD::UMUL_LOHI:
19147 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19150 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19156 case ISD::UMULO: return LowerXALUO(Op, DAG);
19157 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19158 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19162 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19163 case ISD::ADD: return LowerADD(Op, DAG);
19164 case ISD::SUB: return LowerSUB(Op, DAG);
19168 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19169 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19170 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19171 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19172 case ISD::GC_TRANSITION_START:
19173 return LowerGC_TRANSITION_START(Op, DAG);
19174 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19178 /// ReplaceNodeResults - Replace a node with an illegal result type
19179 /// with a new node built out of custom code.
19180 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19181 SmallVectorImpl<SDValue>&Results,
19182 SelectionDAG &DAG) const {
19184 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19185 switch (N->getOpcode()) {
19187 llvm_unreachable("Do not know how to custom type legalize this operation!");
19188 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19189 case X86ISD::FMINC:
19191 case X86ISD::FMAXC:
19192 case X86ISD::FMAX: {
19193 EVT VT = N->getValueType(0);
19194 if (VT != MVT::v2f32)
19195 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19196 SDValue UNDEF = DAG.getUNDEF(VT);
19197 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19198 N->getOperand(0), UNDEF);
19199 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19200 N->getOperand(1), UNDEF);
19201 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19204 case ISD::SIGN_EXTEND_INREG:
19209 // We don't want to expand or promote these.
19216 case ISD::UDIVREM: {
19217 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19218 Results.push_back(V);
19221 case ISD::FP_TO_SINT:
19222 case ISD::FP_TO_UINT: {
19223 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19225 std::pair<SDValue,SDValue> Vals =
19226 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19227 SDValue FIST = Vals.first, StackSlot = Vals.second;
19228 if (FIST.getNode()) {
19229 EVT VT = N->getValueType(0);
19230 // Return a load from the stack slot.
19231 if (StackSlot.getNode())
19232 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19233 MachinePointerInfo(),
19234 false, false, false, 0));
19236 Results.push_back(FIST);
19240 case ISD::UINT_TO_FP: {
19241 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19242 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19243 N->getValueType(0) != MVT::v2f32)
19245 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19247 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19249 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19250 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19251 DAG.getBitcast(MVT::v2i64, VBias));
19252 Or = DAG.getBitcast(MVT::v2f64, Or);
19253 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19254 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19257 case ISD::FP_ROUND: {
19258 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19260 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19261 Results.push_back(V);
19264 case ISD::FP_EXTEND: {
19265 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19266 // No other ValueType for FP_EXTEND should reach this point.
19267 assert(N->getValueType(0) == MVT::v2f32 &&
19268 "Do not know how to legalize this Node");
19271 case ISD::INTRINSIC_W_CHAIN: {
19272 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19274 default : llvm_unreachable("Do not know how to custom type "
19275 "legalize this intrinsic operation!");
19276 case Intrinsic::x86_rdtsc:
19277 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19279 case Intrinsic::x86_rdtscp:
19280 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19282 case Intrinsic::x86_rdpmc:
19283 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19286 case ISD::READCYCLECOUNTER: {
19287 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19290 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19291 EVT T = N->getValueType(0);
19292 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19293 bool Regs64bit = T == MVT::i128;
19294 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19295 SDValue cpInL, cpInH;
19296 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19297 DAG.getConstant(0, dl, HalfT));
19298 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19299 DAG.getConstant(1, dl, HalfT));
19300 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19301 Regs64bit ? X86::RAX : X86::EAX,
19303 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19304 Regs64bit ? X86::RDX : X86::EDX,
19305 cpInH, cpInL.getValue(1));
19306 SDValue swapInL, swapInH;
19307 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19308 DAG.getConstant(0, dl, HalfT));
19309 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19310 DAG.getConstant(1, dl, HalfT));
19311 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19312 Regs64bit ? X86::RBX : X86::EBX,
19313 swapInL, cpInH.getValue(1));
19314 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19315 Regs64bit ? X86::RCX : X86::ECX,
19316 swapInH, swapInL.getValue(1));
19317 SDValue Ops[] = { swapInH.getValue(0),
19319 swapInH.getValue(1) };
19320 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19321 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19322 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19323 X86ISD::LCMPXCHG8_DAG;
19324 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19325 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19326 Regs64bit ? X86::RAX : X86::EAX,
19327 HalfT, Result.getValue(1));
19328 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19329 Regs64bit ? X86::RDX : X86::EDX,
19330 HalfT, cpOutL.getValue(2));
19331 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19333 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19334 MVT::i32, cpOutH.getValue(2));
19336 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19337 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19338 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19340 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19341 Results.push_back(Success);
19342 Results.push_back(EFLAGS.getValue(1));
19345 case ISD::ATOMIC_SWAP:
19346 case ISD::ATOMIC_LOAD_ADD:
19347 case ISD::ATOMIC_LOAD_SUB:
19348 case ISD::ATOMIC_LOAD_AND:
19349 case ISD::ATOMIC_LOAD_OR:
19350 case ISD::ATOMIC_LOAD_XOR:
19351 case ISD::ATOMIC_LOAD_NAND:
19352 case ISD::ATOMIC_LOAD_MIN:
19353 case ISD::ATOMIC_LOAD_MAX:
19354 case ISD::ATOMIC_LOAD_UMIN:
19355 case ISD::ATOMIC_LOAD_UMAX:
19356 case ISD::ATOMIC_LOAD: {
19357 // Delegate to generic TypeLegalization. Situations we can really handle
19358 // should have already been dealt with by AtomicExpandPass.cpp.
19361 case ISD::BITCAST: {
19362 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19363 EVT DstVT = N->getValueType(0);
19364 EVT SrcVT = N->getOperand(0)->getValueType(0);
19366 if (SrcVT != MVT::f64 ||
19367 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19370 unsigned NumElts = DstVT.getVectorNumElements();
19371 EVT SVT = DstVT.getVectorElementType();
19372 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19373 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19374 MVT::v2f64, N->getOperand(0));
19375 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19377 if (ExperimentalVectorWideningLegalization) {
19378 // If we are legalizing vectors by widening, we already have the desired
19379 // legal vector type, just return it.
19380 Results.push_back(ToVecInt);
19384 SmallVector<SDValue, 8> Elts;
19385 for (unsigned i = 0, e = NumElts; i != e; ++i)
19386 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19387 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19389 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19394 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19395 switch ((X86ISD::NodeType)Opcode) {
19396 case X86ISD::FIRST_NUMBER: break;
19397 case X86ISD::BSF: return "X86ISD::BSF";
19398 case X86ISD::BSR: return "X86ISD::BSR";
19399 case X86ISD::SHLD: return "X86ISD::SHLD";
19400 case X86ISD::SHRD: return "X86ISD::SHRD";
19401 case X86ISD::FAND: return "X86ISD::FAND";
19402 case X86ISD::FANDN: return "X86ISD::FANDN";
19403 case X86ISD::FOR: return "X86ISD::FOR";
19404 case X86ISD::FXOR: return "X86ISD::FXOR";
19405 case X86ISD::FILD: return "X86ISD::FILD";
19406 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19407 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19408 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19409 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19410 case X86ISD::FLD: return "X86ISD::FLD";
19411 case X86ISD::FST: return "X86ISD::FST";
19412 case X86ISD::CALL: return "X86ISD::CALL";
19413 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19414 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19415 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19416 case X86ISD::BT: return "X86ISD::BT";
19417 case X86ISD::CMP: return "X86ISD::CMP";
19418 case X86ISD::COMI: return "X86ISD::COMI";
19419 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19420 case X86ISD::CMPM: return "X86ISD::CMPM";
19421 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19422 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19423 case X86ISD::SETCC: return "X86ISD::SETCC";
19424 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19425 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19426 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19427 case X86ISD::CMOV: return "X86ISD::CMOV";
19428 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19429 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19430 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19431 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19432 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19433 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19434 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19435 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19436 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19437 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19438 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19439 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19440 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19441 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19442 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19443 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19444 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19445 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19446 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19447 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19448 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19449 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19450 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19451 case X86ISD::HADD: return "X86ISD::HADD";
19452 case X86ISD::HSUB: return "X86ISD::HSUB";
19453 case X86ISD::FHADD: return "X86ISD::FHADD";
19454 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19455 case X86ISD::ABS: return "X86ISD::ABS";
19456 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19457 case X86ISD::FMAX: return "X86ISD::FMAX";
19458 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19459 case X86ISD::FMIN: return "X86ISD::FMIN";
19460 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19461 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19462 case X86ISD::FMINC: return "X86ISD::FMINC";
19463 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19464 case X86ISD::FRCP: return "X86ISD::FRCP";
19465 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19466 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19467 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19468 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19469 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19470 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19471 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19472 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19473 case X86ISD::CATCHRET: return "X86ISD::CATCHRET";
19474 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19475 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19476 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19477 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19478 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19479 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19480 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19481 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19482 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19483 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19484 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19485 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19486 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19487 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19488 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19489 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19490 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19491 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19492 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19493 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19494 case X86ISD::VSHL: return "X86ISD::VSHL";
19495 case X86ISD::VSRL: return "X86ISD::VSRL";
19496 case X86ISD::VSRA: return "X86ISD::VSRA";
19497 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19498 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19499 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19500 case X86ISD::CMPP: return "X86ISD::CMPP";
19501 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19502 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19503 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19504 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19505 case X86ISD::ADD: return "X86ISD::ADD";
19506 case X86ISD::SUB: return "X86ISD::SUB";
19507 case X86ISD::ADC: return "X86ISD::ADC";
19508 case X86ISD::SBB: return "X86ISD::SBB";
19509 case X86ISD::SMUL: return "X86ISD::SMUL";
19510 case X86ISD::UMUL: return "X86ISD::UMUL";
19511 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19512 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19513 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19514 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19515 case X86ISD::INC: return "X86ISD::INC";
19516 case X86ISD::DEC: return "X86ISD::DEC";
19517 case X86ISD::OR: return "X86ISD::OR";
19518 case X86ISD::XOR: return "X86ISD::XOR";
19519 case X86ISD::AND: return "X86ISD::AND";
19520 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19521 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19522 case X86ISD::PTEST: return "X86ISD::PTEST";
19523 case X86ISD::TESTP: return "X86ISD::TESTP";
19524 case X86ISD::TESTM: return "X86ISD::TESTM";
19525 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19526 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19527 case X86ISD::KTEST: return "X86ISD::KTEST";
19528 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19529 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19530 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19531 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19532 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19533 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19534 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19535 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19536 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19537 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19538 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19539 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19540 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19541 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19542 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19543 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19544 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19545 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19546 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19547 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19548 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19549 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19550 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19551 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19552 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19553 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19554 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19555 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19556 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19557 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19558 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19559 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19560 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19561 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19562 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19563 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19564 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19565 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19566 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19567 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19568 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19569 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19570 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19571 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19572 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19573 case X86ISD::SAHF: return "X86ISD::SAHF";
19574 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19575 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19576 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19577 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19578 case X86ISD::FMADD: return "X86ISD::FMADD";
19579 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19580 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19581 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19582 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19583 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19584 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19585 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19586 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19587 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19588 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19589 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19590 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19591 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19592 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19593 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19594 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19595 case X86ISD::XTEST: return "X86ISD::XTEST";
19596 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19597 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19598 case X86ISD::SELECT: return "X86ISD::SELECT";
19599 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19600 case X86ISD::RCP28: return "X86ISD::RCP28";
19601 case X86ISD::EXP2: return "X86ISD::EXP2";
19602 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19603 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19604 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19605 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19606 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19607 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19608 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19609 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19610 case X86ISD::ADDS: return "X86ISD::ADDS";
19611 case X86ISD::SUBS: return "X86ISD::SUBS";
19612 case X86ISD::AVG: return "X86ISD::AVG";
19613 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19614 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19615 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19616 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19617 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19622 // isLegalAddressingMode - Return true if the addressing mode represented
19623 // by AM is legal for this target, for a load/store of the specified type.
19624 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19625 const AddrMode &AM, Type *Ty,
19626 unsigned AS) const {
19627 // X86 supports extremely general addressing modes.
19628 CodeModel::Model M = getTargetMachine().getCodeModel();
19629 Reloc::Model R = getTargetMachine().getRelocationModel();
19631 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19632 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19637 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19639 // If a reference to this global requires an extra load, we can't fold it.
19640 if (isGlobalStubReference(GVFlags))
19643 // If BaseGV requires a register for the PIC base, we cannot also have a
19644 // BaseReg specified.
19645 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19648 // If lower 4G is not available, then we must use rip-relative addressing.
19649 if ((M != CodeModel::Small || R != Reloc::Static) &&
19650 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19654 switch (AM.Scale) {
19660 // These scales always work.
19665 // These scales are formed with basereg+scalereg. Only accept if there is
19670 default: // Other stuff never works.
19677 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19678 unsigned Bits = Ty->getScalarSizeInBits();
19680 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19681 // particularly cheaper than those without.
19685 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19686 // variable shifts just as cheap as scalar ones.
19687 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19690 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19691 // fully general vector.
19695 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19696 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19698 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19699 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19700 return NumBits1 > NumBits2;
19703 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19704 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19707 if (!isTypeLegal(EVT::getEVT(Ty1)))
19710 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19712 // Assuming the caller doesn't have a zeroext or signext return parameter,
19713 // truncation all the way down to i1 is valid.
19717 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19718 return isInt<32>(Imm);
19721 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19722 // Can also use sub to handle negated immediates.
19723 return isInt<32>(Imm);
19726 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19727 if (!VT1.isInteger() || !VT2.isInteger())
19729 unsigned NumBits1 = VT1.getSizeInBits();
19730 unsigned NumBits2 = VT2.getSizeInBits();
19731 return NumBits1 > NumBits2;
19734 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19735 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19736 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19739 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19740 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19741 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19744 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19745 EVT VT1 = Val.getValueType();
19746 if (isZExtFree(VT1, VT2))
19749 if (Val.getOpcode() != ISD::LOAD)
19752 if (!VT1.isSimple() || !VT1.isInteger() ||
19753 !VT2.isSimple() || !VT2.isInteger())
19756 switch (VT1.getSimpleVT().SimpleTy) {
19761 // X86 has 8, 16, and 32-bit zero-extending loads.
19768 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
19771 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19772 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
19775 VT = VT.getScalarType();
19777 if (!VT.isSimple())
19780 switch (VT.getSimpleVT().SimpleTy) {
19791 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19792 // i16 instructions are longer (0x66 prefix) and potentially slower.
19793 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19796 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19797 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19798 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19799 /// are assumed to be legal.
19801 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19803 if (!VT.isSimple())
19806 // Not for i1 vectors
19807 if (VT.getScalarType() == MVT::i1)
19810 // Very little shuffling can be done for 64-bit vectors right now.
19811 if (VT.getSizeInBits() == 64)
19814 // We only care that the types being shuffled are legal. The lowering can
19815 // handle any possible shuffle mask that results.
19816 return isTypeLegal(VT.getSimpleVT());
19820 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19822 // Just delegate to the generic legality, clear masks aren't special.
19823 return isShuffleMaskLegal(Mask, VT);
19826 //===----------------------------------------------------------------------===//
19827 // X86 Scheduler Hooks
19828 //===----------------------------------------------------------------------===//
19830 /// Utility function to emit xbegin specifying the start of an RTM region.
19831 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19832 const TargetInstrInfo *TII) {
19833 DebugLoc DL = MI->getDebugLoc();
19835 const BasicBlock *BB = MBB->getBasicBlock();
19836 MachineFunction::iterator I = MBB;
19839 // For the v = xbegin(), we generate
19850 MachineBasicBlock *thisMBB = MBB;
19851 MachineFunction *MF = MBB->getParent();
19852 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19853 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19854 MF->insert(I, mainMBB);
19855 MF->insert(I, sinkMBB);
19857 // Transfer the remainder of BB and its successor edges to sinkMBB.
19858 sinkMBB->splice(sinkMBB->begin(), MBB,
19859 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19860 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19864 // # fallthrough to mainMBB
19865 // # abortion to sinkMBB
19866 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19867 thisMBB->addSuccessor(mainMBB);
19868 thisMBB->addSuccessor(sinkMBB);
19872 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19873 mainMBB->addSuccessor(sinkMBB);
19876 // EAX is live into the sinkMBB
19877 sinkMBB->addLiveIn(X86::EAX);
19878 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19879 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19882 MI->eraseFromParent();
19886 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19887 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19888 // in the .td file.
19889 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19890 const TargetInstrInfo *TII) {
19892 switch (MI->getOpcode()) {
19893 default: llvm_unreachable("illegal opcode!");
19894 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19895 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19896 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19897 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19898 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19899 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19900 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19901 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19904 DebugLoc dl = MI->getDebugLoc();
19905 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19907 unsigned NumArgs = MI->getNumOperands();
19908 for (unsigned i = 1; i < NumArgs; ++i) {
19909 MachineOperand &Op = MI->getOperand(i);
19910 if (!(Op.isReg() && Op.isImplicit()))
19911 MIB.addOperand(Op);
19913 if (MI->hasOneMemOperand())
19914 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19916 BuildMI(*BB, MI, dl,
19917 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19918 .addReg(X86::XMM0);
19920 MI->eraseFromParent();
19924 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19925 // defs in an instruction pattern
19926 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19927 const TargetInstrInfo *TII) {
19929 switch (MI->getOpcode()) {
19930 default: llvm_unreachable("illegal opcode!");
19931 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19932 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19933 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19934 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19935 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19936 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19937 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19938 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19941 DebugLoc dl = MI->getDebugLoc();
19942 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19944 unsigned NumArgs = MI->getNumOperands(); // remove the results
19945 for (unsigned i = 1; i < NumArgs; ++i) {
19946 MachineOperand &Op = MI->getOperand(i);
19947 if (!(Op.isReg() && Op.isImplicit()))
19948 MIB.addOperand(Op);
19950 if (MI->hasOneMemOperand())
19951 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19953 BuildMI(*BB, MI, dl,
19954 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19957 MI->eraseFromParent();
19961 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19962 const X86Subtarget *Subtarget) {
19963 DebugLoc dl = MI->getDebugLoc();
19964 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19965 // Address into RAX/EAX, other two args into ECX, EDX.
19966 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19967 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19968 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19969 for (int i = 0; i < X86::AddrNumOperands; ++i)
19970 MIB.addOperand(MI->getOperand(i));
19972 unsigned ValOps = X86::AddrNumOperands;
19973 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19974 .addReg(MI->getOperand(ValOps).getReg());
19975 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19976 .addReg(MI->getOperand(ValOps+1).getReg());
19978 // The instruction doesn't actually take any operands though.
19979 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19981 MI->eraseFromParent(); // The pseudo is gone now.
19985 MachineBasicBlock *
19986 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
19987 MachineBasicBlock *MBB) const {
19988 // Emit va_arg instruction on X86-64.
19990 // Operands to this pseudo-instruction:
19991 // 0 ) Output : destination address (reg)
19992 // 1-5) Input : va_list address (addr, i64mem)
19993 // 6 ) ArgSize : Size (in bytes) of vararg type
19994 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19995 // 8 ) Align : Alignment of type
19996 // 9 ) EFLAGS (implicit-def)
19998 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19999 static_assert(X86::AddrNumOperands == 5,
20000 "VAARG_64 assumes 5 address operands");
20002 unsigned DestReg = MI->getOperand(0).getReg();
20003 MachineOperand &Base = MI->getOperand(1);
20004 MachineOperand &Scale = MI->getOperand(2);
20005 MachineOperand &Index = MI->getOperand(3);
20006 MachineOperand &Disp = MI->getOperand(4);
20007 MachineOperand &Segment = MI->getOperand(5);
20008 unsigned ArgSize = MI->getOperand(6).getImm();
20009 unsigned ArgMode = MI->getOperand(7).getImm();
20010 unsigned Align = MI->getOperand(8).getImm();
20012 // Memory Reference
20013 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20014 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20015 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20017 // Machine Information
20018 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20019 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20020 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20021 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20022 DebugLoc DL = MI->getDebugLoc();
20024 // struct va_list {
20027 // i64 overflow_area (address)
20028 // i64 reg_save_area (address)
20030 // sizeof(va_list) = 24
20031 // alignment(va_list) = 8
20033 unsigned TotalNumIntRegs = 6;
20034 unsigned TotalNumXMMRegs = 8;
20035 bool UseGPOffset = (ArgMode == 1);
20036 bool UseFPOffset = (ArgMode == 2);
20037 unsigned MaxOffset = TotalNumIntRegs * 8 +
20038 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20040 /* Align ArgSize to a multiple of 8 */
20041 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20042 bool NeedsAlign = (Align > 8);
20044 MachineBasicBlock *thisMBB = MBB;
20045 MachineBasicBlock *overflowMBB;
20046 MachineBasicBlock *offsetMBB;
20047 MachineBasicBlock *endMBB;
20049 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20050 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20051 unsigned OffsetReg = 0;
20053 if (!UseGPOffset && !UseFPOffset) {
20054 // If we only pull from the overflow region, we don't create a branch.
20055 // We don't need to alter control flow.
20056 OffsetDestReg = 0; // unused
20057 OverflowDestReg = DestReg;
20059 offsetMBB = nullptr;
20060 overflowMBB = thisMBB;
20063 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20064 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20065 // If not, pull from overflow_area. (branch to overflowMBB)
20070 // offsetMBB overflowMBB
20075 // Registers for the PHI in endMBB
20076 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20077 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20079 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20080 MachineFunction *MF = MBB->getParent();
20081 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20082 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20083 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20085 MachineFunction::iterator MBBIter = MBB;
20088 // Insert the new basic blocks
20089 MF->insert(MBBIter, offsetMBB);
20090 MF->insert(MBBIter, overflowMBB);
20091 MF->insert(MBBIter, endMBB);
20093 // Transfer the remainder of MBB and its successor edges to endMBB.
20094 endMBB->splice(endMBB->begin(), thisMBB,
20095 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20096 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20098 // Make offsetMBB and overflowMBB successors of thisMBB
20099 thisMBB->addSuccessor(offsetMBB);
20100 thisMBB->addSuccessor(overflowMBB);
20102 // endMBB is a successor of both offsetMBB and overflowMBB
20103 offsetMBB->addSuccessor(endMBB);
20104 overflowMBB->addSuccessor(endMBB);
20106 // Load the offset value into a register
20107 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20108 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20112 .addDisp(Disp, UseFPOffset ? 4 : 0)
20113 .addOperand(Segment)
20114 .setMemRefs(MMOBegin, MMOEnd);
20116 // Check if there is enough room left to pull this argument.
20117 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20119 .addImm(MaxOffset + 8 - ArgSizeA8);
20121 // Branch to "overflowMBB" if offset >= max
20122 // Fall through to "offsetMBB" otherwise
20123 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20124 .addMBB(overflowMBB);
20127 // In offsetMBB, emit code to use the reg_save_area.
20129 assert(OffsetReg != 0);
20131 // Read the reg_save_area address.
20132 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20133 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20138 .addOperand(Segment)
20139 .setMemRefs(MMOBegin, MMOEnd);
20141 // Zero-extend the offset
20142 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20143 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20146 .addImm(X86::sub_32bit);
20148 // Add the offset to the reg_save_area to get the final address.
20149 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20150 .addReg(OffsetReg64)
20151 .addReg(RegSaveReg);
20153 // Compute the offset for the next argument
20154 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20155 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20157 .addImm(UseFPOffset ? 16 : 8);
20159 // Store it back into the va_list.
20160 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20164 .addDisp(Disp, UseFPOffset ? 4 : 0)
20165 .addOperand(Segment)
20166 .addReg(NextOffsetReg)
20167 .setMemRefs(MMOBegin, MMOEnd);
20170 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20175 // Emit code to use overflow area
20178 // Load the overflow_area address into a register.
20179 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20180 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20185 .addOperand(Segment)
20186 .setMemRefs(MMOBegin, MMOEnd);
20188 // If we need to align it, do so. Otherwise, just copy the address
20189 // to OverflowDestReg.
20191 // Align the overflow address
20192 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20193 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20195 // aligned_addr = (addr + (align-1)) & ~(align-1)
20196 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20197 .addReg(OverflowAddrReg)
20200 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20202 .addImm(~(uint64_t)(Align-1));
20204 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20205 .addReg(OverflowAddrReg);
20208 // Compute the next overflow address after this argument.
20209 // (the overflow address should be kept 8-byte aligned)
20210 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20211 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20212 .addReg(OverflowDestReg)
20213 .addImm(ArgSizeA8);
20215 // Store the new overflow address.
20216 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20221 .addOperand(Segment)
20222 .addReg(NextAddrReg)
20223 .setMemRefs(MMOBegin, MMOEnd);
20225 // If we branched, emit the PHI to the front of endMBB.
20227 BuildMI(*endMBB, endMBB->begin(), DL,
20228 TII->get(X86::PHI), DestReg)
20229 .addReg(OffsetDestReg).addMBB(offsetMBB)
20230 .addReg(OverflowDestReg).addMBB(overflowMBB);
20233 // Erase the pseudo instruction
20234 MI->eraseFromParent();
20239 MachineBasicBlock *
20240 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20242 MachineBasicBlock *MBB) const {
20243 // Emit code to save XMM registers to the stack. The ABI says that the
20244 // number of registers to save is given in %al, so it's theoretically
20245 // possible to do an indirect jump trick to avoid saving all of them,
20246 // however this code takes a simpler approach and just executes all
20247 // of the stores if %al is non-zero. It's less code, and it's probably
20248 // easier on the hardware branch predictor, and stores aren't all that
20249 // expensive anyway.
20251 // Create the new basic blocks. One block contains all the XMM stores,
20252 // and one block is the final destination regardless of whether any
20253 // stores were performed.
20254 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20255 MachineFunction *F = MBB->getParent();
20256 MachineFunction::iterator MBBIter = MBB;
20258 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20259 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20260 F->insert(MBBIter, XMMSaveMBB);
20261 F->insert(MBBIter, EndMBB);
20263 // Transfer the remainder of MBB and its successor edges to EndMBB.
20264 EndMBB->splice(EndMBB->begin(), MBB,
20265 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20266 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20268 // The original block will now fall through to the XMM save block.
20269 MBB->addSuccessor(XMMSaveMBB);
20270 // The XMMSaveMBB will fall through to the end block.
20271 XMMSaveMBB->addSuccessor(EndMBB);
20273 // Now add the instructions.
20274 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20275 DebugLoc DL = MI->getDebugLoc();
20277 unsigned CountReg = MI->getOperand(0).getReg();
20278 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20279 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20281 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20282 // If %al is 0, branch around the XMM save block.
20283 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20284 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20285 MBB->addSuccessor(EndMBB);
20288 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20289 // that was just emitted, but clearly shouldn't be "saved".
20290 assert((MI->getNumOperands() <= 3 ||
20291 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20292 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20293 && "Expected last argument to be EFLAGS");
20294 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20295 // In the XMM save block, save all the XMM argument registers.
20296 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20297 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20298 MachineMemOperand *MMO = F->getMachineMemOperand(
20299 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20300 MachineMemOperand::MOStore,
20301 /*Size=*/16, /*Align=*/16);
20302 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20303 .addFrameIndex(RegSaveFrameIndex)
20304 .addImm(/*Scale=*/1)
20305 .addReg(/*IndexReg=*/0)
20306 .addImm(/*Disp=*/Offset)
20307 .addReg(/*Segment=*/0)
20308 .addReg(MI->getOperand(i).getReg())
20309 .addMemOperand(MMO);
20312 MI->eraseFromParent(); // The pseudo instruction is gone now.
20317 // The EFLAGS operand of SelectItr might be missing a kill marker
20318 // because there were multiple uses of EFLAGS, and ISel didn't know
20319 // which to mark. Figure out whether SelectItr should have had a
20320 // kill marker, and set it if it should. Returns the correct kill
20322 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20323 MachineBasicBlock* BB,
20324 const TargetRegisterInfo* TRI) {
20325 // Scan forward through BB for a use/def of EFLAGS.
20326 MachineBasicBlock::iterator miI(std::next(SelectItr));
20327 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20328 const MachineInstr& mi = *miI;
20329 if (mi.readsRegister(X86::EFLAGS))
20331 if (mi.definesRegister(X86::EFLAGS))
20332 break; // Should have kill-flag - update below.
20335 // If we hit the end of the block, check whether EFLAGS is live into a
20337 if (miI == BB->end()) {
20338 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20339 sEnd = BB->succ_end();
20340 sItr != sEnd; ++sItr) {
20341 MachineBasicBlock* succ = *sItr;
20342 if (succ->isLiveIn(X86::EFLAGS))
20347 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20348 // out. SelectMI should have a kill flag on EFLAGS.
20349 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20353 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20354 // together with other CMOV pseudo-opcodes into a single basic-block with
20355 // conditional jump around it.
20356 static bool isCMOVPseudo(MachineInstr *MI) {
20357 switch (MI->getOpcode()) {
20358 case X86::CMOV_FR32:
20359 case X86::CMOV_FR64:
20360 case X86::CMOV_GR8:
20361 case X86::CMOV_GR16:
20362 case X86::CMOV_GR32:
20363 case X86::CMOV_RFP32:
20364 case X86::CMOV_RFP64:
20365 case X86::CMOV_RFP80:
20366 case X86::CMOV_V2F64:
20367 case X86::CMOV_V2I64:
20368 case X86::CMOV_V4F32:
20369 case X86::CMOV_V4F64:
20370 case X86::CMOV_V4I64:
20371 case X86::CMOV_V16F32:
20372 case X86::CMOV_V8F32:
20373 case X86::CMOV_V8F64:
20374 case X86::CMOV_V8I64:
20375 case X86::CMOV_V8I1:
20376 case X86::CMOV_V16I1:
20377 case X86::CMOV_V32I1:
20378 case X86::CMOV_V64I1:
20386 MachineBasicBlock *
20387 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20388 MachineBasicBlock *BB) const {
20389 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20390 DebugLoc DL = MI->getDebugLoc();
20392 // To "insert" a SELECT_CC instruction, we actually have to insert the
20393 // diamond control-flow pattern. The incoming instruction knows the
20394 // destination vreg to set, the condition code register to branch on, the
20395 // true/false values to select between, and a branch opcode to use.
20396 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20397 MachineFunction::iterator It = BB;
20403 // cmpTY ccX, r1, r2
20405 // fallthrough --> copy0MBB
20406 MachineBasicBlock *thisMBB = BB;
20407 MachineFunction *F = BB->getParent();
20409 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20410 // as described above, by inserting a BB, and then making a PHI at the join
20411 // point to select the true and false operands of the CMOV in the PHI.
20413 // The code also handles two different cases of multiple CMOV opcodes
20417 // In this case, there are multiple CMOVs in a row, all which are based on
20418 // the same condition setting (or the exact opposite condition setting).
20419 // In this case we can lower all the CMOVs using a single inserted BB, and
20420 // then make a number of PHIs at the join point to model the CMOVs. The only
20421 // trickiness here, is that in a case like:
20423 // t2 = CMOV cond1 t1, f1
20424 // t3 = CMOV cond1 t2, f2
20426 // when rewriting this into PHIs, we have to perform some renaming on the
20427 // temps since you cannot have a PHI operand refer to a PHI result earlier
20428 // in the same block. The "simple" but wrong lowering would be:
20430 // t2 = PHI t1(BB1), f1(BB2)
20431 // t3 = PHI t2(BB1), f2(BB2)
20433 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20434 // renaming is to note that on the path through BB1, t2 is really just a
20435 // copy of t1, and do that renaming, properly generating:
20437 // t2 = PHI t1(BB1), f1(BB2)
20438 // t3 = PHI t1(BB1), f2(BB2)
20440 // Case 2, we lower cascaded CMOVs such as
20442 // (CMOV (CMOV F, T, cc1), T, cc2)
20444 // to two successives branches. For that, we look for another CMOV as the
20445 // following instruction.
20447 // Without this, we would add a PHI between the two jumps, which ends up
20448 // creating a few copies all around. For instance, for
20450 // (sitofp (zext (fcmp une)))
20452 // we would generate:
20454 // ucomiss %xmm1, %xmm0
20455 // movss <1.0f>, %xmm0
20456 // movaps %xmm0, %xmm1
20458 // xorps %xmm1, %xmm1
20461 // movaps %xmm1, %xmm0
20465 // because this custom-inserter would have generated:
20477 // A: X = ...; Y = ...
20479 // C: Z = PHI [X, A], [Y, B]
20481 // E: PHI [X, C], [Z, D]
20483 // If we lower both CMOVs in a single step, we can instead generate:
20495 // A: X = ...; Y = ...
20497 // E: PHI [X, A], [X, C], [Y, D]
20499 // Which, in our sitofp/fcmp example, gives us something like:
20501 // ucomiss %xmm1, %xmm0
20502 // movss <1.0f>, %xmm0
20505 // xorps %xmm0, %xmm0
20509 MachineInstr *CascadedCMOV = nullptr;
20510 MachineInstr *LastCMOV = MI;
20511 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20512 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20513 MachineBasicBlock::iterator NextMIIt =
20514 std::next(MachineBasicBlock::iterator(MI));
20516 // Check for case 1, where there are multiple CMOVs with the same condition
20517 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20518 // number of jumps the most.
20520 if (isCMOVPseudo(MI)) {
20521 // See if we have a string of CMOVS with the same condition.
20522 while (NextMIIt != BB->end() &&
20523 isCMOVPseudo(NextMIIt) &&
20524 (NextMIIt->getOperand(3).getImm() == CC ||
20525 NextMIIt->getOperand(3).getImm() == OppCC)) {
20526 LastCMOV = &*NextMIIt;
20531 // This checks for case 2, but only do this if we didn't already find
20532 // case 1, as indicated by LastCMOV == MI.
20533 if (LastCMOV == MI &&
20534 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20535 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20536 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20537 CascadedCMOV = &*NextMIIt;
20540 MachineBasicBlock *jcc1MBB = nullptr;
20542 // If we have a cascaded CMOV, we lower it to two successive branches to
20543 // the same block. EFLAGS is used by both, so mark it as live in the second.
20544 if (CascadedCMOV) {
20545 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20546 F->insert(It, jcc1MBB);
20547 jcc1MBB->addLiveIn(X86::EFLAGS);
20550 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20551 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20552 F->insert(It, copy0MBB);
20553 F->insert(It, sinkMBB);
20555 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20556 // live into the sink and copy blocks.
20557 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20559 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20560 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20561 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20562 copy0MBB->addLiveIn(X86::EFLAGS);
20563 sinkMBB->addLiveIn(X86::EFLAGS);
20566 // Transfer the remainder of BB and its successor edges to sinkMBB.
20567 sinkMBB->splice(sinkMBB->begin(), BB,
20568 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20569 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20571 // Add the true and fallthrough blocks as its successors.
20572 if (CascadedCMOV) {
20573 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20574 BB->addSuccessor(jcc1MBB);
20576 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20577 // jump to the sinkMBB.
20578 jcc1MBB->addSuccessor(copy0MBB);
20579 jcc1MBB->addSuccessor(sinkMBB);
20581 BB->addSuccessor(copy0MBB);
20584 // The true block target of the first (or only) branch is always sinkMBB.
20585 BB->addSuccessor(sinkMBB);
20587 // Create the conditional branch instruction.
20588 unsigned Opc = X86::GetCondBranchFromCond(CC);
20589 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20591 if (CascadedCMOV) {
20592 unsigned Opc2 = X86::GetCondBranchFromCond(
20593 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20594 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20598 // %FalseValue = ...
20599 // # fallthrough to sinkMBB
20600 copy0MBB->addSuccessor(sinkMBB);
20603 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20605 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20606 MachineBasicBlock::iterator MIItEnd =
20607 std::next(MachineBasicBlock::iterator(LastCMOV));
20608 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20609 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20610 MachineInstrBuilder MIB;
20612 // As we are creating the PHIs, we have to be careful if there is more than
20613 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20614 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20615 // That also means that PHI construction must work forward from earlier to
20616 // later, and that the code must maintain a mapping from earlier PHI's
20617 // destination registers, and the registers that went into the PHI.
20619 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20620 unsigned DestReg = MIIt->getOperand(0).getReg();
20621 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20622 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20624 // If this CMOV we are generating is the opposite condition from
20625 // the jump we generated, then we have to swap the operands for the
20626 // PHI that is going to be generated.
20627 if (MIIt->getOperand(3).getImm() == OppCC)
20628 std::swap(Op1Reg, Op2Reg);
20630 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20631 Op1Reg = RegRewriteTable[Op1Reg].first;
20633 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20634 Op2Reg = RegRewriteTable[Op2Reg].second;
20636 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20637 TII->get(X86::PHI), DestReg)
20638 .addReg(Op1Reg).addMBB(copy0MBB)
20639 .addReg(Op2Reg).addMBB(thisMBB);
20641 // Add this PHI to the rewrite table.
20642 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20645 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20646 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20647 if (CascadedCMOV) {
20648 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20649 // Copy the PHI result to the register defined by the second CMOV.
20650 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20651 DL, TII->get(TargetOpcode::COPY),
20652 CascadedCMOV->getOperand(0).getReg())
20653 .addReg(MI->getOperand(0).getReg());
20654 CascadedCMOV->eraseFromParent();
20657 // Now remove the CMOV(s).
20658 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20659 (MIIt++)->eraseFromParent();
20664 MachineBasicBlock *
20665 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20666 MachineBasicBlock *BB) const {
20667 // Combine the following atomic floating-point modification pattern:
20668 // a.store(reg OP a.load(acquire), release)
20669 // Transform them into:
20670 // OPss (%gpr), %xmm
20671 // movss %xmm, (%gpr)
20672 // Or sd equivalent for 64-bit operations.
20674 switch (MI->getOpcode()) {
20675 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20676 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20677 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20679 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20680 DebugLoc DL = MI->getDebugLoc();
20681 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20682 unsigned MSrc = MI->getOperand(0).getReg();
20683 unsigned VSrc = MI->getOperand(5).getReg();
20684 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20685 .addReg(/*Base=*/MSrc)
20686 .addImm(/*Scale=*/1)
20687 .addReg(/*Index=*/0)
20690 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20691 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20693 .addReg(/*Base=*/MSrc)
20694 .addImm(/*Scale=*/1)
20695 .addReg(/*Index=*/0)
20696 .addImm(/*Disp=*/0)
20697 .addReg(/*Segment=*/0);
20698 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20699 MI->eraseFromParent(); // The pseudo instruction is gone now.
20703 MachineBasicBlock *
20704 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20705 MachineBasicBlock *BB) const {
20706 MachineFunction *MF = BB->getParent();
20707 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20708 DebugLoc DL = MI->getDebugLoc();
20709 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20711 assert(MF->shouldSplitStack());
20713 const bool Is64Bit = Subtarget->is64Bit();
20714 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20716 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20717 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20720 // ... [Till the alloca]
20721 // If stacklet is not large enough, jump to mallocMBB
20724 // Allocate by subtracting from RSP
20725 // Jump to continueMBB
20728 // Allocate by call to runtime
20732 // [rest of original BB]
20735 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20736 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20737 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20739 MachineRegisterInfo &MRI = MF->getRegInfo();
20740 const TargetRegisterClass *AddrRegClass =
20741 getRegClassFor(getPointerTy(MF->getDataLayout()));
20743 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20744 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20745 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20746 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20747 sizeVReg = MI->getOperand(1).getReg(),
20748 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20750 MachineFunction::iterator MBBIter = BB;
20753 MF->insert(MBBIter, bumpMBB);
20754 MF->insert(MBBIter, mallocMBB);
20755 MF->insert(MBBIter, continueMBB);
20757 continueMBB->splice(continueMBB->begin(), BB,
20758 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20759 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20761 // Add code to the main basic block to check if the stack limit has been hit,
20762 // and if so, jump to mallocMBB otherwise to bumpMBB.
20763 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20764 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20765 .addReg(tmpSPVReg).addReg(sizeVReg);
20766 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20767 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20768 .addReg(SPLimitVReg);
20769 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20771 // bumpMBB simply decreases the stack pointer, since we know the current
20772 // stacklet has enough space.
20773 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20774 .addReg(SPLimitVReg);
20775 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20776 .addReg(SPLimitVReg);
20777 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20779 // Calls into a routine in libgcc to allocate more space from the heap.
20780 const uint32_t *RegMask =
20781 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
20783 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20785 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20786 .addExternalSymbol("__morestack_allocate_stack_space")
20787 .addRegMask(RegMask)
20788 .addReg(X86::RDI, RegState::Implicit)
20789 .addReg(X86::RAX, RegState::ImplicitDefine);
20790 } else if (Is64Bit) {
20791 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20793 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20794 .addExternalSymbol("__morestack_allocate_stack_space")
20795 .addRegMask(RegMask)
20796 .addReg(X86::EDI, RegState::Implicit)
20797 .addReg(X86::EAX, RegState::ImplicitDefine);
20799 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20801 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20802 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20803 .addExternalSymbol("__morestack_allocate_stack_space")
20804 .addRegMask(RegMask)
20805 .addReg(X86::EAX, RegState::ImplicitDefine);
20809 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20812 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20813 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20814 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20816 // Set up the CFG correctly.
20817 BB->addSuccessor(bumpMBB);
20818 BB->addSuccessor(mallocMBB);
20819 mallocMBB->addSuccessor(continueMBB);
20820 bumpMBB->addSuccessor(continueMBB);
20822 // Take care of the PHI nodes.
20823 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20824 MI->getOperand(0).getReg())
20825 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20826 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20828 // Delete the original pseudo instruction.
20829 MI->eraseFromParent();
20832 return continueMBB;
20835 MachineBasicBlock *
20836 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20837 MachineBasicBlock *BB) const {
20838 DebugLoc DL = MI->getDebugLoc();
20840 assert(!Subtarget->isTargetMachO());
20842 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
20845 MI->eraseFromParent(); // The pseudo instruction is gone now.
20849 MachineBasicBlock *
20850 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20851 MachineBasicBlock *BB) const {
20852 // This is pretty easy. We're taking the value that we received from
20853 // our load from the relocation, sticking it in either RDI (x86-64)
20854 // or EAX and doing an indirect call. The return value will then
20855 // be in the normal return register.
20856 MachineFunction *F = BB->getParent();
20857 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20858 DebugLoc DL = MI->getDebugLoc();
20860 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20861 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20863 // Get a register mask for the lowered call.
20864 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20865 // proper register mask.
20866 const uint32_t *RegMask =
20867 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
20868 if (Subtarget->is64Bit()) {
20869 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20870 TII->get(X86::MOV64rm), X86::RDI)
20872 .addImm(0).addReg(0)
20873 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20874 MI->getOperand(3).getTargetFlags())
20876 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20877 addDirectMem(MIB, X86::RDI);
20878 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20879 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20880 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20881 TII->get(X86::MOV32rm), X86::EAX)
20883 .addImm(0).addReg(0)
20884 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20885 MI->getOperand(3).getTargetFlags())
20887 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20888 addDirectMem(MIB, X86::EAX);
20889 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20891 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20892 TII->get(X86::MOV32rm), X86::EAX)
20893 .addReg(TII->getGlobalBaseReg(F))
20894 .addImm(0).addReg(0)
20895 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20896 MI->getOperand(3).getTargetFlags())
20898 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20899 addDirectMem(MIB, X86::EAX);
20900 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20903 MI->eraseFromParent(); // The pseudo instruction is gone now.
20907 MachineBasicBlock *
20908 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20909 MachineBasicBlock *MBB) const {
20910 DebugLoc DL = MI->getDebugLoc();
20911 MachineFunction *MF = MBB->getParent();
20912 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20913 MachineRegisterInfo &MRI = MF->getRegInfo();
20915 const BasicBlock *BB = MBB->getBasicBlock();
20916 MachineFunction::iterator I = MBB;
20919 // Memory Reference
20920 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20921 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20924 unsigned MemOpndSlot = 0;
20926 unsigned CurOp = 0;
20928 DstReg = MI->getOperand(CurOp++).getReg();
20929 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20930 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20931 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20932 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20934 MemOpndSlot = CurOp;
20936 MVT PVT = getPointerTy(MF->getDataLayout());
20937 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20938 "Invalid Pointer Size!");
20940 // For v = setjmp(buf), we generate
20943 // buf[LabelOffset] = restoreMBB
20944 // SjLjSetup restoreMBB
20950 // v = phi(main, restore)
20953 // if base pointer being used, load it from frame
20956 MachineBasicBlock *thisMBB = MBB;
20957 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20958 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20959 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20960 MF->insert(I, mainMBB);
20961 MF->insert(I, sinkMBB);
20962 MF->push_back(restoreMBB);
20964 MachineInstrBuilder MIB;
20966 // Transfer the remainder of BB and its successor edges to sinkMBB.
20967 sinkMBB->splice(sinkMBB->begin(), MBB,
20968 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20969 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20972 unsigned PtrStoreOpc = 0;
20973 unsigned LabelReg = 0;
20974 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20975 Reloc::Model RM = MF->getTarget().getRelocationModel();
20976 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20977 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20979 // Prepare IP either in reg or imm.
20980 if (!UseImmLabel) {
20981 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20982 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20983 LabelReg = MRI.createVirtualRegister(PtrRC);
20984 if (Subtarget->is64Bit()) {
20985 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20989 .addMBB(restoreMBB)
20992 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20993 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20994 .addReg(XII->getGlobalBaseReg(MF))
20997 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21001 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21003 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21004 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21005 if (i == X86::AddrDisp)
21006 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21008 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21011 MIB.addReg(LabelReg);
21013 MIB.addMBB(restoreMBB);
21014 MIB.setMemRefs(MMOBegin, MMOEnd);
21016 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21017 .addMBB(restoreMBB);
21019 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21020 MIB.addRegMask(RegInfo->getNoPreservedMask());
21021 thisMBB->addSuccessor(mainMBB);
21022 thisMBB->addSuccessor(restoreMBB);
21026 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21027 mainMBB->addSuccessor(sinkMBB);
21030 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21031 TII->get(X86::PHI), DstReg)
21032 .addReg(mainDstReg).addMBB(mainMBB)
21033 .addReg(restoreDstReg).addMBB(restoreMBB);
21036 if (RegInfo->hasBasePointer(*MF)) {
21037 const bool Uses64BitFramePtr =
21038 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21039 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21040 X86FI->setRestoreBasePointer(MF);
21041 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21042 unsigned BasePtr = RegInfo->getBaseRegister();
21043 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21044 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21045 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21046 .setMIFlag(MachineInstr::FrameSetup);
21048 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21049 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21050 restoreMBB->addSuccessor(sinkMBB);
21052 MI->eraseFromParent();
21056 MachineBasicBlock *
21057 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21058 MachineBasicBlock *MBB) const {
21059 DebugLoc DL = MI->getDebugLoc();
21060 MachineFunction *MF = MBB->getParent();
21061 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21062 MachineRegisterInfo &MRI = MF->getRegInfo();
21064 // Memory Reference
21065 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21066 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21068 MVT PVT = getPointerTy(MF->getDataLayout());
21069 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21070 "Invalid Pointer Size!");
21072 const TargetRegisterClass *RC =
21073 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21074 unsigned Tmp = MRI.createVirtualRegister(RC);
21075 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21076 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21077 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21078 unsigned SP = RegInfo->getStackRegister();
21080 MachineInstrBuilder MIB;
21082 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21083 const int64_t SPOffset = 2 * PVT.getStoreSize();
21085 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21086 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21089 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21090 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21091 MIB.addOperand(MI->getOperand(i));
21092 MIB.setMemRefs(MMOBegin, MMOEnd);
21094 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21095 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21096 if (i == X86::AddrDisp)
21097 MIB.addDisp(MI->getOperand(i), LabelOffset);
21099 MIB.addOperand(MI->getOperand(i));
21101 MIB.setMemRefs(MMOBegin, MMOEnd);
21103 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21104 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21105 if (i == X86::AddrDisp)
21106 MIB.addDisp(MI->getOperand(i), SPOffset);
21108 MIB.addOperand(MI->getOperand(i));
21110 MIB.setMemRefs(MMOBegin, MMOEnd);
21112 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21114 MI->eraseFromParent();
21118 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21119 // accumulator loops. Writing back to the accumulator allows the coalescer
21120 // to remove extra copies in the loop.
21121 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21122 MachineBasicBlock *
21123 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21124 MachineBasicBlock *MBB) const {
21125 MachineOperand &AddendOp = MI->getOperand(3);
21127 // Bail out early if the addend isn't a register - we can't switch these.
21128 if (!AddendOp.isReg())
21131 MachineFunction &MF = *MBB->getParent();
21132 MachineRegisterInfo &MRI = MF.getRegInfo();
21134 // Check whether the addend is defined by a PHI:
21135 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21136 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21137 if (!AddendDef.isPHI())
21140 // Look for the following pattern:
21142 // %addend = phi [%entry, 0], [%loop, %result]
21144 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21148 // %addend = phi [%entry, 0], [%loop, %result]
21150 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21152 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21153 assert(AddendDef.getOperand(i).isReg());
21154 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21155 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21156 if (&PHISrcInst == MI) {
21157 // Found a matching instruction.
21158 unsigned NewFMAOpc = 0;
21159 switch (MI->getOpcode()) {
21160 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21161 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21162 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21163 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21164 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21165 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21166 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21167 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21168 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21169 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21170 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21171 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21172 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21173 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21174 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21175 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21176 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21177 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21178 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21179 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21181 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21182 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21183 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21184 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21185 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21186 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21187 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21188 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21189 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21190 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21191 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21192 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21193 default: llvm_unreachable("Unrecognized FMA variant.");
21196 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21197 MachineInstrBuilder MIB =
21198 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21199 .addOperand(MI->getOperand(0))
21200 .addOperand(MI->getOperand(3))
21201 .addOperand(MI->getOperand(2))
21202 .addOperand(MI->getOperand(1));
21203 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21204 MI->eraseFromParent();
21211 MachineBasicBlock *
21212 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21213 MachineBasicBlock *BB) const {
21214 switch (MI->getOpcode()) {
21215 default: llvm_unreachable("Unexpected instr type to insert");
21216 case X86::TAILJMPd64:
21217 case X86::TAILJMPr64:
21218 case X86::TAILJMPm64:
21219 case X86::TAILJMPd64_REX:
21220 case X86::TAILJMPr64_REX:
21221 case X86::TAILJMPm64_REX:
21222 llvm_unreachable("TAILJMP64 would not be touched here.");
21223 case X86::TCRETURNdi64:
21224 case X86::TCRETURNri64:
21225 case X86::TCRETURNmi64:
21227 case X86::WIN_ALLOCA:
21228 return EmitLoweredWinAlloca(MI, BB);
21229 case X86::SEG_ALLOCA_32:
21230 case X86::SEG_ALLOCA_64:
21231 return EmitLoweredSegAlloca(MI, BB);
21232 case X86::TLSCall_32:
21233 case X86::TLSCall_64:
21234 return EmitLoweredTLSCall(MI, BB);
21235 case X86::CMOV_FR32:
21236 case X86::CMOV_FR64:
21237 case X86::CMOV_GR8:
21238 case X86::CMOV_GR16:
21239 case X86::CMOV_GR32:
21240 case X86::CMOV_RFP32:
21241 case X86::CMOV_RFP64:
21242 case X86::CMOV_RFP80:
21243 case X86::CMOV_V2F64:
21244 case X86::CMOV_V2I64:
21245 case X86::CMOV_V4F32:
21246 case X86::CMOV_V4F64:
21247 case X86::CMOV_V4I64:
21248 case X86::CMOV_V16F32:
21249 case X86::CMOV_V8F32:
21250 case X86::CMOV_V8F64:
21251 case X86::CMOV_V8I64:
21252 case X86::CMOV_V8I1:
21253 case X86::CMOV_V16I1:
21254 case X86::CMOV_V32I1:
21255 case X86::CMOV_V64I1:
21256 return EmitLoweredSelect(MI, BB);
21258 case X86::RELEASE_FADD32mr:
21259 case X86::RELEASE_FADD64mr:
21260 return EmitLoweredAtomicFP(MI, BB);
21262 case X86::FP32_TO_INT16_IN_MEM:
21263 case X86::FP32_TO_INT32_IN_MEM:
21264 case X86::FP32_TO_INT64_IN_MEM:
21265 case X86::FP64_TO_INT16_IN_MEM:
21266 case X86::FP64_TO_INT32_IN_MEM:
21267 case X86::FP64_TO_INT64_IN_MEM:
21268 case X86::FP80_TO_INT16_IN_MEM:
21269 case X86::FP80_TO_INT32_IN_MEM:
21270 case X86::FP80_TO_INT64_IN_MEM: {
21271 MachineFunction *F = BB->getParent();
21272 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21273 DebugLoc DL = MI->getDebugLoc();
21275 // Change the floating point control register to use "round towards zero"
21276 // mode when truncating to an integer value.
21277 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21278 addFrameReference(BuildMI(*BB, MI, DL,
21279 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21281 // Load the old value of the high byte of the control word...
21283 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21284 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21287 // Set the high part to be round to zero...
21288 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21291 // Reload the modified control word now...
21292 addFrameReference(BuildMI(*BB, MI, DL,
21293 TII->get(X86::FLDCW16m)), CWFrameIdx);
21295 // Restore the memory image of control word to original value
21296 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21299 // Get the X86 opcode to use.
21301 switch (MI->getOpcode()) {
21302 default: llvm_unreachable("illegal opcode!");
21303 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21304 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21305 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21306 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21307 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21308 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21309 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21310 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21311 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21315 MachineOperand &Op = MI->getOperand(0);
21317 AM.BaseType = X86AddressMode::RegBase;
21318 AM.Base.Reg = Op.getReg();
21320 AM.BaseType = X86AddressMode::FrameIndexBase;
21321 AM.Base.FrameIndex = Op.getIndex();
21323 Op = MI->getOperand(1);
21325 AM.Scale = Op.getImm();
21326 Op = MI->getOperand(2);
21328 AM.IndexReg = Op.getImm();
21329 Op = MI->getOperand(3);
21330 if (Op.isGlobal()) {
21331 AM.GV = Op.getGlobal();
21333 AM.Disp = Op.getImm();
21335 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21336 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21338 // Reload the original control word now.
21339 addFrameReference(BuildMI(*BB, MI, DL,
21340 TII->get(X86::FLDCW16m)), CWFrameIdx);
21342 MI->eraseFromParent(); // The pseudo instruction is gone now.
21345 // String/text processing lowering.
21346 case X86::PCMPISTRM128REG:
21347 case X86::VPCMPISTRM128REG:
21348 case X86::PCMPISTRM128MEM:
21349 case X86::VPCMPISTRM128MEM:
21350 case X86::PCMPESTRM128REG:
21351 case X86::VPCMPESTRM128REG:
21352 case X86::PCMPESTRM128MEM:
21353 case X86::VPCMPESTRM128MEM:
21354 assert(Subtarget->hasSSE42() &&
21355 "Target must have SSE4.2 or AVX features enabled");
21356 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21358 // String/text processing lowering.
21359 case X86::PCMPISTRIREG:
21360 case X86::VPCMPISTRIREG:
21361 case X86::PCMPISTRIMEM:
21362 case X86::VPCMPISTRIMEM:
21363 case X86::PCMPESTRIREG:
21364 case X86::VPCMPESTRIREG:
21365 case X86::PCMPESTRIMEM:
21366 case X86::VPCMPESTRIMEM:
21367 assert(Subtarget->hasSSE42() &&
21368 "Target must have SSE4.2 or AVX features enabled");
21369 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21371 // Thread synchronization.
21373 return EmitMonitor(MI, BB, Subtarget);
21377 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21379 case X86::VASTART_SAVE_XMM_REGS:
21380 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21382 case X86::VAARG_64:
21383 return EmitVAARG64WithCustomInserter(MI, BB);
21385 case X86::EH_SjLj_SetJmp32:
21386 case X86::EH_SjLj_SetJmp64:
21387 return emitEHSjLjSetJmp(MI, BB);
21389 case X86::EH_SjLj_LongJmp32:
21390 case X86::EH_SjLj_LongJmp64:
21391 return emitEHSjLjLongJmp(MI, BB);
21393 case TargetOpcode::STATEPOINT:
21394 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21395 // this point in the process. We diverge later.
21396 return emitPatchPoint(MI, BB);
21398 case TargetOpcode::STACKMAP:
21399 case TargetOpcode::PATCHPOINT:
21400 return emitPatchPoint(MI, BB);
21402 case X86::VFMADDPDr213r:
21403 case X86::VFMADDPSr213r:
21404 case X86::VFMADDSDr213r:
21405 case X86::VFMADDSSr213r:
21406 case X86::VFMSUBPDr213r:
21407 case X86::VFMSUBPSr213r:
21408 case X86::VFMSUBSDr213r:
21409 case X86::VFMSUBSSr213r:
21410 case X86::VFNMADDPDr213r:
21411 case X86::VFNMADDPSr213r:
21412 case X86::VFNMADDSDr213r:
21413 case X86::VFNMADDSSr213r:
21414 case X86::VFNMSUBPDr213r:
21415 case X86::VFNMSUBPSr213r:
21416 case X86::VFNMSUBSDr213r:
21417 case X86::VFNMSUBSSr213r:
21418 case X86::VFMADDSUBPDr213r:
21419 case X86::VFMADDSUBPSr213r:
21420 case X86::VFMSUBADDPDr213r:
21421 case X86::VFMSUBADDPSr213r:
21422 case X86::VFMADDPDr213rY:
21423 case X86::VFMADDPSr213rY:
21424 case X86::VFMSUBPDr213rY:
21425 case X86::VFMSUBPSr213rY:
21426 case X86::VFNMADDPDr213rY:
21427 case X86::VFNMADDPSr213rY:
21428 case X86::VFNMSUBPDr213rY:
21429 case X86::VFNMSUBPSr213rY:
21430 case X86::VFMADDSUBPDr213rY:
21431 case X86::VFMADDSUBPSr213rY:
21432 case X86::VFMSUBADDPDr213rY:
21433 case X86::VFMSUBADDPSr213rY:
21434 return emitFMA3Instr(MI, BB);
21438 //===----------------------------------------------------------------------===//
21439 // X86 Optimization Hooks
21440 //===----------------------------------------------------------------------===//
21442 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21445 const SelectionDAG &DAG,
21446 unsigned Depth) const {
21447 unsigned BitWidth = KnownZero.getBitWidth();
21448 unsigned Opc = Op.getOpcode();
21449 assert((Opc >= ISD::BUILTIN_OP_END ||
21450 Opc == ISD::INTRINSIC_WO_CHAIN ||
21451 Opc == ISD::INTRINSIC_W_CHAIN ||
21452 Opc == ISD::INTRINSIC_VOID) &&
21453 "Should use MaskedValueIsZero if you don't know whether Op"
21454 " is a target node!");
21456 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21470 // These nodes' second result is a boolean.
21471 if (Op.getResNo() == 0)
21474 case X86ISD::SETCC:
21475 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21477 case ISD::INTRINSIC_WO_CHAIN: {
21478 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21479 unsigned NumLoBits = 0;
21482 case Intrinsic::x86_sse_movmsk_ps:
21483 case Intrinsic::x86_avx_movmsk_ps_256:
21484 case Intrinsic::x86_sse2_movmsk_pd:
21485 case Intrinsic::x86_avx_movmsk_pd_256:
21486 case Intrinsic::x86_mmx_pmovmskb:
21487 case Intrinsic::x86_sse2_pmovmskb_128:
21488 case Intrinsic::x86_avx2_pmovmskb: {
21489 // High bits of movmskp{s|d}, pmovmskb are known zero.
21491 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21492 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21493 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21494 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21495 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21496 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21497 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21498 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21500 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21509 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21511 const SelectionDAG &,
21512 unsigned Depth) const {
21513 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21514 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21515 return Op.getValueType().getScalarType().getSizeInBits();
21521 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21522 /// node is a GlobalAddress + offset.
21523 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21524 const GlobalValue* &GA,
21525 int64_t &Offset) const {
21526 if (N->getOpcode() == X86ISD::Wrapper) {
21527 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21528 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21529 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21533 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21536 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21537 /// same as extracting the high 128-bit part of 256-bit vector and then
21538 /// inserting the result into the low part of a new 256-bit vector
21539 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21540 EVT VT = SVOp->getValueType(0);
21541 unsigned NumElems = VT.getVectorNumElements();
21543 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21544 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21545 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21546 SVOp->getMaskElt(j) >= 0)
21552 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21553 /// same as extracting the low 128-bit part of 256-bit vector and then
21554 /// inserting the result into the high part of a new 256-bit vector
21555 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21556 EVT VT = SVOp->getValueType(0);
21557 unsigned NumElems = VT.getVectorNumElements();
21559 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21560 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21561 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21562 SVOp->getMaskElt(j) >= 0)
21568 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21569 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21570 TargetLowering::DAGCombinerInfo &DCI,
21571 const X86Subtarget* Subtarget) {
21573 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21574 SDValue V1 = SVOp->getOperand(0);
21575 SDValue V2 = SVOp->getOperand(1);
21576 EVT VT = SVOp->getValueType(0);
21577 unsigned NumElems = VT.getVectorNumElements();
21579 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21580 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21584 // V UNDEF BUILD_VECTOR UNDEF
21586 // CONCAT_VECTOR CONCAT_VECTOR
21589 // RESULT: V + zero extended
21591 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21592 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21593 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21596 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21599 // To match the shuffle mask, the first half of the mask should
21600 // be exactly the first vector, and all the rest a splat with the
21601 // first element of the second one.
21602 for (unsigned i = 0; i != NumElems/2; ++i)
21603 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21604 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21607 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21608 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21609 if (Ld->hasNUsesOfValue(1, 0)) {
21610 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21611 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21613 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21615 Ld->getPointerInfo(),
21616 Ld->getAlignment(),
21617 false/*isVolatile*/, true/*ReadMem*/,
21618 false/*WriteMem*/);
21620 // Make sure the newly-created LOAD is in the same position as Ld in
21621 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21622 // and update uses of Ld's output chain to use the TokenFactor.
21623 if (Ld->hasAnyUseOfValue(1)) {
21624 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21625 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21626 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21627 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21628 SDValue(ResNode.getNode(), 1));
21631 return DAG.getBitcast(VT, ResNode);
21635 // Emit a zeroed vector and insert the desired subvector on its
21637 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21638 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21639 return DCI.CombineTo(N, InsV);
21642 //===--------------------------------------------------------------------===//
21643 // Combine some shuffles into subvector extracts and inserts:
21646 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21647 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21648 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21649 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21650 return DCI.CombineTo(N, InsV);
21653 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21654 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21655 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21656 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21657 return DCI.CombineTo(N, InsV);
21663 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21666 /// This is the leaf of the recursive combinine below. When we have found some
21667 /// chain of single-use x86 shuffle instructions and accumulated the combined
21668 /// shuffle mask represented by them, this will try to pattern match that mask
21669 /// into either a single instruction if there is a special purpose instruction
21670 /// for this operation, or into a PSHUFB instruction which is a fully general
21671 /// instruction but should only be used to replace chains over a certain depth.
21672 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21673 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21674 TargetLowering::DAGCombinerInfo &DCI,
21675 const X86Subtarget *Subtarget) {
21676 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21678 // Find the operand that enters the chain. Note that multiple uses are OK
21679 // here, we're not going to remove the operand we find.
21680 SDValue Input = Op.getOperand(0);
21681 while (Input.getOpcode() == ISD::BITCAST)
21682 Input = Input.getOperand(0);
21684 MVT VT = Input.getSimpleValueType();
21685 MVT RootVT = Root.getSimpleValueType();
21688 // Just remove no-op shuffle masks.
21689 if (Mask.size() == 1) {
21690 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21695 // Use the float domain if the operand type is a floating point type.
21696 bool FloatDomain = VT.isFloatingPoint();
21698 // For floating point shuffles, we don't have free copies in the shuffle
21699 // instructions or the ability to load as part of the instruction, so
21700 // canonicalize their shuffles to UNPCK or MOV variants.
21702 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21703 // vectors because it can have a load folded into it that UNPCK cannot. This
21704 // doesn't preclude something switching to the shorter encoding post-RA.
21706 // FIXME: Should teach these routines about AVX vector widths.
21707 if (FloatDomain && VT.getSizeInBits() == 128) {
21708 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21709 bool Lo = Mask.equals({0, 0});
21712 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21713 // is no slower than UNPCKLPD but has the option to fold the input operand
21714 // into even an unaligned memory load.
21715 if (Lo && Subtarget->hasSSE3()) {
21716 Shuffle = X86ISD::MOVDDUP;
21717 ShuffleVT = MVT::v2f64;
21719 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21720 // than the UNPCK variants.
21721 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21722 ShuffleVT = MVT::v4f32;
21724 if (Depth == 1 && Root->getOpcode() == Shuffle)
21725 return false; // Nothing to do!
21726 Op = DAG.getBitcast(ShuffleVT, Input);
21727 DCI.AddToWorklist(Op.getNode());
21728 if (Shuffle == X86ISD::MOVDDUP)
21729 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21731 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21732 DCI.AddToWorklist(Op.getNode());
21733 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21737 if (Subtarget->hasSSE3() &&
21738 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
21739 bool Lo = Mask.equals({0, 0, 2, 2});
21740 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21741 MVT ShuffleVT = MVT::v4f32;
21742 if (Depth == 1 && Root->getOpcode() == Shuffle)
21743 return false; // Nothing to do!
21744 Op = DAG.getBitcast(ShuffleVT, Input);
21745 DCI.AddToWorklist(Op.getNode());
21746 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21747 DCI.AddToWorklist(Op.getNode());
21748 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21752 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
21753 bool Lo = Mask.equals({0, 0, 1, 1});
21754 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21755 MVT ShuffleVT = MVT::v4f32;
21756 if (Depth == 1 && Root->getOpcode() == Shuffle)
21757 return false; // Nothing to do!
21758 Op = DAG.getBitcast(ShuffleVT, Input);
21759 DCI.AddToWorklist(Op.getNode());
21760 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21761 DCI.AddToWorklist(Op.getNode());
21762 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21768 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21769 // variants as none of these have single-instruction variants that are
21770 // superior to the UNPCK formulation.
21771 if (!FloatDomain && VT.getSizeInBits() == 128 &&
21772 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21773 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
21774 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
21776 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
21777 bool Lo = Mask[0] == 0;
21778 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21779 if (Depth == 1 && Root->getOpcode() == Shuffle)
21780 return false; // Nothing to do!
21782 switch (Mask.size()) {
21784 ShuffleVT = MVT::v8i16;
21787 ShuffleVT = MVT::v16i8;
21790 llvm_unreachable("Impossible mask size!");
21792 Op = DAG.getBitcast(ShuffleVT, Input);
21793 DCI.AddToWorklist(Op.getNode());
21794 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21795 DCI.AddToWorklist(Op.getNode());
21796 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21801 // Don't try to re-form single instruction chains under any circumstances now
21802 // that we've done encoding canonicalization for them.
21806 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21807 // can replace them with a single PSHUFB instruction profitably. Intel's
21808 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21809 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21810 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21811 SmallVector<SDValue, 16> PSHUFBMask;
21812 int NumBytes = VT.getSizeInBits() / 8;
21813 int Ratio = NumBytes / Mask.size();
21814 for (int i = 0; i < NumBytes; ++i) {
21815 if (Mask[i / Ratio] == SM_SentinelUndef) {
21816 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21819 int M = Mask[i / Ratio] != SM_SentinelZero
21820 ? Ratio * Mask[i / Ratio] + i % Ratio
21822 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
21824 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
21825 Op = DAG.getBitcast(ByteVT, Input);
21826 DCI.AddToWorklist(Op.getNode());
21827 SDValue PSHUFBMaskOp =
21828 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
21829 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21830 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
21831 DCI.AddToWorklist(Op.getNode());
21832 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21837 // Failed to find any combines.
21841 /// \brief Fully generic combining of x86 shuffle instructions.
21843 /// This should be the last combine run over the x86 shuffle instructions. Once
21844 /// they have been fully optimized, this will recursively consider all chains
21845 /// of single-use shuffle instructions, build a generic model of the cumulative
21846 /// shuffle operation, and check for simpler instructions which implement this
21847 /// operation. We use this primarily for two purposes:
21849 /// 1) Collapse generic shuffles to specialized single instructions when
21850 /// equivalent. In most cases, this is just an encoding size win, but
21851 /// sometimes we will collapse multiple generic shuffles into a single
21852 /// special-purpose shuffle.
21853 /// 2) Look for sequences of shuffle instructions with 3 or more total
21854 /// instructions, and replace them with the slightly more expensive SSSE3
21855 /// PSHUFB instruction if available. We do this as the last combining step
21856 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21857 /// a suitable short sequence of other instructions. The PHUFB will either
21858 /// use a register or have to read from memory and so is slightly (but only
21859 /// slightly) more expensive than the other shuffle instructions.
21861 /// Because this is inherently a quadratic operation (for each shuffle in
21862 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21863 /// This should never be an issue in practice as the shuffle lowering doesn't
21864 /// produce sequences of more than 8 instructions.
21866 /// FIXME: We will currently miss some cases where the redundant shuffling
21867 /// would simplify under the threshold for PSHUFB formation because of
21868 /// combine-ordering. To fix this, we should do the redundant instruction
21869 /// combining in this recursive walk.
21870 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21871 ArrayRef<int> RootMask,
21872 int Depth, bool HasPSHUFB,
21874 TargetLowering::DAGCombinerInfo &DCI,
21875 const X86Subtarget *Subtarget) {
21876 // Bound the depth of our recursive combine because this is ultimately
21877 // quadratic in nature.
21881 // Directly rip through bitcasts to find the underlying operand.
21882 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21883 Op = Op.getOperand(0);
21885 MVT VT = Op.getSimpleValueType();
21886 if (!VT.isVector())
21887 return false; // Bail if we hit a non-vector.
21889 assert(Root.getSimpleValueType().isVector() &&
21890 "Shuffles operate on vector types!");
21891 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21892 "Can only combine shuffles of the same vector register size.");
21894 if (!isTargetShuffle(Op.getOpcode()))
21896 SmallVector<int, 16> OpMask;
21898 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21899 // We only can combine unary shuffles which we can decode the mask for.
21900 if (!HaveMask || !IsUnary)
21903 assert(VT.getVectorNumElements() == OpMask.size() &&
21904 "Different mask size from vector size!");
21905 assert(((RootMask.size() > OpMask.size() &&
21906 RootMask.size() % OpMask.size() == 0) ||
21907 (OpMask.size() > RootMask.size() &&
21908 OpMask.size() % RootMask.size() == 0) ||
21909 OpMask.size() == RootMask.size()) &&
21910 "The smaller number of elements must divide the larger.");
21911 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21912 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21913 assert(((RootRatio == 1 && OpRatio == 1) ||
21914 (RootRatio == 1) != (OpRatio == 1)) &&
21915 "Must not have a ratio for both incoming and op masks!");
21917 SmallVector<int, 16> Mask;
21918 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21920 // Merge this shuffle operation's mask into our accumulated mask. Note that
21921 // this shuffle's mask will be the first applied to the input, followed by the
21922 // root mask to get us all the way to the root value arrangement. The reason
21923 // for this order is that we are recursing up the operation chain.
21924 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21925 int RootIdx = i / RootRatio;
21926 if (RootMask[RootIdx] < 0) {
21927 // This is a zero or undef lane, we're done.
21928 Mask.push_back(RootMask[RootIdx]);
21932 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21933 int OpIdx = RootMaskedIdx / OpRatio;
21934 if (OpMask[OpIdx] < 0) {
21935 // The incoming lanes are zero or undef, it doesn't matter which ones we
21937 Mask.push_back(OpMask[OpIdx]);
21941 // Ok, we have non-zero lanes, map them through.
21942 Mask.push_back(OpMask[OpIdx] * OpRatio +
21943 RootMaskedIdx % OpRatio);
21946 // See if we can recurse into the operand to combine more things.
21947 switch (Op.getOpcode()) {
21948 case X86ISD::PSHUFB:
21950 case X86ISD::PSHUFD:
21951 case X86ISD::PSHUFHW:
21952 case X86ISD::PSHUFLW:
21953 if (Op.getOperand(0).hasOneUse() &&
21954 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21955 HasPSHUFB, DAG, DCI, Subtarget))
21959 case X86ISD::UNPCKL:
21960 case X86ISD::UNPCKH:
21961 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21962 // We can't check for single use, we have to check that this shuffle is the only user.
21963 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21964 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21965 HasPSHUFB, DAG, DCI, Subtarget))
21970 // Minor canonicalization of the accumulated shuffle mask to make it easier
21971 // to match below. All this does is detect masks with squential pairs of
21972 // elements, and shrink them to the half-width mask. It does this in a loop
21973 // so it will reduce the size of the mask to the minimal width mask which
21974 // performs an equivalent shuffle.
21975 SmallVector<int, 16> WidenedMask;
21976 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21977 Mask = std::move(WidenedMask);
21978 WidenedMask.clear();
21981 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21985 /// \brief Get the PSHUF-style mask from PSHUF node.
21987 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21988 /// PSHUF-style masks that can be reused with such instructions.
21989 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21990 MVT VT = N.getSimpleValueType();
21991 SmallVector<int, 4> Mask;
21993 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
21997 // If we have more than 128-bits, only the low 128-bits of shuffle mask
21998 // matter. Check that the upper masks are repeats and remove them.
21999 if (VT.getSizeInBits() > 128) {
22000 int LaneElts = 128 / VT.getScalarSizeInBits();
22002 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22003 for (int j = 0; j < LaneElts; ++j)
22004 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22005 "Mask doesn't repeat in high 128-bit lanes!");
22007 Mask.resize(LaneElts);
22010 switch (N.getOpcode()) {
22011 case X86ISD::PSHUFD:
22013 case X86ISD::PSHUFLW:
22016 case X86ISD::PSHUFHW:
22017 Mask.erase(Mask.begin(), Mask.begin() + 4);
22018 for (int &M : Mask)
22022 llvm_unreachable("No valid shuffle instruction found!");
22026 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22028 /// We walk up the chain and look for a combinable shuffle, skipping over
22029 /// shuffles that we could hoist this shuffle's transformation past without
22030 /// altering anything.
22032 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22034 TargetLowering::DAGCombinerInfo &DCI) {
22035 assert(N.getOpcode() == X86ISD::PSHUFD &&
22036 "Called with something other than an x86 128-bit half shuffle!");
22039 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22040 // of the shuffles in the chain so that we can form a fresh chain to replace
22042 SmallVector<SDValue, 8> Chain;
22043 SDValue V = N.getOperand(0);
22044 for (; V.hasOneUse(); V = V.getOperand(0)) {
22045 switch (V.getOpcode()) {
22047 return SDValue(); // Nothing combined!
22050 // Skip bitcasts as we always know the type for the target specific
22054 case X86ISD::PSHUFD:
22055 // Found another dword shuffle.
22058 case X86ISD::PSHUFLW:
22059 // Check that the low words (being shuffled) are the identity in the
22060 // dword shuffle, and the high words are self-contained.
22061 if (Mask[0] != 0 || Mask[1] != 1 ||
22062 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22065 Chain.push_back(V);
22068 case X86ISD::PSHUFHW:
22069 // Check that the high words (being shuffled) are the identity in the
22070 // dword shuffle, and the low words are self-contained.
22071 if (Mask[2] != 2 || Mask[3] != 3 ||
22072 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22075 Chain.push_back(V);
22078 case X86ISD::UNPCKL:
22079 case X86ISD::UNPCKH:
22080 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22081 // shuffle into a preceding word shuffle.
22082 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22083 V.getSimpleValueType().getScalarType() != MVT::i16)
22086 // Search for a half-shuffle which we can combine with.
22087 unsigned CombineOp =
22088 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22089 if (V.getOperand(0) != V.getOperand(1) ||
22090 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22092 Chain.push_back(V);
22093 V = V.getOperand(0);
22095 switch (V.getOpcode()) {
22097 return SDValue(); // Nothing to combine.
22099 case X86ISD::PSHUFLW:
22100 case X86ISD::PSHUFHW:
22101 if (V.getOpcode() == CombineOp)
22104 Chain.push_back(V);
22108 V = V.getOperand(0);
22112 } while (V.hasOneUse());
22115 // Break out of the loop if we break out of the switch.
22119 if (!V.hasOneUse())
22120 // We fell out of the loop without finding a viable combining instruction.
22123 // Merge this node's mask and our incoming mask.
22124 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22125 for (int &M : Mask)
22127 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22128 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22130 // Rebuild the chain around this new shuffle.
22131 while (!Chain.empty()) {
22132 SDValue W = Chain.pop_back_val();
22134 if (V.getValueType() != W.getOperand(0).getValueType())
22135 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22137 switch (W.getOpcode()) {
22139 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22141 case X86ISD::UNPCKL:
22142 case X86ISD::UNPCKH:
22143 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22146 case X86ISD::PSHUFD:
22147 case X86ISD::PSHUFLW:
22148 case X86ISD::PSHUFHW:
22149 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22153 if (V.getValueType() != N.getValueType())
22154 V = DAG.getBitcast(N.getValueType(), V);
22156 // Return the new chain to replace N.
22160 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22162 /// We walk up the chain, skipping shuffles of the other half and looking
22163 /// through shuffles which switch halves trying to find a shuffle of the same
22164 /// pair of dwords.
22165 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22167 TargetLowering::DAGCombinerInfo &DCI) {
22169 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22170 "Called with something other than an x86 128-bit half shuffle!");
22172 unsigned CombineOpcode = N.getOpcode();
22174 // Walk up a single-use chain looking for a combinable shuffle.
22175 SDValue V = N.getOperand(0);
22176 for (; V.hasOneUse(); V = V.getOperand(0)) {
22177 switch (V.getOpcode()) {
22179 return false; // Nothing combined!
22182 // Skip bitcasts as we always know the type for the target specific
22186 case X86ISD::PSHUFLW:
22187 case X86ISD::PSHUFHW:
22188 if (V.getOpcode() == CombineOpcode)
22191 // Other-half shuffles are no-ops.
22194 // Break out of the loop if we break out of the switch.
22198 if (!V.hasOneUse())
22199 // We fell out of the loop without finding a viable combining instruction.
22202 // Combine away the bottom node as its shuffle will be accumulated into
22203 // a preceding shuffle.
22204 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22206 // Record the old value.
22209 // Merge this node's mask and our incoming mask (adjusted to account for all
22210 // the pshufd instructions encountered).
22211 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22212 for (int &M : Mask)
22214 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22215 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22217 // Check that the shuffles didn't cancel each other out. If not, we need to
22218 // combine to the new one.
22220 // Replace the combinable shuffle with the combined one, updating all users
22221 // so that we re-evaluate the chain here.
22222 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22227 /// \brief Try to combine x86 target specific shuffles.
22228 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22229 TargetLowering::DAGCombinerInfo &DCI,
22230 const X86Subtarget *Subtarget) {
22232 MVT VT = N.getSimpleValueType();
22233 SmallVector<int, 4> Mask;
22235 switch (N.getOpcode()) {
22236 case X86ISD::PSHUFD:
22237 case X86ISD::PSHUFLW:
22238 case X86ISD::PSHUFHW:
22239 Mask = getPSHUFShuffleMask(N);
22240 assert(Mask.size() == 4);
22246 // Nuke no-op shuffles that show up after combining.
22247 if (isNoopShuffleMask(Mask))
22248 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22250 // Look for simplifications involving one or two shuffle instructions.
22251 SDValue V = N.getOperand(0);
22252 switch (N.getOpcode()) {
22255 case X86ISD::PSHUFLW:
22256 case X86ISD::PSHUFHW:
22257 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22259 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22260 return SDValue(); // We combined away this shuffle, so we're done.
22262 // See if this reduces to a PSHUFD which is no more expensive and can
22263 // combine with more operations. Note that it has to at least flip the
22264 // dwords as otherwise it would have been removed as a no-op.
22265 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22266 int DMask[] = {0, 1, 2, 3};
22267 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22268 DMask[DOffset + 0] = DOffset + 1;
22269 DMask[DOffset + 1] = DOffset + 0;
22270 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22271 V = DAG.getBitcast(DVT, V);
22272 DCI.AddToWorklist(V.getNode());
22273 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22274 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22275 DCI.AddToWorklist(V.getNode());
22276 return DAG.getBitcast(VT, V);
22279 // Look for shuffle patterns which can be implemented as a single unpack.
22280 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22281 // only works when we have a PSHUFD followed by two half-shuffles.
22282 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22283 (V.getOpcode() == X86ISD::PSHUFLW ||
22284 V.getOpcode() == X86ISD::PSHUFHW) &&
22285 V.getOpcode() != N.getOpcode() &&
22287 SDValue D = V.getOperand(0);
22288 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22289 D = D.getOperand(0);
22290 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22291 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22292 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22293 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22294 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22296 for (int i = 0; i < 4; ++i) {
22297 WordMask[i + NOffset] = Mask[i] + NOffset;
22298 WordMask[i + VOffset] = VMask[i] + VOffset;
22300 // Map the word mask through the DWord mask.
22302 for (int i = 0; i < 8; ++i)
22303 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22304 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22305 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22306 // We can replace all three shuffles with an unpack.
22307 V = DAG.getBitcast(VT, D.getOperand(0));
22308 DCI.AddToWorklist(V.getNode());
22309 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22318 case X86ISD::PSHUFD:
22319 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22328 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22330 /// We combine this directly on the abstract vector shuffle nodes so it is
22331 /// easier to generically match. We also insert dummy vector shuffle nodes for
22332 /// the operands which explicitly discard the lanes which are unused by this
22333 /// operation to try to flow through the rest of the combiner the fact that
22334 /// they're unused.
22335 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22337 EVT VT = N->getValueType(0);
22339 // We only handle target-independent shuffles.
22340 // FIXME: It would be easy and harmless to use the target shuffle mask
22341 // extraction tool to support more.
22342 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22345 auto *SVN = cast<ShuffleVectorSDNode>(N);
22346 ArrayRef<int> Mask = SVN->getMask();
22347 SDValue V1 = N->getOperand(0);
22348 SDValue V2 = N->getOperand(1);
22350 // We require the first shuffle operand to be the SUB node, and the second to
22351 // be the ADD node.
22352 // FIXME: We should support the commuted patterns.
22353 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22356 // If there are other uses of these operations we can't fold them.
22357 if (!V1->hasOneUse() || !V2->hasOneUse())
22360 // Ensure that both operations have the same operands. Note that we can
22361 // commute the FADD operands.
22362 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22363 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22364 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22367 // We're looking for blends between FADD and FSUB nodes. We insist on these
22368 // nodes being lined up in a specific expected pattern.
22369 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22370 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22371 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22374 // Only specific types are legal at this point, assert so we notice if and
22375 // when these change.
22376 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22377 VT == MVT::v4f64) &&
22378 "Unknown vector type encountered!");
22380 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22383 /// PerformShuffleCombine - Performs several different shuffle combines.
22384 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22385 TargetLowering::DAGCombinerInfo &DCI,
22386 const X86Subtarget *Subtarget) {
22388 SDValue N0 = N->getOperand(0);
22389 SDValue N1 = N->getOperand(1);
22390 EVT VT = N->getValueType(0);
22392 // Don't create instructions with illegal types after legalize types has run.
22393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22394 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22397 // If we have legalized the vector types, look for blends of FADD and FSUB
22398 // nodes that we can fuse into an ADDSUB node.
22399 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22400 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22403 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22404 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22405 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22406 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22408 // During Type Legalization, when promoting illegal vector types,
22409 // the backend might introduce new shuffle dag nodes and bitcasts.
22411 // This code performs the following transformation:
22412 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22413 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22415 // We do this only if both the bitcast and the BINOP dag nodes have
22416 // one use. Also, perform this transformation only if the new binary
22417 // operation is legal. This is to avoid introducing dag nodes that
22418 // potentially need to be further expanded (or custom lowered) into a
22419 // less optimal sequence of dag nodes.
22420 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22421 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22422 N0.getOpcode() == ISD::BITCAST) {
22423 SDValue BC0 = N0.getOperand(0);
22424 EVT SVT = BC0.getValueType();
22425 unsigned Opcode = BC0.getOpcode();
22426 unsigned NumElts = VT.getVectorNumElements();
22428 if (BC0.hasOneUse() && SVT.isVector() &&
22429 SVT.getVectorNumElements() * 2 == NumElts &&
22430 TLI.isOperationLegal(Opcode, VT)) {
22431 bool CanFold = false;
22443 unsigned SVTNumElts = SVT.getVectorNumElements();
22444 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22445 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22446 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22447 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22448 CanFold = SVOp->getMaskElt(i) < 0;
22451 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22452 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22453 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22454 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22459 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22460 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22461 // consecutive, non-overlapping, and in the right order.
22462 SmallVector<SDValue, 16> Elts;
22463 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22464 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22466 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22469 if (isTargetShuffle(N->getOpcode())) {
22471 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22472 if (Shuffle.getNode())
22475 // Try recursively combining arbitrary sequences of x86 shuffle
22476 // instructions into higher-order shuffles. We do this after combining
22477 // specific PSHUF instruction sequences into their minimal form so that we
22478 // can evaluate how many specialized shuffle instructions are involved in
22479 // a particular chain.
22480 SmallVector<int, 1> NonceMask; // Just a placeholder.
22481 NonceMask.push_back(0);
22482 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22483 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22485 return SDValue(); // This routine will use CombineTo to replace N.
22491 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22492 /// specific shuffle of a load can be folded into a single element load.
22493 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22494 /// shuffles have been custom lowered so we need to handle those here.
22495 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22496 TargetLowering::DAGCombinerInfo &DCI) {
22497 if (DCI.isBeforeLegalizeOps())
22500 SDValue InVec = N->getOperand(0);
22501 SDValue EltNo = N->getOperand(1);
22503 if (!isa<ConstantSDNode>(EltNo))
22506 EVT OriginalVT = InVec.getValueType();
22508 if (InVec.getOpcode() == ISD::BITCAST) {
22509 // Don't duplicate a load with other uses.
22510 if (!InVec.hasOneUse())
22512 EVT BCVT = InVec.getOperand(0).getValueType();
22513 if (!BCVT.isVector() ||
22514 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22516 InVec = InVec.getOperand(0);
22519 EVT CurrentVT = InVec.getValueType();
22521 if (!isTargetShuffle(InVec.getOpcode()))
22524 // Don't duplicate a load with other uses.
22525 if (!InVec.hasOneUse())
22528 SmallVector<int, 16> ShuffleMask;
22530 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22531 ShuffleMask, UnaryShuffle))
22534 // Select the input vector, guarding against out of range extract vector.
22535 unsigned NumElems = CurrentVT.getVectorNumElements();
22536 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22537 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22538 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22539 : InVec.getOperand(1);
22541 // If inputs to shuffle are the same for both ops, then allow 2 uses
22542 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22543 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22545 if (LdNode.getOpcode() == ISD::BITCAST) {
22546 // Don't duplicate a load with other uses.
22547 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22550 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22551 LdNode = LdNode.getOperand(0);
22554 if (!ISD::isNormalLoad(LdNode.getNode()))
22557 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22559 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22562 EVT EltVT = N->getValueType(0);
22563 // If there's a bitcast before the shuffle, check if the load type and
22564 // alignment is valid.
22565 unsigned Align = LN0->getAlignment();
22566 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22567 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22568 EltVT.getTypeForEVT(*DAG.getContext()));
22570 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22573 // All checks match so transform back to vector_shuffle so that DAG combiner
22574 // can finish the job
22577 // Create shuffle node taking into account the case that its a unary shuffle
22578 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22579 : InVec.getOperand(1);
22580 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22581 InVec.getOperand(0), Shuffle,
22583 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22584 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22588 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22589 /// special and don't usually play with other vector types, it's better to
22590 /// handle them early to be sure we emit efficient code by avoiding
22591 /// store-load conversions.
22592 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22593 if (N->getValueType(0) != MVT::x86mmx ||
22594 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22595 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22598 SDValue V = N->getOperand(0);
22599 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22600 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22601 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22602 N->getValueType(0), V.getOperand(0));
22607 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22608 /// generation and convert it from being a bunch of shuffles and extracts
22609 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22610 /// storing the value and loading scalars back, while for x64 we should
22611 /// use 64-bit extracts and shifts.
22612 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22613 TargetLowering::DAGCombinerInfo &DCI) {
22614 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22617 SDValue InputVector = N->getOperand(0);
22618 SDLoc dl(InputVector);
22619 // Detect mmx to i32 conversion through a v2i32 elt extract.
22620 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22621 N->getValueType(0) == MVT::i32 &&
22622 InputVector.getValueType() == MVT::v2i32) {
22624 // The bitcast source is a direct mmx result.
22625 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22626 if (MMXSrc.getValueType() == MVT::x86mmx)
22627 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22628 N->getValueType(0),
22629 InputVector.getNode()->getOperand(0));
22631 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22632 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22633 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22634 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22635 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22636 MMXSrcOp.getValueType() == MVT::v1i64 &&
22637 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22638 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22639 N->getValueType(0),
22640 MMXSrcOp.getOperand(0));
22643 EVT VT = N->getValueType(0);
22645 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22646 InputVector.getOpcode() == ISD::BITCAST &&
22647 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22648 uint64_t ExtractedElt =
22649 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22650 uint64_t InputValue =
22651 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22652 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22653 return DAG.getConstant(Res, dl, MVT::i1);
22655 // Only operate on vectors of 4 elements, where the alternative shuffling
22656 // gets to be more expensive.
22657 if (InputVector.getValueType() != MVT::v4i32)
22660 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22661 // single use which is a sign-extend or zero-extend, and all elements are
22663 SmallVector<SDNode *, 4> Uses;
22664 unsigned ExtractedElements = 0;
22665 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22666 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22667 if (UI.getUse().getResNo() != InputVector.getResNo())
22670 SDNode *Extract = *UI;
22671 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22674 if (Extract->getValueType(0) != MVT::i32)
22676 if (!Extract->hasOneUse())
22678 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22679 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22681 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22684 // Record which element was extracted.
22685 ExtractedElements |=
22686 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22688 Uses.push_back(Extract);
22691 // If not all the elements were used, this may not be worthwhile.
22692 if (ExtractedElements != 15)
22695 // Ok, we've now decided to do the transformation.
22696 // If 64-bit shifts are legal, use the extract-shift sequence,
22697 // otherwise bounce the vector off the cache.
22698 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22701 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22702 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22703 auto &DL = DAG.getDataLayout();
22704 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22705 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22706 DAG.getConstant(0, dl, VecIdxTy));
22707 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22708 DAG.getConstant(1, dl, VecIdxTy));
22710 SDValue ShAmt = DAG.getConstant(
22711 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22712 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22713 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22714 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22715 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22716 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22717 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22719 // Store the value to a temporary stack slot.
22720 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22721 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22722 MachinePointerInfo(), false, false, 0);
22724 EVT ElementType = InputVector.getValueType().getVectorElementType();
22725 unsigned EltSize = ElementType.getSizeInBits() / 8;
22727 // Replace each use (extract) with a load of the appropriate element.
22728 for (unsigned i = 0; i < 4; ++i) {
22729 uint64_t Offset = EltSize * i;
22730 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
22731 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
22733 SDValue ScalarAddr =
22734 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
22736 // Load the scalar.
22737 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22738 ScalarAddr, MachinePointerInfo(),
22739 false, false, false, 0);
22744 // Replace the extracts
22745 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22746 UE = Uses.end(); UI != UE; ++UI) {
22747 SDNode *Extract = *UI;
22749 SDValue Idx = Extract->getOperand(1);
22750 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22751 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22754 // The replacement was made in place; don't return anything.
22759 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22760 const X86Subtarget *Subtarget) {
22762 SDValue Cond = N->getOperand(0);
22763 SDValue LHS = N->getOperand(1);
22764 SDValue RHS = N->getOperand(2);
22766 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22767 SDValue CondSrc = Cond->getOperand(0);
22768 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22769 Cond = CondSrc->getOperand(0);
22772 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22775 // A vselect where all conditions and data are constants can be optimized into
22776 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22777 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22778 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22781 unsigned MaskValue = 0;
22782 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22785 MVT VT = N->getSimpleValueType(0);
22786 unsigned NumElems = VT.getVectorNumElements();
22787 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22788 for (unsigned i = 0; i < NumElems; ++i) {
22789 // Be sure we emit undef where we can.
22790 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22791 ShuffleMask[i] = -1;
22793 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22797 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22799 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22802 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22804 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22805 TargetLowering::DAGCombinerInfo &DCI,
22806 const X86Subtarget *Subtarget) {
22808 SDValue Cond = N->getOperand(0);
22809 // Get the LHS/RHS of the select.
22810 SDValue LHS = N->getOperand(1);
22811 SDValue RHS = N->getOperand(2);
22812 EVT VT = LHS.getValueType();
22813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22815 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22816 // instructions match the semantics of the common C idiom x<y?x:y but not
22817 // x<=y?x:y, because of how they handle negative zero (which can be
22818 // ignored in unsafe-math mode).
22819 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
22820 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22821 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
22822 (Subtarget->hasSSE2() ||
22823 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22824 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22826 unsigned Opcode = 0;
22827 // Check for x CC y ? x : y.
22828 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22829 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22833 // Converting this to a min would handle NaNs incorrectly, and swapping
22834 // the operands would cause it to handle comparisons between positive
22835 // and negative zero incorrectly.
22836 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22837 if (!DAG.getTarget().Options.UnsafeFPMath &&
22838 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22840 std::swap(LHS, RHS);
22842 Opcode = X86ISD::FMIN;
22845 // Converting this to a min would handle comparisons between positive
22846 // and negative zero incorrectly.
22847 if (!DAG.getTarget().Options.UnsafeFPMath &&
22848 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22850 Opcode = X86ISD::FMIN;
22853 // Converting this to a min would handle both negative zeros and NaNs
22854 // incorrectly, but we can swap the operands to fix both.
22855 std::swap(LHS, RHS);
22859 Opcode = X86ISD::FMIN;
22863 // Converting this to a max would handle comparisons between positive
22864 // and negative zero incorrectly.
22865 if (!DAG.getTarget().Options.UnsafeFPMath &&
22866 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22868 Opcode = X86ISD::FMAX;
22871 // Converting this to a max would handle NaNs incorrectly, and swapping
22872 // the operands would cause it to handle comparisons between positive
22873 // and negative zero incorrectly.
22874 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22875 if (!DAG.getTarget().Options.UnsafeFPMath &&
22876 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22878 std::swap(LHS, RHS);
22880 Opcode = X86ISD::FMAX;
22883 // Converting this to a max would handle both negative zeros and NaNs
22884 // incorrectly, but we can swap the operands to fix both.
22885 std::swap(LHS, RHS);
22889 Opcode = X86ISD::FMAX;
22892 // Check for x CC y ? y : x -- a min/max with reversed arms.
22893 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22894 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22898 // Converting this to a min would handle comparisons between positive
22899 // and negative zero incorrectly, and swapping the operands would
22900 // cause it to handle NaNs incorrectly.
22901 if (!DAG.getTarget().Options.UnsafeFPMath &&
22902 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22903 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22905 std::swap(LHS, RHS);
22907 Opcode = X86ISD::FMIN;
22910 // Converting this to a min would handle NaNs incorrectly.
22911 if (!DAG.getTarget().Options.UnsafeFPMath &&
22912 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22914 Opcode = X86ISD::FMIN;
22917 // Converting this to a min would handle both negative zeros and NaNs
22918 // incorrectly, but we can swap the operands to fix both.
22919 std::swap(LHS, RHS);
22923 Opcode = X86ISD::FMIN;
22927 // Converting this to a max would handle NaNs incorrectly.
22928 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22930 Opcode = X86ISD::FMAX;
22933 // Converting this to a max would handle comparisons between positive
22934 // and negative zero incorrectly, and swapping the operands would
22935 // cause it to handle NaNs incorrectly.
22936 if (!DAG.getTarget().Options.UnsafeFPMath &&
22937 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22938 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22940 std::swap(LHS, RHS);
22942 Opcode = X86ISD::FMAX;
22945 // Converting this to a max would handle both negative zeros and NaNs
22946 // incorrectly, but we can swap the operands to fix both.
22947 std::swap(LHS, RHS);
22951 Opcode = X86ISD::FMAX;
22957 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22960 EVT CondVT = Cond.getValueType();
22961 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22962 CondVT.getVectorElementType() == MVT::i1) {
22963 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22964 // lowering on KNL. In this case we convert it to
22965 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22966 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22967 // Since SKX these selects have a proper lowering.
22968 EVT OpVT = LHS.getValueType();
22969 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22970 (OpVT.getVectorElementType() == MVT::i8 ||
22971 OpVT.getVectorElementType() == MVT::i16) &&
22972 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22973 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22974 DCI.AddToWorklist(Cond.getNode());
22975 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22978 // If this is a select between two integer constants, try to do some
22980 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22981 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22982 // Don't do this for crazy integer types.
22983 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22984 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22985 // so that TrueC (the true value) is larger than FalseC.
22986 bool NeedsCondInvert = false;
22988 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22989 // Efficiently invertible.
22990 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22991 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22992 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22993 NeedsCondInvert = true;
22994 std::swap(TrueC, FalseC);
22997 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22998 if (FalseC->getAPIntValue() == 0 &&
22999 TrueC->getAPIntValue().isPowerOf2()) {
23000 if (NeedsCondInvert) // Invert the condition if needed.
23001 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23002 DAG.getConstant(1, DL, Cond.getValueType()));
23004 // Zero extend the condition if needed.
23005 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23007 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23008 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23009 DAG.getConstant(ShAmt, DL, MVT::i8));
23012 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23013 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23014 if (NeedsCondInvert) // Invert the condition if needed.
23015 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23016 DAG.getConstant(1, DL, Cond.getValueType()));
23018 // Zero extend the condition if needed.
23019 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23020 FalseC->getValueType(0), Cond);
23021 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23022 SDValue(FalseC, 0));
23025 // Optimize cases that will turn into an LEA instruction. This requires
23026 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23027 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23028 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23029 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23031 bool isFastMultiplier = false;
23033 switch ((unsigned char)Diff) {
23035 case 1: // result = add base, cond
23036 case 2: // result = lea base( , cond*2)
23037 case 3: // result = lea base(cond, cond*2)
23038 case 4: // result = lea base( , cond*4)
23039 case 5: // result = lea base(cond, cond*4)
23040 case 8: // result = lea base( , cond*8)
23041 case 9: // result = lea base(cond, cond*8)
23042 isFastMultiplier = true;
23047 if (isFastMultiplier) {
23048 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23049 if (NeedsCondInvert) // Invert the condition if needed.
23050 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23051 DAG.getConstant(1, DL, Cond.getValueType()));
23053 // Zero extend the condition if needed.
23054 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23056 // Scale the condition by the difference.
23058 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23059 DAG.getConstant(Diff, DL,
23060 Cond.getValueType()));
23062 // Add the base if non-zero.
23063 if (FalseC->getAPIntValue() != 0)
23064 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23065 SDValue(FalseC, 0));
23072 // Canonicalize max and min:
23073 // (x > y) ? x : y -> (x >= y) ? x : y
23074 // (x < y) ? x : y -> (x <= y) ? x : y
23075 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23076 // the need for an extra compare
23077 // against zero. e.g.
23078 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23080 // testl %edi, %edi
23082 // cmovgl %edi, %eax
23086 // cmovsl %eax, %edi
23087 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23088 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23089 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23090 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23095 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23096 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23097 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23098 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23103 // Early exit check
23104 if (!TLI.isTypeLegal(VT))
23107 // Match VSELECTs into subs with unsigned saturation.
23108 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23109 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23110 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23111 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23112 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23114 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23115 // left side invert the predicate to simplify logic below.
23117 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23119 CC = ISD::getSetCCInverse(CC, true);
23120 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23124 if (Other.getNode() && Other->getNumOperands() == 2 &&
23125 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23126 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23127 SDValue CondRHS = Cond->getOperand(1);
23129 // Look for a general sub with unsigned saturation first.
23130 // x >= y ? x-y : 0 --> subus x, y
23131 // x > y ? x-y : 0 --> subus x, y
23132 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23133 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23134 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23136 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23137 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23138 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23139 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23140 // If the RHS is a constant we have to reverse the const
23141 // canonicalization.
23142 // x > C-1 ? x+-C : 0 --> subus x, C
23143 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23144 CondRHSConst->getAPIntValue() ==
23145 (-OpRHSConst->getAPIntValue() - 1))
23146 return DAG.getNode(
23147 X86ISD::SUBUS, DL, VT, OpLHS,
23148 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23150 // Another special case: If C was a sign bit, the sub has been
23151 // canonicalized into a xor.
23152 // FIXME: Would it be better to use computeKnownBits to determine
23153 // whether it's safe to decanonicalize the xor?
23154 // x s< 0 ? x^C : 0 --> subus x, C
23155 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23156 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23157 OpRHSConst->getAPIntValue().isSignBit())
23158 // Note that we have to rebuild the RHS constant here to ensure we
23159 // don't rely on particular values of undef lanes.
23160 return DAG.getNode(
23161 X86ISD::SUBUS, DL, VT, OpLHS,
23162 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23167 // Simplify vector selection if condition value type matches vselect
23169 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23170 assert(Cond.getValueType().isVector() &&
23171 "vector select expects a vector selector!");
23173 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23174 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23176 // Try invert the condition if true value is not all 1s and false value
23178 if (!TValIsAllOnes && !FValIsAllZeros &&
23179 // Check if the selector will be produced by CMPP*/PCMP*
23180 Cond.getOpcode() == ISD::SETCC &&
23181 // Check if SETCC has already been promoted
23182 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23184 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23185 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23187 if (TValIsAllZeros || FValIsAllOnes) {
23188 SDValue CC = Cond.getOperand(2);
23189 ISD::CondCode NewCC =
23190 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23191 Cond.getOperand(0).getValueType().isInteger());
23192 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23193 std::swap(LHS, RHS);
23194 TValIsAllOnes = FValIsAllOnes;
23195 FValIsAllZeros = TValIsAllZeros;
23199 if (TValIsAllOnes || FValIsAllZeros) {
23202 if (TValIsAllOnes && FValIsAllZeros)
23204 else if (TValIsAllOnes)
23206 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23207 else if (FValIsAllZeros)
23208 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23209 DAG.getBitcast(CondVT, LHS));
23211 return DAG.getBitcast(VT, Ret);
23215 // We should generate an X86ISD::BLENDI from a vselect if its argument
23216 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23217 // constants. This specific pattern gets generated when we split a
23218 // selector for a 512 bit vector in a machine without AVX512 (but with
23219 // 256-bit vectors), during legalization:
23221 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23223 // Iff we find this pattern and the build_vectors are built from
23224 // constants, we translate the vselect into a shuffle_vector that we
23225 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23226 if ((N->getOpcode() == ISD::VSELECT ||
23227 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23228 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23229 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23230 if (Shuffle.getNode())
23234 // If this is a *dynamic* select (non-constant condition) and we can match
23235 // this node with one of the variable blend instructions, restructure the
23236 // condition so that the blends can use the high bit of each element and use
23237 // SimplifyDemandedBits to simplify the condition operand.
23238 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23239 !DCI.isBeforeLegalize() &&
23240 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23241 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23243 // Don't optimize vector selects that map to mask-registers.
23247 // We can only handle the cases where VSELECT is directly legal on the
23248 // subtarget. We custom lower VSELECT nodes with constant conditions and
23249 // this makes it hard to see whether a dynamic VSELECT will correctly
23250 // lower, so we both check the operation's status and explicitly handle the
23251 // cases where a *dynamic* blend will fail even though a constant-condition
23252 // blend could be custom lowered.
23253 // FIXME: We should find a better way to handle this class of problems.
23254 // Potentially, we should combine constant-condition vselect nodes
23255 // pre-legalization into shuffles and not mark as many types as custom
23257 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23259 // FIXME: We don't support i16-element blends currently. We could and
23260 // should support them by making *all* the bits in the condition be set
23261 // rather than just the high bit and using an i8-element blend.
23262 if (VT.getScalarType() == MVT::i16)
23264 // Dynamic blending was only available from SSE4.1 onward.
23265 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23267 // Byte blends are only available in AVX2
23268 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23269 !Subtarget->hasAVX2())
23272 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23273 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23275 APInt KnownZero, KnownOne;
23276 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23277 DCI.isBeforeLegalizeOps());
23278 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23279 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23281 // If we changed the computation somewhere in the DAG, this change
23282 // will affect all users of Cond.
23283 // Make sure it is fine and update all the nodes so that we do not
23284 // use the generic VSELECT anymore. Otherwise, we may perform
23285 // wrong optimizations as we messed up with the actual expectation
23286 // for the vector boolean values.
23287 if (Cond != TLO.Old) {
23288 // Check all uses of that condition operand to check whether it will be
23289 // consumed by non-BLEND instructions, which may depend on all bits are
23291 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23293 if (I->getOpcode() != ISD::VSELECT)
23294 // TODO: Add other opcodes eventually lowered into BLEND.
23297 // Update all the users of the condition, before committing the change,
23298 // so that the VSELECT optimizations that expect the correct vector
23299 // boolean value will not be triggered.
23300 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23302 DAG.ReplaceAllUsesOfValueWith(
23304 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23305 Cond, I->getOperand(1), I->getOperand(2)));
23306 DCI.CommitTargetLoweringOpt(TLO);
23309 // At this point, only Cond is changed. Change the condition
23310 // just for N to keep the opportunity to optimize all other
23311 // users their own way.
23312 DAG.ReplaceAllUsesOfValueWith(
23314 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23315 TLO.New, N->getOperand(1), N->getOperand(2)));
23323 // Check whether a boolean test is testing a boolean value generated by
23324 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23327 // Simplify the following patterns:
23328 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23329 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23330 // to (Op EFLAGS Cond)
23332 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23333 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23334 // to (Op EFLAGS !Cond)
23336 // where Op could be BRCOND or CMOV.
23338 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23339 // Quit if not CMP and SUB with its value result used.
23340 if (Cmp.getOpcode() != X86ISD::CMP &&
23341 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23344 // Quit if not used as a boolean value.
23345 if (CC != X86::COND_E && CC != X86::COND_NE)
23348 // Check CMP operands. One of them should be 0 or 1 and the other should be
23349 // an SetCC or extended from it.
23350 SDValue Op1 = Cmp.getOperand(0);
23351 SDValue Op2 = Cmp.getOperand(1);
23354 const ConstantSDNode* C = nullptr;
23355 bool needOppositeCond = (CC == X86::COND_E);
23356 bool checkAgainstTrue = false; // Is it a comparison against 1?
23358 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23360 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23362 else // Quit if all operands are not constants.
23365 if (C->getZExtValue() == 1) {
23366 needOppositeCond = !needOppositeCond;
23367 checkAgainstTrue = true;
23368 } else if (C->getZExtValue() != 0)
23369 // Quit if the constant is neither 0 or 1.
23372 bool truncatedToBoolWithAnd = false;
23373 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23374 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23375 SetCC.getOpcode() == ISD::TRUNCATE ||
23376 SetCC.getOpcode() == ISD::AND) {
23377 if (SetCC.getOpcode() == ISD::AND) {
23379 ConstantSDNode *CS;
23380 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23381 CS->getZExtValue() == 1)
23383 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23384 CS->getZExtValue() == 1)
23388 SetCC = SetCC.getOperand(OpIdx);
23389 truncatedToBoolWithAnd = true;
23391 SetCC = SetCC.getOperand(0);
23394 switch (SetCC.getOpcode()) {
23395 case X86ISD::SETCC_CARRY:
23396 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23397 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23398 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23399 // truncated to i1 using 'and'.
23400 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23402 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23403 "Invalid use of SETCC_CARRY!");
23405 case X86ISD::SETCC:
23406 // Set the condition code or opposite one if necessary.
23407 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23408 if (needOppositeCond)
23409 CC = X86::GetOppositeBranchCondition(CC);
23410 return SetCC.getOperand(1);
23411 case X86ISD::CMOV: {
23412 // Check whether false/true value has canonical one, i.e. 0 or 1.
23413 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23414 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23415 // Quit if true value is not a constant.
23418 // Quit if false value is not a constant.
23420 SDValue Op = SetCC.getOperand(0);
23421 // Skip 'zext' or 'trunc' node.
23422 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23423 Op.getOpcode() == ISD::TRUNCATE)
23424 Op = Op.getOperand(0);
23425 // A special case for rdrand/rdseed, where 0 is set if false cond is
23427 if ((Op.getOpcode() != X86ISD::RDRAND &&
23428 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23431 // Quit if false value is not the constant 0 or 1.
23432 bool FValIsFalse = true;
23433 if (FVal && FVal->getZExtValue() != 0) {
23434 if (FVal->getZExtValue() != 1)
23436 // If FVal is 1, opposite cond is needed.
23437 needOppositeCond = !needOppositeCond;
23438 FValIsFalse = false;
23440 // Quit if TVal is not the constant opposite of FVal.
23441 if (FValIsFalse && TVal->getZExtValue() != 1)
23443 if (!FValIsFalse && TVal->getZExtValue() != 0)
23445 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23446 if (needOppositeCond)
23447 CC = X86::GetOppositeBranchCondition(CC);
23448 return SetCC.getOperand(3);
23455 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23457 /// (X86or (X86setcc) (X86setcc))
23458 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23459 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23460 X86::CondCode &CC1, SDValue &Flags,
23462 if (Cond->getOpcode() == X86ISD::CMP) {
23463 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23464 if (!CondOp1C || !CondOp1C->isNullValue())
23467 Cond = Cond->getOperand(0);
23472 SDValue SetCC0, SetCC1;
23473 switch (Cond->getOpcode()) {
23474 default: return false;
23481 SetCC0 = Cond->getOperand(0);
23482 SetCC1 = Cond->getOperand(1);
23486 // Make sure we have SETCC nodes, using the same flags value.
23487 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23488 SetCC1.getOpcode() != X86ISD::SETCC ||
23489 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23492 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23493 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23494 Flags = SetCC0->getOperand(1);
23498 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23499 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23500 TargetLowering::DAGCombinerInfo &DCI,
23501 const X86Subtarget *Subtarget) {
23504 // If the flag operand isn't dead, don't touch this CMOV.
23505 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23508 SDValue FalseOp = N->getOperand(0);
23509 SDValue TrueOp = N->getOperand(1);
23510 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23511 SDValue Cond = N->getOperand(3);
23513 if (CC == X86::COND_E || CC == X86::COND_NE) {
23514 switch (Cond.getOpcode()) {
23518 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23519 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23520 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23526 Flags = checkBoolTestSetCCCombine(Cond, CC);
23527 if (Flags.getNode() &&
23528 // Extra check as FCMOV only supports a subset of X86 cond.
23529 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23530 SDValue Ops[] = { FalseOp, TrueOp,
23531 DAG.getConstant(CC, DL, MVT::i8), Flags };
23532 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23535 // If this is a select between two integer constants, try to do some
23536 // optimizations. Note that the operands are ordered the opposite of SELECT
23538 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23539 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23540 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23541 // larger than FalseC (the false value).
23542 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23543 CC = X86::GetOppositeBranchCondition(CC);
23544 std::swap(TrueC, FalseC);
23545 std::swap(TrueOp, FalseOp);
23548 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23549 // This is efficient for any integer data type (including i8/i16) and
23551 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23552 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23553 DAG.getConstant(CC, DL, MVT::i8), Cond);
23555 // Zero extend the condition if needed.
23556 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23558 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23559 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23560 DAG.getConstant(ShAmt, DL, MVT::i8));
23561 if (N->getNumValues() == 2) // Dead flag value?
23562 return DCI.CombineTo(N, Cond, SDValue());
23566 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23567 // for any integer data type, including i8/i16.
23568 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23569 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23570 DAG.getConstant(CC, DL, MVT::i8), Cond);
23572 // Zero extend the condition if needed.
23573 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23574 FalseC->getValueType(0), Cond);
23575 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23576 SDValue(FalseC, 0));
23578 if (N->getNumValues() == 2) // Dead flag value?
23579 return DCI.CombineTo(N, Cond, SDValue());
23583 // Optimize cases that will turn into an LEA instruction. This requires
23584 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23585 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23586 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23587 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23589 bool isFastMultiplier = false;
23591 switch ((unsigned char)Diff) {
23593 case 1: // result = add base, cond
23594 case 2: // result = lea base( , cond*2)
23595 case 3: // result = lea base(cond, cond*2)
23596 case 4: // result = lea base( , cond*4)
23597 case 5: // result = lea base(cond, cond*4)
23598 case 8: // result = lea base( , cond*8)
23599 case 9: // result = lea base(cond, cond*8)
23600 isFastMultiplier = true;
23605 if (isFastMultiplier) {
23606 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23607 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23608 DAG.getConstant(CC, DL, MVT::i8), Cond);
23609 // Zero extend the condition if needed.
23610 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23612 // Scale the condition by the difference.
23614 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23615 DAG.getConstant(Diff, DL, Cond.getValueType()));
23617 // Add the base if non-zero.
23618 if (FalseC->getAPIntValue() != 0)
23619 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23620 SDValue(FalseC, 0));
23621 if (N->getNumValues() == 2) // Dead flag value?
23622 return DCI.CombineTo(N, Cond, SDValue());
23629 // Handle these cases:
23630 // (select (x != c), e, c) -> select (x != c), e, x),
23631 // (select (x == c), c, e) -> select (x == c), x, e)
23632 // where the c is an integer constant, and the "select" is the combination
23633 // of CMOV and CMP.
23635 // The rationale for this change is that the conditional-move from a constant
23636 // needs two instructions, however, conditional-move from a register needs
23637 // only one instruction.
23639 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23640 // some instruction-combining opportunities. This opt needs to be
23641 // postponed as late as possible.
23643 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23644 // the DCI.xxxx conditions are provided to postpone the optimization as
23645 // late as possible.
23647 ConstantSDNode *CmpAgainst = nullptr;
23648 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23649 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23650 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23652 if (CC == X86::COND_NE &&
23653 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23654 CC = X86::GetOppositeBranchCondition(CC);
23655 std::swap(TrueOp, FalseOp);
23658 if (CC == X86::COND_E &&
23659 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23660 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23661 DAG.getConstant(CC, DL, MVT::i8), Cond };
23662 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23667 // Fold and/or of setcc's to double CMOV:
23668 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23669 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23671 // This combine lets us generate:
23672 // cmovcc1 (jcc1 if we don't have CMOV)
23678 // cmovne (jne if we don't have CMOV)
23679 // When we can't use the CMOV instruction, it might increase branch
23681 // When we can use CMOV, or when there is no mispredict, this improves
23682 // throughput and reduces register pressure.
23684 if (CC == X86::COND_NE) {
23686 X86::CondCode CC0, CC1;
23688 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23690 std::swap(FalseOp, TrueOp);
23691 CC0 = X86::GetOppositeBranchCondition(CC0);
23692 CC1 = X86::GetOppositeBranchCondition(CC1);
23695 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23697 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23698 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23699 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23700 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23708 /// PerformMulCombine - Optimize a single multiply with constant into two
23709 /// in order to implement it with two cheaper instructions, e.g.
23710 /// LEA + SHL, LEA + LEA.
23711 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23712 TargetLowering::DAGCombinerInfo &DCI) {
23713 // An imul is usually smaller than the alternative sequence.
23714 if (DAG.getMachineFunction().getFunction()->optForMinSize())
23717 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23720 EVT VT = N->getValueType(0);
23721 if (VT != MVT::i64 && VT != MVT::i32)
23724 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23727 uint64_t MulAmt = C->getZExtValue();
23728 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23731 uint64_t MulAmt1 = 0;
23732 uint64_t MulAmt2 = 0;
23733 if ((MulAmt % 9) == 0) {
23735 MulAmt2 = MulAmt / 9;
23736 } else if ((MulAmt % 5) == 0) {
23738 MulAmt2 = MulAmt / 5;
23739 } else if ((MulAmt % 3) == 0) {
23741 MulAmt2 = MulAmt / 3;
23744 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23747 if (isPowerOf2_64(MulAmt2) &&
23748 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23749 // If second multiplifer is pow2, issue it first. We want the multiply by
23750 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23752 std::swap(MulAmt1, MulAmt2);
23755 if (isPowerOf2_64(MulAmt1))
23756 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23757 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
23759 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23760 DAG.getConstant(MulAmt1, DL, VT));
23762 if (isPowerOf2_64(MulAmt2))
23763 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23764 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
23766 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23767 DAG.getConstant(MulAmt2, DL, VT));
23769 // Do not add new nodes to DAG combiner worklist.
23770 DCI.CombineTo(N, NewMul, false);
23775 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23776 SDValue N0 = N->getOperand(0);
23777 SDValue N1 = N->getOperand(1);
23778 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23779 EVT VT = N0.getValueType();
23781 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23782 // since the result of setcc_c is all zero's or all ones.
23783 if (VT.isInteger() && !VT.isVector() &&
23784 N1C && N0.getOpcode() == ISD::AND &&
23785 N0.getOperand(1).getOpcode() == ISD::Constant) {
23786 SDValue N00 = N0.getOperand(0);
23787 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23788 APInt ShAmt = N1C->getAPIntValue();
23789 Mask = Mask.shl(ShAmt);
23790 bool MaskOK = false;
23791 // We can handle cases concerning bit-widening nodes containing setcc_c if
23792 // we carefully interrogate the mask to make sure we are semantics
23794 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
23795 // of the underlying setcc_c operation if the setcc_c was zero extended.
23796 // Consider the following example:
23797 // zext(setcc_c) -> i32 0x0000FFFF
23798 // c1 -> i32 0x0000FFFF
23799 // c2 -> i32 0x00000001
23800 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
23801 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
23802 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23804 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
23805 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
23807 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
23808 N00.getOpcode() == ISD::ANY_EXTEND) &&
23809 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
23810 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
23812 if (MaskOK && Mask != 0) {
23814 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
23818 // Hardware support for vector shifts is sparse which makes us scalarize the
23819 // vector operations in many cases. Also, on sandybridge ADD is faster than
23821 // (shl V, 1) -> add V,V
23822 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23823 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23824 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23825 // We shift all of the values by one. In many cases we do not have
23826 // hardware support for this operation. This is better expressed as an ADD
23828 if (N1SplatC->getAPIntValue() == 1)
23829 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23835 /// \brief Returns a vector of 0s if the node in input is a vector logical
23836 /// shift by a constant amount which is known to be bigger than or equal
23837 /// to the vector element size in bits.
23838 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23839 const X86Subtarget *Subtarget) {
23840 EVT VT = N->getValueType(0);
23842 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23843 (!Subtarget->hasInt256() ||
23844 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23847 SDValue Amt = N->getOperand(1);
23849 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23850 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23851 APInt ShiftAmt = AmtSplat->getAPIntValue();
23852 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23854 // SSE2/AVX2 logical shifts always return a vector of 0s
23855 // if the shift amount is bigger than or equal to
23856 // the element size. The constant shift amount will be
23857 // encoded as a 8-bit immediate.
23858 if (ShiftAmt.trunc(8).uge(MaxAmount))
23859 return getZeroVector(VT, Subtarget, DAG, DL);
23865 /// PerformShiftCombine - Combine shifts.
23866 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23867 TargetLowering::DAGCombinerInfo &DCI,
23868 const X86Subtarget *Subtarget) {
23869 if (N->getOpcode() == ISD::SHL)
23870 if (SDValue V = PerformSHLCombine(N, DAG))
23873 // Try to fold this logical shift into a zero vector.
23874 if (N->getOpcode() != ISD::SRA)
23875 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
23881 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23882 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23883 // and friends. Likewise for OR -> CMPNEQSS.
23884 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23885 TargetLowering::DAGCombinerInfo &DCI,
23886 const X86Subtarget *Subtarget) {
23889 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23890 // we're requiring SSE2 for both.
23891 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23892 SDValue N0 = N->getOperand(0);
23893 SDValue N1 = N->getOperand(1);
23894 SDValue CMP0 = N0->getOperand(1);
23895 SDValue CMP1 = N1->getOperand(1);
23898 // The SETCCs should both refer to the same CMP.
23899 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23902 SDValue CMP00 = CMP0->getOperand(0);
23903 SDValue CMP01 = CMP0->getOperand(1);
23904 EVT VT = CMP00.getValueType();
23906 if (VT == MVT::f32 || VT == MVT::f64) {
23907 bool ExpectingFlags = false;
23908 // Check for any users that want flags:
23909 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23910 !ExpectingFlags && UI != UE; ++UI)
23911 switch (UI->getOpcode()) {
23916 ExpectingFlags = true;
23918 case ISD::CopyToReg:
23919 case ISD::SIGN_EXTEND:
23920 case ISD::ZERO_EXTEND:
23921 case ISD::ANY_EXTEND:
23925 if (!ExpectingFlags) {
23926 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23927 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23929 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23930 X86::CondCode tmp = cc0;
23935 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23936 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23937 // FIXME: need symbolic constants for these magic numbers.
23938 // See X86ATTInstPrinter.cpp:printSSECC().
23939 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23940 if (Subtarget->hasAVX512()) {
23941 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23943 DAG.getConstant(x86cc, DL, MVT::i8));
23944 if (N->getValueType(0) != MVT::i1)
23945 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23949 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23950 CMP00.getValueType(), CMP00, CMP01,
23951 DAG.getConstant(x86cc, DL,
23954 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23955 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23957 if (is64BitFP && !Subtarget->is64Bit()) {
23958 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23959 // 64-bit integer, since that's not a legal type. Since
23960 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23961 // bits, but can do this little dance to extract the lowest 32 bits
23962 // and work with those going forward.
23963 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23965 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
23966 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23967 Vector32, DAG.getIntPtrConstant(0, DL));
23971 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23972 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23973 DAG.getConstant(1, DL, IntVT));
23974 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
23976 return OneBitOfTruth;
23984 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23985 /// so it can be folded inside ANDNP.
23986 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23987 EVT VT = N->getValueType(0);
23989 // Match direct AllOnes for 128 and 256-bit vectors
23990 if (ISD::isBuildVectorAllOnes(N))
23993 // Look through a bit convert.
23994 if (N->getOpcode() == ISD::BITCAST)
23995 N = N->getOperand(0).getNode();
23997 // Sometimes the operand may come from a insert_subvector building a 256-bit
23999 if (VT.is256BitVector() &&
24000 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24001 SDValue V1 = N->getOperand(0);
24002 SDValue V2 = N->getOperand(1);
24004 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24005 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24006 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24007 ISD::isBuildVectorAllOnes(V2.getNode()))
24014 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24015 // register. In most cases we actually compare or select YMM-sized registers
24016 // and mixing the two types creates horrible code. This method optimizes
24017 // some of the transition sequences.
24018 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24019 TargetLowering::DAGCombinerInfo &DCI,
24020 const X86Subtarget *Subtarget) {
24021 EVT VT = N->getValueType(0);
24022 if (!VT.is256BitVector())
24025 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24026 N->getOpcode() == ISD::ZERO_EXTEND ||
24027 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24029 SDValue Narrow = N->getOperand(0);
24030 EVT NarrowVT = Narrow->getValueType(0);
24031 if (!NarrowVT.is128BitVector())
24034 if (Narrow->getOpcode() != ISD::XOR &&
24035 Narrow->getOpcode() != ISD::AND &&
24036 Narrow->getOpcode() != ISD::OR)
24039 SDValue N0 = Narrow->getOperand(0);
24040 SDValue N1 = Narrow->getOperand(1);
24043 // The Left side has to be a trunc.
24044 if (N0.getOpcode() != ISD::TRUNCATE)
24047 // The type of the truncated inputs.
24048 EVT WideVT = N0->getOperand(0)->getValueType(0);
24052 // The right side has to be a 'trunc' or a constant vector.
24053 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24054 ConstantSDNode *RHSConstSplat = nullptr;
24055 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24056 RHSConstSplat = RHSBV->getConstantSplatNode();
24057 if (!RHSTrunc && !RHSConstSplat)
24060 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24062 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24065 // Set N0 and N1 to hold the inputs to the new wide operation.
24066 N0 = N0->getOperand(0);
24067 if (RHSConstSplat) {
24068 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24069 SDValue(RHSConstSplat, 0));
24070 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24071 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24072 } else if (RHSTrunc) {
24073 N1 = N1->getOperand(0);
24076 // Generate the wide operation.
24077 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24078 unsigned Opcode = N->getOpcode();
24080 case ISD::ANY_EXTEND:
24082 case ISD::ZERO_EXTEND: {
24083 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24084 APInt Mask = APInt::getAllOnesValue(InBits);
24085 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24086 return DAG.getNode(ISD::AND, DL, VT,
24087 Op, DAG.getConstant(Mask, DL, VT));
24089 case ISD::SIGN_EXTEND:
24090 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24091 Op, DAG.getValueType(NarrowVT));
24093 llvm_unreachable("Unexpected opcode");
24097 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24098 TargetLowering::DAGCombinerInfo &DCI,
24099 const X86Subtarget *Subtarget) {
24100 SDValue N0 = N->getOperand(0);
24101 SDValue N1 = N->getOperand(1);
24104 // A vector zext_in_reg may be represented as a shuffle,
24105 // feeding into a bitcast (this represents anyext) feeding into
24106 // an and with a mask.
24107 // We'd like to try to combine that into a shuffle with zero
24108 // plus a bitcast, removing the and.
24109 if (N0.getOpcode() != ISD::BITCAST ||
24110 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24113 // The other side of the AND should be a splat of 2^C, where C
24114 // is the number of bits in the source type.
24115 if (N1.getOpcode() == ISD::BITCAST)
24116 N1 = N1.getOperand(0);
24117 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24119 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24121 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24122 EVT SrcType = Shuffle->getValueType(0);
24124 // We expect a single-source shuffle
24125 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24128 unsigned SrcSize = SrcType.getScalarSizeInBits();
24130 APInt SplatValue, SplatUndef;
24131 unsigned SplatBitSize;
24133 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24134 SplatBitSize, HasAnyUndefs))
24137 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24138 // Make sure the splat matches the mask we expect
24139 if (SplatBitSize > ResSize ||
24140 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24143 // Make sure the input and output size make sense
24144 if (SrcSize >= ResSize || ResSize % SrcSize)
24147 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24148 // The number of u's between each two values depends on the ratio between
24149 // the source and dest type.
24150 unsigned ZextRatio = ResSize / SrcSize;
24151 bool IsZext = true;
24152 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24153 if (i % ZextRatio) {
24154 if (Shuffle->getMaskElt(i) > 0) {
24160 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24161 // Expected element number
24171 // Ok, perform the transformation - replace the shuffle with
24172 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24173 // (instead of undef) where the k elements come from the zero vector.
24174 SmallVector<int, 8> Mask;
24175 unsigned NumElems = SrcType.getVectorNumElements();
24176 for (unsigned i = 0; i < NumElems; ++i)
24178 Mask.push_back(NumElems);
24180 Mask.push_back(i / ZextRatio);
24182 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24183 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24184 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24187 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24188 TargetLowering::DAGCombinerInfo &DCI,
24189 const X86Subtarget *Subtarget) {
24190 if (DCI.isBeforeLegalizeOps())
24193 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24196 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24199 EVT VT = N->getValueType(0);
24200 SDValue N0 = N->getOperand(0);
24201 SDValue N1 = N->getOperand(1);
24204 // Create BEXTR instructions
24205 // BEXTR is ((X >> imm) & (2**size-1))
24206 if (VT == MVT::i32 || VT == MVT::i64) {
24207 // Check for BEXTR.
24208 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24209 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24210 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24211 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24212 if (MaskNode && ShiftNode) {
24213 uint64_t Mask = MaskNode->getZExtValue();
24214 uint64_t Shift = ShiftNode->getZExtValue();
24215 if (isMask_64(Mask)) {
24216 uint64_t MaskSize = countPopulation(Mask);
24217 if (Shift + MaskSize <= VT.getSizeInBits())
24218 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24219 DAG.getConstant(Shift | (MaskSize << 8), DL,
24228 // Want to form ANDNP nodes:
24229 // 1) In the hopes of then easily combining them with OR and AND nodes
24230 // to form PBLEND/PSIGN.
24231 // 2) To match ANDN packed intrinsics
24232 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24235 // Check LHS for vnot
24236 if (N0.getOpcode() == ISD::XOR &&
24237 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24238 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24239 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24241 // Check RHS for vnot
24242 if (N1.getOpcode() == ISD::XOR &&
24243 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24244 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24245 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24250 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24251 TargetLowering::DAGCombinerInfo &DCI,
24252 const X86Subtarget *Subtarget) {
24253 if (DCI.isBeforeLegalizeOps())
24256 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24259 SDValue N0 = N->getOperand(0);
24260 SDValue N1 = N->getOperand(1);
24261 EVT VT = N->getValueType(0);
24263 // look for psign/blend
24264 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24265 if (!Subtarget->hasSSSE3() ||
24266 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24269 // Canonicalize pandn to RHS
24270 if (N0.getOpcode() == X86ISD::ANDNP)
24272 // or (and (m, y), (pandn m, x))
24273 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24274 SDValue Mask = N1.getOperand(0);
24275 SDValue X = N1.getOperand(1);
24277 if (N0.getOperand(0) == Mask)
24278 Y = N0.getOperand(1);
24279 if (N0.getOperand(1) == Mask)
24280 Y = N0.getOperand(0);
24282 // Check to see if the mask appeared in both the AND and ANDNP and
24286 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24287 // Look through mask bitcast.
24288 if (Mask.getOpcode() == ISD::BITCAST)
24289 Mask = Mask.getOperand(0);
24290 if (X.getOpcode() == ISD::BITCAST)
24291 X = X.getOperand(0);
24292 if (Y.getOpcode() == ISD::BITCAST)
24293 Y = Y.getOperand(0);
24295 EVT MaskVT = Mask.getValueType();
24297 // Validate that the Mask operand is a vector sra node.
24298 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24299 // there is no psrai.b
24300 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24301 unsigned SraAmt = ~0;
24302 if (Mask.getOpcode() == ISD::SRA) {
24303 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24304 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24305 SraAmt = AmtConst->getZExtValue();
24306 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24307 SDValue SraC = Mask.getOperand(1);
24308 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24310 if ((SraAmt + 1) != EltBits)
24315 // Now we know we at least have a plendvb with the mask val. See if
24316 // we can form a psignb/w/d.
24317 // psign = x.type == y.type == mask.type && y = sub(0, x);
24318 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24319 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24320 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24321 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24322 "Unsupported VT for PSIGN");
24323 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24324 return DAG.getBitcast(VT, Mask);
24326 // PBLENDVB only available on SSE 4.1
24327 if (!Subtarget->hasSSE41())
24330 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24332 X = DAG.getBitcast(BlendVT, X);
24333 Y = DAG.getBitcast(BlendVT, Y);
24334 Mask = DAG.getBitcast(BlendVT, Mask);
24335 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24336 return DAG.getBitcast(VT, Mask);
24340 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24343 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24344 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24346 // SHLD/SHRD instructions have lower register pressure, but on some
24347 // platforms they have higher latency than the equivalent
24348 // series of shifts/or that would otherwise be generated.
24349 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24350 // have higher latencies and we are not optimizing for size.
24351 if (!OptForSize && Subtarget->isSHLDSlow())
24354 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24356 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24358 if (!N0.hasOneUse() || !N1.hasOneUse())
24361 SDValue ShAmt0 = N0.getOperand(1);
24362 if (ShAmt0.getValueType() != MVT::i8)
24364 SDValue ShAmt1 = N1.getOperand(1);
24365 if (ShAmt1.getValueType() != MVT::i8)
24367 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24368 ShAmt0 = ShAmt0.getOperand(0);
24369 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24370 ShAmt1 = ShAmt1.getOperand(0);
24373 unsigned Opc = X86ISD::SHLD;
24374 SDValue Op0 = N0.getOperand(0);
24375 SDValue Op1 = N1.getOperand(0);
24376 if (ShAmt0.getOpcode() == ISD::SUB) {
24377 Opc = X86ISD::SHRD;
24378 std::swap(Op0, Op1);
24379 std::swap(ShAmt0, ShAmt1);
24382 unsigned Bits = VT.getSizeInBits();
24383 if (ShAmt1.getOpcode() == ISD::SUB) {
24384 SDValue Sum = ShAmt1.getOperand(0);
24385 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24386 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24387 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24388 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24389 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24390 return DAG.getNode(Opc, DL, VT,
24392 DAG.getNode(ISD::TRUNCATE, DL,
24395 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24396 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24398 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24399 return DAG.getNode(Opc, DL, VT,
24400 N0.getOperand(0), N1.getOperand(0),
24401 DAG.getNode(ISD::TRUNCATE, DL,
24408 // Generate NEG and CMOV for integer abs.
24409 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24410 EVT VT = N->getValueType(0);
24412 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24413 // 8-bit integer abs to NEG and CMOV.
24414 if (VT.isInteger() && VT.getSizeInBits() == 8)
24417 SDValue N0 = N->getOperand(0);
24418 SDValue N1 = N->getOperand(1);
24421 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24422 // and change it to SUB and CMOV.
24423 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24424 N0.getOpcode() == ISD::ADD &&
24425 N0.getOperand(1) == N1 &&
24426 N1.getOpcode() == ISD::SRA &&
24427 N1.getOperand(0) == N0.getOperand(0))
24428 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24429 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24430 // Generate SUB & CMOV.
24431 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24432 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24434 SDValue Ops[] = { N0.getOperand(0), Neg,
24435 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24436 SDValue(Neg.getNode(), 1) };
24437 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24442 // Try to turn tests against the signbit in the form of:
24443 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24446 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24447 // This is only worth doing if the output type is i8.
24448 if (N->getValueType(0) != MVT::i8)
24451 SDValue N0 = N->getOperand(0);
24452 SDValue N1 = N->getOperand(1);
24454 // We should be performing an xor against a truncated shift.
24455 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24458 // Make sure we are performing an xor against one.
24459 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24462 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24463 SDValue Shift = N0.getOperand(0);
24464 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24467 // Make sure we are truncating from one of i16, i32 or i64.
24468 EVT ShiftTy = Shift.getValueType();
24469 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24472 // Make sure the shift amount extracts the sign bit.
24473 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24474 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24477 // Create a greater-than comparison against -1.
24478 // N.B. Using SETGE against 0 works but we want a canonical looking
24479 // comparison, using SETGT matches up with what TranslateX86CC.
24481 SDValue ShiftOp = Shift.getOperand(0);
24482 EVT ShiftOpTy = ShiftOp.getValueType();
24483 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24484 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24488 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24489 TargetLowering::DAGCombinerInfo &DCI,
24490 const X86Subtarget *Subtarget) {
24491 if (DCI.isBeforeLegalizeOps())
24494 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24497 if (Subtarget->hasCMov())
24498 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24504 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24505 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24506 TargetLowering::DAGCombinerInfo &DCI,
24507 const X86Subtarget *Subtarget) {
24508 LoadSDNode *Ld = cast<LoadSDNode>(N);
24509 EVT RegVT = Ld->getValueType(0);
24510 EVT MemVT = Ld->getMemoryVT();
24512 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24514 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24515 // into two 16-byte operations.
24516 ISD::LoadExtType Ext = Ld->getExtensionType();
24518 unsigned AddressSpace = Ld->getAddressSpace();
24519 unsigned Alignment = Ld->getAlignment();
24520 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24521 Ext == ISD::NON_EXTLOAD &&
24522 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24523 AddressSpace, Alignment, &Fast) && !Fast) {
24524 unsigned NumElems = RegVT.getVectorNumElements();
24528 SDValue Ptr = Ld->getBasePtr();
24529 SDValue Increment =
24530 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24532 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24534 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24535 Ld->getPointerInfo(), Ld->isVolatile(),
24536 Ld->isNonTemporal(), Ld->isInvariant(),
24538 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24539 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24540 Ld->getPointerInfo(), Ld->isVolatile(),
24541 Ld->isNonTemporal(), Ld->isInvariant(),
24542 std::min(16U, Alignment));
24543 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24545 Load2.getValue(1));
24547 SDValue NewVec = DAG.getUNDEF(RegVT);
24548 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24549 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24550 return DCI.CombineTo(N, NewVec, TF, true);
24556 /// PerformMLOADCombine - Resolve extending loads
24557 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24558 TargetLowering::DAGCombinerInfo &DCI,
24559 const X86Subtarget *Subtarget) {
24560 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24561 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24564 EVT VT = Mld->getValueType(0);
24565 unsigned NumElems = VT.getVectorNumElements();
24566 EVT LdVT = Mld->getMemoryVT();
24569 assert(LdVT != VT && "Cannot extend to the same type");
24570 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24571 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24572 // From, To sizes and ElemCount must be pow of two
24573 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24574 "Unexpected size for extending masked load");
24576 unsigned SizeRatio = ToSz / FromSz;
24577 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24579 // Create a type on which we perform the shuffle
24580 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24581 LdVT.getScalarType(), NumElems*SizeRatio);
24582 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24584 // Convert Src0 value
24585 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24586 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24587 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24588 for (unsigned i = 0; i != NumElems; ++i)
24589 ShuffleVec[i] = i * SizeRatio;
24591 // Can't shuffle using an illegal type.
24592 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24593 && "WideVecVT should be legal");
24594 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24595 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24597 // Prepare the new mask
24599 SDValue Mask = Mld->getMask();
24600 if (Mask.getValueType() == VT) {
24601 // Mask and original value have the same type
24602 NewMask = DAG.getBitcast(WideVecVT, Mask);
24603 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24604 for (unsigned i = 0; i != NumElems; ++i)
24605 ShuffleVec[i] = i * SizeRatio;
24606 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24607 ShuffleVec[i] = NumElems*SizeRatio;
24608 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24609 DAG.getConstant(0, dl, WideVecVT),
24613 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24614 unsigned WidenNumElts = NumElems*SizeRatio;
24615 unsigned MaskNumElts = VT.getVectorNumElements();
24616 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24619 unsigned NumConcat = WidenNumElts / MaskNumElts;
24620 SmallVector<SDValue, 16> Ops(NumConcat);
24621 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24623 for (unsigned i = 1; i != NumConcat; ++i)
24626 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24629 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24630 Mld->getBasePtr(), NewMask, WideSrc0,
24631 Mld->getMemoryVT(), Mld->getMemOperand(),
24633 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24634 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24637 /// PerformMSTORECombine - Resolve truncating stores
24638 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24639 const X86Subtarget *Subtarget) {
24640 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24641 if (!Mst->isTruncatingStore())
24644 EVT VT = Mst->getValue().getValueType();
24645 unsigned NumElems = VT.getVectorNumElements();
24646 EVT StVT = Mst->getMemoryVT();
24649 assert(StVT != VT && "Cannot truncate to the same type");
24650 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24651 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24653 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24655 // The truncating store is legal in some cases. For example
24656 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24657 // are designated for truncate store.
24658 // In this case we don't need any further transformations.
24659 if (TLI.isTruncStoreLegal(VT, StVT))
24662 // From, To sizes and ElemCount must be pow of two
24663 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24664 "Unexpected size for truncating masked store");
24665 // We are going to use the original vector elt for storing.
24666 // Accumulated smaller vector elements must be a multiple of the store size.
24667 assert (((NumElems * FromSz) % ToSz) == 0 &&
24668 "Unexpected ratio for truncating masked store");
24670 unsigned SizeRatio = FromSz / ToSz;
24671 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24673 // Create a type on which we perform the shuffle
24674 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24675 StVT.getScalarType(), NumElems*SizeRatio);
24677 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24679 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
24680 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24681 for (unsigned i = 0; i != NumElems; ++i)
24682 ShuffleVec[i] = i * SizeRatio;
24684 // Can't shuffle using an illegal type.
24685 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24686 && "WideVecVT should be legal");
24688 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24689 DAG.getUNDEF(WideVecVT),
24693 SDValue Mask = Mst->getMask();
24694 if (Mask.getValueType() == VT) {
24695 // Mask and original value have the same type
24696 NewMask = DAG.getBitcast(WideVecVT, Mask);
24697 for (unsigned i = 0; i != NumElems; ++i)
24698 ShuffleVec[i] = i * SizeRatio;
24699 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24700 ShuffleVec[i] = NumElems*SizeRatio;
24701 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24702 DAG.getConstant(0, dl, WideVecVT),
24706 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24707 unsigned WidenNumElts = NumElems*SizeRatio;
24708 unsigned MaskNumElts = VT.getVectorNumElements();
24709 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24712 unsigned NumConcat = WidenNumElts / MaskNumElts;
24713 SmallVector<SDValue, 16> Ops(NumConcat);
24714 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24716 for (unsigned i = 1; i != NumConcat; ++i)
24719 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24722 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
24723 NewMask, StVT, Mst->getMemOperand(), false);
24725 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24726 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24727 const X86Subtarget *Subtarget) {
24728 StoreSDNode *St = cast<StoreSDNode>(N);
24729 EVT VT = St->getValue().getValueType();
24730 EVT StVT = St->getMemoryVT();
24732 SDValue StoredVal = St->getOperand(1);
24733 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24735 // If we are saving a concatenation of two XMM registers and 32-byte stores
24736 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24738 unsigned AddressSpace = St->getAddressSpace();
24739 unsigned Alignment = St->getAlignment();
24740 if (VT.is256BitVector() && StVT == VT &&
24741 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
24742 AddressSpace, Alignment, &Fast) && !Fast) {
24743 unsigned NumElems = VT.getVectorNumElements();
24747 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24748 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24751 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24752 SDValue Ptr0 = St->getBasePtr();
24753 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24755 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24756 St->getPointerInfo(), St->isVolatile(),
24757 St->isNonTemporal(), Alignment);
24758 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24759 St->getPointerInfo(), St->isVolatile(),
24760 St->isNonTemporal(),
24761 std::min(16U, Alignment));
24762 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24765 // Optimize trunc store (of multiple scalars) to shuffle and store.
24766 // First, pack all of the elements in one place. Next, store to memory
24767 // in fewer chunks.
24768 if (St->isTruncatingStore() && VT.isVector()) {
24769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24770 unsigned NumElems = VT.getVectorNumElements();
24771 assert(StVT != VT && "Cannot truncate to the same type");
24772 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24773 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24775 // The truncating store is legal in some cases. For example
24776 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24777 // are designated for truncate store.
24778 // In this case we don't need any further transformations.
24779 if (TLI.isTruncStoreLegal(VT, StVT))
24782 // From, To sizes and ElemCount must be pow of two
24783 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24784 // We are going to use the original vector elt for storing.
24785 // Accumulated smaller vector elements must be a multiple of the store size.
24786 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24788 unsigned SizeRatio = FromSz / ToSz;
24790 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24792 // Create a type on which we perform the shuffle
24793 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24794 StVT.getScalarType(), NumElems*SizeRatio);
24796 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24798 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
24799 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24800 for (unsigned i = 0; i != NumElems; ++i)
24801 ShuffleVec[i] = i * SizeRatio;
24803 // Can't shuffle using an illegal type.
24804 if (!TLI.isTypeLegal(WideVecVT))
24807 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24808 DAG.getUNDEF(WideVecVT),
24810 // At this point all of the data is stored at the bottom of the
24811 // register. We now need to save it to mem.
24813 // Find the largest store unit
24814 MVT StoreType = MVT::i8;
24815 for (MVT Tp : MVT::integer_valuetypes()) {
24816 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24820 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24821 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24822 (64 <= NumElems * ToSz))
24823 StoreType = MVT::f64;
24825 // Bitcast the original vector into a vector of store-size units
24826 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24827 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24828 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24829 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
24830 SmallVector<SDValue, 8> Chains;
24831 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
24832 TLI.getPointerTy(DAG.getDataLayout()));
24833 SDValue Ptr = St->getBasePtr();
24835 // Perform one or more big stores into memory.
24836 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24837 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24838 StoreType, ShuffWide,
24839 DAG.getIntPtrConstant(i, dl));
24840 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24841 St->getPointerInfo(), St->isVolatile(),
24842 St->isNonTemporal(), St->getAlignment());
24843 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24844 Chains.push_back(Ch);
24847 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24850 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24851 // the FP state in cases where an emms may be missing.
24852 // A preferable solution to the general problem is to figure out the right
24853 // places to insert EMMS. This qualifies as a quick hack.
24855 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24856 if (VT.getSizeInBits() != 64)
24859 const Function *F = DAG.getMachineFunction().getFunction();
24860 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
24862 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
24863 if ((VT.isVector() ||
24864 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24865 isa<LoadSDNode>(St->getValue()) &&
24866 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24867 St->getChain().hasOneUse() && !St->isVolatile()) {
24868 SDNode* LdVal = St->getValue().getNode();
24869 LoadSDNode *Ld = nullptr;
24870 int TokenFactorIndex = -1;
24871 SmallVector<SDValue, 8> Ops;
24872 SDNode* ChainVal = St->getChain().getNode();
24873 // Must be a store of a load. We currently handle two cases: the load
24874 // is a direct child, and it's under an intervening TokenFactor. It is
24875 // possible to dig deeper under nested TokenFactors.
24876 if (ChainVal == LdVal)
24877 Ld = cast<LoadSDNode>(St->getChain());
24878 else if (St->getValue().hasOneUse() &&
24879 ChainVal->getOpcode() == ISD::TokenFactor) {
24880 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24881 if (ChainVal->getOperand(i).getNode() == LdVal) {
24882 TokenFactorIndex = i;
24883 Ld = cast<LoadSDNode>(St->getValue());
24885 Ops.push_back(ChainVal->getOperand(i));
24889 if (!Ld || !ISD::isNormalLoad(Ld))
24892 // If this is not the MMX case, i.e. we are just turning i64 load/store
24893 // into f64 load/store, avoid the transformation if there are multiple
24894 // uses of the loaded value.
24895 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24900 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24901 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24903 if (Subtarget->is64Bit() || F64IsLegal) {
24904 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24905 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24906 Ld->getPointerInfo(), Ld->isVolatile(),
24907 Ld->isNonTemporal(), Ld->isInvariant(),
24908 Ld->getAlignment());
24909 SDValue NewChain = NewLd.getValue(1);
24910 if (TokenFactorIndex != -1) {
24911 Ops.push_back(NewChain);
24912 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24914 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24915 St->getPointerInfo(),
24916 St->isVolatile(), St->isNonTemporal(),
24917 St->getAlignment());
24920 // Otherwise, lower to two pairs of 32-bit loads / stores.
24921 SDValue LoAddr = Ld->getBasePtr();
24922 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24923 DAG.getConstant(4, LdDL, MVT::i32));
24925 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24926 Ld->getPointerInfo(),
24927 Ld->isVolatile(), Ld->isNonTemporal(),
24928 Ld->isInvariant(), Ld->getAlignment());
24929 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24930 Ld->getPointerInfo().getWithOffset(4),
24931 Ld->isVolatile(), Ld->isNonTemporal(),
24933 MinAlign(Ld->getAlignment(), 4));
24935 SDValue NewChain = LoLd.getValue(1);
24936 if (TokenFactorIndex != -1) {
24937 Ops.push_back(LoLd);
24938 Ops.push_back(HiLd);
24939 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24942 LoAddr = St->getBasePtr();
24943 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24944 DAG.getConstant(4, StDL, MVT::i32));
24946 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24947 St->getPointerInfo(),
24948 St->isVolatile(), St->isNonTemporal(),
24949 St->getAlignment());
24950 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24951 St->getPointerInfo().getWithOffset(4),
24953 St->isNonTemporal(),
24954 MinAlign(St->getAlignment(), 4));
24955 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24958 // This is similar to the above case, but here we handle a scalar 64-bit
24959 // integer store that is extracted from a vector on a 32-bit target.
24960 // If we have SSE2, then we can treat it like a floating-point double
24961 // to get past legalization. The execution dependencies fixup pass will
24962 // choose the optimal machine instruction for the store if this really is
24963 // an integer or v2f32 rather than an f64.
24964 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
24965 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
24966 SDValue OldExtract = St->getOperand(1);
24967 SDValue ExtOp0 = OldExtract.getOperand(0);
24968 unsigned VecSize = ExtOp0.getValueSizeInBits();
24969 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
24970 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
24971 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
24972 BitCast, OldExtract.getOperand(1));
24973 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
24974 St->getPointerInfo(), St->isVolatile(),
24975 St->isNonTemporal(), St->getAlignment());
24981 /// Return 'true' if this vector operation is "horizontal"
24982 /// and return the operands for the horizontal operation in LHS and RHS. A
24983 /// horizontal operation performs the binary operation on successive elements
24984 /// of its first operand, then on successive elements of its second operand,
24985 /// returning the resulting values in a vector. For example, if
24986 /// A = < float a0, float a1, float a2, float a3 >
24988 /// B = < float b0, float b1, float b2, float b3 >
24989 /// then the result of doing a horizontal operation on A and B is
24990 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24991 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24992 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24993 /// set to A, RHS to B, and the routine returns 'true'.
24994 /// Note that the binary operation should have the property that if one of the
24995 /// operands is UNDEF then the result is UNDEF.
24996 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24997 // Look for the following pattern: if
24998 // A = < float a0, float a1, float a2, float a3 >
24999 // B = < float b0, float b1, float b2, float b3 >
25001 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25002 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25003 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25004 // which is A horizontal-op B.
25006 // At least one of the operands should be a vector shuffle.
25007 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25008 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25011 MVT VT = LHS.getSimpleValueType();
25013 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25014 "Unsupported vector type for horizontal add/sub");
25016 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25017 // operate independently on 128-bit lanes.
25018 unsigned NumElts = VT.getVectorNumElements();
25019 unsigned NumLanes = VT.getSizeInBits()/128;
25020 unsigned NumLaneElts = NumElts / NumLanes;
25021 assert((NumLaneElts % 2 == 0) &&
25022 "Vector type should have an even number of elements in each lane");
25023 unsigned HalfLaneElts = NumLaneElts/2;
25025 // View LHS in the form
25026 // LHS = VECTOR_SHUFFLE A, B, LMask
25027 // If LHS is not a shuffle then pretend it is the shuffle
25028 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25029 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25032 SmallVector<int, 16> LMask(NumElts);
25033 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25034 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25035 A = LHS.getOperand(0);
25036 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25037 B = LHS.getOperand(1);
25038 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25039 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25041 if (LHS.getOpcode() != ISD::UNDEF)
25043 for (unsigned i = 0; i != NumElts; ++i)
25047 // Likewise, view RHS in the form
25048 // RHS = VECTOR_SHUFFLE C, D, RMask
25050 SmallVector<int, 16> RMask(NumElts);
25051 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25052 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25053 C = RHS.getOperand(0);
25054 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25055 D = RHS.getOperand(1);
25056 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25057 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25059 if (RHS.getOpcode() != ISD::UNDEF)
25061 for (unsigned i = 0; i != NumElts; ++i)
25065 // Check that the shuffles are both shuffling the same vectors.
25066 if (!(A == C && B == D) && !(A == D && B == C))
25069 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25070 if (!A.getNode() && !B.getNode())
25073 // If A and B occur in reverse order in RHS, then "swap" them (which means
25074 // rewriting the mask).
25076 ShuffleVectorSDNode::commuteMask(RMask);
25078 // At this point LHS and RHS are equivalent to
25079 // LHS = VECTOR_SHUFFLE A, B, LMask
25080 // RHS = VECTOR_SHUFFLE A, B, RMask
25081 // Check that the masks correspond to performing a horizontal operation.
25082 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25083 for (unsigned i = 0; i != NumLaneElts; ++i) {
25084 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25086 // Ignore any UNDEF components.
25087 if (LIdx < 0 || RIdx < 0 ||
25088 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25089 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25092 // Check that successive elements are being operated on. If not, this is
25093 // not a horizontal operation.
25094 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25095 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25096 if (!(LIdx == Index && RIdx == Index + 1) &&
25097 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25102 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25103 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25107 /// Do target-specific dag combines on floating point adds.
25108 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25109 const X86Subtarget *Subtarget) {
25110 EVT VT = N->getValueType(0);
25111 SDValue LHS = N->getOperand(0);
25112 SDValue RHS = N->getOperand(1);
25114 // Try to synthesize horizontal adds from adds of shuffles.
25115 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25116 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25117 isHorizontalBinOp(LHS, RHS, true))
25118 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25122 /// Do target-specific dag combines on floating point subs.
25123 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25124 const X86Subtarget *Subtarget) {
25125 EVT VT = N->getValueType(0);
25126 SDValue LHS = N->getOperand(0);
25127 SDValue RHS = N->getOperand(1);
25129 // Try to synthesize horizontal subs from subs of shuffles.
25130 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25131 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25132 isHorizontalBinOp(LHS, RHS, false))
25133 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25137 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25138 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
25139 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25141 // F[X]OR(0.0, x) -> x
25142 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25143 if (C->getValueAPF().isPosZero())
25144 return N->getOperand(1);
25146 // F[X]OR(x, 0.0) -> x
25147 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25148 if (C->getValueAPF().isPosZero())
25149 return N->getOperand(0);
25153 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25154 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25155 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25157 // Only perform optimizations if UnsafeMath is used.
25158 if (!DAG.getTarget().Options.UnsafeFPMath)
25161 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25162 // into FMINC and FMAXC, which are Commutative operations.
25163 unsigned NewOp = 0;
25164 switch (N->getOpcode()) {
25165 default: llvm_unreachable("unknown opcode");
25166 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25167 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25170 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25171 N->getOperand(0), N->getOperand(1));
25174 /// Do target-specific dag combines on X86ISD::FAND nodes.
25175 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25176 // FAND(0.0, x) -> 0.0
25177 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25178 if (C->getValueAPF().isPosZero())
25179 return N->getOperand(0);
25181 // FAND(x, 0.0) -> 0.0
25182 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25183 if (C->getValueAPF().isPosZero())
25184 return N->getOperand(1);
25189 /// Do target-specific dag combines on X86ISD::FANDN nodes
25190 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25191 // FANDN(0.0, x) -> x
25192 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25193 if (C->getValueAPF().isPosZero())
25194 return N->getOperand(1);
25196 // FANDN(x, 0.0) -> 0.0
25197 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25198 if (C->getValueAPF().isPosZero())
25199 return N->getOperand(1);
25204 static SDValue PerformBTCombine(SDNode *N,
25206 TargetLowering::DAGCombinerInfo &DCI) {
25207 // BT ignores high bits in the bit index operand.
25208 SDValue Op1 = N->getOperand(1);
25209 if (Op1.hasOneUse()) {
25210 unsigned BitWidth = Op1.getValueSizeInBits();
25211 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25212 APInt KnownZero, KnownOne;
25213 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25214 !DCI.isBeforeLegalizeOps());
25215 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25216 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25217 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25218 DCI.CommitTargetLoweringOpt(TLO);
25223 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25224 SDValue Op = N->getOperand(0);
25225 if (Op.getOpcode() == ISD::BITCAST)
25226 Op = Op.getOperand(0);
25227 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25228 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25229 VT.getVectorElementType().getSizeInBits() ==
25230 OpVT.getVectorElementType().getSizeInBits()) {
25231 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25236 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25237 const X86Subtarget *Subtarget) {
25238 EVT VT = N->getValueType(0);
25239 if (!VT.isVector())
25242 SDValue N0 = N->getOperand(0);
25243 SDValue N1 = N->getOperand(1);
25244 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25247 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25248 // both SSE and AVX2 since there is no sign-extended shift right
25249 // operation on a vector with 64-bit elements.
25250 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25251 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25252 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25253 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25254 SDValue N00 = N0.getOperand(0);
25256 // EXTLOAD has a better solution on AVX2,
25257 // it may be replaced with X86ISD::VSEXT node.
25258 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25259 if (!ISD::isNormalLoad(N00.getNode()))
25262 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25263 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25265 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25271 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25272 TargetLowering::DAGCombinerInfo &DCI,
25273 const X86Subtarget *Subtarget) {
25274 SDValue N0 = N->getOperand(0);
25275 EVT VT = N->getValueType(0);
25276 EVT SVT = VT.getScalarType();
25277 EVT InVT = N0.getValueType();
25278 EVT InSVT = InVT.getScalarType();
25281 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25282 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25283 // This exposes the sext to the sdivrem lowering, so that it directly extends
25284 // from AH (which we otherwise need to do contortions to access).
25285 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25286 InVT == MVT::i8 && VT == MVT::i32) {
25287 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25288 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25289 N0.getOperand(0), N0.getOperand(1));
25290 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25291 return R.getValue(1);
25294 if (!DCI.isBeforeLegalizeOps()) {
25295 if (InVT == MVT::i1) {
25296 SDValue Zero = DAG.getConstant(0, DL, VT);
25298 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25299 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25304 if (VT.isVector() && Subtarget->hasSSE2()) {
25305 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25306 EVT InVT = N.getValueType();
25307 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25308 Size / InVT.getScalarSizeInBits());
25309 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25310 DAG.getUNDEF(InVT));
25312 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25315 // If target-size is less than 128-bits, extend to a type that would extend
25316 // to 128 bits, extend that and extract the original target vector.
25317 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25318 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25319 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25320 unsigned Scale = 128 / VT.getSizeInBits();
25322 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25323 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25324 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25325 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25326 DAG.getIntPtrConstant(0, DL));
25329 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25330 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25331 if (VT.getSizeInBits() == 128 &&
25332 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25333 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25334 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25335 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25338 // On pre-AVX2 targets, split into 128-bit nodes of
25339 // ISD::SIGN_EXTEND_VECTOR_INREG.
25340 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25341 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25342 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25343 unsigned NumVecs = VT.getSizeInBits() / 128;
25344 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25345 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25346 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25348 SmallVector<SDValue, 8> Opnds;
25349 for (unsigned i = 0, Offset = 0; i != NumVecs;
25350 ++i, Offset += NumSubElts) {
25351 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25352 DAG.getIntPtrConstant(Offset, DL));
25353 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25354 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25355 Opnds.push_back(SrcVec);
25357 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25361 if (!Subtarget->hasFp256())
25364 if (VT.isVector() && VT.getSizeInBits() == 256)
25365 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25371 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25372 const X86Subtarget* Subtarget) {
25374 EVT VT = N->getValueType(0);
25376 // Let legalize expand this if it isn't a legal type yet.
25377 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25380 EVT ScalarVT = VT.getScalarType();
25381 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25382 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25383 !Subtarget->hasAVX512()))
25386 SDValue A = N->getOperand(0);
25387 SDValue B = N->getOperand(1);
25388 SDValue C = N->getOperand(2);
25390 bool NegA = (A.getOpcode() == ISD::FNEG);
25391 bool NegB = (B.getOpcode() == ISD::FNEG);
25392 bool NegC = (C.getOpcode() == ISD::FNEG);
25394 // Negative multiplication when NegA xor NegB
25395 bool NegMul = (NegA != NegB);
25397 A = A.getOperand(0);
25399 B = B.getOperand(0);
25401 C = C.getOperand(0);
25405 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25407 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25409 return DAG.getNode(Opcode, dl, VT, A, B, C);
25412 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25413 TargetLowering::DAGCombinerInfo &DCI,
25414 const X86Subtarget *Subtarget) {
25415 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25416 // (and (i32 x86isd::setcc_carry), 1)
25417 // This eliminates the zext. This transformation is necessary because
25418 // ISD::SETCC is always legalized to i8.
25420 SDValue N0 = N->getOperand(0);
25421 EVT VT = N->getValueType(0);
25423 if (N0.getOpcode() == ISD::AND &&
25425 N0.getOperand(0).hasOneUse()) {
25426 SDValue N00 = N0.getOperand(0);
25427 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25428 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25429 if (!C || C->getZExtValue() != 1)
25431 return DAG.getNode(ISD::AND, dl, VT,
25432 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25433 N00.getOperand(0), N00.getOperand(1)),
25434 DAG.getConstant(1, dl, VT));
25438 if (N0.getOpcode() == ISD::TRUNCATE &&
25440 N0.getOperand(0).hasOneUse()) {
25441 SDValue N00 = N0.getOperand(0);
25442 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25443 return DAG.getNode(ISD::AND, dl, VT,
25444 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25445 N00.getOperand(0), N00.getOperand(1)),
25446 DAG.getConstant(1, dl, VT));
25450 if (VT.is256BitVector())
25451 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25454 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25455 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25456 // This exposes the zext to the udivrem lowering, so that it directly extends
25457 // from AH (which we otherwise need to do contortions to access).
25458 if (N0.getOpcode() == ISD::UDIVREM &&
25459 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25460 (VT == MVT::i32 || VT == MVT::i64)) {
25461 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25462 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25463 N0.getOperand(0), N0.getOperand(1));
25464 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25465 return R.getValue(1);
25471 // Optimize x == -y --> x+y == 0
25472 // x != -y --> x+y != 0
25473 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25474 const X86Subtarget* Subtarget) {
25475 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25476 SDValue LHS = N->getOperand(0);
25477 SDValue RHS = N->getOperand(1);
25478 EVT VT = N->getValueType(0);
25481 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25483 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25484 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25485 LHS.getOperand(1));
25486 return DAG.getSetCC(DL, N->getValueType(0), addV,
25487 DAG.getConstant(0, DL, addV.getValueType()), CC);
25489 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25491 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25492 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25493 RHS.getOperand(1));
25494 return DAG.getSetCC(DL, N->getValueType(0), addV,
25495 DAG.getConstant(0, DL, addV.getValueType()), CC);
25498 if (VT.getScalarType() == MVT::i1 &&
25499 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25501 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25502 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25503 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25505 if (!IsSEXT0 || !IsVZero1) {
25506 // Swap the operands and update the condition code.
25507 std::swap(LHS, RHS);
25508 CC = ISD::getSetCCSwappedOperands(CC);
25510 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25511 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25512 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25515 if (IsSEXT0 && IsVZero1) {
25516 assert(VT == LHS.getOperand(0).getValueType() &&
25517 "Uexpected operand type");
25518 if (CC == ISD::SETGT)
25519 return DAG.getConstant(0, DL, VT);
25520 if (CC == ISD::SETLE)
25521 return DAG.getConstant(1, DL, VT);
25522 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25523 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25525 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25526 "Unexpected condition code!");
25527 return LHS.getOperand(0);
25534 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25535 SelectionDAG &DAG) {
25537 MVT VT = Load->getSimpleValueType(0);
25538 MVT EVT = VT.getVectorElementType();
25539 SDValue Addr = Load->getOperand(1);
25540 SDValue NewAddr = DAG.getNode(
25541 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25542 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25543 Addr.getSimpleValueType()));
25546 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25547 DAG.getMachineFunction().getMachineMemOperand(
25548 Load->getMemOperand(), 0, EVT.getStoreSize()));
25552 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25553 const X86Subtarget *Subtarget) {
25555 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25556 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25557 "X86insertps is only defined for v4x32");
25559 SDValue Ld = N->getOperand(1);
25560 if (MayFoldLoad(Ld)) {
25561 // Extract the countS bits from the immediate so we can get the proper
25562 // address when narrowing the vector load to a specific element.
25563 // When the second source op is a memory address, insertps doesn't use
25564 // countS and just gets an f32 from that address.
25565 unsigned DestIndex =
25566 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25568 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25570 // Create this as a scalar to vector to match the instruction pattern.
25571 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25572 // countS bits are ignored when loading from memory on insertps, which
25573 // means we don't need to explicitly set them to 0.
25574 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25575 LoadScalarToVector, N->getOperand(2));
25580 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25581 SDValue V0 = N->getOperand(0);
25582 SDValue V1 = N->getOperand(1);
25584 EVT VT = N->getValueType(0);
25586 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25587 // operands and changing the mask to 1. This saves us a bunch of
25588 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25589 // x86InstrInfo knows how to commute this back after instruction selection
25590 // if it would help register allocation.
25592 // TODO: If optimizing for size or a processor that doesn't suffer from
25593 // partial register update stalls, this should be transformed into a MOVSD
25594 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25596 if (VT == MVT::v2f64)
25597 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25598 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25599 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25600 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25606 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25607 // as "sbb reg,reg", since it can be extended without zext and produces
25608 // an all-ones bit which is more useful than 0/1 in some cases.
25609 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25612 return DAG.getNode(ISD::AND, DL, VT,
25613 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25614 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25616 DAG.getConstant(1, DL, VT));
25617 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25618 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25619 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25620 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25624 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25625 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25626 TargetLowering::DAGCombinerInfo &DCI,
25627 const X86Subtarget *Subtarget) {
25629 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25630 SDValue EFLAGS = N->getOperand(1);
25632 if (CC == X86::COND_A) {
25633 // Try to convert COND_A into COND_B in an attempt to facilitate
25634 // materializing "setb reg".
25636 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25637 // cannot take an immediate as its first operand.
25639 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25640 EFLAGS.getValueType().isInteger() &&
25641 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25642 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25643 EFLAGS.getNode()->getVTList(),
25644 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25645 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25646 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25650 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25651 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25653 if (CC == X86::COND_B)
25654 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25656 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25657 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25658 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25664 // Optimize branch condition evaluation.
25666 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25667 TargetLowering::DAGCombinerInfo &DCI,
25668 const X86Subtarget *Subtarget) {
25670 SDValue Chain = N->getOperand(0);
25671 SDValue Dest = N->getOperand(1);
25672 SDValue EFLAGS = N->getOperand(3);
25673 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25675 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25676 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25677 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25684 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25685 SelectionDAG &DAG) {
25686 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25687 // optimize away operation when it's from a constant.
25689 // The general transformation is:
25690 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25691 // AND(VECTOR_CMP(x,y), constant2)
25692 // constant2 = UNARYOP(constant)
25694 // Early exit if this isn't a vector operation, the operand of the
25695 // unary operation isn't a bitwise AND, or if the sizes of the operations
25696 // aren't the same.
25697 EVT VT = N->getValueType(0);
25698 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25699 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25700 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25703 // Now check that the other operand of the AND is a constant. We could
25704 // make the transformation for non-constant splats as well, but it's unclear
25705 // that would be a benefit as it would not eliminate any operations, just
25706 // perform one more step in scalar code before moving to the vector unit.
25707 if (BuildVectorSDNode *BV =
25708 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25709 // Bail out if the vector isn't a constant.
25710 if (!BV->isConstant())
25713 // Everything checks out. Build up the new and improved node.
25715 EVT IntVT = BV->getValueType(0);
25716 // Create a new constant of the appropriate type for the transformed
25718 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25719 // The AND node needs bitcasts to/from an integer vector type around it.
25720 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
25721 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25722 N->getOperand(0)->getOperand(0), MaskConst);
25723 SDValue Res = DAG.getBitcast(VT, NewAnd);
25730 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25731 const X86Subtarget *Subtarget) {
25732 SDValue Op0 = N->getOperand(0);
25733 EVT VT = N->getValueType(0);
25734 EVT InVT = Op0.getValueType();
25735 EVT InSVT = InVT.getScalarType();
25736 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25738 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
25739 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
25740 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25742 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25743 InVT.getVectorNumElements());
25744 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
25746 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
25747 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
25749 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25755 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25756 const X86Subtarget *Subtarget) {
25757 // First try to optimize away the conversion entirely when it's
25758 // conditionally from a constant. Vectors only.
25759 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
25762 // Now move on to more general possibilities.
25763 SDValue Op0 = N->getOperand(0);
25764 EVT VT = N->getValueType(0);
25765 EVT InVT = Op0.getValueType();
25766 EVT InSVT = InVT.getScalarType();
25768 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
25769 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
25770 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25772 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25773 InVT.getVectorNumElements());
25774 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25775 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25778 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25779 // a 32-bit target where SSE doesn't support i64->FP operations.
25780 if (Op0.getOpcode() == ISD::LOAD) {
25781 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25782 EVT LdVT = Ld->getValueType(0);
25784 // This transformation is not supported if the result type is f16
25785 if (VT == MVT::f16)
25788 if (!Ld->isVolatile() && !VT.isVector() &&
25789 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25790 !Subtarget->is64Bit() && LdVT == MVT::i64) {
25791 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
25792 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
25793 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25800 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25801 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25802 X86TargetLowering::DAGCombinerInfo &DCI) {
25803 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25804 // the result is either zero or one (depending on the input carry bit).
25805 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25806 if (X86::isZeroNode(N->getOperand(0)) &&
25807 X86::isZeroNode(N->getOperand(1)) &&
25808 // We don't have a good way to replace an EFLAGS use, so only do this when
25810 SDValue(N, 1).use_empty()) {
25812 EVT VT = N->getValueType(0);
25813 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
25814 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25815 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25816 DAG.getConstant(X86::COND_B, DL,
25819 DAG.getConstant(1, DL, VT));
25820 return DCI.CombineTo(N, Res1, CarryOut);
25826 // fold (add Y, (sete X, 0)) -> adc 0, Y
25827 // (add Y, (setne X, 0)) -> sbb -1, Y
25828 // (sub (sete X, 0), Y) -> sbb 0, Y
25829 // (sub (setne X, 0), Y) -> adc -1, Y
25830 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25833 // Look through ZExts.
25834 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25835 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25838 SDValue SetCC = Ext.getOperand(0);
25839 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25842 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25843 if (CC != X86::COND_E && CC != X86::COND_NE)
25846 SDValue Cmp = SetCC.getOperand(1);
25847 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25848 !X86::isZeroNode(Cmp.getOperand(1)) ||
25849 !Cmp.getOperand(0).getValueType().isInteger())
25852 SDValue CmpOp0 = Cmp.getOperand(0);
25853 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25854 DAG.getConstant(1, DL, CmpOp0.getValueType()));
25856 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25857 if (CC == X86::COND_NE)
25858 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25859 DL, OtherVal.getValueType(), OtherVal,
25860 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
25862 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25863 DL, OtherVal.getValueType(), OtherVal,
25864 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
25867 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25868 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25869 const X86Subtarget *Subtarget) {
25870 EVT VT = N->getValueType(0);
25871 SDValue Op0 = N->getOperand(0);
25872 SDValue Op1 = N->getOperand(1);
25874 // Try to synthesize horizontal adds from adds of shuffles.
25875 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25876 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25877 isHorizontalBinOp(Op0, Op1, true))
25878 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25880 return OptimizeConditionalInDecrement(N, DAG);
25883 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25884 const X86Subtarget *Subtarget) {
25885 SDValue Op0 = N->getOperand(0);
25886 SDValue Op1 = N->getOperand(1);
25888 // X86 can't encode an immediate LHS of a sub. See if we can push the
25889 // negation into a preceding instruction.
25890 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25891 // If the RHS of the sub is a XOR with one use and a constant, invert the
25892 // immediate. Then add one to the LHS of the sub so we can turn
25893 // X-Y -> X+~Y+1, saving one register.
25894 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25895 isa<ConstantSDNode>(Op1.getOperand(1))) {
25896 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25897 EVT VT = Op0.getValueType();
25898 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25900 DAG.getConstant(~XorC, SDLoc(Op1), VT));
25901 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25902 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
25906 // Try to synthesize horizontal adds from adds of shuffles.
25907 EVT VT = N->getValueType(0);
25908 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25909 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25910 isHorizontalBinOp(Op0, Op1, true))
25911 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25913 return OptimizeConditionalInDecrement(N, DAG);
25916 /// performVZEXTCombine - Performs build vector combines
25917 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25918 TargetLowering::DAGCombinerInfo &DCI,
25919 const X86Subtarget *Subtarget) {
25921 MVT VT = N->getSimpleValueType(0);
25922 SDValue Op = N->getOperand(0);
25923 MVT OpVT = Op.getSimpleValueType();
25924 MVT OpEltVT = OpVT.getVectorElementType();
25925 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25927 // (vzext (bitcast (vzext (x)) -> (vzext x)
25929 while (V.getOpcode() == ISD::BITCAST)
25930 V = V.getOperand(0);
25932 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25933 MVT InnerVT = V.getSimpleValueType();
25934 MVT InnerEltVT = InnerVT.getVectorElementType();
25936 // If the element sizes match exactly, we can just do one larger vzext. This
25937 // is always an exact type match as vzext operates on integer types.
25938 if (OpEltVT == InnerEltVT) {
25939 assert(OpVT == InnerVT && "Types must match for vzext!");
25940 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25943 // The only other way we can combine them is if only a single element of the
25944 // inner vzext is used in the input to the outer vzext.
25945 if (InnerEltVT.getSizeInBits() < InputBits)
25948 // In this case, the inner vzext is completely dead because we're going to
25949 // only look at bits inside of the low element. Just do the outer vzext on
25950 // a bitcast of the input to the inner.
25951 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
25954 // Check if we can bypass extracting and re-inserting an element of an input
25955 // vector. Essentially:
25956 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25957 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25958 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25959 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25960 SDValue ExtractedV = V.getOperand(0);
25961 SDValue OrigV = ExtractedV.getOperand(0);
25962 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25963 if (ExtractIdx->getZExtValue() == 0) {
25964 MVT OrigVT = OrigV.getSimpleValueType();
25965 // Extract a subvector if necessary...
25966 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25967 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25968 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25969 OrigVT.getVectorNumElements() / Ratio);
25970 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25971 DAG.getIntPtrConstant(0, DL));
25973 Op = DAG.getBitcast(OpVT, OrigV);
25974 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25981 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25982 DAGCombinerInfo &DCI) const {
25983 SelectionDAG &DAG = DCI.DAG;
25984 switch (N->getOpcode()) {
25986 case ISD::EXTRACT_VECTOR_ELT:
25987 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25990 case X86ISD::SHRUNKBLEND:
25991 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25992 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
25993 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25994 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25995 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25996 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25997 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26000 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26001 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26002 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26003 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26004 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26005 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26006 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26007 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26008 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26009 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26010 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26011 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26013 case X86ISD::FOR: return PerformFORCombine(N, DAG);
26015 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26016 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26017 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26018 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26019 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26020 case ISD::ANY_EXTEND:
26021 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26022 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26023 case ISD::SIGN_EXTEND_INREG:
26024 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26025 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26026 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26027 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26028 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26029 case X86ISD::SHUFP: // Handle all target specific shuffles
26030 case X86ISD::PALIGNR:
26031 case X86ISD::UNPCKH:
26032 case X86ISD::UNPCKL:
26033 case X86ISD::MOVHLPS:
26034 case X86ISD::MOVLHPS:
26035 case X86ISD::PSHUFB:
26036 case X86ISD::PSHUFD:
26037 case X86ISD::PSHUFHW:
26038 case X86ISD::PSHUFLW:
26039 case X86ISD::MOVSS:
26040 case X86ISD::MOVSD:
26041 case X86ISD::VPERMILPI:
26042 case X86ISD::VPERM2X128:
26043 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26044 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26045 case X86ISD::INSERTPS: {
26046 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26047 return PerformINSERTPSCombine(N, DAG, Subtarget);
26050 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26056 /// isTypeDesirableForOp - Return true if the target has native support for
26057 /// the specified value type and it is 'desirable' to use the type for the
26058 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26059 /// instruction encodings are longer and some i16 instructions are slow.
26060 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26061 if (!isTypeLegal(VT))
26063 if (VT != MVT::i16)
26070 case ISD::SIGN_EXTEND:
26071 case ISD::ZERO_EXTEND:
26072 case ISD::ANY_EXTEND:
26085 /// IsDesirableToPromoteOp - This method query the target whether it is
26086 /// beneficial for dag combiner to promote the specified node. If true, it
26087 /// should return the desired promotion type by reference.
26088 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26089 EVT VT = Op.getValueType();
26090 if (VT != MVT::i16)
26093 bool Promote = false;
26094 bool Commute = false;
26095 switch (Op.getOpcode()) {
26098 LoadSDNode *LD = cast<LoadSDNode>(Op);
26099 // If the non-extending load has a single use and it's not live out, then it
26100 // might be folded.
26101 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26102 Op.hasOneUse()*/) {
26103 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26104 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26105 // The only case where we'd want to promote LOAD (rather then it being
26106 // promoted as an operand is when it's only use is liveout.
26107 if (UI->getOpcode() != ISD::CopyToReg)
26114 case ISD::SIGN_EXTEND:
26115 case ISD::ZERO_EXTEND:
26116 case ISD::ANY_EXTEND:
26121 SDValue N0 = Op.getOperand(0);
26122 // Look out for (store (shl (load), x)).
26123 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26136 SDValue N0 = Op.getOperand(0);
26137 SDValue N1 = Op.getOperand(1);
26138 if (!Commute && MayFoldLoad(N1))
26140 // Avoid disabling potential load folding opportunities.
26141 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26143 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26153 //===----------------------------------------------------------------------===//
26154 // X86 Inline Assembly Support
26155 //===----------------------------------------------------------------------===//
26157 // Helper to match a string separated by whitespace.
26158 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26159 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26161 for (StringRef Piece : Pieces) {
26162 if (!S.startswith(Piece)) // Check if the piece matches.
26165 S = S.substr(Piece.size());
26166 StringRef::size_type Pos = S.find_first_not_of(" \t");
26167 if (Pos == 0) // We matched a prefix.
26176 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26178 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26179 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26180 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26181 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26183 if (AsmPieces.size() == 3)
26185 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26192 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26193 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26195 std::string AsmStr = IA->getAsmString();
26197 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26198 if (!Ty || Ty->getBitWidth() % 16 != 0)
26201 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26202 SmallVector<StringRef, 4> AsmPieces;
26203 SplitString(AsmStr, AsmPieces, ";\n");
26205 switch (AsmPieces.size()) {
26206 default: return false;
26208 // FIXME: this should verify that we are targeting a 486 or better. If not,
26209 // we will turn this bswap into something that will be lowered to logical
26210 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26211 // lower so don't worry about this.
26213 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26214 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26215 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26216 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26217 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26218 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26219 // No need to check constraints, nothing other than the equivalent of
26220 // "=r,0" would be valid here.
26221 return IntrinsicLowering::LowerToByteSwap(CI);
26224 // rorw $$8, ${0:w} --> llvm.bswap.i16
26225 if (CI->getType()->isIntegerTy(16) &&
26226 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26227 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26228 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26230 StringRef ConstraintsStr = IA->getConstraintString();
26231 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26232 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26233 if (clobbersFlagRegisters(AsmPieces))
26234 return IntrinsicLowering::LowerToByteSwap(CI);
26238 if (CI->getType()->isIntegerTy(32) &&
26239 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26240 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26241 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26242 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26244 StringRef ConstraintsStr = IA->getConstraintString();
26245 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26246 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26247 if (clobbersFlagRegisters(AsmPieces))
26248 return IntrinsicLowering::LowerToByteSwap(CI);
26251 if (CI->getType()->isIntegerTy(64)) {
26252 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26253 if (Constraints.size() >= 2 &&
26254 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26255 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26256 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26257 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26258 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26259 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26260 return IntrinsicLowering::LowerToByteSwap(CI);
26268 /// getConstraintType - Given a constraint letter, return the type of
26269 /// constraint it is for this target.
26270 X86TargetLowering::ConstraintType
26271 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26272 if (Constraint.size() == 1) {
26273 switch (Constraint[0]) {
26284 return C_RegisterClass;
26308 return TargetLowering::getConstraintType(Constraint);
26311 /// Examine constraint type and operand type and determine a weight value.
26312 /// This object must already have been set up with the operand type
26313 /// and the current alternative constraint selected.
26314 TargetLowering::ConstraintWeight
26315 X86TargetLowering::getSingleConstraintMatchWeight(
26316 AsmOperandInfo &info, const char *constraint) const {
26317 ConstraintWeight weight = CW_Invalid;
26318 Value *CallOperandVal = info.CallOperandVal;
26319 // If we don't have a value, we can't do a match,
26320 // but allow it at the lowest weight.
26321 if (!CallOperandVal)
26323 Type *type = CallOperandVal->getType();
26324 // Look at the constraint type.
26325 switch (*constraint) {
26327 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26338 if (CallOperandVal->getType()->isIntegerTy())
26339 weight = CW_SpecificReg;
26344 if (type->isFloatingPointTy())
26345 weight = CW_SpecificReg;
26348 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26349 weight = CW_SpecificReg;
26353 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26354 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26355 weight = CW_Register;
26358 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26359 if (C->getZExtValue() <= 31)
26360 weight = CW_Constant;
26364 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26365 if (C->getZExtValue() <= 63)
26366 weight = CW_Constant;
26370 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26371 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26372 weight = CW_Constant;
26376 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26377 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26378 weight = CW_Constant;
26382 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26383 if (C->getZExtValue() <= 3)
26384 weight = CW_Constant;
26388 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26389 if (C->getZExtValue() <= 0xff)
26390 weight = CW_Constant;
26395 if (isa<ConstantFP>(CallOperandVal)) {
26396 weight = CW_Constant;
26400 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26401 if ((C->getSExtValue() >= -0x80000000LL) &&
26402 (C->getSExtValue() <= 0x7fffffffLL))
26403 weight = CW_Constant;
26407 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26408 if (C->getZExtValue() <= 0xffffffff)
26409 weight = CW_Constant;
26416 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26417 /// with another that has more specific requirements based on the type of the
26418 /// corresponding operand.
26419 const char *X86TargetLowering::
26420 LowerXConstraint(EVT ConstraintVT) const {
26421 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26422 // 'f' like normal targets.
26423 if (ConstraintVT.isFloatingPoint()) {
26424 if (Subtarget->hasSSE2())
26426 if (Subtarget->hasSSE1())
26430 return TargetLowering::LowerXConstraint(ConstraintVT);
26433 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26434 /// vector. If it is invalid, don't add anything to Ops.
26435 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26436 std::string &Constraint,
26437 std::vector<SDValue>&Ops,
26438 SelectionDAG &DAG) const {
26441 // Only support length 1 constraints for now.
26442 if (Constraint.length() > 1) return;
26444 char ConstraintLetter = Constraint[0];
26445 switch (ConstraintLetter) {
26448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26449 if (C->getZExtValue() <= 31) {
26450 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26451 Op.getValueType());
26457 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26458 if (C->getZExtValue() <= 63) {
26459 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26460 Op.getValueType());
26466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26467 if (isInt<8>(C->getSExtValue())) {
26468 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26469 Op.getValueType());
26475 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26476 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26477 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26478 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26479 Op.getValueType());
26485 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26486 if (C->getZExtValue() <= 3) {
26487 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26488 Op.getValueType());
26494 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26495 if (C->getZExtValue() <= 255) {
26496 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26497 Op.getValueType());
26503 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26504 if (C->getZExtValue() <= 127) {
26505 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26506 Op.getValueType());
26512 // 32-bit signed value
26513 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26514 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26515 C->getSExtValue())) {
26516 // Widen to 64 bits here to get it sign extended.
26517 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26520 // FIXME gcc accepts some relocatable values here too, but only in certain
26521 // memory models; it's complicated.
26526 // 32-bit unsigned value
26527 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26528 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26529 C->getZExtValue())) {
26530 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26531 Op.getValueType());
26535 // FIXME gcc accepts some relocatable values here too, but only in certain
26536 // memory models; it's complicated.
26540 // Literal immediates are always ok.
26541 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26542 // Widen to 64 bits here to get it sign extended.
26543 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26547 // In any sort of PIC mode addresses need to be computed at runtime by
26548 // adding in a register or some sort of table lookup. These can't
26549 // be used as immediates.
26550 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26553 // If we are in non-pic codegen mode, we allow the address of a global (with
26554 // an optional displacement) to be used with 'i'.
26555 GlobalAddressSDNode *GA = nullptr;
26556 int64_t Offset = 0;
26558 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26560 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26561 Offset += GA->getOffset();
26563 } else if (Op.getOpcode() == ISD::ADD) {
26564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26565 Offset += C->getZExtValue();
26566 Op = Op.getOperand(0);
26569 } else if (Op.getOpcode() == ISD::SUB) {
26570 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26571 Offset += -C->getZExtValue();
26572 Op = Op.getOperand(0);
26577 // Otherwise, this isn't something we can handle, reject it.
26581 const GlobalValue *GV = GA->getGlobal();
26582 // If we require an extra load to get this address, as in PIC mode, we
26583 // can't accept it.
26584 if (isGlobalStubReference(
26585 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26588 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26589 GA->getValueType(0), Offset);
26594 if (Result.getNode()) {
26595 Ops.push_back(Result);
26598 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26601 std::pair<unsigned, const TargetRegisterClass *>
26602 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26603 StringRef Constraint,
26605 // First, see if this is a constraint that directly corresponds to an LLVM
26607 if (Constraint.size() == 1) {
26608 // GCC Constraint Letters
26609 switch (Constraint[0]) {
26611 // TODO: Slight differences here in allocation order and leaving
26612 // RIP in the class. Do they matter any more here than they do
26613 // in the normal allocation?
26614 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26615 if (Subtarget->is64Bit()) {
26616 if (VT == MVT::i32 || VT == MVT::f32)
26617 return std::make_pair(0U, &X86::GR32RegClass);
26618 if (VT == MVT::i16)
26619 return std::make_pair(0U, &X86::GR16RegClass);
26620 if (VT == MVT::i8 || VT == MVT::i1)
26621 return std::make_pair(0U, &X86::GR8RegClass);
26622 if (VT == MVT::i64 || VT == MVT::f64)
26623 return std::make_pair(0U, &X86::GR64RegClass);
26626 // 32-bit fallthrough
26627 case 'Q': // Q_REGS
26628 if (VT == MVT::i32 || VT == MVT::f32)
26629 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26630 if (VT == MVT::i16)
26631 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26632 if (VT == MVT::i8 || VT == MVT::i1)
26633 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26634 if (VT == MVT::i64)
26635 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26637 case 'r': // GENERAL_REGS
26638 case 'l': // INDEX_REGS
26639 if (VT == MVT::i8 || VT == MVT::i1)
26640 return std::make_pair(0U, &X86::GR8RegClass);
26641 if (VT == MVT::i16)
26642 return std::make_pair(0U, &X86::GR16RegClass);
26643 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26644 return std::make_pair(0U, &X86::GR32RegClass);
26645 return std::make_pair(0U, &X86::GR64RegClass);
26646 case 'R': // LEGACY_REGS
26647 if (VT == MVT::i8 || VT == MVT::i1)
26648 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26649 if (VT == MVT::i16)
26650 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26651 if (VT == MVT::i32 || !Subtarget->is64Bit())
26652 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26653 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26654 case 'f': // FP Stack registers.
26655 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26656 // value to the correct fpstack register class.
26657 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26658 return std::make_pair(0U, &X86::RFP32RegClass);
26659 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26660 return std::make_pair(0U, &X86::RFP64RegClass);
26661 return std::make_pair(0U, &X86::RFP80RegClass);
26662 case 'y': // MMX_REGS if MMX allowed.
26663 if (!Subtarget->hasMMX()) break;
26664 return std::make_pair(0U, &X86::VR64RegClass);
26665 case 'Y': // SSE_REGS if SSE2 allowed
26666 if (!Subtarget->hasSSE2()) break;
26668 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26669 if (!Subtarget->hasSSE1()) break;
26671 switch (VT.SimpleTy) {
26673 // Scalar SSE types.
26676 return std::make_pair(0U, &X86::FR32RegClass);
26679 return std::make_pair(0U, &X86::FR64RegClass);
26687 return std::make_pair(0U, &X86::VR128RegClass);
26695 return std::make_pair(0U, &X86::VR256RegClass);
26700 return std::make_pair(0U, &X86::VR512RegClass);
26706 // Use the default implementation in TargetLowering to convert the register
26707 // constraint into a member of a register class.
26708 std::pair<unsigned, const TargetRegisterClass*> Res;
26709 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
26711 // Not found as a standard register?
26713 // Map st(0) -> st(7) -> ST0
26714 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26715 tolower(Constraint[1]) == 's' &&
26716 tolower(Constraint[2]) == 't' &&
26717 Constraint[3] == '(' &&
26718 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26719 Constraint[5] == ')' &&
26720 Constraint[6] == '}') {
26722 Res.first = X86::FP0+Constraint[4]-'0';
26723 Res.second = &X86::RFP80RegClass;
26727 // GCC allows "st(0)" to be called just plain "st".
26728 if (StringRef("{st}").equals_lower(Constraint)) {
26729 Res.first = X86::FP0;
26730 Res.second = &X86::RFP80RegClass;
26735 if (StringRef("{flags}").equals_lower(Constraint)) {
26736 Res.first = X86::EFLAGS;
26737 Res.second = &X86::CCRRegClass;
26741 // 'A' means EAX + EDX.
26742 if (Constraint == "A") {
26743 Res.first = X86::EAX;
26744 Res.second = &X86::GR32_ADRegClass;
26750 // Otherwise, check to see if this is a register class of the wrong value
26751 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26752 // turn into {ax},{dx}.
26753 // MVT::Other is used to specify clobber names.
26754 if (Res.second->hasType(VT) || VT == MVT::Other)
26755 return Res; // Correct type already, nothing to do.
26757 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
26758 // return "eax". This should even work for things like getting 64bit integer
26759 // registers when given an f64 type.
26760 const TargetRegisterClass *Class = Res.second;
26761 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
26762 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
26763 unsigned Size = VT.getSizeInBits();
26764 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
26765 : Size == 16 ? MVT::i16
26766 : Size == 32 ? MVT::i32
26767 : Size == 64 ? MVT::i64
26769 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
26771 Res.first = DestReg;
26772 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
26773 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
26774 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
26775 : &X86::GR64RegClass;
26776 assert(Res.second->contains(Res.first) && "Register in register class");
26778 // No register found/type mismatch.
26780 Res.second = nullptr;
26782 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
26783 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
26784 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
26785 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
26786 Class == &X86::VR512RegClass) {
26787 // Handle references to XMM physical registers that got mapped into the
26788 // wrong class. This can happen with constraints like {xmm0} where the
26789 // target independent register mapper will just pick the first match it can
26790 // find, ignoring the required type.
26792 if (VT == MVT::f32 || VT == MVT::i32)
26793 Res.second = &X86::FR32RegClass;
26794 else if (VT == MVT::f64 || VT == MVT::i64)
26795 Res.second = &X86::FR64RegClass;
26796 else if (X86::VR128RegClass.hasType(VT))
26797 Res.second = &X86::VR128RegClass;
26798 else if (X86::VR256RegClass.hasType(VT))
26799 Res.second = &X86::VR256RegClass;
26800 else if (X86::VR512RegClass.hasType(VT))
26801 Res.second = &X86::VR512RegClass;
26803 // Type mismatch and not a clobber: Return an error;
26805 Res.second = nullptr;
26812 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
26813 const AddrMode &AM, Type *Ty,
26814 unsigned AS) const {
26815 // Scaling factors are not free at all.
26816 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26817 // will take 2 allocations in the out of order engine instead of 1
26818 // for plain addressing mode, i.e. inst (reg1).
26820 // vaddps (%rsi,%drx), %ymm0, %ymm1
26821 // Requires two allocations (one for the load, one for the computation)
26823 // vaddps (%rsi), %ymm0, %ymm1
26824 // Requires just 1 allocation, i.e., freeing allocations for other operations
26825 // and having less micro operations to execute.
26827 // For some X86 architectures, this is even worse because for instance for
26828 // stores, the complex addressing mode forces the instruction to use the
26829 // "load" ports instead of the dedicated "store" port.
26830 // E.g., on Haswell:
26831 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26832 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26833 if (isLegalAddressingMode(DL, AM, Ty, AS))
26834 // Scale represents reg2 * scale, thus account for 1
26835 // as soon as we use a second register.
26836 return AM.Scale != 0;
26840 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
26841 // Integer division on x86 is expensive. However, when aggressively optimizing
26842 // for code size, we prefer to use a div instruction, as it is usually smaller
26843 // than the alternative sequence.
26844 // The exception to this is vector division. Since x86 doesn't have vector
26845 // integer division, leaving the division as-is is a loss even in terms of
26846 // size, because it will have to be scalarized, while the alternative code
26847 // sequence can be performed in vector form.
26848 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
26849 Attribute::MinSize);
26850 return OptSize && !VT.isVector();