1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/EHPersonalities.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::f128, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
303 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::f128, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
312 if (Subtarget->is64Bit())
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
315 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
317 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
319 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
320 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
321 // is. We should promote the value to 64-bits to solve this.
322 // This is what the CRT headers do - `fmodf` is an inline header
323 // function casting to f64 and calling `fmod`.
324 setOperationAction(ISD::FREM , MVT::f32 , Promote);
326 setOperationAction(ISD::FREM , MVT::f32 , Expand);
329 setOperationAction(ISD::FREM , MVT::f64 , Expand);
330 setOperationAction(ISD::FREM , MVT::f80 , Expand);
331 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
333 // Promote the i8 variants and force them on up to i32 which has a shorter
335 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
337 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
338 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
339 if (Subtarget->hasBMI()) {
340 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
342 if (Subtarget->is64Bit())
343 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
345 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
346 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
351 if (Subtarget->hasLZCNT()) {
352 // When promoting the i8 variants, force them to i32 for a shorter
354 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
357 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
360 if (Subtarget->is64Bit())
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
363 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
364 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
365 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
367 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
368 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
369 if (Subtarget->is64Bit()) {
370 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
371 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
375 // Special handling for half-precision floating point conversions.
376 // If we don't have F16C support, then lower half float conversions
377 // into library calls.
378 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
379 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
383 // There's never any support for operations beyond MVT::f32.
384 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
385 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
386 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
387 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
390 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
391 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
393 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
394 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
396 if (Subtarget->hasPOPCNT()) {
397 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
399 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
400 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
401 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
406 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
408 if (!Subtarget->hasMOVBE())
409 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
411 // These should be promoted to a larger select which is supported.
412 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
413 // X86 wants to expand cmov itself.
414 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
415 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
416 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
418 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
419 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
420 setOperationAction(ISD::SELECT , MVT::f128 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
424 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
425 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
426 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f128 , Custom);
428 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
429 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
431 if (Subtarget->is64Bit()) {
432 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
433 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
434 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
436 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
437 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
438 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
439 // support continuation, user-level threading, and etc.. As a result, no
440 // other SjLj exception interfaces are implemented and please don't build
441 // your own exception handling based on them.
442 // LLVM/Clang supports zero-cost DWARF exception handling.
443 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
444 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
447 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
448 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
449 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
450 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
451 if (Subtarget->is64Bit())
452 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
453 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
454 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
455 if (Subtarget->is64Bit()) {
456 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
457 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
458 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
459 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
460 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
462 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
463 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
466 if (Subtarget->is64Bit()) {
467 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
468 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
469 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
472 if (Subtarget->hasSSE1())
473 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
475 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
477 // Expand certain atomics
478 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
479 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
480 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
481 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
484 if (Subtarget->hasCmpxchg16b()) {
485 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
488 // FIXME - use subtarget debug flags
489 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
490 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
491 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
494 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
495 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
497 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
498 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
500 setOperationAction(ISD::TRAP, MVT::Other, Legal);
501 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
503 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
504 setOperationAction(ISD::VASTART , MVT::Other, Custom);
505 setOperationAction(ISD::VAEND , MVT::Other, Expand);
506 if (Subtarget->is64Bit()) {
507 setOperationAction(ISD::VAARG , MVT::Other, Custom);
508 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
510 // TargetInfo::CharPtrBuiltinVaList
511 setOperationAction(ISD::VAARG , MVT::Other, Expand);
512 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
515 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
516 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
518 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
520 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
521 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
522 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
524 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
525 // f32 and f64 use SSE.
526 // Set up the FP register classes.
527 addRegisterClass(MVT::f32, &X86::FR32RegClass);
528 addRegisterClass(MVT::f64, &X86::FR64RegClass);
530 // Use ANDPD to simulate FABS.
531 setOperationAction(ISD::FABS , MVT::f64, Custom);
532 setOperationAction(ISD::FABS , MVT::f32, Custom);
534 // Use XORP to simulate FNEG.
535 setOperationAction(ISD::FNEG , MVT::f64, Custom);
536 setOperationAction(ISD::FNEG , MVT::f32, Custom);
538 // Use ANDPD and ORPD to simulate FCOPYSIGN.
539 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
540 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
542 // Lower this to FGETSIGNx86 plus an AND.
543 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
544 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
546 // We don't support sin/cos/fmod
547 setOperationAction(ISD::FSIN , MVT::f64, Expand);
548 setOperationAction(ISD::FCOS , MVT::f64, Expand);
549 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
550 setOperationAction(ISD::FSIN , MVT::f32, Expand);
551 setOperationAction(ISD::FCOS , MVT::f32, Expand);
552 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
554 // Expand FP immediates into loads from the stack, except for the special
556 addLegalFPImmediate(APFloat(+0.0)); // xorpd
557 addLegalFPImmediate(APFloat(+0.0f)); // xorps
558 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
559 // Use SSE for f32, x87 for f64.
560 // Set up the FP register classes.
561 addRegisterClass(MVT::f32, &X86::FR32RegClass);
562 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
564 // Use ANDPS to simulate FABS.
565 setOperationAction(ISD::FABS , MVT::f32, Custom);
567 // Use XORP to simulate FNEG.
568 setOperationAction(ISD::FNEG , MVT::f32, Custom);
570 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
572 // Use ANDPS and ORPS to simulate FCOPYSIGN.
573 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
574 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
576 // We don't support sin/cos/fmod
577 setOperationAction(ISD::FSIN , MVT::f32, Expand);
578 setOperationAction(ISD::FCOS , MVT::f32, Expand);
579 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
581 // Special cases we handle for FP constants.
582 addLegalFPImmediate(APFloat(+0.0f)); // xorps
583 addLegalFPImmediate(APFloat(+0.0)); // FLD0
584 addLegalFPImmediate(APFloat(+1.0)); // FLD1
585 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
586 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
588 if (!TM.Options.UnsafeFPMath) {
589 setOperationAction(ISD::FSIN , MVT::f64, Expand);
590 setOperationAction(ISD::FCOS , MVT::f64, Expand);
591 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
593 } else if (!Subtarget->useSoftFloat()) {
594 // f32 and f64 in x87.
595 // Set up the FP register classes.
596 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
597 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
599 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
600 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
601 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
602 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
604 if (!TM.Options.UnsafeFPMath) {
605 setOperationAction(ISD::FSIN , MVT::f64, Expand);
606 setOperationAction(ISD::FSIN , MVT::f32, Expand);
607 setOperationAction(ISD::FCOS , MVT::f64, Expand);
608 setOperationAction(ISD::FCOS , MVT::f32, Expand);
609 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
610 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
612 addLegalFPImmediate(APFloat(+0.0)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
616 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
617 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
618 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
619 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
622 // We don't support FMA.
623 setOperationAction(ISD::FMA, MVT::f64, Expand);
624 setOperationAction(ISD::FMA, MVT::f32, Expand);
626 // Long double always uses X87, except f128 in MMX.
627 if (!Subtarget->useSoftFloat()) {
628 if (Subtarget->is64Bit() && Subtarget->hasMMX()) {
629 addRegisterClass(MVT::f128, &X86::FR128RegClass);
630 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
631 setOperationAction(ISD::FABS , MVT::f128, Custom);
632 setOperationAction(ISD::FNEG , MVT::f128, Custom);
633 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
636 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
637 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
638 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
640 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
641 addLegalFPImmediate(TmpFlt); // FLD0
643 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
646 APFloat TmpFlt2(+1.0);
647 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
649 addLegalFPImmediate(TmpFlt2); // FLD1
650 TmpFlt2.changeSign();
651 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
654 if (!TM.Options.UnsafeFPMath) {
655 setOperationAction(ISD::FSIN , MVT::f80, Expand);
656 setOperationAction(ISD::FCOS , MVT::f80, Expand);
657 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
660 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
661 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
662 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
663 setOperationAction(ISD::FRINT, MVT::f80, Expand);
664 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
665 setOperationAction(ISD::FMA, MVT::f80, Expand);
668 // Always use a library call for pow.
669 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
670 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
671 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
673 setOperationAction(ISD::FLOG, MVT::f80, Expand);
674 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
675 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
676 setOperationAction(ISD::FEXP, MVT::f80, Expand);
677 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
678 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
679 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
681 // First set operation action for all vector types to either promote
682 // (for widening) or expand (for scalarization). Then we will selectively
683 // turn on ones that can be effectively codegen'd.
684 for (MVT VT : MVT::vector_valuetypes()) {
685 setOperationAction(ISD::ADD , VT, Expand);
686 setOperationAction(ISD::SUB , VT, Expand);
687 setOperationAction(ISD::FADD, VT, Expand);
688 setOperationAction(ISD::FNEG, VT, Expand);
689 setOperationAction(ISD::FSUB, VT, Expand);
690 setOperationAction(ISD::MUL , VT, Expand);
691 setOperationAction(ISD::FMUL, VT, Expand);
692 setOperationAction(ISD::SDIV, VT, Expand);
693 setOperationAction(ISD::UDIV, VT, Expand);
694 setOperationAction(ISD::FDIV, VT, Expand);
695 setOperationAction(ISD::SREM, VT, Expand);
696 setOperationAction(ISD::UREM, VT, Expand);
697 setOperationAction(ISD::LOAD, VT, Expand);
698 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
699 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
700 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
701 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
702 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
703 setOperationAction(ISD::FABS, VT, Expand);
704 setOperationAction(ISD::FSIN, VT, Expand);
705 setOperationAction(ISD::FSINCOS, VT, Expand);
706 setOperationAction(ISD::FCOS, VT, Expand);
707 setOperationAction(ISD::FSINCOS, VT, Expand);
708 setOperationAction(ISD::FREM, VT, Expand);
709 setOperationAction(ISD::FMA, VT, Expand);
710 setOperationAction(ISD::FPOWI, VT, Expand);
711 setOperationAction(ISD::FSQRT, VT, Expand);
712 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
713 setOperationAction(ISD::FFLOOR, VT, Expand);
714 setOperationAction(ISD::FCEIL, VT, Expand);
715 setOperationAction(ISD::FTRUNC, VT, Expand);
716 setOperationAction(ISD::FRINT, VT, Expand);
717 setOperationAction(ISD::FNEARBYINT, VT, Expand);
718 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
719 setOperationAction(ISD::MULHS, VT, Expand);
720 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
721 setOperationAction(ISD::MULHU, VT, Expand);
722 setOperationAction(ISD::SDIVREM, VT, Expand);
723 setOperationAction(ISD::UDIVREM, VT, Expand);
724 setOperationAction(ISD::FPOW, VT, Expand);
725 setOperationAction(ISD::CTPOP, VT, Expand);
726 setOperationAction(ISD::CTTZ, VT, Expand);
727 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
728 setOperationAction(ISD::CTLZ, VT, Expand);
729 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
730 setOperationAction(ISD::SHL, VT, Expand);
731 setOperationAction(ISD::SRA, VT, Expand);
732 setOperationAction(ISD::SRL, VT, Expand);
733 setOperationAction(ISD::ROTL, VT, Expand);
734 setOperationAction(ISD::ROTR, VT, Expand);
735 setOperationAction(ISD::BSWAP, VT, Expand);
736 setOperationAction(ISD::SETCC, VT, Expand);
737 setOperationAction(ISD::FLOG, VT, Expand);
738 setOperationAction(ISD::FLOG2, VT, Expand);
739 setOperationAction(ISD::FLOG10, VT, Expand);
740 setOperationAction(ISD::FEXP, VT, Expand);
741 setOperationAction(ISD::FEXP2, VT, Expand);
742 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
743 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
744 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
745 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
746 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
747 setOperationAction(ISD::TRUNCATE, VT, Expand);
748 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
749 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
750 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
751 setOperationAction(ISD::VSELECT, VT, Expand);
752 setOperationAction(ISD::SELECT_CC, VT, Expand);
753 for (MVT InnerVT : MVT::vector_valuetypes()) {
754 setTruncStoreAction(InnerVT, VT, Expand);
756 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
757 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
759 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
760 // types, we have to deal with them whether we ask for Expansion or not.
761 // Setting Expand causes its own optimisation problems though, so leave
763 if (VT.getVectorElementType() == MVT::i1)
764 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
766 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
767 // split/scalarized right now.
768 if (VT.getVectorElementType() == MVT::f16)
769 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
773 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
774 // with -msoft-float, disable use of MMX as well.
775 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
776 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
777 // No operations on x86mmx supported, everything uses intrinsics.
780 // MMX-sized vectors (other than x86mmx) are expected to be expanded
781 // into smaller operations.
782 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
783 setOperationAction(ISD::MULHS, MMXTy, Expand);
784 setOperationAction(ISD::AND, MMXTy, Expand);
785 setOperationAction(ISD::OR, MMXTy, Expand);
786 setOperationAction(ISD::XOR, MMXTy, Expand);
787 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
788 setOperationAction(ISD::SELECT, MMXTy, Expand);
789 setOperationAction(ISD::BITCAST, MMXTy, Expand);
791 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
793 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
794 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
796 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
797 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
798 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
799 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
800 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
801 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
802 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
803 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
804 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
805 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
806 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
807 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
808 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
809 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
812 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
813 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
815 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
816 // registers cannot be used even for integer operations.
817 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
818 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
819 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
820 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
822 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
823 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
824 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
825 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
826 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
827 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
828 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
829 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
830 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
831 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
832 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
833 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
834 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
835 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
836 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
837 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
838 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
839 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
840 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
841 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
842 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
843 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
844 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
846 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
847 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
848 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
849 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
851 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
852 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
853 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
854 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
856 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
857 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
858 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
859 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
862 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
863 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
864 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
865 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
867 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
868 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
869 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
870 // ISD::CTTZ v2i64 - scalarization is faster.
871 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
872 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
873 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
874 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
877 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
878 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
879 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
880 setOperationAction(ISD::VSELECT, VT, Custom);
881 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
884 // We support custom legalizing of sext and anyext loads for specific
885 // memory vector types which we can load as a scalar (or sequence of
886 // scalars) and extend in-register to a legal 128-bit vector type. For sext
887 // loads these must work with a single scalar load.
888 for (MVT VT : MVT::integer_vector_valuetypes()) {
889 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
892 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
893 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
894 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
895 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
896 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
897 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
900 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
901 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
902 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
903 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
904 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
905 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
906 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
907 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
909 if (Subtarget->is64Bit()) {
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
911 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
914 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
915 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (Subtarget->hasXOP()) {
1054 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1055 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1056 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1057 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1058 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1059 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1060 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1061 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1064 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1065 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1066 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1067 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1068 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1069 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1070 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1072 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1073 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1074 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1077 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1078 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1079 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1080 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1081 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1084 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1086 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1087 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1089 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1090 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1091 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1092 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1093 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1094 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1095 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1096 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1097 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1098 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1099 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1100 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1102 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1103 // even though v8i16 is a legal type.
1104 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1105 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1106 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1108 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1109 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1110 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1112 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1113 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1115 for (MVT VT : MVT::fp_vector_valuetypes())
1116 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1118 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1119 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1121 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1122 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1124 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1125 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1127 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1128 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1129 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1130 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1132 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1133 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1134 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1136 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1137 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1139 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1140 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1141 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1142 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1143 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1144 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1145 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1146 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1147 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1149 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1150 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1151 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1152 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1154 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1155 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1156 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1157 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1158 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1160 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1161 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1163 if (Subtarget->hasAnyFMA()) {
1164 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1165 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1166 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1167 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1168 setOperationAction(ISD::FMA, MVT::f32, Legal);
1169 setOperationAction(ISD::FMA, MVT::f64, Legal);
1172 if (Subtarget->hasInt256()) {
1173 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1174 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1175 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1176 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1178 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1179 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1180 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1183 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1184 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1185 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1186 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1188 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1189 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1190 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1191 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1193 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1194 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1195 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1196 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1197 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1198 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1199 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1200 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1201 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1202 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1203 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1204 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1206 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1207 // when we have a 256bit-wide blend with immediate.
1208 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1210 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1211 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1212 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1213 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1214 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1215 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1216 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1218 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1220 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1223 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1225 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1226 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1227 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1228 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1232 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1235 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1236 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1237 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1238 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1240 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1241 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1243 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1244 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1245 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1247 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1248 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1249 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1250 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1251 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1254 // In the customized shift lowering, the legal cases in AVX2 will be
1256 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1257 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1259 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1260 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1262 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1263 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1265 // Custom lower several nodes for 256-bit types.
1266 for (MVT VT : MVT::vector_valuetypes()) {
1267 if (VT.getScalarSizeInBits() >= 32) {
1268 setOperationAction(ISD::MLOAD, VT, Legal);
1269 setOperationAction(ISD::MSTORE, VT, Legal);
1271 // Extract subvector is special because the value type
1272 // (result) is 128-bit but the source is 256-bit wide.
1273 if (VT.is128BitVector()) {
1274 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1276 // Do not attempt to custom lower other non-256-bit vectors
1277 if (!VT.is256BitVector())
1280 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1281 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1282 setOperationAction(ISD::VSELECT, VT, Custom);
1283 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1284 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1285 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1286 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1287 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1290 if (Subtarget->hasInt256())
1291 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1293 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1294 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1295 setOperationAction(ISD::AND, VT, Promote);
1296 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1297 setOperationAction(ISD::OR, VT, Promote);
1298 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1299 setOperationAction(ISD::XOR, VT, Promote);
1300 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1301 setOperationAction(ISD::LOAD, VT, Promote);
1302 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1303 setOperationAction(ISD::SELECT, VT, Promote);
1304 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1308 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1309 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1310 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1311 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1312 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1314 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1315 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1316 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1318 for (MVT VT : MVT::fp_vector_valuetypes())
1319 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1321 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1322 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1323 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1324 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1325 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1326 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1327 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1328 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1329 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1330 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1331 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1332 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1334 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1335 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1336 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1337 setOperationAction(ISD::XOR, MVT::i1, Legal);
1338 setOperationAction(ISD::OR, MVT::i1, Legal);
1339 setOperationAction(ISD::AND, MVT::i1, Legal);
1340 setOperationAction(ISD::SUB, MVT::i1, Custom);
1341 setOperationAction(ISD::ADD, MVT::i1, Custom);
1342 setOperationAction(ISD::MUL, MVT::i1, Custom);
1343 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1346 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1347 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1349 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1350 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1351 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1355 setOperationAction(ISD::FABS, MVT::v16f32, Custom);
1357 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1358 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1363 setOperationAction(ISD::FABS, MVT::v8f64, Custom);
1364 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1365 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1367 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1368 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1369 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1370 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1371 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1372 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1373 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1374 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1375 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1376 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1377 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1378 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1379 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1380 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1381 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1382 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1384 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1385 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1386 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1387 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1388 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1389 if (Subtarget->hasVLX()){
1390 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1391 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1392 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1393 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1394 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1396 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1397 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1398 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1399 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1400 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1402 setOperationAction(ISD::MLOAD, MVT::v8i32, Custom);
1403 setOperationAction(ISD::MLOAD, MVT::v8f32, Custom);
1404 setOperationAction(ISD::MSTORE, MVT::v8i32, Custom);
1405 setOperationAction(ISD::MSTORE, MVT::v8f32, Custom);
1407 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1408 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1409 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1410 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1411 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1412 if (Subtarget->hasDQI()) {
1413 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1414 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1418 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1419 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1420 if (Subtarget->hasVLX()) {
1421 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1423 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1431 if (Subtarget->hasVLX()) {
1432 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1433 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1434 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1435 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1436 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1437 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1439 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1441 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1444 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1445 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1446 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1447 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1448 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1453 if (Subtarget->hasDQI()) {
1454 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1455 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1457 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1458 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1459 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1460 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1461 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1462 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1463 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1464 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1465 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1466 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1468 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1474 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1475 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1477 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1479 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1480 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1481 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1482 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1483 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1484 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1485 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1486 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1488 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1489 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1490 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1492 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1493 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1494 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1495 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1496 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1497 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1498 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1499 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1501 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1502 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1504 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1505 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1507 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1509 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1510 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1512 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1513 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1515 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1516 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1518 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1519 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1520 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1521 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1522 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1523 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1525 if (Subtarget->hasCDI()) {
1526 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1527 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1531 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1532 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1533 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1534 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1535 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1540 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1543 if (Subtarget->hasVLX()) {
1544 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1545 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1546 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1547 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1548 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1549 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1553 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1554 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1555 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1556 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1558 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1559 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1560 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1561 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1562 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1563 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1564 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1565 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1567 } // Subtarget->hasCDI()
1569 if (Subtarget->hasDQI()) {
1570 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1571 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1572 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1574 // Custom lower several nodes.
1575 for (MVT VT : MVT::vector_valuetypes()) {
1576 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1578 setOperationAction(ISD::AND, VT, Legal);
1579 setOperationAction(ISD::OR, VT, Legal);
1580 setOperationAction(ISD::XOR, VT, Legal);
1582 if ((VT.is128BitVector() || VT.is256BitVector()) && EltSize >= 32) {
1583 setOperationAction(ISD::MGATHER, VT, Custom);
1584 setOperationAction(ISD::MSCATTER, VT, Custom);
1586 // Extract subvector is special because the value type
1587 // (result) is 256/128-bit but the source is 512-bit wide.
1588 if (VT.is128BitVector() || VT.is256BitVector()) {
1589 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1591 if (VT.getVectorElementType() == MVT::i1)
1592 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1594 // Do not attempt to custom lower other non-512-bit vectors
1595 if (!VT.is512BitVector())
1598 if (EltSize >= 32) {
1599 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1600 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1601 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1602 setOperationAction(ISD::VSELECT, VT, Legal);
1603 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1604 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1605 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1606 setOperationAction(ISD::MLOAD, VT, Legal);
1607 setOperationAction(ISD::MSTORE, VT, Legal);
1608 setOperationAction(ISD::MGATHER, VT, Legal);
1609 setOperationAction(ISD::MSCATTER, VT, Custom);
1612 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1613 setOperationAction(ISD::SELECT, VT, Promote);
1614 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1618 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1619 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1620 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1622 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1623 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1625 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1626 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1627 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1628 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1629 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1630 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1631 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1632 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1633 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1634 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1635 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1636 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1637 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1638 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1639 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1640 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1641 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1642 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1644 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1645 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1646 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1647 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1648 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1649 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1650 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1651 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1652 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1653 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1654 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1655 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1656 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1658 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1659 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1660 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1661 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1662 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1663 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1664 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1665 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1668 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1669 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1670 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1671 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1672 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1673 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1674 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1675 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1677 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1678 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1679 if (Subtarget->hasVLX())
1680 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1682 if (Subtarget->hasCDI()) {
1683 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1684 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1685 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1686 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1689 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1690 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1691 setOperationAction(ISD::VSELECT, VT, Legal);
1692 setOperationAction(ISD::SRL, VT, Custom);
1693 setOperationAction(ISD::SHL, VT, Custom);
1694 setOperationAction(ISD::SRA, VT, Custom);
1696 setOperationAction(ISD::AND, VT, Promote);
1697 AddPromotedToType (ISD::AND, VT, MVT::v8i64);
1698 setOperationAction(ISD::OR, VT, Promote);
1699 AddPromotedToType (ISD::OR, VT, MVT::v8i64);
1700 setOperationAction(ISD::XOR, VT, Promote);
1701 AddPromotedToType (ISD::XOR, VT, MVT::v8i64);
1705 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1706 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1707 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1709 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1710 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1711 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1712 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1713 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1714 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1715 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1716 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1717 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1718 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1719 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1720 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1722 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1723 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1724 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1725 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1726 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1727 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1728 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1729 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1731 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1732 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1733 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1734 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1735 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1736 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1737 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1738 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1741 // We want to custom lower some of our intrinsics.
1742 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1743 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1744 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1745 if (!Subtarget->is64Bit()) {
1746 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1747 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1750 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1751 // handle type legalization for these operations here.
1753 // FIXME: We really should do custom legalization for addition and
1754 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1755 // than generic legalization for 64-bit multiplication-with-overflow, though.
1756 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1757 if (VT == MVT::i64 && !Subtarget->is64Bit())
1759 // Add/Sub/Mul with overflow operations are custom lowered.
1760 setOperationAction(ISD::SADDO, VT, Custom);
1761 setOperationAction(ISD::UADDO, VT, Custom);
1762 setOperationAction(ISD::SSUBO, VT, Custom);
1763 setOperationAction(ISD::USUBO, VT, Custom);
1764 setOperationAction(ISD::SMULO, VT, Custom);
1765 setOperationAction(ISD::UMULO, VT, Custom);
1768 if (!Subtarget->is64Bit()) {
1769 // These libcalls are not available in 32-bit.
1770 setLibcallName(RTLIB::SHL_I128, nullptr);
1771 setLibcallName(RTLIB::SRL_I128, nullptr);
1772 setLibcallName(RTLIB::SRA_I128, nullptr);
1775 // Combine sin / cos into one node or libcall if possible.
1776 if (Subtarget->hasSinCos()) {
1777 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1778 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1779 if (Subtarget->isTargetDarwin()) {
1780 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1781 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1782 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1783 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1787 if (Subtarget->isTargetWin64()) {
1788 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1789 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1790 setOperationAction(ISD::SREM, MVT::i128, Custom);
1791 setOperationAction(ISD::UREM, MVT::i128, Custom);
1792 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1793 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1796 // We have target-specific dag combine patterns for the following nodes:
1797 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1798 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1799 setTargetDAGCombine(ISD::BITCAST);
1800 setTargetDAGCombine(ISD::VSELECT);
1801 setTargetDAGCombine(ISD::SELECT);
1802 setTargetDAGCombine(ISD::SHL);
1803 setTargetDAGCombine(ISD::SRA);
1804 setTargetDAGCombine(ISD::SRL);
1805 setTargetDAGCombine(ISD::OR);
1806 setTargetDAGCombine(ISD::AND);
1807 setTargetDAGCombine(ISD::ADD);
1808 setTargetDAGCombine(ISD::FADD);
1809 setTargetDAGCombine(ISD::FSUB);
1810 setTargetDAGCombine(ISD::FNEG);
1811 setTargetDAGCombine(ISD::FMA);
1812 setTargetDAGCombine(ISD::FMAXNUM);
1813 setTargetDAGCombine(ISD::SUB);
1814 setTargetDAGCombine(ISD::LOAD);
1815 setTargetDAGCombine(ISD::MLOAD);
1816 setTargetDAGCombine(ISD::STORE);
1817 setTargetDAGCombine(ISD::MSTORE);
1818 setTargetDAGCombine(ISD::TRUNCATE);
1819 setTargetDAGCombine(ISD::ZERO_EXTEND);
1820 setTargetDAGCombine(ISD::ANY_EXTEND);
1821 setTargetDAGCombine(ISD::SIGN_EXTEND);
1822 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1823 setTargetDAGCombine(ISD::SINT_TO_FP);
1824 setTargetDAGCombine(ISD::UINT_TO_FP);
1825 setTargetDAGCombine(ISD::SETCC);
1826 setTargetDAGCombine(ISD::BUILD_VECTOR);
1827 setTargetDAGCombine(ISD::MUL);
1828 setTargetDAGCombine(ISD::XOR);
1829 setTargetDAGCombine(ISD::MSCATTER);
1830 setTargetDAGCombine(ISD::MGATHER);
1832 computeRegisterProperties(Subtarget->getRegisterInfo());
1834 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1835 MaxStoresPerMemsetOptSize = 8;
1836 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1837 MaxStoresPerMemcpyOptSize = 4;
1838 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1839 MaxStoresPerMemmoveOptSize = 4;
1840 setPrefLoopAlignment(4); // 2^4 bytes.
1842 // A predictable cmov does not hurt on an in-order CPU.
1843 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1844 PredictableSelectIsExpensive = !Subtarget->isAtom();
1845 EnableExtLdPromotion = true;
1846 setPrefFunctionAlignment(4); // 2^4 bytes.
1848 verifyIntrinsicTables();
1851 // This has so far only been implemented for 64-bit MachO.
1852 bool X86TargetLowering::useLoadStackGuardNode() const {
1853 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1856 TargetLoweringBase::LegalizeTypeAction
1857 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1858 if (ExperimentalVectorWideningLegalization &&
1859 VT.getVectorNumElements() != 1 &&
1860 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1861 return TypeWidenVector;
1863 return TargetLoweringBase::getPreferredVectorAction(VT);
1866 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1869 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1871 if (VT.isSimple()) {
1872 MVT VVT = VT.getSimpleVT();
1873 const unsigned NumElts = VVT.getVectorNumElements();
1874 const MVT EltVT = VVT.getVectorElementType();
1875 if (VVT.is512BitVector()) {
1876 if (Subtarget->hasAVX512())
1877 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1878 EltVT == MVT::f32 || EltVT == MVT::f64)
1880 case 8: return MVT::v8i1;
1881 case 16: return MVT::v16i1;
1883 if (Subtarget->hasBWI())
1884 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1886 case 32: return MVT::v32i1;
1887 case 64: return MVT::v64i1;
1891 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1892 if (Subtarget->hasVLX())
1893 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1894 EltVT == MVT::f32 || EltVT == MVT::f64)
1896 case 2: return MVT::v2i1;
1897 case 4: return MVT::v4i1;
1898 case 8: return MVT::v8i1;
1900 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1901 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1903 case 8: return MVT::v8i1;
1904 case 16: return MVT::v16i1;
1905 case 32: return MVT::v32i1;
1910 return VT.changeVectorElementTypeToInteger();
1913 /// Helper for getByValTypeAlignment to determine
1914 /// the desired ByVal argument alignment.
1915 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1918 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1919 if (VTy->getBitWidth() == 128)
1921 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1922 unsigned EltAlign = 0;
1923 getMaxByValAlign(ATy->getElementType(), EltAlign);
1924 if (EltAlign > MaxAlign)
1925 MaxAlign = EltAlign;
1926 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1927 for (auto *EltTy : STy->elements()) {
1928 unsigned EltAlign = 0;
1929 getMaxByValAlign(EltTy, EltAlign);
1930 if (EltAlign > MaxAlign)
1931 MaxAlign = EltAlign;
1938 /// Return the desired alignment for ByVal aggregate
1939 /// function arguments in the caller parameter area. For X86, aggregates
1940 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1941 /// are at 4-byte boundaries.
1942 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1943 const DataLayout &DL) const {
1944 if (Subtarget->is64Bit()) {
1945 // Max of 8 and alignment of type.
1946 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1953 if (Subtarget->hasSSE1())
1954 getMaxByValAlign(Ty, Align);
1958 /// Returns the target specific optimal type for load
1959 /// and store operations as a result of memset, memcpy, and memmove
1960 /// lowering. If DstAlign is zero that means it's safe to destination
1961 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1962 /// means there isn't a need to check it against alignment requirement,
1963 /// probably because the source does not need to be loaded. If 'IsMemset' is
1964 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1965 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1966 /// source is constant so it does not need to be loaded.
1967 /// It returns EVT::Other if the type should be determined using generic
1968 /// target-independent logic.
1970 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1971 unsigned DstAlign, unsigned SrcAlign,
1972 bool IsMemset, bool ZeroMemset,
1974 MachineFunction &MF) const {
1975 const Function *F = MF.getFunction();
1976 if ((!IsMemset || ZeroMemset) &&
1977 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1979 (!Subtarget->isUnalignedMem16Slow() ||
1980 ((DstAlign == 0 || DstAlign >= 16) &&
1981 (SrcAlign == 0 || SrcAlign >= 16)))) {
1983 // FIXME: Check if unaligned 32-byte accesses are slow.
1984 if (Subtarget->hasInt256())
1986 if (Subtarget->hasFp256())
1989 if (Subtarget->hasSSE2())
1991 if (Subtarget->hasSSE1())
1993 } else if (!MemcpyStrSrc && Size >= 8 &&
1994 !Subtarget->is64Bit() &&
1995 Subtarget->hasSSE2()) {
1996 // Do not use f64 to lower memcpy if source is string constant. It's
1997 // better to use i32 to avoid the loads.
2001 // This is a compromise. If we reach here, unaligned accesses may be slow on
2002 // this target. However, creating smaller, aligned accesses could be even
2003 // slower and would certainly be a lot more code.
2004 if (Subtarget->is64Bit() && Size >= 8)
2009 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2011 return X86ScalarSSEf32;
2012 else if (VT == MVT::f64)
2013 return X86ScalarSSEf64;
2018 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
2023 switch (VT.getSizeInBits()) {
2025 // 8-byte and under are always assumed to be fast.
2029 *Fast = !Subtarget->isUnalignedMem16Slow();
2032 *Fast = !Subtarget->isUnalignedMem32Slow();
2034 // TODO: What about AVX-512 (512-bit) accesses?
2037 // Misaligned accesses of any size are always allowed.
2041 /// Return the entry encoding for a jump table in the
2042 /// current function. The returned value is a member of the
2043 /// MachineJumpTableInfo::JTEntryKind enum.
2044 unsigned X86TargetLowering::getJumpTableEncoding() const {
2045 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2047 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2048 Subtarget->isPICStyleGOT())
2049 return MachineJumpTableInfo::EK_Custom32;
2051 // Otherwise, use the normal jump table encoding heuristics.
2052 return TargetLowering::getJumpTableEncoding();
2055 bool X86TargetLowering::useSoftFloat() const {
2056 return Subtarget->useSoftFloat();
2060 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2061 const MachineBasicBlock *MBB,
2062 unsigned uid,MCContext &Ctx) const{
2063 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2064 Subtarget->isPICStyleGOT());
2065 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2067 return MCSymbolRefExpr::create(MBB->getSymbol(),
2068 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2071 /// Returns relocation base for the given PIC jumptable.
2072 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2073 SelectionDAG &DAG) const {
2074 if (!Subtarget->is64Bit())
2075 // This doesn't have SDLoc associated with it, but is not really the
2076 // same as a Register.
2077 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2078 getPointerTy(DAG.getDataLayout()));
2082 /// This returns the relocation base for the given PIC jumptable,
2083 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2084 const MCExpr *X86TargetLowering::
2085 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2086 MCContext &Ctx) const {
2087 // X86-64 uses RIP relative addressing based on the jump table label.
2088 if (Subtarget->isPICStyleRIPRel())
2089 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2091 // Otherwise, the reference is relative to the PIC base.
2092 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2095 std::pair<const TargetRegisterClass *, uint8_t>
2096 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2098 const TargetRegisterClass *RRC = nullptr;
2100 switch (VT.SimpleTy) {
2102 return TargetLowering::findRepresentativeClass(TRI, VT);
2103 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2104 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2107 RRC = &X86::VR64RegClass;
2109 case MVT::f32: case MVT::f64:
2110 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2111 case MVT::v4f32: case MVT::v2f64:
2112 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2114 RRC = &X86::VR128RegClass;
2117 return std::make_pair(RRC, Cost);
2120 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2121 unsigned &Offset) const {
2122 if (!Subtarget->isTargetLinux())
2125 if (Subtarget->is64Bit()) {
2126 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2128 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2140 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2141 if (!Subtarget->isTargetAndroid())
2142 return TargetLowering::getSafeStackPointerLocation(IRB);
2144 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2145 // definition of TLS_SLOT_SAFESTACK in
2146 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2147 unsigned AddressSpace, Offset;
2148 if (Subtarget->is64Bit()) {
2149 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2151 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2161 return ConstantExpr::getIntToPtr(
2162 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2163 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2166 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2167 unsigned DestAS) const {
2168 assert(SrcAS != DestAS && "Expected different address spaces!");
2170 return SrcAS < 256 && DestAS < 256;
2173 //===----------------------------------------------------------------------===//
2174 // Return Value Calling Convention Implementation
2175 //===----------------------------------------------------------------------===//
2177 #include "X86GenCallingConv.inc"
2179 bool X86TargetLowering::CanLowerReturn(
2180 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2181 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2182 SmallVector<CCValAssign, 16> RVLocs;
2183 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2184 return CCInfo.CheckReturn(Outs, RetCC_X86);
2187 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2188 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2193 X86TargetLowering::LowerReturn(SDValue Chain,
2194 CallingConv::ID CallConv, bool isVarArg,
2195 const SmallVectorImpl<ISD::OutputArg> &Outs,
2196 const SmallVectorImpl<SDValue> &OutVals,
2197 SDLoc dl, SelectionDAG &DAG) const {
2198 MachineFunction &MF = DAG.getMachineFunction();
2199 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2201 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2202 report_fatal_error("X86 interrupts may not return any value");
2204 SmallVector<CCValAssign, 16> RVLocs;
2205 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2206 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2209 SmallVector<SDValue, 6> RetOps;
2210 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2211 // Operand #1 = Bytes To Pop
2212 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2215 // Copy the result values into the output registers.
2216 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2217 CCValAssign &VA = RVLocs[i];
2218 assert(VA.isRegLoc() && "Can only return in registers!");
2219 SDValue ValToCopy = OutVals[i];
2220 EVT ValVT = ValToCopy.getValueType();
2222 // Promote values to the appropriate types.
2223 if (VA.getLocInfo() == CCValAssign::SExt)
2224 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2225 else if (VA.getLocInfo() == CCValAssign::ZExt)
2226 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2227 else if (VA.getLocInfo() == CCValAssign::AExt) {
2228 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2229 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2231 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2233 else if (VA.getLocInfo() == CCValAssign::BCvt)
2234 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2236 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2237 "Unexpected FP-extend for return value.");
2239 // If this is x86-64, and we disabled SSE, we can't return FP values,
2240 // or SSE or MMX vectors.
2241 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2242 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2243 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2244 report_fatal_error("SSE register return with SSE disabled");
2246 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2247 // llvm-gcc has never done it right and no one has noticed, so this
2248 // should be OK for now.
2249 if (ValVT == MVT::f64 &&
2250 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2251 report_fatal_error("SSE2 register return with SSE2 disabled");
2253 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2254 // the RET instruction and handled by the FP Stackifier.
2255 if (VA.getLocReg() == X86::FP0 ||
2256 VA.getLocReg() == X86::FP1) {
2257 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2258 // change the value to the FP stack register class.
2259 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2260 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2261 RetOps.push_back(ValToCopy);
2262 // Don't emit a copytoreg.
2266 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2267 // which is returned in RAX / RDX.
2268 if (Subtarget->is64Bit()) {
2269 if (ValVT == MVT::x86mmx) {
2270 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2271 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2272 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2274 // If we don't have SSE2 available, convert to v4f32 so the generated
2275 // register is legal.
2276 if (!Subtarget->hasSSE2())
2277 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2282 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2283 Flag = Chain.getValue(1);
2284 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2287 // All x86 ABIs require that for returning structs by value we copy
2288 // the sret argument into %rax/%eax (depending on ABI) for the return.
2289 // We saved the argument into a virtual register in the entry block,
2290 // so now we copy the value out and into %rax/%eax.
2292 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2293 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2294 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2295 // either case FuncInfo->setSRetReturnReg() will have been called.
2296 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2297 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2298 getPointerTy(MF.getDataLayout()));
2301 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2302 X86::RAX : X86::EAX;
2303 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2304 Flag = Chain.getValue(1);
2306 // RAX/EAX now acts like a return value.
2308 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2311 RetOps[0] = Chain; // Update chain.
2313 // Add the flag if we have it.
2315 RetOps.push_back(Flag);
2317 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2318 if (CallConv == CallingConv::X86_INTR)
2319 opcode = X86ISD::IRET;
2320 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2323 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2324 if (N->getNumValues() != 1)
2326 if (!N->hasNUsesOfValue(1, 0))
2329 SDValue TCChain = Chain;
2330 SDNode *Copy = *N->use_begin();
2331 if (Copy->getOpcode() == ISD::CopyToReg) {
2332 // If the copy has a glue operand, we conservatively assume it isn't safe to
2333 // perform a tail call.
2334 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2336 TCChain = Copy->getOperand(0);
2337 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2340 bool HasRet = false;
2341 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2343 if (UI->getOpcode() != X86ISD::RET_FLAG)
2345 // If we are returning more than one value, we can definitely
2346 // not make a tail call see PR19530
2347 if (UI->getNumOperands() > 4)
2349 if (UI->getNumOperands() == 4 &&
2350 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2363 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2364 ISD::NodeType ExtendKind) const {
2366 // TODO: Is this also valid on 32-bit?
2367 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2368 ReturnMVT = MVT::i8;
2370 ReturnMVT = MVT::i32;
2372 EVT MinVT = getRegisterType(Context, ReturnMVT);
2373 return VT.bitsLT(MinVT) ? MinVT : VT;
2376 /// Lower the result values of a call into the
2377 /// appropriate copies out of appropriate physical registers.
2380 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2381 CallingConv::ID CallConv, bool isVarArg,
2382 const SmallVectorImpl<ISD::InputArg> &Ins,
2383 SDLoc dl, SelectionDAG &DAG,
2384 SmallVectorImpl<SDValue> &InVals) const {
2386 // Assign locations to each value returned by this call.
2387 SmallVector<CCValAssign, 16> RVLocs;
2388 bool Is64Bit = Subtarget->is64Bit();
2389 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2391 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2393 // Copy all of the result registers out of their specified physreg.
2394 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2395 CCValAssign &VA = RVLocs[i];
2396 EVT CopyVT = VA.getLocVT();
2398 // If this is x86-64, and we disabled SSE, we can't return FP values
2399 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2400 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2401 report_fatal_error("SSE register return with SSE disabled");
2404 // If we prefer to use the value in xmm registers, copy it out as f80 and
2405 // use a truncate to move it from fp stack reg to xmm reg.
2406 bool RoundAfterCopy = false;
2407 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2408 isScalarFPTypeInSSEReg(VA.getValVT())) {
2410 RoundAfterCopy = (CopyVT != VA.getLocVT());
2413 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2414 CopyVT, InFlag).getValue(1);
2415 SDValue Val = Chain.getValue(0);
2418 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2419 // This truncation won't change the value.
2420 DAG.getIntPtrConstant(1, dl));
2422 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2423 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2425 InFlag = Chain.getValue(2);
2426 InVals.push_back(Val);
2432 //===----------------------------------------------------------------------===//
2433 // C & StdCall & Fast Calling Convention implementation
2434 //===----------------------------------------------------------------------===//
2435 // StdCall calling convention seems to be standard for many Windows' API
2436 // routines and around. It differs from C calling convention just a little:
2437 // callee should clean up the stack, not caller. Symbols should be also
2438 // decorated in some fancy way :) It doesn't support any vector arguments.
2439 // For info on fast calling convention see Fast Calling Convention (tail call)
2440 // implementation LowerX86_32FastCCCallTo.
2442 /// CallIsStructReturn - Determines whether a call uses struct return
2444 enum StructReturnType {
2449 static StructReturnType
2450 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2452 return NotStructReturn;
2454 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2455 if (!Flags.isSRet())
2456 return NotStructReturn;
2457 if (Flags.isInReg())
2458 return RegStructReturn;
2459 return StackStructReturn;
2462 /// Determines whether a function uses struct return semantics.
2463 static StructReturnType
2464 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2466 return NotStructReturn;
2468 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2469 if (!Flags.isSRet())
2470 return NotStructReturn;
2471 if (Flags.isInReg())
2472 return RegStructReturn;
2473 return StackStructReturn;
2476 /// Make a copy of an aggregate at address specified by "Src" to address
2477 /// "Dst" with size and alignment information specified by the specific
2478 /// parameter attribute. The copy will be passed as a byval function parameter.
2480 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2481 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2483 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2485 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2486 /*isVolatile*/false, /*AlwaysInline=*/true,
2487 /*isTailCall*/false,
2488 MachinePointerInfo(), MachinePointerInfo());
2491 /// Return true if the calling convention is one that we can guarantee TCO for.
2492 static bool canGuaranteeTCO(CallingConv::ID CC) {
2493 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2494 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2497 /// Return true if we might ever do TCO for calls with this calling convention.
2498 static bool mayTailCallThisCC(CallingConv::ID CC) {
2500 // C calling conventions:
2501 case CallingConv::C:
2502 case CallingConv::X86_64_Win64:
2503 case CallingConv::X86_64_SysV:
2504 // Callee pop conventions:
2505 case CallingConv::X86_ThisCall:
2506 case CallingConv::X86_StdCall:
2507 case CallingConv::X86_VectorCall:
2508 case CallingConv::X86_FastCall:
2511 return canGuaranteeTCO(CC);
2515 /// Return true if the function is being made into a tailcall target by
2516 /// changing its ABI.
2517 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2518 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2521 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2523 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2524 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2528 CallingConv::ID CalleeCC = CS.getCallingConv();
2529 if (!mayTailCallThisCC(CalleeCC))
2536 X86TargetLowering::LowerMemArgument(SDValue Chain,
2537 CallingConv::ID CallConv,
2538 const SmallVectorImpl<ISD::InputArg> &Ins,
2539 SDLoc dl, SelectionDAG &DAG,
2540 const CCValAssign &VA,
2541 MachineFrameInfo *MFI,
2543 // Create the nodes corresponding to a load from this parameter slot.
2544 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2545 bool AlwaysUseMutable = shouldGuaranteeTCO(
2546 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2547 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2550 // If value is passed by pointer we have address passed instead of the value
2552 bool ExtendedInMem = VA.isExtInLoc() &&
2553 VA.getValVT().getScalarType() == MVT::i1;
2555 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2556 ValVT = VA.getLocVT();
2558 ValVT = VA.getValVT();
2560 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
2561 // taken by a return address.
2563 if (CallConv == CallingConv::X86_INTR) {
2564 const X86Subtarget& Subtarget =
2565 static_cast<const X86Subtarget&>(DAG.getSubtarget());
2566 // X86 interrupts may take one or two arguments.
2567 // On the stack there will be no return address as in regular call.
2568 // Offset of last argument need to be set to -4/-8 bytes.
2569 // Where offset of the first argument out of two, should be set to 0 bytes.
2570 Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2573 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2574 // changed with more analysis.
2575 // In case of tail call optimization mark all arguments mutable. Since they
2576 // could be overwritten by lowering of arguments in case of a tail call.
2577 if (Flags.isByVal()) {
2578 unsigned Bytes = Flags.getByValSize();
2579 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2580 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2581 // Adjust SP offset of interrupt parameter.
2582 if (CallConv == CallingConv::X86_INTR) {
2583 MFI->setObjectOffset(FI, Offset);
2585 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2587 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2588 VA.getLocMemOffset(), isImmutable);
2589 // Adjust SP offset of interrupt parameter.
2590 if (CallConv == CallingConv::X86_INTR) {
2591 MFI->setObjectOffset(FI, Offset);
2594 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2595 SDValue Val = DAG.getLoad(
2596 ValVT, dl, Chain, FIN,
2597 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2599 return ExtendedInMem ?
2600 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2604 // FIXME: Get this from tablegen.
2605 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2606 const X86Subtarget *Subtarget) {
2607 assert(Subtarget->is64Bit());
2609 if (Subtarget->isCallingConvWin64(CallConv)) {
2610 static const MCPhysReg GPR64ArgRegsWin64[] = {
2611 X86::RCX, X86::RDX, X86::R8, X86::R9
2613 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2616 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2617 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2619 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2622 // FIXME: Get this from tablegen.
2623 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2624 CallingConv::ID CallConv,
2625 const X86Subtarget *Subtarget) {
2626 assert(Subtarget->is64Bit());
2627 if (Subtarget->isCallingConvWin64(CallConv)) {
2628 // The XMM registers which might contain var arg parameters are shadowed
2629 // in their paired GPR. So we only need to save the GPR to their home
2631 // TODO: __vectorcall will change this.
2635 const Function *Fn = MF.getFunction();
2636 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2637 bool isSoftFloat = Subtarget->useSoftFloat();
2638 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2639 "SSE register cannot be used when SSE is disabled!");
2640 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2641 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2645 static const MCPhysReg XMMArgRegs64Bit[] = {
2646 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2647 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2649 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2652 SDValue X86TargetLowering::LowerFormalArguments(
2653 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2654 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2655 SmallVectorImpl<SDValue> &InVals) const {
2656 MachineFunction &MF = DAG.getMachineFunction();
2657 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2658 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2660 const Function* Fn = MF.getFunction();
2661 if (Fn->hasExternalLinkage() &&
2662 Subtarget->isTargetCygMing() &&
2663 Fn->getName() == "main")
2664 FuncInfo->setForceFramePointer(true);
2666 MachineFrameInfo *MFI = MF.getFrameInfo();
2667 bool Is64Bit = Subtarget->is64Bit();
2668 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2670 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2671 "Var args not supported with calling convention fastcc, ghc or hipe");
2673 if (CallConv == CallingConv::X86_INTR) {
2674 bool isLegal = Ins.size() == 1 ||
2675 (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||
2676 (!Is64Bit && Ins[1].VT == MVT::i32)));
2678 report_fatal_error("X86 interrupts may take one or two arguments");
2681 // Assign locations to all of the incoming arguments.
2682 SmallVector<CCValAssign, 16> ArgLocs;
2683 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2685 // Allocate shadow area for Win64
2687 CCInfo.AllocateStack(32, 8);
2689 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2691 unsigned LastVal = ~0U;
2693 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2694 CCValAssign &VA = ArgLocs[i];
2695 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2697 assert(VA.getValNo() != LastVal &&
2698 "Don't support value assigned to multiple locs yet");
2700 LastVal = VA.getValNo();
2702 if (VA.isRegLoc()) {
2703 EVT RegVT = VA.getLocVT();
2704 const TargetRegisterClass *RC;
2705 if (RegVT == MVT::i32)
2706 RC = &X86::GR32RegClass;
2707 else if (Is64Bit && RegVT == MVT::i64)
2708 RC = &X86::GR64RegClass;
2709 else if (RegVT == MVT::f32)
2710 RC = &X86::FR32RegClass;
2711 else if (RegVT == MVT::f64)
2712 RC = &X86::FR64RegClass;
2713 else if (RegVT == MVT::f128)
2714 RC = &X86::FR128RegClass;
2715 else if (RegVT.is512BitVector())
2716 RC = &X86::VR512RegClass;
2717 else if (RegVT.is256BitVector())
2718 RC = &X86::VR256RegClass;
2719 else if (RegVT.is128BitVector())
2720 RC = &X86::VR128RegClass;
2721 else if (RegVT == MVT::x86mmx)
2722 RC = &X86::VR64RegClass;
2723 else if (RegVT == MVT::i1)
2724 RC = &X86::VK1RegClass;
2725 else if (RegVT == MVT::v8i1)
2726 RC = &X86::VK8RegClass;
2727 else if (RegVT == MVT::v16i1)
2728 RC = &X86::VK16RegClass;
2729 else if (RegVT == MVT::v32i1)
2730 RC = &X86::VK32RegClass;
2731 else if (RegVT == MVT::v64i1)
2732 RC = &X86::VK64RegClass;
2734 llvm_unreachable("Unknown argument type!");
2736 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2737 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2739 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2740 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2742 if (VA.getLocInfo() == CCValAssign::SExt)
2743 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2744 DAG.getValueType(VA.getValVT()));
2745 else if (VA.getLocInfo() == CCValAssign::ZExt)
2746 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2747 DAG.getValueType(VA.getValVT()));
2748 else if (VA.getLocInfo() == CCValAssign::BCvt)
2749 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2751 if (VA.isExtInLoc()) {
2752 // Handle MMX values passed in XMM regs.
2753 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2754 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2756 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2759 assert(VA.isMemLoc());
2760 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2763 // If value is passed via pointer - do a load.
2764 if (VA.getLocInfo() == CCValAssign::Indirect)
2765 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2766 MachinePointerInfo(), false, false, false, 0);
2768 InVals.push_back(ArgValue);
2771 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2772 // All x86 ABIs require that for returning structs by value we copy the
2773 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2774 // the argument into a virtual register so that we can access it from the
2776 if (Ins[i].Flags.isSRet()) {
2777 unsigned Reg = FuncInfo->getSRetReturnReg();
2779 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2780 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2781 FuncInfo->setSRetReturnReg(Reg);
2783 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2784 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2789 unsigned StackSize = CCInfo.getNextStackOffset();
2790 // Align stack specially for tail calls.
2791 if (shouldGuaranteeTCO(CallConv,
2792 MF.getTarget().Options.GuaranteedTailCallOpt))
2793 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2795 // If the function takes variable number of arguments, make a frame index for
2796 // the start of the first vararg value... for expansion of llvm.va_start. We
2797 // can skip this if there are no va_start calls.
2798 if (MFI->hasVAStart() &&
2799 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2800 CallConv != CallingConv::X86_ThisCall))) {
2801 FuncInfo->setVarArgsFrameIndex(
2802 MFI->CreateFixedObject(1, StackSize, true));
2805 // Figure out if XMM registers are in use.
2806 assert(!(Subtarget->useSoftFloat() &&
2807 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2808 "SSE register cannot be used when SSE is disabled!");
2810 // 64-bit calling conventions support varargs and register parameters, so we
2811 // have to do extra work to spill them in the prologue.
2812 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2813 // Find the first unallocated argument registers.
2814 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2815 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2816 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2817 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2818 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2819 "SSE register cannot be used when SSE is disabled!");
2821 // Gather all the live in physical registers.
2822 SmallVector<SDValue, 6> LiveGPRs;
2823 SmallVector<SDValue, 8> LiveXMMRegs;
2825 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2826 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2828 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2830 if (!ArgXMMs.empty()) {
2831 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2832 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2833 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2834 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2835 LiveXMMRegs.push_back(
2836 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2841 // Get to the caller-allocated home save location. Add 8 to account
2842 // for the return address.
2843 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2844 FuncInfo->setRegSaveFrameIndex(
2845 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2846 // Fixup to set vararg frame on shadow area (4 x i64).
2848 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2850 // For X86-64, if there are vararg parameters that are passed via
2851 // registers, then we must store them to their spots on the stack so
2852 // they may be loaded by deferencing the result of va_next.
2853 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2854 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2855 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2856 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2859 // Store the integer parameter registers.
2860 SmallVector<SDValue, 8> MemOps;
2861 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2862 getPointerTy(DAG.getDataLayout()));
2863 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2864 for (SDValue Val : LiveGPRs) {
2865 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2866 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2868 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2869 MachinePointerInfo::getFixedStack(
2870 DAG.getMachineFunction(),
2871 FuncInfo->getRegSaveFrameIndex(), Offset),
2873 MemOps.push_back(Store);
2877 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2878 // Now store the XMM (fp + vector) parameter registers.
2879 SmallVector<SDValue, 12> SaveXMMOps;
2880 SaveXMMOps.push_back(Chain);
2881 SaveXMMOps.push_back(ALVal);
2882 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2883 FuncInfo->getRegSaveFrameIndex(), dl));
2884 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2885 FuncInfo->getVarArgsFPOffset(), dl));
2886 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2888 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2889 MVT::Other, SaveXMMOps));
2892 if (!MemOps.empty())
2893 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2896 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2897 // Find the largest legal vector type.
2898 MVT VecVT = MVT::Other;
2899 // FIXME: Only some x86_32 calling conventions support AVX512.
2900 if (Subtarget->hasAVX512() &&
2901 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2902 CallConv == CallingConv::Intel_OCL_BI)))
2903 VecVT = MVT::v16f32;
2904 else if (Subtarget->hasAVX())
2906 else if (Subtarget->hasSSE2())
2909 // We forward some GPRs and some vector types.
2910 SmallVector<MVT, 2> RegParmTypes;
2911 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2912 RegParmTypes.push_back(IntVT);
2913 if (VecVT != MVT::Other)
2914 RegParmTypes.push_back(VecVT);
2916 // Compute the set of forwarded registers. The rest are scratch.
2917 SmallVectorImpl<ForwardedRegister> &Forwards =
2918 FuncInfo->getForwardedMustTailRegParms();
2919 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2921 // Conservatively forward AL on x86_64, since it might be used for varargs.
2922 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2923 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2924 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2927 // Copy all forwards from physical to virtual registers.
2928 for (ForwardedRegister &F : Forwards) {
2929 // FIXME: Can we use a less constrained schedule?
2930 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2931 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2932 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2936 // Some CCs need callee pop.
2937 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2938 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2939 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2940 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
2941 // X86 interrupts must pop the error code if present
2942 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 8 : 4);
2944 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2945 // If this is an sret function, the return should pop the hidden pointer.
2946 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2947 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2948 argsAreStructReturn(Ins) == StackStructReturn)
2949 FuncInfo->setBytesToPopOnReturn(4);
2953 // RegSaveFrameIndex is X86-64 only.
2954 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2955 if (CallConv == CallingConv::X86_FastCall ||
2956 CallConv == CallingConv::X86_ThisCall)
2957 // fastcc functions can't have varargs.
2958 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2961 FuncInfo->setArgumentStackSize(StackSize);
2963 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2964 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2965 if (Personality == EHPersonality::CoreCLR) {
2967 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2968 // that we'd prefer this slot be allocated towards the bottom of the frame
2969 // (i.e. near the stack pointer after allocating the frame). Every
2970 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2971 // offset from the bottom of this and each funclet's frame must be the
2972 // same, so the size of funclets' (mostly empty) frames is dictated by
2973 // how far this slot is from the bottom (since they allocate just enough
2974 // space to accomodate holding this slot at the correct offset).
2975 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2976 EHInfo->PSPSymFrameIdx = PSPSymFI;
2984 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2985 SDValue StackPtr, SDValue Arg,
2986 SDLoc dl, SelectionDAG &DAG,
2987 const CCValAssign &VA,
2988 ISD::ArgFlagsTy Flags) const {
2989 unsigned LocMemOffset = VA.getLocMemOffset();
2990 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2991 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2993 if (Flags.isByVal())
2994 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2996 return DAG.getStore(
2997 Chain, dl, Arg, PtrOff,
2998 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
3002 /// Emit a load of return address if tail call
3003 /// optimization is performed and it is required.
3005 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
3006 SDValue &OutRetAddr, SDValue Chain,
3007 bool IsTailCall, bool Is64Bit,
3008 int FPDiff, SDLoc dl) const {
3009 // Adjust the Return address stack slot.
3010 EVT VT = getPointerTy(DAG.getDataLayout());
3011 OutRetAddr = getReturnAddressFrameIndex(DAG);
3013 // Load the "old" Return address.
3014 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
3015 false, false, false, 0);
3016 return SDValue(OutRetAddr.getNode(), 1);
3019 /// Emit a store of the return address if tail call
3020 /// optimization is performed and it is required (FPDiff!=0).
3021 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3022 SDValue Chain, SDValue RetAddrFrIdx,
3023 EVT PtrVT, unsigned SlotSize,
3024 int FPDiff, SDLoc dl) {
3025 // Store the return address to the appropriate stack slot.
3026 if (!FPDiff) return Chain;
3027 // Calculate the new stack slot for the return address.
3028 int NewReturnAddrFI =
3029 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3031 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3032 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3033 MachinePointerInfo::getFixedStack(
3034 DAG.getMachineFunction(), NewReturnAddrFI),
3039 /// Returns a vector_shuffle mask for an movs{s|d}, movd
3040 /// operation of specified width.
3041 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
3043 unsigned NumElems = VT.getVectorNumElements();
3044 SmallVector<int, 8> Mask;
3045 Mask.push_back(NumElems);
3046 for (unsigned i = 1; i != NumElems; ++i)
3048 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3052 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3053 SmallVectorImpl<SDValue> &InVals) const {
3054 SelectionDAG &DAG = CLI.DAG;
3056 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3057 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3058 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3059 SDValue Chain = CLI.Chain;
3060 SDValue Callee = CLI.Callee;
3061 CallingConv::ID CallConv = CLI.CallConv;
3062 bool &isTailCall = CLI.IsTailCall;
3063 bool isVarArg = CLI.IsVarArg;
3065 MachineFunction &MF = DAG.getMachineFunction();
3066 bool Is64Bit = Subtarget->is64Bit();
3067 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
3068 StructReturnType SR = callIsStructReturn(Outs);
3069 bool IsSibcall = false;
3070 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3071 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3073 if (CallConv == CallingConv::X86_INTR)
3074 report_fatal_error("X86 interrupts may not be called directly");
3076 if (Attr.getValueAsString() == "true")
3079 if (Subtarget->isPICStyleGOT() &&
3080 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3081 // If we are using a GOT, disable tail calls to external symbols with
3082 // default visibility. Tail calling such a symbol requires using a GOT
3083 // relocation, which forces early binding of the symbol. This breaks code
3084 // that require lazy function symbol resolution. Using musttail or
3085 // GuaranteedTailCallOpt will override this.
3086 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3087 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3088 G->getGlobal()->hasDefaultVisibility()))
3092 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3094 // Force this to be a tail call. The verifier rules are enough to ensure
3095 // that we can lower this successfully without moving the return address
3098 } else if (isTailCall) {
3099 // Check if it's really possible to do a tail call.
3100 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3101 isVarArg, SR != NotStructReturn,
3102 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3103 Outs, OutVals, Ins, DAG);
3105 // Sibcalls are automatically detected tailcalls which do not require
3107 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3114 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3115 "Var args not supported with calling convention fastcc, ghc or hipe");
3117 // Analyze operands of the call, assigning locations to each operand.
3118 SmallVector<CCValAssign, 16> ArgLocs;
3119 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3121 // Allocate shadow area for Win64
3123 CCInfo.AllocateStack(32, 8);
3125 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3127 // Get a count of how many bytes are to be pushed on the stack.
3128 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3130 // This is a sibcall. The memory operands are available in caller's
3131 // own caller's stack.
3133 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3134 canGuaranteeTCO(CallConv))
3135 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3138 if (isTailCall && !IsSibcall && !IsMustTail) {
3139 // Lower arguments at fp - stackoffset + fpdiff.
3140 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3142 FPDiff = NumBytesCallerPushed - NumBytes;
3144 // Set the delta of movement of the returnaddr stackslot.
3145 // But only set if delta is greater than previous delta.
3146 if (FPDiff < X86Info->getTCReturnAddrDelta())
3147 X86Info->setTCReturnAddrDelta(FPDiff);
3150 unsigned NumBytesToPush = NumBytes;
3151 unsigned NumBytesToPop = NumBytes;
3153 // If we have an inalloca argument, all stack space has already been allocated
3154 // for us and be right at the top of the stack. We don't support multiple
3155 // arguments passed in memory when using inalloca.
3156 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3158 if (!ArgLocs.back().isMemLoc())
3159 report_fatal_error("cannot use inalloca attribute on a register "
3161 if (ArgLocs.back().getLocMemOffset() != 0)
3162 report_fatal_error("any parameter with the inalloca attribute must be "
3163 "the only memory argument");
3167 Chain = DAG.getCALLSEQ_START(
3168 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3170 SDValue RetAddrFrIdx;
3171 // Load return address for tail calls.
3172 if (isTailCall && FPDiff)
3173 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3174 Is64Bit, FPDiff, dl);
3176 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3177 SmallVector<SDValue, 8> MemOpChains;
3180 // Walk the register/memloc assignments, inserting copies/loads. In the case
3181 // of tail call optimization arguments are handle later.
3182 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3183 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3184 // Skip inalloca arguments, they have already been written.
3185 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3186 if (Flags.isInAlloca())
3189 CCValAssign &VA = ArgLocs[i];
3190 EVT RegVT = VA.getLocVT();
3191 SDValue Arg = OutVals[i];
3192 bool isByVal = Flags.isByVal();
3194 // Promote the value if needed.
3195 switch (VA.getLocInfo()) {
3196 default: llvm_unreachable("Unknown loc info!");
3197 case CCValAssign::Full: break;
3198 case CCValAssign::SExt:
3199 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3201 case CCValAssign::ZExt:
3202 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3204 case CCValAssign::AExt:
3205 if (Arg.getValueType().isVector() &&
3206 Arg.getValueType().getVectorElementType() == MVT::i1)
3207 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3208 else if (RegVT.is128BitVector()) {
3209 // Special case: passing MMX values in XMM registers.
3210 Arg = DAG.getBitcast(MVT::i64, Arg);
3211 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3212 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3214 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3216 case CCValAssign::BCvt:
3217 Arg = DAG.getBitcast(RegVT, Arg);
3219 case CCValAssign::Indirect: {
3220 // Store the argument.
3221 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3222 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3223 Chain = DAG.getStore(
3224 Chain, dl, Arg, SpillSlot,
3225 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3232 if (VA.isRegLoc()) {
3233 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3234 if (isVarArg && IsWin64) {
3235 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3236 // shadow reg if callee is a varargs function.
3237 unsigned ShadowReg = 0;
3238 switch (VA.getLocReg()) {
3239 case X86::XMM0: ShadowReg = X86::RCX; break;
3240 case X86::XMM1: ShadowReg = X86::RDX; break;
3241 case X86::XMM2: ShadowReg = X86::R8; break;
3242 case X86::XMM3: ShadowReg = X86::R9; break;
3245 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3247 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3248 assert(VA.isMemLoc());
3249 if (!StackPtr.getNode())
3250 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3251 getPointerTy(DAG.getDataLayout()));
3252 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3253 dl, DAG, VA, Flags));
3257 if (!MemOpChains.empty())
3258 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3260 if (Subtarget->isPICStyleGOT()) {
3261 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3264 RegsToPass.push_back(std::make_pair(
3265 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3266 getPointerTy(DAG.getDataLayout()))));
3268 // If we are tail calling and generating PIC/GOT style code load the
3269 // address of the callee into ECX. The value in ecx is used as target of
3270 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3271 // for tail calls on PIC/GOT architectures. Normally we would just put the
3272 // address of GOT into ebx and then call target@PLT. But for tail calls
3273 // ebx would be restored (since ebx is callee saved) before jumping to the
3276 // Note: The actual moving to ECX is done further down.
3277 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3278 if (G && !G->getGlobal()->hasLocalLinkage() &&
3279 G->getGlobal()->hasDefaultVisibility())
3280 Callee = LowerGlobalAddress(Callee, DAG);
3281 else if (isa<ExternalSymbolSDNode>(Callee))
3282 Callee = LowerExternalSymbol(Callee, DAG);
3286 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3287 // From AMD64 ABI document:
3288 // For calls that may call functions that use varargs or stdargs
3289 // (prototype-less calls or calls to functions containing ellipsis (...) in
3290 // the declaration) %al is used as hidden argument to specify the number
3291 // of SSE registers used. The contents of %al do not need to match exactly
3292 // the number of registers, but must be an ubound on the number of SSE
3293 // registers used and is in the range 0 - 8 inclusive.
3295 // Count the number of XMM registers allocated.
3296 static const MCPhysReg XMMArgRegs[] = {
3297 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3298 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3300 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3301 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3302 && "SSE registers cannot be used when SSE is disabled");
3304 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3305 DAG.getConstant(NumXMMRegs, dl,
3309 if (isVarArg && IsMustTail) {
3310 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3311 for (const auto &F : Forwards) {
3312 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3313 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3317 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3318 // don't need this because the eligibility check rejects calls that require
3319 // shuffling arguments passed in memory.
3320 if (!IsSibcall && isTailCall) {
3321 // Force all the incoming stack arguments to be loaded from the stack
3322 // before any new outgoing arguments are stored to the stack, because the
3323 // outgoing stack slots may alias the incoming argument stack slots, and
3324 // the alias isn't otherwise explicit. This is slightly more conservative
3325 // than necessary, because it means that each store effectively depends
3326 // on every argument instead of just those arguments it would clobber.
3327 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3329 SmallVector<SDValue, 8> MemOpChains2;
3332 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3333 CCValAssign &VA = ArgLocs[i];
3336 assert(VA.isMemLoc());
3337 SDValue Arg = OutVals[i];
3338 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3339 // Skip inalloca arguments. They don't require any work.
3340 if (Flags.isInAlloca())
3342 // Create frame index.
3343 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3344 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3345 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3346 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3348 if (Flags.isByVal()) {
3349 // Copy relative to framepointer.
3350 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3351 if (!StackPtr.getNode())
3352 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3353 getPointerTy(DAG.getDataLayout()));
3354 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3357 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3361 // Store relative to framepointer.
3362 MemOpChains2.push_back(DAG.getStore(
3363 ArgChain, dl, Arg, FIN,
3364 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3369 if (!MemOpChains2.empty())
3370 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3372 // Store the return address to the appropriate stack slot.
3373 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3374 getPointerTy(DAG.getDataLayout()),
3375 RegInfo->getSlotSize(), FPDiff, dl);
3378 // Build a sequence of copy-to-reg nodes chained together with token chain
3379 // and flag operands which copy the outgoing args into registers.
3381 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3382 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3383 RegsToPass[i].second, InFlag);
3384 InFlag = Chain.getValue(1);
3387 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3388 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3389 // In the 64-bit large code model, we have to make all calls
3390 // through a register, since the call instruction's 32-bit
3391 // pc-relative offset may not be large enough to hold the whole
3393 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3394 // If the callee is a GlobalAddress node (quite common, every direct call
3395 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3397 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3399 // We should use extra load for direct calls to dllimported functions in
3401 const GlobalValue *GV = G->getGlobal();
3402 if (!GV->hasDLLImportStorageClass()) {
3403 unsigned char OpFlags = 0;
3404 bool ExtraLoad = false;
3405 unsigned WrapperKind = ISD::DELETED_NODE;
3407 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3408 // external symbols most go through the PLT in PIC mode. If the symbol
3409 // has hidden or protected visibility, or if it is static or local, then
3410 // we don't need to use the PLT - we can directly call it.
3411 if (Subtarget->isTargetELF() &&
3412 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3413 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3414 OpFlags = X86II::MO_PLT;
3415 } else if (Subtarget->isPICStyleStubAny() &&
3416 !GV->isStrongDefinitionForLinker() &&
3417 (!Subtarget->getTargetTriple().isMacOSX() ||
3418 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3419 // PC-relative references to external symbols should go through $stub,
3420 // unless we're building with the leopard linker or later, which
3421 // automatically synthesizes these stubs.
3422 OpFlags = X86II::MO_DARWIN_STUB;
3423 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3424 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3425 // If the function is marked as non-lazy, generate an indirect call
3426 // which loads from the GOT directly. This avoids runtime overhead
3427 // at the cost of eager binding (and one extra byte of encoding).
3428 OpFlags = X86II::MO_GOTPCREL;
3429 WrapperKind = X86ISD::WrapperRIP;
3433 Callee = DAG.getTargetGlobalAddress(
3434 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3436 // Add a wrapper if needed.
3437 if (WrapperKind != ISD::DELETED_NODE)
3438 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3439 getPointerTy(DAG.getDataLayout()), Callee);
3440 // Add extra indirection if needed.
3442 Callee = DAG.getLoad(
3443 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3444 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3447 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3448 unsigned char OpFlags = 0;
3450 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3451 // external symbols should go through the PLT.
3452 if (Subtarget->isTargetELF() &&
3453 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3454 OpFlags = X86II::MO_PLT;
3455 } else if (Subtarget->isPICStyleStubAny() &&
3456 (!Subtarget->getTargetTriple().isMacOSX() ||
3457 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3458 // PC-relative references to external symbols should go through $stub,
3459 // unless we're building with the leopard linker or later, which
3460 // automatically synthesizes these stubs.
3461 OpFlags = X86II::MO_DARWIN_STUB;
3464 Callee = DAG.getTargetExternalSymbol(
3465 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3466 } else if (Subtarget->isTarget64BitILP32() &&
3467 Callee->getValueType(0) == MVT::i32) {
3468 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3469 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3472 // Returns a chain & a flag for retval copy to use.
3473 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3474 SmallVector<SDValue, 8> Ops;
3476 if (!IsSibcall && isTailCall) {
3477 Chain = DAG.getCALLSEQ_END(Chain,
3478 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3479 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3480 InFlag = Chain.getValue(1);
3483 Ops.push_back(Chain);
3484 Ops.push_back(Callee);
3487 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3489 // Add argument registers to the end of the list so that they are known live
3491 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3492 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3493 RegsToPass[i].second.getValueType()));
3495 // Add a register mask operand representing the call-preserved registers.
3496 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3497 assert(Mask && "Missing call preserved mask for calling convention");
3499 // If this is an invoke in a 32-bit function using a funclet-based
3500 // personality, assume the function clobbers all registers. If an exception
3501 // is thrown, the runtime will not restore CSRs.
3502 // FIXME: Model this more precisely so that we can register allocate across
3503 // the normal edge and spill and fill across the exceptional edge.
3504 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3505 const Function *CallerFn = MF.getFunction();
3506 EHPersonality Pers =
3507 CallerFn->hasPersonalityFn()
3508 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3509 : EHPersonality::Unknown;
3510 if (isFuncletEHPersonality(Pers))
3511 Mask = RegInfo->getNoPreservedMask();
3514 Ops.push_back(DAG.getRegisterMask(Mask));
3516 if (InFlag.getNode())
3517 Ops.push_back(InFlag);
3521 //// If this is the first return lowered for this function, add the regs
3522 //// to the liveout set for the function.
3523 // This isn't right, although it's probably harmless on x86; liveouts
3524 // should be computed from returns not tail calls. Consider a void
3525 // function making a tail call to a function returning int.
3526 MF.getFrameInfo()->setHasTailCall();
3527 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3530 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3531 InFlag = Chain.getValue(1);
3533 // Create the CALLSEQ_END node.
3534 unsigned NumBytesForCalleeToPop;
3535 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3536 DAG.getTarget().Options.GuaranteedTailCallOpt))
3537 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3538 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3539 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3540 SR == StackStructReturn)
3541 // If this is a call to a struct-return function, the callee
3542 // pops the hidden struct pointer, so we have to push it back.
3543 // This is common for Darwin/X86, Linux & Mingw32 targets.
3544 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3545 NumBytesForCalleeToPop = 4;
3547 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3549 // Returns a flag for retval copy to use.
3551 Chain = DAG.getCALLSEQ_END(Chain,
3552 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3553 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3556 InFlag = Chain.getValue(1);
3559 // Handle result values, copying them out of physregs into vregs that we
3561 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3562 Ins, dl, DAG, InVals);
3565 //===----------------------------------------------------------------------===//
3566 // Fast Calling Convention (tail call) implementation
3567 //===----------------------------------------------------------------------===//
3569 // Like std call, callee cleans arguments, convention except that ECX is
3570 // reserved for storing the tail called function address. Only 2 registers are
3571 // free for argument passing (inreg). Tail call optimization is performed
3573 // * tailcallopt is enabled
3574 // * caller/callee are fastcc
3575 // On X86_64 architecture with GOT-style position independent code only local
3576 // (within module) calls are supported at the moment.
3577 // To keep the stack aligned according to platform abi the function
3578 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3579 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3580 // If a tail called function callee has more arguments than the caller the
3581 // caller needs to make sure that there is room to move the RETADDR to. This is
3582 // achieved by reserving an area the size of the argument delta right after the
3583 // original RETADDR, but before the saved framepointer or the spilled registers
3584 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3596 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3599 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3600 SelectionDAG& DAG) const {
3601 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3602 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3603 unsigned StackAlignment = TFI.getStackAlignment();
3604 uint64_t AlignMask = StackAlignment - 1;
3605 int64_t Offset = StackSize;
3606 unsigned SlotSize = RegInfo->getSlotSize();
3607 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3608 // Number smaller than 12 so just add the difference.
3609 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3611 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3612 Offset = ((~AlignMask) & Offset) + StackAlignment +
3613 (StackAlignment-SlotSize);
3618 /// Return true if the given stack call argument is already available in the
3619 /// same position (relatively) of the caller's incoming argument stack.
3621 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3622 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3623 const X86InstrInfo *TII) {
3624 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3626 if (Arg.getOpcode() == ISD::CopyFromReg) {
3627 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3628 if (!TargetRegisterInfo::isVirtualRegister(VR))
3630 MachineInstr *Def = MRI->getVRegDef(VR);
3633 if (!Flags.isByVal()) {
3634 if (!TII->isLoadFromStackSlot(Def, FI))
3637 unsigned Opcode = Def->getOpcode();
3638 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3639 Opcode == X86::LEA64_32r) &&
3640 Def->getOperand(1).isFI()) {
3641 FI = Def->getOperand(1).getIndex();
3642 Bytes = Flags.getByValSize();
3646 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3647 if (Flags.isByVal())
3648 // ByVal argument is passed in as a pointer but it's now being
3649 // dereferenced. e.g.
3650 // define @foo(%struct.X* %A) {
3651 // tail call @bar(%struct.X* byval %A)
3654 SDValue Ptr = Ld->getBasePtr();
3655 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3658 FI = FINode->getIndex();
3659 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3660 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3661 FI = FINode->getIndex();
3662 Bytes = Flags.getByValSize();
3666 assert(FI != INT_MAX);
3667 if (!MFI->isFixedObjectIndex(FI))
3669 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3672 /// Check whether the call is eligible for tail call optimization. Targets
3673 /// that want to do tail call optimization should implement this function.
3674 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3675 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3676 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3677 const SmallVectorImpl<ISD::OutputArg> &Outs,
3678 const SmallVectorImpl<SDValue> &OutVals,
3679 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3680 if (!mayTailCallThisCC(CalleeCC))
3683 // If -tailcallopt is specified, make fastcc functions tail-callable.
3684 MachineFunction &MF = DAG.getMachineFunction();
3685 const Function *CallerF = MF.getFunction();
3687 // If the function return type is x86_fp80 and the callee return type is not,
3688 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3689 // perform a tailcall optimization here.
3690 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3693 CallingConv::ID CallerCC = CallerF->getCallingConv();
3694 bool CCMatch = CallerCC == CalleeCC;
3695 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3696 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3698 // Win64 functions have extra shadow space for argument homing. Don't do the
3699 // sibcall if the caller and callee have mismatched expectations for this
3701 if (IsCalleeWin64 != IsCallerWin64)
3704 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3705 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3710 // Look for obvious safe cases to perform tail call optimization that do not
3711 // require ABI changes. This is what gcc calls sibcall.
3713 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3714 // emit a special epilogue.
3715 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3716 if (RegInfo->needsStackRealignment(MF))
3719 // Also avoid sibcall optimization if either caller or callee uses struct
3720 // return semantics.
3721 if (isCalleeStructRet || isCallerStructRet)
3724 // Do not sibcall optimize vararg calls unless all arguments are passed via
3726 if (isVarArg && !Outs.empty()) {
3727 // Optimizing for varargs on Win64 is unlikely to be safe without
3728 // additional testing.
3729 if (IsCalleeWin64 || IsCallerWin64)
3732 SmallVector<CCValAssign, 16> ArgLocs;
3733 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3736 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3737 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3738 if (!ArgLocs[i].isRegLoc())
3742 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3743 // stack. Therefore, if it's not used by the call it is not safe to optimize
3744 // this into a sibcall.
3745 bool Unused = false;
3746 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3753 SmallVector<CCValAssign, 16> RVLocs;
3754 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3756 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3757 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3758 CCValAssign &VA = RVLocs[i];
3759 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3764 // If the calling conventions do not match, then we'd better make sure the
3765 // results are returned in the same way as what the caller expects.
3767 SmallVector<CCValAssign, 16> RVLocs1;
3768 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3770 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3772 SmallVector<CCValAssign, 16> RVLocs2;
3773 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3775 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3777 if (RVLocs1.size() != RVLocs2.size())
3779 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3780 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3782 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3784 if (RVLocs1[i].isRegLoc()) {
3785 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3788 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3794 unsigned StackArgsSize = 0;
3796 // If the callee takes no arguments then go on to check the results of the
3798 if (!Outs.empty()) {
3799 // Check if stack adjustment is needed. For now, do not do this if any
3800 // argument is passed on the stack.
3801 SmallVector<CCValAssign, 16> ArgLocs;
3802 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3805 // Allocate shadow area for Win64
3807 CCInfo.AllocateStack(32, 8);
3809 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3810 StackArgsSize = CCInfo.getNextStackOffset();
3812 if (CCInfo.getNextStackOffset()) {
3813 // Check if the arguments are already laid out in the right way as
3814 // the caller's fixed stack objects.
3815 MachineFrameInfo *MFI = MF.getFrameInfo();
3816 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3817 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3818 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3819 CCValAssign &VA = ArgLocs[i];
3820 SDValue Arg = OutVals[i];
3821 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3822 if (VA.getLocInfo() == CCValAssign::Indirect)
3824 if (!VA.isRegLoc()) {
3825 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3832 // If the tailcall address may be in a register, then make sure it's
3833 // possible to register allocate for it. In 32-bit, the call address can
3834 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3835 // callee-saved registers are restored. These happen to be the same
3836 // registers used to pass 'inreg' arguments so watch out for those.
3837 if (!Subtarget->is64Bit() &&
3838 ((!isa<GlobalAddressSDNode>(Callee) &&
3839 !isa<ExternalSymbolSDNode>(Callee)) ||
3840 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3841 unsigned NumInRegs = 0;
3842 // In PIC we need an extra register to formulate the address computation
3844 unsigned MaxInRegs =
3845 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3848 CCValAssign &VA = ArgLocs[i];
3851 unsigned Reg = VA.getLocReg();
3854 case X86::EAX: case X86::EDX: case X86::ECX:
3855 if (++NumInRegs == MaxInRegs)
3863 bool CalleeWillPop =
3864 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3865 MF.getTarget().Options.GuaranteedTailCallOpt);
3867 if (unsigned BytesToPop =
3868 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3869 // If we have bytes to pop, the callee must pop them.
3870 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3871 if (!CalleePopMatches)
3873 } else if (CalleeWillPop && StackArgsSize > 0) {
3874 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3882 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3883 const TargetLibraryInfo *libInfo) const {
3884 return X86::createFastISel(funcInfo, libInfo);
3887 //===----------------------------------------------------------------------===//
3888 // Other Lowering Hooks
3889 //===----------------------------------------------------------------------===//
3891 static bool MayFoldLoad(SDValue Op) {
3892 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3895 static bool MayFoldIntoStore(SDValue Op) {
3896 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3899 static bool isTargetShuffle(unsigned Opcode) {
3901 default: return false;
3902 case X86ISD::BLENDI:
3903 case X86ISD::PSHUFB:
3904 case X86ISD::PSHUFD:
3905 case X86ISD::PSHUFHW:
3906 case X86ISD::PSHUFLW:
3908 case X86ISD::PALIGNR:
3909 case X86ISD::MOVLHPS:
3910 case X86ISD::MOVLHPD:
3911 case X86ISD::MOVHLPS:
3912 case X86ISD::MOVLPS:
3913 case X86ISD::MOVLPD:
3914 case X86ISD::MOVSHDUP:
3915 case X86ISD::MOVSLDUP:
3916 case X86ISD::MOVDDUP:
3919 case X86ISD::UNPCKL:
3920 case X86ISD::UNPCKH:
3921 case X86ISD::VPERMILPI:
3922 case X86ISD::VPERM2X128:
3923 case X86ISD::VPERMI:
3924 case X86ISD::VPERMV:
3925 case X86ISD::VPERMV3:
3930 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3931 SDValue V1, unsigned TargetMask,
3932 SelectionDAG &DAG) {
3934 default: llvm_unreachable("Unknown x86 shuffle node");
3935 case X86ISD::PSHUFD:
3936 case X86ISD::PSHUFHW:
3937 case X86ISD::PSHUFLW:
3938 case X86ISD::VPERMILPI:
3939 case X86ISD::VPERMI:
3940 return DAG.getNode(Opc, dl, VT, V1,
3941 DAG.getConstant(TargetMask, dl, MVT::i8));
3945 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3946 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3948 default: llvm_unreachable("Unknown x86 shuffle node");
3949 case X86ISD::MOVLHPS:
3950 case X86ISD::MOVLHPD:
3951 case X86ISD::MOVHLPS:
3952 case X86ISD::MOVLPS:
3953 case X86ISD::MOVLPD:
3956 case X86ISD::UNPCKL:
3957 case X86ISD::UNPCKH:
3958 return DAG.getNode(Opc, dl, VT, V1, V2);
3962 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3963 MachineFunction &MF = DAG.getMachineFunction();
3964 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3965 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3966 int ReturnAddrIndex = FuncInfo->getRAIndex();
3968 if (ReturnAddrIndex == 0) {
3969 // Set up a frame object for the return address.
3970 unsigned SlotSize = RegInfo->getSlotSize();
3971 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3974 FuncInfo->setRAIndex(ReturnAddrIndex);
3977 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3980 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3981 bool hasSymbolicDisplacement) {
3982 // Offset should fit into 32 bit immediate field.
3983 if (!isInt<32>(Offset))
3986 // If we don't have a symbolic displacement - we don't have any extra
3988 if (!hasSymbolicDisplacement)
3991 // FIXME: Some tweaks might be needed for medium code model.
3992 if (M != CodeModel::Small && M != CodeModel::Kernel)
3995 // For small code model we assume that latest object is 16MB before end of 31
3996 // bits boundary. We may also accept pretty large negative constants knowing
3997 // that all objects are in the positive half of address space.
3998 if (M == CodeModel::Small && Offset < 16*1024*1024)
4001 // For kernel code model we know that all object resist in the negative half
4002 // of 32bits address space. We may not accept negative offsets, since they may
4003 // be just off and we may accept pretty large positive ones.
4004 if (M == CodeModel::Kernel && Offset >= 0)
4010 /// Determines whether the callee is required to pop its own arguments.
4011 /// Callee pop is necessary to support tail calls.
4012 bool X86::isCalleePop(CallingConv::ID CallingConv,
4013 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4014 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4015 // can guarantee TCO.
4016 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4019 switch (CallingConv) {
4022 case CallingConv::X86_StdCall:
4023 case CallingConv::X86_FastCall:
4024 case CallingConv::X86_ThisCall:
4025 case CallingConv::X86_VectorCall:
4030 /// \brief Return true if the condition is an unsigned comparison operation.
4031 static bool isX86CCUnsigned(unsigned X86CC) {
4033 default: llvm_unreachable("Invalid integer condition!");
4034 case X86::COND_E: return true;
4035 case X86::COND_G: return false;
4036 case X86::COND_GE: return false;
4037 case X86::COND_L: return false;
4038 case X86::COND_LE: return false;
4039 case X86::COND_NE: return true;
4040 case X86::COND_B: return true;
4041 case X86::COND_A: return true;
4042 case X86::COND_BE: return true;
4043 case X86::COND_AE: return true;
4047 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4048 switch (SetCCOpcode) {
4049 default: llvm_unreachable("Invalid integer condition!");
4050 case ISD::SETEQ: return X86::COND_E;
4051 case ISD::SETGT: return X86::COND_G;
4052 case ISD::SETGE: return X86::COND_GE;
4053 case ISD::SETLT: return X86::COND_L;
4054 case ISD::SETLE: return X86::COND_LE;
4055 case ISD::SETNE: return X86::COND_NE;
4056 case ISD::SETULT: return X86::COND_B;
4057 case ISD::SETUGT: return X86::COND_A;
4058 case ISD::SETULE: return X86::COND_BE;
4059 case ISD::SETUGE: return X86::COND_AE;
4063 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4064 /// condition code, returning the condition code and the LHS/RHS of the
4065 /// comparison to make.
4066 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
4067 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
4069 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4070 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4071 // X > -1 -> X == 0, jump !sign.
4072 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4073 return X86::COND_NS;
4075 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4076 // X < 0 -> X == 0, jump on sign.
4079 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4081 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4082 return X86::COND_LE;
4086 return TranslateIntegerX86CC(SetCCOpcode);
4089 // First determine if it is required or is profitable to flip the operands.
4091 // If LHS is a foldable load, but RHS is not, flip the condition.
4092 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4093 !ISD::isNON_EXTLoad(RHS.getNode())) {
4094 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4095 std::swap(LHS, RHS);
4098 switch (SetCCOpcode) {
4104 std::swap(LHS, RHS);
4108 // On a floating point condition, the flags are set as follows:
4110 // 0 | 0 | 0 | X > Y
4111 // 0 | 0 | 1 | X < Y
4112 // 1 | 0 | 0 | X == Y
4113 // 1 | 1 | 1 | unordered
4114 switch (SetCCOpcode) {
4115 default: llvm_unreachable("Condcode should be pre-legalized away");
4117 case ISD::SETEQ: return X86::COND_E;
4118 case ISD::SETOLT: // flipped
4120 case ISD::SETGT: return X86::COND_A;
4121 case ISD::SETOLE: // flipped
4123 case ISD::SETGE: return X86::COND_AE;
4124 case ISD::SETUGT: // flipped
4126 case ISD::SETLT: return X86::COND_B;
4127 case ISD::SETUGE: // flipped
4129 case ISD::SETLE: return X86::COND_BE;
4131 case ISD::SETNE: return X86::COND_NE;
4132 case ISD::SETUO: return X86::COND_P;
4133 case ISD::SETO: return X86::COND_NP;
4135 case ISD::SETUNE: return X86::COND_INVALID;
4139 /// Is there a floating point cmov for the specific X86 condition code?
4140 /// Current x86 isa includes the following FP cmov instructions:
4141 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4142 static bool hasFPCMov(unsigned X86CC) {
4158 /// Returns true if the target can instruction select the
4159 /// specified FP immediate natively. If false, the legalizer will
4160 /// materialize the FP immediate as a load from a constant pool.
4161 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4162 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4163 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4169 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4170 ISD::LoadExtType ExtTy,
4172 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4173 // relocation target a movq or addq instruction: don't let the load shrink.
4174 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4175 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4176 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4177 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4181 /// \brief Returns true if it is beneficial to convert a load of a constant
4182 /// to just the constant itself.
4183 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4185 assert(Ty->isIntegerTy());
4187 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4188 if (BitSize == 0 || BitSize > 64)
4193 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4194 unsigned Index) const {
4195 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4198 return (Index == 0 || Index == ResVT.getVectorNumElements());
4201 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4202 // Speculate cttz only if we can directly use TZCNT.
4203 return Subtarget->hasBMI();
4206 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4207 // Speculate ctlz only if we can directly use LZCNT.
4208 return Subtarget->hasLZCNT();
4211 /// Return true if every element in Mask, beginning
4212 /// from position Pos and ending in Pos+Size is undef.
4213 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4214 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4220 /// Return true if Val is undef or if its value falls within the
4221 /// specified range (L, H].
4222 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4223 return (Val < 0) || (Val >= Low && Val < Hi);
4226 /// Val is either less than zero (undef) or equal to the specified value.
4227 static bool isUndefOrEqual(int Val, int CmpVal) {
4228 return (Val < 0 || Val == CmpVal);
4231 /// Return true if every element in Mask, beginning
4232 /// from position Pos and ending in Pos+Size, falls within the specified
4233 /// sequential range (Low, Low+Size]. or is undef.
4234 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4235 unsigned Pos, unsigned Size, int Low) {
4236 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4237 if (!isUndefOrEqual(Mask[i], Low))
4242 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4243 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4244 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4245 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4246 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4249 // The index should be aligned on a vecWidth-bit boundary.
4251 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4253 MVT VT = N->getSimpleValueType(0);
4254 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4255 bool Result = (Index * ElSize) % vecWidth == 0;
4260 /// Return true if the specified INSERT_SUBVECTOR
4261 /// operand specifies a subvector insert that is suitable for input to
4262 /// insertion of 128 or 256-bit subvectors
4263 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4264 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4265 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4267 // The index should be aligned on a vecWidth-bit boundary.
4269 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4271 MVT VT = N->getSimpleValueType(0);
4272 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4273 bool Result = (Index * ElSize) % vecWidth == 0;
4278 bool X86::isVINSERT128Index(SDNode *N) {
4279 return isVINSERTIndex(N, 128);
4282 bool X86::isVINSERT256Index(SDNode *N) {
4283 return isVINSERTIndex(N, 256);
4286 bool X86::isVEXTRACT128Index(SDNode *N) {
4287 return isVEXTRACTIndex(N, 128);
4290 bool X86::isVEXTRACT256Index(SDNode *N) {
4291 return isVEXTRACTIndex(N, 256);
4294 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4295 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4296 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4297 "Illegal extract subvector for VEXTRACT");
4300 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4302 MVT VecVT = N->getOperand(0).getSimpleValueType();
4303 MVT ElVT = VecVT.getVectorElementType();
4305 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4306 return Index / NumElemsPerChunk;
4309 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4310 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4311 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4312 "Illegal insert subvector for VINSERT");
4315 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4317 MVT VecVT = N->getSimpleValueType(0);
4318 MVT ElVT = VecVT.getVectorElementType();
4320 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4321 return Index / NumElemsPerChunk;
4324 /// Return the appropriate immediate to extract the specified
4325 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4326 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4327 return getExtractVEXTRACTImmediate(N, 128);
4330 /// Return the appropriate immediate to extract the specified
4331 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4332 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4333 return getExtractVEXTRACTImmediate(N, 256);
4336 /// Return the appropriate immediate to insert at the specified
4337 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4338 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4339 return getInsertVINSERTImmediate(N, 128);
4342 /// Return the appropriate immediate to insert at the specified
4343 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4344 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4345 return getInsertVINSERTImmediate(N, 256);
4348 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4349 bool X86::isZeroNode(SDValue Elt) {
4350 return isNullConstant(Elt) || isNullFPConstant(Elt);
4353 // Build a vector of constants
4354 // Use an UNDEF node if MaskElt == -1.
4355 // Spilt 64-bit constants in the 32-bit mode.
4356 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4358 SDLoc dl, bool IsMask = false) {
4360 SmallVector<SDValue, 32> Ops;
4363 MVT ConstVecVT = VT;
4364 unsigned NumElts = VT.getVectorNumElements();
4365 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4366 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4367 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4371 MVT EltVT = ConstVecVT.getVectorElementType();
4372 for (unsigned i = 0; i < NumElts; ++i) {
4373 bool IsUndef = Values[i] < 0 && IsMask;
4374 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4375 DAG.getConstant(Values[i], dl, EltVT);
4376 Ops.push_back(OpNode);
4378 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4379 DAG.getConstant(0, dl, EltVT));
4381 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4383 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4387 /// Returns a vector of specified type with all zero elements.
4388 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4389 SelectionDAG &DAG, SDLoc dl) {
4390 assert(VT.isVector() && "Expected a vector type");
4392 // Always build SSE zero vectors as <4 x i32> bitcasted
4393 // to their dest type. This ensures they get CSE'd.
4395 if (VT.is128BitVector()) { // SSE
4396 if (Subtarget->hasSSE2()) { // SSE2
4397 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4398 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4400 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4401 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4403 } else if (VT.is256BitVector()) { // AVX
4404 if (Subtarget->hasInt256()) { // AVX2
4405 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4406 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4407 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4409 // 256-bit logic and arithmetic instructions in AVX are all
4410 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4411 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4412 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4413 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4415 } else if (VT.is512BitVector()) { // AVX-512
4416 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4417 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4418 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4419 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4420 } else if (VT.getVectorElementType() == MVT::i1) {
4422 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4423 && "Unexpected vector type");
4424 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4425 && "Unexpected vector type");
4426 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4427 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4428 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4430 llvm_unreachable("Unexpected vector type");
4432 return DAG.getBitcast(VT, Vec);
4435 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4436 SelectionDAG &DAG, SDLoc dl,
4437 unsigned vectorWidth) {
4438 assert((vectorWidth == 128 || vectorWidth == 256) &&
4439 "Unsupported vector width");
4440 EVT VT = Vec.getValueType();
4441 EVT ElVT = VT.getVectorElementType();
4442 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4443 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4444 VT.getVectorNumElements()/Factor);
4446 // Extract from UNDEF is UNDEF.
4447 if (Vec.getOpcode() == ISD::UNDEF)
4448 return DAG.getUNDEF(ResultVT);
4450 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4451 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4452 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4454 // This is the index of the first element of the vectorWidth-bit chunk
4455 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4456 IdxVal &= ~(ElemsPerChunk - 1);
4458 // If the input is a buildvector just emit a smaller one.
4459 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4460 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4461 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4463 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4464 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4467 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4468 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4469 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4470 /// instructions or a simple subregister reference. Idx is an index in the
4471 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4472 /// lowering EXTRACT_VECTOR_ELT operations easier.
4473 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4474 SelectionDAG &DAG, SDLoc dl) {
4475 assert((Vec.getValueType().is256BitVector() ||
4476 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4477 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4480 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4481 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4482 SelectionDAG &DAG, SDLoc dl) {
4483 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4484 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4487 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4488 unsigned IdxVal, SelectionDAG &DAG,
4489 SDLoc dl, unsigned vectorWidth) {
4490 assert((vectorWidth == 128 || vectorWidth == 256) &&
4491 "Unsupported vector width");
4492 // Inserting UNDEF is Result
4493 if (Vec.getOpcode() == ISD::UNDEF)
4495 EVT VT = Vec.getValueType();
4496 EVT ElVT = VT.getVectorElementType();
4497 EVT ResultVT = Result.getValueType();
4499 // Insert the relevant vectorWidth bits.
4500 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4501 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4503 // This is the index of the first element of the vectorWidth-bit chunk
4504 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4505 IdxVal &= ~(ElemsPerChunk - 1);
4507 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4508 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4511 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4512 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4513 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4514 /// simple superregister reference. Idx is an index in the 128 bits
4515 /// we want. It need not be aligned to a 128-bit boundary. That makes
4516 /// lowering INSERT_VECTOR_ELT operations easier.
4517 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4518 SelectionDAG &DAG, SDLoc dl) {
4519 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4521 // For insertion into the zero index (low half) of a 256-bit vector, it is
4522 // more efficient to generate a blend with immediate instead of an insert*128.
4523 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4524 // extend the subvector to the size of the result vector. Make sure that
4525 // we are not recursing on that node by checking for undef here.
4526 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4527 Result.getOpcode() != ISD::UNDEF) {
4528 EVT ResultVT = Result.getValueType();
4529 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4530 SDValue Undef = DAG.getUNDEF(ResultVT);
4531 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4534 // The blend instruction, and therefore its mask, depend on the data type.
4535 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4536 if (ScalarType.isFloatingPoint()) {
4537 // Choose either vblendps (float) or vblendpd (double).
4538 unsigned ScalarSize = ScalarType.getSizeInBits();
4539 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4540 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4541 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4542 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4545 const X86Subtarget &Subtarget =
4546 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4548 // AVX2 is needed for 256-bit integer blend support.
4549 // Integers must be cast to 32-bit because there is only vpblendd;
4550 // vpblendw can't be used for this because it has a handicapped mask.
4552 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4553 // is still more efficient than using the wrong domain vinsertf128 that
4554 // will be created by InsertSubVector().
4555 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4557 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4558 Vec256 = DAG.getBitcast(CastVT, Vec256);
4559 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4560 return DAG.getBitcast(ResultVT, Vec256);
4563 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4566 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4567 SelectionDAG &DAG, SDLoc dl) {
4568 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4569 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4572 /// Insert i1-subvector to i1-vector.
4573 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4576 SDValue Vec = Op.getOperand(0);
4577 SDValue SubVec = Op.getOperand(1);
4578 SDValue Idx = Op.getOperand(2);
4580 if (!isa<ConstantSDNode>(Idx))
4583 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4584 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4587 MVT OpVT = Op.getSimpleValueType();
4588 MVT SubVecVT = SubVec.getSimpleValueType();
4589 unsigned NumElems = OpVT.getVectorNumElements();
4590 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4592 assert(IdxVal + SubVecNumElems <= NumElems &&
4593 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4594 "Unexpected index value in INSERT_SUBVECTOR");
4596 // There are 3 possible cases:
4597 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4598 // 2. Subvector should be inserted in the upper part
4599 // (IdxVal + SubVecNumElems == NumElems)
4600 // 3. Subvector should be inserted in the middle (for example v2i1
4601 // to v16i1, index 2)
4603 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4604 SDValue Undef = DAG.getUNDEF(OpVT);
4605 SDValue WideSubVec =
4606 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4608 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4609 DAG.getConstant(IdxVal, dl, MVT::i8));
4611 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4612 unsigned ShiftLeft = NumElems - SubVecNumElems;
4613 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4614 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4615 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4616 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4617 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4621 // Zero lower bits of the Vec
4622 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4623 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4624 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4625 // Merge them together
4626 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4629 // Simple case when we put subvector in the upper part
4630 if (IdxVal + SubVecNumElems == NumElems) {
4631 // Zero upper bits of the Vec
4632 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4633 DAG.getConstant(IdxVal, dl, MVT::i8));
4634 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4635 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4636 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4637 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4639 // Subvector should be inserted in the middle - use shuffle
4640 SmallVector<int, 64> Mask;
4641 for (unsigned i = 0; i < NumElems; ++i)
4642 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4644 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4647 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4648 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4649 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4650 /// large BUILD_VECTORS.
4651 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4652 unsigned NumElems, SelectionDAG &DAG,
4654 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4655 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4658 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4659 unsigned NumElems, SelectionDAG &DAG,
4661 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4662 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4665 /// Returns a vector of specified type with all bits set.
4666 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4667 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4668 /// Then bitcast to their original type, ensuring they get CSE'd.
4669 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4670 SelectionDAG &DAG, SDLoc dl) {
4671 assert(VT.isVector() && "Expected a vector type");
4673 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4675 if (VT.is512BitVector()) {
4676 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4677 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4678 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4679 } else if (VT.is256BitVector()) {
4680 if (Subtarget->hasInt256()) { // AVX2
4681 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4682 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4684 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4685 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4687 } else if (VT.is128BitVector()) {
4688 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4690 llvm_unreachable("Unexpected vector type");
4692 return DAG.getBitcast(VT, Vec);
4695 /// Returns a vector_shuffle node for an unpackl operation.
4696 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4698 unsigned NumElems = VT.getVectorNumElements();
4699 SmallVector<int, 8> Mask;
4700 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4702 Mask.push_back(i + NumElems);
4704 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4707 /// Returns a vector_shuffle node for an unpackh operation.
4708 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4710 unsigned NumElems = VT.getVectorNumElements();
4711 SmallVector<int, 8> Mask;
4712 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4713 Mask.push_back(i + Half);
4714 Mask.push_back(i + NumElems + Half);
4716 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4719 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4720 /// This produces a shuffle where the low element of V2 is swizzled into the
4721 /// zero/undef vector, landing at element Idx.
4722 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4723 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4725 const X86Subtarget *Subtarget,
4726 SelectionDAG &DAG) {
4727 MVT VT = V2.getSimpleValueType();
4729 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4730 unsigned NumElems = VT.getVectorNumElements();
4731 SmallVector<int, 16> MaskVec;
4732 for (unsigned i = 0; i != NumElems; ++i)
4733 // If this is the insertion idx, put the low elt of V2 here.
4734 MaskVec.push_back(i == Idx ? NumElems : i);
4735 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4738 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4739 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4740 /// uses one source. Note that this will set IsUnary for shuffles which use a
4741 /// single input multiple times, and in those cases it will
4742 /// adjust the mask to only have indices within that single input.
4743 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4744 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4745 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4746 unsigned NumElems = VT.getVectorNumElements();
4750 bool IsFakeUnary = false;
4751 switch(N->getOpcode()) {
4752 case X86ISD::BLENDI:
4753 ImmN = N->getOperand(N->getNumOperands()-1);
4754 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4757 ImmN = N->getOperand(N->getNumOperands()-1);
4758 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4759 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4761 case X86ISD::UNPCKH:
4762 DecodeUNPCKHMask(VT, Mask);
4763 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4765 case X86ISD::UNPCKL:
4766 DecodeUNPCKLMask(VT, Mask);
4767 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4769 case X86ISD::MOVHLPS:
4770 DecodeMOVHLPSMask(NumElems, Mask);
4771 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4773 case X86ISD::MOVLHPS:
4774 DecodeMOVLHPSMask(NumElems, Mask);
4775 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4777 case X86ISD::PALIGNR:
4778 ImmN = N->getOperand(N->getNumOperands()-1);
4779 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4781 case X86ISD::PSHUFD:
4782 case X86ISD::VPERMILPI:
4783 ImmN = N->getOperand(N->getNumOperands()-1);
4784 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4787 case X86ISD::PSHUFHW:
4788 ImmN = N->getOperand(N->getNumOperands()-1);
4789 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4792 case X86ISD::PSHUFLW:
4793 ImmN = N->getOperand(N->getNumOperands()-1);
4794 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4797 case X86ISD::PSHUFB: {
4799 SDValue MaskNode = N->getOperand(1);
4800 while (MaskNode->getOpcode() == ISD::BITCAST)
4801 MaskNode = MaskNode->getOperand(0);
4803 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4804 // If we have a build-vector, then things are easy.
4805 MVT VT = MaskNode.getSimpleValueType();
4806 assert(VT.isVector() &&
4807 "Can't produce a non-vector with a build_vector!");
4808 if (!VT.isInteger())
4811 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4813 SmallVector<uint64_t, 32> RawMask;
4814 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4815 SDValue Op = MaskNode->getOperand(i);
4816 if (Op->getOpcode() == ISD::UNDEF) {
4817 RawMask.push_back((uint64_t)SM_SentinelUndef);
4820 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4823 APInt MaskElement = CN->getAPIntValue();
4825 // We now have to decode the element which could be any integer size and
4826 // extract each byte of it.
4827 for (int j = 0; j < NumBytesPerElement; ++j) {
4828 // Note that this is x86 and so always little endian: the low byte is
4829 // the first byte of the mask.
4830 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4831 MaskElement = MaskElement.lshr(8);
4834 DecodePSHUFBMask(RawMask, Mask);
4838 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4842 SDValue Ptr = MaskLoad->getBasePtr();
4843 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4844 Ptr->getOpcode() == X86ISD::WrapperRIP)
4845 Ptr = Ptr->getOperand(0);
4847 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4848 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4851 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4852 DecodePSHUFBMask(C, Mask);
4860 case X86ISD::VPERMI:
4861 ImmN = N->getOperand(N->getNumOperands()-1);
4862 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4867 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4869 case X86ISD::VPERM2X128:
4870 ImmN = N->getOperand(N->getNumOperands()-1);
4871 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4872 if (Mask.empty()) return false;
4873 // Mask only contains negative index if an element is zero.
4874 if (std::any_of(Mask.begin(), Mask.end(),
4875 [](int M){ return M == SM_SentinelZero; }))
4878 case X86ISD::MOVSLDUP:
4879 DecodeMOVSLDUPMask(VT, Mask);
4882 case X86ISD::MOVSHDUP:
4883 DecodeMOVSHDUPMask(VT, Mask);
4886 case X86ISD::MOVDDUP:
4887 DecodeMOVDDUPMask(VT, Mask);
4890 case X86ISD::MOVLHPD:
4891 case X86ISD::MOVLPD:
4892 case X86ISD::MOVLPS:
4893 // Not yet implemented
4895 case X86ISD::VPERMV: {
4897 SDValue MaskNode = N->getOperand(0);
4898 while (MaskNode->getOpcode() == ISD::BITCAST)
4899 MaskNode = MaskNode->getOperand(0);
4901 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4902 SmallVector<uint64_t, 32> RawMask;
4903 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4904 // If we have a build-vector, then things are easy.
4905 assert(MaskNode.getSimpleValueType().isInteger() &&
4906 MaskNode.getSimpleValueType().getVectorNumElements() ==
4907 VT.getVectorNumElements());
4909 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4910 SDValue Op = MaskNode->getOperand(i);
4911 if (Op->getOpcode() == ISD::UNDEF)
4912 RawMask.push_back((uint64_t)SM_SentinelUndef);
4913 else if (isa<ConstantSDNode>(Op)) {
4914 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4915 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4919 DecodeVPERMVMask(RawMask, Mask);
4922 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4923 unsigned NumEltsInMask = MaskNode->getNumOperands();
4924 MaskNode = MaskNode->getOperand(0);
4925 if (auto *CN = dyn_cast<ConstantSDNode>(MaskNode)) {
4926 APInt MaskEltValue = CN->getAPIntValue();
4927 for (unsigned i = 0; i < NumEltsInMask; ++i)
4928 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4929 DecodeVPERMVMask(RawMask, Mask);
4932 // It may be a scalar load
4935 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4939 SDValue Ptr = MaskLoad->getBasePtr();
4940 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4941 Ptr->getOpcode() == X86ISD::WrapperRIP)
4942 Ptr = Ptr->getOperand(0);
4944 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4945 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4948 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4949 DecodeVPERMVMask(C, VT, Mask);
4956 case X86ISD::VPERMV3: {
4958 SDValue MaskNode = N->getOperand(1);
4959 while (MaskNode->getOpcode() == ISD::BITCAST)
4960 MaskNode = MaskNode->getOperand(1);
4962 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4963 // If we have a build-vector, then things are easy.
4964 assert(MaskNode.getSimpleValueType().isInteger() &&
4965 MaskNode.getSimpleValueType().getVectorNumElements() ==
4966 VT.getVectorNumElements());
4968 SmallVector<uint64_t, 32> RawMask;
4969 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4971 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4972 SDValue Op = MaskNode->getOperand(i);
4973 if (Op->getOpcode() == ISD::UNDEF)
4974 RawMask.push_back((uint64_t)SM_SentinelUndef);
4976 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4979 APInt MaskElement = CN->getAPIntValue();
4980 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4983 DecodeVPERMV3Mask(RawMask, Mask);
4987 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4991 SDValue Ptr = MaskLoad->getBasePtr();
4992 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4993 Ptr->getOpcode() == X86ISD::WrapperRIP)
4994 Ptr = Ptr->getOperand(0);
4996 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4997 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5000 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5001 DecodeVPERMV3Mask(C, VT, Mask);
5008 default: llvm_unreachable("unknown target shuffle node");
5011 // If we have a fake unary shuffle, the shuffle mask is spread across two
5012 // inputs that are actually the same node. Re-map the mask to always point
5013 // into the first input.
5016 if (M >= (int)Mask.size())
5022 /// Returns the scalar element that will make up the ith
5023 /// element of the result of the vector shuffle.
5024 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5027 return SDValue(); // Limit search depth.
5029 SDValue V = SDValue(N, 0);
5030 EVT VT = V.getValueType();
5031 unsigned Opcode = V.getOpcode();
5033 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5034 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5035 int Elt = SV->getMaskElt(Index);
5038 return DAG.getUNDEF(VT.getVectorElementType());
5040 unsigned NumElems = VT.getVectorNumElements();
5041 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5042 : SV->getOperand(1);
5043 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5046 // Recurse into target specific vector shuffles to find scalars.
5047 if (isTargetShuffle(Opcode)) {
5048 MVT ShufVT = V.getSimpleValueType();
5049 unsigned NumElems = ShufVT.getVectorNumElements();
5050 SmallVector<int, 16> ShuffleMask;
5053 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5056 int Elt = ShuffleMask[Index];
5058 return DAG.getUNDEF(ShufVT.getVectorElementType());
5060 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5062 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5066 // Actual nodes that may contain scalar elements
5067 if (Opcode == ISD::BITCAST) {
5068 V = V.getOperand(0);
5069 EVT SrcVT = V.getValueType();
5070 unsigned NumElems = VT.getVectorNumElements();
5072 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5076 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5077 return (Index == 0) ? V.getOperand(0)
5078 : DAG.getUNDEF(VT.getVectorElementType());
5080 if (V.getOpcode() == ISD::BUILD_VECTOR)
5081 return V.getOperand(Index);
5086 /// Custom lower build_vector of v16i8.
5087 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5088 unsigned NumNonZero, unsigned NumZero,
5090 const X86Subtarget* Subtarget,
5091 const TargetLowering &TLI) {
5099 // SSE4.1 - use PINSRB to insert each byte directly.
5100 if (Subtarget->hasSSE41()) {
5101 for (unsigned i = 0; i < 16; ++i) {
5102 bool isNonZero = (NonZeros & (1 << i)) != 0;
5106 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5108 V = DAG.getUNDEF(MVT::v16i8);
5111 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5112 MVT::v16i8, V, Op.getOperand(i),
5113 DAG.getIntPtrConstant(i, dl));
5120 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5121 for (unsigned i = 0; i < 16; ++i) {
5122 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5123 if (ThisIsNonZero && First) {
5125 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5127 V = DAG.getUNDEF(MVT::v8i16);
5132 SDValue ThisElt, LastElt;
5133 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5134 if (LastIsNonZero) {
5135 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5136 MVT::i16, Op.getOperand(i-1));
5138 if (ThisIsNonZero) {
5139 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5140 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5141 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5143 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5147 if (ThisElt.getNode())
5148 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5149 DAG.getIntPtrConstant(i/2, dl));
5153 return DAG.getBitcast(MVT::v16i8, V);
5156 /// Custom lower build_vector of v8i16.
5157 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5158 unsigned NumNonZero, unsigned NumZero,
5160 const X86Subtarget* Subtarget,
5161 const TargetLowering &TLI) {
5168 for (unsigned i = 0; i < 8; ++i) {
5169 bool isNonZero = (NonZeros & (1 << i)) != 0;
5173 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5175 V = DAG.getUNDEF(MVT::v8i16);
5178 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5179 MVT::v8i16, V, Op.getOperand(i),
5180 DAG.getIntPtrConstant(i, dl));
5187 /// Custom lower build_vector of v4i32 or v4f32.
5188 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5189 const X86Subtarget *Subtarget,
5190 const TargetLowering &TLI) {
5191 // Find all zeroable elements.
5192 std::bitset<4> Zeroable;
5193 for (int i=0; i < 4; ++i) {
5194 SDValue Elt = Op->getOperand(i);
5195 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5197 assert(Zeroable.size() - Zeroable.count() > 1 &&
5198 "We expect at least two non-zero elements!");
5200 // We only know how to deal with build_vector nodes where elements are either
5201 // zeroable or extract_vector_elt with constant index.
5202 SDValue FirstNonZero;
5203 unsigned FirstNonZeroIdx;
5204 for (unsigned i=0; i < 4; ++i) {
5207 SDValue Elt = Op->getOperand(i);
5208 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5209 !isa<ConstantSDNode>(Elt.getOperand(1)))
5211 // Make sure that this node is extracting from a 128-bit vector.
5212 MVT VT = Elt.getOperand(0).getSimpleValueType();
5213 if (!VT.is128BitVector())
5215 if (!FirstNonZero.getNode()) {
5217 FirstNonZeroIdx = i;
5221 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5222 SDValue V1 = FirstNonZero.getOperand(0);
5223 MVT VT = V1.getSimpleValueType();
5225 // See if this build_vector can be lowered as a blend with zero.
5227 unsigned EltMaskIdx, EltIdx;
5229 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5230 if (Zeroable[EltIdx]) {
5231 // The zero vector will be on the right hand side.
5232 Mask[EltIdx] = EltIdx+4;
5236 Elt = Op->getOperand(EltIdx);
5237 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5238 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5239 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5241 Mask[EltIdx] = EltIdx;
5245 // Let the shuffle legalizer deal with blend operations.
5246 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5247 if (V1.getSimpleValueType() != VT)
5248 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5249 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5252 // See if we can lower this build_vector to a INSERTPS.
5253 if (!Subtarget->hasSSE41())
5256 SDValue V2 = Elt.getOperand(0);
5257 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5260 bool CanFold = true;
5261 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5265 SDValue Current = Op->getOperand(i);
5266 SDValue SrcVector = Current->getOperand(0);
5269 CanFold = SrcVector == V1 &&
5270 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5276 assert(V1.getNode() && "Expected at least two non-zero elements!");
5277 if (V1.getSimpleValueType() != MVT::v4f32)
5278 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5279 if (V2.getSimpleValueType() != MVT::v4f32)
5280 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5282 // Ok, we can emit an INSERTPS instruction.
5283 unsigned ZMask = Zeroable.to_ulong();
5285 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5286 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5288 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5289 DAG.getIntPtrConstant(InsertPSMask, DL));
5290 return DAG.getBitcast(VT, Result);
5293 /// Return a vector logical shift node.
5294 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5295 unsigned NumBits, SelectionDAG &DAG,
5296 const TargetLowering &TLI, SDLoc dl) {
5297 assert(VT.is128BitVector() && "Unknown type for VShift");
5298 MVT ShVT = MVT::v2i64;
5299 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5300 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5301 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5302 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5303 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5304 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5308 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5310 // Check if the scalar load can be widened into a vector load. And if
5311 // the address is "base + cst" see if the cst can be "absorbed" into
5312 // the shuffle mask.
5313 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5314 SDValue Ptr = LD->getBasePtr();
5315 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5317 EVT PVT = LD->getValueType(0);
5318 if (PVT != MVT::i32 && PVT != MVT::f32)
5323 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5324 FI = FINode->getIndex();
5326 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5327 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5328 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5329 Offset = Ptr.getConstantOperandVal(1);
5330 Ptr = Ptr.getOperand(0);
5335 // FIXME: 256-bit vector instructions don't require a strict alignment,
5336 // improve this code to support it better.
5337 unsigned RequiredAlign = VT.getSizeInBits()/8;
5338 SDValue Chain = LD->getChain();
5339 // Make sure the stack object alignment is at least 16 or 32.
5340 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5341 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5342 if (MFI->isFixedObjectIndex(FI)) {
5343 // Can't change the alignment. FIXME: It's possible to compute
5344 // the exact stack offset and reference FI + adjust offset instead.
5345 // If someone *really* cares about this. That's the way to implement it.
5348 MFI->setObjectAlignment(FI, RequiredAlign);
5352 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5353 // Ptr + (Offset & ~15).
5356 if ((Offset % RequiredAlign) & 3)
5358 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5361 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5362 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5365 int EltNo = (Offset - StartOffset) >> 2;
5366 unsigned NumElems = VT.getVectorNumElements();
5368 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5369 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5370 LD->getPointerInfo().getWithOffset(StartOffset),
5371 false, false, false, 0);
5373 SmallVector<int, 8> Mask(NumElems, EltNo);
5375 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5381 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5382 /// elements can be replaced by a single large load which has the same value as
5383 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5385 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5387 /// FIXME: we'd also like to handle the case where the last elements are zero
5388 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5389 /// There's even a handy isZeroNode for that purpose.
5390 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5391 SDLoc &DL, SelectionDAG &DAG,
5392 bool isAfterLegalize) {
5393 unsigned NumElems = Elts.size();
5395 LoadSDNode *LDBase = nullptr;
5396 unsigned LastLoadedElt = -1U;
5398 // For each element in the initializer, see if we've found a load or an undef.
5399 // If we don't find an initial load element, or later load elements are
5400 // non-consecutive, bail out.
5401 for (unsigned i = 0; i < NumElems; ++i) {
5402 SDValue Elt = Elts[i];
5403 // Look through a bitcast.
5404 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5405 Elt = Elt.getOperand(0);
5406 if (!Elt.getNode() ||
5407 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5410 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5412 LDBase = cast<LoadSDNode>(Elt.getNode());
5416 if (Elt.getOpcode() == ISD::UNDEF)
5419 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5420 EVT LdVT = Elt.getValueType();
5421 // Each loaded element must be the correct fractional portion of the
5422 // requested vector load.
5423 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5425 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5430 // If we have found an entire vector of loads and undefs, then return a large
5431 // load of the entire vector width starting at the base pointer. If we found
5432 // consecutive loads for the low half, generate a vzext_load node.
5433 if (LastLoadedElt == NumElems - 1) {
5434 assert(LDBase && "Did not find base load for merging consecutive loads");
5435 EVT EltVT = LDBase->getValueType(0);
5436 // Ensure that the input vector size for the merged loads matches the
5437 // cumulative size of the input elements.
5438 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5441 if (isAfterLegalize &&
5442 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5445 SDValue NewLd = SDValue();
5447 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5448 LDBase->getPointerInfo(), LDBase->isVolatile(),
5449 LDBase->isNonTemporal(), LDBase->isInvariant(),
5450 LDBase->getAlignment());
5452 if (LDBase->hasAnyUseOfValue(1)) {
5453 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5455 SDValue(NewLd.getNode(), 1));
5456 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5457 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5458 SDValue(NewLd.getNode(), 1));
5464 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5465 //of a v4i32 / v4f32. It's probably worth generalizing.
5466 EVT EltVT = VT.getVectorElementType();
5467 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5468 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5469 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5470 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5472 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5473 LDBase->getPointerInfo(),
5474 LDBase->getAlignment(),
5475 false/*isVolatile*/, true/*ReadMem*/,
5478 // Make sure the newly-created LOAD is in the same position as LDBase in
5479 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5480 // update uses of LDBase's output chain to use the TokenFactor.
5481 if (LDBase->hasAnyUseOfValue(1)) {
5482 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5483 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5484 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5485 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5486 SDValue(ResNode.getNode(), 1));
5489 return DAG.getBitcast(VT, ResNode);
5494 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5495 /// to generate a splat value for the following cases:
5496 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5497 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5498 /// a scalar load, or a constant.
5499 /// The VBROADCAST node is returned when a pattern is found,
5500 /// or SDValue() otherwise.
5501 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5502 SelectionDAG &DAG) {
5503 // VBROADCAST requires AVX.
5504 // TODO: Splats could be generated for non-AVX CPUs using SSE
5505 // instructions, but there's less potential gain for only 128-bit vectors.
5506 if (!Subtarget->hasAVX())
5509 MVT VT = Op.getSimpleValueType();
5512 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5513 "Unsupported vector type for broadcast.");
5518 switch (Op.getOpcode()) {
5520 // Unknown pattern found.
5523 case ISD::BUILD_VECTOR: {
5524 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5525 BitVector UndefElements;
5526 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5528 // We need a splat of a single value to use broadcast, and it doesn't
5529 // make any sense if the value is only in one element of the vector.
5530 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5534 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5535 Ld.getOpcode() == ISD::ConstantFP);
5537 // Make sure that all of the users of a non-constant load are from the
5538 // BUILD_VECTOR node.
5539 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5544 case ISD::VECTOR_SHUFFLE: {
5545 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5547 // Shuffles must have a splat mask where the first element is
5549 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5552 SDValue Sc = Op.getOperand(0);
5553 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5554 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5556 if (!Subtarget->hasInt256())
5559 // Use the register form of the broadcast instruction available on AVX2.
5560 if (VT.getSizeInBits() >= 256)
5561 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5562 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5565 Ld = Sc.getOperand(0);
5566 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5567 Ld.getOpcode() == ISD::ConstantFP);
5569 // The scalar_to_vector node and the suspected
5570 // load node must have exactly one user.
5571 // Constants may have multiple users.
5573 // AVX-512 has register version of the broadcast
5574 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5575 Ld.getValueType().getSizeInBits() >= 32;
5576 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5583 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5584 bool IsGE256 = (VT.getSizeInBits() >= 256);
5586 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5587 // instruction to save 8 or more bytes of constant pool data.
5588 // TODO: If multiple splats are generated to load the same constant,
5589 // it may be detrimental to overall size. There needs to be a way to detect
5590 // that condition to know if this is truly a size win.
5591 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5593 // Handle broadcasting a single constant scalar from the constant pool
5595 // On Sandybridge (no AVX2), it is still better to load a constant vector
5596 // from the constant pool and not to broadcast it from a scalar.
5597 // But override that restriction when optimizing for size.
5598 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5599 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5600 EVT CVT = Ld.getValueType();
5601 assert(!CVT.isVector() && "Must not broadcast a vector type");
5603 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5604 // For size optimization, also splat v2f64 and v2i64, and for size opt
5605 // with AVX2, also splat i8 and i16.
5606 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5607 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5608 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5609 const Constant *C = nullptr;
5610 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5611 C = CI->getConstantIntValue();
5612 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5613 C = CF->getConstantFPValue();
5615 assert(C && "Invalid constant type");
5617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5619 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5620 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5622 CVT, dl, DAG.getEntryNode(), CP,
5623 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5624 false, false, Alignment);
5626 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5630 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5632 // Handle AVX2 in-register broadcasts.
5633 if (!IsLoad && Subtarget->hasInt256() &&
5634 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5635 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5637 // The scalar source must be a normal load.
5641 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5642 (Subtarget->hasVLX() && ScalarSize == 64))
5643 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5645 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5646 // double since there is no vbroadcastsd xmm
5647 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5648 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5649 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5652 // Unsupported broadcast.
5656 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5657 /// underlying vector and index.
5659 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5661 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5663 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5664 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5667 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5669 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5671 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5672 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5675 // In this case the vector is the extract_subvector expression and the index
5676 // is 2, as specified by the shuffle.
5677 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5678 SDValue ShuffleVec = SVOp->getOperand(0);
5679 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5680 assert(ShuffleVecVT.getVectorElementType() ==
5681 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5683 int ShuffleIdx = SVOp->getMaskElt(Idx);
5684 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5685 ExtractedFromVec = ShuffleVec;
5691 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5692 MVT VT = Op.getSimpleValueType();
5694 // Skip if insert_vec_elt is not supported.
5695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5696 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5700 unsigned NumElems = Op.getNumOperands();
5704 SmallVector<unsigned, 4> InsertIndices;
5705 SmallVector<int, 8> Mask(NumElems, -1);
5707 for (unsigned i = 0; i != NumElems; ++i) {
5708 unsigned Opc = Op.getOperand(i).getOpcode();
5710 if (Opc == ISD::UNDEF)
5713 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5714 // Quit if more than 1 elements need inserting.
5715 if (InsertIndices.size() > 1)
5718 InsertIndices.push_back(i);
5722 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5723 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5724 // Quit if non-constant index.
5725 if (!isa<ConstantSDNode>(ExtIdx))
5727 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5729 // Quit if extracted from vector of different type.
5730 if (ExtractedFromVec.getValueType() != VT)
5733 if (!VecIn1.getNode())
5734 VecIn1 = ExtractedFromVec;
5735 else if (VecIn1 != ExtractedFromVec) {
5736 if (!VecIn2.getNode())
5737 VecIn2 = ExtractedFromVec;
5738 else if (VecIn2 != ExtractedFromVec)
5739 // Quit if more than 2 vectors to shuffle
5743 if (ExtractedFromVec == VecIn1)
5745 else if (ExtractedFromVec == VecIn2)
5746 Mask[i] = Idx + NumElems;
5749 if (!VecIn1.getNode())
5752 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5753 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5754 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5755 unsigned Idx = InsertIndices[i];
5756 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5757 DAG.getIntPtrConstant(Idx, DL));
5763 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5764 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5765 Op.getScalarValueSizeInBits() == 1 &&
5766 "Can not convert non-constant vector");
5767 uint64_t Immediate = 0;
5768 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5769 SDValue In = Op.getOperand(idx);
5770 if (In.getOpcode() != ISD::UNDEF)
5771 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5775 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5776 return DAG.getConstant(Immediate, dl, VT);
5778 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5780 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5782 MVT VT = Op.getSimpleValueType();
5783 assert((VT.getVectorElementType() == MVT::i1) &&
5784 "Unexpected type in LowerBUILD_VECTORvXi1!");
5787 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5788 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5789 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5790 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5793 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5794 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5795 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5796 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5799 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5800 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5801 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5802 return DAG.getBitcast(VT, Imm);
5803 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5804 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5805 DAG.getIntPtrConstant(0, dl));
5808 // Vector has one or more non-const elements
5809 uint64_t Immediate = 0;
5810 SmallVector<unsigned, 16> NonConstIdx;
5811 bool IsSplat = true;
5812 bool HasConstElts = false;
5814 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5815 SDValue In = Op.getOperand(idx);
5816 if (In.getOpcode() == ISD::UNDEF)
5818 if (!isa<ConstantSDNode>(In))
5819 NonConstIdx.push_back(idx);
5821 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5822 HasConstElts = true;
5826 else if (In != Op.getOperand(SplatIdx))
5830 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5832 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5833 DAG.getConstant(1, dl, VT),
5834 DAG.getConstant(0, dl, VT));
5836 // insert elements one by one
5840 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5841 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5843 else if (HasConstElts)
5844 Imm = DAG.getConstant(0, dl, VT);
5846 Imm = DAG.getUNDEF(VT);
5847 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5848 DstVec = DAG.getBitcast(VT, Imm);
5850 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5851 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5852 DAG.getIntPtrConstant(0, dl));
5855 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5856 unsigned InsertIdx = NonConstIdx[i];
5857 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5858 Op.getOperand(InsertIdx),
5859 DAG.getIntPtrConstant(InsertIdx, dl));
5864 /// \brief Return true if \p N implements a horizontal binop and return the
5865 /// operands for the horizontal binop into V0 and V1.
5867 /// This is a helper function of LowerToHorizontalOp().
5868 /// This function checks that the build_vector \p N in input implements a
5869 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5870 /// operation to match.
5871 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5872 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5873 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5876 /// This function only analyzes elements of \p N whose indices are
5877 /// in range [BaseIdx, LastIdx).
5878 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5880 unsigned BaseIdx, unsigned LastIdx,
5881 SDValue &V0, SDValue &V1) {
5882 EVT VT = N->getValueType(0);
5884 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5885 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5886 "Invalid Vector in input!");
5888 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5889 bool CanFold = true;
5890 unsigned ExpectedVExtractIdx = BaseIdx;
5891 unsigned NumElts = LastIdx - BaseIdx;
5892 V0 = DAG.getUNDEF(VT);
5893 V1 = DAG.getUNDEF(VT);
5895 // Check if N implements a horizontal binop.
5896 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5897 SDValue Op = N->getOperand(i + BaseIdx);
5900 if (Op->getOpcode() == ISD::UNDEF) {
5901 // Update the expected vector extract index.
5902 if (i * 2 == NumElts)
5903 ExpectedVExtractIdx = BaseIdx;
5904 ExpectedVExtractIdx += 2;
5908 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5913 SDValue Op0 = Op.getOperand(0);
5914 SDValue Op1 = Op.getOperand(1);
5916 // Try to match the following pattern:
5917 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5918 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5919 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5920 Op0.getOperand(0) == Op1.getOperand(0) &&
5921 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5922 isa<ConstantSDNode>(Op1.getOperand(1)));
5926 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5927 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5929 if (i * 2 < NumElts) {
5930 if (V0.getOpcode() == ISD::UNDEF) {
5931 V0 = Op0.getOperand(0);
5932 if (V0.getValueType() != VT)
5936 if (V1.getOpcode() == ISD::UNDEF) {
5937 V1 = Op0.getOperand(0);
5938 if (V1.getValueType() != VT)
5941 if (i * 2 == NumElts)
5942 ExpectedVExtractIdx = BaseIdx;
5945 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5946 if (I0 == ExpectedVExtractIdx)
5947 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5948 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5949 // Try to match the following dag sequence:
5950 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5951 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5955 ExpectedVExtractIdx += 2;
5961 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5962 /// a concat_vector.
5964 /// This is a helper function of LowerToHorizontalOp().
5965 /// This function expects two 256-bit vectors called V0 and V1.
5966 /// At first, each vector is split into two separate 128-bit vectors.
5967 /// Then, the resulting 128-bit vectors are used to implement two
5968 /// horizontal binary operations.
5970 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5972 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5973 /// the two new horizontal binop.
5974 /// When Mode is set, the first horizontal binop dag node would take as input
5975 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5976 /// horizontal binop dag node would take as input the lower 128-bit of V1
5977 /// and the upper 128-bit of V1.
5979 /// HADD V0_LO, V0_HI
5980 /// HADD V1_LO, V1_HI
5982 /// Otherwise, the first horizontal binop dag node takes as input the lower
5983 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5984 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5986 /// HADD V0_LO, V1_LO
5987 /// HADD V0_HI, V1_HI
5989 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5990 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5991 /// the upper 128-bits of the result.
5992 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5993 SDLoc DL, SelectionDAG &DAG,
5994 unsigned X86Opcode, bool Mode,
5995 bool isUndefLO, bool isUndefHI) {
5996 EVT VT = V0.getValueType();
5997 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5998 "Invalid nodes in input!");
6000 unsigned NumElts = VT.getVectorNumElements();
6001 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6002 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6003 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6004 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6005 EVT NewVT = V0_LO.getValueType();
6007 SDValue LO = DAG.getUNDEF(NewVT);
6008 SDValue HI = DAG.getUNDEF(NewVT);
6011 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6012 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6013 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6014 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6015 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6017 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6018 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6019 V1_LO->getOpcode() != ISD::UNDEF))
6020 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6022 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6023 V1_HI->getOpcode() != ISD::UNDEF))
6024 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6027 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6030 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
6032 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
6033 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6034 MVT VT = BV->getSimpleValueType(0);
6035 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
6036 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
6040 unsigned NumElts = VT.getVectorNumElements();
6041 SDValue InVec0 = DAG.getUNDEF(VT);
6042 SDValue InVec1 = DAG.getUNDEF(VT);
6044 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6045 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6047 // Odd-numbered elements in the input build vector are obtained from
6048 // adding two integer/float elements.
6049 // Even-numbered elements in the input build vector are obtained from
6050 // subtracting two integer/float elements.
6051 unsigned ExpectedOpcode = ISD::FSUB;
6052 unsigned NextExpectedOpcode = ISD::FADD;
6053 bool AddFound = false;
6054 bool SubFound = false;
6056 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6057 SDValue Op = BV->getOperand(i);
6059 // Skip 'undef' values.
6060 unsigned Opcode = Op.getOpcode();
6061 if (Opcode == ISD::UNDEF) {
6062 std::swap(ExpectedOpcode, NextExpectedOpcode);
6066 // Early exit if we found an unexpected opcode.
6067 if (Opcode != ExpectedOpcode)
6070 SDValue Op0 = Op.getOperand(0);
6071 SDValue Op1 = Op.getOperand(1);
6073 // Try to match the following pattern:
6074 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6075 // Early exit if we cannot match that sequence.
6076 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6077 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6078 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6079 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6080 Op0.getOperand(1) != Op1.getOperand(1))
6083 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6087 // We found a valid add/sub node. Update the information accordingly.
6093 // Update InVec0 and InVec1.
6094 if (InVec0.getOpcode() == ISD::UNDEF) {
6095 InVec0 = Op0.getOperand(0);
6096 if (InVec0.getSimpleValueType() != VT)
6099 if (InVec1.getOpcode() == ISD::UNDEF) {
6100 InVec1 = Op1.getOperand(0);
6101 if (InVec1.getSimpleValueType() != VT)
6105 // Make sure that operands in input to each add/sub node always
6106 // come from a same pair of vectors.
6107 if (InVec0 != Op0.getOperand(0)) {
6108 if (ExpectedOpcode == ISD::FSUB)
6111 // FADD is commutable. Try to commute the operands
6112 // and then test again.
6113 std::swap(Op0, Op1);
6114 if (InVec0 != Op0.getOperand(0))
6118 if (InVec1 != Op1.getOperand(0))
6121 // Update the pair of expected opcodes.
6122 std::swap(ExpectedOpcode, NextExpectedOpcode);
6125 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6126 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6127 InVec1.getOpcode() != ISD::UNDEF)
6128 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6133 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6134 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6135 const X86Subtarget *Subtarget,
6136 SelectionDAG &DAG) {
6137 MVT VT = BV->getSimpleValueType(0);
6138 unsigned NumElts = VT.getVectorNumElements();
6139 unsigned NumUndefsLO = 0;
6140 unsigned NumUndefsHI = 0;
6141 unsigned Half = NumElts/2;
6143 // Count the number of UNDEF operands in the build_vector in input.
6144 for (unsigned i = 0, e = Half; i != e; ++i)
6145 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6148 for (unsigned i = Half, e = NumElts; i != e; ++i)
6149 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6152 // Early exit if this is either a build_vector of all UNDEFs or all the
6153 // operands but one are UNDEF.
6154 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6158 SDValue InVec0, InVec1;
6159 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6160 // Try to match an SSE3 float HADD/HSUB.
6161 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6162 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6164 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6165 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6166 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6167 // Try to match an SSSE3 integer HADD/HSUB.
6168 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6169 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6171 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6172 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6175 if (!Subtarget->hasAVX())
6178 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6179 // Try to match an AVX horizontal add/sub of packed single/double
6180 // precision floating point values from 256-bit vectors.
6181 SDValue InVec2, InVec3;
6182 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6183 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6184 ((InVec0.getOpcode() == ISD::UNDEF ||
6185 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6186 ((InVec1.getOpcode() == ISD::UNDEF ||
6187 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6188 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6190 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6191 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6192 ((InVec0.getOpcode() == ISD::UNDEF ||
6193 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6194 ((InVec1.getOpcode() == ISD::UNDEF ||
6195 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6196 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6197 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6198 // Try to match an AVX2 horizontal add/sub of signed integers.
6199 SDValue InVec2, InVec3;
6201 bool CanFold = true;
6203 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6204 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6205 ((InVec0.getOpcode() == ISD::UNDEF ||
6206 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6207 ((InVec1.getOpcode() == ISD::UNDEF ||
6208 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6209 X86Opcode = X86ISD::HADD;
6210 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6211 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6212 ((InVec0.getOpcode() == ISD::UNDEF ||
6213 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6214 ((InVec1.getOpcode() == ISD::UNDEF ||
6215 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6216 X86Opcode = X86ISD::HSUB;
6221 // Fold this build_vector into a single horizontal add/sub.
6222 // Do this only if the target has AVX2.
6223 if (Subtarget->hasAVX2())
6224 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6226 // Do not try to expand this build_vector into a pair of horizontal
6227 // add/sub if we can emit a pair of scalar add/sub.
6228 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6231 // Convert this build_vector into a pair of horizontal binop followed by
6233 bool isUndefLO = NumUndefsLO == Half;
6234 bool isUndefHI = NumUndefsHI == Half;
6235 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6236 isUndefLO, isUndefHI);
6240 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6241 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6243 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6244 X86Opcode = X86ISD::HADD;
6245 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6246 X86Opcode = X86ISD::HSUB;
6247 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6248 X86Opcode = X86ISD::FHADD;
6249 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6250 X86Opcode = X86ISD::FHSUB;
6254 // Don't try to expand this build_vector into a pair of horizontal add/sub
6255 // if we can simply emit a pair of scalar add/sub.
6256 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6259 // Convert this build_vector into two horizontal add/sub followed by
6261 bool isUndefLO = NumUndefsLO == Half;
6262 bool isUndefHI = NumUndefsHI == Half;
6263 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6264 isUndefLO, isUndefHI);
6271 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6274 MVT VT = Op.getSimpleValueType();
6275 MVT ExtVT = VT.getVectorElementType();
6276 unsigned NumElems = Op.getNumOperands();
6278 // Generate vectors for predicate vectors.
6279 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6280 return LowerBUILD_VECTORvXi1(Op, DAG);
6282 // Vectors containing all zeros can be matched by pxor and xorps later
6283 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6284 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6285 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6286 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6289 return getZeroVector(VT, Subtarget, DAG, dl);
6292 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6293 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6294 // vpcmpeqd on 256-bit vectors.
6295 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6296 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6299 if (!VT.is512BitVector())
6300 return getOnesVector(VT, Subtarget, DAG, dl);
6303 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6304 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6306 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6307 return HorizontalOp;
6308 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6311 unsigned EVTBits = ExtVT.getSizeInBits();
6313 unsigned NumZero = 0;
6314 unsigned NumNonZero = 0;
6315 uint64_t NonZeros = 0;
6316 bool IsAllConstants = true;
6317 SmallSet<SDValue, 8> Values;
6318 for (unsigned i = 0; i < NumElems; ++i) {
6319 SDValue Elt = Op.getOperand(i);
6320 if (Elt.getOpcode() == ISD::UNDEF)
6323 if (Elt.getOpcode() != ISD::Constant &&
6324 Elt.getOpcode() != ISD::ConstantFP)
6325 IsAllConstants = false;
6326 if (X86::isZeroNode(Elt))
6329 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6330 NonZeros |= ((uint64_t)1 << i);
6335 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6336 if (NumNonZero == 0)
6337 return DAG.getUNDEF(VT);
6339 // Special case for single non-zero, non-undef, element.
6340 if (NumNonZero == 1) {
6341 unsigned Idx = countTrailingZeros(NonZeros);
6342 SDValue Item = Op.getOperand(Idx);
6344 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6345 // the value are obviously zero, truncate the value to i32 and do the
6346 // insertion that way. Only do this if the value is non-constant or if the
6347 // value is a constant being inserted into element 0. It is cheaper to do
6348 // a constant pool load than it is to do a movd + shuffle.
6349 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6350 (!IsAllConstants || Idx == 0)) {
6351 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6353 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6354 MVT VecVT = MVT::v4i32;
6356 // Truncate the value (which may itself be a constant) to i32, and
6357 // convert it to a vector with movd (S2V+shuffle to zero extend).
6358 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6359 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6360 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6361 Item, Idx * 2, true, Subtarget, DAG));
6365 // If we have a constant or non-constant insertion into the low element of
6366 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6367 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6368 // depending on what the source datatype is.
6371 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6373 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6374 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6375 if (VT.is512BitVector()) {
6376 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6377 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6378 Item, DAG.getIntPtrConstant(0, dl));
6380 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6381 "Expected an SSE value type!");
6382 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6383 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6384 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6387 // We can't directly insert an i8 or i16 into a vector, so zero extend
6389 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6390 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6391 if (VT.is256BitVector()) {
6392 if (Subtarget->hasAVX()) {
6393 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6394 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6396 // Without AVX, we need to extend to a 128-bit vector and then
6397 // insert into the 256-bit vector.
6398 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6399 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6400 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6403 assert(VT.is128BitVector() && "Expected an SSE value type!");
6404 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6405 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6407 return DAG.getBitcast(VT, Item);
6411 // Is it a vector logical left shift?
6412 if (NumElems == 2 && Idx == 1 &&
6413 X86::isZeroNode(Op.getOperand(0)) &&
6414 !X86::isZeroNode(Op.getOperand(1))) {
6415 unsigned NumBits = VT.getSizeInBits();
6416 return getVShift(true, VT,
6417 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6418 VT, Op.getOperand(1)),
6419 NumBits/2, DAG, *this, dl);
6422 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6425 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6426 // is a non-constant being inserted into an element other than the low one,
6427 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6428 // movd/movss) to move this into the low element, then shuffle it into
6430 if (EVTBits == 32) {
6431 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6432 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6436 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6437 if (Values.size() == 1) {
6438 if (EVTBits == 32) {
6439 // Instead of a shuffle like this:
6440 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6441 // Check if it's possible to issue this instead.
6442 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6443 unsigned Idx = countTrailingZeros(NonZeros);
6444 SDValue Item = Op.getOperand(Idx);
6445 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6446 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6451 // A vector full of immediates; various special cases are already
6452 // handled, so this is best done with a single constant-pool load.
6456 // For AVX-length vectors, see if we can use a vector load to get all of the
6457 // elements, otherwise build the individual 128-bit pieces and use
6458 // shuffles to put them in place.
6459 if (VT.is256BitVector() || VT.is512BitVector()) {
6460 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6462 // Check for a build vector of consecutive loads.
6463 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6466 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6468 // Build both the lower and upper subvector.
6469 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6470 makeArrayRef(&V[0], NumElems/2));
6471 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6472 makeArrayRef(&V[NumElems / 2], NumElems/2));
6474 // Recreate the wider vector with the lower and upper part.
6475 if (VT.is256BitVector())
6476 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6477 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6480 // Let legalizer expand 2-wide build_vectors.
6481 if (EVTBits == 64) {
6482 if (NumNonZero == 1) {
6483 // One half is zero or undef.
6484 unsigned Idx = countTrailingZeros(NonZeros);
6485 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6486 Op.getOperand(Idx));
6487 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6492 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6493 if (EVTBits == 8 && NumElems == 16)
6494 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6495 DAG, Subtarget, *this))
6498 if (EVTBits == 16 && NumElems == 8)
6499 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6500 DAG, Subtarget, *this))
6503 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6504 if (EVTBits == 32 && NumElems == 4)
6505 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6508 // If element VT is == 32 bits, turn it into a number of shuffles.
6509 SmallVector<SDValue, 8> V(NumElems);
6510 if (NumElems == 4 && NumZero > 0) {
6511 for (unsigned i = 0; i < 4; ++i) {
6512 bool isZero = !(NonZeros & (1ULL << i));
6514 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6516 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6519 for (unsigned i = 0; i < 2; ++i) {
6520 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6523 V[i] = V[i*2]; // Must be a zero vector.
6526 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6529 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6532 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6537 bool Reverse1 = (NonZeros & 0x3) == 2;
6538 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6542 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6543 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6545 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6548 if (Values.size() > 1 && VT.is128BitVector()) {
6549 // Check for a build vector of consecutive loads.
6550 for (unsigned i = 0; i < NumElems; ++i)
6551 V[i] = Op.getOperand(i);
6553 // Check for elements which are consecutive loads.
6554 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6557 // Check for a build vector from mostly shuffle plus few inserting.
6558 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6561 // For SSE 4.1, use insertps to put the high elements into the low element.
6562 if (Subtarget->hasSSE41()) {
6564 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6565 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6567 Result = DAG.getUNDEF(VT);
6569 for (unsigned i = 1; i < NumElems; ++i) {
6570 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6571 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6572 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6577 // Otherwise, expand into a number of unpckl*, start by extending each of
6578 // our (non-undef) elements to the full vector width with the element in the
6579 // bottom slot of the vector (which generates no code for SSE).
6580 for (unsigned i = 0; i < NumElems; ++i) {
6581 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6582 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6584 V[i] = DAG.getUNDEF(VT);
6587 // Next, we iteratively mix elements, e.g. for v4f32:
6588 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6589 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6590 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6591 unsigned EltStride = NumElems >> 1;
6592 while (EltStride != 0) {
6593 for (unsigned i = 0; i < EltStride; ++i) {
6594 // If V[i+EltStride] is undef and this is the first round of mixing,
6595 // then it is safe to just drop this shuffle: V[i] is already in the
6596 // right place, the one element (since it's the first round) being
6597 // inserted as undef can be dropped. This isn't safe for successive
6598 // rounds because they will permute elements within both vectors.
6599 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6600 EltStride == NumElems/2)
6603 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6612 // 256-bit AVX can use the vinsertf128 instruction
6613 // to create 256-bit vectors from two other 128-bit ones.
6614 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6616 MVT ResVT = Op.getSimpleValueType();
6618 assert((ResVT.is256BitVector() ||
6619 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6621 SDValue V1 = Op.getOperand(0);
6622 SDValue V2 = Op.getOperand(1);
6623 unsigned NumElems = ResVT.getVectorNumElements();
6624 if (ResVT.is256BitVector())
6625 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6627 if (Op.getNumOperands() == 4) {
6628 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6629 ResVT.getVectorNumElements()/2);
6630 SDValue V3 = Op.getOperand(2);
6631 SDValue V4 = Op.getOperand(3);
6632 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6633 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6635 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6638 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6639 const X86Subtarget *Subtarget,
6640 SelectionDAG & DAG) {
6642 MVT ResVT = Op.getSimpleValueType();
6643 unsigned NumOfOperands = Op.getNumOperands();
6645 assert(isPowerOf2_32(NumOfOperands) &&
6646 "Unexpected number of operands in CONCAT_VECTORS");
6648 SDValue Undef = DAG.getUNDEF(ResVT);
6649 if (NumOfOperands > 2) {
6650 // Specialize the cases when all, or all but one, of the operands are undef.
6651 unsigned NumOfDefinedOps = 0;
6653 for (unsigned i = 0; i < NumOfOperands; i++)
6654 if (!Op.getOperand(i).isUndef()) {
6658 if (NumOfDefinedOps == 0)
6660 if (NumOfDefinedOps == 1) {
6661 unsigned SubVecNumElts =
6662 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6663 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6664 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6665 Op.getOperand(OpIdx), IdxVal);
6668 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6669 ResVT.getVectorNumElements()/2);
6670 SmallVector<SDValue, 2> Ops;
6671 for (unsigned i = 0; i < NumOfOperands/2; i++)
6672 Ops.push_back(Op.getOperand(i));
6673 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6675 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6676 Ops.push_back(Op.getOperand(i));
6677 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6678 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6682 SDValue V1 = Op.getOperand(0);
6683 SDValue V2 = Op.getOperand(1);
6684 unsigned NumElems = ResVT.getVectorNumElements();
6685 assert(V1.getValueType() == V2.getValueType() &&
6686 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6687 "Unexpected operands in CONCAT_VECTORS");
6689 if (ResVT.getSizeInBits() >= 16)
6690 return Op; // The operation is legal with KUNPCK
6692 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6693 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6694 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6695 if (IsZeroV1 && IsZeroV2)
6698 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6700 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6702 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6704 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6706 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6709 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6711 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6712 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6715 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6716 const X86Subtarget *Subtarget,
6717 SelectionDAG &DAG) {
6718 MVT VT = Op.getSimpleValueType();
6719 if (VT.getVectorElementType() == MVT::i1)
6720 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6722 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6723 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6724 Op.getNumOperands() == 4)));
6726 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6727 // from two other 128-bit ones.
6729 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6730 return LowerAVXCONCAT_VECTORS(Op, DAG);
6733 //===----------------------------------------------------------------------===//
6734 // Vector shuffle lowering
6736 // This is an experimental code path for lowering vector shuffles on x86. It is
6737 // designed to handle arbitrary vector shuffles and blends, gracefully
6738 // degrading performance as necessary. It works hard to recognize idiomatic
6739 // shuffles and lower them to optimal instruction patterns without leaving
6740 // a framework that allows reasonably efficient handling of all vector shuffle
6742 //===----------------------------------------------------------------------===//
6744 /// \brief Tiny helper function to identify a no-op mask.
6746 /// This is a somewhat boring predicate function. It checks whether the mask
6747 /// array input, which is assumed to be a single-input shuffle mask of the kind
6748 /// used by the X86 shuffle instructions (not a fully general
6749 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6750 /// in-place shuffle are 'no-op's.
6751 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6752 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6753 if (Mask[i] != -1 && Mask[i] != i)
6758 /// \brief Helper function to classify a mask as a single-input mask.
6760 /// This isn't a generic single-input test because in the vector shuffle
6761 /// lowering we canonicalize single inputs to be the first input operand. This
6762 /// means we can more quickly test for a single input by only checking whether
6763 /// an input from the second operand exists. We also assume that the size of
6764 /// mask corresponds to the size of the input vectors which isn't true in the
6765 /// fully general case.
6766 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6768 if (M >= (int)Mask.size())
6773 /// \brief Test whether there are elements crossing 128-bit lanes in this
6776 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6777 /// and we routinely test for these.
6778 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6779 int LaneSize = 128 / VT.getScalarSizeInBits();
6780 int Size = Mask.size();
6781 for (int i = 0; i < Size; ++i)
6782 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6787 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6789 /// This checks a shuffle mask to see if it is performing the same
6790 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6791 /// that it is also not lane-crossing. It may however involve a blend from the
6792 /// same lane of a second vector.
6794 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6795 /// non-trivial to compute in the face of undef lanes. The representation is
6796 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6797 /// entries from both V1 and V2 inputs to the wider mask.
6799 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6800 SmallVectorImpl<int> &RepeatedMask) {
6801 int LaneSize = 128 / VT.getScalarSizeInBits();
6802 RepeatedMask.resize(LaneSize, -1);
6803 int Size = Mask.size();
6804 for (int i = 0; i < Size; ++i) {
6807 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6808 // This entry crosses lanes, so there is no way to model this shuffle.
6811 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6812 if (RepeatedMask[i % LaneSize] == -1)
6813 // This is the first non-undef entry in this slot of a 128-bit lane.
6814 RepeatedMask[i % LaneSize] =
6815 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6816 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6817 // Found a mismatch with the repeated mask.
6823 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6826 /// This is a fast way to test a shuffle mask against a fixed pattern:
6828 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6830 /// It returns true if the mask is exactly as wide as the argument list, and
6831 /// each element of the mask is either -1 (signifying undef) or the value given
6832 /// in the argument.
6833 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6834 ArrayRef<int> ExpectedMask) {
6835 if (Mask.size() != ExpectedMask.size())
6838 int Size = Mask.size();
6840 // If the values are build vectors, we can look through them to find
6841 // equivalent inputs that make the shuffles equivalent.
6842 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6843 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6845 for (int i = 0; i < Size; ++i)
6846 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6847 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6848 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6849 if (!MaskBV || !ExpectedBV ||
6850 MaskBV->getOperand(Mask[i] % Size) !=
6851 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6858 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6860 /// This helper function produces an 8-bit shuffle immediate corresponding to
6861 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6862 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6865 /// NB: We rely heavily on "undef" masks preserving the input lane.
6866 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6867 SelectionDAG &DAG) {
6868 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6869 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6870 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6871 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6872 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6875 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6876 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6877 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6878 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6879 return DAG.getConstant(Imm, DL, MVT::i8);
6882 /// \brief Compute whether each element of a shuffle is zeroable.
6884 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6885 /// Either it is an undef element in the shuffle mask, the element of the input
6886 /// referenced is undef, or the element of the input referenced is known to be
6887 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6888 /// as many lanes with this technique as possible to simplify the remaining
6890 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6891 SDValue V1, SDValue V2) {
6892 SmallBitVector Zeroable(Mask.size(), false);
6894 while (V1.getOpcode() == ISD::BITCAST)
6895 V1 = V1->getOperand(0);
6896 while (V2.getOpcode() == ISD::BITCAST)
6897 V2 = V2->getOperand(0);
6899 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6900 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6902 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6904 // Handle the easy cases.
6905 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6910 // If this is an index into a build_vector node (which has the same number
6911 // of elements), dig out the input value and use it.
6912 SDValue V = M < Size ? V1 : V2;
6913 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6916 SDValue Input = V.getOperand(M % Size);
6917 // The UNDEF opcode check really should be dead code here, but not quite
6918 // worth asserting on (it isn't invalid, just unexpected).
6919 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6926 // X86 has dedicated unpack instructions that can handle specific blend
6927 // operations: UNPCKH and UNPCKL.
6928 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6929 SDValue V1, SDValue V2,
6930 SelectionDAG &DAG) {
6931 int NumElts = VT.getVectorNumElements();
6932 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6933 SmallVector<int, 8> Unpckl;
6934 SmallVector<int, 8> Unpckh;
6936 for (int i = 0; i < NumElts; ++i) {
6937 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6938 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6939 int HiPos = LoPos + NumEltsInLane / 2;
6940 Unpckl.push_back(LoPos);
6941 Unpckh.push_back(HiPos);
6944 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6945 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6946 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6947 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6949 // Commute and try again.
6950 ShuffleVectorSDNode::commuteMask(Unpckl);
6951 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6952 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6954 ShuffleVectorSDNode::commuteMask(Unpckh);
6955 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6956 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6961 /// \brief Try to emit a bitmask instruction for a shuffle.
6963 /// This handles cases where we can model a blend exactly as a bitmask due to
6964 /// one of the inputs being zeroable.
6965 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6966 SDValue V2, ArrayRef<int> Mask,
6967 SelectionDAG &DAG) {
6968 MVT EltVT = VT.getVectorElementType();
6969 int NumEltBits = EltVT.getSizeInBits();
6970 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6971 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6972 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6974 if (EltVT.isFloatingPoint()) {
6975 Zero = DAG.getBitcast(EltVT, Zero);
6976 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6978 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6979 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6981 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6984 if (Mask[i] % Size != i)
6985 return SDValue(); // Not a blend.
6987 V = Mask[i] < Size ? V1 : V2;
6988 else if (V != (Mask[i] < Size ? V1 : V2))
6989 return SDValue(); // Can only let one input through the mask.
6991 VMaskOps[i] = AllOnes;
6994 return SDValue(); // No non-zeroable elements!
6996 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6997 V = DAG.getNode(VT.isFloatingPoint()
6998 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
7003 /// \brief Try to emit a blend instruction for a shuffle using bit math.
7005 /// This is used as a fallback approach when first class blend instructions are
7006 /// unavailable. Currently it is only suitable for integer vectors, but could
7007 /// be generalized for floating point vectors if desirable.
7008 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
7009 SDValue V2, ArrayRef<int> Mask,
7010 SelectionDAG &DAG) {
7011 assert(VT.isInteger() && "Only supports integer vector types!");
7012 MVT EltVT = VT.getVectorElementType();
7013 int NumEltBits = EltVT.getSizeInBits();
7014 SDValue Zero = DAG.getConstant(0, DL, EltVT);
7015 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
7017 SmallVector<SDValue, 16> MaskOps;
7018 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7019 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
7020 return SDValue(); // Shuffled input!
7021 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
7024 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
7025 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
7026 // We have to cast V2 around.
7027 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
7028 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
7029 DAG.getBitcast(MaskVT, V1Mask),
7030 DAG.getBitcast(MaskVT, V2)));
7031 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
7034 /// \brief Try to emit a blend instruction for a shuffle.
7036 /// This doesn't do any checks for the availability of instructions for blending
7037 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7038 /// be matched in the backend with the type given. What it does check for is
7039 /// that the shuffle mask is a blend, or convertible into a blend with zero.
7040 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7041 SDValue V2, ArrayRef<int> Original,
7042 const X86Subtarget *Subtarget,
7043 SelectionDAG &DAG) {
7044 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7045 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7046 SmallVector<int, 8> Mask(Original.begin(), Original.end());
7047 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7048 bool ForceV1Zero = false, ForceV2Zero = false;
7050 // Attempt to generate the binary blend mask. If an input is zero then
7051 // we can use any lane.
7052 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
7053 unsigned BlendMask = 0;
7054 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7060 if (M == i + Size) {
7061 BlendMask |= 1u << i;
7072 BlendMask |= 1u << i;
7077 return SDValue(); // Shuffled input!
7080 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7082 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7084 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7086 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7087 unsigned ScaledMask = 0;
7088 for (int i = 0; i != Size; ++i)
7089 if (BlendMask & (1u << i))
7090 for (int j = 0; j != Scale; ++j)
7091 ScaledMask |= 1u << (i * Scale + j);
7095 switch (VT.SimpleTy) {
7100 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7101 DAG.getConstant(BlendMask, DL, MVT::i8));
7105 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7109 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7110 // that instruction.
7111 if (Subtarget->hasAVX2()) {
7112 // Scale the blend by the number of 32-bit dwords per element.
7113 int Scale = VT.getScalarSizeInBits() / 32;
7114 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7115 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7116 V1 = DAG.getBitcast(BlendVT, V1);
7117 V2 = DAG.getBitcast(BlendVT, V2);
7118 return DAG.getBitcast(
7119 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7120 DAG.getConstant(BlendMask, DL, MVT::i8)));
7124 // For integer shuffles we need to expand the mask and cast the inputs to
7125 // v8i16s prior to blending.
7126 int Scale = 8 / VT.getVectorNumElements();
7127 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7128 V1 = DAG.getBitcast(MVT::v8i16, V1);
7129 V2 = DAG.getBitcast(MVT::v8i16, V2);
7130 return DAG.getBitcast(VT,
7131 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7132 DAG.getConstant(BlendMask, DL, MVT::i8)));
7136 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7137 SmallVector<int, 8> RepeatedMask;
7138 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7139 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7140 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7142 for (int i = 0; i < 8; ++i)
7143 if (RepeatedMask[i] >= 16)
7144 BlendMask |= 1u << i;
7145 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7146 DAG.getConstant(BlendMask, DL, MVT::i8));
7152 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7153 "256-bit byte-blends require AVX2 support!");
7155 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7156 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7159 // Scale the blend by the number of bytes per element.
7160 int Scale = VT.getScalarSizeInBits() / 8;
7162 // This form of blend is always done on bytes. Compute the byte vector
7164 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7166 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7167 // mix of LLVM's code generator and the x86 backend. We tell the code
7168 // generator that boolean values in the elements of an x86 vector register
7169 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7170 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7171 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7172 // of the element (the remaining are ignored) and 0 in that high bit would
7173 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7174 // the LLVM model for boolean values in vector elements gets the relevant
7175 // bit set, it is set backwards and over constrained relative to x86's
7177 SmallVector<SDValue, 32> VSELECTMask;
7178 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7179 for (int j = 0; j < Scale; ++j)
7180 VSELECTMask.push_back(
7181 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7182 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7185 V1 = DAG.getBitcast(BlendVT, V1);
7186 V2 = DAG.getBitcast(BlendVT, V2);
7187 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7188 DAG.getNode(ISD::BUILD_VECTOR, DL,
7189 BlendVT, VSELECTMask),
7194 llvm_unreachable("Not a supported integer vector type!");
7198 /// \brief Try to lower as a blend of elements from two inputs followed by
7199 /// a single-input permutation.
7201 /// This matches the pattern where we can blend elements from two inputs and
7202 /// then reduce the shuffle to a single-input permutation.
7203 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7206 SelectionDAG &DAG) {
7207 // We build up the blend mask while checking whether a blend is a viable way
7208 // to reduce the shuffle.
7209 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7210 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7212 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7216 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7218 if (BlendMask[Mask[i] % Size] == -1)
7219 BlendMask[Mask[i] % Size] = Mask[i];
7220 else if (BlendMask[Mask[i] % Size] != Mask[i])
7221 return SDValue(); // Can't blend in the needed input!
7223 PermuteMask[i] = Mask[i] % Size;
7226 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7227 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7230 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7231 /// blends and permutes.
7233 /// This matches the extremely common pattern for handling combined
7234 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7235 /// operations. It will try to pick the best arrangement of shuffles and
7237 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7241 SelectionDAG &DAG) {
7242 // Shuffle the input elements into the desired positions in V1 and V2 and
7243 // blend them together.
7244 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7245 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7246 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7247 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7248 if (Mask[i] >= 0 && Mask[i] < Size) {
7249 V1Mask[i] = Mask[i];
7251 } else if (Mask[i] >= Size) {
7252 V2Mask[i] = Mask[i] - Size;
7253 BlendMask[i] = i + Size;
7256 // Try to lower with the simpler initial blend strategy unless one of the
7257 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7258 // shuffle may be able to fold with a load or other benefit. However, when
7259 // we'll have to do 2x as many shuffles in order to achieve this, blending
7260 // first is a better strategy.
7261 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7262 if (SDValue BlendPerm =
7263 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7266 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7267 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7268 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7271 /// \brief Try to lower a vector shuffle as a byte rotation.
7273 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7274 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7275 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7276 /// try to generically lower a vector shuffle through such an pattern. It
7277 /// does not check for the profitability of lowering either as PALIGNR or
7278 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7279 /// This matches shuffle vectors that look like:
7281 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7283 /// Essentially it concatenates V1 and V2, shifts right by some number of
7284 /// elements, and takes the low elements as the result. Note that while this is
7285 /// specified as a *right shift* because x86 is little-endian, it is a *left
7286 /// rotate* of the vector lanes.
7287 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7290 const X86Subtarget *Subtarget,
7291 SelectionDAG &DAG) {
7292 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7294 int NumElts = Mask.size();
7295 int NumLanes = VT.getSizeInBits() / 128;
7296 int NumLaneElts = NumElts / NumLanes;
7298 // We need to detect various ways of spelling a rotation:
7299 // [11, 12, 13, 14, 15, 0, 1, 2]
7300 // [-1, 12, 13, 14, -1, -1, 1, -1]
7301 // [-1, -1, -1, -1, -1, -1, 1, 2]
7302 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7303 // [-1, 4, 5, 6, -1, -1, 9, -1]
7304 // [-1, 4, 5, 6, -1, -1, -1, -1]
7307 for (int l = 0; l < NumElts; l += NumLaneElts) {
7308 for (int i = 0; i < NumLaneElts; ++i) {
7309 if (Mask[l + i] == -1)
7311 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7313 // Get the mod-Size index and lane correct it.
7314 int LaneIdx = (Mask[l + i] % NumElts) - l;
7315 // Make sure it was in this lane.
7316 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7319 // Determine where a rotated vector would have started.
7320 int StartIdx = i - LaneIdx;
7322 // The identity rotation isn't interesting, stop.
7325 // If we found the tail of a vector the rotation must be the missing
7326 // front. If we found the head of a vector, it must be how much of the
7328 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7331 Rotation = CandidateRotation;
7332 else if (Rotation != CandidateRotation)
7333 // The rotations don't match, so we can't match this mask.
7336 // Compute which value this mask is pointing at.
7337 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7339 // Compute which of the two target values this index should be assigned
7340 // to. This reflects whether the high elements are remaining or the low
7341 // elements are remaining.
7342 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7344 // Either set up this value if we've not encountered it before, or check
7345 // that it remains consistent.
7348 else if (TargetV != MaskV)
7349 // This may be a rotation, but it pulls from the inputs in some
7350 // unsupported interleaving.
7355 // Check that we successfully analyzed the mask, and normalize the results.
7356 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7357 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7363 // The actual rotate instruction rotates bytes, so we need to scale the
7364 // rotation based on how many bytes are in the vector lane.
7365 int Scale = 16 / NumLaneElts;
7367 // SSSE3 targets can use the palignr instruction.
7368 if (Subtarget->hasSSSE3()) {
7369 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7370 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7371 Lo = DAG.getBitcast(AlignVT, Lo);
7372 Hi = DAG.getBitcast(AlignVT, Hi);
7374 return DAG.getBitcast(
7375 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7376 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7379 assert(VT.is128BitVector() &&
7380 "Rotate-based lowering only supports 128-bit lowering!");
7381 assert(Mask.size() <= 16 &&
7382 "Can shuffle at most 16 bytes in a 128-bit vector!");
7384 // Default SSE2 implementation
7385 int LoByteShift = 16 - Rotation * Scale;
7386 int HiByteShift = Rotation * Scale;
7388 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7389 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7390 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7392 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7393 DAG.getConstant(LoByteShift, DL, MVT::i8));
7394 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7395 DAG.getConstant(HiByteShift, DL, MVT::i8));
7396 return DAG.getBitcast(VT,
7397 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7400 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7402 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7403 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7404 /// matches elements from one of the input vectors shuffled to the left or
7405 /// right with zeroable elements 'shifted in'. It handles both the strictly
7406 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7409 /// PSHL : (little-endian) left bit shift.
7410 /// [ zz, 0, zz, 2 ]
7411 /// [ -1, 4, zz, -1 ]
7412 /// PSRL : (little-endian) right bit shift.
7414 /// [ -1, -1, 7, zz]
7415 /// PSLLDQ : (little-endian) left byte shift
7416 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7417 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7418 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7419 /// PSRLDQ : (little-endian) right byte shift
7420 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7421 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7422 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7423 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7424 SDValue V2, ArrayRef<int> Mask,
7425 SelectionDAG &DAG) {
7426 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7428 int Size = Mask.size();
7429 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7431 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7432 for (int i = 0; i < Size; i += Scale)
7433 for (int j = 0; j < Shift; ++j)
7434 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7440 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7441 for (int i = 0; i != Size; i += Scale) {
7442 unsigned Pos = Left ? i + Shift : i;
7443 unsigned Low = Left ? i : i + Shift;
7444 unsigned Len = Scale - Shift;
7445 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7446 Low + (V == V1 ? 0 : Size)))
7450 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7451 bool ByteShift = ShiftEltBits > 64;
7452 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7453 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7454 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7456 // Normalize the scale for byte shifts to still produce an i64 element
7458 Scale = ByteShift ? Scale / 2 : Scale;
7460 // We need to round trip through the appropriate type for the shift.
7461 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7462 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7463 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7464 "Illegal integer vector type");
7465 V = DAG.getBitcast(ShiftVT, V);
7467 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7468 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7469 return DAG.getBitcast(VT, V);
7472 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7473 // keep doubling the size of the integer elements up to that. We can
7474 // then shift the elements of the integer vector by whole multiples of
7475 // their width within the elements of the larger integer vector. Test each
7476 // multiple to see if we can find a match with the moved element indices
7477 // and that the shifted in elements are all zeroable.
7478 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7479 for (int Shift = 1; Shift != Scale; ++Shift)
7480 for (bool Left : {true, false})
7481 if (CheckZeros(Shift, Scale, Left))
7482 for (SDValue V : {V1, V2})
7483 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7490 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7491 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7492 SDValue V2, ArrayRef<int> Mask,
7493 SelectionDAG &DAG) {
7494 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7495 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7497 int Size = Mask.size();
7498 int HalfSize = Size / 2;
7499 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7501 // Upper half must be undefined.
7502 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7505 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7506 // Remainder of lower half result is zero and upper half is all undef.
7507 auto LowerAsEXTRQ = [&]() {
7508 // Determine the extraction length from the part of the
7509 // lower half that isn't zeroable.
7511 for (; Len > 0; --Len)
7512 if (!Zeroable[Len - 1])
7514 assert(Len > 0 && "Zeroable shuffle mask");
7516 // Attempt to match first Len sequential elements from the lower half.
7519 for (int i = 0; i != Len; ++i) {
7523 SDValue &V = (M < Size ? V1 : V2);
7526 // The extracted elements must start at a valid index and all mask
7527 // elements must be in the lower half.
7528 if (i > M || M >= HalfSize)
7531 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7542 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7543 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7544 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7545 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7546 DAG.getConstant(BitLen, DL, MVT::i8),
7547 DAG.getConstant(BitIdx, DL, MVT::i8));
7550 if (SDValue ExtrQ = LowerAsEXTRQ())
7553 // INSERTQ: Extract lowest Len elements from lower half of second source and
7554 // insert over first source, starting at Idx.
7555 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7556 auto LowerAsInsertQ = [&]() {
7557 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7560 // Attempt to match first source from mask before insertion point.
7561 if (isUndefInRange(Mask, 0, Idx)) {
7563 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7565 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7571 // Extend the extraction length looking to match both the insertion of
7572 // the second source and the remaining elements of the first.
7573 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7578 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7580 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7586 // Match the remaining elements of the lower half.
7587 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7589 } else if ((!Base || (Base == V1)) &&
7590 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7592 } else if ((!Base || (Base == V2)) &&
7593 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7600 // We may not have a base (first source) - this can safely be undefined.
7602 Base = DAG.getUNDEF(VT);
7604 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7605 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7606 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7607 DAG.getConstant(BitLen, DL, MVT::i8),
7608 DAG.getConstant(BitIdx, DL, MVT::i8));
7615 if (SDValue InsertQ = LowerAsInsertQ())
7621 /// \brief Lower a vector shuffle as a zero or any extension.
7623 /// Given a specific number of elements, element bit width, and extension
7624 /// stride, produce either a zero or any extension based on the available
7625 /// features of the subtarget. The extended elements are consecutive and
7626 /// begin and can start from an offseted element index in the input; to
7627 /// avoid excess shuffling the offset must either being in the bottom lane
7628 /// or at the start of a higher lane. All extended elements must be from
7630 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7631 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7632 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7633 assert(Scale > 1 && "Need a scale to extend.");
7634 int EltBits = VT.getScalarSizeInBits();
7635 int NumElements = VT.getVectorNumElements();
7636 int NumEltsPerLane = 128 / EltBits;
7637 int OffsetLane = Offset / NumEltsPerLane;
7638 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7639 "Only 8, 16, and 32 bit elements can be extended.");
7640 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7641 assert(0 <= Offset && "Extension offset must be positive.");
7642 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7643 "Extension offset must be in the first lane or start an upper lane.");
7645 // Check that an index is in same lane as the base offset.
7646 auto SafeOffset = [&](int Idx) {
7647 return OffsetLane == (Idx / NumEltsPerLane);
7650 // Shift along an input so that the offset base moves to the first element.
7651 auto ShuffleOffset = [&](SDValue V) {
7655 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7656 for (int i = 0; i * Scale < NumElements; ++i) {
7657 int SrcIdx = i + Offset;
7658 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7660 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7663 // Found a valid zext mask! Try various lowering strategies based on the
7664 // input type and available ISA extensions.
7665 if (Subtarget->hasSSE41()) {
7666 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7667 // PUNPCK will catch this in a later shuffle match.
7668 if (Offset && Scale == 2 && VT.is128BitVector())
7670 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7671 NumElements / Scale);
7672 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7673 return DAG.getBitcast(VT, InputV);
7676 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7678 // For any extends we can cheat for larger element sizes and use shuffle
7679 // instructions that can fold with a load and/or copy.
7680 if (AnyExt && EltBits == 32) {
7681 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7683 return DAG.getBitcast(
7684 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7685 DAG.getBitcast(MVT::v4i32, InputV),
7686 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7688 if (AnyExt && EltBits == 16 && Scale > 2) {
7689 int PSHUFDMask[4] = {Offset / 2, -1,
7690 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7691 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7692 DAG.getBitcast(MVT::v4i32, InputV),
7693 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7694 int PSHUFWMask[4] = {1, -1, -1, -1};
7695 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7696 return DAG.getBitcast(
7697 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7698 DAG.getBitcast(MVT::v8i16, InputV),
7699 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7702 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7704 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7705 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7706 assert(VT.is128BitVector() && "Unexpected vector width!");
7708 int LoIdx = Offset * EltBits;
7709 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7710 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7711 DAG.getConstant(EltBits, DL, MVT::i8),
7712 DAG.getConstant(LoIdx, DL, MVT::i8)));
7714 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7715 !SafeOffset(Offset + 1))
7716 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7718 int HiIdx = (Offset + 1) * EltBits;
7719 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7720 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7721 DAG.getConstant(EltBits, DL, MVT::i8),
7722 DAG.getConstant(HiIdx, DL, MVT::i8)));
7723 return DAG.getNode(ISD::BITCAST, DL, VT,
7724 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7727 // If this would require more than 2 unpack instructions to expand, use
7728 // pshufb when available. We can only use more than 2 unpack instructions
7729 // when zero extending i8 elements which also makes it easier to use pshufb.
7730 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7731 assert(NumElements == 16 && "Unexpected byte vector width!");
7732 SDValue PSHUFBMask[16];
7733 for (int i = 0; i < 16; ++i) {
7734 int Idx = Offset + (i / Scale);
7735 PSHUFBMask[i] = DAG.getConstant(
7736 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7738 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7739 return DAG.getBitcast(VT,
7740 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7741 DAG.getNode(ISD::BUILD_VECTOR, DL,
7742 MVT::v16i8, PSHUFBMask)));
7745 // If we are extending from an offset, ensure we start on a boundary that
7746 // we can unpack from.
7747 int AlignToUnpack = Offset % (NumElements / Scale);
7748 if (AlignToUnpack) {
7749 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7750 for (int i = AlignToUnpack; i < NumElements; ++i)
7751 ShMask[i - AlignToUnpack] = i;
7752 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7753 Offset -= AlignToUnpack;
7756 // Otherwise emit a sequence of unpacks.
7758 unsigned UnpackLoHi = X86ISD::UNPCKL;
7759 if (Offset >= (NumElements / 2)) {
7760 UnpackLoHi = X86ISD::UNPCKH;
7761 Offset -= (NumElements / 2);
7764 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7765 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7766 : getZeroVector(InputVT, Subtarget, DAG, DL);
7767 InputV = DAG.getBitcast(InputVT, InputV);
7768 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7772 } while (Scale > 1);
7773 return DAG.getBitcast(VT, InputV);
7776 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7778 /// This routine will try to do everything in its power to cleverly lower
7779 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7780 /// check for the profitability of this lowering, it tries to aggressively
7781 /// match this pattern. It will use all of the micro-architectural details it
7782 /// can to emit an efficient lowering. It handles both blends with all-zero
7783 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7784 /// masking out later).
7786 /// The reason we have dedicated lowering for zext-style shuffles is that they
7787 /// are both incredibly common and often quite performance sensitive.
7788 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7789 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7790 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7791 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7793 int Bits = VT.getSizeInBits();
7794 int NumLanes = Bits / 128;
7795 int NumElements = VT.getVectorNumElements();
7796 int NumEltsPerLane = NumElements / NumLanes;
7797 assert(VT.getScalarSizeInBits() <= 32 &&
7798 "Exceeds 32-bit integer zero extension limit");
7799 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7801 // Define a helper function to check a particular ext-scale and lower to it if
7803 auto Lower = [&](int Scale) -> SDValue {
7808 for (int i = 0; i < NumElements; ++i) {
7811 continue; // Valid anywhere but doesn't tell us anything.
7812 if (i % Scale != 0) {
7813 // Each of the extended elements need to be zeroable.
7817 // We no longer are in the anyext case.
7822 // Each of the base elements needs to be consecutive indices into the
7823 // same input vector.
7824 SDValue V = M < NumElements ? V1 : V2;
7825 M = M % NumElements;
7828 Offset = M - (i / Scale);
7829 } else if (InputV != V)
7830 return SDValue(); // Flip-flopping inputs.
7832 // Offset must start in the lowest 128-bit lane or at the start of an
7834 // FIXME: Is it ever worth allowing a negative base offset?
7835 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7836 (Offset % NumEltsPerLane) == 0))
7839 // If we are offsetting, all referenced entries must come from the same
7841 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7844 if ((M % NumElements) != (Offset + (i / Scale)))
7845 return SDValue(); // Non-consecutive strided elements.
7849 // If we fail to find an input, we have a zero-shuffle which should always
7850 // have already been handled.
7851 // FIXME: Maybe handle this here in case during blending we end up with one?
7855 // If we are offsetting, don't extend if we only match a single input, we
7856 // can always do better by using a basic PSHUF or PUNPCK.
7857 if (Offset != 0 && Matches < 2)
7860 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7861 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7864 // The widest scale possible for extending is to a 64-bit integer.
7865 assert(Bits % 64 == 0 &&
7866 "The number of bits in a vector must be divisible by 64 on x86!");
7867 int NumExtElements = Bits / 64;
7869 // Each iteration, try extending the elements half as much, but into twice as
7871 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7872 assert(NumElements % NumExtElements == 0 &&
7873 "The input vector size must be divisible by the extended size.");
7874 if (SDValue V = Lower(NumElements / NumExtElements))
7878 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7882 // Returns one of the source operands if the shuffle can be reduced to a
7883 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7884 auto CanZExtLowHalf = [&]() {
7885 for (int i = NumElements / 2; i != NumElements; ++i)
7888 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7890 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7895 if (SDValue V = CanZExtLowHalf()) {
7896 V = DAG.getBitcast(MVT::v2i64, V);
7897 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7898 return DAG.getBitcast(VT, V);
7901 // No viable ext lowering found.
7905 /// \brief Try to get a scalar value for a specific element of a vector.
7907 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7908 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7909 SelectionDAG &DAG) {
7910 MVT VT = V.getSimpleValueType();
7911 MVT EltVT = VT.getVectorElementType();
7912 while (V.getOpcode() == ISD::BITCAST)
7913 V = V.getOperand(0);
7914 // If the bitcasts shift the element size, we can't extract an equivalent
7916 MVT NewVT = V.getSimpleValueType();
7917 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7920 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7921 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7922 // Ensure the scalar operand is the same size as the destination.
7923 // FIXME: Add support for scalar truncation where possible.
7924 SDValue S = V.getOperand(Idx);
7925 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7926 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7932 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7934 /// This is particularly important because the set of instructions varies
7935 /// significantly based on whether the operand is a load or not.
7936 static bool isShuffleFoldableLoad(SDValue V) {
7937 while (V.getOpcode() == ISD::BITCAST)
7938 V = V.getOperand(0);
7940 return ISD::isNON_EXTLoad(V.getNode());
7943 /// \brief Try to lower insertion of a single element into a zero vector.
7945 /// This is a common pattern that we have especially efficient patterns to lower
7946 /// across all subtarget feature sets.
7947 static SDValue lowerVectorShuffleAsElementInsertion(
7948 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7949 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7950 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7952 MVT EltVT = VT.getVectorElementType();
7954 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7955 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7957 bool IsV1Zeroable = true;
7958 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7959 if (i != V2Index && !Zeroable[i]) {
7960 IsV1Zeroable = false;
7964 // Check for a single input from a SCALAR_TO_VECTOR node.
7965 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7966 // all the smarts here sunk into that routine. However, the current
7967 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7968 // vector shuffle lowering is dead.
7969 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7971 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7972 // We need to zext the scalar if it is smaller than an i32.
7973 V2S = DAG.getBitcast(EltVT, V2S);
7974 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7975 // Using zext to expand a narrow element won't work for non-zero
7980 // Zero-extend directly to i32.
7982 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7984 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7985 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7986 EltVT == MVT::i16) {
7987 // Either not inserting from the low element of the input or the input
7988 // element size is too small to use VZEXT_MOVL to clear the high bits.
7992 if (!IsV1Zeroable) {
7993 // If V1 can't be treated as a zero vector we have fewer options to lower
7994 // this. We can't support integer vectors or non-zero targets cheaply, and
7995 // the V1 elements can't be permuted in any way.
7996 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7997 if (!VT.isFloatingPoint() || V2Index != 0)
7999 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8000 V1Mask[V2Index] = -1;
8001 if (!isNoopShuffleMask(V1Mask))
8003 // This is essentially a special case blend operation, but if we have
8004 // general purpose blend operations, they are always faster. Bail and let
8005 // the rest of the lowering handle these as blends.
8006 if (Subtarget->hasSSE41())
8009 // Otherwise, use MOVSD or MOVSS.
8010 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8011 "Only two types of floating point element types to handle!");
8012 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8016 // This lowering only works for the low element with floating point vectors.
8017 if (VT.isFloatingPoint() && V2Index != 0)
8020 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8022 V2 = DAG.getBitcast(VT, V2);
8025 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8026 // the desired position. Otherwise it is more efficient to do a vector
8027 // shift left. We know that we can do a vector shift left because all
8028 // the inputs are zero.
8029 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8030 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8031 V2Shuffle[V2Index] = 0;
8032 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8034 V2 = DAG.getBitcast(MVT::v2i64, V2);
8036 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8037 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
8038 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
8039 DAG.getDataLayout(), VT)));
8040 V2 = DAG.getBitcast(VT, V2);
8046 /// \brief Try to lower broadcast of a single - truncated - integer element,
8047 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
8049 /// This assumes we have AVX2.
8050 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
8052 const X86Subtarget *Subtarget,
8053 SelectionDAG &DAG) {
8054 assert(Subtarget->hasAVX2() &&
8055 "We can only lower integer broadcasts with AVX2!");
8057 EVT EltVT = VT.getVectorElementType();
8058 EVT V0VT = V0.getValueType();
8060 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
8061 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
8063 EVT V0EltVT = V0VT.getVectorElementType();
8064 if (!V0EltVT.isInteger())
8067 const unsigned EltSize = EltVT.getSizeInBits();
8068 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8070 // This is only a truncation if the original element type is larger.
8071 if (V0EltSize <= EltSize)
8074 assert(((V0EltSize % EltSize) == 0) &&
8075 "Scalar type sizes must all be powers of 2 on x86!");
8077 const unsigned V0Opc = V0.getOpcode();
8078 const unsigned Scale = V0EltSize / EltSize;
8079 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8081 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8082 V0Opc != ISD::BUILD_VECTOR)
8085 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8087 // If we're extracting non-least-significant bits, shift so we can truncate.
8088 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8089 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8090 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8091 if (const int OffsetIdx = BroadcastIdx % Scale)
8092 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8093 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8095 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8096 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8099 /// \brief Try to lower broadcast of a single element.
8101 /// For convenience, this code also bundles all of the subtarget feature set
8102 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8103 /// a convenient way to factor it out.
8104 /// FIXME: This is very similar to LowerVectorBroadcast - can we merge them?
8105 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8107 const X86Subtarget *Subtarget,
8108 SelectionDAG &DAG) {
8109 if (!Subtarget->hasAVX())
8111 if (VT.isInteger() && !Subtarget->hasAVX2())
8114 // Check that the mask is a broadcast.
8115 int BroadcastIdx = -1;
8117 if (M >= 0 && BroadcastIdx == -1)
8119 else if (M >= 0 && M != BroadcastIdx)
8122 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8123 "a sorted mask where the broadcast "
8126 // Go up the chain of (vector) values to find a scalar load that we can
8127 // combine with the broadcast.
8129 switch (V.getOpcode()) {
8130 case ISD::CONCAT_VECTORS: {
8131 int OperandSize = Mask.size() / V.getNumOperands();
8132 V = V.getOperand(BroadcastIdx / OperandSize);
8133 BroadcastIdx %= OperandSize;
8137 case ISD::INSERT_SUBVECTOR: {
8138 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8139 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8143 int BeginIdx = (int)ConstantIdx->getZExtValue();
8145 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8146 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8147 BroadcastIdx -= BeginIdx;
8158 // Check if this is a broadcast of a scalar. We special case lowering
8159 // for scalars so that we can more effectively fold with loads.
8160 // First, look through bitcast: if the original value has a larger element
8161 // type than the shuffle, the broadcast element is in essence truncated.
8162 // Make that explicit to ease folding.
8163 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8164 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8165 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8166 return TruncBroadcast;
8168 // Also check the simpler case, where we can directly reuse the scalar.
8169 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8170 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8171 V = V.getOperand(BroadcastIdx);
8173 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8174 // Only AVX2 has register broadcasts.
8175 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8177 } else if (MayFoldLoad(V) && !cast<LoadSDNode>(V)->isVolatile()) {
8178 // If we are broadcasting a load that is only used by the shuffle
8179 // then we can reduce the vector load to the broadcasted scalar load.
8180 LoadSDNode *Ld = cast<LoadSDNode>(V);
8181 SDValue BaseAddr = Ld->getOperand(1);
8182 EVT AddrVT = BaseAddr.getValueType();
8183 EVT SVT = VT.getScalarType();
8184 unsigned Offset = BroadcastIdx * SVT.getStoreSize();
8185 SDValue NewAddr = DAG.getNode(
8186 ISD::ADD, DL, AddrVT, BaseAddr,
8187 DAG.getConstant(Offset, DL, AddrVT));
8188 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr,
8189 DAG.getMachineFunction().getMachineMemOperand(
8190 Ld->getMemOperand(), Offset, SVT.getStoreSize()));
8191 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8192 // We can't broadcast from a vector register without AVX2, and we can only
8193 // broadcast from the zero-element of a vector register.
8197 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8200 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8201 // INSERTPS when the V1 elements are already in the correct locations
8202 // because otherwise we can just always use two SHUFPS instructions which
8203 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8204 // perform INSERTPS if a single V1 element is out of place and all V2
8205 // elements are zeroable.
8206 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8208 SelectionDAG &DAG) {
8209 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8210 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8211 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8212 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8214 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8217 int V1DstIndex = -1;
8218 int V2DstIndex = -1;
8219 bool V1UsedInPlace = false;
8221 for (int i = 0; i < 4; ++i) {
8222 // Synthesize a zero mask from the zeroable elements (includes undefs).
8228 // Flag if we use any V1 inputs in place.
8230 V1UsedInPlace = true;
8234 // We can only insert a single non-zeroable element.
8235 if (V1DstIndex != -1 || V2DstIndex != -1)
8239 // V1 input out of place for insertion.
8242 // V2 input for insertion.
8247 // Don't bother if we have no (non-zeroable) element for insertion.
8248 if (V1DstIndex == -1 && V2DstIndex == -1)
8251 // Determine element insertion src/dst indices. The src index is from the
8252 // start of the inserted vector, not the start of the concatenated vector.
8253 unsigned V2SrcIndex = 0;
8254 if (V1DstIndex != -1) {
8255 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8256 // and don't use the original V2 at all.
8257 V2SrcIndex = Mask[V1DstIndex];
8258 V2DstIndex = V1DstIndex;
8261 V2SrcIndex = Mask[V2DstIndex] - 4;
8264 // If no V1 inputs are used in place, then the result is created only from
8265 // the zero mask and the V2 insertion - so remove V1 dependency.
8267 V1 = DAG.getUNDEF(MVT::v4f32);
8269 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8270 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8272 // Insert the V2 element into the desired position.
8274 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8275 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8278 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8279 /// UNPCK instruction.
8281 /// This specifically targets cases where we end up with alternating between
8282 /// the two inputs, and so can permute them into something that feeds a single
8283 /// UNPCK instruction. Note that this routine only targets integer vectors
8284 /// because for floating point vectors we have a generalized SHUFPS lowering
8285 /// strategy that handles everything that doesn't *exactly* match an unpack,
8286 /// making this clever lowering unnecessary.
8287 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8288 SDValue V1, SDValue V2,
8290 SelectionDAG &DAG) {
8291 assert(!VT.isFloatingPoint() &&
8292 "This routine only supports integer vectors.");
8293 assert(!isSingleInputShuffleMask(Mask) &&
8294 "This routine should only be used when blending two inputs.");
8295 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8297 int Size = Mask.size();
8299 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8300 return M >= 0 && M % Size < Size / 2;
8302 int NumHiInputs = std::count_if(
8303 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8305 bool UnpackLo = NumLoInputs >= NumHiInputs;
8307 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8308 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8309 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8311 for (int i = 0; i < Size; ++i) {
8315 // Each element of the unpack contains Scale elements from this mask.
8316 int UnpackIdx = i / Scale;
8318 // We only handle the case where V1 feeds the first slots of the unpack.
8319 // We rely on canonicalization to ensure this is the case.
8320 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8323 // Setup the mask for this input. The indexing is tricky as we have to
8324 // handle the unpack stride.
8325 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8326 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8330 // If we will have to shuffle both inputs to use the unpack, check whether
8331 // we can just unpack first and shuffle the result. If so, skip this unpack.
8332 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8333 !isNoopShuffleMask(V2Mask))
8336 // Shuffle the inputs into place.
8337 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8338 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8340 // Cast the inputs to the type we will use to unpack them.
8341 V1 = DAG.getBitcast(UnpackVT, V1);
8342 V2 = DAG.getBitcast(UnpackVT, V2);
8344 // Unpack the inputs and cast the result back to the desired type.
8345 return DAG.getBitcast(
8346 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8350 // We try each unpack from the largest to the smallest to try and find one
8351 // that fits this mask.
8352 int OrigNumElements = VT.getVectorNumElements();
8353 int OrigScalarSize = VT.getScalarSizeInBits();
8354 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8355 int Scale = ScalarSize / OrigScalarSize;
8356 int NumElements = OrigNumElements / Scale;
8357 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8358 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8362 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8364 if (NumLoInputs == 0 || NumHiInputs == 0) {
8365 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8366 "We have to have *some* inputs!");
8367 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8369 // FIXME: We could consider the total complexity of the permute of each
8370 // possible unpacking. Or at the least we should consider how many
8371 // half-crossings are created.
8372 // FIXME: We could consider commuting the unpacks.
8374 SmallVector<int, 32> PermMask;
8375 PermMask.assign(Size, -1);
8376 for (int i = 0; i < Size; ++i) {
8380 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8383 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8385 return DAG.getVectorShuffle(
8386 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8388 DAG.getUNDEF(VT), PermMask);
8394 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8396 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8397 /// support for floating point shuffles but not integer shuffles. These
8398 /// instructions will incur a domain crossing penalty on some chips though so
8399 /// it is better to avoid lowering through this for integer vectors where
8401 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8402 const X86Subtarget *Subtarget,
8403 SelectionDAG &DAG) {
8405 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8406 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8407 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8408 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8409 ArrayRef<int> Mask = SVOp->getMask();
8410 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8412 if (isSingleInputShuffleMask(Mask)) {
8413 // Use low duplicate instructions for masks that match their pattern.
8414 if (Subtarget->hasSSE3())
8415 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8416 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8418 // Straight shuffle of a single input vector. Simulate this by using the
8419 // single input as both of the "inputs" to this instruction..
8420 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8422 if (Subtarget->hasAVX()) {
8423 // If we have AVX, we can use VPERMILPS which will allow folding a load
8424 // into the shuffle.
8425 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8426 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8429 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8430 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8432 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8433 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8435 // If we have a single input, insert that into V1 if we can do so cheaply.
8436 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8437 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8438 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8440 // Try inverting the insertion since for v2 masks it is easy to do and we
8441 // can't reliably sort the mask one way or the other.
8442 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8443 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8444 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8445 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8449 // Try to use one of the special instruction patterns to handle two common
8450 // blend patterns if a zero-blend above didn't work.
8451 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8452 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8453 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8454 // We can either use a special instruction to load over the low double or
8455 // to move just the low double.
8457 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8459 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8461 if (Subtarget->hasSSE41())
8462 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8466 // Use dedicated unpack instructions for masks that match their pattern.
8468 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8471 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8472 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8473 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8476 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8478 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8479 /// the integer unit to minimize domain crossing penalties. However, for blends
8480 /// it falls back to the floating point shuffle operation with appropriate bit
8482 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8483 const X86Subtarget *Subtarget,
8484 SelectionDAG &DAG) {
8486 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8487 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8488 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8489 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8490 ArrayRef<int> Mask = SVOp->getMask();
8491 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8493 if (isSingleInputShuffleMask(Mask)) {
8494 // Check for being able to broadcast a single element.
8495 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8496 Mask, Subtarget, DAG))
8499 // Straight shuffle of a single input vector. For everything from SSE2
8500 // onward this has a single fast instruction with no scary immediates.
8501 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8502 V1 = DAG.getBitcast(MVT::v4i32, V1);
8503 int WidenedMask[4] = {
8504 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8505 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8506 return DAG.getBitcast(
8508 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8509 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8511 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8512 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8513 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8514 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8516 // If we have a blend of two PACKUS operations an the blend aligns with the
8517 // low and half halves, we can just merge the PACKUS operations. This is
8518 // particularly important as it lets us merge shuffles that this routine itself
8520 auto GetPackNode = [](SDValue V) {
8521 while (V.getOpcode() == ISD::BITCAST)
8522 V = V.getOperand(0);
8524 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8526 if (SDValue V1Pack = GetPackNode(V1))
8527 if (SDValue V2Pack = GetPackNode(V2))
8528 return DAG.getBitcast(MVT::v2i64,
8529 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8530 Mask[0] == 0 ? V1Pack.getOperand(0)
8531 : V1Pack.getOperand(1),
8532 Mask[1] == 2 ? V2Pack.getOperand(0)
8533 : V2Pack.getOperand(1)));
8535 // Try to use shift instructions.
8537 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8540 // When loading a scalar and then shuffling it into a vector we can often do
8541 // the insertion cheaply.
8542 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8543 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8545 // Try inverting the insertion since for v2 masks it is easy to do and we
8546 // can't reliably sort the mask one way or the other.
8547 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8548 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8549 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8552 // We have different paths for blend lowering, but they all must use the
8553 // *exact* same predicate.
8554 bool IsBlendSupported = Subtarget->hasSSE41();
8555 if (IsBlendSupported)
8556 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8560 // Use dedicated unpack instructions for masks that match their pattern.
8562 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8565 // Try to use byte rotation instructions.
8566 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8567 if (Subtarget->hasSSSE3())
8568 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8569 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8572 // If we have direct support for blends, we should lower by decomposing into
8573 // a permute. That will be faster than the domain cross.
8574 if (IsBlendSupported)
8575 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8578 // We implement this with SHUFPD which is pretty lame because it will likely
8579 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8580 // However, all the alternatives are still more cycles and newer chips don't
8581 // have this problem. It would be really nice if x86 had better shuffles here.
8582 V1 = DAG.getBitcast(MVT::v2f64, V1);
8583 V2 = DAG.getBitcast(MVT::v2f64, V2);
8584 return DAG.getBitcast(MVT::v2i64,
8585 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8588 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8590 /// This is used to disable more specialized lowerings when the shufps lowering
8591 /// will happen to be efficient.
8592 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8593 // This routine only handles 128-bit shufps.
8594 assert(Mask.size() == 4 && "Unsupported mask size!");
8596 // To lower with a single SHUFPS we need to have the low half and high half
8597 // each requiring a single input.
8598 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8600 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8606 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8608 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8609 /// It makes no assumptions about whether this is the *best* lowering, it simply
8611 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8612 ArrayRef<int> Mask, SDValue V1,
8613 SDValue V2, SelectionDAG &DAG) {
8614 SDValue LowV = V1, HighV = V2;
8615 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8618 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8620 if (NumV2Elements == 1) {
8622 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8625 // Compute the index adjacent to V2Index and in the same half by toggling
8627 int V2AdjIndex = V2Index ^ 1;
8629 if (Mask[V2AdjIndex] == -1) {
8630 // Handles all the cases where we have a single V2 element and an undef.
8631 // This will only ever happen in the high lanes because we commute the
8632 // vector otherwise.
8634 std::swap(LowV, HighV);
8635 NewMask[V2Index] -= 4;
8637 // Handle the case where the V2 element ends up adjacent to a V1 element.
8638 // To make this work, blend them together as the first step.
8639 int V1Index = V2AdjIndex;
8640 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8641 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8642 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8644 // Now proceed to reconstruct the final blend as we have the necessary
8645 // high or low half formed.
8652 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8653 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8655 } else if (NumV2Elements == 2) {
8656 if (Mask[0] < 4 && Mask[1] < 4) {
8657 // Handle the easy case where we have V1 in the low lanes and V2 in the
8661 } else if (Mask[2] < 4 && Mask[3] < 4) {
8662 // We also handle the reversed case because this utility may get called
8663 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8664 // arrange things in the right direction.
8670 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8671 // trying to place elements directly, just blend them and set up the final
8672 // shuffle to place them.
8674 // The first two blend mask elements are for V1, the second two are for
8676 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8677 Mask[2] < 4 ? Mask[2] : Mask[3],
8678 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8679 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8680 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8681 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8683 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8686 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8687 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8688 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8689 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8692 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8693 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8696 /// \brief Lower 4-lane 32-bit floating point shuffles.
8698 /// Uses instructions exclusively from the floating point unit to minimize
8699 /// domain crossing penalties, as these are sufficient to implement all v4f32
8701 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8702 const X86Subtarget *Subtarget,
8703 SelectionDAG &DAG) {
8705 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8706 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8707 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8708 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8709 ArrayRef<int> Mask = SVOp->getMask();
8710 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8713 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8715 if (NumV2Elements == 0) {
8716 // Check for being able to broadcast a single element.
8717 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8718 Mask, Subtarget, DAG))
8721 // Use even/odd duplicate instructions for masks that match their pattern.
8722 if (Subtarget->hasSSE3()) {
8723 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8724 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8725 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8726 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8729 if (Subtarget->hasAVX()) {
8730 // If we have AVX, we can use VPERMILPS which will allow folding a load
8731 // into the shuffle.
8732 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8733 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8736 // Otherwise, use a straight shuffle of a single input vector. We pass the
8737 // input vector to both operands to simulate this with a SHUFPS.
8738 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8739 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8742 // There are special ways we can lower some single-element blends. However, we
8743 // have custom ways we can lower more complex single-element blends below that
8744 // we defer to if both this and BLENDPS fail to match, so restrict this to
8745 // when the V2 input is targeting element 0 of the mask -- that is the fast
8747 if (NumV2Elements == 1 && Mask[0] >= 4)
8748 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8749 Mask, Subtarget, DAG))
8752 if (Subtarget->hasSSE41()) {
8753 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8757 // Use INSERTPS if we can complete the shuffle efficiently.
8758 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8761 if (!isSingleSHUFPSMask(Mask))
8762 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8763 DL, MVT::v4f32, V1, V2, Mask, DAG))
8767 // Use dedicated unpack instructions for masks that match their pattern.
8769 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8772 // Otherwise fall back to a SHUFPS lowering strategy.
8773 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8776 /// \brief Lower 4-lane i32 vector shuffles.
8778 /// We try to handle these with integer-domain shuffles where we can, but for
8779 /// blends we use the floating point domain blend instructions.
8780 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8781 const X86Subtarget *Subtarget,
8782 SelectionDAG &DAG) {
8784 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8785 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8786 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8787 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8788 ArrayRef<int> Mask = SVOp->getMask();
8789 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8791 // Whenever we can lower this as a zext, that instruction is strictly faster
8792 // than any alternative. It also allows us to fold memory operands into the
8793 // shuffle in many cases.
8794 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8795 Mask, Subtarget, DAG))
8799 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8801 if (NumV2Elements == 0) {
8802 // Check for being able to broadcast a single element.
8803 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8804 Mask, Subtarget, DAG))
8807 // Straight shuffle of a single input vector. For everything from SSE2
8808 // onward this has a single fast instruction with no scary immediates.
8809 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8810 // but we aren't actually going to use the UNPCK instruction because doing
8811 // so prevents folding a load into this instruction or making a copy.
8812 const int UnpackLoMask[] = {0, 0, 1, 1};
8813 const int UnpackHiMask[] = {2, 2, 3, 3};
8814 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8815 Mask = UnpackLoMask;
8816 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8817 Mask = UnpackHiMask;
8819 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8820 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8823 // Try to use shift instructions.
8825 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8828 // There are special ways we can lower some single-element blends.
8829 if (NumV2Elements == 1)
8830 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8831 Mask, Subtarget, DAG))
8834 // We have different paths for blend lowering, but they all must use the
8835 // *exact* same predicate.
8836 bool IsBlendSupported = Subtarget->hasSSE41();
8837 if (IsBlendSupported)
8838 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8842 if (SDValue Masked =
8843 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8846 // Use dedicated unpack instructions for masks that match their pattern.
8848 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8851 // Try to use byte rotation instructions.
8852 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8853 if (Subtarget->hasSSSE3())
8854 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8855 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8858 // If we have direct support for blends, we should lower by decomposing into
8859 // a permute. That will be faster than the domain cross.
8860 if (IsBlendSupported)
8861 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8864 // Try to lower by permuting the inputs into an unpack instruction.
8865 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8869 // We implement this with SHUFPS because it can blend from two vectors.
8870 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8871 // up the inputs, bypassing domain shift penalties that we would encur if we
8872 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8874 return DAG.getBitcast(
8876 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8877 DAG.getBitcast(MVT::v4f32, V2), Mask));
8880 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8881 /// shuffle lowering, and the most complex part.
8883 /// The lowering strategy is to try to form pairs of input lanes which are
8884 /// targeted at the same half of the final vector, and then use a dword shuffle
8885 /// to place them onto the right half, and finally unpack the paired lanes into
8886 /// their final position.
8888 /// The exact breakdown of how to form these dword pairs and align them on the
8889 /// correct sides is really tricky. See the comments within the function for
8890 /// more of the details.
8892 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8893 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8894 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8895 /// vector, form the analogous 128-bit 8-element Mask.
8896 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8897 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8898 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8899 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8900 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8902 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8903 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8904 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8906 SmallVector<int, 4> LoInputs;
8907 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8908 [](int M) { return M >= 0; });
8909 std::sort(LoInputs.begin(), LoInputs.end());
8910 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8911 SmallVector<int, 4> HiInputs;
8912 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8913 [](int M) { return M >= 0; });
8914 std::sort(HiInputs.begin(), HiInputs.end());
8915 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8917 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8918 int NumHToL = LoInputs.size() - NumLToL;
8920 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8921 int NumHToH = HiInputs.size() - NumLToH;
8922 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8923 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8924 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8925 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8927 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8928 // such inputs we can swap two of the dwords across the half mark and end up
8929 // with <=2 inputs to each half in each half. Once there, we can fall through
8930 // to the generic code below. For example:
8932 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8933 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8935 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8936 // and an existing 2-into-2 on the other half. In this case we may have to
8937 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8938 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8939 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8940 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8941 // half than the one we target for fixing) will be fixed when we re-enter this
8942 // path. We will also combine away any sequence of PSHUFD instructions that
8943 // result into a single instruction. Here is an example of the tricky case:
8945 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8946 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8948 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8950 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8951 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8953 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8954 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8956 // The result is fine to be handled by the generic logic.
8957 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8958 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8959 int AOffset, int BOffset) {
8960 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8961 "Must call this with A having 3 or 1 inputs from the A half.");
8962 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8963 "Must call this with B having 1 or 3 inputs from the B half.");
8964 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8965 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8967 bool ThreeAInputs = AToAInputs.size() == 3;
8969 // Compute the index of dword with only one word among the three inputs in
8970 // a half by taking the sum of the half with three inputs and subtracting
8971 // the sum of the actual three inputs. The difference is the remaining
8974 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8975 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8976 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8977 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8978 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8979 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8980 int TripleNonInputIdx =
8981 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8982 TripleDWord = TripleNonInputIdx / 2;
8984 // We use xor with one to compute the adjacent DWord to whichever one the
8986 OneInputDWord = (OneInput / 2) ^ 1;
8988 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8989 // and BToA inputs. If there is also such a problem with the BToB and AToB
8990 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8991 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8992 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8993 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8994 // Compute how many inputs will be flipped by swapping these DWords. We
8996 // to balance this to ensure we don't form a 3-1 shuffle in the other
8998 int NumFlippedAToBInputs =
8999 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
9000 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
9001 int NumFlippedBToBInputs =
9002 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
9003 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
9004 if ((NumFlippedAToBInputs == 1 &&
9005 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
9006 (NumFlippedBToBInputs == 1 &&
9007 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
9008 // We choose whether to fix the A half or B half based on whether that
9009 // half has zero flipped inputs. At zero, we may not be able to fix it
9010 // with that half. We also bias towards fixing the B half because that
9011 // will more commonly be the high half, and we have to bias one way.
9012 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
9013 ArrayRef<int> Inputs) {
9014 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
9015 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
9016 PinnedIdx ^ 1) != Inputs.end();
9017 // Determine whether the free index is in the flipped dword or the
9018 // unflipped dword based on where the pinned index is. We use this bit
9019 // in an xor to conditionally select the adjacent dword.
9020 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
9021 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
9022 FixFreeIdx) != Inputs.end();
9023 if (IsFixIdxInput == IsFixFreeIdxInput)
9025 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
9026 FixFreeIdx) != Inputs.end();
9027 assert(IsFixIdxInput != IsFixFreeIdxInput &&
9028 "We need to be changing the number of flipped inputs!");
9029 int PSHUFHalfMask[] = {0, 1, 2, 3};
9030 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
9031 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
9033 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
9036 if (M != -1 && M == FixIdx)
9038 else if (M != -1 && M == FixFreeIdx)
9041 if (NumFlippedBToBInputs != 0) {
9043 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
9044 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
9046 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
9047 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
9048 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
9053 int PSHUFDMask[] = {0, 1, 2, 3};
9054 PSHUFDMask[ADWord] = BDWord;
9055 PSHUFDMask[BDWord] = ADWord;
9058 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9059 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9061 // Adjust the mask to match the new locations of A and B.
9063 if (M != -1 && M/2 == ADWord)
9064 M = 2 * BDWord + M % 2;
9065 else if (M != -1 && M/2 == BDWord)
9066 M = 2 * ADWord + M % 2;
9068 // Recurse back into this routine to re-compute state now that this isn't
9069 // a 3 and 1 problem.
9070 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
9073 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
9074 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
9075 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
9076 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
9078 // At this point there are at most two inputs to the low and high halves from
9079 // each half. That means the inputs can always be grouped into dwords and
9080 // those dwords can then be moved to the correct half with a dword shuffle.
9081 // We use at most one low and one high word shuffle to collect these paired
9082 // inputs into dwords, and finally a dword shuffle to place them.
9083 int PSHUFLMask[4] = {-1, -1, -1, -1};
9084 int PSHUFHMask[4] = {-1, -1, -1, -1};
9085 int PSHUFDMask[4] = {-1, -1, -1, -1};
9087 // First fix the masks for all the inputs that are staying in their
9088 // original halves. This will then dictate the targets of the cross-half
9090 auto fixInPlaceInputs =
9091 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9092 MutableArrayRef<int> SourceHalfMask,
9093 MutableArrayRef<int> HalfMask, int HalfOffset) {
9094 if (InPlaceInputs.empty())
9096 if (InPlaceInputs.size() == 1) {
9097 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9098 InPlaceInputs[0] - HalfOffset;
9099 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9102 if (IncomingInputs.empty()) {
9103 // Just fix all of the in place inputs.
9104 for (int Input : InPlaceInputs) {
9105 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9106 PSHUFDMask[Input / 2] = Input / 2;
9111 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9112 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9113 InPlaceInputs[0] - HalfOffset;
9114 // Put the second input next to the first so that they are packed into
9115 // a dword. We find the adjacent index by toggling the low bit.
9116 int AdjIndex = InPlaceInputs[0] ^ 1;
9117 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9118 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9119 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9121 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9122 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9124 // Now gather the cross-half inputs and place them into a free dword of
9125 // their target half.
9126 // FIXME: This operation could almost certainly be simplified dramatically to
9127 // look more like the 3-1 fixing operation.
9128 auto moveInputsToRightHalf = [&PSHUFDMask](
9129 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9130 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9131 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9133 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9134 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9136 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9138 int LowWord = Word & ~1;
9139 int HighWord = Word | 1;
9140 return isWordClobbered(SourceHalfMask, LowWord) ||
9141 isWordClobbered(SourceHalfMask, HighWord);
9144 if (IncomingInputs.empty())
9147 if (ExistingInputs.empty()) {
9148 // Map any dwords with inputs from them into the right half.
9149 for (int Input : IncomingInputs) {
9150 // If the source half mask maps over the inputs, turn those into
9151 // swaps and use the swapped lane.
9152 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9153 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9154 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9155 Input - SourceOffset;
9156 // We have to swap the uses in our half mask in one sweep.
9157 for (int &M : HalfMask)
9158 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9160 else if (M == Input)
9161 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9163 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9164 Input - SourceOffset &&
9165 "Previous placement doesn't match!");
9167 // Note that this correctly re-maps both when we do a swap and when
9168 // we observe the other side of the swap above. We rely on that to
9169 // avoid swapping the members of the input list directly.
9170 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9173 // Map the input's dword into the correct half.
9174 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9175 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9177 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9179 "Previous placement doesn't match!");
9182 // And just directly shift any other-half mask elements to be same-half
9183 // as we will have mirrored the dword containing the element into the
9184 // same position within that half.
9185 for (int &M : HalfMask)
9186 if (M >= SourceOffset && M < SourceOffset + 4) {
9187 M = M - SourceOffset + DestOffset;
9188 assert(M >= 0 && "This should never wrap below zero!");
9193 // Ensure we have the input in a viable dword of its current half. This
9194 // is particularly tricky because the original position may be clobbered
9195 // by inputs being moved and *staying* in that half.
9196 if (IncomingInputs.size() == 1) {
9197 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9198 int InputFixed = std::find(std::begin(SourceHalfMask),
9199 std::end(SourceHalfMask), -1) -
9200 std::begin(SourceHalfMask) + SourceOffset;
9201 SourceHalfMask[InputFixed - SourceOffset] =
9202 IncomingInputs[0] - SourceOffset;
9203 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9205 IncomingInputs[0] = InputFixed;
9207 } else if (IncomingInputs.size() == 2) {
9208 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9209 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9210 // We have two non-adjacent or clobbered inputs we need to extract from
9211 // the source half. To do this, we need to map them into some adjacent
9212 // dword slot in the source mask.
9213 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9214 IncomingInputs[1] - SourceOffset};
9216 // If there is a free slot in the source half mask adjacent to one of
9217 // the inputs, place the other input in it. We use (Index XOR 1) to
9218 // compute an adjacent index.
9219 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9220 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9221 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9222 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9223 InputsFixed[1] = InputsFixed[0] ^ 1;
9224 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9225 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9226 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9227 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9228 InputsFixed[0] = InputsFixed[1] ^ 1;
9229 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9230 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9231 // The two inputs are in the same DWord but it is clobbered and the
9232 // adjacent DWord isn't used at all. Move both inputs to the free
9234 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9235 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9236 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9237 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9239 // The only way we hit this point is if there is no clobbering
9240 // (because there are no off-half inputs to this half) and there is no
9241 // free slot adjacent to one of the inputs. In this case, we have to
9242 // swap an input with a non-input.
9243 for (int i = 0; i < 4; ++i)
9244 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9245 "We can't handle any clobbers here!");
9246 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9247 "Cannot have adjacent inputs here!");
9249 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9250 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9252 // We also have to update the final source mask in this case because
9253 // it may need to undo the above swap.
9254 for (int &M : FinalSourceHalfMask)
9255 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9256 M = InputsFixed[1] + SourceOffset;
9257 else if (M == InputsFixed[1] + SourceOffset)
9258 M = (InputsFixed[0] ^ 1) + SourceOffset;
9260 InputsFixed[1] = InputsFixed[0] ^ 1;
9263 // Point everything at the fixed inputs.
9264 for (int &M : HalfMask)
9265 if (M == IncomingInputs[0])
9266 M = InputsFixed[0] + SourceOffset;
9267 else if (M == IncomingInputs[1])
9268 M = InputsFixed[1] + SourceOffset;
9270 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9271 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9274 llvm_unreachable("Unhandled input size!");
9277 // Now hoist the DWord down to the right half.
9278 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9279 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9280 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9281 for (int &M : HalfMask)
9282 for (int Input : IncomingInputs)
9284 M = FreeDWord * 2 + Input % 2;
9286 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9287 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9288 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9289 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9291 // Now enact all the shuffles we've computed to move the inputs into their
9293 if (!isNoopShuffleMask(PSHUFLMask))
9294 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9295 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9296 if (!isNoopShuffleMask(PSHUFHMask))
9297 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9298 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9299 if (!isNoopShuffleMask(PSHUFDMask))
9302 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9303 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9305 // At this point, each half should contain all its inputs, and we can then
9306 // just shuffle them into their final position.
9307 assert(std::count_if(LoMask.begin(), LoMask.end(),
9308 [](int M) { return M >= 4; }) == 0 &&
9309 "Failed to lift all the high half inputs to the low mask!");
9310 assert(std::count_if(HiMask.begin(), HiMask.end(),
9311 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9312 "Failed to lift all the low half inputs to the high mask!");
9314 // Do a half shuffle for the low mask.
9315 if (!isNoopShuffleMask(LoMask))
9316 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9317 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9319 // Do a half shuffle with the high mask after shifting its values down.
9320 for (int &M : HiMask)
9323 if (!isNoopShuffleMask(HiMask))
9324 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9325 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9330 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9331 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9332 SDValue V2, ArrayRef<int> Mask,
9333 SelectionDAG &DAG, bool &V1InUse,
9335 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9341 int Size = Mask.size();
9342 int Scale = 16 / Size;
9343 for (int i = 0; i < 16; ++i) {
9344 if (Mask[i / Scale] == -1) {
9345 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9347 const int ZeroMask = 0x80;
9348 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9350 int V2Idx = Mask[i / Scale] < Size
9352 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9353 if (Zeroable[i / Scale])
9354 V1Idx = V2Idx = ZeroMask;
9355 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9356 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9357 V1InUse |= (ZeroMask != V1Idx);
9358 V2InUse |= (ZeroMask != V2Idx);
9363 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9364 DAG.getBitcast(MVT::v16i8, V1),
9365 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9367 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9368 DAG.getBitcast(MVT::v16i8, V2),
9369 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9371 // If we need shuffled inputs from both, blend the two.
9373 if (V1InUse && V2InUse)
9374 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9376 V = V1InUse ? V1 : V2;
9378 // Cast the result back to the correct type.
9379 return DAG.getBitcast(VT, V);
9382 /// \brief Generic lowering of 8-lane i16 shuffles.
9384 /// This handles both single-input shuffles and combined shuffle/blends with
9385 /// two inputs. The single input shuffles are immediately delegated to
9386 /// a dedicated lowering routine.
9388 /// The blends are lowered in one of three fundamental ways. If there are few
9389 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9390 /// of the input is significantly cheaper when lowered as an interleaving of
9391 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9392 /// halves of the inputs separately (making them have relatively few inputs)
9393 /// and then concatenate them.
9394 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9395 const X86Subtarget *Subtarget,
9396 SelectionDAG &DAG) {
9398 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9399 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9400 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9401 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9402 ArrayRef<int> OrigMask = SVOp->getMask();
9403 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9404 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9405 MutableArrayRef<int> Mask(MaskStorage);
9407 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9409 // Whenever we can lower this as a zext, that instruction is strictly faster
9410 // than any alternative.
9411 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9412 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9415 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9417 auto isV2 = [](int M) { return M >= 8; };
9419 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9421 if (NumV2Inputs == 0) {
9422 // Check for being able to broadcast a single element.
9423 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9424 Mask, Subtarget, DAG))
9427 // Try to use shift instructions.
9429 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9432 // Use dedicated unpack instructions for masks that match their pattern.
9434 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9437 // Try to use byte rotation instructions.
9438 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9439 Mask, Subtarget, DAG))
9442 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9446 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9447 "All single-input shuffles should be canonicalized to be V1-input "
9450 // Try to use shift instructions.
9452 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9455 // See if we can use SSE4A Extraction / Insertion.
9456 if (Subtarget->hasSSE4A())
9457 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9460 // There are special ways we can lower some single-element blends.
9461 if (NumV2Inputs == 1)
9462 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9463 Mask, Subtarget, DAG))
9466 // We have different paths for blend lowering, but they all must use the
9467 // *exact* same predicate.
9468 bool IsBlendSupported = Subtarget->hasSSE41();
9469 if (IsBlendSupported)
9470 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9474 if (SDValue Masked =
9475 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9478 // Use dedicated unpack instructions for masks that match their pattern.
9480 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9483 // Try to use byte rotation instructions.
9484 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9485 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9488 if (SDValue BitBlend =
9489 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9492 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9496 // If we can't directly blend but can use PSHUFB, that will be better as it
9497 // can both shuffle and set up the inefficient blend.
9498 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9499 bool V1InUse, V2InUse;
9500 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9504 // We can always bit-blend if we have to so the fallback strategy is to
9505 // decompose into single-input permutes and blends.
9506 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9510 /// \brief Check whether a compaction lowering can be done by dropping even
9511 /// elements and compute how many times even elements must be dropped.
9513 /// This handles shuffles which take every Nth element where N is a power of
9514 /// two. Example shuffle masks:
9516 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9517 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9518 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9519 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9520 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9521 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9523 /// Any of these lanes can of course be undef.
9525 /// This routine only supports N <= 3.
9526 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9529 /// \returns N above, or the number of times even elements must be dropped if
9530 /// there is such a number. Otherwise returns zero.
9531 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9532 // Figure out whether we're looping over two inputs or just one.
9533 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9535 // The modulus for the shuffle vector entries is based on whether this is
9536 // a single input or not.
9537 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9538 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9539 "We should only be called with masks with a power-of-2 size!");
9541 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9543 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9544 // and 2^3 simultaneously. This is because we may have ambiguity with
9545 // partially undef inputs.
9546 bool ViableForN[3] = {true, true, true};
9548 for (int i = 0, e = Mask.size(); i < e; ++i) {
9549 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9554 bool IsAnyViable = false;
9555 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9556 if (ViableForN[j]) {
9559 // The shuffle mask must be equal to (i * 2^N) % M.
9560 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9563 ViableForN[j] = false;
9565 // Early exit if we exhaust the possible powers of two.
9570 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9574 // Return 0 as there is no viable power of two.
9578 /// \brief Generic lowering of v16i8 shuffles.
9580 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9581 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9582 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9583 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9585 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9586 const X86Subtarget *Subtarget,
9587 SelectionDAG &DAG) {
9589 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9590 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9591 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9592 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9593 ArrayRef<int> Mask = SVOp->getMask();
9594 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9596 // Try to use shift instructions.
9598 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9601 // Try to use byte rotation instructions.
9602 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9603 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9606 // Try to use a zext lowering.
9607 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9608 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9611 // See if we can use SSE4A Extraction / Insertion.
9612 if (Subtarget->hasSSE4A())
9613 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9617 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9619 // For single-input shuffles, there are some nicer lowering tricks we can use.
9620 if (NumV2Elements == 0) {
9621 // Check for being able to broadcast a single element.
9622 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9623 Mask, Subtarget, DAG))
9626 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9627 // Notably, this handles splat and partial-splat shuffles more efficiently.
9628 // However, it only makes sense if the pre-duplication shuffle simplifies
9629 // things significantly. Currently, this means we need to be able to
9630 // express the pre-duplication shuffle as an i16 shuffle.
9632 // FIXME: We should check for other patterns which can be widened into an
9633 // i16 shuffle as well.
9634 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9635 for (int i = 0; i < 16; i += 2)
9636 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9641 auto tryToWidenViaDuplication = [&]() -> SDValue {
9642 if (!canWidenViaDuplication(Mask))
9644 SmallVector<int, 4> LoInputs;
9645 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9646 [](int M) { return M >= 0 && M < 8; });
9647 std::sort(LoInputs.begin(), LoInputs.end());
9648 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9650 SmallVector<int, 4> HiInputs;
9651 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9652 [](int M) { return M >= 8; });
9653 std::sort(HiInputs.begin(), HiInputs.end());
9654 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9657 bool TargetLo = LoInputs.size() >= HiInputs.size();
9658 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9659 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9661 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9662 SmallDenseMap<int, int, 8> LaneMap;
9663 for (int I : InPlaceInputs) {
9664 PreDupI16Shuffle[I/2] = I/2;
9667 int j = TargetLo ? 0 : 4, je = j + 4;
9668 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9669 // Check if j is already a shuffle of this input. This happens when
9670 // there are two adjacent bytes after we move the low one.
9671 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9672 // If we haven't yet mapped the input, search for a slot into which
9674 while (j < je && PreDupI16Shuffle[j] != -1)
9678 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9681 // Map this input with the i16 shuffle.
9682 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9685 // Update the lane map based on the mapping we ended up with.
9686 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9688 V1 = DAG.getBitcast(
9690 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9691 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9693 // Unpack the bytes to form the i16s that will be shuffled into place.
9694 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9695 MVT::v16i8, V1, V1);
9697 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9698 for (int i = 0; i < 16; ++i)
9699 if (Mask[i] != -1) {
9700 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9701 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9702 if (PostDupI16Shuffle[i / 2] == -1)
9703 PostDupI16Shuffle[i / 2] = MappedMask;
9705 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9706 "Conflicting entrties in the original shuffle!");
9708 return DAG.getBitcast(
9710 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9711 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9713 if (SDValue V = tryToWidenViaDuplication())
9717 if (SDValue Masked =
9718 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9721 // Use dedicated unpack instructions for masks that match their pattern.
9723 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9726 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9727 // with PSHUFB. It is important to do this before we attempt to generate any
9728 // blends but after all of the single-input lowerings. If the single input
9729 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9730 // want to preserve that and we can DAG combine any longer sequences into
9731 // a PSHUFB in the end. But once we start blending from multiple inputs,
9732 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9733 // and there are *very* few patterns that would actually be faster than the
9734 // PSHUFB approach because of its ability to zero lanes.
9736 // FIXME: The only exceptions to the above are blends which are exact
9737 // interleavings with direct instructions supporting them. We currently don't
9738 // handle those well here.
9739 if (Subtarget->hasSSSE3()) {
9740 bool V1InUse = false;
9741 bool V2InUse = false;
9743 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9744 DAG, V1InUse, V2InUse);
9746 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9747 // do so. This avoids using them to handle blends-with-zero which is
9748 // important as a single pshufb is significantly faster for that.
9749 if (V1InUse && V2InUse) {
9750 if (Subtarget->hasSSE41())
9751 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9752 Mask, Subtarget, DAG))
9755 // We can use an unpack to do the blending rather than an or in some
9756 // cases. Even though the or may be (very minorly) more efficient, we
9757 // preference this lowering because there are common cases where part of
9758 // the complexity of the shuffles goes away when we do the final blend as
9760 // FIXME: It might be worth trying to detect if the unpack-feeding
9761 // shuffles will both be pshufb, in which case we shouldn't bother with
9763 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9764 DL, MVT::v16i8, V1, V2, Mask, DAG))
9771 // There are special ways we can lower some single-element blends.
9772 if (NumV2Elements == 1)
9773 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9774 Mask, Subtarget, DAG))
9777 if (SDValue BitBlend =
9778 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9781 // Check whether a compaction lowering can be done. This handles shuffles
9782 // which take every Nth element for some even N. See the helper function for
9785 // We special case these as they can be particularly efficiently handled with
9786 // the PACKUSB instruction on x86 and they show up in common patterns of
9787 // rearranging bytes to truncate wide elements.
9788 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9789 // NumEvenDrops is the power of two stride of the elements. Another way of
9790 // thinking about it is that we need to drop the even elements this many
9791 // times to get the original input.
9792 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9794 // First we need to zero all the dropped bytes.
9795 assert(NumEvenDrops <= 3 &&
9796 "No support for dropping even elements more than 3 times.");
9797 // We use the mask type to pick which bytes are preserved based on how many
9798 // elements are dropped.
9799 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9800 SDValue ByteClearMask = DAG.getBitcast(
9801 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9802 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9804 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9806 // Now pack things back together.
9807 V1 = DAG.getBitcast(MVT::v8i16, V1);
9808 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9809 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9810 for (int i = 1; i < NumEvenDrops; ++i) {
9811 Result = DAG.getBitcast(MVT::v8i16, Result);
9812 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9818 // Handle multi-input cases by blending single-input shuffles.
9819 if (NumV2Elements > 0)
9820 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9823 // The fallback path for single-input shuffles widens this into two v8i16
9824 // vectors with unpacks, shuffles those, and then pulls them back together
9828 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9829 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9830 for (int i = 0; i < 16; ++i)
9832 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9834 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9836 SDValue VLoHalf, VHiHalf;
9837 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9838 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9840 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9841 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9842 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9843 [](int M) { return M >= 0 && M % 2 == 1; })) {
9844 // Use a mask to drop the high bytes.
9845 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9846 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9847 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9849 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9850 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9852 // Squash the masks to point directly into VLoHalf.
9853 for (int &M : LoBlendMask)
9856 for (int &M : HiBlendMask)
9860 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9861 // VHiHalf so that we can blend them as i16s.
9862 VLoHalf = DAG.getBitcast(
9863 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9864 VHiHalf = DAG.getBitcast(
9865 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9868 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9869 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9871 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9874 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9876 /// This routine breaks down the specific type of 128-bit shuffle and
9877 /// dispatches to the lowering routines accordingly.
9878 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9879 MVT VT, const X86Subtarget *Subtarget,
9880 SelectionDAG &DAG) {
9881 switch (VT.SimpleTy) {
9883 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9885 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9887 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9889 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9891 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9893 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9896 llvm_unreachable("Unimplemented!");
9900 /// \brief Helper function to test whether a shuffle mask could be
9901 /// simplified by widening the elements being shuffled.
9903 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9904 /// leaves it in an unspecified state.
9906 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9907 /// shuffle masks. The latter have the special property of a '-2' representing
9908 /// a zero-ed lane of a vector.
9909 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9910 SmallVectorImpl<int> &WidenedMask) {
9911 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9912 // If both elements are undef, its trivial.
9913 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9914 WidenedMask.push_back(SM_SentinelUndef);
9918 // Check for an undef mask and a mask value properly aligned to fit with
9919 // a pair of values. If we find such a case, use the non-undef mask's value.
9920 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9921 WidenedMask.push_back(Mask[i + 1] / 2);
9924 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9925 WidenedMask.push_back(Mask[i] / 2);
9929 // When zeroing, we need to spread the zeroing across both lanes to widen.
9930 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9931 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9932 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9933 WidenedMask.push_back(SM_SentinelZero);
9939 // Finally check if the two mask values are adjacent and aligned with
9941 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9942 WidenedMask.push_back(Mask[i] / 2);
9946 // Otherwise we can't safely widen the elements used in this shuffle.
9949 assert(WidenedMask.size() == Mask.size() / 2 &&
9950 "Incorrect size of mask after widening the elements!");
9955 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9957 /// This routine just extracts two subvectors, shuffles them independently, and
9958 /// then concatenates them back together. This should work effectively with all
9959 /// AVX vector shuffle types.
9960 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9961 SDValue V2, ArrayRef<int> Mask,
9962 SelectionDAG &DAG) {
9963 assert(VT.getSizeInBits() >= 256 &&
9964 "Only for 256-bit or wider vector shuffles!");
9965 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9966 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9968 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9969 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9971 int NumElements = VT.getVectorNumElements();
9972 int SplitNumElements = NumElements / 2;
9973 MVT ScalarVT = VT.getVectorElementType();
9974 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9976 // Rather than splitting build-vectors, just build two narrower build
9977 // vectors. This helps shuffling with splats and zeros.
9978 auto SplitVector = [&](SDValue V) {
9979 while (V.getOpcode() == ISD::BITCAST)
9980 V = V->getOperand(0);
9982 MVT OrigVT = V.getSimpleValueType();
9983 int OrigNumElements = OrigVT.getVectorNumElements();
9984 int OrigSplitNumElements = OrigNumElements / 2;
9985 MVT OrigScalarVT = OrigVT.getVectorElementType();
9986 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9990 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9992 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9993 DAG.getIntPtrConstant(0, DL));
9994 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9995 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9998 SmallVector<SDValue, 16> LoOps, HiOps;
9999 for (int i = 0; i < OrigSplitNumElements; ++i) {
10000 LoOps.push_back(BV->getOperand(i));
10001 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
10003 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
10004 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
10006 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
10007 DAG.getBitcast(SplitVT, HiV));
10010 SDValue LoV1, HiV1, LoV2, HiV2;
10011 std::tie(LoV1, HiV1) = SplitVector(V1);
10012 std::tie(LoV2, HiV2) = SplitVector(V2);
10014 // Now create two 4-way blends of these half-width vectors.
10015 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
10016 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
10017 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
10018 for (int i = 0; i < SplitNumElements; ++i) {
10019 int M = HalfMask[i];
10020 if (M >= NumElements) {
10021 if (M >= NumElements + SplitNumElements)
10025 V2BlendMask.push_back(M - NumElements);
10026 V1BlendMask.push_back(-1);
10027 BlendMask.push_back(SplitNumElements + i);
10028 } else if (M >= 0) {
10029 if (M >= SplitNumElements)
10033 V2BlendMask.push_back(-1);
10034 V1BlendMask.push_back(M);
10035 BlendMask.push_back(i);
10037 V2BlendMask.push_back(-1);
10038 V1BlendMask.push_back(-1);
10039 BlendMask.push_back(-1);
10043 // Because the lowering happens after all combining takes place, we need to
10044 // manually combine these blend masks as much as possible so that we create
10045 // a minimal number of high-level vector shuffle nodes.
10047 // First try just blending the halves of V1 or V2.
10048 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
10049 return DAG.getUNDEF(SplitVT);
10050 if (!UseLoV2 && !UseHiV2)
10051 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
10052 if (!UseLoV1 && !UseHiV1)
10053 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10055 SDValue V1Blend, V2Blend;
10056 if (UseLoV1 && UseHiV1) {
10058 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
10060 // We only use half of V1 so map the usage down into the final blend mask.
10061 V1Blend = UseLoV1 ? LoV1 : HiV1;
10062 for (int i = 0; i < SplitNumElements; ++i)
10063 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
10064 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
10066 if (UseLoV2 && UseHiV2) {
10068 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10070 // We only use half of V2 so map the usage down into the final blend mask.
10071 V2Blend = UseLoV2 ? LoV2 : HiV2;
10072 for (int i = 0; i < SplitNumElements; ++i)
10073 if (BlendMask[i] >= SplitNumElements)
10074 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
10076 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
10078 SDValue Lo = HalfBlend(LoMask);
10079 SDValue Hi = HalfBlend(HiMask);
10080 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
10083 /// \brief Either split a vector in halves or decompose the shuffles and the
10086 /// This is provided as a good fallback for many lowerings of non-single-input
10087 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10088 /// between splitting the shuffle into 128-bit components and stitching those
10089 /// back together vs. extracting the single-input shuffles and blending those
10091 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10092 SDValue V2, ArrayRef<int> Mask,
10093 SelectionDAG &DAG) {
10094 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10095 "lower single-input shuffles as it "
10096 "could then recurse on itself.");
10097 int Size = Mask.size();
10099 // If this can be modeled as a broadcast of two elements followed by a blend,
10100 // prefer that lowering. This is especially important because broadcasts can
10101 // often fold with memory operands.
10102 auto DoBothBroadcast = [&] {
10103 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10106 if (V2BroadcastIdx == -1)
10107 V2BroadcastIdx = M - Size;
10108 else if (M - Size != V2BroadcastIdx)
10110 } else if (M >= 0) {
10111 if (V1BroadcastIdx == -1)
10112 V1BroadcastIdx = M;
10113 else if (M != V1BroadcastIdx)
10118 if (DoBothBroadcast())
10119 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10122 // If the inputs all stem from a single 128-bit lane of each input, then we
10123 // split them rather than blending because the split will decompose to
10124 // unusually few instructions.
10125 int LaneCount = VT.getSizeInBits() / 128;
10126 int LaneSize = Size / LaneCount;
10127 SmallBitVector LaneInputs[2];
10128 LaneInputs[0].resize(LaneCount, false);
10129 LaneInputs[1].resize(LaneCount, false);
10130 for (int i = 0; i < Size; ++i)
10132 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10133 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10134 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10136 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10137 // that the decomposed single-input shuffles don't end up here.
10138 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10141 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10142 /// a permutation and blend of those lanes.
10144 /// This essentially blends the out-of-lane inputs to each lane into the lane
10145 /// from a permuted copy of the vector. This lowering strategy results in four
10146 /// instructions in the worst case for a single-input cross lane shuffle which
10147 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10148 /// of. Special cases for each particular shuffle pattern should be handled
10149 /// prior to trying this lowering.
10150 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10151 SDValue V1, SDValue V2,
10152 ArrayRef<int> Mask,
10153 SelectionDAG &DAG) {
10154 // FIXME: This should probably be generalized for 512-bit vectors as well.
10155 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10156 int LaneSize = Mask.size() / 2;
10158 // If there are only inputs from one 128-bit lane, splitting will in fact be
10159 // less expensive. The flags track whether the given lane contains an element
10160 // that crosses to another lane.
10161 bool LaneCrossing[2] = {false, false};
10162 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10163 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10164 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10165 if (!LaneCrossing[0] || !LaneCrossing[1])
10166 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10168 if (isSingleInputShuffleMask(Mask)) {
10169 SmallVector<int, 32> FlippedBlendMask;
10170 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10171 FlippedBlendMask.push_back(
10172 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10174 : Mask[i] % LaneSize +
10175 (i / LaneSize) * LaneSize + Size));
10177 // Flip the vector, and blend the results which should now be in-lane. The
10178 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10179 // 5 for the high source. The value 3 selects the high half of source 2 and
10180 // the value 2 selects the low half of source 2. We only use source 2 to
10181 // allow folding it into a memory operand.
10182 unsigned PERMMask = 3 | 2 << 4;
10183 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10184 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10185 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10188 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10189 // will be handled by the above logic and a blend of the results, much like
10190 // other patterns in AVX.
10191 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10194 /// \brief Handle lowering 2-lane 128-bit shuffles.
10195 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10196 SDValue V2, ArrayRef<int> Mask,
10197 const X86Subtarget *Subtarget,
10198 SelectionDAG &DAG) {
10199 // TODO: If minimizing size and one of the inputs is a zero vector and the
10200 // the zero vector has only one use, we could use a VPERM2X128 to save the
10201 // instruction bytes needed to explicitly generate the zero vector.
10203 // Blends are faster and handle all the non-lane-crossing cases.
10204 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10208 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10209 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10211 // If either input operand is a zero vector, use VPERM2X128 because its mask
10212 // allows us to replace the zero input with an implicit zero.
10213 if (!IsV1Zero && !IsV2Zero) {
10214 // Check for patterns which can be matched with a single insert of a 128-bit
10216 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10217 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10218 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10219 VT.getVectorNumElements() / 2);
10220 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10221 DAG.getIntPtrConstant(0, DL));
10222 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10223 OnlyUsesV1 ? V1 : V2,
10224 DAG.getIntPtrConstant(0, DL));
10225 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10229 // Otherwise form a 128-bit permutation. After accounting for undefs,
10230 // convert the 64-bit shuffle mask selection values into 128-bit
10231 // selection bits by dividing the indexes by 2 and shifting into positions
10232 // defined by a vperm2*128 instruction's immediate control byte.
10234 // The immediate permute control byte looks like this:
10235 // [1:0] - select 128 bits from sources for low half of destination
10237 // [3] - zero low half of destination
10238 // [5:4] - select 128 bits from sources for high half of destination
10240 // [7] - zero high half of destination
10242 int MaskLO = Mask[0];
10243 if (MaskLO == SM_SentinelUndef)
10244 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10246 int MaskHI = Mask[2];
10247 if (MaskHI == SM_SentinelUndef)
10248 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10250 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10252 // If either input is a zero vector, replace it with an undef input.
10253 // Shuffle mask values < 4 are selecting elements of V1.
10254 // Shuffle mask values >= 4 are selecting elements of V2.
10255 // Adjust each half of the permute mask by clearing the half that was
10256 // selecting the zero vector and setting the zero mask bit.
10258 V1 = DAG.getUNDEF(VT);
10260 PermMask = (PermMask & 0xf0) | 0x08;
10262 PermMask = (PermMask & 0x0f) | 0x80;
10265 V2 = DAG.getUNDEF(VT);
10267 PermMask = (PermMask & 0xf0) | 0x08;
10269 PermMask = (PermMask & 0x0f) | 0x80;
10272 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10273 DAG.getConstant(PermMask, DL, MVT::i8));
10276 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10277 /// shuffling each lane.
10279 /// This will only succeed when the result of fixing the 128-bit lanes results
10280 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10281 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10282 /// the lane crosses early and then use simpler shuffles within each lane.
10284 /// FIXME: It might be worthwhile at some point to support this without
10285 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10286 /// in x86 only floating point has interesting non-repeating shuffles, and even
10287 /// those are still *marginally* more expensive.
10288 static SDValue lowerVectorShuffleByMerging128BitLanes(
10289 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10290 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10291 assert(!isSingleInputShuffleMask(Mask) &&
10292 "This is only useful with multiple inputs.");
10294 int Size = Mask.size();
10295 int LaneSize = 128 / VT.getScalarSizeInBits();
10296 int NumLanes = Size / LaneSize;
10297 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10299 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10300 // check whether the in-128-bit lane shuffles share a repeating pattern.
10301 SmallVector<int, 4> Lanes;
10302 Lanes.resize(NumLanes, -1);
10303 SmallVector<int, 4> InLaneMask;
10304 InLaneMask.resize(LaneSize, -1);
10305 for (int i = 0; i < Size; ++i) {
10309 int j = i / LaneSize;
10311 if (Lanes[j] < 0) {
10312 // First entry we've seen for this lane.
10313 Lanes[j] = Mask[i] / LaneSize;
10314 } else if (Lanes[j] != Mask[i] / LaneSize) {
10315 // This doesn't match the lane selected previously!
10319 // Check that within each lane we have a consistent shuffle mask.
10320 int k = i % LaneSize;
10321 if (InLaneMask[k] < 0) {
10322 InLaneMask[k] = Mask[i] % LaneSize;
10323 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10324 // This doesn't fit a repeating in-lane mask.
10329 // First shuffle the lanes into place.
10330 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10331 VT.getSizeInBits() / 64);
10332 SmallVector<int, 8> LaneMask;
10333 LaneMask.resize(NumLanes * 2, -1);
10334 for (int i = 0; i < NumLanes; ++i)
10335 if (Lanes[i] >= 0) {
10336 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10337 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10340 V1 = DAG.getBitcast(LaneVT, V1);
10341 V2 = DAG.getBitcast(LaneVT, V2);
10342 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10344 // Cast it back to the type we actually want.
10345 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10347 // Now do a simple shuffle that isn't lane crossing.
10348 SmallVector<int, 8> NewMask;
10349 NewMask.resize(Size, -1);
10350 for (int i = 0; i < Size; ++i)
10352 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10353 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10354 "Must not introduce lane crosses at this point!");
10356 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10359 /// Lower shuffles where an entire half of a 256-bit vector is UNDEF.
10360 /// This allows for fast cases such as subvector extraction/insertion
10361 /// or shuffling smaller vector types which can lower more efficiently.
10362 static SDValue lowerVectorShuffleWithUndefHalf(SDLoc DL, MVT VT, SDValue V1,
10363 SDValue V2, ArrayRef<int> Mask,
10364 const X86Subtarget *Subtarget,
10365 SelectionDAG &DAG) {
10366 assert(VT.getSizeInBits() == 256 && "Expected 256-bit vector");
10368 unsigned NumElts = VT.getVectorNumElements();
10369 unsigned HalfNumElts = NumElts / 2;
10370 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(), HalfNumElts);
10372 bool UndefLower = isUndefInRange(Mask, 0, HalfNumElts);
10373 bool UndefUpper = isUndefInRange(Mask, HalfNumElts, HalfNumElts);
10374 if (!UndefLower && !UndefUpper)
10377 // Upper half is undef and lower half is whole upper subvector.
10378 // e.g. vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
10380 isSequentialOrUndefInRange(Mask, 0, HalfNumElts, HalfNumElts)) {
10381 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1,
10382 DAG.getIntPtrConstant(HalfNumElts, DL));
10383 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
10384 DAG.getIntPtrConstant(0, DL));
10387 // Lower half is undef and upper half is whole lower subvector.
10388 // e.g. vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
10390 isSequentialOrUndefInRange(Mask, HalfNumElts, HalfNumElts, 0)) {
10391 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1,
10392 DAG.getIntPtrConstant(0, DL));
10393 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
10394 DAG.getIntPtrConstant(HalfNumElts, DL));
10397 // AVX2 supports efficient immediate 64-bit element cross-lane shuffles.
10398 if (UndefLower && Subtarget->hasAVX2() &&
10399 (VT == MVT::v4f64 || VT == MVT::v4i64))
10402 // If the shuffle only uses the lower halves of the input operands,
10403 // then extract them and perform the 'half' shuffle at half width.
10404 // e.g. vector_shuffle <X, X, X, X, u, u, u, u> or <X, X, u, u>
10405 int HalfIdx1 = -1, HalfIdx2 = -1;
10406 SmallVector<int, 8> HalfMask;
10407 unsigned Offset = UndefLower ? HalfNumElts : 0;
10408 for (unsigned i = 0; i != HalfNumElts; ++i) {
10409 int M = Mask[i + Offset];
10411 HalfMask.push_back(M);
10415 // Determine which of the 4 half vectors this element is from.
10416 // i.e. 0 = Lower V1, 1 = Upper V1, 2 = Lower V2, 3 = Upper V2.
10417 int HalfIdx = M / HalfNumElts;
10419 // Only shuffle using the lower halves of the inputs.
10420 // TODO: Investigate usefulness of shuffling with upper halves.
10421 if (HalfIdx != 0 && HalfIdx != 2)
10424 // Determine the element index into its half vector source.
10425 int HalfElt = M % HalfNumElts;
10427 // We can shuffle with up to 2 half vectors, set the new 'half'
10428 // shuffle mask accordingly.
10429 if (-1 == HalfIdx1 || HalfIdx1 == HalfIdx) {
10430 HalfMask.push_back(HalfElt);
10431 HalfIdx1 = HalfIdx;
10434 if (-1 == HalfIdx2 || HalfIdx2 == HalfIdx) {
10435 HalfMask.push_back(HalfElt + HalfNumElts);
10436 HalfIdx2 = HalfIdx;
10440 // Too many half vectors referenced.
10443 assert(HalfMask.size() == HalfNumElts && "Unexpected shuffle mask length");
10445 auto GetHalfVector = [&](int HalfIdx) {
10447 return DAG.getUNDEF(HalfVT);
10448 SDValue V = (HalfIdx < 2 ? V1 : V2);
10449 HalfIdx = (HalfIdx % 2) * HalfNumElts;
10450 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V,
10451 DAG.getIntPtrConstant(HalfIdx, DL));
10454 SDValue Half1 = GetHalfVector(HalfIdx1);
10455 SDValue Half2 = GetHalfVector(HalfIdx2);
10456 SDValue V = DAG.getVectorShuffle(HalfVT, DL, Half1, Half2, HalfMask);
10457 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V,
10458 DAG.getIntPtrConstant(Offset, DL));
10461 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10464 /// This returns true if the elements from a particular input are already in the
10465 /// slot required by the given mask and require no permutation.
10466 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10467 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10468 int Size = Mask.size();
10469 for (int i = 0; i < Size; ++i)
10470 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10476 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10477 ArrayRef<int> Mask, SDValue V1,
10478 SDValue V2, SelectionDAG &DAG) {
10480 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10481 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10482 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10483 int NumElts = VT.getVectorNumElements();
10484 bool ShufpdMask = true;
10485 bool CommutableMask = true;
10486 unsigned Immediate = 0;
10487 for (int i = 0; i < NumElts; ++i) {
10490 int Val = (i & 6) + NumElts * (i & 1);
10491 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10492 if (Mask[i] < Val || Mask[i] > Val + 1)
10493 ShufpdMask = false;
10494 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10495 CommutableMask = false;
10496 Immediate |= (Mask[i] % 2) << i;
10499 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10500 DAG.getConstant(Immediate, DL, MVT::i8));
10501 if (CommutableMask)
10502 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10503 DAG.getConstant(Immediate, DL, MVT::i8));
10507 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10509 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10510 /// isn't available.
10511 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10512 const X86Subtarget *Subtarget,
10513 SelectionDAG &DAG) {
10515 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10516 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10517 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10518 ArrayRef<int> Mask = SVOp->getMask();
10519 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10521 SmallVector<int, 4> WidenedMask;
10522 if (canWidenShuffleElements(Mask, WidenedMask))
10523 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10526 if (isSingleInputShuffleMask(Mask)) {
10527 // Check for being able to broadcast a single element.
10528 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10529 Mask, Subtarget, DAG))
10532 // Use low duplicate instructions for masks that match their pattern.
10533 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10534 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10536 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10537 // Non-half-crossing single input shuffles can be lowerid with an
10538 // interleaved permutation.
10539 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10540 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10541 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10542 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10545 // With AVX2 we have direct support for this permutation.
10546 if (Subtarget->hasAVX2())
10547 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10548 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10550 // Otherwise, fall back.
10551 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10555 // Use dedicated unpack instructions for masks that match their pattern.
10557 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10560 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10564 // Check if the blend happens to exactly fit that of SHUFPD.
10566 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10569 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10570 // shuffle. However, if we have AVX2 and either inputs are already in place,
10571 // we will be able to shuffle even across lanes the other input in a single
10572 // instruction so skip this pattern.
10573 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10574 isShuffleMaskInputInPlace(1, Mask))))
10575 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10576 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10579 // If we have AVX2 then we always want to lower with a blend because an v4 we
10580 // can fully permute the elements.
10581 if (Subtarget->hasAVX2())
10582 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10585 // Otherwise fall back on generic lowering.
10586 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10589 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10591 /// This routine is only called when we have AVX2 and thus a reasonable
10592 /// instruction set for v4i64 shuffling..
10593 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10594 const X86Subtarget *Subtarget,
10595 SelectionDAG &DAG) {
10597 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10598 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10599 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10600 ArrayRef<int> Mask = SVOp->getMask();
10601 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10602 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10604 SmallVector<int, 4> WidenedMask;
10605 if (canWidenShuffleElements(Mask, WidenedMask))
10606 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10609 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10613 // Check for being able to broadcast a single element.
10614 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10615 Mask, Subtarget, DAG))
10618 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10619 // use lower latency instructions that will operate on both 128-bit lanes.
10620 SmallVector<int, 2> RepeatedMask;
10621 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10622 if (isSingleInputShuffleMask(Mask)) {
10623 int PSHUFDMask[] = {-1, -1, -1, -1};
10624 for (int i = 0; i < 2; ++i)
10625 if (RepeatedMask[i] >= 0) {
10626 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10627 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10629 return DAG.getBitcast(
10631 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10632 DAG.getBitcast(MVT::v8i32, V1),
10633 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10637 // AVX2 provides a direct instruction for permuting a single input across
10639 if (isSingleInputShuffleMask(Mask))
10640 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10641 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10643 // Try to use shift instructions.
10644 if (SDValue Shift =
10645 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10648 // Use dedicated unpack instructions for masks that match their pattern.
10650 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10653 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10654 // shuffle. However, if we have AVX2 and either inputs are already in place,
10655 // we will be able to shuffle even across lanes the other input in a single
10656 // instruction so skip this pattern.
10657 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10658 isShuffleMaskInputInPlace(1, Mask))))
10659 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10660 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10663 // Otherwise fall back on generic blend lowering.
10664 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10668 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10670 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10671 /// isn't available.
10672 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10673 const X86Subtarget *Subtarget,
10674 SelectionDAG &DAG) {
10676 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10677 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10678 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10679 ArrayRef<int> Mask = SVOp->getMask();
10680 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10682 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10686 // Check for being able to broadcast a single element.
10687 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10688 Mask, Subtarget, DAG))
10691 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10692 // options to efficiently lower the shuffle.
10693 SmallVector<int, 4> RepeatedMask;
10694 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10695 assert(RepeatedMask.size() == 4 &&
10696 "Repeated masks must be half the mask width!");
10698 // Use even/odd duplicate instructions for masks that match their pattern.
10699 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10700 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10701 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10702 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10704 if (isSingleInputShuffleMask(Mask))
10705 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10706 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10708 // Use dedicated unpack instructions for masks that match their pattern.
10710 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10713 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10714 // have already handled any direct blends. We also need to squash the
10715 // repeated mask into a simulated v4f32 mask.
10716 for (int i = 0; i < 4; ++i)
10717 if (RepeatedMask[i] >= 8)
10718 RepeatedMask[i] -= 4;
10719 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10722 // If we have a single input shuffle with different shuffle patterns in the
10723 // two 128-bit lanes use the variable mask to VPERMILPS.
10724 if (isSingleInputShuffleMask(Mask)) {
10725 SDValue VPermMask[8];
10726 for (int i = 0; i < 8; ++i)
10727 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10728 : DAG.getConstant(Mask[i], DL, MVT::i32);
10729 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10730 return DAG.getNode(
10731 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10732 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10734 if (Subtarget->hasAVX2())
10735 return DAG.getNode(
10736 X86ISD::VPERMV, DL, MVT::v8f32,
10737 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10739 // Otherwise, fall back.
10740 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10744 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10746 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10747 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10750 // If we have AVX2 then we always want to lower with a blend because at v8 we
10751 // can fully permute the elements.
10752 if (Subtarget->hasAVX2())
10753 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10756 // Otherwise fall back on generic lowering.
10757 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10760 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10762 /// This routine is only called when we have AVX2 and thus a reasonable
10763 /// instruction set for v8i32 shuffling..
10764 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10765 const X86Subtarget *Subtarget,
10766 SelectionDAG &DAG) {
10768 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10769 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10770 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10771 ArrayRef<int> Mask = SVOp->getMask();
10772 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10773 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10775 // Whenever we can lower this as a zext, that instruction is strictly faster
10776 // than any alternative. It also allows us to fold memory operands into the
10777 // shuffle in many cases.
10778 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10779 Mask, Subtarget, DAG))
10782 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10786 // Check for being able to broadcast a single element.
10787 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10788 Mask, Subtarget, DAG))
10791 // If the shuffle mask is repeated in each 128-bit lane we can use more
10792 // efficient instructions that mirror the shuffles across the two 128-bit
10794 SmallVector<int, 4> RepeatedMask;
10795 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10796 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10797 if (isSingleInputShuffleMask(Mask))
10798 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10799 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10801 // Use dedicated unpack instructions for masks that match their pattern.
10803 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10807 // Try to use shift instructions.
10808 if (SDValue Shift =
10809 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10812 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10813 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10816 // If the shuffle patterns aren't repeated but it is a single input, directly
10817 // generate a cross-lane VPERMD instruction.
10818 if (isSingleInputShuffleMask(Mask)) {
10819 SDValue VPermMask[8];
10820 for (int i = 0; i < 8; ++i)
10821 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10822 : DAG.getConstant(Mask[i], DL, MVT::i32);
10823 return DAG.getNode(
10824 X86ISD::VPERMV, DL, MVT::v8i32,
10825 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10828 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10830 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10831 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10834 // Otherwise fall back on generic blend lowering.
10835 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10839 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10841 /// This routine is only called when we have AVX2 and thus a reasonable
10842 /// instruction set for v16i16 shuffling..
10843 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10844 const X86Subtarget *Subtarget,
10845 SelectionDAG &DAG) {
10847 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10848 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10849 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10850 ArrayRef<int> Mask = SVOp->getMask();
10851 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10852 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10854 // Whenever we can lower this as a zext, that instruction is strictly faster
10855 // than any alternative. It also allows us to fold memory operands into the
10856 // shuffle in many cases.
10857 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10858 Mask, Subtarget, DAG))
10861 // Check for being able to broadcast a single element.
10862 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10863 Mask, Subtarget, DAG))
10866 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10870 // Use dedicated unpack instructions for masks that match their pattern.
10872 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10875 // Try to use shift instructions.
10876 if (SDValue Shift =
10877 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10880 // Try to use byte rotation instructions.
10881 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10882 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10885 if (isSingleInputShuffleMask(Mask)) {
10886 // There are no generalized cross-lane shuffle operations available on i16
10888 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10889 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10892 SmallVector<int, 8> RepeatedMask;
10893 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10894 // As this is a single-input shuffle, the repeated mask should be
10895 // a strictly valid v8i16 mask that we can pass through to the v8i16
10896 // lowering to handle even the v16 case.
10897 return lowerV8I16GeneralSingleInputVectorShuffle(
10898 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10901 SDValue PSHUFBMask[32];
10902 for (int i = 0; i < 16; ++i) {
10903 if (Mask[i] == -1) {
10904 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10908 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10909 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10910 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10911 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10913 return DAG.getBitcast(MVT::v16i16,
10914 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10915 DAG.getBitcast(MVT::v32i8, V1),
10916 DAG.getNode(ISD::BUILD_VECTOR, DL,
10917 MVT::v32i8, PSHUFBMask)));
10920 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10922 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10923 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10926 // Otherwise fall back on generic lowering.
10927 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10930 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10932 /// This routine is only called when we have AVX2 and thus a reasonable
10933 /// instruction set for v32i8 shuffling..
10934 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10935 const X86Subtarget *Subtarget,
10936 SelectionDAG &DAG) {
10938 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10939 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10940 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10941 ArrayRef<int> Mask = SVOp->getMask();
10942 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10943 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10945 // Whenever we can lower this as a zext, that instruction is strictly faster
10946 // than any alternative. It also allows us to fold memory operands into the
10947 // shuffle in many cases.
10948 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10949 Mask, Subtarget, DAG))
10952 // Check for being able to broadcast a single element.
10953 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10954 Mask, Subtarget, DAG))
10957 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10961 // Use dedicated unpack instructions for masks that match their pattern.
10963 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10966 // Try to use shift instructions.
10967 if (SDValue Shift =
10968 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10971 // Try to use byte rotation instructions.
10972 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10973 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10976 if (isSingleInputShuffleMask(Mask)) {
10977 // There are no generalized cross-lane shuffle operations available on i8
10979 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10980 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10983 SDValue PSHUFBMask[32];
10984 for (int i = 0; i < 32; ++i)
10987 ? DAG.getUNDEF(MVT::i8)
10988 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10991 return DAG.getNode(
10992 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10993 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10996 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10998 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10999 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
11002 // Otherwise fall back on generic lowering.
11003 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
11006 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
11008 /// This routine either breaks down the specific type of a 256-bit x86 vector
11009 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
11010 /// together based on the available instructions.
11011 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11012 MVT VT, const X86Subtarget *Subtarget,
11013 SelectionDAG &DAG) {
11015 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11016 ArrayRef<int> Mask = SVOp->getMask();
11018 // If we have a single input to the zero element, insert that into V1 if we
11019 // can do so cheaply.
11020 int NumElts = VT.getVectorNumElements();
11021 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
11022 return M >= NumElts;
11025 if (NumV2Elements == 1 && Mask[0] >= NumElts)
11026 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
11027 DL, VT, V1, V2, Mask, Subtarget, DAG))
11030 // Handle special cases where the lower or upper half is UNDEF.
11032 lowerVectorShuffleWithUndefHalf(DL, VT, V1, V2, Mask, Subtarget, DAG))
11035 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
11036 // can check for those subtargets here and avoid much of the subtarget
11037 // querying in the per-vector-type lowering routines. With AVX1 we have
11038 // essentially *zero* ability to manipulate a 256-bit vector with integer
11039 // types. Since we'll use floating point types there eventually, just
11040 // immediately cast everything to a float and operate entirely in that domain.
11041 if (VT.isInteger() && !Subtarget->hasAVX2()) {
11042 int ElementBits = VT.getScalarSizeInBits();
11043 if (ElementBits < 32)
11044 // No floating point type available, decompose into 128-bit vectors.
11045 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11047 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
11048 VT.getVectorNumElements());
11049 V1 = DAG.getBitcast(FpVT, V1);
11050 V2 = DAG.getBitcast(FpVT, V2);
11051 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
11054 switch (VT.SimpleTy) {
11056 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11058 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11060 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11062 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11064 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11066 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11069 llvm_unreachable("Not a valid 256-bit x86 vector type!");
11073 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
11074 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
11075 ArrayRef<int> Mask,
11076 SDValue V1, SDValue V2,
11077 SelectionDAG &DAG) {
11078 assert(VT.getScalarSizeInBits() == 64 &&
11079 "Unexpected element type size for 128bit shuffle.");
11081 // To handle 256 bit vector requires VLX and most probably
11082 // function lowerV2X128VectorShuffle() is better solution.
11083 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
11085 SmallVector<int, 4> WidenedMask;
11086 if (!canWidenShuffleElements(Mask, WidenedMask))
11089 // Form a 128-bit permutation.
11090 // Convert the 64-bit shuffle mask selection values into 128-bit selection
11091 // bits defined by a vshuf64x2 instruction's immediate control byte.
11092 unsigned PermMask = 0, Imm = 0;
11093 unsigned ControlBitsNum = WidenedMask.size() / 2;
11095 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
11096 if (WidenedMask[i] == SM_SentinelZero)
11099 // Use first element in place of undef mask.
11100 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
11101 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
11104 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
11105 DAG.getConstant(PermMask, DL, MVT::i8));
11108 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
11109 ArrayRef<int> Mask, SDValue V1,
11110 SDValue V2, SelectionDAG &DAG) {
11112 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
11114 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
11115 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
11117 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
11118 if (isSingleInputShuffleMask(Mask))
11119 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
11121 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
11124 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
11125 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11126 const X86Subtarget *Subtarget,
11127 SelectionDAG &DAG) {
11129 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11130 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11131 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11132 ArrayRef<int> Mask = SVOp->getMask();
11133 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11135 if (SDValue Shuf128 =
11136 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
11139 if (SDValue Unpck =
11140 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
11143 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
11146 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
11147 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11148 const X86Subtarget *Subtarget,
11149 SelectionDAG &DAG) {
11151 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11152 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11153 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11154 ArrayRef<int> Mask = SVOp->getMask();
11155 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11157 if (SDValue Unpck =
11158 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
11161 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
11164 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
11165 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11166 const X86Subtarget *Subtarget,
11167 SelectionDAG &DAG) {
11169 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11170 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11171 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11172 ArrayRef<int> Mask = SVOp->getMask();
11173 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11175 if (SDValue Shuf128 =
11176 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
11179 if (SDValue Unpck =
11180 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
11183 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
11186 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
11187 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11188 const X86Subtarget *Subtarget,
11189 SelectionDAG &DAG) {
11191 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11192 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11193 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11194 ArrayRef<int> Mask = SVOp->getMask();
11195 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11197 if (SDValue Unpck =
11198 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11201 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11204 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11205 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11206 const X86Subtarget *Subtarget,
11207 SelectionDAG &DAG) {
11209 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11210 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11211 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11212 ArrayRef<int> Mask = SVOp->getMask();
11213 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11214 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11216 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11219 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11220 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11221 const X86Subtarget *Subtarget,
11222 SelectionDAG &DAG) {
11224 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11225 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11226 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11227 ArrayRef<int> Mask = SVOp->getMask();
11228 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11229 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11231 // FIXME: Implement direct support for this type!
11232 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11235 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11237 /// This routine either breaks down the specific type of a 512-bit x86 vector
11238 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11239 /// together based on the available instructions.
11240 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11241 MVT VT, const X86Subtarget *Subtarget,
11242 SelectionDAG &DAG) {
11244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11245 ArrayRef<int> Mask = SVOp->getMask();
11246 assert(Subtarget->hasAVX512() &&
11247 "Cannot lower 512-bit vectors w/ basic ISA!");
11249 // Check for being able to broadcast a single element.
11250 if (SDValue Broadcast =
11251 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11254 // Dispatch to each element type for lowering. If we don't have supprot for
11255 // specific element type shuffles at 512 bits, immediately split them and
11256 // lower them. Each lowering routine of a given type is allowed to assume that
11257 // the requisite ISA extensions for that element type are available.
11258 switch (VT.SimpleTy) {
11260 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11262 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11264 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11266 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11268 if (Subtarget->hasBWI())
11269 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11272 if (Subtarget->hasBWI())
11273 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11277 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11280 // Otherwise fall back on splitting.
11281 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11284 // Lower vXi1 vector shuffles.
11285 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11286 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11287 // vector, shuffle and then truncate it back.
11288 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11289 MVT VT, const X86Subtarget *Subtarget,
11290 SelectionDAG &DAG) {
11292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11293 ArrayRef<int> Mask = SVOp->getMask();
11294 assert(Subtarget->hasAVX512() &&
11295 "Cannot lower 512-bit vectors w/o basic ISA!");
11297 switch (VT.SimpleTy) {
11299 llvm_unreachable("Expected a vector of i1 elements");
11301 ExtVT = MVT::v2i64;
11304 ExtVT = MVT::v4i32;
11307 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11310 ExtVT = MVT::v16i32;
11313 ExtVT = MVT::v32i16;
11316 ExtVT = MVT::v64i8;
11320 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11321 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11322 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11323 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11325 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11328 V2 = DAG.getUNDEF(ExtVT);
11329 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11330 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11331 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11332 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11334 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11335 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11336 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11338 /// \brief Top-level lowering for x86 vector shuffles.
11340 /// This handles decomposition, canonicalization, and lowering of all x86
11341 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11342 /// above in helper routines. The canonicalization attempts to widen shuffles
11343 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11344 /// s.t. only one of the two inputs needs to be tested, etc.
11345 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11346 SelectionDAG &DAG) {
11347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11348 ArrayRef<int> Mask = SVOp->getMask();
11349 SDValue V1 = Op.getOperand(0);
11350 SDValue V2 = Op.getOperand(1);
11351 MVT VT = Op.getSimpleValueType();
11352 int NumElements = VT.getVectorNumElements();
11354 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11356 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11357 "Can't lower MMX shuffles");
11359 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11360 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11361 if (V1IsUndef && V2IsUndef)
11362 return DAG.getUNDEF(VT);
11364 // When we create a shuffle node we put the UNDEF node to second operand,
11365 // but in some cases the first operand may be transformed to UNDEF.
11366 // In this case we should just commute the node.
11368 return DAG.getCommutedVectorShuffle(*SVOp);
11370 // Check for non-undef masks pointing at an undef vector and make the masks
11371 // undef as well. This makes it easier to match the shuffle based solely on
11375 if (M >= NumElements) {
11376 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11377 for (int &M : NewMask)
11378 if (M >= NumElements)
11380 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11383 // We actually see shuffles that are entirely re-arrangements of a set of
11384 // zero inputs. This mostly happens while decomposing complex shuffles into
11385 // simple ones. Directly lower these as a buildvector of zeros.
11386 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11387 if (Zeroable.all())
11388 return getZeroVector(VT, Subtarget, DAG, dl);
11390 // Try to collapse shuffles into using a vector type with fewer elements but
11391 // wider element types. We cap this to not form integers or floating point
11392 // elements wider than 64 bits, but it might be interesting to form i128
11393 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11394 SmallVector<int, 16> WidenedMask;
11395 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11396 canWidenShuffleElements(Mask, WidenedMask)) {
11397 MVT NewEltVT = VT.isFloatingPoint()
11398 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11399 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11400 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11401 // Make sure that the new vector type is legal. For example, v2f64 isn't
11403 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11404 V1 = DAG.getBitcast(NewVT, V1);
11405 V2 = DAG.getBitcast(NewVT, V2);
11406 return DAG.getBitcast(
11407 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11411 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11412 for (int M : SVOp->getMask())
11414 ++NumUndefElements;
11415 else if (M < NumElements)
11420 // Commute the shuffle as needed such that more elements come from V1 than
11421 // V2. This allows us to match the shuffle pattern strictly on how many
11422 // elements come from V1 without handling the symmetric cases.
11423 if (NumV2Elements > NumV1Elements)
11424 return DAG.getCommutedVectorShuffle(*SVOp);
11426 // When the number of V1 and V2 elements are the same, try to minimize the
11427 // number of uses of V2 in the low half of the vector. When that is tied,
11428 // ensure that the sum of indices for V1 is equal to or lower than the sum
11429 // indices for V2. When those are equal, try to ensure that the number of odd
11430 // indices for V1 is lower than the number of odd indices for V2.
11431 if (NumV1Elements == NumV2Elements) {
11432 int LowV1Elements = 0, LowV2Elements = 0;
11433 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11434 if (M >= NumElements)
11438 if (LowV2Elements > LowV1Elements) {
11439 return DAG.getCommutedVectorShuffle(*SVOp);
11440 } else if (LowV2Elements == LowV1Elements) {
11441 int SumV1Indices = 0, SumV2Indices = 0;
11442 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11443 if (SVOp->getMask()[i] >= NumElements)
11445 else if (SVOp->getMask()[i] >= 0)
11447 if (SumV2Indices < SumV1Indices) {
11448 return DAG.getCommutedVectorShuffle(*SVOp);
11449 } else if (SumV2Indices == SumV1Indices) {
11450 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11451 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11452 if (SVOp->getMask()[i] >= NumElements)
11453 NumV2OddIndices += i % 2;
11454 else if (SVOp->getMask()[i] >= 0)
11455 NumV1OddIndices += i % 2;
11456 if (NumV2OddIndices < NumV1OddIndices)
11457 return DAG.getCommutedVectorShuffle(*SVOp);
11462 // For each vector width, delegate to a specialized lowering routine.
11463 if (VT.is128BitVector())
11464 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11466 if (VT.is256BitVector())
11467 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11469 if (VT.is512BitVector())
11470 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11473 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11474 llvm_unreachable("Unimplemented!");
11477 // This function assumes its argument is a BUILD_VECTOR of constants or
11478 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11480 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11481 unsigned &MaskValue) {
11483 unsigned NumElems = BuildVector->getNumOperands();
11485 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11486 // We don't handle the >2 lanes case right now.
11487 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11491 unsigned NumElemsInLane = NumElems / NumLanes;
11493 // Blend for v16i16 should be symmetric for the both lanes.
11494 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11495 SDValue EltCond = BuildVector->getOperand(i);
11496 SDValue SndLaneEltCond =
11497 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11499 int Lane1Cond = -1, Lane2Cond = -1;
11500 if (isa<ConstantSDNode>(EltCond))
11501 Lane1Cond = !isNullConstant(EltCond);
11502 if (isa<ConstantSDNode>(SndLaneEltCond))
11503 Lane2Cond = !isNullConstant(SndLaneEltCond);
11505 unsigned LaneMask = 0;
11506 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11507 // Lane1Cond != 0, means we want the first argument.
11508 // Lane1Cond == 0, means we want the second argument.
11509 // The encoding of this argument is 0 for the first argument, 1
11510 // for the second. Therefore, invert the condition.
11511 LaneMask = !Lane1Cond << i;
11512 else if (Lane1Cond < 0)
11513 LaneMask = !Lane2Cond << i;
11517 MaskValue |= LaneMask;
11519 MaskValue |= LaneMask << NumElemsInLane;
11524 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11525 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11526 const X86Subtarget *Subtarget,
11527 SelectionDAG &DAG) {
11528 SDValue Cond = Op.getOperand(0);
11529 SDValue LHS = Op.getOperand(1);
11530 SDValue RHS = Op.getOperand(2);
11532 MVT VT = Op.getSimpleValueType();
11534 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11536 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11538 // Only non-legal VSELECTs reach this lowering, convert those into generic
11539 // shuffles and re-use the shuffle lowering path for blends.
11540 SmallVector<int, 32> Mask;
11541 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11542 SDValue CondElt = CondBV->getOperand(i);
11544 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11547 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11550 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11551 // A vselect where all conditions and data are constants can be optimized into
11552 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11553 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11554 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11555 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11558 // Try to lower this to a blend-style vector shuffle. This can handle all
11559 // constant condition cases.
11560 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11563 // Variable blends are only legal from SSE4.1 onward.
11564 if (!Subtarget->hasSSE41())
11567 // Only some types will be legal on some subtargets. If we can emit a legal
11568 // VSELECT-matching blend, return Op, and but if we need to expand, return
11570 switch (Op.getSimpleValueType().SimpleTy) {
11572 // Most of the vector types have blends past SSE4.1.
11576 // The byte blends for AVX vectors were introduced only in AVX2.
11577 if (Subtarget->hasAVX2())
11584 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11585 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11588 // FIXME: We should custom lower this by fixing the condition and using i8
11594 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11595 MVT VT = Op.getSimpleValueType();
11598 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11601 if (VT.getSizeInBits() == 8) {
11602 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11603 Op.getOperand(0), Op.getOperand(1));
11604 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11605 DAG.getValueType(VT));
11606 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11609 if (VT.getSizeInBits() == 16) {
11610 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11611 if (isNullConstant(Op.getOperand(1)))
11612 return DAG.getNode(
11613 ISD::TRUNCATE, dl, MVT::i16,
11614 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11615 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11616 Op.getOperand(1)));
11617 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11618 Op.getOperand(0), Op.getOperand(1));
11619 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11620 DAG.getValueType(VT));
11621 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11624 if (VT == MVT::f32) {
11625 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11626 // the result back to FR32 register. It's only worth matching if the
11627 // result has a single use which is a store or a bitcast to i32. And in
11628 // the case of a store, it's not worth it if the index is a constant 0,
11629 // because a MOVSSmr can be used instead, which is smaller and faster.
11630 if (!Op.hasOneUse())
11632 SDNode *User = *Op.getNode()->use_begin();
11633 if ((User->getOpcode() != ISD::STORE ||
11634 isNullConstant(Op.getOperand(1))) &&
11635 (User->getOpcode() != ISD::BITCAST ||
11636 User->getValueType(0) != MVT::i32))
11638 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11639 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11641 return DAG.getBitcast(MVT::f32, Extract);
11644 if (VT == MVT::i32 || VT == MVT::i64) {
11645 // ExtractPS/pextrq works with constant index.
11646 if (isa<ConstantSDNode>(Op.getOperand(1)))
11652 /// Extract one bit from mask vector, like v16i1 or v8i1.
11653 /// AVX-512 feature.
11655 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11656 SDValue Vec = Op.getOperand(0);
11658 MVT VecVT = Vec.getSimpleValueType();
11659 SDValue Idx = Op.getOperand(1);
11660 MVT EltVT = Op.getSimpleValueType();
11662 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11663 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11664 "Unexpected vector type in ExtractBitFromMaskVector");
11666 // variable index can't be handled in mask registers,
11667 // extend vector to VR512
11668 if (!isa<ConstantSDNode>(Idx)) {
11669 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11670 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11671 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11672 ExtVT.getVectorElementType(), Ext, Idx);
11673 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11676 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11677 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11678 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11679 rc = getRegClassFor(MVT::v16i1);
11680 unsigned MaxSift = rc->getSize()*8 - 1;
11681 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11682 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11683 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11684 DAG.getConstant(MaxSift, dl, MVT::i8));
11685 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11686 DAG.getIntPtrConstant(0, dl));
11690 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11691 SelectionDAG &DAG) const {
11693 SDValue Vec = Op.getOperand(0);
11694 MVT VecVT = Vec.getSimpleValueType();
11695 SDValue Idx = Op.getOperand(1);
11697 if (Op.getSimpleValueType() == MVT::i1)
11698 return ExtractBitFromMaskVector(Op, DAG);
11700 if (!isa<ConstantSDNode>(Idx)) {
11701 if (VecVT.is512BitVector() ||
11702 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11703 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11706 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11707 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11708 MaskEltVT.getSizeInBits());
11710 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11711 auto PtrVT = getPointerTy(DAG.getDataLayout());
11712 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11713 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11714 DAG.getConstant(0, dl, PtrVT));
11715 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11716 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11717 DAG.getConstant(0, dl, PtrVT));
11722 // If this is a 256-bit vector result, first extract the 128-bit vector and
11723 // then extract the element from the 128-bit vector.
11724 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11726 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11727 // Get the 128-bit vector.
11728 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11729 MVT EltVT = VecVT.getVectorElementType();
11731 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11732 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11734 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11735 // this can be done with a mask.
11736 IdxVal &= ElemsPerChunk - 1;
11737 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11738 DAG.getConstant(IdxVal, dl, MVT::i32));
11741 assert(VecVT.is128BitVector() && "Unexpected vector length");
11743 if (Subtarget->hasSSE41())
11744 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11747 MVT VT = Op.getSimpleValueType();
11748 // TODO: handle v16i8.
11749 if (VT.getSizeInBits() == 16) {
11750 SDValue Vec = Op.getOperand(0);
11751 if (isNullConstant(Op.getOperand(1)))
11752 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11753 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11754 DAG.getBitcast(MVT::v4i32, Vec),
11755 Op.getOperand(1)));
11756 // Transform it so it match pextrw which produces a 32-bit result.
11757 MVT EltVT = MVT::i32;
11758 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11759 Op.getOperand(0), Op.getOperand(1));
11760 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11761 DAG.getValueType(VT));
11762 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11765 if (VT.getSizeInBits() == 32) {
11766 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11770 // SHUFPS the element to the lowest double word, then movss.
11771 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11772 MVT VVT = Op.getOperand(0).getSimpleValueType();
11773 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11774 DAG.getUNDEF(VVT), Mask);
11775 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11776 DAG.getIntPtrConstant(0, dl));
11779 if (VT.getSizeInBits() == 64) {
11780 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11781 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11782 // to match extract_elt for f64.
11783 if (isNullConstant(Op.getOperand(1)))
11786 // UNPCKHPD the element to the lowest double word, then movsd.
11787 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11788 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11789 int Mask[2] = { 1, -1 };
11790 MVT VVT = Op.getOperand(0).getSimpleValueType();
11791 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11792 DAG.getUNDEF(VVT), Mask);
11793 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11794 DAG.getIntPtrConstant(0, dl));
11800 /// Insert one bit to mask vector, like v16i1 or v8i1.
11801 /// AVX-512 feature.
11803 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11805 SDValue Vec = Op.getOperand(0);
11806 SDValue Elt = Op.getOperand(1);
11807 SDValue Idx = Op.getOperand(2);
11808 MVT VecVT = Vec.getSimpleValueType();
11810 if (!isa<ConstantSDNode>(Idx)) {
11811 // Non constant index. Extend source and destination,
11812 // insert element and then truncate the result.
11813 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11814 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11815 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11816 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11817 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11818 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11821 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11822 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11824 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11825 DAG.getConstant(IdxVal, dl, MVT::i8));
11826 if (Vec.getOpcode() == ISD::UNDEF)
11828 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11831 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11832 SelectionDAG &DAG) const {
11833 MVT VT = Op.getSimpleValueType();
11834 MVT EltVT = VT.getVectorElementType();
11836 if (EltVT == MVT::i1)
11837 return InsertBitToMaskVector(Op, DAG);
11840 SDValue N0 = Op.getOperand(0);
11841 SDValue N1 = Op.getOperand(1);
11842 SDValue N2 = Op.getOperand(2);
11843 if (!isa<ConstantSDNode>(N2))
11845 auto *N2C = cast<ConstantSDNode>(N2);
11846 unsigned IdxVal = N2C->getZExtValue();
11848 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11849 // into that, and then insert the subvector back into the result.
11850 if (VT.is256BitVector() || VT.is512BitVector()) {
11851 // With a 256-bit vector, we can insert into the zero element efficiently
11852 // using a blend if we have AVX or AVX2 and the right data type.
11853 if (VT.is256BitVector() && IdxVal == 0) {
11854 // TODO: It is worthwhile to cast integer to floating point and back
11855 // and incur a domain crossing penalty if that's what we'll end up
11856 // doing anyway after extracting to a 128-bit vector.
11857 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11858 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11859 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11860 N2 = DAG.getIntPtrConstant(1, dl);
11861 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11865 // Get the desired 128-bit vector chunk.
11866 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11868 // Insert the element into the desired chunk.
11869 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11870 assert(isPowerOf2_32(NumEltsIn128));
11871 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11872 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11874 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11875 DAG.getConstant(IdxIn128, dl, MVT::i32));
11877 // Insert the changed part back into the bigger vector
11878 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11880 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11882 if (Subtarget->hasSSE41()) {
11883 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11885 if (VT == MVT::v8i16) {
11886 Opc = X86ISD::PINSRW;
11888 assert(VT == MVT::v16i8);
11889 Opc = X86ISD::PINSRB;
11892 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11894 if (N1.getValueType() != MVT::i32)
11895 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11896 if (N2.getValueType() != MVT::i32)
11897 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11898 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11901 if (EltVT == MVT::f32) {
11902 // Bits [7:6] of the constant are the source select. This will always be
11903 // zero here. The DAG Combiner may combine an extract_elt index into
11904 // these bits. For example (insert (extract, 3), 2) could be matched by
11905 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11906 // Bits [5:4] of the constant are the destination select. This is the
11907 // value of the incoming immediate.
11908 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11909 // combine either bitwise AND or insert of float 0.0 to set these bits.
11911 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11912 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11913 // If this is an insertion of 32-bits into the low 32-bits of
11914 // a vector, we prefer to generate a blend with immediate rather
11915 // than an insertps. Blends are simpler operations in hardware and so
11916 // will always have equal or better performance than insertps.
11917 // But if optimizing for size and there's a load folding opportunity,
11918 // generate insertps because blendps does not have a 32-bit memory
11920 N2 = DAG.getIntPtrConstant(1, dl);
11921 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11922 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11924 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11925 // Create this as a scalar to vector..
11926 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11927 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11930 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11931 // PINSR* works with constant index.
11936 if (EltVT == MVT::i8)
11939 if (EltVT.getSizeInBits() == 16) {
11940 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11941 // as its second argument.
11942 if (N1.getValueType() != MVT::i32)
11943 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11944 if (N2.getValueType() != MVT::i32)
11945 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11946 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11951 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11953 MVT OpVT = Op.getSimpleValueType();
11955 // If this is a 256-bit vector result, first insert into a 128-bit
11956 // vector and then insert into the 256-bit vector.
11957 if (!OpVT.is128BitVector()) {
11958 // Insert into a 128-bit vector.
11959 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11960 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11961 OpVT.getVectorNumElements() / SizeFactor);
11963 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11965 // Insert the 128-bit vector.
11966 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11969 if (OpVT == MVT::v1i64 &&
11970 Op.getOperand(0).getValueType() == MVT::i64)
11971 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11973 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11974 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11975 return DAG.getBitcast(
11976 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11979 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11980 // a simple subregister reference or explicit instructions to grab
11981 // upper bits of a vector.
11982 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11983 SelectionDAG &DAG) {
11985 SDValue In = Op.getOperand(0);
11986 SDValue Idx = Op.getOperand(1);
11987 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11988 MVT ResVT = Op.getSimpleValueType();
11989 MVT InVT = In.getSimpleValueType();
11991 if (Subtarget->hasFp256()) {
11992 if (ResVT.is128BitVector() &&
11993 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11994 isa<ConstantSDNode>(Idx)) {
11995 return Extract128BitVector(In, IdxVal, DAG, dl);
11997 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11998 isa<ConstantSDNode>(Idx)) {
11999 return Extract256BitVector(In, IdxVal, DAG, dl);
12005 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12006 // simple superregister reference or explicit instructions to insert
12007 // the upper bits of a vector.
12008 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12009 SelectionDAG &DAG) {
12010 if (!Subtarget->hasAVX())
12014 SDValue Vec = Op.getOperand(0);
12015 SDValue SubVec = Op.getOperand(1);
12016 SDValue Idx = Op.getOperand(2);
12018 if (!isa<ConstantSDNode>(Idx))
12021 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12022 MVT OpVT = Op.getSimpleValueType();
12023 MVT SubVecVT = SubVec.getSimpleValueType();
12025 // Fold two 16-byte subvector loads into one 32-byte load:
12026 // (insert_subvector (insert_subvector undef, (load addr), 0),
12027 // (load addr + 16), Elts/2)
12029 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
12030 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
12031 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
12032 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
12033 if (Idx2 && Idx2->getZExtValue() == 0) {
12034 SDValue SubVec2 = Vec.getOperand(1);
12035 // If needed, look through a bitcast to get to the load.
12036 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
12037 SubVec2 = SubVec2.getOperand(0);
12039 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
12041 unsigned Alignment = FirstLd->getAlignment();
12042 unsigned AS = FirstLd->getAddressSpace();
12043 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
12044 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
12045 OpVT, AS, Alignment, &Fast) && Fast) {
12046 SDValue Ops[] = { SubVec2, SubVec };
12047 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
12054 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
12055 SubVecVT.is128BitVector())
12056 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12058 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
12059 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12061 if (OpVT.getVectorElementType() == MVT::i1)
12062 return Insert1BitVector(Op, DAG);
12067 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12068 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12069 // one of the above mentioned nodes. It has to be wrapped because otherwise
12070 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12071 // be used to form addressing mode. These wrapped nodes will be selected
12074 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12075 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12077 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12078 // global base reg.
12079 unsigned char OpFlag = 0;
12080 unsigned WrapperKind = X86ISD::Wrapper;
12081 CodeModel::Model M = DAG.getTarget().getCodeModel();
12083 if (Subtarget->isPICStyleRIPRel() &&
12084 (M == CodeModel::Small || M == CodeModel::Kernel))
12085 WrapperKind = X86ISD::WrapperRIP;
12086 else if (Subtarget->isPICStyleGOT())
12087 OpFlag = X86II::MO_GOTOFF;
12088 else if (Subtarget->isPICStyleStubPIC())
12089 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12091 auto PtrVT = getPointerTy(DAG.getDataLayout());
12092 SDValue Result = DAG.getTargetConstantPool(
12093 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
12095 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12096 // With PIC, the address is actually $g + Offset.
12099 DAG.getNode(ISD::ADD, DL, PtrVT,
12100 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12106 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12107 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12109 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12110 // global base reg.
12111 unsigned char OpFlag = 0;
12112 unsigned WrapperKind = X86ISD::Wrapper;
12113 CodeModel::Model M = DAG.getTarget().getCodeModel();
12115 if (Subtarget->isPICStyleRIPRel() &&
12116 (M == CodeModel::Small || M == CodeModel::Kernel))
12117 WrapperKind = X86ISD::WrapperRIP;
12118 else if (Subtarget->isPICStyleGOT())
12119 OpFlag = X86II::MO_GOTOFF;
12120 else if (Subtarget->isPICStyleStubPIC())
12121 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12123 auto PtrVT = getPointerTy(DAG.getDataLayout());
12124 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
12126 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12128 // With PIC, the address is actually $g + Offset.
12131 DAG.getNode(ISD::ADD, DL, PtrVT,
12132 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12138 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12139 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12141 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12142 // global base reg.
12143 unsigned char OpFlag = 0;
12144 unsigned WrapperKind = X86ISD::Wrapper;
12145 CodeModel::Model M = DAG.getTarget().getCodeModel();
12147 if (Subtarget->isPICStyleRIPRel() &&
12148 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12149 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12150 OpFlag = X86II::MO_GOTPCREL;
12151 WrapperKind = X86ISD::WrapperRIP;
12152 } else if (Subtarget->isPICStyleGOT()) {
12153 OpFlag = X86II::MO_GOT;
12154 } else if (Subtarget->isPICStyleStubPIC()) {
12155 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12156 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12157 OpFlag = X86II::MO_DARWIN_NONLAZY;
12160 auto PtrVT = getPointerTy(DAG.getDataLayout());
12161 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
12164 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12166 // With PIC, the address is actually $g + Offset.
12167 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12168 !Subtarget->is64Bit()) {
12170 DAG.getNode(ISD::ADD, DL, PtrVT,
12171 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12174 // For symbols that require a load from a stub to get the address, emit the
12176 if (isGlobalStubReference(OpFlag))
12177 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
12178 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12179 false, false, false, 0);
12185 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12186 // Create the TargetBlockAddressAddress node.
12187 unsigned char OpFlags =
12188 Subtarget->ClassifyBlockAddressReference();
12189 CodeModel::Model M = DAG.getTarget().getCodeModel();
12190 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12191 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12193 auto PtrVT = getPointerTy(DAG.getDataLayout());
12194 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12196 if (Subtarget->isPICStyleRIPRel() &&
12197 (M == CodeModel::Small || M == CodeModel::Kernel))
12198 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12200 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12202 // With PIC, the address is actually $g + Offset.
12203 if (isGlobalRelativeToPICBase(OpFlags)) {
12204 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12205 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12212 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12213 int64_t Offset, SelectionDAG &DAG) const {
12214 // Create the TargetGlobalAddress node, folding in the constant
12215 // offset if it is legal.
12216 unsigned char OpFlags =
12217 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12218 CodeModel::Model M = DAG.getTarget().getCodeModel();
12219 auto PtrVT = getPointerTy(DAG.getDataLayout());
12221 if (OpFlags == X86II::MO_NO_FLAG &&
12222 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12223 // A direct static reference to a global.
12224 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12227 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12230 if (Subtarget->isPICStyleRIPRel() &&
12231 (M == CodeModel::Small || M == CodeModel::Kernel))
12232 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12234 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12236 // With PIC, the address is actually $g + Offset.
12237 if (isGlobalRelativeToPICBase(OpFlags)) {
12238 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12239 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12242 // For globals that require a load from a stub to get the address, emit the
12244 if (isGlobalStubReference(OpFlags))
12245 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12246 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12247 false, false, false, 0);
12249 // If there was a non-zero offset that we didn't fold, create an explicit
12250 // addition for it.
12252 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12253 DAG.getConstant(Offset, dl, PtrVT));
12259 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12260 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12261 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12262 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12266 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12267 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12268 unsigned char OperandFlags, bool LocalDynamic = false) {
12269 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12270 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12272 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12273 GA->getValueType(0),
12277 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12281 SDValue Ops[] = { Chain, TGA, *InFlag };
12282 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12284 SDValue Ops[] = { Chain, TGA };
12285 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12288 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12289 MFI->setAdjustsStack(true);
12290 MFI->setHasCalls(true);
12292 SDValue Flag = Chain.getValue(1);
12293 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12296 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12298 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12301 SDLoc dl(GA); // ? function entry point might be better
12302 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12303 DAG.getNode(X86ISD::GlobalBaseReg,
12304 SDLoc(), PtrVT), InFlag);
12305 InFlag = Chain.getValue(1);
12307 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12310 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12312 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12314 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12315 X86::RAX, X86II::MO_TLSGD);
12318 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12324 // Get the start address of the TLS block for this module.
12325 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12326 .getInfo<X86MachineFunctionInfo>();
12327 MFI->incNumLocalDynamicTLSAccesses();
12331 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12332 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12335 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12336 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12337 InFlag = Chain.getValue(1);
12338 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12339 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12342 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12346 unsigned char OperandFlags = X86II::MO_DTPOFF;
12347 unsigned WrapperKind = X86ISD::Wrapper;
12348 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12349 GA->getValueType(0),
12350 GA->getOffset(), OperandFlags);
12351 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12353 // Add x@dtpoff with the base.
12354 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12357 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12358 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12359 const EVT PtrVT, TLSModel::Model model,
12360 bool is64Bit, bool isPIC) {
12363 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12364 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12365 is64Bit ? 257 : 256));
12367 SDValue ThreadPointer =
12368 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12369 MachinePointerInfo(Ptr), false, false, false, 0);
12371 unsigned char OperandFlags = 0;
12372 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12374 unsigned WrapperKind = X86ISD::Wrapper;
12375 if (model == TLSModel::LocalExec) {
12376 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12377 } else if (model == TLSModel::InitialExec) {
12379 OperandFlags = X86II::MO_GOTTPOFF;
12380 WrapperKind = X86ISD::WrapperRIP;
12382 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12385 llvm_unreachable("Unexpected model");
12388 // emit "addl x@ntpoff,%eax" (local exec)
12389 // or "addl x@indntpoff,%eax" (initial exec)
12390 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12392 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12393 GA->getOffset(), OperandFlags);
12394 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12396 if (model == TLSModel::InitialExec) {
12397 if (isPIC && !is64Bit) {
12398 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12399 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12403 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12404 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12405 false, false, false, 0);
12408 // The address of the thread local variable is the add of the thread
12409 // pointer with the offset of the variable.
12410 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12414 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12416 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12418 // Cygwin uses emutls.
12419 // FIXME: It may be EmulatedTLS-generic also for X86-Android.
12420 if (Subtarget->isTargetWindowsCygwin())
12421 return LowerToTLSEmulatedModel(GA, DAG);
12423 const GlobalValue *GV = GA->getGlobal();
12424 auto PtrVT = getPointerTy(DAG.getDataLayout());
12426 if (Subtarget->isTargetELF()) {
12427 if (DAG.getTarget().Options.EmulatedTLS)
12428 return LowerToTLSEmulatedModel(GA, DAG);
12429 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12431 case TLSModel::GeneralDynamic:
12432 if (Subtarget->is64Bit())
12433 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12434 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12435 case TLSModel::LocalDynamic:
12436 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12437 Subtarget->is64Bit());
12438 case TLSModel::InitialExec:
12439 case TLSModel::LocalExec:
12440 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12441 DAG.getTarget().getRelocationModel() ==
12444 llvm_unreachable("Unknown TLS model.");
12447 if (Subtarget->isTargetDarwin()) {
12448 // Darwin only has one model of TLS. Lower to that.
12449 unsigned char OpFlag = 0;
12450 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12451 X86ISD::WrapperRIP : X86ISD::Wrapper;
12453 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12454 // global base reg.
12455 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12456 !Subtarget->is64Bit();
12458 OpFlag = X86II::MO_TLVP_PIC_BASE;
12460 OpFlag = X86II::MO_TLVP;
12462 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12463 GA->getValueType(0),
12464 GA->getOffset(), OpFlag);
12465 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12467 // With PIC32, the address is actually $g + Offset.
12469 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12470 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12473 // Lowering the machine isd will make sure everything is in the right
12475 SDValue Chain = DAG.getEntryNode();
12476 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12477 SDValue Args[] = { Chain, Offset };
12478 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12480 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12481 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12482 MFI->setAdjustsStack(true);
12484 // And our return value (tls address) is in the standard call return value
12486 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12487 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12490 if (Subtarget->isTargetKnownWindowsMSVC() ||
12491 Subtarget->isTargetWindowsGNU()) {
12492 // Just use the implicit TLS architecture
12493 // Need to generate someting similar to:
12494 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12496 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12497 // mov rcx, qword [rdx+rcx*8]
12498 // mov eax, .tls$:tlsvar
12499 // [rax+rcx] contains the address
12500 // Windows 64bit: gs:0x58
12501 // Windows 32bit: fs:__tls_array
12504 SDValue Chain = DAG.getEntryNode();
12506 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12507 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12508 // use its literal value of 0x2C.
12509 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12510 ? Type::getInt8PtrTy(*DAG.getContext(),
12512 : Type::getInt32PtrTy(*DAG.getContext(),
12515 SDValue TlsArray = Subtarget->is64Bit()
12516 ? DAG.getIntPtrConstant(0x58, dl)
12517 : (Subtarget->isTargetWindowsGNU()
12518 ? DAG.getIntPtrConstant(0x2C, dl)
12519 : DAG.getExternalSymbol("_tls_array", PtrVT));
12521 SDValue ThreadPointer =
12522 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12526 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12527 res = ThreadPointer;
12529 // Load the _tls_index variable
12530 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12531 if (Subtarget->is64Bit())
12532 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12533 MachinePointerInfo(), MVT::i32, false, false,
12536 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12539 auto &DL = DAG.getDataLayout();
12541 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12542 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12544 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12547 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12550 // Get the offset of start of .tls section
12551 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12552 GA->getValueType(0),
12553 GA->getOffset(), X86II::MO_SECREL);
12554 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12556 // The address of the thread local variable is the add of the thread
12557 // pointer with the offset of the variable.
12558 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12561 llvm_unreachable("TLS not implemented for this target.");
12564 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12565 /// and take a 2 x i32 value to shift plus a shift amount.
12566 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12567 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12568 MVT VT = Op.getSimpleValueType();
12569 unsigned VTBits = VT.getSizeInBits();
12571 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12572 SDValue ShOpLo = Op.getOperand(0);
12573 SDValue ShOpHi = Op.getOperand(1);
12574 SDValue ShAmt = Op.getOperand(2);
12575 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12576 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12578 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12579 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12580 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12581 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12582 : DAG.getConstant(0, dl, VT);
12584 SDValue Tmp2, Tmp3;
12585 if (Op.getOpcode() == ISD::SHL_PARTS) {
12586 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12587 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12589 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12590 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12593 // If the shift amount is larger or equal than the width of a part we can't
12594 // rely on the results of shld/shrd. Insert a test and select the appropriate
12595 // values for large shift amounts.
12596 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12597 DAG.getConstant(VTBits, dl, MVT::i8));
12598 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12599 AndNode, DAG.getConstant(0, dl, MVT::i8));
12602 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12603 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12604 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12606 if (Op.getOpcode() == ISD::SHL_PARTS) {
12607 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12608 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12610 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12611 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12614 SDValue Ops[2] = { Lo, Hi };
12615 return DAG.getMergeValues(Ops, dl);
12618 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12619 SelectionDAG &DAG) const {
12620 SDValue Src = Op.getOperand(0);
12621 MVT SrcVT = Src.getSimpleValueType();
12622 MVT VT = Op.getSimpleValueType();
12625 if (SrcVT.isVector()) {
12626 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12627 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12628 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12629 DAG.getUNDEF(SrcVT)));
12631 if (SrcVT.getVectorElementType() == MVT::i1) {
12632 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12633 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12634 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12639 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12640 "Unknown SINT_TO_FP to lower!");
12642 // These are really Legal; return the operand so the caller accepts it as
12644 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12646 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12647 Subtarget->is64Bit()) {
12651 unsigned Size = SrcVT.getSizeInBits()/8;
12652 MachineFunction &MF = DAG.getMachineFunction();
12653 auto PtrVT = getPointerTy(MF.getDataLayout());
12654 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12655 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12656 SDValue Chain = DAG.getStore(
12657 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12658 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12660 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12663 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12665 SelectionDAG &DAG) const {
12669 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12671 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12673 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12675 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12677 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12678 MachineMemOperand *MMO;
12680 int SSFI = FI->getIndex();
12681 MMO = DAG.getMachineFunction().getMachineMemOperand(
12682 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12683 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12685 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12686 StackSlot = StackSlot.getOperand(1);
12688 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12689 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12691 Tys, Ops, SrcVT, MMO);
12694 Chain = Result.getValue(1);
12695 SDValue InFlag = Result.getValue(2);
12697 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12698 // shouldn't be necessary except that RFP cannot be live across
12699 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12700 MachineFunction &MF = DAG.getMachineFunction();
12701 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12702 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12703 auto PtrVT = getPointerTy(MF.getDataLayout());
12704 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12705 Tys = DAG.getVTList(MVT::Other);
12707 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12709 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12710 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12711 MachineMemOperand::MOStore, SSFISize, SSFISize);
12713 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12714 Ops, Op.getValueType(), MMO);
12715 Result = DAG.getLoad(
12716 Op.getValueType(), DL, Chain, StackSlot,
12717 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12718 false, false, false, 0);
12724 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12725 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12726 SelectionDAG &DAG) const {
12727 // This algorithm is not obvious. Here it is what we're trying to output:
12730 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12731 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12733 haddpd %xmm0, %xmm0
12735 pshufd $0x4e, %xmm0, %xmm1
12741 LLVMContext *Context = DAG.getContext();
12743 // Build some magic constants.
12744 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12745 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12746 auto PtrVT = getPointerTy(DAG.getDataLayout());
12747 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12749 SmallVector<Constant*,2> CV1;
12751 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12752 APInt(64, 0x4330000000000000ULL))));
12754 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12755 APInt(64, 0x4530000000000000ULL))));
12756 Constant *C1 = ConstantVector::get(CV1);
12757 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12759 // Load the 64-bit value into an XMM register.
12760 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12763 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12764 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12765 false, false, false, 16);
12767 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12770 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12771 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12772 false, false, false, 16);
12773 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12774 // TODO: Are there any fast-math-flags to propagate here?
12775 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12778 if (Subtarget->hasSSE3()) {
12779 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12780 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12782 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12783 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12785 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12786 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12789 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12790 DAG.getIntPtrConstant(0, dl));
12793 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12794 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12795 SelectionDAG &DAG) const {
12797 // FP constant to bias correct the final result.
12798 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12801 // Load the 32-bit value into an XMM register.
12802 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12805 // Zero out the upper parts of the register.
12806 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12808 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12809 DAG.getBitcast(MVT::v2f64, Load),
12810 DAG.getIntPtrConstant(0, dl));
12812 // Or the load with the bias.
12813 SDValue Or = DAG.getNode(
12814 ISD::OR, dl, MVT::v2i64,
12815 DAG.getBitcast(MVT::v2i64,
12816 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12817 DAG.getBitcast(MVT::v2i64,
12818 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12820 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12821 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12823 // Subtract the bias.
12824 // TODO: Are there any fast-math-flags to propagate here?
12825 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12827 // Handle final rounding.
12828 MVT DestVT = Op.getSimpleValueType();
12830 if (DestVT.bitsLT(MVT::f64))
12831 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12832 DAG.getIntPtrConstant(0, dl));
12833 if (DestVT.bitsGT(MVT::f64))
12834 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12836 // Handle final rounding.
12840 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12841 const X86Subtarget &Subtarget) {
12842 // The algorithm is the following:
12843 // #ifdef __SSE4_1__
12844 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12845 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12846 // (uint4) 0x53000000, 0xaa);
12848 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12849 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12851 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12852 // return (float4) lo + fhi;
12854 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12855 // reassociate the two FADDs, and if we do that, the algorithm fails
12856 // spectacularly (PR24512).
12857 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12858 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12859 // there's also the MachineCombiner reassociations happening on Machine IR.
12860 if (DAG.getTarget().Options.UnsafeFPMath)
12864 SDValue V = Op->getOperand(0);
12865 MVT VecIntVT = V.getSimpleValueType();
12866 bool Is128 = VecIntVT == MVT::v4i32;
12867 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12868 // If we convert to something else than the supported type, e.g., to v4f64,
12870 if (VecFloatVT != Op->getSimpleValueType(0))
12873 unsigned NumElts = VecIntVT.getVectorNumElements();
12874 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12875 "Unsupported custom type");
12876 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12878 // In the #idef/#else code, we have in common:
12879 // - The vector of constants:
12885 // Create the splat vector for 0x4b000000.
12886 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12887 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12888 CstLow, CstLow, CstLow, CstLow};
12889 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12890 makeArrayRef(&CstLowArray[0], NumElts));
12891 // Create the splat vector for 0x53000000.
12892 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12893 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12894 CstHigh, CstHigh, CstHigh, CstHigh};
12895 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12896 makeArrayRef(&CstHighArray[0], NumElts));
12898 // Create the right shift.
12899 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12900 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12901 CstShift, CstShift, CstShift, CstShift};
12902 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12903 makeArrayRef(&CstShiftArray[0], NumElts));
12904 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12907 if (Subtarget.hasSSE41()) {
12908 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12909 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12910 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12911 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12912 // Low will be bitcasted right away, so do not bother bitcasting back to its
12914 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12915 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12916 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12917 // (uint4) 0x53000000, 0xaa);
12918 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12919 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12920 // High will be bitcasted right away, so do not bother bitcasting back to
12921 // its original type.
12922 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12923 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12925 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12926 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12927 CstMask, CstMask, CstMask);
12928 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12929 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12930 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12932 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12933 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12936 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12937 SDValue CstFAdd = DAG.getConstantFP(
12938 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12939 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12940 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12941 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12942 makeArrayRef(&CstFAddArray[0], NumElts));
12944 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12945 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12946 // TODO: Are there any fast-math-flags to propagate here?
12948 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12949 // return (float4) lo + fhi;
12950 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12951 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12954 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12955 SelectionDAG &DAG) const {
12956 SDValue N0 = Op.getOperand(0);
12957 MVT SVT = N0.getSimpleValueType();
12960 switch (SVT.SimpleTy) {
12962 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12967 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12968 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12969 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12973 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12976 assert(Subtarget->hasAVX512());
12977 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12978 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12982 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12983 SelectionDAG &DAG) const {
12984 SDValue N0 = Op.getOperand(0);
12986 auto PtrVT = getPointerTy(DAG.getDataLayout());
12988 if (Op.getSimpleValueType().isVector())
12989 return lowerUINT_TO_FP_vec(Op, DAG);
12991 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12992 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12993 // the optimization here.
12994 if (DAG.SignBitIsZero(N0))
12995 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12997 MVT SrcVT = N0.getSimpleValueType();
12998 MVT DstVT = Op.getSimpleValueType();
13000 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
13001 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
13002 // Conversions from unsigned i32 to f32/f64 are legal,
13003 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
13007 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13008 return LowerUINT_TO_FP_i64(Op, DAG);
13009 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13010 return LowerUINT_TO_FP_i32(Op, DAG);
13011 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13014 // Make a 64-bit buffer, and use it to build an FILD.
13015 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13016 if (SrcVT == MVT::i32) {
13017 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
13018 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
13019 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13020 StackSlot, MachinePointerInfo(),
13022 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
13023 OffsetSlot, MachinePointerInfo(),
13025 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13029 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13030 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13031 StackSlot, MachinePointerInfo(),
13033 // For i64 source, we need to add the appropriate power of 2 if the input
13034 // was negative. This is the same as the optimization in
13035 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13036 // we must be careful to do the computation in x87 extended precision, not
13037 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13038 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13039 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
13040 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
13041 MachineMemOperand::MOLoad, 8, 8);
13043 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13044 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13045 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13048 APInt FF(32, 0x5F800000ULL);
13050 // Check whether the sign bit is set.
13051 SDValue SignSet = DAG.getSetCC(
13052 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
13053 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
13055 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13056 SDValue FudgePtr = DAG.getConstantPool(
13057 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
13059 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13060 SDValue Zero = DAG.getIntPtrConstant(0, dl);
13061 SDValue Four = DAG.getIntPtrConstant(4, dl);
13062 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13064 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
13066 // Load the value out, extending it from f32 to f80.
13067 // FIXME: Avoid the extend by constructing the right constant pool?
13068 SDValue Fudge = DAG.getExtLoad(
13069 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
13070 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
13071 false, false, false, 4);
13072 // Extend everything to 80 bits to force it to be done on x87.
13073 // TODO: Are there any fast-math-flags to propagate here?
13074 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13075 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
13076 DAG.getIntPtrConstant(0, dl));
13079 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
13080 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
13081 // just return an <SDValue(), SDValue()> pair.
13082 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
13083 // to i16, i32 or i64, and we lower it to a legal sequence.
13084 // If lowered to the final integer result we return a <result, SDValue()> pair.
13085 // Otherwise we lower it to a sequence ending with a FIST, return a
13086 // <FIST, StackSlot> pair, and the caller is responsible for loading
13087 // the final integer result from StackSlot.
13088 std::pair<SDValue,SDValue>
13089 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13090 bool IsSigned, bool IsReplace) const {
13093 EVT DstTy = Op.getValueType();
13094 EVT TheVT = Op.getOperand(0).getValueType();
13095 auto PtrVT = getPointerTy(DAG.getDataLayout());
13097 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
13098 // f16 must be promoted before using the lowering in this routine.
13099 // fp128 does not use this lowering.
13100 return std::make_pair(SDValue(), SDValue());
13103 // If using FIST to compute an unsigned i64, we'll need some fixup
13104 // to handle values above the maximum signed i64. A FIST is always
13105 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
13106 bool UnsignedFixup = !IsSigned &&
13107 DstTy == MVT::i64 &&
13108 (!Subtarget->is64Bit() ||
13109 !isScalarFPTypeInSSEReg(TheVT));
13111 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
13112 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
13113 // The low 32 bits of the fist result will have the correct uint32 result.
13114 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13118 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13119 DstTy.getSimpleVT() >= MVT::i16 &&
13120 "Unknown FP_TO_INT to lower!");
13122 // These are really Legal.
13123 if (DstTy == MVT::i32 &&
13124 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13125 return std::make_pair(SDValue(), SDValue());
13126 if (Subtarget->is64Bit() &&
13127 DstTy == MVT::i64 &&
13128 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13129 return std::make_pair(SDValue(), SDValue());
13131 // We lower FP->int64 into FISTP64 followed by a load from a temporary
13133 MachineFunction &MF = DAG.getMachineFunction();
13134 unsigned MemSize = DstTy.getSizeInBits()/8;
13135 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13136 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13139 switch (DstTy.getSimpleVT().SimpleTy) {
13140 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13141 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13142 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13143 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13146 SDValue Chain = DAG.getEntryNode();
13147 SDValue Value = Op.getOperand(0);
13148 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
13150 if (UnsignedFixup) {
13152 // Conversion to unsigned i64 is implemented with a select,
13153 // depending on whether the source value fits in the range
13154 // of a signed i64. Let Thresh be the FP equivalent of
13155 // 0x8000000000000000ULL.
13157 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
13158 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
13159 // Fist-to-mem64 FistSrc
13160 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
13161 // to XOR'ing the high 32 bits with Adjust.
13163 // Being a power of 2, Thresh is exactly representable in all FP formats.
13164 // For X87 we'd like to use the smallest FP type for this constant, but
13165 // for DAG type consistency we have to match the FP operand type.
13167 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
13168 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
13169 bool LosesInfo = false;
13170 if (TheVT == MVT::f64)
13171 // The rounding mode is irrelevant as the conversion should be exact.
13172 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
13174 else if (TheVT == MVT::f80)
13175 Status = Thresh.convert(APFloat::x87DoubleExtended,
13176 APFloat::rmNearestTiesToEven, &LosesInfo);
13178 assert(Status == APFloat::opOK && !LosesInfo &&
13179 "FP conversion should have been exact");
13181 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
13183 SDValue Cmp = DAG.getSetCC(DL,
13184 getSetCCResultType(DAG.getDataLayout(),
13185 *DAG.getContext(), TheVT),
13186 Value, ThreshVal, ISD::SETLT);
13187 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
13188 DAG.getConstant(0, DL, MVT::i32),
13189 DAG.getConstant(0x80000000, DL, MVT::i32));
13190 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
13191 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
13192 *DAG.getContext(), TheVT),
13193 Value, ThreshVal, ISD::SETLT);
13194 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13197 // FIXME This causes a redundant load/store if the SSE-class value is already
13198 // in memory, such as if it is on the callstack.
13199 if (isScalarFPTypeInSSEReg(TheVT)) {
13200 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13201 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13202 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13204 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13206 Chain, StackSlot, DAG.getValueType(TheVT)
13209 MachineMemOperand *MMO =
13210 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13211 MachineMemOperand::MOLoad, MemSize, MemSize);
13212 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13213 Chain = Value.getValue(1);
13214 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13215 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13218 MachineMemOperand *MMO =
13219 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13220 MachineMemOperand::MOStore, MemSize, MemSize);
13222 if (UnsignedFixup) {
13224 // Insert the FIST, load its result as two i32's,
13225 // and XOR the high i32 with Adjust.
13227 SDValue FistOps[] = { Chain, Value, StackSlot };
13228 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13229 FistOps, DstTy, MMO);
13231 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13232 MachinePointerInfo(),
13233 false, false, false, 0);
13234 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13235 DAG.getConstant(4, DL, PtrVT));
13237 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13238 MachinePointerInfo(),
13239 false, false, false, 0);
13240 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13242 if (Subtarget->is64Bit()) {
13243 // Join High32 and Low32 into a 64-bit result.
13244 // (High32 << 32) | Low32
13245 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13246 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13247 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13248 DAG.getConstant(32, DL, MVT::i8));
13249 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13250 return std::make_pair(Result, SDValue());
13253 SDValue ResultOps[] = { Low32, High32 };
13255 SDValue pair = IsReplace
13256 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13257 : DAG.getMergeValues(ResultOps, DL);
13258 return std::make_pair(pair, SDValue());
13260 // Build the FP_TO_INT*_IN_MEM
13261 SDValue Ops[] = { Chain, Value, StackSlot };
13262 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13264 return std::make_pair(FIST, StackSlot);
13268 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13269 const X86Subtarget *Subtarget) {
13270 MVT VT = Op->getSimpleValueType(0);
13271 SDValue In = Op->getOperand(0);
13272 MVT InVT = In.getSimpleValueType();
13275 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13276 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13278 // Optimize vectors in AVX mode:
13281 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13282 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13283 // Concat upper and lower parts.
13286 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13287 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13288 // Concat upper and lower parts.
13291 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13292 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13293 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13296 if (Subtarget->hasInt256())
13297 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13299 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13300 SDValue Undef = DAG.getUNDEF(InVT);
13301 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13302 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13303 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13305 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13306 VT.getVectorNumElements()/2);
13308 OpLo = DAG.getBitcast(HVT, OpLo);
13309 OpHi = DAG.getBitcast(HVT, OpHi);
13311 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13314 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13315 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13316 MVT VT = Op->getSimpleValueType(0);
13317 SDValue In = Op->getOperand(0);
13318 MVT InVT = In.getSimpleValueType();
13320 unsigned int NumElts = VT.getVectorNumElements();
13321 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13324 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13325 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13327 assert(InVT.getVectorElementType() == MVT::i1);
13328 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13330 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13332 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13334 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13335 if (VT.is512BitVector())
13337 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13340 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13341 SelectionDAG &DAG) {
13342 if (Subtarget->hasFp256())
13343 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13349 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13350 SelectionDAG &DAG) {
13352 MVT VT = Op.getSimpleValueType();
13353 SDValue In = Op.getOperand(0);
13354 MVT SVT = In.getSimpleValueType();
13356 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13357 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13359 if (Subtarget->hasFp256())
13360 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13363 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13364 VT.getVectorNumElements() != SVT.getVectorNumElements());
13368 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13370 MVT VT = Op.getSimpleValueType();
13371 SDValue In = Op.getOperand(0);
13372 MVT InVT = In.getSimpleValueType();
13374 if (VT == MVT::i1) {
13375 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13376 "Invalid scalar TRUNCATE operation");
13377 if (InVT.getSizeInBits() >= 32)
13379 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13380 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13382 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13383 "Invalid TRUNCATE operation");
13385 // move vector to mask - truncate solution for SKX
13386 if (VT.getVectorElementType() == MVT::i1) {
13387 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13388 Subtarget->hasBWI())
13389 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13390 if ((InVT.is256BitVector() || InVT.is128BitVector())
13391 && InVT.getScalarSizeInBits() <= 16 &&
13392 Subtarget->hasBWI() && Subtarget->hasVLX())
13393 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13394 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13395 Subtarget->hasDQI())
13396 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13397 if ((InVT.is256BitVector() || InVT.is128BitVector())
13398 && InVT.getScalarSizeInBits() >= 32 &&
13399 Subtarget->hasDQI() && Subtarget->hasVLX())
13400 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13403 if (VT.getVectorElementType() == MVT::i1) {
13404 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13405 unsigned NumElts = InVT.getVectorNumElements();
13406 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13407 if (InVT.getSizeInBits() < 512) {
13408 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13409 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13414 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13415 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13416 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13419 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13420 if (Subtarget->hasAVX512()) {
13421 // word to byte only under BWI
13422 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13423 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13424 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13425 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13427 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13428 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13429 if (Subtarget->hasInt256()) {
13430 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13431 In = DAG.getBitcast(MVT::v8i32, In);
13432 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13434 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13435 DAG.getIntPtrConstant(0, DL));
13438 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13439 DAG.getIntPtrConstant(0, DL));
13440 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13441 DAG.getIntPtrConstant(2, DL));
13442 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13443 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13444 static const int ShufMask[] = {0, 2, 4, 6};
13445 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13448 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13449 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13450 if (Subtarget->hasInt256()) {
13451 In = DAG.getBitcast(MVT::v32i8, In);
13453 SmallVector<SDValue,32> pshufbMask;
13454 for (unsigned i = 0; i < 2; ++i) {
13455 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13456 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13457 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13458 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13459 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13460 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13461 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13462 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13463 for (unsigned j = 0; j < 8; ++j)
13464 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13466 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13467 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13468 In = DAG.getBitcast(MVT::v4i64, In);
13470 static const int ShufMask[] = {0, 2, -1, -1};
13471 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13473 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13474 DAG.getIntPtrConstant(0, DL));
13475 return DAG.getBitcast(VT, In);
13478 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13479 DAG.getIntPtrConstant(0, DL));
13481 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13482 DAG.getIntPtrConstant(4, DL));
13484 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13485 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13487 // The PSHUFB mask:
13488 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13489 -1, -1, -1, -1, -1, -1, -1, -1};
13491 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13492 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13493 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13495 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13496 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13498 // The MOVLHPS Mask:
13499 static const int ShufMask2[] = {0, 1, 4, 5};
13500 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13501 return DAG.getBitcast(MVT::v8i16, res);
13504 // Handle truncation of V256 to V128 using shuffles.
13505 if (!VT.is128BitVector() || !InVT.is256BitVector())
13508 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13510 unsigned NumElems = VT.getVectorNumElements();
13511 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13513 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13514 // Prepare truncation shuffle mask
13515 for (unsigned i = 0; i != NumElems; ++i)
13516 MaskVec[i] = i * 2;
13517 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13518 DAG.getUNDEF(NVT), &MaskVec[0]);
13519 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13520 DAG.getIntPtrConstant(0, DL));
13523 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13524 SelectionDAG &DAG) const {
13525 assert(!Op.getSimpleValueType().isVector());
13527 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13528 /*IsSigned=*/ true, /*IsReplace=*/ false);
13529 SDValue FIST = Vals.first, StackSlot = Vals.second;
13530 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13531 if (!FIST.getNode())
13534 if (StackSlot.getNode())
13535 // Load the result.
13536 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13537 FIST, StackSlot, MachinePointerInfo(),
13538 false, false, false, 0);
13540 // The node is the result.
13544 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13545 SelectionDAG &DAG) const {
13546 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13547 /*IsSigned=*/ false, /*IsReplace=*/ false);
13548 SDValue FIST = Vals.first, StackSlot = Vals.second;
13549 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13550 if (!FIST.getNode())
13553 if (StackSlot.getNode())
13554 // Load the result.
13555 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13556 FIST, StackSlot, MachinePointerInfo(),
13557 false, false, false, 0);
13559 // The node is the result.
13563 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13565 MVT VT = Op.getSimpleValueType();
13566 SDValue In = Op.getOperand(0);
13567 MVT SVT = In.getSimpleValueType();
13569 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13571 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13572 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13573 In, DAG.getUNDEF(SVT)));
13576 /// The only differences between FABS and FNEG are the mask and the logic op.
13577 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13578 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13579 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13580 "Wrong opcode for lowering FABS or FNEG.");
13582 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13584 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13585 // into an FNABS. We'll lower the FABS after that if it is still in use.
13587 for (SDNode *User : Op->uses())
13588 if (User->getOpcode() == ISD::FNEG)
13592 MVT VT = Op.getSimpleValueType();
13594 bool IsF128 = (VT == MVT::f128);
13596 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13597 // decide if we should generate a 16-byte constant mask when we only need 4 or
13598 // 8 bytes for the scalar case.
13604 if (VT.isVector()) {
13606 EltVT = VT.getVectorElementType();
13607 NumElts = VT.getVectorNumElements();
13608 } else if (IsF128) {
13609 // SSE instructions are used for optimized f128 logical operations.
13610 LogicVT = MVT::f128;
13614 // There are no scalar bitwise logical SSE/AVX instructions, so we
13615 // generate a 16-byte vector constant and logic op even for the scalar case.
13616 // Using a 16-byte mask allows folding the load of the mask with
13617 // the logic op, so it can save (~4 bytes) on code size.
13618 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13620 NumElts = (VT == MVT::f64) ? 2 : 4;
13623 unsigned EltBits = EltVT.getSizeInBits();
13624 LLVMContext *Context = DAG.getContext();
13625 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13627 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13628 Constant *C = ConstantInt::get(*Context, MaskElt);
13629 C = ConstantVector::getSplat(NumElts, C);
13630 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13631 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13632 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13634 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13635 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13636 false, false, false, Alignment);
13638 SDValue Op0 = Op.getOperand(0);
13639 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13641 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13642 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13644 if (VT.isVector() || IsF128)
13645 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13647 // For the scalar case extend to a 128-bit vector, perform the logic op,
13648 // and extract the scalar result back out.
13649 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13650 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13651 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13652 DAG.getIntPtrConstant(0, dl));
13655 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13656 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13657 LLVMContext *Context = DAG.getContext();
13658 SDValue Op0 = Op.getOperand(0);
13659 SDValue Op1 = Op.getOperand(1);
13661 MVT VT = Op.getSimpleValueType();
13662 MVT SrcVT = Op1.getSimpleValueType();
13663 bool IsF128 = (VT == MVT::f128);
13665 // If second operand is smaller, extend it first.
13666 if (SrcVT.bitsLT(VT)) {
13667 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13670 // And if it is bigger, shrink it first.
13671 if (SrcVT.bitsGT(VT)) {
13672 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13676 // At this point the operands and the result should have the same
13677 // type, and that won't be f80 since that is not custom lowered.
13678 assert((VT == MVT::f64 || VT == MVT::f32 || IsF128) &&
13679 "Unexpected type in LowerFCOPYSIGN");
13681 const fltSemantics &Sem =
13682 VT == MVT::f64 ? APFloat::IEEEdouble :
13683 (IsF128 ? APFloat::IEEEquad : APFloat::IEEEsingle);
13684 const unsigned SizeInBits = VT.getSizeInBits();
13686 SmallVector<Constant *, 4> CV(
13687 VT == MVT::f64 ? 2 : (IsF128 ? 1 : 4),
13688 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13690 // First, clear all bits but the sign bit from the second operand (sign).
13691 CV[0] = ConstantFP::get(*Context,
13692 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13693 Constant *C = ConstantVector::get(CV);
13694 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13695 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13697 // Perform all logic operations as 16-byte vectors because there are no
13698 // scalar FP logic instructions in SSE. This allows load folding of the
13699 // constants into the logic instructions.
13700 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : (IsF128 ? MVT::f128 : MVT::v4f32);
13702 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13703 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13704 false, false, false, 16);
13706 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13707 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13709 // Next, clear the sign bit from the first operand (magnitude).
13710 // If it's a constant, we can clear it here.
13711 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13712 APFloat APF = Op0CN->getValueAPF();
13713 // If the magnitude is a positive zero, the sign bit alone is enough.
13714 if (APF.isPosZero())
13715 return IsF128 ? SignBit :
13716 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13717 DAG.getIntPtrConstant(0, dl));
13719 CV[0] = ConstantFP::get(*Context, APF);
13721 CV[0] = ConstantFP::get(
13723 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13725 C = ConstantVector::get(CV);
13726 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13728 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13729 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13730 false, false, false, 16);
13731 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13732 if (!isa<ConstantFPSDNode>(Op0)) {
13734 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13735 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13737 // OR the magnitude value with the sign bit.
13738 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13739 return IsF128 ? Val :
13740 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13741 DAG.getIntPtrConstant(0, dl));
13744 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13745 SDValue N0 = Op.getOperand(0);
13747 MVT VT = Op.getSimpleValueType();
13749 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13750 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13751 DAG.getConstant(1, dl, VT));
13752 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13755 // Check whether an OR'd tree is PTEST-able.
13756 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13757 SelectionDAG &DAG) {
13758 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13760 if (!Subtarget->hasSSE41())
13763 if (!Op->hasOneUse())
13766 SDNode *N = Op.getNode();
13769 SmallVector<SDValue, 8> Opnds;
13770 DenseMap<SDValue, unsigned> VecInMap;
13771 SmallVector<SDValue, 8> VecIns;
13772 EVT VT = MVT::Other;
13774 // Recognize a special case where a vector is casted into wide integer to
13776 Opnds.push_back(N->getOperand(0));
13777 Opnds.push_back(N->getOperand(1));
13779 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13780 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13781 // BFS traverse all OR'd operands.
13782 if (I->getOpcode() == ISD::OR) {
13783 Opnds.push_back(I->getOperand(0));
13784 Opnds.push_back(I->getOperand(1));
13785 // Re-evaluate the number of nodes to be traversed.
13786 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13790 // Quit if a non-EXTRACT_VECTOR_ELT
13791 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13794 // Quit if without a constant index.
13795 SDValue Idx = I->getOperand(1);
13796 if (!isa<ConstantSDNode>(Idx))
13799 SDValue ExtractedFromVec = I->getOperand(0);
13800 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13801 if (M == VecInMap.end()) {
13802 VT = ExtractedFromVec.getValueType();
13803 // Quit if not 128/256-bit vector.
13804 if (!VT.is128BitVector() && !VT.is256BitVector())
13806 // Quit if not the same type.
13807 if (VecInMap.begin() != VecInMap.end() &&
13808 VT != VecInMap.begin()->first.getValueType())
13810 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13811 VecIns.push_back(ExtractedFromVec);
13813 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13816 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13817 "Not extracted from 128-/256-bit vector.");
13819 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13821 for (DenseMap<SDValue, unsigned>::const_iterator
13822 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13823 // Quit if not all elements are used.
13824 if (I->second != FullMask)
13828 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13830 // Cast all vectors into TestVT for PTEST.
13831 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13832 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13834 // If more than one full vectors are evaluated, OR them first before PTEST.
13835 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13836 // Each iteration will OR 2 nodes and append the result until there is only
13837 // 1 node left, i.e. the final OR'd value of all vectors.
13838 SDValue LHS = VecIns[Slot];
13839 SDValue RHS = VecIns[Slot + 1];
13840 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13843 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13844 VecIns.back(), VecIns.back());
13847 /// \brief return true if \c Op has a use that doesn't just read flags.
13848 static bool hasNonFlagsUse(SDValue Op) {
13849 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13851 SDNode *User = *UI;
13852 unsigned UOpNo = UI.getOperandNo();
13853 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13854 // Look pass truncate.
13855 UOpNo = User->use_begin().getOperandNo();
13856 User = *User->use_begin();
13859 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13860 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13866 /// Emit nodes that will be selected as "test Op0,Op0", or something
13868 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13869 SelectionDAG &DAG) const {
13870 if (Op.getValueType() == MVT::i1) {
13871 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13872 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13873 DAG.getConstant(0, dl, MVT::i8));
13875 // CF and OF aren't always set the way we want. Determine which
13876 // of these we need.
13877 bool NeedCF = false;
13878 bool NeedOF = false;
13881 case X86::COND_A: case X86::COND_AE:
13882 case X86::COND_B: case X86::COND_BE:
13885 case X86::COND_G: case X86::COND_GE:
13886 case X86::COND_L: case X86::COND_LE:
13887 case X86::COND_O: case X86::COND_NO: {
13888 // Check if we really need to set the
13889 // Overflow flag. If NoSignedWrap is present
13890 // that is not actually needed.
13891 switch (Op->getOpcode()) {
13896 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13897 if (BinNode->Flags.hasNoSignedWrap())
13907 // See if we can use the EFLAGS value from the operand instead of
13908 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13909 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13910 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13911 // Emit a CMP with 0, which is the TEST pattern.
13912 //if (Op.getValueType() == MVT::i1)
13913 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13914 // DAG.getConstant(0, MVT::i1));
13915 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13916 DAG.getConstant(0, dl, Op.getValueType()));
13918 unsigned Opcode = 0;
13919 unsigned NumOperands = 0;
13921 // Truncate operations may prevent the merge of the SETCC instruction
13922 // and the arithmetic instruction before it. Attempt to truncate the operands
13923 // of the arithmetic instruction and use a reduced bit-width instruction.
13924 bool NeedTruncation = false;
13925 SDValue ArithOp = Op;
13926 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13927 SDValue Arith = Op->getOperand(0);
13928 // Both the trunc and the arithmetic op need to have one user each.
13929 if (Arith->hasOneUse())
13930 switch (Arith.getOpcode()) {
13937 NeedTruncation = true;
13943 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13944 // which may be the result of a CAST. We use the variable 'Op', which is the
13945 // non-casted variable when we check for possible users.
13946 switch (ArithOp.getOpcode()) {
13948 // Due to an isel shortcoming, be conservative if this add is likely to be
13949 // selected as part of a load-modify-store instruction. When the root node
13950 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13951 // uses of other nodes in the match, such as the ADD in this case. This
13952 // leads to the ADD being left around and reselected, with the result being
13953 // two adds in the output. Alas, even if none our users are stores, that
13954 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13955 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13956 // climbing the DAG back to the root, and it doesn't seem to be worth the
13958 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13959 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13960 if (UI->getOpcode() != ISD::CopyToReg &&
13961 UI->getOpcode() != ISD::SETCC &&
13962 UI->getOpcode() != ISD::STORE)
13965 if (ConstantSDNode *C =
13966 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13967 // An add of one will be selected as an INC.
13968 if (C->isOne() && !Subtarget->slowIncDec()) {
13969 Opcode = X86ISD::INC;
13974 // An add of negative one (subtract of one) will be selected as a DEC.
13975 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
13976 Opcode = X86ISD::DEC;
13982 // Otherwise use a regular EFLAGS-setting add.
13983 Opcode = X86ISD::ADD;
13988 // If we have a constant logical shift that's only used in a comparison
13989 // against zero turn it into an equivalent AND. This allows turning it into
13990 // a TEST instruction later.
13991 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13992 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13993 EVT VT = Op.getValueType();
13994 unsigned BitWidth = VT.getSizeInBits();
13995 unsigned ShAmt = Op->getConstantOperandVal(1);
13996 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13998 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13999 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14000 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14001 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14003 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14004 DAG.getConstant(Mask, dl, VT));
14005 DAG.ReplaceAllUsesWith(Op, New);
14011 // If the primary and result isn't used, don't bother using X86ISD::AND,
14012 // because a TEST instruction will be better.
14013 if (!hasNonFlagsUse(Op))
14019 // Due to the ISEL shortcoming noted above, be conservative if this op is
14020 // likely to be selected as part of a load-modify-store instruction.
14021 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14022 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14023 if (UI->getOpcode() == ISD::STORE)
14026 // Otherwise use a regular EFLAGS-setting instruction.
14027 switch (ArithOp.getOpcode()) {
14028 default: llvm_unreachable("unexpected operator!");
14029 case ISD::SUB: Opcode = X86ISD::SUB; break;
14030 case ISD::XOR: Opcode = X86ISD::XOR; break;
14031 case ISD::AND: Opcode = X86ISD::AND; break;
14033 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14034 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14035 if (EFLAGS.getNode())
14038 Opcode = X86ISD::OR;
14052 return SDValue(Op.getNode(), 1);
14058 // If we found that truncation is beneficial, perform the truncation and
14060 if (NeedTruncation) {
14061 EVT VT = Op.getValueType();
14062 SDValue WideVal = Op->getOperand(0);
14063 EVT WideVT = WideVal.getValueType();
14064 unsigned ConvertedOp = 0;
14065 // Use a target machine opcode to prevent further DAGCombine
14066 // optimizations that may separate the arithmetic operations
14067 // from the setcc node.
14068 switch (WideVal.getOpcode()) {
14070 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14071 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14072 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14073 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14074 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14079 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14080 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14081 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14082 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14088 // Emit a CMP with 0, which is the TEST pattern.
14089 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14090 DAG.getConstant(0, dl, Op.getValueType()));
14092 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14093 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
14095 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14096 DAG.ReplaceAllUsesWith(Op, New);
14097 return SDValue(New.getNode(), 1);
14100 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14102 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14103 SDLoc dl, SelectionDAG &DAG) const {
14104 if (isNullConstant(Op1))
14105 return EmitTest(Op0, X86CC, dl, DAG);
14107 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
14108 "Unexpected comparison operation for MVT::i1 operands");
14110 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14111 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14112 // Do the comparison at i32 if it's smaller, besides the Atom case.
14113 // This avoids subregister aliasing issues. Keep the smaller reference
14114 // if we're optimizing for size, however, as that'll allow better folding
14115 // of memory operations.
14116 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14117 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
14118 !Subtarget->isAtom()) {
14119 unsigned ExtendOp =
14120 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14121 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14122 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14124 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14125 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14126 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14128 return SDValue(Sub.getNode(), 1);
14130 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14133 /// Convert a comparison if required by the subtarget.
14134 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14135 SelectionDAG &DAG) const {
14136 // If the subtarget does not support the FUCOMI instruction, floating-point
14137 // comparisons have to be converted.
14138 if (Subtarget->hasCMov() ||
14139 Cmp.getOpcode() != X86ISD::CMP ||
14140 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14141 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14144 // The instruction selector will select an FUCOM instruction instead of
14145 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14146 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14147 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14149 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14150 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14151 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14152 DAG.getConstant(8, dl, MVT::i8));
14153 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14155 // Some 64-bit targets lack SAHF support, but they do support FCOMI.
14156 assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
14157 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14160 /// The minimum architected relative accuracy is 2^-12. We need one
14161 /// Newton-Raphson step to have a good float result (24 bits of precision).
14162 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14163 DAGCombinerInfo &DCI,
14164 unsigned &RefinementSteps,
14165 bool &UseOneConstNR) const {
14166 EVT VT = Op.getValueType();
14167 const char *RecipOp;
14169 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
14170 // TODO: Add support for AVX512 (v16f32).
14171 // It is likely not profitable to do this for f64 because a double-precision
14172 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14173 // instructions: convert to single, rsqrtss, convert back to double, refine
14174 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14175 // along with FMA, this could be a throughput win.
14176 if (VT == MVT::f32 && Subtarget->hasSSE1())
14178 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14179 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14180 RecipOp = "vec-sqrtf";
14184 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14185 if (!Recips.isEnabled(RecipOp))
14188 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14189 UseOneConstNR = false;
14190 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14193 /// The minimum architected relative accuracy is 2^-12. We need one
14194 /// Newton-Raphson step to have a good float result (24 bits of precision).
14195 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14196 DAGCombinerInfo &DCI,
14197 unsigned &RefinementSteps) const {
14198 EVT VT = Op.getValueType();
14199 const char *RecipOp;
14201 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14202 // TODO: Add support for AVX512 (v16f32).
14203 // It is likely not profitable to do this for f64 because a double-precision
14204 // reciprocal estimate with refinement on x86 prior to FMA requires
14205 // 15 instructions: convert to single, rcpss, convert back to double, refine
14206 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14207 // along with FMA, this could be a throughput win.
14208 if (VT == MVT::f32 && Subtarget->hasSSE1())
14210 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14211 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14212 RecipOp = "vec-divf";
14216 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14217 if (!Recips.isEnabled(RecipOp))
14220 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14221 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14224 /// If we have at least two divisions that use the same divisor, convert to
14225 /// multplication by a reciprocal. This may need to be adjusted for a given
14226 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14227 /// This is because we still need one division to calculate the reciprocal and
14228 /// then we need two multiplies by that reciprocal as replacements for the
14229 /// original divisions.
14230 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14234 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14235 /// if it's possible.
14236 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14237 SDLoc dl, SelectionDAG &DAG) const {
14238 SDValue Op0 = And.getOperand(0);
14239 SDValue Op1 = And.getOperand(1);
14240 if (Op0.getOpcode() == ISD::TRUNCATE)
14241 Op0 = Op0.getOperand(0);
14242 if (Op1.getOpcode() == ISD::TRUNCATE)
14243 Op1 = Op1.getOperand(0);
14246 if (Op1.getOpcode() == ISD::SHL)
14247 std::swap(Op0, Op1);
14248 if (Op0.getOpcode() == ISD::SHL) {
14249 if (isOneConstant(Op0.getOperand(0))) {
14250 // If we looked past a truncate, check that it's only truncating away
14252 unsigned BitWidth = Op0.getValueSizeInBits();
14253 unsigned AndBitWidth = And.getValueSizeInBits();
14254 if (BitWidth > AndBitWidth) {
14256 DAG.computeKnownBits(Op0, Zeros, Ones);
14257 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14261 RHS = Op0.getOperand(1);
14263 } else if (Op1.getOpcode() == ISD::Constant) {
14264 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14265 uint64_t AndRHSVal = AndRHS->getZExtValue();
14266 SDValue AndLHS = Op0;
14268 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14269 LHS = AndLHS.getOperand(0);
14270 RHS = AndLHS.getOperand(1);
14273 // Use BT if the immediate can't be encoded in a TEST instruction.
14274 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14276 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14280 if (LHS.getNode()) {
14281 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14282 // instruction. Since the shift amount is in-range-or-undefined, we know
14283 // that doing a bittest on the i32 value is ok. We extend to i32 because
14284 // the encoding for the i16 version is larger than the i32 version.
14285 // Also promote i16 to i32 for performance / code size reason.
14286 if (LHS.getValueType() == MVT::i8 ||
14287 LHS.getValueType() == MVT::i16)
14288 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14290 // If the operand types disagree, extend the shift amount to match. Since
14291 // BT ignores high bits (like shifts) we can use anyextend.
14292 if (LHS.getValueType() != RHS.getValueType())
14293 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14295 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14296 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14297 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14298 DAG.getConstant(Cond, dl, MVT::i8), BT);
14304 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14306 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14311 // SSE Condition code mapping:
14320 switch (SetCCOpcode) {
14321 default: llvm_unreachable("Unexpected SETCC condition");
14323 case ISD::SETEQ: SSECC = 0; break;
14325 case ISD::SETGT: Swap = true; // Fallthrough
14327 case ISD::SETOLT: SSECC = 1; break;
14329 case ISD::SETGE: Swap = true; // Fallthrough
14331 case ISD::SETOLE: SSECC = 2; break;
14332 case ISD::SETUO: SSECC = 3; break;
14334 case ISD::SETNE: SSECC = 4; break;
14335 case ISD::SETULE: Swap = true; // Fallthrough
14336 case ISD::SETUGE: SSECC = 5; break;
14337 case ISD::SETULT: Swap = true; // Fallthrough
14338 case ISD::SETUGT: SSECC = 6; break;
14339 case ISD::SETO: SSECC = 7; break;
14341 case ISD::SETONE: SSECC = 8; break;
14344 std::swap(Op0, Op1);
14349 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14350 // ones, and then concatenate the result back.
14351 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14352 MVT VT = Op.getSimpleValueType();
14354 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14355 "Unsupported value type for operation");
14357 unsigned NumElems = VT.getVectorNumElements();
14359 SDValue CC = Op.getOperand(2);
14361 // Extract the LHS vectors
14362 SDValue LHS = Op.getOperand(0);
14363 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14364 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14366 // Extract the RHS vectors
14367 SDValue RHS = Op.getOperand(1);
14368 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14369 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14371 // Issue the operation on the smaller types and concatenate the result back
14372 MVT EltVT = VT.getVectorElementType();
14373 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14374 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14375 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14376 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14379 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14380 SDValue Op0 = Op.getOperand(0);
14381 SDValue Op1 = Op.getOperand(1);
14382 SDValue CC = Op.getOperand(2);
14383 MVT VT = Op.getSimpleValueType();
14386 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14387 "Unexpected type for boolean compare operation");
14388 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14389 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14390 DAG.getConstant(-1, dl, VT));
14391 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14392 DAG.getConstant(-1, dl, VT));
14393 switch (SetCCOpcode) {
14394 default: llvm_unreachable("Unexpected SETCC condition");
14396 // (x == y) -> ~(x ^ y)
14397 return DAG.getNode(ISD::XOR, dl, VT,
14398 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14399 DAG.getConstant(-1, dl, VT));
14401 // (x != y) -> (x ^ y)
14402 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14405 // (x > y) -> (x & ~y)
14406 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14409 // (x < y) -> (~x & y)
14410 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14413 // (x <= y) -> (~x | y)
14414 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14417 // (x >=y) -> (x | ~y)
14418 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14422 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14423 const X86Subtarget *Subtarget) {
14424 SDValue Op0 = Op.getOperand(0);
14425 SDValue Op1 = Op.getOperand(1);
14426 SDValue CC = Op.getOperand(2);
14427 MVT VT = Op.getSimpleValueType();
14430 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14431 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14432 "Cannot set masked compare for this operation");
14434 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14436 bool Unsigned = false;
14439 switch (SetCCOpcode) {
14440 default: llvm_unreachable("Unexpected SETCC condition");
14441 case ISD::SETNE: SSECC = 4; break;
14442 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14443 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14444 case ISD::SETLT: Swap = true; //fall-through
14445 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14446 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14447 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14448 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14449 case ISD::SETULE: Unsigned = true; //fall-through
14450 case ISD::SETLE: SSECC = 2; break;
14454 std::swap(Op0, Op1);
14456 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14457 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14458 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14459 DAG.getConstant(SSECC, dl, MVT::i8));
14462 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14463 /// operand \p Op1. If non-trivial (for example because it's not constant)
14464 /// return an empty value.
14465 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14467 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14471 MVT VT = Op1.getSimpleValueType();
14472 MVT EVT = VT.getVectorElementType();
14473 unsigned n = VT.getVectorNumElements();
14474 SmallVector<SDValue, 8> ULTOp1;
14476 for (unsigned i = 0; i < n; ++i) {
14477 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14478 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14481 // Avoid underflow.
14482 APInt Val = Elt->getAPIntValue();
14486 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14489 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14492 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14493 SelectionDAG &DAG) {
14494 SDValue Op0 = Op.getOperand(0);
14495 SDValue Op1 = Op.getOperand(1);
14496 SDValue CC = Op.getOperand(2);
14497 MVT VT = Op.getSimpleValueType();
14498 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14499 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14504 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14505 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14508 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14509 unsigned Opc = X86ISD::CMPP;
14510 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14511 assert(VT.getVectorNumElements() <= 16);
14512 Opc = X86ISD::CMPM;
14514 // In the two special cases we can't handle, emit two comparisons.
14517 unsigned CombineOpc;
14518 if (SetCCOpcode == ISD::SETUEQ) {
14519 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14521 assert(SetCCOpcode == ISD::SETONE);
14522 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14525 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14526 DAG.getConstant(CC0, dl, MVT::i8));
14527 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14528 DAG.getConstant(CC1, dl, MVT::i8));
14529 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14531 // Handle all other FP comparisons here.
14532 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14533 DAG.getConstant(SSECC, dl, MVT::i8));
14536 MVT VTOp0 = Op0.getSimpleValueType();
14537 assert(VTOp0 == Op1.getSimpleValueType() &&
14538 "Expected operands with same type!");
14539 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14540 "Invalid number of packed elements for source and destination!");
14542 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14543 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14544 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14545 // legalizer firstly checks if the first operand in input to the setcc has
14546 // a legal type. If so, then it promotes the return type to that same type.
14547 // Otherwise, the return type is promoted to the 'next legal type' which,
14548 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14550 // We reach this code only if the following two conditions are met:
14551 // 1. Both return type and operand type have been promoted to wider types
14552 // by the type legalizer.
14553 // 2. The original operand type has been promoted to a 256-bit vector.
14555 // Note that condition 2. only applies for AVX targets.
14556 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14557 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14560 // The non-AVX512 code below works under the assumption that source and
14561 // destination types are the same.
14562 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14563 "Value types for source and destination must be the same!");
14565 // Break 256-bit integer vector compare into smaller ones.
14566 if (VT.is256BitVector() && !Subtarget->hasInt256())
14567 return Lower256IntVSETCC(Op, DAG);
14569 MVT OpVT = Op1.getSimpleValueType();
14570 if (OpVT.getVectorElementType() == MVT::i1)
14571 return LowerBoolVSETCC_AVX512(Op, DAG);
14573 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14574 if (Subtarget->hasAVX512()) {
14575 if (Op1.getSimpleValueType().is512BitVector() ||
14576 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14577 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14578 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14580 // In AVX-512 architecture setcc returns mask with i1 elements,
14581 // But there is no compare instruction for i8 and i16 elements in KNL.
14582 // We are not talking about 512-bit operands in this case, these
14583 // types are illegal.
14585 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14586 OpVT.getVectorElementType().getSizeInBits() >= 8))
14587 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14588 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14591 // Lower using XOP integer comparisons.
14592 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14593 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14594 // Translate compare code to XOP PCOM compare mode.
14595 unsigned CmpMode = 0;
14596 switch (SetCCOpcode) {
14597 default: llvm_unreachable("Unexpected SETCC condition");
14599 case ISD::SETLT: CmpMode = 0x00; break;
14601 case ISD::SETLE: CmpMode = 0x01; break;
14603 case ISD::SETGT: CmpMode = 0x02; break;
14605 case ISD::SETGE: CmpMode = 0x03; break;
14606 case ISD::SETEQ: CmpMode = 0x04; break;
14607 case ISD::SETNE: CmpMode = 0x05; break;
14610 // Are we comparing unsigned or signed integers?
14611 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14612 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14614 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14615 DAG.getConstant(CmpMode, dl, MVT::i8));
14618 // We are handling one of the integer comparisons here. Since SSE only has
14619 // GT and EQ comparisons for integer, swapping operands and multiple
14620 // operations may be required for some comparisons.
14622 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14623 bool Subus = false;
14625 switch (SetCCOpcode) {
14626 default: llvm_unreachable("Unexpected SETCC condition");
14627 case ISD::SETNE: Invert = true;
14628 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14629 case ISD::SETLT: Swap = true;
14630 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14631 case ISD::SETGE: Swap = true;
14632 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14633 Invert = true; break;
14634 case ISD::SETULT: Swap = true;
14635 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14636 FlipSigns = true; break;
14637 case ISD::SETUGE: Swap = true;
14638 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14639 FlipSigns = true; Invert = true; break;
14642 // Special case: Use min/max operations for SETULE/SETUGE
14643 MVT VET = VT.getVectorElementType();
14645 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14646 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14649 switch (SetCCOpcode) {
14651 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14652 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14655 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14658 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14659 if (!MinMax && hasSubus) {
14660 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14662 // t = psubus Op0, Op1
14663 // pcmpeq t, <0..0>
14664 switch (SetCCOpcode) {
14666 case ISD::SETULT: {
14667 // If the comparison is against a constant we can turn this into a
14668 // setule. With psubus, setule does not require a swap. This is
14669 // beneficial because the constant in the register is no longer
14670 // destructed as the destination so it can be hoisted out of a loop.
14671 // Only do this pre-AVX since vpcmp* is no longer destructive.
14672 if (Subtarget->hasAVX())
14674 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14675 if (ULEOp1.getNode()) {
14677 Subus = true; Invert = false; Swap = false;
14681 // Psubus is better than flip-sign because it requires no inversion.
14682 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14683 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14687 Opc = X86ISD::SUBUS;
14693 std::swap(Op0, Op1);
14695 // Check that the operation in question is available (most are plain SSE2,
14696 // but PCMPGTQ and PCMPEQQ have different requirements).
14697 if (VT == MVT::v2i64) {
14698 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14699 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14701 // First cast everything to the right type.
14702 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14703 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14705 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14706 // bits of the inputs before performing those operations. The lower
14707 // compare is always unsigned.
14710 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14712 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14713 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14714 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14715 Sign, Zero, Sign, Zero);
14717 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14718 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14720 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14721 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14722 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14724 // Create masks for only the low parts/high parts of the 64 bit integers.
14725 static const int MaskHi[] = { 1, 1, 3, 3 };
14726 static const int MaskLo[] = { 0, 0, 2, 2 };
14727 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14728 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14729 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14731 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14732 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14735 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14737 return DAG.getBitcast(VT, Result);
14740 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14741 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14742 // pcmpeqd + pshufd + pand.
14743 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14745 // First cast everything to the right type.
14746 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14747 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14750 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14752 // Make sure the lower and upper halves are both all-ones.
14753 static const int Mask[] = { 1, 0, 3, 2 };
14754 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14755 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14758 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14760 return DAG.getBitcast(VT, Result);
14764 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14765 // bits of the inputs before performing those operations.
14767 MVT EltVT = VT.getVectorElementType();
14768 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14770 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14771 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14774 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14776 // If the logical-not of the result is required, perform that now.
14778 Result = DAG.getNOT(dl, Result, VT);
14781 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14784 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14785 getZeroVector(VT, Subtarget, DAG, dl));
14790 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14792 MVT VT = Op.getSimpleValueType();
14794 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14796 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14797 && "SetCC type must be 8-bit or 1-bit integer");
14798 SDValue Op0 = Op.getOperand(0);
14799 SDValue Op1 = Op.getOperand(1);
14801 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14803 // Optimize to BT if possible.
14804 // Lower (X & (1 << N)) == 0 to BT(X, N).
14805 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14806 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14807 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14808 isNullConstant(Op1) &&
14809 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14810 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14812 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14817 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14819 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14820 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14822 // If the input is a setcc, then reuse the input setcc or use a new one with
14823 // the inverted condition.
14824 if (Op0.getOpcode() == X86ISD::SETCC) {
14825 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14826 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14830 CCode = X86::GetOppositeBranchCondition(CCode);
14831 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14832 DAG.getConstant(CCode, dl, MVT::i8),
14833 Op0.getOperand(1));
14835 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14839 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14840 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14842 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14843 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14846 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14847 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14848 if (X86CC == X86::COND_INVALID)
14851 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14852 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14853 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14854 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14856 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14860 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14861 SDValue LHS = Op.getOperand(0);
14862 SDValue RHS = Op.getOperand(1);
14863 SDValue Carry = Op.getOperand(2);
14864 SDValue Cond = Op.getOperand(3);
14867 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14868 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14870 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14871 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14872 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14873 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14874 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14877 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14878 static bool isX86LogicalCmp(SDValue Op) {
14879 unsigned Opc = Op.getNode()->getOpcode();
14880 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14881 Opc == X86ISD::SAHF)
14883 if (Op.getResNo() == 1 &&
14884 (Opc == X86ISD::ADD ||
14885 Opc == X86ISD::SUB ||
14886 Opc == X86ISD::ADC ||
14887 Opc == X86ISD::SBB ||
14888 Opc == X86ISD::SMUL ||
14889 Opc == X86ISD::UMUL ||
14890 Opc == X86ISD::INC ||
14891 Opc == X86ISD::DEC ||
14892 Opc == X86ISD::OR ||
14893 Opc == X86ISD::XOR ||
14894 Opc == X86ISD::AND))
14897 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14903 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14904 if (V.getOpcode() != ISD::TRUNCATE)
14907 SDValue VOp0 = V.getOperand(0);
14908 unsigned InBits = VOp0.getValueSizeInBits();
14909 unsigned Bits = V.getValueSizeInBits();
14910 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14913 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14914 bool addTest = true;
14915 SDValue Cond = Op.getOperand(0);
14916 SDValue Op1 = Op.getOperand(1);
14917 SDValue Op2 = Op.getOperand(2);
14919 MVT VT = Op1.getSimpleValueType();
14922 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14923 // are available or VBLENDV if AVX is available.
14924 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14925 if (Cond.getOpcode() == ISD::SETCC &&
14926 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14927 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14928 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14929 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14930 int SSECC = translateX86FSETCC(
14931 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14934 if (Subtarget->hasAVX512()) {
14935 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14936 DAG.getConstant(SSECC, DL, MVT::i8));
14937 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14940 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14941 DAG.getConstant(SSECC, DL, MVT::i8));
14943 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14944 // of 3 logic instructions for size savings and potentially speed.
14945 // Unfortunately, there is no scalar form of VBLENDV.
14947 // If either operand is a constant, don't try this. We can expect to
14948 // optimize away at least one of the logic instructions later in that
14949 // case, so that sequence would be faster than a variable blend.
14951 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14952 // uses XMM0 as the selection register. That may need just as many
14953 // instructions as the AND/ANDN/OR sequence due to register moves, so
14956 if (Subtarget->hasAVX() &&
14957 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14959 // Convert to vectors, do a VSELECT, and convert back to scalar.
14960 // All of the conversions should be optimized away.
14962 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14963 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14964 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14965 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14967 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14968 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14970 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14972 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14973 VSel, DAG.getIntPtrConstant(0, DL));
14975 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14976 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14977 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14981 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14983 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14984 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14985 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14986 Op1Scalar = Op1.getOperand(0);
14988 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14989 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14990 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14991 Op2Scalar = Op2.getOperand(0);
14992 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14993 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14994 Op1Scalar.getValueType(),
14995 Cond, Op1Scalar, Op2Scalar);
14996 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14997 return DAG.getBitcast(VT, newSelect);
14998 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14999 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
15000 DAG.getIntPtrConstant(0, DL));
15004 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
15005 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
15006 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
15007 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
15008 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
15009 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
15010 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
15012 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
15015 if (Cond.getOpcode() == ISD::SETCC) {
15016 SDValue NewCond = LowerSETCC(Cond, DAG);
15017 if (NewCond.getNode())
15021 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15022 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15023 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15024 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15025 if (Cond.getOpcode() == X86ISD::SETCC &&
15026 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15027 isNullConstant(Cond.getOperand(1).getOperand(1))) {
15028 SDValue Cmp = Cond.getOperand(1);
15030 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15032 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
15033 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15034 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
15036 SDValue CmpOp0 = Cmp.getOperand(0);
15037 // Apply further optimizations for special cases
15038 // (select (x != 0), -1, 0) -> neg & sbb
15039 // (select (x == 0), 0, -1) -> neg & sbb
15040 if (isNullConstant(Y) &&
15041 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
15042 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15043 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15044 DAG.getConstant(0, DL,
15045 CmpOp0.getValueType()),
15047 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15048 DAG.getConstant(X86::COND_B, DL, MVT::i8),
15049 SDValue(Neg.getNode(), 1));
15053 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15054 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
15055 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15057 SDValue Res = // Res = 0 or -1.
15058 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15059 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
15061 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
15062 Res = DAG.getNOT(DL, Res, Res.getValueType());
15064 if (!isNullConstant(Op2))
15065 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15070 // Look past (and (setcc_carry (cmp ...)), 1).
15071 if (Cond.getOpcode() == ISD::AND &&
15072 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15073 isOneConstant(Cond.getOperand(1)))
15074 Cond = Cond.getOperand(0);
15076 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15077 // setting operand in place of the X86ISD::SETCC.
15078 unsigned CondOpcode = Cond.getOpcode();
15079 if (CondOpcode == X86ISD::SETCC ||
15080 CondOpcode == X86ISD::SETCC_CARRY) {
15081 CC = Cond.getOperand(0);
15083 SDValue Cmp = Cond.getOperand(1);
15084 unsigned Opc = Cmp.getOpcode();
15085 MVT VT = Op.getSimpleValueType();
15087 bool IllegalFPCMov = false;
15088 if (VT.isFloatingPoint() && !VT.isVector() &&
15089 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15090 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15092 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15093 Opc == X86ISD::BT) { // FIXME
15097 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15098 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15099 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15100 Cond.getOperand(0).getValueType() != MVT::i8)) {
15101 SDValue LHS = Cond.getOperand(0);
15102 SDValue RHS = Cond.getOperand(1);
15103 unsigned X86Opcode;
15106 switch (CondOpcode) {
15107 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15108 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15109 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15110 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15111 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15112 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15113 default: llvm_unreachable("unexpected overflowing operator");
15115 if (CondOpcode == ISD::UMULO)
15116 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15119 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15121 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15123 if (CondOpcode == ISD::UMULO)
15124 Cond = X86Op.getValue(2);
15126 Cond = X86Op.getValue(1);
15128 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
15133 // Look past the truncate if the high bits are known zero.
15134 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15135 Cond = Cond.getOperand(0);
15137 // We know the result of AND is compared against zero. Try to match
15139 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15140 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
15141 CC = NewSetCC.getOperand(0);
15142 Cond = NewSetCC.getOperand(1);
15149 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
15150 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15153 // a < b ? -1 : 0 -> RES = ~setcc_carry
15154 // a < b ? 0 : -1 -> RES = setcc_carry
15155 // a >= b ? -1 : 0 -> RES = setcc_carry
15156 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15157 if (Cond.getOpcode() == X86ISD::SUB) {
15158 Cond = ConvertCmpIfNecessary(Cond, DAG);
15159 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15161 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15162 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
15163 (isNullConstant(Op1) || isNullConstant(Op2))) {
15164 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15165 DAG.getConstant(X86::COND_B, DL, MVT::i8),
15167 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
15168 return DAG.getNOT(DL, Res, Res.getValueType());
15173 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15174 // widen the cmov and push the truncate through. This avoids introducing a new
15175 // branch during isel and doesn't add any extensions.
15176 if (Op.getValueType() == MVT::i8 &&
15177 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15178 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15179 if (T1.getValueType() == T2.getValueType() &&
15180 // Blacklist CopyFromReg to avoid partial register stalls.
15181 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15182 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15183 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15184 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15188 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15189 // condition is true.
15190 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15191 SDValue Ops[] = { Op2, Op1, CC, Cond };
15192 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15195 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15196 const X86Subtarget *Subtarget,
15197 SelectionDAG &DAG) {
15198 MVT VT = Op->getSimpleValueType(0);
15199 SDValue In = Op->getOperand(0);
15200 MVT InVT = In.getSimpleValueType();
15201 MVT VTElt = VT.getVectorElementType();
15202 MVT InVTElt = InVT.getVectorElementType();
15206 if ((InVTElt == MVT::i1) &&
15207 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15208 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15210 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15211 VTElt.getSizeInBits() <= 16)) ||
15213 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15214 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15216 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15217 VTElt.getSizeInBits() >= 32))))
15218 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15220 unsigned int NumElts = VT.getVectorNumElements();
15222 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15225 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15226 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15227 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15228 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15231 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15232 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15234 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15237 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15239 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15240 if (VT.is512BitVector())
15242 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15245 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15246 const X86Subtarget *Subtarget,
15247 SelectionDAG &DAG) {
15248 SDValue In = Op->getOperand(0);
15249 MVT VT = Op->getSimpleValueType(0);
15250 MVT InVT = In.getSimpleValueType();
15251 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15253 MVT InSVT = InVT.getVectorElementType();
15254 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15256 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15258 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15263 // SSE41 targets can use the pmovsx* instructions directly.
15264 if (Subtarget->hasSSE41())
15265 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15267 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15271 // As SRAI is only available on i16/i32 types, we expand only up to i32
15272 // and handle i64 separately.
15273 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15274 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15275 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15276 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15277 Curr = DAG.getBitcast(CurrVT, Curr);
15280 SDValue SignExt = Curr;
15281 if (CurrVT != InVT) {
15282 unsigned SignExtShift =
15283 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15284 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15285 DAG.getConstant(SignExtShift, dl, MVT::i8));
15291 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15292 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15293 DAG.getConstant(31, dl, MVT::i8));
15294 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15295 return DAG.getBitcast(VT, Ext);
15301 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15302 SelectionDAG &DAG) {
15303 MVT VT = Op->getSimpleValueType(0);
15304 SDValue In = Op->getOperand(0);
15305 MVT InVT = In.getSimpleValueType();
15308 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15309 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15311 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15312 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15313 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15316 if (Subtarget->hasInt256())
15317 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15319 // Optimize vectors in AVX mode
15320 // Sign extend v8i16 to v8i32 and
15323 // Divide input vector into two parts
15324 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15325 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15326 // concat the vectors to original VT
15328 unsigned NumElems = InVT.getVectorNumElements();
15329 SDValue Undef = DAG.getUNDEF(InVT);
15331 SmallVector<int,8> ShufMask1(NumElems, -1);
15332 for (unsigned i = 0; i != NumElems/2; ++i)
15335 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15337 SmallVector<int,8> ShufMask2(NumElems, -1);
15338 for (unsigned i = 0; i != NumElems/2; ++i)
15339 ShufMask2[i] = i + NumElems/2;
15341 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15343 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15344 VT.getVectorNumElements()/2);
15346 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15347 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15349 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15352 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15353 // may emit an illegal shuffle but the expansion is still better than scalar
15354 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15355 // we'll emit a shuffle and a arithmetic shift.
15356 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15357 // TODO: It is possible to support ZExt by zeroing the undef values during
15358 // the shuffle phase or after the shuffle.
15359 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15360 SelectionDAG &DAG) {
15361 MVT RegVT = Op.getSimpleValueType();
15362 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15363 assert(RegVT.isInteger() &&
15364 "We only custom lower integer vector sext loads.");
15366 // Nothing useful we can do without SSE2 shuffles.
15367 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15369 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15371 EVT MemVT = Ld->getMemoryVT();
15372 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15373 unsigned RegSz = RegVT.getSizeInBits();
15375 ISD::LoadExtType Ext = Ld->getExtensionType();
15377 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15378 && "Only anyext and sext are currently implemented.");
15379 assert(MemVT != RegVT && "Cannot extend to the same type");
15380 assert(MemVT.isVector() && "Must load a vector from memory");
15382 unsigned NumElems = RegVT.getVectorNumElements();
15383 unsigned MemSz = MemVT.getSizeInBits();
15384 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15386 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15387 // The only way in which we have a legal 256-bit vector result but not the
15388 // integer 256-bit operations needed to directly lower a sextload is if we
15389 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15390 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15391 // correctly legalized. We do this late to allow the canonical form of
15392 // sextload to persist throughout the rest of the DAG combiner -- it wants
15393 // to fold together any extensions it can, and so will fuse a sign_extend
15394 // of an sextload into a sextload targeting a wider value.
15396 if (MemSz == 128) {
15397 // Just switch this to a normal load.
15398 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15399 "it must be a legal 128-bit vector "
15401 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15402 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15403 Ld->isInvariant(), Ld->getAlignment());
15405 assert(MemSz < 128 &&
15406 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15407 // Do an sext load to a 128-bit vector type. We want to use the same
15408 // number of elements, but elements half as wide. This will end up being
15409 // recursively lowered by this routine, but will succeed as we definitely
15410 // have all the necessary features if we're using AVX1.
15412 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15413 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15415 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15416 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15417 Ld->isNonTemporal(), Ld->isInvariant(),
15418 Ld->getAlignment());
15421 // Replace chain users with the new chain.
15422 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15423 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15425 // Finally, do a normal sign-extend to the desired register.
15426 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15429 // All sizes must be a power of two.
15430 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15431 "Non-power-of-two elements are not custom lowered!");
15433 // Attempt to load the original value using scalar loads.
15434 // Find the largest scalar type that divides the total loaded size.
15435 MVT SclrLoadTy = MVT::i8;
15436 for (MVT Tp : MVT::integer_valuetypes()) {
15437 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15442 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15443 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15445 SclrLoadTy = MVT::f64;
15447 // Calculate the number of scalar loads that we need to perform
15448 // in order to load our vector from memory.
15449 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15451 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15452 "Can only lower sext loads with a single scalar load!");
15454 unsigned loadRegZize = RegSz;
15455 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15458 // Represent our vector as a sequence of elements which are the
15459 // largest scalar that we can load.
15460 EVT LoadUnitVecVT = EVT::getVectorVT(
15461 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15463 // Represent the data using the same element type that is stored in
15464 // memory. In practice, we ''widen'' MemVT.
15466 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15467 loadRegZize / MemVT.getScalarSizeInBits());
15469 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15470 "Invalid vector type");
15472 // We can't shuffle using an illegal type.
15473 assert(TLI.isTypeLegal(WideVecVT) &&
15474 "We only lower types that form legal widened vector types");
15476 SmallVector<SDValue, 8> Chains;
15477 SDValue Ptr = Ld->getBasePtr();
15478 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15479 TLI.getPointerTy(DAG.getDataLayout()));
15480 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15482 for (unsigned i = 0; i < NumLoads; ++i) {
15483 // Perform a single load.
15484 SDValue ScalarLoad =
15485 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15486 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15487 Ld->getAlignment());
15488 Chains.push_back(ScalarLoad.getValue(1));
15489 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15490 // another round of DAGCombining.
15492 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15494 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15495 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15497 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15500 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15502 // Bitcast the loaded value to a vector of the original element type, in
15503 // the size of the target vector type.
15504 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15505 unsigned SizeRatio = RegSz / MemSz;
15507 if (Ext == ISD::SEXTLOAD) {
15508 // If we have SSE4.1, we can directly emit a VSEXT node.
15509 if (Subtarget->hasSSE41()) {
15510 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15511 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15515 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15517 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15518 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15520 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15521 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15525 // Redistribute the loaded elements into the different locations.
15526 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15527 for (unsigned i = 0; i != NumElems; ++i)
15528 ShuffleVec[i * SizeRatio] = i;
15530 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15531 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15533 // Bitcast to the requested type.
15534 Shuff = DAG.getBitcast(RegVT, Shuff);
15535 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15539 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15540 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15541 // from the AND / OR.
15542 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15543 Opc = Op.getOpcode();
15544 if (Opc != ISD::OR && Opc != ISD::AND)
15546 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15547 Op.getOperand(0).hasOneUse() &&
15548 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15549 Op.getOperand(1).hasOneUse());
15552 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15553 // 1 and that the SETCC node has a single use.
15554 static bool isXor1OfSetCC(SDValue Op) {
15555 if (Op.getOpcode() != ISD::XOR)
15557 if (isOneConstant(Op.getOperand(1)))
15558 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15559 Op.getOperand(0).hasOneUse();
15563 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15564 bool addTest = true;
15565 SDValue Chain = Op.getOperand(0);
15566 SDValue Cond = Op.getOperand(1);
15567 SDValue Dest = Op.getOperand(2);
15570 bool Inverted = false;
15572 if (Cond.getOpcode() == ISD::SETCC) {
15573 // Check for setcc([su]{add,sub,mul}o == 0).
15574 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15575 isNullConstant(Cond.getOperand(1)) &&
15576 Cond.getOperand(0).getResNo() == 1 &&
15577 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15578 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15579 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15580 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15581 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15582 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15584 Cond = Cond.getOperand(0);
15586 SDValue NewCond = LowerSETCC(Cond, DAG);
15587 if (NewCond.getNode())
15592 // FIXME: LowerXALUO doesn't handle these!!
15593 else if (Cond.getOpcode() == X86ISD::ADD ||
15594 Cond.getOpcode() == X86ISD::SUB ||
15595 Cond.getOpcode() == X86ISD::SMUL ||
15596 Cond.getOpcode() == X86ISD::UMUL)
15597 Cond = LowerXALUO(Cond, DAG);
15600 // Look pass (and (setcc_carry (cmp ...)), 1).
15601 if (Cond.getOpcode() == ISD::AND &&
15602 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15603 isOneConstant(Cond.getOperand(1)))
15604 Cond = Cond.getOperand(0);
15606 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15607 // setting operand in place of the X86ISD::SETCC.
15608 unsigned CondOpcode = Cond.getOpcode();
15609 if (CondOpcode == X86ISD::SETCC ||
15610 CondOpcode == X86ISD::SETCC_CARRY) {
15611 CC = Cond.getOperand(0);
15613 SDValue Cmp = Cond.getOperand(1);
15614 unsigned Opc = Cmp.getOpcode();
15615 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15616 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15620 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15624 // These can only come from an arithmetic instruction with overflow,
15625 // e.g. SADDO, UADDO.
15626 Cond = Cond.getNode()->getOperand(1);
15632 CondOpcode = Cond.getOpcode();
15633 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15634 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15635 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15636 Cond.getOperand(0).getValueType() != MVT::i8)) {
15637 SDValue LHS = Cond.getOperand(0);
15638 SDValue RHS = Cond.getOperand(1);
15639 unsigned X86Opcode;
15642 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15643 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15645 switch (CondOpcode) {
15646 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15648 if (isOneConstant(RHS)) {
15649 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15652 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15653 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15655 if (isOneConstant(RHS)) {
15656 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15659 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15660 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15661 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15662 default: llvm_unreachable("unexpected overflowing operator");
15665 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15666 if (CondOpcode == ISD::UMULO)
15667 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15670 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15672 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15674 if (CondOpcode == ISD::UMULO)
15675 Cond = X86Op.getValue(2);
15677 Cond = X86Op.getValue(1);
15679 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15683 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15684 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15685 if (CondOpc == ISD::OR) {
15686 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15687 // two branches instead of an explicit OR instruction with a
15689 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15690 isX86LogicalCmp(Cmp)) {
15691 CC = Cond.getOperand(0).getOperand(0);
15692 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15693 Chain, Dest, CC, Cmp);
15694 CC = Cond.getOperand(1).getOperand(0);
15698 } else { // ISD::AND
15699 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15700 // two branches instead of an explicit AND instruction with a
15701 // separate test. However, we only do this if this block doesn't
15702 // have a fall-through edge, because this requires an explicit
15703 // jmp when the condition is false.
15704 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15705 isX86LogicalCmp(Cmp) &&
15706 Op.getNode()->hasOneUse()) {
15707 X86::CondCode CCode =
15708 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15709 CCode = X86::GetOppositeBranchCondition(CCode);
15710 CC = DAG.getConstant(CCode, dl, MVT::i8);
15711 SDNode *User = *Op.getNode()->use_begin();
15712 // Look for an unconditional branch following this conditional branch.
15713 // We need this because we need to reverse the successors in order
15714 // to implement FCMP_OEQ.
15715 if (User->getOpcode() == ISD::BR) {
15716 SDValue FalseBB = User->getOperand(1);
15718 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15719 assert(NewBR == User);
15723 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15724 Chain, Dest, CC, Cmp);
15725 X86::CondCode CCode =
15726 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15727 CCode = X86::GetOppositeBranchCondition(CCode);
15728 CC = DAG.getConstant(CCode, dl, MVT::i8);
15734 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15735 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15736 // It should be transformed during dag combiner except when the condition
15737 // is set by a arithmetics with overflow node.
15738 X86::CondCode CCode =
15739 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15740 CCode = X86::GetOppositeBranchCondition(CCode);
15741 CC = DAG.getConstant(CCode, dl, MVT::i8);
15742 Cond = Cond.getOperand(0).getOperand(1);
15744 } else if (Cond.getOpcode() == ISD::SETCC &&
15745 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15746 // For FCMP_OEQ, we can emit
15747 // two branches instead of an explicit AND instruction with a
15748 // separate test. However, we only do this if this block doesn't
15749 // have a fall-through edge, because this requires an explicit
15750 // jmp when the condition is false.
15751 if (Op.getNode()->hasOneUse()) {
15752 SDNode *User = *Op.getNode()->use_begin();
15753 // Look for an unconditional branch following this conditional branch.
15754 // We need this because we need to reverse the successors in order
15755 // to implement FCMP_OEQ.
15756 if (User->getOpcode() == ISD::BR) {
15757 SDValue FalseBB = User->getOperand(1);
15759 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15760 assert(NewBR == User);
15764 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15765 Cond.getOperand(0), Cond.getOperand(1));
15766 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15767 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15768 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15769 Chain, Dest, CC, Cmp);
15770 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15775 } else if (Cond.getOpcode() == ISD::SETCC &&
15776 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15777 // For FCMP_UNE, we can emit
15778 // two branches instead of an explicit AND instruction with a
15779 // separate test. However, we only do this if this block doesn't
15780 // have a fall-through edge, because this requires an explicit
15781 // jmp when the condition is false.
15782 if (Op.getNode()->hasOneUse()) {
15783 SDNode *User = *Op.getNode()->use_begin();
15784 // Look for an unconditional branch following this conditional branch.
15785 // We need this because we need to reverse the successors in order
15786 // to implement FCMP_UNE.
15787 if (User->getOpcode() == ISD::BR) {
15788 SDValue FalseBB = User->getOperand(1);
15790 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15791 assert(NewBR == User);
15794 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15795 Cond.getOperand(0), Cond.getOperand(1));
15796 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15797 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15798 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15799 Chain, Dest, CC, Cmp);
15800 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15810 // Look pass the truncate if the high bits are known zero.
15811 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15812 Cond = Cond.getOperand(0);
15814 // We know the result of AND is compared against zero. Try to match
15816 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15817 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15818 CC = NewSetCC.getOperand(0);
15819 Cond = NewSetCC.getOperand(1);
15826 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15827 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15828 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15830 Cond = ConvertCmpIfNecessary(Cond, DAG);
15831 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15832 Chain, Dest, CC, Cond);
15835 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15836 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15837 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15838 // that the guard pages used by the OS virtual memory manager are allocated in
15839 // correct sequence.
15841 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15842 SelectionDAG &DAG) const {
15843 MachineFunction &MF = DAG.getMachineFunction();
15844 bool SplitStack = MF.shouldSplitStack();
15845 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15850 SDNode *Node = Op.getNode();
15851 SDValue Chain = Op.getOperand(0);
15852 SDValue Size = Op.getOperand(1);
15853 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15854 EVT VT = Node->getValueType(0);
15856 // Chain the dynamic stack allocation so that it doesn't modify the stack
15857 // pointer when other instructions are using the stack.
15858 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
15860 bool Is64Bit = Subtarget->is64Bit();
15861 MVT SPTy = getPointerTy(DAG.getDataLayout());
15865 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15866 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15867 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15868 " not tell us which reg is the stack pointer!");
15869 EVT VT = Node->getValueType(0);
15870 SDValue Tmp3 = Node->getOperand(2);
15872 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15873 Chain = SP.getValue(1);
15874 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15875 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15876 unsigned StackAlign = TFI.getStackAlignment();
15877 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15878 if (Align > StackAlign)
15879 Result = DAG.getNode(ISD::AND, dl, VT, Result,
15880 DAG.getConstant(-(uint64_t)Align, dl, VT));
15881 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
15882 } else if (SplitStack) {
15883 MachineRegisterInfo &MRI = MF.getRegInfo();
15886 // The 64 bit implementation of segmented stacks needs to clobber both r10
15887 // r11. This makes it impossible to use it along with nested parameters.
15888 const Function *F = MF.getFunction();
15890 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15892 if (I->hasNestAttr())
15893 report_fatal_error("Cannot use segmented stacks with functions that "
15894 "have nested arguments.");
15897 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15898 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15899 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15900 Result = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15901 DAG.getRegister(Vreg, SPTy));
15904 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15906 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15907 Flag = Chain.getValue(1);
15908 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15910 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15912 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15913 unsigned SPReg = RegInfo->getStackRegister();
15914 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15915 Chain = SP.getValue(1);
15918 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15919 DAG.getConstant(-(uint64_t)Align, dl, VT));
15920 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15926 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15927 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
15929 SDValue Ops[2] = {Result, Chain};
15930 return DAG.getMergeValues(Ops, dl);
15933 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15934 MachineFunction &MF = DAG.getMachineFunction();
15935 auto PtrVT = getPointerTy(MF.getDataLayout());
15936 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15938 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15941 if (!Subtarget->is64Bit() ||
15942 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15943 // vastart just stores the address of the VarArgsFrameIndex slot into the
15944 // memory location argument.
15945 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15946 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15947 MachinePointerInfo(SV), false, false, 0);
15951 // gp_offset (0 - 6 * 8)
15952 // fp_offset (48 - 48 + 8 * 16)
15953 // overflow_arg_area (point to parameters coming in memory).
15955 SmallVector<SDValue, 8> MemOps;
15956 SDValue FIN = Op.getOperand(1);
15958 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15959 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15961 FIN, MachinePointerInfo(SV), false, false, 0);
15962 MemOps.push_back(Store);
15965 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15966 Store = DAG.getStore(Op.getOperand(0), DL,
15967 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15969 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15970 MemOps.push_back(Store);
15972 // Store ptr to overflow_arg_area
15973 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15974 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15975 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15976 MachinePointerInfo(SV, 8),
15978 MemOps.push_back(Store);
15980 // Store ptr to reg_save_area.
15981 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15982 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15983 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15984 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15985 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15986 MemOps.push_back(Store);
15987 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15990 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15991 assert(Subtarget->is64Bit() &&
15992 "LowerVAARG only handles 64-bit va_arg!");
15993 assert(Op.getNode()->getNumOperands() == 4);
15995 MachineFunction &MF = DAG.getMachineFunction();
15996 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15997 // The Win64 ABI uses char* instead of a structure.
15998 return DAG.expandVAArg(Op.getNode());
16000 SDValue Chain = Op.getOperand(0);
16001 SDValue SrcPtr = Op.getOperand(1);
16002 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16003 unsigned Align = Op.getConstantOperandVal(3);
16006 EVT ArgVT = Op.getNode()->getValueType(0);
16007 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16008 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
16011 // Decide which area this value should be read from.
16012 // TODO: Implement the AMD64 ABI in its entirety. This simple
16013 // selection mechanism works only for the basic types.
16014 if (ArgVT == MVT::f80) {
16015 llvm_unreachable("va_arg for f80 not yet implemented");
16016 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16017 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16018 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16019 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16021 llvm_unreachable("Unhandled argument type in LowerVAARG");
16024 if (ArgMode == 2) {
16025 // Sanity Check: Make sure using fp_offset makes sense.
16026 assert(!Subtarget->useSoftFloat() &&
16027 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
16028 Subtarget->hasSSE1());
16031 // Insert VAARG_64 node into the DAG
16032 // VAARG_64 returns two values: Variable Argument Address, Chain
16033 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
16034 DAG.getConstant(ArgMode, dl, MVT::i8),
16035 DAG.getConstant(Align, dl, MVT::i32)};
16036 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
16037 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16038 VTs, InstOps, MVT::i64,
16039 MachinePointerInfo(SV),
16041 /*Volatile=*/false,
16043 /*WriteMem=*/true);
16044 Chain = VAARG.getValue(1);
16046 // Load the next argument and return it
16047 return DAG.getLoad(ArgVT, dl,
16050 MachinePointerInfo(),
16051 false, false, false, 0);
16054 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16055 SelectionDAG &DAG) {
16056 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
16057 // where a va_list is still an i8*.
16058 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16059 if (Subtarget->isCallingConvWin64(
16060 DAG.getMachineFunction().getFunction()->getCallingConv()))
16061 // Probably a Win64 va_copy.
16062 return DAG.expandVACopy(Op.getNode());
16064 SDValue Chain = Op.getOperand(0);
16065 SDValue DstPtr = Op.getOperand(1);
16066 SDValue SrcPtr = Op.getOperand(2);
16067 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16068 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16071 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16072 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
16074 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16077 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16078 // amount is a constant. Takes immediate version of shift as input.
16079 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16080 SDValue SrcOp, uint64_t ShiftAmt,
16081 SelectionDAG &DAG) {
16082 MVT ElementType = VT.getVectorElementType();
16084 // Fold this packed shift into its first operand if ShiftAmt is 0.
16088 // Check for ShiftAmt >= element width
16089 if (ShiftAmt >= ElementType.getSizeInBits()) {
16090 if (Opc == X86ISD::VSRAI)
16091 ShiftAmt = ElementType.getSizeInBits() - 1;
16093 return DAG.getConstant(0, dl, VT);
16096 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16097 && "Unknown target vector shift-by-constant node");
16099 // Fold this packed vector shift into a build vector if SrcOp is a
16100 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16101 if (VT == SrcOp.getSimpleValueType() &&
16102 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16103 SmallVector<SDValue, 8> Elts;
16104 unsigned NumElts = SrcOp->getNumOperands();
16105 ConstantSDNode *ND;
16108 default: llvm_unreachable(nullptr);
16109 case X86ISD::VSHLI:
16110 for (unsigned i=0; i!=NumElts; ++i) {
16111 SDValue CurrentOp = SrcOp->getOperand(i);
16112 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16113 Elts.push_back(CurrentOp);
16116 ND = cast<ConstantSDNode>(CurrentOp);
16117 const APInt &C = ND->getAPIntValue();
16118 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
16121 case X86ISD::VSRLI:
16122 for (unsigned i=0; i!=NumElts; ++i) {
16123 SDValue CurrentOp = SrcOp->getOperand(i);
16124 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16125 Elts.push_back(CurrentOp);
16128 ND = cast<ConstantSDNode>(CurrentOp);
16129 const APInt &C = ND->getAPIntValue();
16130 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
16133 case X86ISD::VSRAI:
16134 for (unsigned i=0; i!=NumElts; ++i) {
16135 SDValue CurrentOp = SrcOp->getOperand(i);
16136 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16137 Elts.push_back(CurrentOp);
16140 ND = cast<ConstantSDNode>(CurrentOp);
16141 const APInt &C = ND->getAPIntValue();
16142 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
16147 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16150 return DAG.getNode(Opc, dl, VT, SrcOp,
16151 DAG.getConstant(ShiftAmt, dl, MVT::i8));
16154 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16155 // may or may not be a constant. Takes immediate version of shift as input.
16156 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16157 SDValue SrcOp, SDValue ShAmt,
16158 SelectionDAG &DAG) {
16159 MVT SVT = ShAmt.getSimpleValueType();
16160 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16162 // Catch shift-by-constant.
16163 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16164 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16165 CShAmt->getZExtValue(), DAG);
16167 // Change opcode to non-immediate version
16169 default: llvm_unreachable("Unknown target vector shift node");
16170 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16171 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16172 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16175 const X86Subtarget &Subtarget =
16176 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16177 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16178 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16179 // Let the shuffle legalizer expand this shift amount node.
16180 SDValue Op0 = ShAmt.getOperand(0);
16181 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16182 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16184 // Need to build a vector containing shift amount.
16185 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16186 SmallVector<SDValue, 4> ShOps;
16187 ShOps.push_back(ShAmt);
16188 if (SVT == MVT::i32) {
16189 ShOps.push_back(DAG.getConstant(0, dl, SVT));
16190 ShOps.push_back(DAG.getUNDEF(SVT));
16192 ShOps.push_back(DAG.getUNDEF(SVT));
16194 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16195 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16198 // The return type has to be a 128-bit type with the same element
16199 // type as the input type.
16200 MVT EltVT = VT.getVectorElementType();
16201 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16203 ShAmt = DAG.getBitcast(ShVT, ShAmt);
16204 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16207 /// \brief Return Mask with the necessary casting or extending
16208 /// for \p Mask according to \p MaskVT when lowering masking intrinsics
16209 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
16210 const X86Subtarget *Subtarget,
16211 SelectionDAG &DAG, SDLoc dl) {
16213 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16214 // Mask should be extended
16215 Mask = DAG.getNode(ISD::ANY_EXTEND, dl,
16216 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask);
16219 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget->is32Bit()) {
16220 if (MaskVT == MVT::v64i1) {
16221 assert(Subtarget->hasBWI() && "Expected AVX512BW target!");
16222 // In case 32bit mode, bitcast i64 is illegal, extend/split it.
16224 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16225 DAG.getConstant(0, dl, MVT::i32));
16226 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16227 DAG.getConstant(1, dl, MVT::i32));
16229 Lo = DAG.getBitcast(MVT::v32i1, Lo);
16230 Hi = DAG.getBitcast(MVT::v32i1, Hi);
16232 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
16234 // MaskVT require < 64bit. Truncate mask (should succeed in any case),
16236 MVT TruncVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16237 return DAG.getBitcast(MaskVT,
16238 DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Mask));
16242 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16243 Mask.getSimpleValueType().getSizeInBits());
16244 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16245 // are extracted by EXTRACT_SUBVECTOR.
16246 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16247 DAG.getBitcast(BitcastVT, Mask),
16248 DAG.getIntPtrConstant(0, dl));
16252 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16253 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16254 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16255 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16256 SDValue PreservedSrc,
16257 const X86Subtarget *Subtarget,
16258 SelectionDAG &DAG) {
16259 MVT VT = Op.getSimpleValueType();
16260 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16261 unsigned OpcodeSelect = ISD::VSELECT;
16264 if (isAllOnesConstant(Mask))
16267 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16269 switch (Op.getOpcode()) {
16271 case X86ISD::PCMPEQM:
16272 case X86ISD::PCMPGTM:
16274 case X86ISD::CMPMU:
16275 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16276 case X86ISD::VFPCLASS:
16277 case X86ISD::VFPCLASSS:
16278 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16279 case X86ISD::VTRUNC:
16280 case X86ISD::VTRUNCS:
16281 case X86ISD::VTRUNCUS:
16282 // We can't use ISD::VSELECT here because it is not always "Legal"
16283 // for the destination type. For example vpmovqb require only AVX512
16284 // and vselect that can operate on byte element type require BWI
16285 OpcodeSelect = X86ISD::SELECT;
16288 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16289 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16290 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16293 /// \brief Creates an SDNode for a predicated scalar operation.
16294 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16295 /// The mask is coming as MVT::i8 and it should be truncated
16296 /// to MVT::i1 while lowering masking intrinsics.
16297 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16298 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16299 /// for a scalar instruction.
16300 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16301 SDValue PreservedSrc,
16302 const X86Subtarget *Subtarget,
16303 SelectionDAG &DAG) {
16304 if (isAllOnesConstant(Mask))
16307 MVT VT = Op.getSimpleValueType();
16309 // The mask should be of type MVT::i1
16310 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16312 if (Op.getOpcode() == X86ISD::FSETCC)
16313 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16314 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16315 Op.getOpcode() == X86ISD::VFPCLASSS)
16316 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16318 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16319 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16320 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16323 static int getSEHRegistrationNodeSize(const Function *Fn) {
16324 if (!Fn->hasPersonalityFn())
16325 report_fatal_error(
16326 "querying registration node size for function without personality");
16327 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16328 // WinEHStatePass for the full struct definition.
16329 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16330 case EHPersonality::MSVC_X86SEH: return 24;
16331 case EHPersonality::MSVC_CXX: return 16;
16334 report_fatal_error(
16335 "can only recover FP for 32-bit MSVC EH personality functions");
16338 /// When the MSVC runtime transfers control to us, either to an outlined
16339 /// function or when returning to a parent frame after catching an exception, we
16340 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16341 /// Here's the math:
16342 /// RegNodeBase = EntryEBP - RegNodeSize
16343 /// ParentFP = RegNodeBase - ParentFrameOffset
16344 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16345 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16346 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16347 SDValue EntryEBP) {
16348 MachineFunction &MF = DAG.getMachineFunction();
16351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16352 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16354 // It's possible that the parent function no longer has a personality function
16355 // if the exceptional code was optimized away, in which case we just return
16356 // the incoming EBP.
16357 if (!Fn->hasPersonalityFn())
16360 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16361 // registration, or the .set_setframe offset.
16362 MCSymbol *OffsetSym =
16363 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16364 GlobalValue::getRealLinkageName(Fn->getName()));
16365 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16366 SDValue ParentFrameOffset =
16367 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16369 // Return EntryEBP + ParentFrameOffset for x64. This adjusts from RSP after
16370 // prologue to RBP in the parent function.
16371 const X86Subtarget &Subtarget =
16372 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16373 if (Subtarget.is64Bit())
16374 return DAG.getNode(ISD::ADD, dl, PtrVT, EntryEBP, ParentFrameOffset);
16376 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16377 // RegNodeBase = EntryEBP - RegNodeSize
16378 // ParentFP = RegNodeBase - ParentFrameOffset
16379 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16380 DAG.getConstant(RegNodeSize, dl, PtrVT));
16381 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, ParentFrameOffset);
16384 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16385 SelectionDAG &DAG) {
16387 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16388 MVT VT = Op.getSimpleValueType();
16389 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16391 switch(IntrData->Type) {
16392 case INTR_TYPE_1OP:
16393 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16394 case INTR_TYPE_2OP:
16395 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16397 case INTR_TYPE_2OP_IMM8:
16398 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16399 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16400 case INTR_TYPE_3OP:
16401 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16402 Op.getOperand(2), Op.getOperand(3));
16403 case INTR_TYPE_4OP:
16404 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16405 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16406 case INTR_TYPE_1OP_MASK_RM: {
16407 SDValue Src = Op.getOperand(1);
16408 SDValue PassThru = Op.getOperand(2);
16409 SDValue Mask = Op.getOperand(3);
16410 SDValue RoundingMode;
16411 // We allways add rounding mode to the Node.
16412 // If the rounding mode is not specified, we add the
16413 // "current direction" mode.
16414 if (Op.getNumOperands() == 4)
16416 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16418 RoundingMode = Op.getOperand(4);
16419 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16420 if (IntrWithRoundingModeOpcode != 0)
16421 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16422 X86::STATIC_ROUNDING::CUR_DIRECTION)
16423 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16424 dl, Op.getValueType(), Src, RoundingMode),
16425 Mask, PassThru, Subtarget, DAG);
16426 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16428 Mask, PassThru, Subtarget, DAG);
16430 case INTR_TYPE_1OP_MASK: {
16431 SDValue Src = Op.getOperand(1);
16432 SDValue PassThru = Op.getOperand(2);
16433 SDValue Mask = Op.getOperand(3);
16434 // We add rounding mode to the Node when
16435 // - RM Opcode is specified and
16436 // - RM is not "current direction".
16437 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16438 if (IntrWithRoundingModeOpcode != 0) {
16439 SDValue Rnd = Op.getOperand(4);
16440 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16441 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16442 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16443 dl, Op.getValueType(),
16445 Mask, PassThru, Subtarget, DAG);
16448 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16449 Mask, PassThru, Subtarget, DAG);
16451 case INTR_TYPE_SCALAR_MASK: {
16452 SDValue Src1 = Op.getOperand(1);
16453 SDValue Src2 = Op.getOperand(2);
16454 SDValue passThru = Op.getOperand(3);
16455 SDValue Mask = Op.getOperand(4);
16456 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16457 Mask, passThru, Subtarget, DAG);
16459 case INTR_TYPE_SCALAR_MASK_RM: {
16460 SDValue Src1 = Op.getOperand(1);
16461 SDValue Src2 = Op.getOperand(2);
16462 SDValue Src0 = Op.getOperand(3);
16463 SDValue Mask = Op.getOperand(4);
16464 // There are 2 kinds of intrinsics in this group:
16465 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16466 // (2) With rounding mode and sae - 7 operands.
16467 if (Op.getNumOperands() == 6) {
16468 SDValue Sae = Op.getOperand(5);
16469 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16470 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16472 Mask, Src0, Subtarget, DAG);
16474 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16475 SDValue RoundingMode = Op.getOperand(5);
16476 SDValue Sae = Op.getOperand(6);
16477 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16478 RoundingMode, Sae),
16479 Mask, Src0, Subtarget, DAG);
16481 case INTR_TYPE_2OP_MASK:
16482 case INTR_TYPE_2OP_IMM8_MASK: {
16483 SDValue Src1 = Op.getOperand(1);
16484 SDValue Src2 = Op.getOperand(2);
16485 SDValue PassThru = Op.getOperand(3);
16486 SDValue Mask = Op.getOperand(4);
16488 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16489 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16491 // We specify 2 possible opcodes for intrinsics with rounding modes.
16492 // First, we check if the intrinsic may have non-default rounding mode,
16493 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16494 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16495 if (IntrWithRoundingModeOpcode != 0) {
16496 SDValue Rnd = Op.getOperand(5);
16497 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16498 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16499 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16500 dl, Op.getValueType(),
16502 Mask, PassThru, Subtarget, DAG);
16505 // TODO: Intrinsics should have fast-math-flags to propagate.
16506 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16507 Mask, PassThru, Subtarget, DAG);
16509 case INTR_TYPE_2OP_MASK_RM: {
16510 SDValue Src1 = Op.getOperand(1);
16511 SDValue Src2 = Op.getOperand(2);
16512 SDValue PassThru = Op.getOperand(3);
16513 SDValue Mask = Op.getOperand(4);
16514 // We specify 2 possible modes for intrinsics, with/without rounding
16516 // First, we check if the intrinsic have rounding mode (6 operands),
16517 // if not, we set rounding mode to "current".
16519 if (Op.getNumOperands() == 6)
16520 Rnd = Op.getOperand(5);
16522 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16523 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16525 Mask, PassThru, Subtarget, DAG);
16527 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16528 SDValue Src1 = Op.getOperand(1);
16529 SDValue Src2 = Op.getOperand(2);
16530 SDValue Src3 = Op.getOperand(3);
16531 SDValue PassThru = Op.getOperand(4);
16532 SDValue Mask = Op.getOperand(5);
16533 SDValue Sae = Op.getOperand(6);
16535 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16537 Mask, PassThru, Subtarget, DAG);
16539 case INTR_TYPE_3OP_MASK_RM: {
16540 SDValue Src1 = Op.getOperand(1);
16541 SDValue Src2 = Op.getOperand(2);
16542 SDValue Imm = Op.getOperand(3);
16543 SDValue PassThru = Op.getOperand(4);
16544 SDValue Mask = Op.getOperand(5);
16545 // We specify 2 possible modes for intrinsics, with/without rounding
16547 // First, we check if the intrinsic have rounding mode (7 operands),
16548 // if not, we set rounding mode to "current".
16550 if (Op.getNumOperands() == 7)
16551 Rnd = Op.getOperand(6);
16553 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16554 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16555 Src1, Src2, Imm, Rnd),
16556 Mask, PassThru, Subtarget, DAG);
16558 case INTR_TYPE_3OP_IMM8_MASK:
16559 case INTR_TYPE_3OP_MASK:
16560 case INSERT_SUBVEC: {
16561 SDValue Src1 = Op.getOperand(1);
16562 SDValue Src2 = Op.getOperand(2);
16563 SDValue Src3 = Op.getOperand(3);
16564 SDValue PassThru = Op.getOperand(4);
16565 SDValue Mask = Op.getOperand(5);
16567 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16568 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16569 else if (IntrData->Type == INSERT_SUBVEC) {
16570 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16571 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16572 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16573 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16574 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16577 // We specify 2 possible opcodes for intrinsics with rounding modes.
16578 // First, we check if the intrinsic may have non-default rounding mode,
16579 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16580 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16581 if (IntrWithRoundingModeOpcode != 0) {
16582 SDValue Rnd = Op.getOperand(6);
16583 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16584 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16585 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16586 dl, Op.getValueType(),
16587 Src1, Src2, Src3, Rnd),
16588 Mask, PassThru, Subtarget, DAG);
16591 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16593 Mask, PassThru, Subtarget, DAG);
16595 case VPERM_3OP_MASKZ:
16596 case VPERM_3OP_MASK:{
16597 // Src2 is the PassThru
16598 SDValue Src1 = Op.getOperand(1);
16599 SDValue Src2 = Op.getOperand(2);
16600 SDValue Src3 = Op.getOperand(3);
16601 SDValue Mask = Op.getOperand(4);
16602 MVT VT = Op.getSimpleValueType();
16603 SDValue PassThru = SDValue();
16605 // set PassThru element
16606 if (IntrData->Type == VPERM_3OP_MASKZ)
16607 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16609 PassThru = DAG.getBitcast(VT, Src2);
16611 // Swap Src1 and Src2 in the node creation
16612 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16613 dl, Op.getValueType(),
16615 Mask, PassThru, Subtarget, DAG);
16619 case FMA_OP_MASK: {
16620 SDValue Src1 = Op.getOperand(1);
16621 SDValue Src2 = Op.getOperand(2);
16622 SDValue Src3 = Op.getOperand(3);
16623 SDValue Mask = Op.getOperand(4);
16624 MVT VT = Op.getSimpleValueType();
16625 SDValue PassThru = SDValue();
16627 // set PassThru element
16628 if (IntrData->Type == FMA_OP_MASKZ)
16629 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16630 else if (IntrData->Type == FMA_OP_MASK3)
16635 // We specify 2 possible opcodes for intrinsics with rounding modes.
16636 // First, we check if the intrinsic may have non-default rounding mode,
16637 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16638 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16639 if (IntrWithRoundingModeOpcode != 0) {
16640 SDValue Rnd = Op.getOperand(5);
16641 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16642 X86::STATIC_ROUNDING::CUR_DIRECTION)
16643 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16644 dl, Op.getValueType(),
16645 Src1, Src2, Src3, Rnd),
16646 Mask, PassThru, Subtarget, DAG);
16648 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16649 dl, Op.getValueType(),
16651 Mask, PassThru, Subtarget, DAG);
16653 case TERLOG_OP_MASK:
16654 case TERLOG_OP_MASKZ: {
16655 SDValue Src1 = Op.getOperand(1);
16656 SDValue Src2 = Op.getOperand(2);
16657 SDValue Src3 = Op.getOperand(3);
16658 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16659 SDValue Mask = Op.getOperand(5);
16660 MVT VT = Op.getSimpleValueType();
16661 SDValue PassThru = Src1;
16662 // Set PassThru element.
16663 if (IntrData->Type == TERLOG_OP_MASKZ)
16664 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16666 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16667 Src1, Src2, Src3, Src4),
16668 Mask, PassThru, Subtarget, DAG);
16671 // FPclass intrinsics with mask
16672 SDValue Src1 = Op.getOperand(1);
16673 MVT VT = Src1.getSimpleValueType();
16674 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16675 SDValue Imm = Op.getOperand(2);
16676 SDValue Mask = Op.getOperand(3);
16677 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16678 Mask.getSimpleValueType().getSizeInBits());
16679 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16680 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16681 DAG.getTargetConstant(0, dl, MaskVT),
16683 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16684 DAG.getUNDEF(BitcastVT), FPclassMask,
16685 DAG.getIntPtrConstant(0, dl));
16686 return DAG.getBitcast(Op.getValueType(), Res);
16689 SDValue Src1 = Op.getOperand(1);
16690 SDValue Imm = Op.getOperand(2);
16691 SDValue Mask = Op.getOperand(3);
16692 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16693 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16694 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16695 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16698 case CMP_MASK_CC: {
16699 // Comparison intrinsics with masks.
16700 // Example of transformation:
16701 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16702 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16704 // (v8i1 (insert_subvector undef,
16705 // (v2i1 (and (PCMPEQM %a, %b),
16706 // (extract_subvector
16707 // (v8i1 (bitcast %mask)), 0))), 0))))
16708 MVT VT = Op.getOperand(1).getSimpleValueType();
16709 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16710 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16711 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16712 Mask.getSimpleValueType().getSizeInBits());
16714 if (IntrData->Type == CMP_MASK_CC) {
16715 SDValue CC = Op.getOperand(3);
16716 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16717 // We specify 2 possible opcodes for intrinsics with rounding modes.
16718 // First, we check if the intrinsic may have non-default rounding mode,
16719 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16720 if (IntrData->Opc1 != 0) {
16721 SDValue Rnd = Op.getOperand(5);
16722 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16723 X86::STATIC_ROUNDING::CUR_DIRECTION)
16724 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16725 Op.getOperand(2), CC, Rnd);
16727 //default rounding mode
16729 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16730 Op.getOperand(2), CC);
16733 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16734 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16737 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16738 DAG.getTargetConstant(0, dl,
16741 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16742 DAG.getUNDEF(BitcastVT), CmpMask,
16743 DAG.getIntPtrConstant(0, dl));
16744 return DAG.getBitcast(Op.getValueType(), Res);
16746 case CMP_MASK_SCALAR_CC: {
16747 SDValue Src1 = Op.getOperand(1);
16748 SDValue Src2 = Op.getOperand(2);
16749 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16750 SDValue Mask = Op.getOperand(4);
16753 if (IntrData->Opc1 != 0) {
16754 SDValue Rnd = Op.getOperand(5);
16755 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16756 X86::STATIC_ROUNDING::CUR_DIRECTION)
16757 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16759 //default rounding mode
16761 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16763 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16764 DAG.getTargetConstant(0, dl,
16768 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16769 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16770 DAG.getValueType(MVT::i1));
16772 case COMI: { // Comparison intrinsics
16773 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16774 SDValue LHS = Op.getOperand(1);
16775 SDValue RHS = Op.getOperand(2);
16776 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16777 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16778 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16779 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16780 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16781 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16783 case COMI_RM: { // Comparison intrinsics with Sae
16784 SDValue LHS = Op.getOperand(1);
16785 SDValue RHS = Op.getOperand(2);
16786 SDValue CC = Op.getOperand(3);
16787 SDValue Sae = Op.getOperand(4);
16788 auto ComiType = TranslateX86ConstCondToX86CC(CC);
16789 // choose between ordered and unordered (comi/ucomi)
16790 unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;
16792 if (cast<ConstantSDNode>(Sae)->getZExtValue() !=
16793 X86::STATIC_ROUNDING::CUR_DIRECTION)
16794 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);
16796 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);
16797 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16798 DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);
16799 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16802 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16803 Op.getOperand(1), Op.getOperand(2), DAG);
16805 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16806 Op.getSimpleValueType(),
16808 Op.getOperand(2), DAG),
16809 Op.getOperand(4), Op.getOperand(3), Subtarget,
16811 case COMPRESS_EXPAND_IN_REG: {
16812 SDValue Mask = Op.getOperand(3);
16813 SDValue DataToCompress = Op.getOperand(1);
16814 SDValue PassThru = Op.getOperand(2);
16815 if (isAllOnesConstant(Mask)) // return data as is
16816 return Op.getOperand(1);
16818 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16820 Mask, PassThru, Subtarget, DAG);
16823 SDValue Mask = Op.getOperand(1);
16824 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16825 Mask = DAG.getBitcast(MaskVT, Mask);
16826 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16829 SDValue Mask = Op.getOperand(3);
16830 MVT VT = Op.getSimpleValueType();
16831 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16832 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16833 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16837 MVT VT = Op.getSimpleValueType();
16838 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits()/2);
16840 SDValue Src1 = getMaskNode(Op.getOperand(1), MaskVT, Subtarget, DAG, dl);
16841 SDValue Src2 = getMaskNode(Op.getOperand(2), MaskVT, Subtarget, DAG, dl);
16842 // Arguments should be swapped.
16843 SDValue Res = DAG.getNode(IntrData->Opc0, dl,
16844 MVT::getVectorVT(MVT::i1, VT.getSizeInBits()),
16846 return DAG.getBitcast(VT, Res);
16848 case CONVERT_MASK_TO_VEC: {
16849 SDValue Mask = Op.getOperand(1);
16850 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16851 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16852 return DAG.getNode(IntrData->Opc0, dl, VT, VMask);
16860 default: return SDValue(); // Don't custom lower most intrinsics.
16862 case Intrinsic::x86_avx2_permd:
16863 case Intrinsic::x86_avx2_permps:
16864 // Operands intentionally swapped. Mask is last operand to intrinsic,
16865 // but second operand for node/instruction.
16866 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16867 Op.getOperand(2), Op.getOperand(1));
16869 // ptest and testp intrinsics. The intrinsic these come from are designed to
16870 // return an integer value, not just an instruction so lower it to the ptest
16871 // or testp pattern and a setcc for the result.
16872 case Intrinsic::x86_sse41_ptestz:
16873 case Intrinsic::x86_sse41_ptestc:
16874 case Intrinsic::x86_sse41_ptestnzc:
16875 case Intrinsic::x86_avx_ptestz_256:
16876 case Intrinsic::x86_avx_ptestc_256:
16877 case Intrinsic::x86_avx_ptestnzc_256:
16878 case Intrinsic::x86_avx_vtestz_ps:
16879 case Intrinsic::x86_avx_vtestc_ps:
16880 case Intrinsic::x86_avx_vtestnzc_ps:
16881 case Intrinsic::x86_avx_vtestz_pd:
16882 case Intrinsic::x86_avx_vtestc_pd:
16883 case Intrinsic::x86_avx_vtestnzc_pd:
16884 case Intrinsic::x86_avx_vtestz_ps_256:
16885 case Intrinsic::x86_avx_vtestc_ps_256:
16886 case Intrinsic::x86_avx_vtestnzc_ps_256:
16887 case Intrinsic::x86_avx_vtestz_pd_256:
16888 case Intrinsic::x86_avx_vtestc_pd_256:
16889 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16890 bool IsTestPacked = false;
16893 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16894 case Intrinsic::x86_avx_vtestz_ps:
16895 case Intrinsic::x86_avx_vtestz_pd:
16896 case Intrinsic::x86_avx_vtestz_ps_256:
16897 case Intrinsic::x86_avx_vtestz_pd_256:
16898 IsTestPacked = true; // Fallthrough
16899 case Intrinsic::x86_sse41_ptestz:
16900 case Intrinsic::x86_avx_ptestz_256:
16902 X86CC = X86::COND_E;
16904 case Intrinsic::x86_avx_vtestc_ps:
16905 case Intrinsic::x86_avx_vtestc_pd:
16906 case Intrinsic::x86_avx_vtestc_ps_256:
16907 case Intrinsic::x86_avx_vtestc_pd_256:
16908 IsTestPacked = true; // Fallthrough
16909 case Intrinsic::x86_sse41_ptestc:
16910 case Intrinsic::x86_avx_ptestc_256:
16912 X86CC = X86::COND_B;
16914 case Intrinsic::x86_avx_vtestnzc_ps:
16915 case Intrinsic::x86_avx_vtestnzc_pd:
16916 case Intrinsic::x86_avx_vtestnzc_ps_256:
16917 case Intrinsic::x86_avx_vtestnzc_pd_256:
16918 IsTestPacked = true; // Fallthrough
16919 case Intrinsic::x86_sse41_ptestnzc:
16920 case Intrinsic::x86_avx_ptestnzc_256:
16922 X86CC = X86::COND_A;
16926 SDValue LHS = Op.getOperand(1);
16927 SDValue RHS = Op.getOperand(2);
16928 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16929 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16930 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16931 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16932 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16934 case Intrinsic::x86_avx512_kortestz_w:
16935 case Intrinsic::x86_avx512_kortestc_w: {
16936 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16937 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16938 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16939 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16940 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16941 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16942 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16945 case Intrinsic::x86_sse42_pcmpistria128:
16946 case Intrinsic::x86_sse42_pcmpestria128:
16947 case Intrinsic::x86_sse42_pcmpistric128:
16948 case Intrinsic::x86_sse42_pcmpestric128:
16949 case Intrinsic::x86_sse42_pcmpistrio128:
16950 case Intrinsic::x86_sse42_pcmpestrio128:
16951 case Intrinsic::x86_sse42_pcmpistris128:
16952 case Intrinsic::x86_sse42_pcmpestris128:
16953 case Intrinsic::x86_sse42_pcmpistriz128:
16954 case Intrinsic::x86_sse42_pcmpestriz128: {
16958 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16959 case Intrinsic::x86_sse42_pcmpistria128:
16960 Opcode = X86ISD::PCMPISTRI;
16961 X86CC = X86::COND_A;
16963 case Intrinsic::x86_sse42_pcmpestria128:
16964 Opcode = X86ISD::PCMPESTRI;
16965 X86CC = X86::COND_A;
16967 case Intrinsic::x86_sse42_pcmpistric128:
16968 Opcode = X86ISD::PCMPISTRI;
16969 X86CC = X86::COND_B;
16971 case Intrinsic::x86_sse42_pcmpestric128:
16972 Opcode = X86ISD::PCMPESTRI;
16973 X86CC = X86::COND_B;
16975 case Intrinsic::x86_sse42_pcmpistrio128:
16976 Opcode = X86ISD::PCMPISTRI;
16977 X86CC = X86::COND_O;
16979 case Intrinsic::x86_sse42_pcmpestrio128:
16980 Opcode = X86ISD::PCMPESTRI;
16981 X86CC = X86::COND_O;
16983 case Intrinsic::x86_sse42_pcmpistris128:
16984 Opcode = X86ISD::PCMPISTRI;
16985 X86CC = X86::COND_S;
16987 case Intrinsic::x86_sse42_pcmpestris128:
16988 Opcode = X86ISD::PCMPESTRI;
16989 X86CC = X86::COND_S;
16991 case Intrinsic::x86_sse42_pcmpistriz128:
16992 Opcode = X86ISD::PCMPISTRI;
16993 X86CC = X86::COND_E;
16995 case Intrinsic::x86_sse42_pcmpestriz128:
16996 Opcode = X86ISD::PCMPESTRI;
16997 X86CC = X86::COND_E;
17000 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17001 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17002 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17003 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17004 DAG.getConstant(X86CC, dl, MVT::i8),
17005 SDValue(PCMP.getNode(), 1));
17006 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17009 case Intrinsic::x86_sse42_pcmpistri128:
17010 case Intrinsic::x86_sse42_pcmpestri128: {
17012 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17013 Opcode = X86ISD::PCMPISTRI;
17015 Opcode = X86ISD::PCMPESTRI;
17017 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17018 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17019 return DAG.getNode(Opcode, dl, VTs, NewOps);
17022 case Intrinsic::x86_seh_lsda: {
17023 // Compute the symbol for the LSDA. We know it'll get emitted later.
17024 MachineFunction &MF = DAG.getMachineFunction();
17025 SDValue Op1 = Op.getOperand(1);
17026 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
17027 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
17028 GlobalValue::getRealLinkageName(Fn->getName()));
17030 // Generate a simple absolute symbol reference. This intrinsic is only
17031 // supported on 32-bit Windows, which isn't PIC.
17032 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
17033 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
17036 case Intrinsic::x86_seh_recoverfp: {
17037 SDValue FnOp = Op.getOperand(1);
17038 SDValue IncomingFPOp = Op.getOperand(2);
17039 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
17040 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
17042 report_fatal_error(
17043 "llvm.x86.seh.recoverfp must take a function as the first argument");
17044 return recoverFramePointer(DAG, Fn, IncomingFPOp);
17047 case Intrinsic::localaddress: {
17048 // Returns one of the stack, base, or frame pointer registers, depending on
17049 // which is used to reference local variables.
17050 MachineFunction &MF = DAG.getMachineFunction();
17051 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17053 if (RegInfo->hasBasePointer(MF))
17054 Reg = RegInfo->getBaseRegister();
17055 else // This function handles the SP or FP case.
17056 Reg = RegInfo->getPtrSizedFrameRegister(MF);
17057 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
17062 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17063 SDValue Src, SDValue Mask, SDValue Base,
17064 SDValue Index, SDValue ScaleOp, SDValue Chain,
17065 const X86Subtarget * Subtarget) {
17067 auto *C = cast<ConstantSDNode>(ScaleOp);
17068 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17069 MVT MaskVT = MVT::getVectorVT(MVT::i1,
17070 Index.getSimpleValueType().getVectorNumElements());
17072 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17074 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17076 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17077 Mask.getSimpleValueType().getSizeInBits());
17079 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17080 // are extracted by EXTRACT_SUBVECTOR.
17081 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17082 DAG.getBitcast(BitcastVT, Mask),
17083 DAG.getIntPtrConstant(0, dl));
17085 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17086 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17087 SDValue Segment = DAG.getRegister(0, MVT::i32);
17088 if (Src.getOpcode() == ISD::UNDEF)
17089 Src = getZeroVector(Op.getSimpleValueType(), Subtarget, DAG, dl);
17090 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17091 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17092 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17093 return DAG.getMergeValues(RetOps, dl);
17096 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17097 SDValue Src, SDValue Mask, SDValue Base,
17098 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17100 auto *C = cast<ConstantSDNode>(ScaleOp);
17101 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17102 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17103 SDValue Segment = DAG.getRegister(0, MVT::i32);
17104 MVT MaskVT = MVT::getVectorVT(MVT::i1,
17105 Index.getSimpleValueType().getVectorNumElements());
17107 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17109 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17111 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17112 Mask.getSimpleValueType().getSizeInBits());
17114 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17115 // are extracted by EXTRACT_SUBVECTOR.
17116 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17117 DAG.getBitcast(BitcastVT, Mask),
17118 DAG.getIntPtrConstant(0, dl));
17120 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17121 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17122 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17123 return SDValue(Res, 1);
17126 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17127 SDValue Mask, SDValue Base, SDValue Index,
17128 SDValue ScaleOp, SDValue Chain) {
17130 auto *C = cast<ConstantSDNode>(ScaleOp);
17131 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17132 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17133 SDValue Segment = DAG.getRegister(0, MVT::i32);
17135 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17137 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17139 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17141 MaskInReg = DAG.getBitcast(MaskVT, Mask);
17142 //SDVTList VTs = DAG.getVTList(MVT::Other);
17143 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17144 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17145 return SDValue(Res, 0);
17148 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17149 // read performance monitor counters (x86_rdpmc).
17150 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17151 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17152 SmallVectorImpl<SDValue> &Results) {
17153 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17154 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17157 // The ECX register is used to select the index of the performance counter
17159 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17161 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17163 // Reads the content of a 64-bit performance counter and returns it in the
17164 // registers EDX:EAX.
17165 if (Subtarget->is64Bit()) {
17166 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17167 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17170 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17171 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17174 Chain = HI.getValue(1);
17176 if (Subtarget->is64Bit()) {
17177 // The EAX register is loaded with the low-order 32 bits. The EDX register
17178 // is loaded with the supported high-order bits of the counter.
17179 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17180 DAG.getConstant(32, DL, MVT::i8));
17181 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17182 Results.push_back(Chain);
17186 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17187 SDValue Ops[] = { LO, HI };
17188 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17189 Results.push_back(Pair);
17190 Results.push_back(Chain);
17193 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17194 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17195 // also used to custom lower READCYCLECOUNTER nodes.
17196 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17197 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17198 SmallVectorImpl<SDValue> &Results) {
17199 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17200 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17203 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17204 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17205 // and the EAX register is loaded with the low-order 32 bits.
17206 if (Subtarget->is64Bit()) {
17207 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17208 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17211 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17212 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17215 SDValue Chain = HI.getValue(1);
17217 if (Opcode == X86ISD::RDTSCP_DAG) {
17218 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17220 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17221 // the ECX register. Add 'ecx' explicitly to the chain.
17222 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17224 // Explicitly store the content of ECX at the location passed in input
17225 // to the 'rdtscp' intrinsic.
17226 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17227 MachinePointerInfo(), false, false, 0);
17230 if (Subtarget->is64Bit()) {
17231 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17232 // the EAX register is loaded with the low-order 32 bits.
17233 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17234 DAG.getConstant(32, DL, MVT::i8));
17235 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17236 Results.push_back(Chain);
17240 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17241 SDValue Ops[] = { LO, HI };
17242 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17243 Results.push_back(Pair);
17244 Results.push_back(Chain);
17247 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17248 SelectionDAG &DAG) {
17249 SmallVector<SDValue, 2> Results;
17251 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17253 return DAG.getMergeValues(Results, DL);
17256 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17257 MachineFunction &MF = DAG.getMachineFunction();
17258 SDValue Chain = Op.getOperand(0);
17259 SDValue RegNode = Op.getOperand(2);
17260 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17262 report_fatal_error("EH registrations only live in functions using WinEH");
17264 // Cast the operand to an alloca, and remember the frame index.
17265 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17267 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17268 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17270 // Return the chain operand without making any DAG nodes.
17274 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17275 /// return truncate Store/MaskedStore Node
17276 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17280 SDValue Mask = Op.getOperand(4);
17281 SDValue DataToTruncate = Op.getOperand(3);
17282 SDValue Addr = Op.getOperand(2);
17283 SDValue Chain = Op.getOperand(0);
17285 MVT VT = DataToTruncate.getSimpleValueType();
17286 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17288 if (isAllOnesConstant(Mask)) // return just a truncate store
17289 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17290 MachinePointerInfo(), SVT, false, false,
17291 SVT.getScalarSizeInBits()/8);
17293 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17294 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17295 Mask.getSimpleValueType().getSizeInBits());
17296 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17297 // are extracted by EXTRACT_SUBVECTOR.
17298 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17299 DAG.getBitcast(BitcastVT, Mask),
17300 DAG.getIntPtrConstant(0, dl));
17302 MachineMemOperand *MMO = DAG.getMachineFunction().
17303 getMachineMemOperand(MachinePointerInfo(),
17304 MachineMemOperand::MOStore, SVT.getStoreSize(),
17305 SVT.getScalarSizeInBits()/8);
17307 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17308 VMask, SVT, MMO, true);
17311 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17312 SelectionDAG &DAG) {
17313 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17315 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17317 if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17318 return MarkEHRegistrationNode(Op, DAG);
17323 switch(IntrData->Type) {
17324 default: llvm_unreachable("Unknown Intrinsic Type");
17327 // Emit the node with the right value type.
17328 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17329 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17331 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17332 // Otherwise return the value from Rand, which is always 0, casted to i32.
17333 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17334 DAG.getConstant(1, dl, Op->getValueType(1)),
17335 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17336 SDValue(Result.getNode(), 1) };
17337 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17338 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17341 // Return { result, isValid, chain }.
17342 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17343 SDValue(Result.getNode(), 2));
17346 //gather(v1, mask, index, base, scale);
17347 SDValue Chain = Op.getOperand(0);
17348 SDValue Src = Op.getOperand(2);
17349 SDValue Base = Op.getOperand(3);
17350 SDValue Index = Op.getOperand(4);
17351 SDValue Mask = Op.getOperand(5);
17352 SDValue Scale = Op.getOperand(6);
17353 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17357 //scatter(base, mask, index, v1, scale);
17358 SDValue Chain = Op.getOperand(0);
17359 SDValue Base = Op.getOperand(2);
17360 SDValue Mask = Op.getOperand(3);
17361 SDValue Index = Op.getOperand(4);
17362 SDValue Src = Op.getOperand(5);
17363 SDValue Scale = Op.getOperand(6);
17364 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17368 SDValue Hint = Op.getOperand(6);
17369 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17370 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17371 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17372 SDValue Chain = Op.getOperand(0);
17373 SDValue Mask = Op.getOperand(2);
17374 SDValue Index = Op.getOperand(3);
17375 SDValue Base = Op.getOperand(4);
17376 SDValue Scale = Op.getOperand(5);
17377 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17379 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17381 SmallVector<SDValue, 2> Results;
17382 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17384 return DAG.getMergeValues(Results, dl);
17386 // Read Performance Monitoring Counters.
17388 SmallVector<SDValue, 2> Results;
17389 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17390 return DAG.getMergeValues(Results, dl);
17392 // XTEST intrinsics.
17394 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17395 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17396 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17397 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17399 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17400 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17401 Ret, SDValue(InTrans.getNode(), 1));
17405 SmallVector<SDValue, 2> Results;
17406 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17407 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17408 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17409 DAG.getConstant(-1, dl, MVT::i8));
17410 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17411 Op.getOperand(4), GenCF.getValue(1));
17412 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17413 Op.getOperand(5), MachinePointerInfo(),
17415 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17416 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17418 Results.push_back(SetCC);
17419 Results.push_back(Store);
17420 return DAG.getMergeValues(Results, dl);
17422 case COMPRESS_TO_MEM: {
17424 SDValue Mask = Op.getOperand(4);
17425 SDValue DataToCompress = Op.getOperand(3);
17426 SDValue Addr = Op.getOperand(2);
17427 SDValue Chain = Op.getOperand(0);
17429 MVT VT = DataToCompress.getSimpleValueType();
17430 if (isAllOnesConstant(Mask)) // return just a store
17431 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17432 MachinePointerInfo(), false, false,
17433 VT.getScalarSizeInBits()/8);
17435 SDValue Compressed =
17436 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17437 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17438 return DAG.getStore(Chain, dl, Compressed, Addr,
17439 MachinePointerInfo(), false, false,
17440 VT.getScalarSizeInBits()/8);
17442 case TRUNCATE_TO_MEM_VI8:
17443 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17444 case TRUNCATE_TO_MEM_VI16:
17445 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17446 case TRUNCATE_TO_MEM_VI32:
17447 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17448 case EXPAND_FROM_MEM: {
17450 SDValue Mask = Op.getOperand(4);
17451 SDValue PassThru = Op.getOperand(3);
17452 SDValue Addr = Op.getOperand(2);
17453 SDValue Chain = Op.getOperand(0);
17454 MVT VT = Op.getSimpleValueType();
17456 if (isAllOnesConstant(Mask)) // return just a load
17457 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17458 false, VT.getScalarSizeInBits()/8);
17460 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17461 false, false, false,
17462 VT.getScalarSizeInBits()/8);
17464 SDValue Results[] = {
17465 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17466 Mask, PassThru, Subtarget, DAG), Chain};
17467 return DAG.getMergeValues(Results, dl);
17472 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17473 SelectionDAG &DAG) const {
17474 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17475 MFI->setReturnAddressIsTaken(true);
17477 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17480 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17482 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17485 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17486 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17487 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17488 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17489 DAG.getNode(ISD::ADD, dl, PtrVT,
17490 FrameAddr, Offset),
17491 MachinePointerInfo(), false, false, false, 0);
17494 // Just load the return address.
17495 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17496 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17497 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17500 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17501 MachineFunction &MF = DAG.getMachineFunction();
17502 MachineFrameInfo *MFI = MF.getFrameInfo();
17503 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17504 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17505 EVT VT = Op.getValueType();
17507 MFI->setFrameAddressIsTaken(true);
17509 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17510 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17511 // is not possible to crawl up the stack without looking at the unwind codes
17513 int FrameAddrIndex = FuncInfo->getFAIndex();
17514 if (!FrameAddrIndex) {
17515 // Set up a frame object for the return address.
17516 unsigned SlotSize = RegInfo->getSlotSize();
17517 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17518 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17519 FuncInfo->setFAIndex(FrameAddrIndex);
17521 return DAG.getFrameIndex(FrameAddrIndex, VT);
17524 unsigned FrameReg =
17525 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17526 SDLoc dl(Op); // FIXME probably not meaningful
17527 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17528 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17529 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17530 "Invalid Frame Register!");
17531 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17533 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17534 MachinePointerInfo(),
17535 false, false, false, 0);
17539 // FIXME? Maybe this could be a TableGen attribute on some registers and
17540 // this table could be generated automatically from RegInfo.
17541 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17542 SelectionDAG &DAG) const {
17543 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17544 const MachineFunction &MF = DAG.getMachineFunction();
17546 unsigned Reg = StringSwitch<unsigned>(RegName)
17547 .Case("esp", X86::ESP)
17548 .Case("rsp", X86::RSP)
17549 .Case("ebp", X86::EBP)
17550 .Case("rbp", X86::RBP)
17553 if (Reg == X86::EBP || Reg == X86::RBP) {
17554 if (!TFI.hasFP(MF))
17555 report_fatal_error("register " + StringRef(RegName) +
17556 " is allocatable: function has no frame pointer");
17559 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17560 unsigned FrameReg =
17561 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17562 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17563 "Invalid Frame Register!");
17571 report_fatal_error("Invalid register name global variable");
17574 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17575 SelectionDAG &DAG) const {
17576 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17577 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17580 unsigned X86TargetLowering::getExceptionPointerRegister(
17581 const Constant *PersonalityFn) const {
17582 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17583 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17585 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17588 unsigned X86TargetLowering::getExceptionSelectorRegister(
17589 const Constant *PersonalityFn) const {
17590 // Funclet personalities don't use selectors (the runtime does the selection).
17591 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17592 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17595 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17596 SDValue Chain = Op.getOperand(0);
17597 SDValue Offset = Op.getOperand(1);
17598 SDValue Handler = Op.getOperand(2);
17601 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17602 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17603 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17604 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17605 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17606 "Invalid Frame Register!");
17607 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17608 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17610 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17611 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17613 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17614 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17616 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17618 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17619 DAG.getRegister(StoreAddrReg, PtrVT));
17622 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17623 SelectionDAG &DAG) const {
17625 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17626 DAG.getVTList(MVT::i32, MVT::Other),
17627 Op.getOperand(0), Op.getOperand(1));
17630 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17631 SelectionDAG &DAG) const {
17633 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17634 Op.getOperand(0), Op.getOperand(1));
17637 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17638 return Op.getOperand(0);
17641 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17642 SelectionDAG &DAG) const {
17643 SDValue Root = Op.getOperand(0);
17644 SDValue Trmp = Op.getOperand(1); // trampoline
17645 SDValue FPtr = Op.getOperand(2); // nested function
17646 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17649 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17650 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17652 if (Subtarget->is64Bit()) {
17653 SDValue OutChains[6];
17655 // Large code-model.
17656 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17657 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17659 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17660 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17662 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17664 // Load the pointer to the nested function into R11.
17665 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17666 SDValue Addr = Trmp;
17667 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17668 Addr, MachinePointerInfo(TrmpAddr),
17671 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17672 DAG.getConstant(2, dl, MVT::i64));
17673 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17674 MachinePointerInfo(TrmpAddr, 2),
17677 // Load the 'nest' parameter value into R10.
17678 // R10 is specified in X86CallingConv.td
17679 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17680 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17681 DAG.getConstant(10, dl, MVT::i64));
17682 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17683 Addr, MachinePointerInfo(TrmpAddr, 10),
17686 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17687 DAG.getConstant(12, dl, MVT::i64));
17688 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17689 MachinePointerInfo(TrmpAddr, 12),
17692 // Jump to the nested function.
17693 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17694 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17695 DAG.getConstant(20, dl, MVT::i64));
17696 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17697 Addr, MachinePointerInfo(TrmpAddr, 20),
17700 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17701 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17702 DAG.getConstant(22, dl, MVT::i64));
17703 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17704 Addr, MachinePointerInfo(TrmpAddr, 22),
17707 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17709 const Function *Func =
17710 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17711 CallingConv::ID CC = Func->getCallingConv();
17716 llvm_unreachable("Unsupported calling convention");
17717 case CallingConv::C:
17718 case CallingConv::X86_StdCall: {
17719 // Pass 'nest' parameter in ECX.
17720 // Must be kept in sync with X86CallingConv.td
17721 NestReg = X86::ECX;
17723 // Check that ECX wasn't needed by an 'inreg' parameter.
17724 FunctionType *FTy = Func->getFunctionType();
17725 const AttributeSet &Attrs = Func->getAttributes();
17727 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17728 unsigned InRegCount = 0;
17731 for (FunctionType::param_iterator I = FTy->param_begin(),
17732 E = FTy->param_end(); I != E; ++I, ++Idx)
17733 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17734 auto &DL = DAG.getDataLayout();
17735 // FIXME: should only count parameters that are lowered to integers.
17736 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17739 if (InRegCount > 2) {
17740 report_fatal_error("Nest register in use - reduce number of inreg"
17746 case CallingConv::X86_FastCall:
17747 case CallingConv::X86_ThisCall:
17748 case CallingConv::Fast:
17749 // Pass 'nest' parameter in EAX.
17750 // Must be kept in sync with X86CallingConv.td
17751 NestReg = X86::EAX;
17755 SDValue OutChains[4];
17756 SDValue Addr, Disp;
17758 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17759 DAG.getConstant(10, dl, MVT::i32));
17760 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17762 // This is storing the opcode for MOV32ri.
17763 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17764 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17765 OutChains[0] = DAG.getStore(Root, dl,
17766 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17767 Trmp, MachinePointerInfo(TrmpAddr),
17770 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17771 DAG.getConstant(1, dl, MVT::i32));
17772 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17773 MachinePointerInfo(TrmpAddr, 1),
17776 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17777 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17778 DAG.getConstant(5, dl, MVT::i32));
17779 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17780 Addr, MachinePointerInfo(TrmpAddr, 5),
17783 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17784 DAG.getConstant(6, dl, MVT::i32));
17785 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17786 MachinePointerInfo(TrmpAddr, 6),
17789 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17793 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17794 SelectionDAG &DAG) const {
17796 The rounding mode is in bits 11:10 of FPSR, and has the following
17798 00 Round to nearest
17803 FLT_ROUNDS, on the other hand, expects the following:
17810 To perform the conversion, we do:
17811 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17814 MachineFunction &MF = DAG.getMachineFunction();
17815 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17816 unsigned StackAlignment = TFI.getStackAlignment();
17817 MVT VT = Op.getSimpleValueType();
17820 // Save FP Control Word to stack slot
17821 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17822 SDValue StackSlot =
17823 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17825 MachineMemOperand *MMO =
17826 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17827 MachineMemOperand::MOStore, 2, 2);
17829 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17830 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17831 DAG.getVTList(MVT::Other),
17832 Ops, MVT::i16, MMO);
17834 // Load FP Control Word from stack slot
17835 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17836 MachinePointerInfo(), false, false, false, 0);
17838 // Transform as necessary
17840 DAG.getNode(ISD::SRL, DL, MVT::i16,
17841 DAG.getNode(ISD::AND, DL, MVT::i16,
17842 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17843 DAG.getConstant(11, DL, MVT::i8));
17845 DAG.getNode(ISD::SRL, DL, MVT::i16,
17846 DAG.getNode(ISD::AND, DL, MVT::i16,
17847 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17848 DAG.getConstant(9, DL, MVT::i8));
17851 DAG.getNode(ISD::AND, DL, MVT::i16,
17852 DAG.getNode(ISD::ADD, DL, MVT::i16,
17853 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17854 DAG.getConstant(1, DL, MVT::i16)),
17855 DAG.getConstant(3, DL, MVT::i16));
17857 return DAG.getNode((VT.getSizeInBits() < 16 ?
17858 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17861 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17863 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17864 // to 512-bit vector.
17865 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17866 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17867 // split the vector, perform operation on it's Lo a Hi part and
17868 // concatenate the results.
17869 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17871 MVT VT = Op.getSimpleValueType();
17872 MVT EltVT = VT.getVectorElementType();
17873 unsigned NumElems = VT.getVectorNumElements();
17875 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17876 // Extend to 512 bit vector.
17877 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17878 "Unsupported value type for operation");
17880 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17881 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17882 DAG.getUNDEF(NewVT),
17884 DAG.getIntPtrConstant(0, dl));
17885 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17887 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17888 DAG.getIntPtrConstant(0, dl));
17891 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17892 "Unsupported element type");
17894 if (16 < NumElems) {
17895 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17897 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17898 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17900 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17901 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17903 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17906 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17908 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17909 "Unsupported value type for operation");
17911 // Use native supported vector instruction vplzcntd.
17912 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17913 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17914 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17915 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17917 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17920 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17921 SelectionDAG &DAG) {
17922 MVT VT = Op.getSimpleValueType();
17924 unsigned NumBits = VT.getSizeInBits();
17927 if (VT.isVector() && Subtarget->hasAVX512())
17928 return LowerVectorCTLZ_AVX512(Op, DAG);
17930 Op = Op.getOperand(0);
17931 if (VT == MVT::i8) {
17932 // Zero extend to i32 since there is not an i8 bsr.
17934 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17937 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17938 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17939 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17941 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17944 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17945 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17948 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17950 // Finally xor with NumBits-1.
17951 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17952 DAG.getConstant(NumBits - 1, dl, OpVT));
17955 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17959 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17960 SelectionDAG &DAG) {
17961 MVT VT = Op.getSimpleValueType();
17963 unsigned NumBits = VT.getSizeInBits();
17966 if (VT.isVector() && Subtarget->hasAVX512())
17967 return LowerVectorCTLZ_AVX512(Op, DAG);
17969 Op = Op.getOperand(0);
17970 if (VT == MVT::i8) {
17971 // Zero extend to i32 since there is not an i8 bsr.
17973 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17976 // Issue a bsr (scan bits in reverse).
17977 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17978 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17980 // And xor with NumBits-1.
17981 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17982 DAG.getConstant(NumBits - 1, dl, OpVT));
17985 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17989 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17990 MVT VT = Op.getSimpleValueType();
17991 unsigned NumBits = VT.getScalarSizeInBits();
17994 if (VT.isVector()) {
17995 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17997 SDValue N0 = Op.getOperand(0);
17998 SDValue Zero = DAG.getConstant(0, dl, VT);
18000 // lsb(x) = (x & -x)
18001 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
18002 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
18004 // cttz_undef(x) = (width - 1) - ctlz(lsb)
18005 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
18006 TLI.isOperationLegal(ISD::CTLZ, VT)) {
18007 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
18008 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
18009 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
18012 // cttz(x) = ctpop(lsb - 1)
18013 SDValue One = DAG.getConstant(1, dl, VT);
18014 return DAG.getNode(ISD::CTPOP, dl, VT,
18015 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
18018 assert(Op.getOpcode() == ISD::CTTZ &&
18019 "Only scalar CTTZ requires custom lowering");
18021 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18022 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18023 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
18025 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18028 DAG.getConstant(NumBits, dl, VT),
18029 DAG.getConstant(X86::COND_E, dl, MVT::i8),
18032 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18035 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18036 // ones, and then concatenate the result back.
18037 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18038 MVT VT = Op.getSimpleValueType();
18040 assert(VT.is256BitVector() && VT.isInteger() &&
18041 "Unsupported value type for operation");
18043 unsigned NumElems = VT.getVectorNumElements();
18046 // Extract the LHS vectors
18047 SDValue LHS = Op.getOperand(0);
18048 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18049 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18051 // Extract the RHS vectors
18052 SDValue RHS = Op.getOperand(1);
18053 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18054 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18056 MVT EltVT = VT.getVectorElementType();
18057 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18059 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18060 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18061 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18064 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18065 if (Op.getValueType() == MVT::i1)
18066 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
18067 Op.getOperand(0), Op.getOperand(1));
18068 assert(Op.getSimpleValueType().is256BitVector() &&
18069 Op.getSimpleValueType().isInteger() &&
18070 "Only handle AVX 256-bit vector integer operation");
18071 return Lower256IntArith(Op, DAG);
18074 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18075 if (Op.getValueType() == MVT::i1)
18076 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
18077 Op.getOperand(0), Op.getOperand(1));
18078 assert(Op.getSimpleValueType().is256BitVector() &&
18079 Op.getSimpleValueType().isInteger() &&
18080 "Only handle AVX 256-bit vector integer operation");
18081 return Lower256IntArith(Op, DAG);
18084 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
18085 assert(Op.getSimpleValueType().is256BitVector() &&
18086 Op.getSimpleValueType().isInteger() &&
18087 "Only handle AVX 256-bit vector integer operation");
18088 return Lower256IntArith(Op, DAG);
18091 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18092 SelectionDAG &DAG) {
18094 MVT VT = Op.getSimpleValueType();
18097 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
18099 // Decompose 256-bit ops into smaller 128-bit ops.
18100 if (VT.is256BitVector() && !Subtarget->hasInt256())
18101 return Lower256IntArith(Op, DAG);
18103 SDValue A = Op.getOperand(0);
18104 SDValue B = Op.getOperand(1);
18106 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
18107 // pairs, multiply and truncate.
18108 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
18109 if (Subtarget->hasInt256()) {
18110 if (VT == MVT::v32i8) {
18111 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
18112 SDValue Lo = DAG.getIntPtrConstant(0, dl);
18113 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
18114 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
18115 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
18116 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
18117 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
18118 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18119 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
18120 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
18123 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
18124 return DAG.getNode(
18125 ISD::TRUNCATE, dl, VT,
18126 DAG.getNode(ISD::MUL, dl, ExVT,
18127 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
18128 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
18131 assert(VT == MVT::v16i8 &&
18132 "Pre-AVX2 support only supports v16i8 multiplication");
18133 MVT ExVT = MVT::v8i16;
18135 // Extract the lo parts and sign extend to i16
18137 if (Subtarget->hasSSE41()) {
18138 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
18139 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
18141 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
18142 -1, 4, -1, 5, -1, 6, -1, 7};
18143 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18144 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18145 ALo = DAG.getBitcast(ExVT, ALo);
18146 BLo = DAG.getBitcast(ExVT, BLo);
18147 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
18148 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
18151 // Extract the hi parts and sign extend to i16
18153 if (Subtarget->hasSSE41()) {
18154 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
18155 -1, -1, -1, -1, -1, -1, -1, -1};
18156 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18157 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18158 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
18159 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
18161 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
18162 -1, 12, -1, 13, -1, 14, -1, 15};
18163 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18164 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18165 AHi = DAG.getBitcast(ExVT, AHi);
18166 BHi = DAG.getBitcast(ExVT, BHi);
18167 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
18168 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
18171 // Multiply, mask the lower 8bits of the lo/hi results and pack
18172 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
18173 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
18174 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
18175 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
18176 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18179 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18180 if (VT == MVT::v4i32) {
18181 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18182 "Should not custom lower when pmuldq is available!");
18184 // Extract the odd parts.
18185 static const int UnpackMask[] = { 1, -1, 3, -1 };
18186 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18187 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18189 // Multiply the even parts.
18190 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18191 // Now multiply odd parts.
18192 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18194 Evens = DAG.getBitcast(VT, Evens);
18195 Odds = DAG.getBitcast(VT, Odds);
18197 // Merge the two vectors back together with a shuffle. This expands into 2
18199 static const int ShufMask[] = { 0, 4, 2, 6 };
18200 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18203 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18204 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18206 // Ahi = psrlqi(a, 32);
18207 // Bhi = psrlqi(b, 32);
18209 // AloBlo = pmuludq(a, b);
18210 // AloBhi = pmuludq(a, Bhi);
18211 // AhiBlo = pmuludq(Ahi, b);
18213 // AloBhi = psllqi(AloBhi, 32);
18214 // AhiBlo = psllqi(AhiBlo, 32);
18215 // return AloBlo + AloBhi + AhiBlo;
18217 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18218 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18220 SDValue AhiBlo = Ahi;
18221 SDValue AloBhi = Bhi;
18222 // Bit cast to 32-bit vectors for MULUDQ
18223 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18224 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18225 A = DAG.getBitcast(MulVT, A);
18226 B = DAG.getBitcast(MulVT, B);
18227 Ahi = DAG.getBitcast(MulVT, Ahi);
18228 Bhi = DAG.getBitcast(MulVT, Bhi);
18230 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18231 // After shifting right const values the result may be all-zero.
18232 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18233 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18234 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18236 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18237 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18238 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18241 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18242 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18245 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18246 assert(Subtarget->isTargetWin64() && "Unexpected target");
18247 EVT VT = Op.getValueType();
18248 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18249 "Unexpected return type for lowering");
18253 switch (Op->getOpcode()) {
18254 default: llvm_unreachable("Unexpected request for libcall!");
18255 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18256 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18257 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18258 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18259 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18260 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18264 SDValue InChain = DAG.getEntryNode();
18266 TargetLowering::ArgListTy Args;
18267 TargetLowering::ArgListEntry Entry;
18268 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18269 EVT ArgVT = Op->getOperand(i).getValueType();
18270 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18271 "Unexpected argument type for lowering");
18272 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18273 Entry.Node = StackPtr;
18274 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18276 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18277 Entry.Ty = PointerType::get(ArgTy,0);
18278 Entry.isSExt = false;
18279 Entry.isZExt = false;
18280 Args.push_back(Entry);
18283 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18284 getPointerTy(DAG.getDataLayout()));
18286 TargetLowering::CallLoweringInfo CLI(DAG);
18287 CLI.setDebugLoc(dl).setChain(InChain)
18288 .setCallee(getLibcallCallingConv(LC),
18289 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18290 Callee, std::move(Args), 0)
18291 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18293 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18294 return DAG.getBitcast(VT, CallInfo.first);
18297 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18298 SelectionDAG &DAG) {
18299 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18300 MVT VT = Op0.getSimpleValueType();
18303 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18304 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18306 // PMULxD operations multiply each even value (starting at 0) of LHS with
18307 // the related value of RHS and produce a widen result.
18308 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18309 // => <2 x i64> <ae|cg>
18311 // In other word, to have all the results, we need to perform two PMULxD:
18312 // 1. one with the even values.
18313 // 2. one with the odd values.
18314 // To achieve #2, with need to place the odd values at an even position.
18316 // Place the odd value at an even position (basically, shift all values 1
18317 // step to the left):
18318 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18319 // <a|b|c|d> => <b|undef|d|undef>
18320 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18321 // <e|f|g|h> => <f|undef|h|undef>
18322 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18324 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18326 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18327 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18329 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18330 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18331 // => <2 x i64> <ae|cg>
18332 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18333 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18334 // => <2 x i64> <bf|dh>
18335 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18337 // Shuffle it back into the right order.
18338 SDValue Highs, Lows;
18339 if (VT == MVT::v8i32) {
18340 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18341 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18342 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18343 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18345 const int HighMask[] = {1, 5, 3, 7};
18346 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18347 const int LowMask[] = {0, 4, 2, 6};
18348 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18351 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18352 // unsigned multiply.
18353 if (IsSigned && !Subtarget->hasSSE41()) {
18354 SDValue ShAmt = DAG.getConstant(
18356 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18357 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18358 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18359 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18360 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18362 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18363 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18366 // The first result of MUL_LOHI is actually the low value, followed by the
18368 SDValue Ops[] = {Lows, Highs};
18369 return DAG.getMergeValues(Ops, dl);
18372 // Return true if the required (according to Opcode) shift-imm form is natively
18373 // supported by the Subtarget
18374 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18376 if (VT.getScalarSizeInBits() < 16)
18379 if (VT.is512BitVector() &&
18380 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18383 bool LShift = VT.is128BitVector() ||
18384 (VT.is256BitVector() && Subtarget->hasInt256());
18386 bool AShift = LShift && (Subtarget->hasVLX() ||
18387 (VT != MVT::v2i64 && VT != MVT::v4i64));
18388 return (Opcode == ISD::SRA) ? AShift : LShift;
18391 // The shift amount is a variable, but it is the same for all vector lanes.
18392 // These instructions are defined together with shift-immediate.
18394 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18396 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18399 // Return true if the required (according to Opcode) variable-shift form is
18400 // natively supported by the Subtarget
18401 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18404 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18407 // vXi16 supported only on AVX-512, BWI
18408 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18411 if (VT.is512BitVector() || Subtarget->hasVLX())
18414 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18415 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18416 return (Opcode == ISD::SRA) ? AShift : LShift;
18419 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18420 const X86Subtarget *Subtarget) {
18421 MVT VT = Op.getSimpleValueType();
18423 SDValue R = Op.getOperand(0);
18424 SDValue Amt = Op.getOperand(1);
18426 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18427 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18429 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18430 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18431 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18432 SDValue Ex = DAG.getBitcast(ExVT, R);
18434 if (ShiftAmt >= 32) {
18435 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18437 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18438 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18439 ShiftAmt - 32, DAG);
18440 if (VT == MVT::v2i64)
18441 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18442 if (VT == MVT::v4i64)
18443 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18444 {9, 1, 11, 3, 13, 5, 15, 7});
18446 // SRA upper i32, SHL whole i64 and select lower i32.
18447 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18450 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18451 Lower = DAG.getBitcast(ExVT, Lower);
18452 if (VT == MVT::v2i64)
18453 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18454 if (VT == MVT::v4i64)
18455 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18456 {8, 1, 10, 3, 12, 5, 14, 7});
18458 return DAG.getBitcast(VT, Ex);
18461 // Optimize shl/srl/sra with constant shift amount.
18462 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18463 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18464 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18466 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18467 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18469 // i64 SRA needs to be performed as partial shifts.
18470 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18471 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18472 return ArithmeticShiftRight64(ShiftAmt);
18474 if (VT == MVT::v16i8 ||
18475 (Subtarget->hasInt256() && VT == MVT::v32i8) ||
18476 VT == MVT::v64i8) {
18477 unsigned NumElts = VT.getVectorNumElements();
18478 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18480 // Simple i8 add case
18481 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18482 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18484 // ashr(R, 7) === cmp_slt(R, 0)
18485 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18486 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18487 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18490 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18491 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18494 if (Op.getOpcode() == ISD::SHL) {
18495 // Make a large shift.
18496 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18498 SHL = DAG.getBitcast(VT, SHL);
18499 // Zero out the rightmost bits.
18500 return DAG.getNode(ISD::AND, dl, VT, SHL,
18501 DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, VT));
18503 if (Op.getOpcode() == ISD::SRL) {
18504 // Make a large shift.
18505 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18507 SRL = DAG.getBitcast(VT, SRL);
18508 // Zero out the leftmost bits.
18509 return DAG.getNode(ISD::AND, dl, VT, SRL,
18510 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, VT));
18512 if (Op.getOpcode() == ISD::SRA) {
18513 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18514 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18516 SDValue Mask = DAG.getConstant(128 >> ShiftAmt, dl, VT);
18517 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18518 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18521 llvm_unreachable("Unknown shift opcode.");
18526 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18527 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18528 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18530 // Peek through any splat that was introduced for i64 shift vectorization.
18531 int SplatIndex = -1;
18532 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18533 if (SVN->isSplat()) {
18534 SplatIndex = SVN->getSplatIndex();
18535 Amt = Amt.getOperand(0);
18536 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18537 "Splat shuffle referencing second operand");
18540 if (Amt.getOpcode() != ISD::BITCAST ||
18541 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18544 Amt = Amt.getOperand(0);
18545 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18546 VT.getVectorNumElements();
18547 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18548 uint64_t ShiftAmt = 0;
18549 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18550 for (unsigned i = 0; i != Ratio; ++i) {
18551 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18555 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18558 // Check remaining shift amounts (if not a splat).
18559 if (SplatIndex < 0) {
18560 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18561 uint64_t ShAmt = 0;
18562 for (unsigned j = 0; j != Ratio; ++j) {
18563 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18567 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18569 if (ShAmt != ShiftAmt)
18574 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18575 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18577 if (Op.getOpcode() == ISD::SRA)
18578 return ArithmeticShiftRight64(ShiftAmt);
18584 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18585 const X86Subtarget* Subtarget) {
18586 MVT VT = Op.getSimpleValueType();
18588 SDValue R = Op.getOperand(0);
18589 SDValue Amt = Op.getOperand(1);
18591 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18592 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18594 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18595 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18597 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18599 MVT EltVT = VT.getVectorElementType();
18601 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18602 // Check if this build_vector node is doing a splat.
18603 // If so, then set BaseShAmt equal to the splat value.
18604 BaseShAmt = BV->getSplatValue();
18605 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18606 BaseShAmt = SDValue();
18608 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18609 Amt = Amt.getOperand(0);
18611 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18612 if (SVN && SVN->isSplat()) {
18613 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18614 SDValue InVec = Amt.getOperand(0);
18615 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18616 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18617 "Unexpected shuffle index found!");
18618 BaseShAmt = InVec.getOperand(SplatIdx);
18619 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18620 if (ConstantSDNode *C =
18621 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18622 if (C->getZExtValue() == SplatIdx)
18623 BaseShAmt = InVec.getOperand(1);
18628 // Avoid introducing an extract element from a shuffle.
18629 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18630 DAG.getIntPtrConstant(SplatIdx, dl));
18634 if (BaseShAmt.getNode()) {
18635 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18636 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18637 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18638 else if (EltVT.bitsLT(MVT::i32))
18639 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18641 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18645 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18646 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18647 Amt.getOpcode() == ISD::BITCAST &&
18648 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18649 Amt = Amt.getOperand(0);
18650 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18651 VT.getVectorNumElements();
18652 std::vector<SDValue> Vals(Ratio);
18653 for (unsigned i = 0; i != Ratio; ++i)
18654 Vals[i] = Amt.getOperand(i);
18655 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18656 for (unsigned j = 0; j != Ratio; ++j)
18657 if (Vals[j] != Amt.getOperand(i + j))
18661 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18662 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18667 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18668 SelectionDAG &DAG) {
18669 MVT VT = Op.getSimpleValueType();
18671 SDValue R = Op.getOperand(0);
18672 SDValue Amt = Op.getOperand(1);
18674 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18675 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18677 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18680 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18683 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18686 // XOP has 128-bit variable logical/arithmetic shifts.
18687 // +ve/-ve Amt = shift left/right.
18688 if (Subtarget->hasXOP() &&
18689 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18690 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18691 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18692 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18693 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18695 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18696 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18697 if (Op.getOpcode() == ISD::SRA)
18698 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18701 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18702 // shifts per-lane and then shuffle the partial results back together.
18703 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18704 // Splat the shift amounts so the scalar shifts above will catch it.
18705 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18706 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18707 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18708 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18709 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18712 // i64 vector arithmetic shift can be emulated with the transform:
18713 // M = lshr(SIGN_BIT, Amt)
18714 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18715 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18716 Op.getOpcode() == ISD::SRA) {
18717 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18718 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18719 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18720 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18721 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18725 // If possible, lower this packed shift into a vector multiply instead of
18726 // expanding it into a sequence of scalar shifts.
18727 // Do this only if the vector shift count is a constant build_vector.
18728 if (Op.getOpcode() == ISD::SHL &&
18729 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18730 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18731 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18732 SmallVector<SDValue, 8> Elts;
18733 MVT SVT = VT.getVectorElementType();
18734 unsigned SVTBits = SVT.getSizeInBits();
18735 APInt One(SVTBits, 1);
18736 unsigned NumElems = VT.getVectorNumElements();
18738 for (unsigned i=0; i !=NumElems; ++i) {
18739 SDValue Op = Amt->getOperand(i);
18740 if (Op->getOpcode() == ISD::UNDEF) {
18741 Elts.push_back(Op);
18745 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18746 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18747 uint64_t ShAmt = C.getZExtValue();
18748 if (ShAmt >= SVTBits) {
18749 Elts.push_back(DAG.getUNDEF(SVT));
18752 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18754 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18755 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18758 // Lower SHL with variable shift amount.
18759 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18760 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18762 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18763 DAG.getConstant(0x3f800000U, dl, VT));
18764 Op = DAG.getBitcast(MVT::v4f32, Op);
18765 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18766 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18769 // If possible, lower this shift as a sequence of two shifts by
18770 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18772 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18774 // Could be rewritten as:
18775 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18777 // The advantage is that the two shifts from the example would be
18778 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18779 // the vector shift into four scalar shifts plus four pairs of vector
18781 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18782 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18783 unsigned TargetOpcode = X86ISD::MOVSS;
18784 bool CanBeSimplified;
18785 // The splat value for the first packed shift (the 'X' from the example).
18786 SDValue Amt1 = Amt->getOperand(0);
18787 // The splat value for the second packed shift (the 'Y' from the example).
18788 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18789 Amt->getOperand(2);
18791 // See if it is possible to replace this node with a sequence of
18792 // two shifts followed by a MOVSS/MOVSD
18793 if (VT == MVT::v4i32) {
18794 // Check if it is legal to use a MOVSS.
18795 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18796 Amt2 == Amt->getOperand(3);
18797 if (!CanBeSimplified) {
18798 // Otherwise, check if we can still simplify this node using a MOVSD.
18799 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18800 Amt->getOperand(2) == Amt->getOperand(3);
18801 TargetOpcode = X86ISD::MOVSD;
18802 Amt2 = Amt->getOperand(2);
18805 // Do similar checks for the case where the machine value type
18807 CanBeSimplified = Amt1 == Amt->getOperand(1);
18808 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18809 CanBeSimplified = Amt2 == Amt->getOperand(i);
18811 if (!CanBeSimplified) {
18812 TargetOpcode = X86ISD::MOVSD;
18813 CanBeSimplified = true;
18814 Amt2 = Amt->getOperand(4);
18815 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18816 CanBeSimplified = Amt1 == Amt->getOperand(i);
18817 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18818 CanBeSimplified = Amt2 == Amt->getOperand(j);
18822 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18823 isa<ConstantSDNode>(Amt2)) {
18824 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18825 MVT CastVT = MVT::v4i32;
18827 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18828 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18830 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18831 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18832 if (TargetOpcode == X86ISD::MOVSD)
18833 CastVT = MVT::v2i64;
18834 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18835 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18836 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18838 return DAG.getBitcast(VT, Result);
18842 // v4i32 Non Uniform Shifts.
18843 // If the shift amount is constant we can shift each lane using the SSE2
18844 // immediate shifts, else we need to zero-extend each lane to the lower i64
18845 // and shift using the SSE2 variable shifts.
18846 // The separate results can then be blended together.
18847 if (VT == MVT::v4i32) {
18848 unsigned Opc = Op.getOpcode();
18849 SDValue Amt0, Amt1, Amt2, Amt3;
18850 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18851 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18852 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18853 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18854 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18856 // ISD::SHL is handled above but we include it here for completeness.
18859 llvm_unreachable("Unknown target vector shift node");
18861 Opc = X86ISD::VSHL;
18864 Opc = X86ISD::VSRL;
18867 Opc = X86ISD::VSRA;
18870 // The SSE2 shifts use the lower i64 as the same shift amount for
18871 // all lanes and the upper i64 is ignored. These shuffle masks
18872 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18873 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18874 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18875 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18876 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18877 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18880 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18881 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18882 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18883 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18884 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18885 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18886 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18889 if (VT == MVT::v16i8 ||
18890 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18891 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18892 unsigned ShiftOpcode = Op->getOpcode();
18894 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18895 // On SSE41 targets we make use of the fact that VSELECT lowers
18896 // to PBLENDVB which selects bytes based just on the sign bit.
18897 if (Subtarget->hasSSE41()) {
18898 V0 = DAG.getBitcast(VT, V0);
18899 V1 = DAG.getBitcast(VT, V1);
18900 Sel = DAG.getBitcast(VT, Sel);
18901 return DAG.getBitcast(SelVT,
18902 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18904 // On pre-SSE41 targets we test for the sign bit by comparing to
18905 // zero - a negative value will set all bits of the lanes to true
18906 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18907 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18908 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18909 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18912 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18913 // We can safely do this using i16 shifts as we're only interested in
18914 // the 3 lower bits of each byte.
18915 Amt = DAG.getBitcast(ExtVT, Amt);
18916 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18917 Amt = DAG.getBitcast(VT, Amt);
18919 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18920 // r = VSELECT(r, shift(r, 4), a);
18922 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18923 R = SignBitSelect(VT, Amt, M, R);
18926 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18928 // r = VSELECT(r, shift(r, 2), a);
18929 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18930 R = SignBitSelect(VT, Amt, M, R);
18933 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18935 // return VSELECT(r, shift(r, 1), a);
18936 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18937 R = SignBitSelect(VT, Amt, M, R);
18941 if (Op->getOpcode() == ISD::SRA) {
18942 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18943 // so we can correctly sign extend. We don't care what happens to the
18945 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18946 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18947 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18948 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18949 ALo = DAG.getBitcast(ExtVT, ALo);
18950 AHi = DAG.getBitcast(ExtVT, AHi);
18951 RLo = DAG.getBitcast(ExtVT, RLo);
18952 RHi = DAG.getBitcast(ExtVT, RHi);
18954 // r = VSELECT(r, shift(r, 4), a);
18955 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18956 DAG.getConstant(4, dl, ExtVT));
18957 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18958 DAG.getConstant(4, dl, ExtVT));
18959 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18960 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18963 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18964 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18966 // r = VSELECT(r, shift(r, 2), a);
18967 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18968 DAG.getConstant(2, dl, ExtVT));
18969 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18970 DAG.getConstant(2, dl, ExtVT));
18971 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18972 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18975 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18976 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18978 // r = VSELECT(r, shift(r, 1), a);
18979 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18980 DAG.getConstant(1, dl, ExtVT));
18981 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18982 DAG.getConstant(1, dl, ExtVT));
18983 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18984 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18986 // Logical shift the result back to the lower byte, leaving a zero upper
18988 // meaning that we can safely pack with PACKUSWB.
18990 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18992 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18993 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18997 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18998 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18999 // solution better.
19000 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
19001 MVT ExtVT = MVT::v8i32;
19003 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
19004 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
19005 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
19006 return DAG.getNode(ISD::TRUNCATE, dl, VT,
19007 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
19010 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
19011 MVT ExtVT = MVT::v8i32;
19012 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
19013 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
19014 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
19015 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
19016 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
19017 ALo = DAG.getBitcast(ExtVT, ALo);
19018 AHi = DAG.getBitcast(ExtVT, AHi);
19019 RLo = DAG.getBitcast(ExtVT, RLo);
19020 RHi = DAG.getBitcast(ExtVT, RHi);
19021 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
19022 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
19023 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
19024 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
19025 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
19028 if (VT == MVT::v8i16) {
19029 unsigned ShiftOpcode = Op->getOpcode();
19031 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
19032 // On SSE41 targets we make use of the fact that VSELECT lowers
19033 // to PBLENDVB which selects bytes based just on the sign bit.
19034 if (Subtarget->hasSSE41()) {
19035 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
19036 V0 = DAG.getBitcast(ExtVT, V0);
19037 V1 = DAG.getBitcast(ExtVT, V1);
19038 Sel = DAG.getBitcast(ExtVT, Sel);
19039 return DAG.getBitcast(
19040 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
19042 // On pre-SSE41 targets we splat the sign bit - a negative value will
19043 // set all bits of the lanes to true and VSELECT uses that in
19044 // its OR(AND(V0,C),AND(V1,~C)) lowering.
19046 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
19047 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
19050 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
19051 if (Subtarget->hasSSE41()) {
19052 // On SSE41 targets we need to replicate the shift mask in both
19053 // bytes for PBLENDVB.
19056 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
19057 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
19059 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
19062 // r = VSELECT(r, shift(r, 8), a);
19063 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
19064 R = SignBitSelect(Amt, M, R);
19067 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19069 // r = VSELECT(r, shift(r, 4), a);
19070 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
19071 R = SignBitSelect(Amt, M, R);
19074 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19076 // r = VSELECT(r, shift(r, 2), a);
19077 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
19078 R = SignBitSelect(Amt, M, R);
19081 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19083 // return VSELECT(r, shift(r, 1), a);
19084 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
19085 R = SignBitSelect(Amt, M, R);
19089 // Decompose 256-bit shifts into smaller 128-bit shifts.
19090 if (VT.is256BitVector()) {
19091 unsigned NumElems = VT.getVectorNumElements();
19092 MVT EltVT = VT.getVectorElementType();
19093 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
19095 // Extract the two vectors
19096 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
19097 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
19099 // Recreate the shift amount vectors
19100 SDValue Amt1, Amt2;
19101 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
19102 // Constant shift amount
19103 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
19104 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
19105 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
19107 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
19108 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
19110 // Variable shift amount
19111 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
19112 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
19115 // Issue new vector shifts for the smaller types
19116 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
19117 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
19119 // Concatenate the result back
19120 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
19126 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
19127 SelectionDAG &DAG) {
19128 MVT VT = Op.getSimpleValueType();
19130 SDValue R = Op.getOperand(0);
19131 SDValue Amt = Op.getOperand(1);
19133 assert(VT.isVector() && "Custom lowering only for vector rotates!");
19134 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
19135 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
19137 // XOP has 128-bit vector variable + immediate rotates.
19138 // +ve/-ve Amt = rotate left/right.
19140 // Split 256-bit integers.
19141 if (VT.is256BitVector())
19142 return Lower256IntArith(Op, DAG);
19144 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
19146 // Attempt to rotate by immediate.
19147 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
19148 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
19149 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
19150 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
19151 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
19152 DAG.getConstant(RotateAmt, DL, MVT::i8));
19156 // Use general rotate by variable (per-element).
19157 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
19160 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
19161 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
19162 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
19163 // looks for this combo and may remove the "setcc" instruction if the "setcc"
19164 // has only one use.
19165 SDNode *N = Op.getNode();
19166 SDValue LHS = N->getOperand(0);
19167 SDValue RHS = N->getOperand(1);
19168 unsigned BaseOp = 0;
19171 switch (Op.getOpcode()) {
19172 default: llvm_unreachable("Unknown ovf instruction!");
19174 // A subtract of one will be selected as a INC. Note that INC doesn't
19175 // set CF, so we can't do this for UADDO.
19176 if (isOneConstant(RHS)) {
19177 BaseOp = X86ISD::INC;
19178 Cond = X86::COND_O;
19181 BaseOp = X86ISD::ADD;
19182 Cond = X86::COND_O;
19185 BaseOp = X86ISD::ADD;
19186 Cond = X86::COND_B;
19189 // A subtract of one will be selected as a DEC. Note that DEC doesn't
19190 // set CF, so we can't do this for USUBO.
19191 if (isOneConstant(RHS)) {
19192 BaseOp = X86ISD::DEC;
19193 Cond = X86::COND_O;
19196 BaseOp = X86ISD::SUB;
19197 Cond = X86::COND_O;
19200 BaseOp = X86ISD::SUB;
19201 Cond = X86::COND_B;
19204 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19205 Cond = X86::COND_O;
19207 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19208 if (N->getValueType(0) == MVT::i8) {
19209 BaseOp = X86ISD::UMUL8;
19210 Cond = X86::COND_O;
19213 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19215 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19218 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19219 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19220 SDValue(Sum.getNode(), 2));
19222 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19226 // Also sets EFLAGS.
19227 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19228 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19231 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19232 DAG.getConstant(Cond, DL, MVT::i32),
19233 SDValue(Sum.getNode(), 1));
19235 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19238 /// Returns true if the operand type is exactly twice the native width, and
19239 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19240 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19241 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19242 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19243 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19246 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19247 else if (OpWidth == 128)
19248 return Subtarget->hasCmpxchg16b();
19253 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19254 return needsCmpXchgNb(SI->getValueOperand()->getType());
19257 // Note: this turns large loads into lock cmpxchg8b/16b.
19258 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19259 TargetLowering::AtomicExpansionKind
19260 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19261 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19262 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19263 : AtomicExpansionKind::None;
19266 TargetLowering::AtomicExpansionKind
19267 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19268 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19269 Type *MemType = AI->getType();
19271 // If the operand is too big, we must see if cmpxchg8/16b is available
19272 // and default to library calls otherwise.
19273 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19274 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19275 : AtomicExpansionKind::None;
19278 AtomicRMWInst::BinOp Op = AI->getOperation();
19281 llvm_unreachable("Unknown atomic operation");
19282 case AtomicRMWInst::Xchg:
19283 case AtomicRMWInst::Add:
19284 case AtomicRMWInst::Sub:
19285 // It's better to use xadd, xsub or xchg for these in all cases.
19286 return AtomicExpansionKind::None;
19287 case AtomicRMWInst::Or:
19288 case AtomicRMWInst::And:
19289 case AtomicRMWInst::Xor:
19290 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19291 // prefix to a normal instruction for these operations.
19292 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19293 : AtomicExpansionKind::None;
19294 case AtomicRMWInst::Nand:
19295 case AtomicRMWInst::Max:
19296 case AtomicRMWInst::Min:
19297 case AtomicRMWInst::UMax:
19298 case AtomicRMWInst::UMin:
19299 // These always require a non-trivial set of data operations on x86. We must
19300 // use a cmpxchg loop.
19301 return AtomicExpansionKind::CmpXChg;
19305 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19306 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19307 // no-sse2). There isn't any reason to disable it if the target processor
19309 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19313 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19314 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19315 Type *MemType = AI->getType();
19316 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19317 // there is no benefit in turning such RMWs into loads, and it is actually
19318 // harmful as it introduces a mfence.
19319 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19322 auto Builder = IRBuilder<>(AI);
19323 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19324 auto SynchScope = AI->getSynchScope();
19325 // We must restrict the ordering to avoid generating loads with Release or
19326 // ReleaseAcquire orderings.
19327 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19328 auto Ptr = AI->getPointerOperand();
19330 // Before the load we need a fence. Here is an example lifted from
19331 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19334 // x.store(1, relaxed);
19335 // r1 = y.fetch_add(0, release);
19337 // y.fetch_add(42, acquire);
19338 // r2 = x.load(relaxed);
19339 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19340 // lowered to just a load without a fence. A mfence flushes the store buffer,
19341 // making the optimization clearly correct.
19342 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19343 // otherwise, we might be able to be more aggressive on relaxed idempotent
19344 // rmw. In practice, they do not look useful, so we don't try to be
19345 // especially clever.
19346 if (SynchScope == SingleThread)
19347 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19348 // the IR level, so we must wrap it in an intrinsic.
19351 if (!hasMFENCE(*Subtarget))
19352 // FIXME: it might make sense to use a locked operation here but on a
19353 // different cache-line to prevent cache-line bouncing. In practice it
19354 // is probably a small win, and x86 processors without mfence are rare
19355 // enough that we do not bother.
19359 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19360 Builder.CreateCall(MFence, {});
19362 // Finally we can emit the atomic load.
19363 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19364 AI->getType()->getPrimitiveSizeInBits());
19365 Loaded->setAtomic(Order, SynchScope);
19366 AI->replaceAllUsesWith(Loaded);
19367 AI->eraseFromParent();
19371 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19372 SelectionDAG &DAG) {
19374 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19375 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19376 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19377 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19379 // The only fence that needs an instruction is a sequentially-consistent
19380 // cross-thread fence.
19381 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19382 if (hasMFENCE(*Subtarget))
19383 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19385 SDValue Chain = Op.getOperand(0);
19386 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19388 DAG.getRegister(X86::ESP, MVT::i32), // Base
19389 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19390 DAG.getRegister(0, MVT::i32), // Index
19391 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19392 DAG.getRegister(0, MVT::i32), // Segment.
19396 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19397 return SDValue(Res, 0);
19400 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19401 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19404 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19405 SelectionDAG &DAG) {
19406 MVT T = Op.getSimpleValueType();
19410 switch(T.SimpleTy) {
19411 default: llvm_unreachable("Invalid value type!");
19412 case MVT::i8: Reg = X86::AL; size = 1; break;
19413 case MVT::i16: Reg = X86::AX; size = 2; break;
19414 case MVT::i32: Reg = X86::EAX; size = 4; break;
19416 assert(Subtarget->is64Bit() && "Node not type legal!");
19417 Reg = X86::RAX; size = 8;
19420 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19421 Op.getOperand(2), SDValue());
19422 SDValue Ops[] = { cpIn.getValue(0),
19425 DAG.getTargetConstant(size, DL, MVT::i8),
19426 cpIn.getValue(1) };
19427 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19428 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19429 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19433 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19434 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19435 MVT::i32, cpOut.getValue(2));
19436 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19437 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19440 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19441 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19442 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19446 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19447 SelectionDAG &DAG) {
19448 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19449 MVT DstVT = Op.getSimpleValueType();
19451 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19452 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19453 if (DstVT != MVT::f64)
19454 // This conversion needs to be expanded.
19457 SDValue InVec = Op->getOperand(0);
19459 unsigned NumElts = SrcVT.getVectorNumElements();
19460 MVT SVT = SrcVT.getVectorElementType();
19462 // Widen the vector in input in the case of MVT::v2i32.
19463 // Example: from MVT::v2i32 to MVT::v4i32.
19464 SmallVector<SDValue, 16> Elts;
19465 for (unsigned i = 0, e = NumElts; i != e; ++i)
19466 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19467 DAG.getIntPtrConstant(i, dl)));
19469 // Explicitly mark the extra elements as Undef.
19470 Elts.append(NumElts, DAG.getUNDEF(SVT));
19472 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19473 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19474 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19475 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19476 DAG.getIntPtrConstant(0, dl));
19479 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19480 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19481 assert((DstVT == MVT::i64 ||
19482 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19483 "Unexpected custom BITCAST");
19484 // i64 <=> MMX conversions are Legal.
19485 if (SrcVT==MVT::i64 && DstVT.isVector())
19487 if (DstVT==MVT::i64 && SrcVT.isVector())
19489 // MMX <=> MMX conversions are Legal.
19490 if (SrcVT.isVector() && DstVT.isVector())
19492 // All other conversions need to be expanded.
19496 /// Compute the horizontal sum of bytes in V for the elements of VT.
19498 /// Requires V to be a byte vector and VT to be an integer vector type with
19499 /// wider elements than V's type. The width of the elements of VT determines
19500 /// how many bytes of V are summed horizontally to produce each element of the
19502 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19503 const X86Subtarget *Subtarget,
19504 SelectionDAG &DAG) {
19506 MVT ByteVecVT = V.getSimpleValueType();
19507 MVT EltVT = VT.getVectorElementType();
19508 int NumElts = VT.getVectorNumElements();
19509 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19510 "Expected value to have byte element type.");
19511 assert(EltVT != MVT::i8 &&
19512 "Horizontal byte sum only makes sense for wider elements!");
19513 unsigned VecSize = VT.getSizeInBits();
19514 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19516 // PSADBW instruction horizontally add all bytes and leave the result in i64
19517 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19518 if (EltVT == MVT::i64) {
19519 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19520 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19521 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19522 return DAG.getBitcast(VT, V);
19525 if (EltVT == MVT::i32) {
19526 // We unpack the low half and high half into i32s interleaved with zeros so
19527 // that we can use PSADBW to horizontally sum them. The most useful part of
19528 // this is that it lines up the results of two PSADBW instructions to be
19529 // two v2i64 vectors which concatenated are the 4 population counts. We can
19530 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19531 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19532 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19533 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19535 // Do the horizontal sums into two v2i64s.
19536 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19537 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19538 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19539 DAG.getBitcast(ByteVecVT, Low), Zeros);
19540 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19541 DAG.getBitcast(ByteVecVT, High), Zeros);
19543 // Merge them together.
19544 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19545 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19546 DAG.getBitcast(ShortVecVT, Low),
19547 DAG.getBitcast(ShortVecVT, High));
19549 return DAG.getBitcast(VT, V);
19552 // The only element type left is i16.
19553 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19555 // To obtain pop count for each i16 element starting from the pop count for
19556 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19557 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19558 // directly supported.
19559 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19560 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19561 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19562 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19563 DAG.getBitcast(ByteVecVT, V));
19564 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19567 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19568 const X86Subtarget *Subtarget,
19569 SelectionDAG &DAG) {
19570 MVT VT = Op.getSimpleValueType();
19571 MVT EltVT = VT.getVectorElementType();
19572 unsigned VecSize = VT.getSizeInBits();
19574 // Implement a lookup table in register by using an algorithm based on:
19575 // http://wm.ite.pl/articles/sse-popcount.html
19577 // The general idea is that every lower byte nibble in the input vector is an
19578 // index into a in-register pre-computed pop count table. We then split up the
19579 // input vector in two new ones: (1) a vector with only the shifted-right
19580 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19581 // masked out higher ones) for each byte. PSHUB is used separately with both
19582 // to index the in-register table. Next, both are added and the result is a
19583 // i8 vector where each element contains the pop count for input byte.
19585 // To obtain the pop count for elements != i8, we follow up with the same
19586 // approach and use additional tricks as described below.
19588 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19589 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19590 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19591 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19593 int NumByteElts = VecSize / 8;
19594 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19595 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19596 SmallVector<SDValue, 16> LUTVec;
19597 for (int i = 0; i < NumByteElts; ++i)
19598 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19599 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19600 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19601 DAG.getConstant(0x0F, DL, MVT::i8));
19602 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19605 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19606 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19607 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19610 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19612 // The input vector is used as the shuffle mask that index elements into the
19613 // LUT. After counting low and high nibbles, add the vector to obtain the
19614 // final pop count per i8 element.
19615 SDValue HighPopCnt =
19616 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19617 SDValue LowPopCnt =
19618 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19619 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19621 if (EltVT == MVT::i8)
19624 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19627 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19628 const X86Subtarget *Subtarget,
19629 SelectionDAG &DAG) {
19630 MVT VT = Op.getSimpleValueType();
19631 assert(VT.is128BitVector() &&
19632 "Only 128-bit vector bitmath lowering supported.");
19634 int VecSize = VT.getSizeInBits();
19635 MVT EltVT = VT.getVectorElementType();
19636 int Len = EltVT.getSizeInBits();
19638 // This is the vectorized version of the "best" algorithm from
19639 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19640 // with a minor tweak to use a series of adds + shifts instead of vector
19641 // multiplications. Implemented for all integer vector types. We only use
19642 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19643 // much faster, even faster than using native popcnt instructions.
19645 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19646 MVT VT = V.getSimpleValueType();
19647 SmallVector<SDValue, 32> Shifters(
19648 VT.getVectorNumElements(),
19649 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19650 return DAG.getNode(OpCode, DL, VT, V,
19651 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19653 auto GetMask = [&](SDValue V, APInt Mask) {
19654 MVT VT = V.getSimpleValueType();
19655 SmallVector<SDValue, 32> Masks(
19656 VT.getVectorNumElements(),
19657 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19658 return DAG.getNode(ISD::AND, DL, VT, V,
19659 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19662 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19663 // x86, so set the SRL type to have elements at least i16 wide. This is
19664 // correct because all of our SRLs are followed immediately by a mask anyways
19665 // that handles any bits that sneak into the high bits of the byte elements.
19666 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19670 // v = v - ((v >> 1) & 0x55555555...)
19672 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19673 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19674 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19676 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19677 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19678 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19679 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19680 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19682 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19683 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19684 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19685 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19687 // At this point, V contains the byte-wise population count, and we are
19688 // merely doing a horizontal sum if necessary to get the wider element
19690 if (EltVT == MVT::i8)
19693 return LowerHorizontalByteSum(
19694 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19698 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19699 SelectionDAG &DAG) {
19700 MVT VT = Op.getSimpleValueType();
19701 // FIXME: Need to add AVX-512 support here!
19702 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19703 "Unknown CTPOP type to handle");
19704 SDLoc DL(Op.getNode());
19705 SDValue Op0 = Op.getOperand(0);
19707 if (!Subtarget->hasSSSE3()) {
19708 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19709 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19710 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19713 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19714 unsigned NumElems = VT.getVectorNumElements();
19716 // Extract each 128-bit vector, compute pop count and concat the result.
19717 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19718 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19720 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19721 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19722 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19725 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19728 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19729 SelectionDAG &DAG) {
19730 assert(Op.getSimpleValueType().isVector() &&
19731 "We only do custom lowering for vector population count.");
19732 return LowerVectorCTPOP(Op, Subtarget, DAG);
19735 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19736 SDNode *Node = Op.getNode();
19738 EVT T = Node->getValueType(0);
19739 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19740 DAG.getConstant(0, dl, T), Node->getOperand(2));
19741 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19742 cast<AtomicSDNode>(Node)->getMemoryVT(),
19743 Node->getOperand(0),
19744 Node->getOperand(1), negOp,
19745 cast<AtomicSDNode>(Node)->getMemOperand(),
19746 cast<AtomicSDNode>(Node)->getOrdering(),
19747 cast<AtomicSDNode>(Node)->getSynchScope());
19750 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19751 SDNode *Node = Op.getNode();
19753 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19755 // Convert seq_cst store -> xchg
19756 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19757 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19758 // (The only way to get a 16-byte store is cmpxchg16b)
19759 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19760 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19761 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19762 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19763 cast<AtomicSDNode>(Node)->getMemoryVT(),
19764 Node->getOperand(0),
19765 Node->getOperand(1), Node->getOperand(2),
19766 cast<AtomicSDNode>(Node)->getMemOperand(),
19767 cast<AtomicSDNode>(Node)->getOrdering(),
19768 cast<AtomicSDNode>(Node)->getSynchScope());
19769 return Swap.getValue(1);
19771 // Other atomic stores have a simple pattern.
19775 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19776 MVT VT = Op.getNode()->getSimpleValueType(0);
19778 // Let legalize expand this if it isn't a legal type yet.
19779 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19782 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19785 bool ExtraOp = false;
19786 switch (Op.getOpcode()) {
19787 default: llvm_unreachable("Invalid code");
19788 case ISD::ADDC: Opc = X86ISD::ADD; break;
19789 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19790 case ISD::SUBC: Opc = X86ISD::SUB; break;
19791 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19795 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19797 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19798 Op.getOperand(1), Op.getOperand(2));
19801 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19802 SelectionDAG &DAG) {
19803 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19805 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19806 // which returns the values as { float, float } (in XMM0) or
19807 // { double, double } (which is returned in XMM0, XMM1).
19809 SDValue Arg = Op.getOperand(0);
19810 EVT ArgVT = Arg.getValueType();
19811 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19813 TargetLowering::ArgListTy Args;
19814 TargetLowering::ArgListEntry Entry;
19818 Entry.isSExt = false;
19819 Entry.isZExt = false;
19820 Args.push_back(Entry);
19822 bool isF64 = ArgVT == MVT::f64;
19823 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19824 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19825 // the results are returned via SRet in memory.
19826 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19827 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19829 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19831 Type *RetTy = isF64
19832 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19833 : (Type*)VectorType::get(ArgTy, 4);
19835 TargetLowering::CallLoweringInfo CLI(DAG);
19836 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19837 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19839 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19842 // Returned in xmm0 and xmm1.
19843 return CallResult.first;
19845 // Returned in bits 0:31 and 32:64 xmm0.
19846 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19847 CallResult.first, DAG.getIntPtrConstant(0, dl));
19848 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19849 CallResult.first, DAG.getIntPtrConstant(1, dl));
19850 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19851 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19854 /// Widen a vector input to a vector of NVT. The
19855 /// input vector must have the same element type as NVT.
19856 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
19857 bool FillWithZeroes = false) {
19858 // Check if InOp already has the right width.
19859 MVT InVT = InOp.getSimpleValueType();
19863 if (InOp.isUndef())
19864 return DAG.getUNDEF(NVT);
19866 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
19867 "input and widen element type must match");
19869 unsigned InNumElts = InVT.getVectorNumElements();
19870 unsigned WidenNumElts = NVT.getVectorNumElements();
19871 assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&
19872 "Unexpected request for vector widening");
19874 EVT EltVT = NVT.getVectorElementType();
19877 if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&
19878 InOp.getNumOperands() == 2) {
19879 SDValue N1 = InOp.getOperand(1);
19880 if ((ISD::isBuildVectorAllZeros(N1.getNode()) && FillWithZeroes) ||
19882 InOp = InOp.getOperand(0);
19883 InVT = InOp.getSimpleValueType();
19884 InNumElts = InVT.getVectorNumElements();
19887 if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) ||
19888 ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
19889 SmallVector<SDValue, 16> Ops;
19890 for (unsigned i = 0; i < InNumElts; ++i)
19891 Ops.push_back(InOp.getOperand(i));
19893 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
19894 DAG.getUNDEF(EltVT);
19895 for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)
19896 Ops.push_back(FillVal);
19897 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
19899 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :
19901 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,
19902 InOp, DAG.getIntPtrConstant(0, dl));
19905 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19906 SelectionDAG &DAG) {
19907 assert(Subtarget->hasAVX512() &&
19908 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19910 // X86 scatter kills mask register, so its type should be added to
19911 // the list of return values.
19912 // If the "scatter" has 2 return values, it is already handled.
19913 if (Op.getNode()->getNumValues() == 2)
19916 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19917 SDValue Src = N->getValue();
19918 MVT VT = Src.getSimpleValueType();
19919 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19922 SDValue NewScatter;
19923 SDValue Index = N->getIndex();
19924 SDValue Mask = N->getMask();
19925 SDValue Chain = N->getChain();
19926 SDValue BasePtr = N->getBasePtr();
19927 MVT MemVT = N->getMemoryVT().getSimpleVT();
19928 MVT IndexVT = Index.getSimpleValueType();
19929 MVT MaskVT = Mask.getSimpleValueType();
19931 if (MemVT.getScalarSizeInBits() < VT.getScalarSizeInBits()) {
19932 // The v2i32 value was promoted to v2i64.
19933 // Now we "redo" the type legalizer's work and widen the original
19934 // v2i32 value to v4i32. The original v2i32 is retrieved from v2i64
19936 assert((MemVT == MVT::v2i32 && VT == MVT::v2i64) &&
19937 "Unexpected memory type");
19938 int ShuffleMask[] = {0, 2, -1, -1};
19939 Src = DAG.getVectorShuffle(MVT::v4i32, dl, DAG.getBitcast(MVT::v4i32, Src),
19940 DAG.getUNDEF(MVT::v4i32), ShuffleMask);
19941 // Now we have 4 elements instead of 2.
19942 // Expand the index.
19943 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), 4);
19944 Index = ExtendToType(Index, NewIndexVT, DAG);
19946 // Expand the mask with zeroes
19947 // Mask may be <2 x i64> or <2 x i1> at this moment
19948 assert((MaskVT == MVT::v2i1 || MaskVT == MVT::v2i64) &&
19949 "Unexpected mask type");
19950 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), 4);
19951 Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
19955 unsigned NumElts = VT.getVectorNumElements();
19956 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19957 !Index.getSimpleValueType().is512BitVector()) {
19958 // AVX512F supports only 512-bit vectors. Or data or index should
19959 // be 512 bit wide. If now the both index and data are 256-bit, but
19960 // the vector contains 8 elements, we just sign-extend the index
19961 if (IndexVT == MVT::v8i32)
19962 // Just extend index
19963 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19965 // The minimal number of elts in scatter is 8
19968 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), NumElts);
19969 // Use original index here, do not modify the index twice
19970 Index = ExtendToType(N->getIndex(), NewIndexVT, DAG);
19971 if (IndexVT.getScalarType() == MVT::i32)
19972 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19975 // At this point we have promoted mask operand
19976 assert(MaskVT.getScalarSizeInBits() >= 32 && "unexpected mask type");
19977 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), NumElts);
19978 // Use the original mask here, do not modify the mask twice
19979 Mask = ExtendToType(N->getMask(), ExtMaskVT, DAG, true);
19981 // The value that should be stored
19982 MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
19983 Src = ExtendToType(Src, NewVT, DAG);
19986 // If the mask is "wide" at this point - truncate it to i1 vector
19987 MVT BitMaskVT = MVT::getVectorVT(MVT::i1, NumElts);
19988 Mask = DAG.getNode(ISD::TRUNCATE, dl, BitMaskVT, Mask);
19990 // The mask is killed by scatter, add it to the values
19991 SDVTList VTs = DAG.getVTList(BitMaskVT, MVT::Other);
19992 SDValue Ops[] = {Chain, Src, Mask, BasePtr, Index};
19993 NewScatter = DAG.getMaskedScatter(VTs, N->getMemoryVT(), dl, Ops,
19994 N->getMemOperand());
19995 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19996 return SDValue(NewScatter.getNode(), 0);
19999 static SDValue LowerMLOAD(SDValue Op, const X86Subtarget *Subtarget,
20000 SelectionDAG &DAG) {
20002 MaskedLoadSDNode *N = cast<MaskedLoadSDNode>(Op.getNode());
20003 MVT VT = Op.getSimpleValueType();
20004 SDValue Mask = N->getMask();
20007 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
20008 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
20009 // This operation is legal for targets with VLX, but without
20010 // VLX the vector should be widened to 512 bit
20011 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
20012 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
20013 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
20014 SDValue Src0 = N->getSrc0();
20015 Src0 = ExtendToType(Src0, WideDataVT, DAG);
20016 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
20017 SDValue NewLoad = DAG.getMaskedLoad(WideDataVT, dl, N->getChain(),
20018 N->getBasePtr(), Mask, Src0,
20019 N->getMemoryVT(), N->getMemOperand(),
20020 N->getExtensionType());
20022 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
20023 NewLoad.getValue(0),
20024 DAG.getIntPtrConstant(0, dl));
20025 SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
20026 return DAG.getMergeValues(RetOps, dl);
20031 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget *Subtarget,
20032 SelectionDAG &DAG) {
20033 MaskedStoreSDNode *N = cast<MaskedStoreSDNode>(Op.getNode());
20034 SDValue DataToStore = N->getValue();
20035 MVT VT = DataToStore.getSimpleValueType();
20036 SDValue Mask = N->getMask();
20039 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
20040 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
20041 // This operation is legal for targets with VLX, but without
20042 // VLX the vector should be widened to 512 bit
20043 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
20044 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
20045 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
20046 DataToStore = ExtendToType(DataToStore, WideDataVT, DAG);
20047 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
20048 return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
20049 Mask, N->getMemoryVT(), N->getMemOperand(),
20050 N->isTruncatingStore());
20055 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
20056 SelectionDAG &DAG) {
20057 assert(Subtarget->hasAVX512() &&
20058 "MGATHER/MSCATTER are supported on AVX-512 arch only");
20060 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
20062 MVT VT = Op.getSimpleValueType();
20063 SDValue Index = N->getIndex();
20064 SDValue Mask = N->getMask();
20065 SDValue Src0 = N->getValue();
20066 MVT IndexVT = Index.getSimpleValueType();
20067 MVT MaskVT = Mask.getSimpleValueType();
20069 unsigned NumElts = VT.getVectorNumElements();
20070 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
20072 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
20073 !Index.getSimpleValueType().is512BitVector()) {
20074 // AVX512F supports only 512-bit vectors. Or data or index should
20075 // be 512 bit wide. If now the both index and data are 256-bit, but
20076 // the vector contains 8 elements, we just sign-extend the index
20077 if (NumElts == 8) {
20078 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20079 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
20080 N->getOperand(3), Index };
20081 DAG.UpdateNodeOperands(N, Ops);
20085 // Minimal number of elements in Gather
20088 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), NumElts);
20089 Index = ExtendToType(Index, NewIndexVT, DAG);
20090 if (IndexVT.getScalarType() == MVT::i32)
20091 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20094 MVT MaskBitVT = MVT::getVectorVT(MVT::i1, NumElts);
20095 // At this point we have promoted mask operand
20096 assert(MaskVT.getScalarSizeInBits() >= 32 && "unexpected mask type");
20097 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), NumElts);
20098 Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
20099 Mask = DAG.getNode(ISD::TRUNCATE, dl, MaskBitVT, Mask);
20101 // The pass-thru value
20102 MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
20103 Src0 = ExtendToType(Src0, NewVT, DAG);
20105 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
20106 SDValue NewGather = DAG.getMaskedGather(DAG.getVTList(NewVT, MVT::Other),
20107 N->getMemoryVT(), dl, Ops,
20108 N->getMemOperand());
20109 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
20110 NewGather.getValue(0),
20111 DAG.getIntPtrConstant(0, dl));
20112 SDValue RetOps[] = {Exract, NewGather.getValue(1)};
20113 return DAG.getMergeValues(RetOps, dl);
20118 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
20119 SelectionDAG &DAG) const {
20120 // TODO: Eventually, the lowering of these nodes should be informed by or
20121 // deferred to the GC strategy for the function in which they appear. For
20122 // now, however, they must be lowered to something. Since they are logically
20123 // no-ops in the case of a null GC strategy (or a GC strategy which does not
20124 // require special handling for these nodes), lower them as literal NOOPs for
20126 SmallVector<SDValue, 2> Ops;
20128 Ops.push_back(Op.getOperand(0));
20129 if (Op->getGluedNode())
20130 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
20133 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
20134 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
20139 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
20140 SelectionDAG &DAG) const {
20141 // TODO: Eventually, the lowering of these nodes should be informed by or
20142 // deferred to the GC strategy for the function in which they appear. For
20143 // now, however, they must be lowered to something. Since they are logically
20144 // no-ops in the case of a null GC strategy (or a GC strategy which does not
20145 // require special handling for these nodes), lower them as literal NOOPs for
20147 SmallVector<SDValue, 2> Ops;
20149 Ops.push_back(Op.getOperand(0));
20150 if (Op->getGluedNode())
20151 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
20154 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
20155 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
20160 /// LowerOperation - Provide custom lowering hooks for some operations.
20162 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
20163 switch (Op.getOpcode()) {
20164 default: llvm_unreachable("Should not custom lower this!");
20165 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
20166 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
20167 return LowerCMP_SWAP(Op, Subtarget, DAG);
20168 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
20169 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
20170 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
20171 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
20172 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
20173 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
20174 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
20175 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
20176 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
20177 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
20178 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
20179 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
20180 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
20181 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
20182 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
20183 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
20184 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
20185 case ISD::SHL_PARTS:
20186 case ISD::SRA_PARTS:
20187 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
20188 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
20189 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
20190 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
20191 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
20192 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
20193 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
20194 case ISD::SIGN_EXTEND_VECTOR_INREG:
20195 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
20196 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
20197 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
20198 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
20199 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
20201 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
20202 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
20203 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
20204 case ISD::SETCC: return LowerSETCC(Op, DAG);
20205 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
20206 case ISD::SELECT: return LowerSELECT(Op, DAG);
20207 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
20208 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
20209 case ISD::VASTART: return LowerVASTART(Op, DAG);
20210 case ISD::VAARG: return LowerVAARG(Op, DAG);
20211 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
20212 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
20213 case ISD::INTRINSIC_VOID:
20214 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
20215 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
20216 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
20217 case ISD::FRAME_TO_ARGS_OFFSET:
20218 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
20219 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
20220 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
20221 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
20222 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
20223 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
20224 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
20225 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
20226 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
20227 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
20229 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
20230 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
20231 case ISD::UMUL_LOHI:
20232 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
20233 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
20236 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
20242 case ISD::UMULO: return LowerXALUO(Op, DAG);
20243 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
20244 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
20248 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
20249 case ISD::ADD: return LowerADD(Op, DAG);
20250 case ISD::SUB: return LowerSUB(Op, DAG);
20254 case ISD::UMIN: return LowerMINMAX(Op, DAG);
20255 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
20256 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG);
20257 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG);
20258 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
20259 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
20260 case ISD::GC_TRANSITION_START:
20261 return LowerGC_TRANSITION_START(Op, DAG);
20262 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
20266 /// ReplaceNodeResults - Replace a node with an illegal result type
20267 /// with a new node built out of custom code.
20268 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
20269 SmallVectorImpl<SDValue>&Results,
20270 SelectionDAG &DAG) const {
20272 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20273 switch (N->getOpcode()) {
20275 llvm_unreachable("Do not know how to custom type legalize this operation!");
20276 case X86ISD::AVG: {
20277 // Legalize types for X86ISD::AVG by expanding vectors.
20278 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20280 auto InVT = N->getValueType(0);
20281 auto InVTSize = InVT.getSizeInBits();
20282 const unsigned RegSize =
20283 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
20284 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
20285 "512-bit vector requires AVX512");
20286 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
20287 "256-bit vector requires AVX2");
20289 auto ElemVT = InVT.getVectorElementType();
20290 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
20291 RegSize / ElemVT.getSizeInBits());
20292 assert(RegSize % InVT.getSizeInBits() == 0);
20293 unsigned NumConcat = RegSize / InVT.getSizeInBits();
20295 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
20296 Ops[0] = N->getOperand(0);
20297 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20298 Ops[0] = N->getOperand(1);
20299 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20301 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
20302 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
20303 DAG.getIntPtrConstant(0, dl)));
20306 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
20307 case X86ISD::FMINC:
20309 case X86ISD::FMAXC:
20310 case X86ISD::FMAX: {
20311 EVT VT = N->getValueType(0);
20312 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
20313 SDValue UNDEF = DAG.getUNDEF(VT);
20314 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20315 N->getOperand(0), UNDEF);
20316 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20317 N->getOperand(1), UNDEF);
20318 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
20321 case ISD::SIGN_EXTEND_INREG:
20326 // We don't want to expand or promote these.
20333 case ISD::UDIVREM: {
20334 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
20335 Results.push_back(V);
20338 case ISD::FP_TO_SINT:
20339 case ISD::FP_TO_UINT: {
20340 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
20342 std::pair<SDValue,SDValue> Vals =
20343 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
20344 SDValue FIST = Vals.first, StackSlot = Vals.second;
20345 if (FIST.getNode()) {
20346 EVT VT = N->getValueType(0);
20347 // Return a load from the stack slot.
20348 if (StackSlot.getNode())
20349 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
20350 MachinePointerInfo(),
20351 false, false, false, 0));
20353 Results.push_back(FIST);
20357 case ISD::UINT_TO_FP: {
20358 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20359 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
20360 N->getValueType(0) != MVT::v2f32)
20362 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
20364 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
20366 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
20367 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
20368 DAG.getBitcast(MVT::v2i64, VBias));
20369 Or = DAG.getBitcast(MVT::v2f64, Or);
20370 // TODO: Are there any fast-math-flags to propagate here?
20371 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
20372 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
20375 case ISD::FP_ROUND: {
20376 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
20378 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
20379 Results.push_back(V);
20382 case ISD::FP_EXTEND: {
20383 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
20384 // No other ValueType for FP_EXTEND should reach this point.
20385 assert(N->getValueType(0) == MVT::v2f32 &&
20386 "Do not know how to legalize this Node");
20389 case ISD::INTRINSIC_W_CHAIN: {
20390 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
20392 default : llvm_unreachable("Do not know how to custom type "
20393 "legalize this intrinsic operation!");
20394 case Intrinsic::x86_rdtsc:
20395 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20397 case Intrinsic::x86_rdtscp:
20398 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
20400 case Intrinsic::x86_rdpmc:
20401 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
20404 case ISD::INTRINSIC_WO_CHAIN: {
20405 if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG))
20406 Results.push_back(V);
20409 case ISD::READCYCLECOUNTER: {
20410 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20413 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
20414 EVT T = N->getValueType(0);
20415 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
20416 bool Regs64bit = T == MVT::i128;
20417 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
20418 SDValue cpInL, cpInH;
20419 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20420 DAG.getConstant(0, dl, HalfT));
20421 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20422 DAG.getConstant(1, dl, HalfT));
20423 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20424 Regs64bit ? X86::RAX : X86::EAX,
20426 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20427 Regs64bit ? X86::RDX : X86::EDX,
20428 cpInH, cpInL.getValue(1));
20429 SDValue swapInL, swapInH;
20430 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20431 DAG.getConstant(0, dl, HalfT));
20432 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20433 DAG.getConstant(1, dl, HalfT));
20434 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20435 Regs64bit ? X86::RBX : X86::EBX,
20436 swapInL, cpInH.getValue(1));
20437 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20438 Regs64bit ? X86::RCX : X86::ECX,
20439 swapInH, swapInL.getValue(1));
20440 SDValue Ops[] = { swapInH.getValue(0),
20442 swapInH.getValue(1) };
20443 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20444 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20445 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20446 X86ISD::LCMPXCHG8_DAG;
20447 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20448 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20449 Regs64bit ? X86::RAX : X86::EAX,
20450 HalfT, Result.getValue(1));
20451 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20452 Regs64bit ? X86::RDX : X86::EDX,
20453 HalfT, cpOutL.getValue(2));
20454 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20456 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20457 MVT::i32, cpOutH.getValue(2));
20459 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20460 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20461 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20463 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20464 Results.push_back(Success);
20465 Results.push_back(EFLAGS.getValue(1));
20468 case ISD::ATOMIC_SWAP:
20469 case ISD::ATOMIC_LOAD_ADD:
20470 case ISD::ATOMIC_LOAD_SUB:
20471 case ISD::ATOMIC_LOAD_AND:
20472 case ISD::ATOMIC_LOAD_OR:
20473 case ISD::ATOMIC_LOAD_XOR:
20474 case ISD::ATOMIC_LOAD_NAND:
20475 case ISD::ATOMIC_LOAD_MIN:
20476 case ISD::ATOMIC_LOAD_MAX:
20477 case ISD::ATOMIC_LOAD_UMIN:
20478 case ISD::ATOMIC_LOAD_UMAX:
20479 case ISD::ATOMIC_LOAD: {
20480 // Delegate to generic TypeLegalization. Situations we can really handle
20481 // should have already been dealt with by AtomicExpandPass.cpp.
20484 case ISD::BITCAST: {
20485 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20486 EVT DstVT = N->getValueType(0);
20487 EVT SrcVT = N->getOperand(0)->getValueType(0);
20489 if (SrcVT != MVT::f64 ||
20490 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20493 unsigned NumElts = DstVT.getVectorNumElements();
20494 EVT SVT = DstVT.getVectorElementType();
20495 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20496 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20497 MVT::v2f64, N->getOperand(0));
20498 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20500 if (ExperimentalVectorWideningLegalization) {
20501 // If we are legalizing vectors by widening, we already have the desired
20502 // legal vector type, just return it.
20503 Results.push_back(ToVecInt);
20507 SmallVector<SDValue, 8> Elts;
20508 for (unsigned i = 0, e = NumElts; i != e; ++i)
20509 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20510 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20512 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20517 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20518 switch ((X86ISD::NodeType)Opcode) {
20519 case X86ISD::FIRST_NUMBER: break;
20520 case X86ISD::BSF: return "X86ISD::BSF";
20521 case X86ISD::BSR: return "X86ISD::BSR";
20522 case X86ISD::SHLD: return "X86ISD::SHLD";
20523 case X86ISD::SHRD: return "X86ISD::SHRD";
20524 case X86ISD::FAND: return "X86ISD::FAND";
20525 case X86ISD::FANDN: return "X86ISD::FANDN";
20526 case X86ISD::FOR: return "X86ISD::FOR";
20527 case X86ISD::FXOR: return "X86ISD::FXOR";
20528 case X86ISD::FILD: return "X86ISD::FILD";
20529 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20530 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20531 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20532 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20533 case X86ISD::FLD: return "X86ISD::FLD";
20534 case X86ISD::FST: return "X86ISD::FST";
20535 case X86ISD::CALL: return "X86ISD::CALL";
20536 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20537 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20538 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20539 case X86ISD::BT: return "X86ISD::BT";
20540 case X86ISD::CMP: return "X86ISD::CMP";
20541 case X86ISD::COMI: return "X86ISD::COMI";
20542 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20543 case X86ISD::CMPM: return "X86ISD::CMPM";
20544 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20545 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20546 case X86ISD::SETCC: return "X86ISD::SETCC";
20547 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20548 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20549 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20550 case X86ISD::CMOV: return "X86ISD::CMOV";
20551 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20552 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20553 case X86ISD::IRET: return "X86ISD::IRET";
20554 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20555 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20556 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20557 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20558 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20559 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20560 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20561 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20562 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20563 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20564 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20565 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20566 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20567 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20568 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20569 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20570 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20571 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20572 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20573 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20574 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20575 case X86ISD::HADD: return "X86ISD::HADD";
20576 case X86ISD::HSUB: return "X86ISD::HSUB";
20577 case X86ISD::FHADD: return "X86ISD::FHADD";
20578 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20579 case X86ISD::ABS: return "X86ISD::ABS";
20580 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20581 case X86ISD::FMAX: return "X86ISD::FMAX";
20582 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20583 case X86ISD::FMIN: return "X86ISD::FMIN";
20584 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20585 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20586 case X86ISD::FMINC: return "X86ISD::FMINC";
20587 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20588 case X86ISD::FRCP: return "X86ISD::FRCP";
20589 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20590 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20591 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20592 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20593 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20594 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20595 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20596 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20597 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20598 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20599 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20600 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20601 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20602 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20603 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20604 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20605 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20606 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20607 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20608 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20609 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20610 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20611 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20612 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20613 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20614 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20615 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20616 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20617 case X86ISD::VSHL: return "X86ISD::VSHL";
20618 case X86ISD::VSRL: return "X86ISD::VSRL";
20619 case X86ISD::VSRA: return "X86ISD::VSRA";
20620 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20621 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20622 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20623 case X86ISD::CMPP: return "X86ISD::CMPP";
20624 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20625 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20626 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20627 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20628 case X86ISD::ADD: return "X86ISD::ADD";
20629 case X86ISD::SUB: return "X86ISD::SUB";
20630 case X86ISD::ADC: return "X86ISD::ADC";
20631 case X86ISD::SBB: return "X86ISD::SBB";
20632 case X86ISD::SMUL: return "X86ISD::SMUL";
20633 case X86ISD::UMUL: return "X86ISD::UMUL";
20634 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20635 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20636 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20637 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20638 case X86ISD::INC: return "X86ISD::INC";
20639 case X86ISD::DEC: return "X86ISD::DEC";
20640 case X86ISD::OR: return "X86ISD::OR";
20641 case X86ISD::XOR: return "X86ISD::XOR";
20642 case X86ISD::AND: return "X86ISD::AND";
20643 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20644 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20645 case X86ISD::PTEST: return "X86ISD::PTEST";
20646 case X86ISD::TESTP: return "X86ISD::TESTP";
20647 case X86ISD::TESTM: return "X86ISD::TESTM";
20648 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20649 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20650 case X86ISD::KTEST: return "X86ISD::KTEST";
20651 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20652 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20653 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20654 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20655 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20656 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20657 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20658 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20659 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20660 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20661 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20662 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20663 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20664 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20665 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20666 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20667 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20668 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20669 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20670 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20671 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20672 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20673 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20674 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20675 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20676 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20677 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20678 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20679 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20680 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20681 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20682 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20683 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20684 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20685 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20686 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20687 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20688 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20689 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20690 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20691 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20692 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20693 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20694 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20695 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20696 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20697 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20698 case X86ISD::SAHF: return "X86ISD::SAHF";
20699 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20700 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20701 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20702 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20703 case X86ISD::VPROT: return "X86ISD::VPROT";
20704 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20705 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20706 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20707 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20708 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20709 case X86ISD::FMADD: return "X86ISD::FMADD";
20710 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20711 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20712 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20713 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20714 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20715 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20716 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20717 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20718 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20719 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20720 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20721 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20722 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20723 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20724 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20725 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20726 case X86ISD::XTEST: return "X86ISD::XTEST";
20727 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20728 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20729 case X86ISD::SELECT: return "X86ISD::SELECT";
20730 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20731 case X86ISD::RCP28: return "X86ISD::RCP28";
20732 case X86ISD::EXP2: return "X86ISD::EXP2";
20733 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20734 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20735 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20736 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20737 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20738 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20739 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20740 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20741 case X86ISD::ADDS: return "X86ISD::ADDS";
20742 case X86ISD::SUBS: return "X86ISD::SUBS";
20743 case X86ISD::AVG: return "X86ISD::AVG";
20744 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20745 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20746 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20747 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20748 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20749 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20750 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20755 // isLegalAddressingMode - Return true if the addressing mode represented
20756 // by AM is legal for this target, for a load/store of the specified type.
20757 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20758 const AddrMode &AM, Type *Ty,
20759 unsigned AS) const {
20760 // X86 supports extremely general addressing modes.
20761 CodeModel::Model M = getTargetMachine().getCodeModel();
20762 Reloc::Model R = getTargetMachine().getRelocationModel();
20764 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20765 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20770 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20772 // If a reference to this global requires an extra load, we can't fold it.
20773 if (isGlobalStubReference(GVFlags))
20776 // If BaseGV requires a register for the PIC base, we cannot also have a
20777 // BaseReg specified.
20778 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20781 // If lower 4G is not available, then we must use rip-relative addressing.
20782 if ((M != CodeModel::Small || R != Reloc::Static) &&
20783 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20787 switch (AM.Scale) {
20793 // These scales always work.
20798 // These scales are formed with basereg+scalereg. Only accept if there is
20803 default: // Other stuff never works.
20810 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20811 unsigned Bits = Ty->getScalarSizeInBits();
20813 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20814 // particularly cheaper than those without.
20818 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20819 // variable shifts just as cheap as scalar ones.
20820 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20823 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20824 // fully general vector.
20828 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20829 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20831 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20832 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20833 return NumBits1 > NumBits2;
20836 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20837 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20840 if (!isTypeLegal(EVT::getEVT(Ty1)))
20843 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20845 // Assuming the caller doesn't have a zeroext or signext return parameter,
20846 // truncation all the way down to i1 is valid.
20850 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20851 return isInt<32>(Imm);
20854 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20855 // Can also use sub to handle negated immediates.
20856 return isInt<32>(Imm);
20859 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20860 if (!VT1.isInteger() || !VT2.isInteger())
20862 unsigned NumBits1 = VT1.getSizeInBits();
20863 unsigned NumBits2 = VT2.getSizeInBits();
20864 return NumBits1 > NumBits2;
20867 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20868 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20869 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20872 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20873 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20874 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20877 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20878 EVT VT1 = Val.getValueType();
20879 if (isZExtFree(VT1, VT2))
20882 if (Val.getOpcode() != ISD::LOAD)
20885 if (!VT1.isSimple() || !VT1.isInteger() ||
20886 !VT2.isSimple() || !VT2.isInteger())
20889 switch (VT1.getSimpleVT().SimpleTy) {
20894 // X86 has 8, 16, and 32-bit zero-extending loads.
20901 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20904 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20905 if (!Subtarget->hasAnyFMA())
20908 VT = VT.getScalarType();
20910 if (!VT.isSimple())
20913 switch (VT.getSimpleVT().SimpleTy) {
20924 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20925 // i16 instructions are longer (0x66 prefix) and potentially slower.
20926 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20929 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20930 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20931 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20932 /// are assumed to be legal.
20934 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20936 if (!VT.isSimple())
20939 // Not for i1 vectors
20940 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20943 // Very little shuffling can be done for 64-bit vectors right now.
20944 if (VT.getSimpleVT().getSizeInBits() == 64)
20947 // We only care that the types being shuffled are legal. The lowering can
20948 // handle any possible shuffle mask that results.
20949 return isTypeLegal(VT.getSimpleVT());
20953 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20955 // Just delegate to the generic legality, clear masks aren't special.
20956 return isShuffleMaskLegal(Mask, VT);
20959 //===----------------------------------------------------------------------===//
20960 // X86 Scheduler Hooks
20961 //===----------------------------------------------------------------------===//
20963 /// Utility function to emit xbegin specifying the start of an RTM region.
20964 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20965 const TargetInstrInfo *TII) {
20966 DebugLoc DL = MI->getDebugLoc();
20968 const BasicBlock *BB = MBB->getBasicBlock();
20969 MachineFunction::iterator I = ++MBB->getIterator();
20971 // For the v = xbegin(), we generate
20982 MachineBasicBlock *thisMBB = MBB;
20983 MachineFunction *MF = MBB->getParent();
20984 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20985 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20986 MF->insert(I, mainMBB);
20987 MF->insert(I, sinkMBB);
20989 // Transfer the remainder of BB and its successor edges to sinkMBB.
20990 sinkMBB->splice(sinkMBB->begin(), MBB,
20991 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20992 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20996 // # fallthrough to mainMBB
20997 // # abortion to sinkMBB
20998 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20999 thisMBB->addSuccessor(mainMBB);
21000 thisMBB->addSuccessor(sinkMBB);
21004 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
21005 mainMBB->addSuccessor(sinkMBB);
21008 // EAX is live into the sinkMBB
21009 sinkMBB->addLiveIn(X86::EAX);
21010 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21011 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21014 MI->eraseFromParent();
21018 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
21019 // or XMM0_V32I8 in AVX all of this code can be replaced with that
21020 // in the .td file.
21021 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
21022 const TargetInstrInfo *TII) {
21024 switch (MI->getOpcode()) {
21025 default: llvm_unreachable("illegal opcode!");
21026 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
21027 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
21028 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
21029 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
21030 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
21031 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
21032 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
21033 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
21036 DebugLoc dl = MI->getDebugLoc();
21037 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
21039 unsigned NumArgs = MI->getNumOperands();
21040 for (unsigned i = 1; i < NumArgs; ++i) {
21041 MachineOperand &Op = MI->getOperand(i);
21042 if (!(Op.isReg() && Op.isImplicit()))
21043 MIB.addOperand(Op);
21045 if (MI->hasOneMemOperand())
21046 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
21048 BuildMI(*BB, MI, dl,
21049 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21050 .addReg(X86::XMM0);
21052 MI->eraseFromParent();
21056 // FIXME: Custom handling because TableGen doesn't support multiple implicit
21057 // defs in an instruction pattern
21058 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
21059 const TargetInstrInfo *TII) {
21061 switch (MI->getOpcode()) {
21062 default: llvm_unreachable("illegal opcode!");
21063 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
21064 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
21065 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
21066 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
21067 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
21068 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
21069 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
21070 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
21073 DebugLoc dl = MI->getDebugLoc();
21074 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
21076 unsigned NumArgs = MI->getNumOperands(); // remove the results
21077 for (unsigned i = 1; i < NumArgs; ++i) {
21078 MachineOperand &Op = MI->getOperand(i);
21079 if (!(Op.isReg() && Op.isImplicit()))
21080 MIB.addOperand(Op);
21082 if (MI->hasOneMemOperand())
21083 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
21085 BuildMI(*BB, MI, dl,
21086 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21089 MI->eraseFromParent();
21093 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
21094 const X86Subtarget *Subtarget) {
21095 DebugLoc dl = MI->getDebugLoc();
21096 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21097 // Address into RAX/EAX, other two args into ECX, EDX.
21098 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
21099 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
21100 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
21101 for (int i = 0; i < X86::AddrNumOperands; ++i)
21102 MIB.addOperand(MI->getOperand(i));
21104 unsigned ValOps = X86::AddrNumOperands;
21105 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
21106 .addReg(MI->getOperand(ValOps).getReg());
21107 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
21108 .addReg(MI->getOperand(ValOps+1).getReg());
21110 // The instruction doesn't actually take any operands though.
21111 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
21113 MI->eraseFromParent(); // The pseudo is gone now.
21117 MachineBasicBlock *
21118 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
21119 MachineBasicBlock *MBB) const {
21120 // Emit va_arg instruction on X86-64.
21122 // Operands to this pseudo-instruction:
21123 // 0 ) Output : destination address (reg)
21124 // 1-5) Input : va_list address (addr, i64mem)
21125 // 6 ) ArgSize : Size (in bytes) of vararg type
21126 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
21127 // 8 ) Align : Alignment of type
21128 // 9 ) EFLAGS (implicit-def)
21130 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
21131 static_assert(X86::AddrNumOperands == 5,
21132 "VAARG_64 assumes 5 address operands");
21134 unsigned DestReg = MI->getOperand(0).getReg();
21135 MachineOperand &Base = MI->getOperand(1);
21136 MachineOperand &Scale = MI->getOperand(2);
21137 MachineOperand &Index = MI->getOperand(3);
21138 MachineOperand &Disp = MI->getOperand(4);
21139 MachineOperand &Segment = MI->getOperand(5);
21140 unsigned ArgSize = MI->getOperand(6).getImm();
21141 unsigned ArgMode = MI->getOperand(7).getImm();
21142 unsigned Align = MI->getOperand(8).getImm();
21144 // Memory Reference
21145 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
21146 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21147 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21149 // Machine Information
21150 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21151 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
21152 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
21153 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
21154 DebugLoc DL = MI->getDebugLoc();
21156 // struct va_list {
21159 // i64 overflow_area (address)
21160 // i64 reg_save_area (address)
21162 // sizeof(va_list) = 24
21163 // alignment(va_list) = 8
21165 unsigned TotalNumIntRegs = 6;
21166 unsigned TotalNumXMMRegs = 8;
21167 bool UseGPOffset = (ArgMode == 1);
21168 bool UseFPOffset = (ArgMode == 2);
21169 unsigned MaxOffset = TotalNumIntRegs * 8 +
21170 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
21172 /* Align ArgSize to a multiple of 8 */
21173 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
21174 bool NeedsAlign = (Align > 8);
21176 MachineBasicBlock *thisMBB = MBB;
21177 MachineBasicBlock *overflowMBB;
21178 MachineBasicBlock *offsetMBB;
21179 MachineBasicBlock *endMBB;
21181 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
21182 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
21183 unsigned OffsetReg = 0;
21185 if (!UseGPOffset && !UseFPOffset) {
21186 // If we only pull from the overflow region, we don't create a branch.
21187 // We don't need to alter control flow.
21188 OffsetDestReg = 0; // unused
21189 OverflowDestReg = DestReg;
21191 offsetMBB = nullptr;
21192 overflowMBB = thisMBB;
21195 // First emit code to check if gp_offset (or fp_offset) is below the bound.
21196 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
21197 // If not, pull from overflow_area. (branch to overflowMBB)
21202 // offsetMBB overflowMBB
21207 // Registers for the PHI in endMBB
21208 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
21209 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
21211 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21212 MachineFunction *MF = MBB->getParent();
21213 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21214 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21215 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21217 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21219 // Insert the new basic blocks
21220 MF->insert(MBBIter, offsetMBB);
21221 MF->insert(MBBIter, overflowMBB);
21222 MF->insert(MBBIter, endMBB);
21224 // Transfer the remainder of MBB and its successor edges to endMBB.
21225 endMBB->splice(endMBB->begin(), thisMBB,
21226 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
21227 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
21229 // Make offsetMBB and overflowMBB successors of thisMBB
21230 thisMBB->addSuccessor(offsetMBB);
21231 thisMBB->addSuccessor(overflowMBB);
21233 // endMBB is a successor of both offsetMBB and overflowMBB
21234 offsetMBB->addSuccessor(endMBB);
21235 overflowMBB->addSuccessor(endMBB);
21237 // Load the offset value into a register
21238 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21239 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
21243 .addDisp(Disp, UseFPOffset ? 4 : 0)
21244 .addOperand(Segment)
21245 .setMemRefs(MMOBegin, MMOEnd);
21247 // Check if there is enough room left to pull this argument.
21248 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
21250 .addImm(MaxOffset + 8 - ArgSizeA8);
21252 // Branch to "overflowMBB" if offset >= max
21253 // Fall through to "offsetMBB" otherwise
21254 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
21255 .addMBB(overflowMBB);
21258 // In offsetMBB, emit code to use the reg_save_area.
21260 assert(OffsetReg != 0);
21262 // Read the reg_save_area address.
21263 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
21264 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
21269 .addOperand(Segment)
21270 .setMemRefs(MMOBegin, MMOEnd);
21272 // Zero-extend the offset
21273 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
21274 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
21277 .addImm(X86::sub_32bit);
21279 // Add the offset to the reg_save_area to get the final address.
21280 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
21281 .addReg(OffsetReg64)
21282 .addReg(RegSaveReg);
21284 // Compute the offset for the next argument
21285 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21286 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
21288 .addImm(UseFPOffset ? 16 : 8);
21290 // Store it back into the va_list.
21291 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
21295 .addDisp(Disp, UseFPOffset ? 4 : 0)
21296 .addOperand(Segment)
21297 .addReg(NextOffsetReg)
21298 .setMemRefs(MMOBegin, MMOEnd);
21301 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
21306 // Emit code to use overflow area
21309 // Load the overflow_area address into a register.
21310 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
21311 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
21316 .addOperand(Segment)
21317 .setMemRefs(MMOBegin, MMOEnd);
21319 // If we need to align it, do so. Otherwise, just copy the address
21320 // to OverflowDestReg.
21322 // Align the overflow address
21323 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
21324 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
21326 // aligned_addr = (addr + (align-1)) & ~(align-1)
21327 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
21328 .addReg(OverflowAddrReg)
21331 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
21333 .addImm(~(uint64_t)(Align-1));
21335 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
21336 .addReg(OverflowAddrReg);
21339 // Compute the next overflow address after this argument.
21340 // (the overflow address should be kept 8-byte aligned)
21341 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
21342 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
21343 .addReg(OverflowDestReg)
21344 .addImm(ArgSizeA8);
21346 // Store the new overflow address.
21347 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
21352 .addOperand(Segment)
21353 .addReg(NextAddrReg)
21354 .setMemRefs(MMOBegin, MMOEnd);
21356 // If we branched, emit the PHI to the front of endMBB.
21358 BuildMI(*endMBB, endMBB->begin(), DL,
21359 TII->get(X86::PHI), DestReg)
21360 .addReg(OffsetDestReg).addMBB(offsetMBB)
21361 .addReg(OverflowDestReg).addMBB(overflowMBB);
21364 // Erase the pseudo instruction
21365 MI->eraseFromParent();
21370 MachineBasicBlock *
21371 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
21373 MachineBasicBlock *MBB) const {
21374 // Emit code to save XMM registers to the stack. The ABI says that the
21375 // number of registers to save is given in %al, so it's theoretically
21376 // possible to do an indirect jump trick to avoid saving all of them,
21377 // however this code takes a simpler approach and just executes all
21378 // of the stores if %al is non-zero. It's less code, and it's probably
21379 // easier on the hardware branch predictor, and stores aren't all that
21380 // expensive anyway.
21382 // Create the new basic blocks. One block contains all the XMM stores,
21383 // and one block is the final destination regardless of whether any
21384 // stores were performed.
21385 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21386 MachineFunction *F = MBB->getParent();
21387 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21388 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
21389 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
21390 F->insert(MBBIter, XMMSaveMBB);
21391 F->insert(MBBIter, EndMBB);
21393 // Transfer the remainder of MBB and its successor edges to EndMBB.
21394 EndMBB->splice(EndMBB->begin(), MBB,
21395 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21396 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
21398 // The original block will now fall through to the XMM save block.
21399 MBB->addSuccessor(XMMSaveMBB);
21400 // The XMMSaveMBB will fall through to the end block.
21401 XMMSaveMBB->addSuccessor(EndMBB);
21403 // Now add the instructions.
21404 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21405 DebugLoc DL = MI->getDebugLoc();
21407 unsigned CountReg = MI->getOperand(0).getReg();
21408 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
21409 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
21411 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
21412 // If %al is 0, branch around the XMM save block.
21413 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
21414 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
21415 MBB->addSuccessor(EndMBB);
21418 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
21419 // that was just emitted, but clearly shouldn't be "saved".
21420 assert((MI->getNumOperands() <= 3 ||
21421 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
21422 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21423 && "Expected last argument to be EFLAGS");
21424 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21425 // In the XMM save block, save all the XMM argument registers.
21426 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21427 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21428 MachineMemOperand *MMO = F->getMachineMemOperand(
21429 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21430 MachineMemOperand::MOStore,
21431 /*Size=*/16, /*Align=*/16);
21432 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21433 .addFrameIndex(RegSaveFrameIndex)
21434 .addImm(/*Scale=*/1)
21435 .addReg(/*IndexReg=*/0)
21436 .addImm(/*Disp=*/Offset)
21437 .addReg(/*Segment=*/0)
21438 .addReg(MI->getOperand(i).getReg())
21439 .addMemOperand(MMO);
21442 MI->eraseFromParent(); // The pseudo instruction is gone now.
21447 // The EFLAGS operand of SelectItr might be missing a kill marker
21448 // because there were multiple uses of EFLAGS, and ISel didn't know
21449 // which to mark. Figure out whether SelectItr should have had a
21450 // kill marker, and set it if it should. Returns the correct kill
21452 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21453 MachineBasicBlock* BB,
21454 const TargetRegisterInfo* TRI) {
21455 // Scan forward through BB for a use/def of EFLAGS.
21456 MachineBasicBlock::iterator miI(std::next(SelectItr));
21457 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21458 const MachineInstr& mi = *miI;
21459 if (mi.readsRegister(X86::EFLAGS))
21461 if (mi.definesRegister(X86::EFLAGS))
21462 break; // Should have kill-flag - update below.
21465 // If we hit the end of the block, check whether EFLAGS is live into a
21467 if (miI == BB->end()) {
21468 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21469 sEnd = BB->succ_end();
21470 sItr != sEnd; ++sItr) {
21471 MachineBasicBlock* succ = *sItr;
21472 if (succ->isLiveIn(X86::EFLAGS))
21477 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21478 // out. SelectMI should have a kill flag on EFLAGS.
21479 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21483 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21484 // together with other CMOV pseudo-opcodes into a single basic-block with
21485 // conditional jump around it.
21486 static bool isCMOVPseudo(MachineInstr *MI) {
21487 switch (MI->getOpcode()) {
21488 case X86::CMOV_FR32:
21489 case X86::CMOV_FR64:
21490 case X86::CMOV_GR8:
21491 case X86::CMOV_GR16:
21492 case X86::CMOV_GR32:
21493 case X86::CMOV_RFP32:
21494 case X86::CMOV_RFP64:
21495 case X86::CMOV_RFP80:
21496 case X86::CMOV_V2F64:
21497 case X86::CMOV_V2I64:
21498 case X86::CMOV_V4F32:
21499 case X86::CMOV_V4F64:
21500 case X86::CMOV_V4I64:
21501 case X86::CMOV_V16F32:
21502 case X86::CMOV_V8F32:
21503 case X86::CMOV_V8F64:
21504 case X86::CMOV_V8I64:
21505 case X86::CMOV_V8I1:
21506 case X86::CMOV_V16I1:
21507 case X86::CMOV_V32I1:
21508 case X86::CMOV_V64I1:
21516 MachineBasicBlock *
21517 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21518 MachineBasicBlock *BB) const {
21519 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21520 DebugLoc DL = MI->getDebugLoc();
21522 // To "insert" a SELECT_CC instruction, we actually have to insert the
21523 // diamond control-flow pattern. The incoming instruction knows the
21524 // destination vreg to set, the condition code register to branch on, the
21525 // true/false values to select between, and a branch opcode to use.
21526 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21527 MachineFunction::iterator It = ++BB->getIterator();
21532 // cmpTY ccX, r1, r2
21534 // fallthrough --> copy0MBB
21535 MachineBasicBlock *thisMBB = BB;
21536 MachineFunction *F = BB->getParent();
21538 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21539 // as described above, by inserting a BB, and then making a PHI at the join
21540 // point to select the true and false operands of the CMOV in the PHI.
21542 // The code also handles two different cases of multiple CMOV opcodes
21546 // In this case, there are multiple CMOVs in a row, all which are based on
21547 // the same condition setting (or the exact opposite condition setting).
21548 // In this case we can lower all the CMOVs using a single inserted BB, and
21549 // then make a number of PHIs at the join point to model the CMOVs. The only
21550 // trickiness here, is that in a case like:
21552 // t2 = CMOV cond1 t1, f1
21553 // t3 = CMOV cond1 t2, f2
21555 // when rewriting this into PHIs, we have to perform some renaming on the
21556 // temps since you cannot have a PHI operand refer to a PHI result earlier
21557 // in the same block. The "simple" but wrong lowering would be:
21559 // t2 = PHI t1(BB1), f1(BB2)
21560 // t3 = PHI t2(BB1), f2(BB2)
21562 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21563 // renaming is to note that on the path through BB1, t2 is really just a
21564 // copy of t1, and do that renaming, properly generating:
21566 // t2 = PHI t1(BB1), f1(BB2)
21567 // t3 = PHI t1(BB1), f2(BB2)
21569 // Case 2, we lower cascaded CMOVs such as
21571 // (CMOV (CMOV F, T, cc1), T, cc2)
21573 // to two successives branches. For that, we look for another CMOV as the
21574 // following instruction.
21576 // Without this, we would add a PHI between the two jumps, which ends up
21577 // creating a few copies all around. For instance, for
21579 // (sitofp (zext (fcmp une)))
21581 // we would generate:
21583 // ucomiss %xmm1, %xmm0
21584 // movss <1.0f>, %xmm0
21585 // movaps %xmm0, %xmm1
21587 // xorps %xmm1, %xmm1
21590 // movaps %xmm1, %xmm0
21594 // because this custom-inserter would have generated:
21606 // A: X = ...; Y = ...
21608 // C: Z = PHI [X, A], [Y, B]
21610 // E: PHI [X, C], [Z, D]
21612 // If we lower both CMOVs in a single step, we can instead generate:
21624 // A: X = ...; Y = ...
21626 // E: PHI [X, A], [X, C], [Y, D]
21628 // Which, in our sitofp/fcmp example, gives us something like:
21630 // ucomiss %xmm1, %xmm0
21631 // movss <1.0f>, %xmm0
21634 // xorps %xmm0, %xmm0
21638 MachineInstr *CascadedCMOV = nullptr;
21639 MachineInstr *LastCMOV = MI;
21640 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21641 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21642 MachineBasicBlock::iterator NextMIIt =
21643 std::next(MachineBasicBlock::iterator(MI));
21645 // Check for case 1, where there are multiple CMOVs with the same condition
21646 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21647 // number of jumps the most.
21649 if (isCMOVPseudo(MI)) {
21650 // See if we have a string of CMOVS with the same condition.
21651 while (NextMIIt != BB->end() &&
21652 isCMOVPseudo(NextMIIt) &&
21653 (NextMIIt->getOperand(3).getImm() == CC ||
21654 NextMIIt->getOperand(3).getImm() == OppCC)) {
21655 LastCMOV = &*NextMIIt;
21660 // This checks for case 2, but only do this if we didn't already find
21661 // case 1, as indicated by LastCMOV == MI.
21662 if (LastCMOV == MI &&
21663 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21664 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21665 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21666 CascadedCMOV = &*NextMIIt;
21669 MachineBasicBlock *jcc1MBB = nullptr;
21671 // If we have a cascaded CMOV, we lower it to two successive branches to
21672 // the same block. EFLAGS is used by both, so mark it as live in the second.
21673 if (CascadedCMOV) {
21674 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21675 F->insert(It, jcc1MBB);
21676 jcc1MBB->addLiveIn(X86::EFLAGS);
21679 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21680 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21681 F->insert(It, copy0MBB);
21682 F->insert(It, sinkMBB);
21684 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21685 // live into the sink and copy blocks.
21686 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21688 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21689 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21690 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21691 copy0MBB->addLiveIn(X86::EFLAGS);
21692 sinkMBB->addLiveIn(X86::EFLAGS);
21695 // Transfer the remainder of BB and its successor edges to sinkMBB.
21696 sinkMBB->splice(sinkMBB->begin(), BB,
21697 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21698 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21700 // Add the true and fallthrough blocks as its successors.
21701 if (CascadedCMOV) {
21702 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21703 BB->addSuccessor(jcc1MBB);
21705 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21706 // jump to the sinkMBB.
21707 jcc1MBB->addSuccessor(copy0MBB);
21708 jcc1MBB->addSuccessor(sinkMBB);
21710 BB->addSuccessor(copy0MBB);
21713 // The true block target of the first (or only) branch is always sinkMBB.
21714 BB->addSuccessor(sinkMBB);
21716 // Create the conditional branch instruction.
21717 unsigned Opc = X86::GetCondBranchFromCond(CC);
21718 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21720 if (CascadedCMOV) {
21721 unsigned Opc2 = X86::GetCondBranchFromCond(
21722 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21723 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21727 // %FalseValue = ...
21728 // # fallthrough to sinkMBB
21729 copy0MBB->addSuccessor(sinkMBB);
21732 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21734 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21735 MachineBasicBlock::iterator MIItEnd =
21736 std::next(MachineBasicBlock::iterator(LastCMOV));
21737 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21738 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21739 MachineInstrBuilder MIB;
21741 // As we are creating the PHIs, we have to be careful if there is more than
21742 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21743 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21744 // That also means that PHI construction must work forward from earlier to
21745 // later, and that the code must maintain a mapping from earlier PHI's
21746 // destination registers, and the registers that went into the PHI.
21748 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21749 unsigned DestReg = MIIt->getOperand(0).getReg();
21750 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21751 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21753 // If this CMOV we are generating is the opposite condition from
21754 // the jump we generated, then we have to swap the operands for the
21755 // PHI that is going to be generated.
21756 if (MIIt->getOperand(3).getImm() == OppCC)
21757 std::swap(Op1Reg, Op2Reg);
21759 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21760 Op1Reg = RegRewriteTable[Op1Reg].first;
21762 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21763 Op2Reg = RegRewriteTable[Op2Reg].second;
21765 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21766 TII->get(X86::PHI), DestReg)
21767 .addReg(Op1Reg).addMBB(copy0MBB)
21768 .addReg(Op2Reg).addMBB(thisMBB);
21770 // Add this PHI to the rewrite table.
21771 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21774 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21775 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21776 if (CascadedCMOV) {
21777 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21778 // Copy the PHI result to the register defined by the second CMOV.
21779 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21780 DL, TII->get(TargetOpcode::COPY),
21781 CascadedCMOV->getOperand(0).getReg())
21782 .addReg(MI->getOperand(0).getReg());
21783 CascadedCMOV->eraseFromParent();
21786 // Now remove the CMOV(s).
21787 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21788 (MIIt++)->eraseFromParent();
21793 MachineBasicBlock *
21794 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21795 MachineBasicBlock *BB) const {
21796 // Combine the following atomic floating-point modification pattern:
21797 // a.store(reg OP a.load(acquire), release)
21798 // Transform them into:
21799 // OPss (%gpr), %xmm
21800 // movss %xmm, (%gpr)
21801 // Or sd equivalent for 64-bit operations.
21803 switch (MI->getOpcode()) {
21804 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21805 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21806 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21808 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21809 DebugLoc DL = MI->getDebugLoc();
21810 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21811 MachineOperand MSrc = MI->getOperand(0);
21812 unsigned VSrc = MI->getOperand(5).getReg();
21813 const MachineOperand &Disp = MI->getOperand(3);
21814 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21815 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21816 if (hasDisp && MSrc.isReg())
21817 MSrc.setIsKill(false);
21818 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21819 .addOperand(/*Base=*/MSrc)
21820 .addImm(/*Scale=*/1)
21821 .addReg(/*Index=*/0)
21822 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21824 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21825 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21827 .addOperand(/*Base=*/MSrc)
21828 .addImm(/*Scale=*/1)
21829 .addReg(/*Index=*/0)
21830 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21831 .addReg(/*Segment=*/0);
21832 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21833 MI->eraseFromParent(); // The pseudo instruction is gone now.
21837 MachineBasicBlock *
21838 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21839 MachineBasicBlock *BB) const {
21840 MachineFunction *MF = BB->getParent();
21841 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21842 DebugLoc DL = MI->getDebugLoc();
21843 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21845 assert(MF->shouldSplitStack());
21847 const bool Is64Bit = Subtarget->is64Bit();
21848 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21850 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21851 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21854 // ... [Till the alloca]
21855 // If stacklet is not large enough, jump to mallocMBB
21858 // Allocate by subtracting from RSP
21859 // Jump to continueMBB
21862 // Allocate by call to runtime
21866 // [rest of original BB]
21869 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21870 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21871 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21873 MachineRegisterInfo &MRI = MF->getRegInfo();
21874 const TargetRegisterClass *AddrRegClass =
21875 getRegClassFor(getPointerTy(MF->getDataLayout()));
21877 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21878 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21879 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21880 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21881 sizeVReg = MI->getOperand(1).getReg(),
21882 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21884 MachineFunction::iterator MBBIter = ++BB->getIterator();
21886 MF->insert(MBBIter, bumpMBB);
21887 MF->insert(MBBIter, mallocMBB);
21888 MF->insert(MBBIter, continueMBB);
21890 continueMBB->splice(continueMBB->begin(), BB,
21891 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21892 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21894 // Add code to the main basic block to check if the stack limit has been hit,
21895 // and if so, jump to mallocMBB otherwise to bumpMBB.
21896 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21897 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21898 .addReg(tmpSPVReg).addReg(sizeVReg);
21899 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21900 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21901 .addReg(SPLimitVReg);
21902 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21904 // bumpMBB simply decreases the stack pointer, since we know the current
21905 // stacklet has enough space.
21906 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21907 .addReg(SPLimitVReg);
21908 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21909 .addReg(SPLimitVReg);
21910 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21912 // Calls into a routine in libgcc to allocate more space from the heap.
21913 const uint32_t *RegMask =
21914 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21916 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21918 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21919 .addExternalSymbol("__morestack_allocate_stack_space")
21920 .addRegMask(RegMask)
21921 .addReg(X86::RDI, RegState::Implicit)
21922 .addReg(X86::RAX, RegState::ImplicitDefine);
21923 } else if (Is64Bit) {
21924 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21926 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21927 .addExternalSymbol("__morestack_allocate_stack_space")
21928 .addRegMask(RegMask)
21929 .addReg(X86::EDI, RegState::Implicit)
21930 .addReg(X86::EAX, RegState::ImplicitDefine);
21932 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21934 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21935 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21936 .addExternalSymbol("__morestack_allocate_stack_space")
21937 .addRegMask(RegMask)
21938 .addReg(X86::EAX, RegState::ImplicitDefine);
21942 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21945 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21946 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21947 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21949 // Set up the CFG correctly.
21950 BB->addSuccessor(bumpMBB);
21951 BB->addSuccessor(mallocMBB);
21952 mallocMBB->addSuccessor(continueMBB);
21953 bumpMBB->addSuccessor(continueMBB);
21955 // Take care of the PHI nodes.
21956 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21957 MI->getOperand(0).getReg())
21958 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21959 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21961 // Delete the original pseudo instruction.
21962 MI->eraseFromParent();
21965 return continueMBB;
21968 MachineBasicBlock *
21969 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21970 MachineBasicBlock *BB) const {
21971 assert(!Subtarget->isTargetMachO());
21972 DebugLoc DL = MI->getDebugLoc();
21973 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21974 *BB->getParent(), *BB, MI, DL, false);
21975 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21976 MI->eraseFromParent(); // The pseudo instruction is gone now.
21980 MachineBasicBlock *
21981 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21982 MachineBasicBlock *BB) const {
21983 MachineFunction *MF = BB->getParent();
21984 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21985 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21986 DebugLoc DL = MI->getDebugLoc();
21988 assert(!isAsynchronousEHPersonality(
21989 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21990 "SEH does not use catchret!");
21992 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21993 if (!Subtarget->is32Bit())
21996 // C++ EH creates a new target block to hold the restore code, and wires up
21997 // the new block to the return destination with a normal JMP_4.
21998 MachineBasicBlock *RestoreMBB =
21999 MF->CreateMachineBasicBlock(BB->getBasicBlock());
22000 assert(BB->succ_size() == 1);
22001 MF->insert(std::next(BB->getIterator()), RestoreMBB);
22002 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
22003 BB->addSuccessor(RestoreMBB);
22004 MI->getOperand(0).setMBB(RestoreMBB);
22006 auto RestoreMBBI = RestoreMBB->begin();
22007 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
22008 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
22012 MachineBasicBlock *
22013 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
22014 MachineBasicBlock *BB) const {
22015 MachineFunction *MF = BB->getParent();
22016 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
22017 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
22018 // Only 32-bit SEH requires special handling for catchpad.
22019 if (IsSEH && Subtarget->is32Bit()) {
22020 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22021 DebugLoc DL = MI->getDebugLoc();
22022 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
22024 MI->eraseFromParent();
22028 MachineBasicBlock *
22029 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
22030 MachineBasicBlock *BB) const {
22031 // This is pretty easy. We're taking the value that we received from
22032 // our load from the relocation, sticking it in either RDI (x86-64)
22033 // or EAX and doing an indirect call. The return value will then
22034 // be in the normal return register.
22035 MachineFunction *F = BB->getParent();
22036 const X86InstrInfo *TII = Subtarget->getInstrInfo();
22037 DebugLoc DL = MI->getDebugLoc();
22039 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
22040 assert(MI->getOperand(3).isGlobal() && "This should be a global");
22042 // Get a register mask for the lowered call.
22043 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
22044 // proper register mask.
22045 const uint32_t *RegMask =
22046 Subtarget->is64Bit() ?
22047 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
22048 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
22049 if (Subtarget->is64Bit()) {
22050 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22051 TII->get(X86::MOV64rm), X86::RDI)
22053 .addImm(0).addReg(0)
22054 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22055 MI->getOperand(3).getTargetFlags())
22057 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
22058 addDirectMem(MIB, X86::RDI);
22059 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
22060 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
22061 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22062 TII->get(X86::MOV32rm), X86::EAX)
22064 .addImm(0).addReg(0)
22065 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22066 MI->getOperand(3).getTargetFlags())
22068 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
22069 addDirectMem(MIB, X86::EAX);
22070 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
22072 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22073 TII->get(X86::MOV32rm), X86::EAX)
22074 .addReg(TII->getGlobalBaseReg(F))
22075 .addImm(0).addReg(0)
22076 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22077 MI->getOperand(3).getTargetFlags())
22079 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
22080 addDirectMem(MIB, X86::EAX);
22081 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
22084 MI->eraseFromParent(); // The pseudo instruction is gone now.
22088 MachineBasicBlock *
22089 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
22090 MachineBasicBlock *MBB) const {
22091 DebugLoc DL = MI->getDebugLoc();
22092 MachineFunction *MF = MBB->getParent();
22093 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22094 MachineRegisterInfo &MRI = MF->getRegInfo();
22096 const BasicBlock *BB = MBB->getBasicBlock();
22097 MachineFunction::iterator I = ++MBB->getIterator();
22099 // Memory Reference
22100 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
22101 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
22104 unsigned MemOpndSlot = 0;
22106 unsigned CurOp = 0;
22108 DstReg = MI->getOperand(CurOp++).getReg();
22109 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
22110 assert(RC->hasType(MVT::i32) && "Invalid destination!");
22111 unsigned mainDstReg = MRI.createVirtualRegister(RC);
22112 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
22114 MemOpndSlot = CurOp;
22116 MVT PVT = getPointerTy(MF->getDataLayout());
22117 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
22118 "Invalid Pointer Size!");
22120 // For v = setjmp(buf), we generate
22123 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
22124 // SjLjSetup restoreMBB
22130 // v = phi(main, restore)
22133 // if base pointer being used, load it from frame
22136 MachineBasicBlock *thisMBB = MBB;
22137 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
22138 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
22139 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
22140 MF->insert(I, mainMBB);
22141 MF->insert(I, sinkMBB);
22142 MF->push_back(restoreMBB);
22143 restoreMBB->setHasAddressTaken();
22145 MachineInstrBuilder MIB;
22147 // Transfer the remainder of BB and its successor edges to sinkMBB.
22148 sinkMBB->splice(sinkMBB->begin(), MBB,
22149 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
22150 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
22153 unsigned PtrStoreOpc = 0;
22154 unsigned LabelReg = 0;
22155 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22156 Reloc::Model RM = MF->getTarget().getRelocationModel();
22157 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
22158 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
22160 // Prepare IP either in reg or imm.
22161 if (!UseImmLabel) {
22162 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
22163 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
22164 LabelReg = MRI.createVirtualRegister(PtrRC);
22165 if (Subtarget->is64Bit()) {
22166 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
22170 .addMBB(restoreMBB)
22173 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
22174 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
22175 .addReg(XII->getGlobalBaseReg(MF))
22178 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
22182 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
22184 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
22185 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22186 if (i == X86::AddrDisp)
22187 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
22189 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
22192 MIB.addReg(LabelReg);
22194 MIB.addMBB(restoreMBB);
22195 MIB.setMemRefs(MMOBegin, MMOEnd);
22197 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
22198 .addMBB(restoreMBB);
22200 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
22201 MIB.addRegMask(RegInfo->getNoPreservedMask());
22202 thisMBB->addSuccessor(mainMBB);
22203 thisMBB->addSuccessor(restoreMBB);
22207 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
22208 mainMBB->addSuccessor(sinkMBB);
22211 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
22212 TII->get(X86::PHI), DstReg)
22213 .addReg(mainDstReg).addMBB(mainMBB)
22214 .addReg(restoreDstReg).addMBB(restoreMBB);
22217 if (RegInfo->hasBasePointer(*MF)) {
22218 const bool Uses64BitFramePtr =
22219 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
22220 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
22221 X86FI->setRestoreBasePointer(MF);
22222 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
22223 unsigned BasePtr = RegInfo->getBaseRegister();
22224 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
22225 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
22226 FramePtr, true, X86FI->getRestoreBasePointerOffset())
22227 .setMIFlag(MachineInstr::FrameSetup);
22229 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
22230 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
22231 restoreMBB->addSuccessor(sinkMBB);
22233 MI->eraseFromParent();
22237 MachineBasicBlock *
22238 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
22239 MachineBasicBlock *MBB) const {
22240 DebugLoc DL = MI->getDebugLoc();
22241 MachineFunction *MF = MBB->getParent();
22242 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22243 MachineRegisterInfo &MRI = MF->getRegInfo();
22245 // Memory Reference
22246 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
22247 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
22249 MVT PVT = getPointerTy(MF->getDataLayout());
22250 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
22251 "Invalid Pointer Size!");
22253 const TargetRegisterClass *RC =
22254 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
22255 unsigned Tmp = MRI.createVirtualRegister(RC);
22256 // Since FP is only updated here but NOT referenced, it's treated as GPR.
22257 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
22258 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
22259 unsigned SP = RegInfo->getStackRegister();
22261 MachineInstrBuilder MIB;
22263 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22264 const int64_t SPOffset = 2 * PVT.getStoreSize();
22266 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
22267 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
22270 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
22271 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
22272 MIB.addOperand(MI->getOperand(i));
22273 MIB.setMemRefs(MMOBegin, MMOEnd);
22275 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
22276 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22277 if (i == X86::AddrDisp)
22278 MIB.addDisp(MI->getOperand(i), LabelOffset);
22280 MIB.addOperand(MI->getOperand(i));
22282 MIB.setMemRefs(MMOBegin, MMOEnd);
22284 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
22285 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22286 if (i == X86::AddrDisp)
22287 MIB.addDisp(MI->getOperand(i), SPOffset);
22289 MIB.addOperand(MI->getOperand(i));
22291 MIB.setMemRefs(MMOBegin, MMOEnd);
22293 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
22295 MI->eraseFromParent();
22299 // Replace 213-type (isel default) FMA3 instructions with 231-type for
22300 // accumulator loops. Writing back to the accumulator allows the coalescer
22301 // to remove extra copies in the loop.
22302 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
22303 MachineBasicBlock *
22304 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
22305 MachineBasicBlock *MBB) const {
22306 MachineOperand &AddendOp = MI->getOperand(3);
22308 // Bail out early if the addend isn't a register - we can't switch these.
22309 if (!AddendOp.isReg())
22312 MachineFunction &MF = *MBB->getParent();
22313 MachineRegisterInfo &MRI = MF.getRegInfo();
22315 // Check whether the addend is defined by a PHI:
22316 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
22317 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
22318 if (!AddendDef.isPHI())
22321 // Look for the following pattern:
22323 // %addend = phi [%entry, 0], [%loop, %result]
22325 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
22329 // %addend = phi [%entry, 0], [%loop, %result]
22331 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
22333 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
22334 assert(AddendDef.getOperand(i).isReg());
22335 MachineOperand PHISrcOp = AddendDef.getOperand(i);
22336 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
22337 if (&PHISrcInst == MI) {
22338 // Found a matching instruction.
22339 unsigned NewFMAOpc = 0;
22340 switch (MI->getOpcode()) {
22341 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
22342 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
22343 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
22344 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
22345 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
22346 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
22347 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
22348 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
22349 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
22350 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
22351 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
22352 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
22353 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
22354 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
22355 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
22356 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
22357 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
22358 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
22359 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
22360 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
22362 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
22363 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
22364 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
22365 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
22366 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
22367 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
22368 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
22369 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
22370 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
22371 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
22372 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
22373 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
22374 default: llvm_unreachable("Unrecognized FMA variant.");
22377 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22378 MachineInstrBuilder MIB =
22379 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
22380 .addOperand(MI->getOperand(0))
22381 .addOperand(MI->getOperand(3))
22382 .addOperand(MI->getOperand(2))
22383 .addOperand(MI->getOperand(1));
22384 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
22385 MI->eraseFromParent();
22392 MachineBasicBlock *
22393 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
22394 MachineBasicBlock *BB) const {
22395 switch (MI->getOpcode()) {
22396 default: llvm_unreachable("Unexpected instr type to insert");
22397 case X86::TAILJMPd64:
22398 case X86::TAILJMPr64:
22399 case X86::TAILJMPm64:
22400 case X86::TAILJMPd64_REX:
22401 case X86::TAILJMPr64_REX:
22402 case X86::TAILJMPm64_REX:
22403 llvm_unreachable("TAILJMP64 would not be touched here.");
22404 case X86::TCRETURNdi64:
22405 case X86::TCRETURNri64:
22406 case X86::TCRETURNmi64:
22408 case X86::WIN_ALLOCA:
22409 return EmitLoweredWinAlloca(MI, BB);
22410 case X86::CATCHRET:
22411 return EmitLoweredCatchRet(MI, BB);
22412 case X86::CATCHPAD:
22413 return EmitLoweredCatchPad(MI, BB);
22414 case X86::SEG_ALLOCA_32:
22415 case X86::SEG_ALLOCA_64:
22416 return EmitLoweredSegAlloca(MI, BB);
22417 case X86::TLSCall_32:
22418 case X86::TLSCall_64:
22419 return EmitLoweredTLSCall(MI, BB);
22420 case X86::CMOV_FR32:
22421 case X86::CMOV_FR64:
22422 case X86::CMOV_FR128:
22423 case X86::CMOV_GR8:
22424 case X86::CMOV_GR16:
22425 case X86::CMOV_GR32:
22426 case X86::CMOV_RFP32:
22427 case X86::CMOV_RFP64:
22428 case X86::CMOV_RFP80:
22429 case X86::CMOV_V2F64:
22430 case X86::CMOV_V2I64:
22431 case X86::CMOV_V4F32:
22432 case X86::CMOV_V4F64:
22433 case X86::CMOV_V4I64:
22434 case X86::CMOV_V16F32:
22435 case X86::CMOV_V8F32:
22436 case X86::CMOV_V8F64:
22437 case X86::CMOV_V8I64:
22438 case X86::CMOV_V8I1:
22439 case X86::CMOV_V16I1:
22440 case X86::CMOV_V32I1:
22441 case X86::CMOV_V64I1:
22442 return EmitLoweredSelect(MI, BB);
22444 case X86::RELEASE_FADD32mr:
22445 case X86::RELEASE_FADD64mr:
22446 return EmitLoweredAtomicFP(MI, BB);
22448 case X86::FP32_TO_INT16_IN_MEM:
22449 case X86::FP32_TO_INT32_IN_MEM:
22450 case X86::FP32_TO_INT64_IN_MEM:
22451 case X86::FP64_TO_INT16_IN_MEM:
22452 case X86::FP64_TO_INT32_IN_MEM:
22453 case X86::FP64_TO_INT64_IN_MEM:
22454 case X86::FP80_TO_INT16_IN_MEM:
22455 case X86::FP80_TO_INT32_IN_MEM:
22456 case X86::FP80_TO_INT64_IN_MEM: {
22457 MachineFunction *F = BB->getParent();
22458 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22459 DebugLoc DL = MI->getDebugLoc();
22461 // Change the floating point control register to use "round towards zero"
22462 // mode when truncating to an integer value.
22463 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22464 addFrameReference(BuildMI(*BB, MI, DL,
22465 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22467 // Load the old value of the high byte of the control word...
22469 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22470 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22473 // Set the high part to be round to zero...
22474 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22477 // Reload the modified control word now...
22478 addFrameReference(BuildMI(*BB, MI, DL,
22479 TII->get(X86::FLDCW16m)), CWFrameIdx);
22481 // Restore the memory image of control word to original value
22482 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22485 // Get the X86 opcode to use.
22487 switch (MI->getOpcode()) {
22488 default: llvm_unreachable("illegal opcode!");
22489 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22490 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22491 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22492 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22493 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22494 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22495 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22496 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22497 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22501 MachineOperand &Op = MI->getOperand(0);
22503 AM.BaseType = X86AddressMode::RegBase;
22504 AM.Base.Reg = Op.getReg();
22506 AM.BaseType = X86AddressMode::FrameIndexBase;
22507 AM.Base.FrameIndex = Op.getIndex();
22509 Op = MI->getOperand(1);
22511 AM.Scale = Op.getImm();
22512 Op = MI->getOperand(2);
22514 AM.IndexReg = Op.getImm();
22515 Op = MI->getOperand(3);
22516 if (Op.isGlobal()) {
22517 AM.GV = Op.getGlobal();
22519 AM.Disp = Op.getImm();
22521 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22522 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22524 // Reload the original control word now.
22525 addFrameReference(BuildMI(*BB, MI, DL,
22526 TII->get(X86::FLDCW16m)), CWFrameIdx);
22528 MI->eraseFromParent(); // The pseudo instruction is gone now.
22531 // String/text processing lowering.
22532 case X86::PCMPISTRM128REG:
22533 case X86::VPCMPISTRM128REG:
22534 case X86::PCMPISTRM128MEM:
22535 case X86::VPCMPISTRM128MEM:
22536 case X86::PCMPESTRM128REG:
22537 case X86::VPCMPESTRM128REG:
22538 case X86::PCMPESTRM128MEM:
22539 case X86::VPCMPESTRM128MEM:
22540 assert(Subtarget->hasSSE42() &&
22541 "Target must have SSE4.2 or AVX features enabled");
22542 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22544 // String/text processing lowering.
22545 case X86::PCMPISTRIREG:
22546 case X86::VPCMPISTRIREG:
22547 case X86::PCMPISTRIMEM:
22548 case X86::VPCMPISTRIMEM:
22549 case X86::PCMPESTRIREG:
22550 case X86::VPCMPESTRIREG:
22551 case X86::PCMPESTRIMEM:
22552 case X86::VPCMPESTRIMEM:
22553 assert(Subtarget->hasSSE42() &&
22554 "Target must have SSE4.2 or AVX features enabled");
22555 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22557 // Thread synchronization.
22559 return EmitMonitor(MI, BB, Subtarget);
22563 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22565 case X86::VASTART_SAVE_XMM_REGS:
22566 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22568 case X86::VAARG_64:
22569 return EmitVAARG64WithCustomInserter(MI, BB);
22571 case X86::EH_SjLj_SetJmp32:
22572 case X86::EH_SjLj_SetJmp64:
22573 return emitEHSjLjSetJmp(MI, BB);
22575 case X86::EH_SjLj_LongJmp32:
22576 case X86::EH_SjLj_LongJmp64:
22577 return emitEHSjLjLongJmp(MI, BB);
22579 case TargetOpcode::STATEPOINT:
22580 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22581 // this point in the process. We diverge later.
22582 return emitPatchPoint(MI, BB);
22584 case TargetOpcode::STACKMAP:
22585 case TargetOpcode::PATCHPOINT:
22586 return emitPatchPoint(MI, BB);
22588 case X86::VFMADDPDr213r:
22589 case X86::VFMADDPSr213r:
22590 case X86::VFMADDSDr213r:
22591 case X86::VFMADDSSr213r:
22592 case X86::VFMSUBPDr213r:
22593 case X86::VFMSUBPSr213r:
22594 case X86::VFMSUBSDr213r:
22595 case X86::VFMSUBSSr213r:
22596 case X86::VFNMADDPDr213r:
22597 case X86::VFNMADDPSr213r:
22598 case X86::VFNMADDSDr213r:
22599 case X86::VFNMADDSSr213r:
22600 case X86::VFNMSUBPDr213r:
22601 case X86::VFNMSUBPSr213r:
22602 case X86::VFNMSUBSDr213r:
22603 case X86::VFNMSUBSSr213r:
22604 case X86::VFMADDSUBPDr213r:
22605 case X86::VFMADDSUBPSr213r:
22606 case X86::VFMSUBADDPDr213r:
22607 case X86::VFMSUBADDPSr213r:
22608 case X86::VFMADDPDr213rY:
22609 case X86::VFMADDPSr213rY:
22610 case X86::VFMSUBPDr213rY:
22611 case X86::VFMSUBPSr213rY:
22612 case X86::VFNMADDPDr213rY:
22613 case X86::VFNMADDPSr213rY:
22614 case X86::VFNMSUBPDr213rY:
22615 case X86::VFNMSUBPSr213rY:
22616 case X86::VFMADDSUBPDr213rY:
22617 case X86::VFMADDSUBPSr213rY:
22618 case X86::VFMSUBADDPDr213rY:
22619 case X86::VFMSUBADDPSr213rY:
22620 return emitFMA3Instr(MI, BB);
22624 //===----------------------------------------------------------------------===//
22625 // X86 Optimization Hooks
22626 //===----------------------------------------------------------------------===//
22628 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22631 const SelectionDAG &DAG,
22632 unsigned Depth) const {
22633 unsigned BitWidth = KnownZero.getBitWidth();
22634 unsigned Opc = Op.getOpcode();
22635 assert((Opc >= ISD::BUILTIN_OP_END ||
22636 Opc == ISD::INTRINSIC_WO_CHAIN ||
22637 Opc == ISD::INTRINSIC_W_CHAIN ||
22638 Opc == ISD::INTRINSIC_VOID) &&
22639 "Should use MaskedValueIsZero if you don't know whether Op"
22640 " is a target node!");
22642 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22656 // These nodes' second result is a boolean.
22657 if (Op.getResNo() == 0)
22660 case X86ISD::SETCC:
22661 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22663 case ISD::INTRINSIC_WO_CHAIN: {
22664 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22665 unsigned NumLoBits = 0;
22668 case Intrinsic::x86_sse_movmsk_ps:
22669 case Intrinsic::x86_avx_movmsk_ps_256:
22670 case Intrinsic::x86_sse2_movmsk_pd:
22671 case Intrinsic::x86_avx_movmsk_pd_256:
22672 case Intrinsic::x86_mmx_pmovmskb:
22673 case Intrinsic::x86_sse2_pmovmskb_128:
22674 case Intrinsic::x86_avx2_pmovmskb: {
22675 // High bits of movmskp{s|d}, pmovmskb are known zero.
22677 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22678 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22679 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22680 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22681 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22682 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22683 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22684 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22686 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22695 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22697 const SelectionDAG &,
22698 unsigned Depth) const {
22699 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22700 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22701 return Op.getValueType().getScalarSizeInBits();
22707 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22708 /// node is a GlobalAddress + offset.
22709 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22710 const GlobalValue* &GA,
22711 int64_t &Offset) const {
22712 if (N->getOpcode() == X86ISD::Wrapper) {
22713 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22714 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22715 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22719 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22722 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22723 /// FIXME: This could be expanded to support 512 bit vectors as well.
22724 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22725 TargetLowering::DAGCombinerInfo &DCI,
22726 const X86Subtarget* Subtarget) {
22728 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22729 SDValue V1 = SVOp->getOperand(0);
22730 SDValue V2 = SVOp->getOperand(1);
22731 MVT VT = SVOp->getSimpleValueType(0);
22732 unsigned NumElems = VT.getVectorNumElements();
22734 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22735 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22739 // V UNDEF BUILD_VECTOR UNDEF
22741 // CONCAT_VECTOR CONCAT_VECTOR
22744 // RESULT: V + zero extended
22746 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22747 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22748 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22751 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22754 // To match the shuffle mask, the first half of the mask should
22755 // be exactly the first vector, and all the rest a splat with the
22756 // first element of the second one.
22757 for (unsigned i = 0; i != NumElems/2; ++i)
22758 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22759 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22762 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22763 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22764 if (Ld->hasNUsesOfValue(1, 0)) {
22765 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22766 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22768 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22770 Ld->getPointerInfo(),
22771 Ld->getAlignment(),
22772 false/*isVolatile*/, true/*ReadMem*/,
22773 false/*WriteMem*/);
22775 // Make sure the newly-created LOAD is in the same position as Ld in
22776 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22777 // and update uses of Ld's output chain to use the TokenFactor.
22778 if (Ld->hasAnyUseOfValue(1)) {
22779 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22780 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22781 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22782 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22783 SDValue(ResNode.getNode(), 1));
22786 return DAG.getBitcast(VT, ResNode);
22790 // Emit a zeroed vector and insert the desired subvector on its
22792 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22793 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22794 return DCI.CombineTo(N, InsV);
22800 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22803 /// This is the leaf of the recursive combinine below. When we have found some
22804 /// chain of single-use x86 shuffle instructions and accumulated the combined
22805 /// shuffle mask represented by them, this will try to pattern match that mask
22806 /// into either a single instruction if there is a special purpose instruction
22807 /// for this operation, or into a PSHUFB instruction which is a fully general
22808 /// instruction but should only be used to replace chains over a certain depth.
22809 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22810 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22811 TargetLowering::DAGCombinerInfo &DCI,
22812 const X86Subtarget *Subtarget) {
22813 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22815 // Find the operand that enters the chain. Note that multiple uses are OK
22816 // here, we're not going to remove the operand we find.
22817 SDValue Input = Op.getOperand(0);
22818 while (Input.getOpcode() == ISD::BITCAST)
22819 Input = Input.getOperand(0);
22821 MVT VT = Input.getSimpleValueType();
22822 MVT RootVT = Root.getSimpleValueType();
22825 if (Mask.size() == 1) {
22826 int Index = Mask[0];
22827 assert((Index >= 0 || Index == SM_SentinelUndef ||
22828 Index == SM_SentinelZero) &&
22829 "Invalid shuffle index found!");
22831 // We may end up with an accumulated mask of size 1 as a result of
22832 // widening of shuffle operands (see function canWidenShuffleElements).
22833 // If the only shuffle index is equal to SM_SentinelZero then propagate
22834 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22835 // mask, and therefore the entire chain of shuffles can be folded away.
22836 if (Index == SM_SentinelZero)
22837 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22839 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22844 // Use the float domain if the operand type is a floating point type.
22845 bool FloatDomain = VT.isFloatingPoint();
22847 // For floating point shuffles, we don't have free copies in the shuffle
22848 // instructions or the ability to load as part of the instruction, so
22849 // canonicalize their shuffles to UNPCK or MOV variants.
22851 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22852 // vectors because it can have a load folded into it that UNPCK cannot. This
22853 // doesn't preclude something switching to the shorter encoding post-RA.
22855 // FIXME: Should teach these routines about AVX vector widths.
22856 if (FloatDomain && VT.is128BitVector()) {
22857 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22858 bool Lo = Mask.equals({0, 0});
22861 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22862 // is no slower than UNPCKLPD but has the option to fold the input operand
22863 // into even an unaligned memory load.
22864 if (Lo && Subtarget->hasSSE3()) {
22865 Shuffle = X86ISD::MOVDDUP;
22866 ShuffleVT = MVT::v2f64;
22868 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22869 // than the UNPCK variants.
22870 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22871 ShuffleVT = MVT::v4f32;
22873 if (Depth == 1 && Root->getOpcode() == Shuffle)
22874 return false; // Nothing to do!
22875 Op = DAG.getBitcast(ShuffleVT, Input);
22876 DCI.AddToWorklist(Op.getNode());
22877 if (Shuffle == X86ISD::MOVDDUP)
22878 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22880 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22881 DCI.AddToWorklist(Op.getNode());
22882 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22886 if (Subtarget->hasSSE3() &&
22887 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22888 bool Lo = Mask.equals({0, 0, 2, 2});
22889 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22890 MVT ShuffleVT = MVT::v4f32;
22891 if (Depth == 1 && Root->getOpcode() == Shuffle)
22892 return false; // Nothing to do!
22893 Op = DAG.getBitcast(ShuffleVT, Input);
22894 DCI.AddToWorklist(Op.getNode());
22895 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22896 DCI.AddToWorklist(Op.getNode());
22897 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22901 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22902 bool Lo = Mask.equals({0, 0, 1, 1});
22903 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22904 MVT ShuffleVT = MVT::v4f32;
22905 if (Depth == 1 && Root->getOpcode() == Shuffle)
22906 return false; // Nothing to do!
22907 Op = DAG.getBitcast(ShuffleVT, Input);
22908 DCI.AddToWorklist(Op.getNode());
22909 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22910 DCI.AddToWorklist(Op.getNode());
22911 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22917 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22918 // variants as none of these have single-instruction variants that are
22919 // superior to the UNPCK formulation.
22920 if (!FloatDomain && VT.is128BitVector() &&
22921 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22922 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22923 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22925 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22926 bool Lo = Mask[0] == 0;
22927 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22928 if (Depth == 1 && Root->getOpcode() == Shuffle)
22929 return false; // Nothing to do!
22931 switch (Mask.size()) {
22933 ShuffleVT = MVT::v8i16;
22936 ShuffleVT = MVT::v16i8;
22939 llvm_unreachable("Impossible mask size!");
22941 Op = DAG.getBitcast(ShuffleVT, Input);
22942 DCI.AddToWorklist(Op.getNode());
22943 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22944 DCI.AddToWorklist(Op.getNode());
22945 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22950 // Don't try to re-form single instruction chains under any circumstances now
22951 // that we've done encoding canonicalization for them.
22955 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22956 // can replace them with a single PSHUFB instruction profitably. Intel's
22957 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22958 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22959 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22960 SmallVector<SDValue, 16> PSHUFBMask;
22961 int NumBytes = VT.getSizeInBits() / 8;
22962 int Ratio = NumBytes / Mask.size();
22963 for (int i = 0; i < NumBytes; ++i) {
22964 if (Mask[i / Ratio] == SM_SentinelUndef) {
22965 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22968 int M = Mask[i / Ratio] != SM_SentinelZero
22969 ? Ratio * Mask[i / Ratio] + i % Ratio
22971 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22973 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22974 Op = DAG.getBitcast(ByteVT, Input);
22975 DCI.AddToWorklist(Op.getNode());
22976 SDValue PSHUFBMaskOp =
22977 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22978 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22979 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22980 DCI.AddToWorklist(Op.getNode());
22981 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22986 // Failed to find any combines.
22990 /// \brief Fully generic combining of x86 shuffle instructions.
22992 /// This should be the last combine run over the x86 shuffle instructions. Once
22993 /// they have been fully optimized, this will recursively consider all chains
22994 /// of single-use shuffle instructions, build a generic model of the cumulative
22995 /// shuffle operation, and check for simpler instructions which implement this
22996 /// operation. We use this primarily for two purposes:
22998 /// 1) Collapse generic shuffles to specialized single instructions when
22999 /// equivalent. In most cases, this is just an encoding size win, but
23000 /// sometimes we will collapse multiple generic shuffles into a single
23001 /// special-purpose shuffle.
23002 /// 2) Look for sequences of shuffle instructions with 3 or more total
23003 /// instructions, and replace them with the slightly more expensive SSSE3
23004 /// PSHUFB instruction if available. We do this as the last combining step
23005 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
23006 /// a suitable short sequence of other instructions. The PHUFB will either
23007 /// use a register or have to read from memory and so is slightly (but only
23008 /// slightly) more expensive than the other shuffle instructions.
23010 /// Because this is inherently a quadratic operation (for each shuffle in
23011 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
23012 /// This should never be an issue in practice as the shuffle lowering doesn't
23013 /// produce sequences of more than 8 instructions.
23015 /// FIXME: We will currently miss some cases where the redundant shuffling
23016 /// would simplify under the threshold for PSHUFB formation because of
23017 /// combine-ordering. To fix this, we should do the redundant instruction
23018 /// combining in this recursive walk.
23019 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
23020 ArrayRef<int> RootMask,
23021 int Depth, bool HasPSHUFB,
23023 TargetLowering::DAGCombinerInfo &DCI,
23024 const X86Subtarget *Subtarget) {
23025 // Bound the depth of our recursive combine because this is ultimately
23026 // quadratic in nature.
23030 // Directly rip through bitcasts to find the underlying operand.
23031 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
23032 Op = Op.getOperand(0);
23034 MVT VT = Op.getSimpleValueType();
23035 if (!VT.isVector())
23036 return false; // Bail if we hit a non-vector.
23038 assert(Root.getSimpleValueType().isVector() &&
23039 "Shuffles operate on vector types!");
23040 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
23041 "Can only combine shuffles of the same vector register size.");
23043 if (!isTargetShuffle(Op.getOpcode()))
23045 SmallVector<int, 16> OpMask;
23047 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
23048 // We only can combine unary shuffles which we can decode the mask for.
23049 if (!HaveMask || !IsUnary)
23052 assert(VT.getVectorNumElements() == OpMask.size() &&
23053 "Different mask size from vector size!");
23054 assert(((RootMask.size() > OpMask.size() &&
23055 RootMask.size() % OpMask.size() == 0) ||
23056 (OpMask.size() > RootMask.size() &&
23057 OpMask.size() % RootMask.size() == 0) ||
23058 OpMask.size() == RootMask.size()) &&
23059 "The smaller number of elements must divide the larger.");
23060 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
23061 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
23062 assert(((RootRatio == 1 && OpRatio == 1) ||
23063 (RootRatio == 1) != (OpRatio == 1)) &&
23064 "Must not have a ratio for both incoming and op masks!");
23066 SmallVector<int, 16> Mask;
23067 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
23069 // Merge this shuffle operation's mask into our accumulated mask. Note that
23070 // this shuffle's mask will be the first applied to the input, followed by the
23071 // root mask to get us all the way to the root value arrangement. The reason
23072 // for this order is that we are recursing up the operation chain.
23073 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
23074 int RootIdx = i / RootRatio;
23075 if (RootMask[RootIdx] < 0) {
23076 // This is a zero or undef lane, we're done.
23077 Mask.push_back(RootMask[RootIdx]);
23081 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
23082 int OpIdx = RootMaskedIdx / OpRatio;
23083 if (OpMask[OpIdx] < 0) {
23084 // The incoming lanes are zero or undef, it doesn't matter which ones we
23086 Mask.push_back(OpMask[OpIdx]);
23090 // Ok, we have non-zero lanes, map them through.
23091 Mask.push_back(OpMask[OpIdx] * OpRatio +
23092 RootMaskedIdx % OpRatio);
23095 // See if we can recurse into the operand to combine more things.
23096 switch (Op.getOpcode()) {
23097 case X86ISD::PSHUFB:
23099 case X86ISD::PSHUFD:
23100 case X86ISD::PSHUFHW:
23101 case X86ISD::PSHUFLW:
23102 if (Op.getOperand(0).hasOneUse() &&
23103 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
23104 HasPSHUFB, DAG, DCI, Subtarget))
23108 case X86ISD::UNPCKL:
23109 case X86ISD::UNPCKH:
23110 assert(Op.getOperand(0) == Op.getOperand(1) &&
23111 "We only combine unary shuffles!");
23112 // We can't check for single use, we have to check that this shuffle is the
23114 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
23115 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
23116 HasPSHUFB, DAG, DCI, Subtarget))
23121 // Minor canonicalization of the accumulated shuffle mask to make it easier
23122 // to match below. All this does is detect masks with squential pairs of
23123 // elements, and shrink them to the half-width mask. It does this in a loop
23124 // so it will reduce the size of the mask to the minimal width mask which
23125 // performs an equivalent shuffle.
23126 SmallVector<int, 16> WidenedMask;
23127 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
23128 Mask = std::move(WidenedMask);
23129 WidenedMask.clear();
23132 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
23136 /// \brief Get the PSHUF-style mask from PSHUF node.
23138 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
23139 /// PSHUF-style masks that can be reused with such instructions.
23140 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
23141 MVT VT = N.getSimpleValueType();
23142 SmallVector<int, 4> Mask;
23144 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
23148 // If we have more than 128-bits, only the low 128-bits of shuffle mask
23149 // matter. Check that the upper masks are repeats and remove them.
23150 if (VT.getSizeInBits() > 128) {
23151 int LaneElts = 128 / VT.getScalarSizeInBits();
23153 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
23154 for (int j = 0; j < LaneElts; ++j)
23155 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
23156 "Mask doesn't repeat in high 128-bit lanes!");
23158 Mask.resize(LaneElts);
23161 switch (N.getOpcode()) {
23162 case X86ISD::PSHUFD:
23164 case X86ISD::PSHUFLW:
23167 case X86ISD::PSHUFHW:
23168 Mask.erase(Mask.begin(), Mask.begin() + 4);
23169 for (int &M : Mask)
23173 llvm_unreachable("No valid shuffle instruction found!");
23177 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
23179 /// We walk up the chain and look for a combinable shuffle, skipping over
23180 /// shuffles that we could hoist this shuffle's transformation past without
23181 /// altering anything.
23183 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
23185 TargetLowering::DAGCombinerInfo &DCI) {
23186 assert(N.getOpcode() == X86ISD::PSHUFD &&
23187 "Called with something other than an x86 128-bit half shuffle!");
23190 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
23191 // of the shuffles in the chain so that we can form a fresh chain to replace
23193 SmallVector<SDValue, 8> Chain;
23194 SDValue V = N.getOperand(0);
23195 for (; V.hasOneUse(); V = V.getOperand(0)) {
23196 switch (V.getOpcode()) {
23198 return SDValue(); // Nothing combined!
23201 // Skip bitcasts as we always know the type for the target specific
23205 case X86ISD::PSHUFD:
23206 // Found another dword shuffle.
23209 case X86ISD::PSHUFLW:
23210 // Check that the low words (being shuffled) are the identity in the
23211 // dword shuffle, and the high words are self-contained.
23212 if (Mask[0] != 0 || Mask[1] != 1 ||
23213 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
23216 Chain.push_back(V);
23219 case X86ISD::PSHUFHW:
23220 // Check that the high words (being shuffled) are the identity in the
23221 // dword shuffle, and the low words are self-contained.
23222 if (Mask[2] != 2 || Mask[3] != 3 ||
23223 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
23226 Chain.push_back(V);
23229 case X86ISD::UNPCKL:
23230 case X86ISD::UNPCKH:
23231 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
23232 // shuffle into a preceding word shuffle.
23233 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
23234 V.getSimpleValueType().getVectorElementType() != MVT::i16)
23237 // Search for a half-shuffle which we can combine with.
23238 unsigned CombineOp =
23239 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
23240 if (V.getOperand(0) != V.getOperand(1) ||
23241 !V->isOnlyUserOf(V.getOperand(0).getNode()))
23243 Chain.push_back(V);
23244 V = V.getOperand(0);
23246 switch (V.getOpcode()) {
23248 return SDValue(); // Nothing to combine.
23250 case X86ISD::PSHUFLW:
23251 case X86ISD::PSHUFHW:
23252 if (V.getOpcode() == CombineOp)
23255 Chain.push_back(V);
23259 V = V.getOperand(0);
23263 } while (V.hasOneUse());
23266 // Break out of the loop if we break out of the switch.
23270 if (!V.hasOneUse())
23271 // We fell out of the loop without finding a viable combining instruction.
23274 // Merge this node's mask and our incoming mask.
23275 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23276 for (int &M : Mask)
23278 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
23279 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23281 // Rebuild the chain around this new shuffle.
23282 while (!Chain.empty()) {
23283 SDValue W = Chain.pop_back_val();
23285 if (V.getValueType() != W.getOperand(0).getValueType())
23286 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
23288 switch (W.getOpcode()) {
23290 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
23292 case X86ISD::UNPCKL:
23293 case X86ISD::UNPCKH:
23294 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
23297 case X86ISD::PSHUFD:
23298 case X86ISD::PSHUFLW:
23299 case X86ISD::PSHUFHW:
23300 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
23304 if (V.getValueType() != N.getValueType())
23305 V = DAG.getBitcast(N.getValueType(), V);
23307 // Return the new chain to replace N.
23311 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
23314 /// We walk up the chain, skipping shuffles of the other half and looking
23315 /// through shuffles which switch halves trying to find a shuffle of the same
23316 /// pair of dwords.
23317 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
23319 TargetLowering::DAGCombinerInfo &DCI) {
23321 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
23322 "Called with something other than an x86 128-bit half shuffle!");
23324 unsigned CombineOpcode = N.getOpcode();
23326 // Walk up a single-use chain looking for a combinable shuffle.
23327 SDValue V = N.getOperand(0);
23328 for (; V.hasOneUse(); V = V.getOperand(0)) {
23329 switch (V.getOpcode()) {
23331 return false; // Nothing combined!
23334 // Skip bitcasts as we always know the type for the target specific
23338 case X86ISD::PSHUFLW:
23339 case X86ISD::PSHUFHW:
23340 if (V.getOpcode() == CombineOpcode)
23343 // Other-half shuffles are no-ops.
23346 // Break out of the loop if we break out of the switch.
23350 if (!V.hasOneUse())
23351 // We fell out of the loop without finding a viable combining instruction.
23354 // Combine away the bottom node as its shuffle will be accumulated into
23355 // a preceding shuffle.
23356 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23358 // Record the old value.
23361 // Merge this node's mask and our incoming mask (adjusted to account for all
23362 // the pshufd instructions encountered).
23363 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23364 for (int &M : Mask)
23366 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23367 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23369 // Check that the shuffles didn't cancel each other out. If not, we need to
23370 // combine to the new one.
23372 // Replace the combinable shuffle with the combined one, updating all users
23373 // so that we re-evaluate the chain here.
23374 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23379 /// \brief Try to combine x86 target specific shuffles.
23380 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23381 TargetLowering::DAGCombinerInfo &DCI,
23382 const X86Subtarget *Subtarget) {
23384 MVT VT = N.getSimpleValueType();
23385 SmallVector<int, 4> Mask;
23387 switch (N.getOpcode()) {
23388 case X86ISD::PSHUFD:
23389 case X86ISD::PSHUFLW:
23390 case X86ISD::PSHUFHW:
23391 Mask = getPSHUFShuffleMask(N);
23392 assert(Mask.size() == 4);
23394 case X86ISD::UNPCKL: {
23395 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23396 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23397 // moves upper half elements into the lower half part. For example:
23399 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23401 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23403 // will be combined to:
23405 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23407 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23408 // happen due to advanced instructions.
23409 if (!VT.is128BitVector())
23412 auto Op0 = N.getOperand(0);
23413 auto Op1 = N.getOperand(1);
23414 if (Op0.getOpcode() == ISD::UNDEF &&
23415 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23416 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23418 unsigned NumElts = VT.getVectorNumElements();
23419 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23420 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23423 auto ShufOp = Op1.getOperand(0);
23424 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23425 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23433 // Nuke no-op shuffles that show up after combining.
23434 if (isNoopShuffleMask(Mask))
23435 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23437 // Look for simplifications involving one or two shuffle instructions.
23438 SDValue V = N.getOperand(0);
23439 switch (N.getOpcode()) {
23442 case X86ISD::PSHUFLW:
23443 case X86ISD::PSHUFHW:
23444 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23446 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23447 return SDValue(); // We combined away this shuffle, so we're done.
23449 // See if this reduces to a PSHUFD which is no more expensive and can
23450 // combine with more operations. Note that it has to at least flip the
23451 // dwords as otherwise it would have been removed as a no-op.
23452 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23453 int DMask[] = {0, 1, 2, 3};
23454 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23455 DMask[DOffset + 0] = DOffset + 1;
23456 DMask[DOffset + 1] = DOffset + 0;
23457 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23458 V = DAG.getBitcast(DVT, V);
23459 DCI.AddToWorklist(V.getNode());
23460 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23461 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23462 DCI.AddToWorklist(V.getNode());
23463 return DAG.getBitcast(VT, V);
23466 // Look for shuffle patterns which can be implemented as a single unpack.
23467 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23468 // only works when we have a PSHUFD followed by two half-shuffles.
23469 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23470 (V.getOpcode() == X86ISD::PSHUFLW ||
23471 V.getOpcode() == X86ISD::PSHUFHW) &&
23472 V.getOpcode() != N.getOpcode() &&
23474 SDValue D = V.getOperand(0);
23475 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23476 D = D.getOperand(0);
23477 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23478 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23479 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23480 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23481 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23483 for (int i = 0; i < 4; ++i) {
23484 WordMask[i + NOffset] = Mask[i] + NOffset;
23485 WordMask[i + VOffset] = VMask[i] + VOffset;
23487 // Map the word mask through the DWord mask.
23489 for (int i = 0; i < 8; ++i)
23490 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23491 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23492 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23493 // We can replace all three shuffles with an unpack.
23494 V = DAG.getBitcast(VT, D.getOperand(0));
23495 DCI.AddToWorklist(V.getNode());
23496 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23505 case X86ISD::PSHUFD:
23506 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23515 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23517 /// We combine this directly on the abstract vector shuffle nodes so it is
23518 /// easier to generically match. We also insert dummy vector shuffle nodes for
23519 /// the operands which explicitly discard the lanes which are unused by this
23520 /// operation to try to flow through the rest of the combiner the fact that
23521 /// they're unused.
23522 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23524 EVT VT = N->getValueType(0);
23526 // We only handle target-independent shuffles.
23527 // FIXME: It would be easy and harmless to use the target shuffle mask
23528 // extraction tool to support more.
23529 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23532 auto *SVN = cast<ShuffleVectorSDNode>(N);
23533 SmallVector<int, 8> Mask;
23534 for (int M : SVN->getMask())
23537 SDValue V1 = N->getOperand(0);
23538 SDValue V2 = N->getOperand(1);
23540 // We require the first shuffle operand to be the FSUB node, and the second to
23541 // be the FADD node.
23542 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23543 ShuffleVectorSDNode::commuteMask(Mask);
23545 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23548 // If there are other uses of these operations we can't fold them.
23549 if (!V1->hasOneUse() || !V2->hasOneUse())
23552 // Ensure that both operations have the same operands. Note that we can
23553 // commute the FADD operands.
23554 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23555 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23556 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23559 // We're looking for blends between FADD and FSUB nodes. We insist on these
23560 // nodes being lined up in a specific expected pattern.
23561 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23562 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23563 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23566 // Only specific types are legal at this point, assert so we notice if and
23567 // when these change.
23568 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23569 VT == MVT::v4f64) &&
23570 "Unknown vector type encountered!");
23572 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23575 /// PerformShuffleCombine - Performs several different shuffle combines.
23576 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23577 TargetLowering::DAGCombinerInfo &DCI,
23578 const X86Subtarget *Subtarget) {
23580 SDValue N0 = N->getOperand(0);
23581 SDValue N1 = N->getOperand(1);
23582 EVT VT = N->getValueType(0);
23584 // Don't create instructions with illegal types after legalize types has run.
23585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23586 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23589 // If we have legalized the vector types, look for blends of FADD and FSUB
23590 // nodes that we can fuse into an ADDSUB node.
23591 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23592 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23595 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23596 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23597 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23598 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23600 // During Type Legalization, when promoting illegal vector types,
23601 // the backend might introduce new shuffle dag nodes and bitcasts.
23603 // This code performs the following transformation:
23604 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23605 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23607 // We do this only if both the bitcast and the BINOP dag nodes have
23608 // one use. Also, perform this transformation only if the new binary
23609 // operation is legal. This is to avoid introducing dag nodes that
23610 // potentially need to be further expanded (or custom lowered) into a
23611 // less optimal sequence of dag nodes.
23612 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23613 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23614 N0.getOpcode() == ISD::BITCAST) {
23615 SDValue BC0 = N0.getOperand(0);
23616 EVT SVT = BC0.getValueType();
23617 unsigned Opcode = BC0.getOpcode();
23618 unsigned NumElts = VT.getVectorNumElements();
23620 if (BC0.hasOneUse() && SVT.isVector() &&
23621 SVT.getVectorNumElements() * 2 == NumElts &&
23622 TLI.isOperationLegal(Opcode, VT)) {
23623 bool CanFold = false;
23635 unsigned SVTNumElts = SVT.getVectorNumElements();
23636 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23637 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23638 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23639 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23640 CanFold = SVOp->getMaskElt(i) < 0;
23643 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23644 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23645 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23646 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23651 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23652 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23653 // consecutive, non-overlapping, and in the right order.
23654 SmallVector<SDValue, 16> Elts;
23655 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23656 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23658 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23661 if (isTargetShuffle(N->getOpcode())) {
23663 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23664 if (Shuffle.getNode())
23667 // Try recursively combining arbitrary sequences of x86 shuffle
23668 // instructions into higher-order shuffles. We do this after combining
23669 // specific PSHUF instruction sequences into their minimal form so that we
23670 // can evaluate how many specialized shuffle instructions are involved in
23671 // a particular chain.
23672 SmallVector<int, 1> NonceMask; // Just a placeholder.
23673 NonceMask.push_back(0);
23674 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23675 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23677 return SDValue(); // This routine will use CombineTo to replace N.
23683 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23684 /// specific shuffle of a load can be folded into a single element load.
23685 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23686 /// shuffles have been custom lowered so we need to handle those here.
23687 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23688 TargetLowering::DAGCombinerInfo &DCI) {
23689 if (DCI.isBeforeLegalizeOps())
23692 SDValue InVec = N->getOperand(0);
23693 SDValue EltNo = N->getOperand(1);
23695 if (!isa<ConstantSDNode>(EltNo))
23698 EVT OriginalVT = InVec.getValueType();
23700 if (InVec.getOpcode() == ISD::BITCAST) {
23701 // Don't duplicate a load with other uses.
23702 if (!InVec.hasOneUse())
23704 EVT BCVT = InVec.getOperand(0).getValueType();
23705 if (!BCVT.isVector() ||
23706 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23708 InVec = InVec.getOperand(0);
23711 EVT CurrentVT = InVec.getValueType();
23713 if (!isTargetShuffle(InVec.getOpcode()))
23716 // Don't duplicate a load with other uses.
23717 if (!InVec.hasOneUse())
23720 SmallVector<int, 16> ShuffleMask;
23722 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23723 ShuffleMask, UnaryShuffle))
23726 // Select the input vector, guarding against out of range extract vector.
23727 unsigned NumElems = CurrentVT.getVectorNumElements();
23728 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23729 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23730 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23731 : InVec.getOperand(1);
23733 // If inputs to shuffle are the same for both ops, then allow 2 uses
23734 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23735 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23737 if (LdNode.getOpcode() == ISD::BITCAST) {
23738 // Don't duplicate a load with other uses.
23739 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23742 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23743 LdNode = LdNode.getOperand(0);
23746 if (!ISD::isNormalLoad(LdNode.getNode()))
23749 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23751 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23754 EVT EltVT = N->getValueType(0);
23755 // If there's a bitcast before the shuffle, check if the load type and
23756 // alignment is valid.
23757 unsigned Align = LN0->getAlignment();
23758 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23759 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23760 EltVT.getTypeForEVT(*DAG.getContext()));
23762 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23765 // All checks match so transform back to vector_shuffle so that DAG combiner
23766 // can finish the job
23769 // Create shuffle node taking into account the case that its a unary shuffle
23770 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23771 : InVec.getOperand(1);
23772 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23773 InVec.getOperand(0), Shuffle,
23775 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23776 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23780 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23781 const X86Subtarget *Subtarget) {
23782 SDValue N0 = N->getOperand(0);
23783 EVT VT = N->getValueType(0);
23785 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23786 // special and don't usually play with other vector types, it's better to
23787 // handle them early to be sure we emit efficient code by avoiding
23788 // store-load conversions.
23789 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23790 N0.getValueType() == MVT::v2i32 &&
23791 isNullConstant(N0.getOperand(1))) {
23792 SDValue N00 = N0->getOperand(0);
23793 if (N00.getValueType() == MVT::i32)
23794 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23797 // Convert a bitcasted integer logic operation that has one bitcasted
23798 // floating-point operand and one constant operand into a floating-point
23799 // logic operation. This may create a load of the constant, but that is
23800 // cheaper than materializing the constant in an integer register and
23801 // transferring it to an SSE register or transferring the SSE operand to
23802 // integer register and back.
23804 switch (N0.getOpcode()) {
23805 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23806 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23807 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23808 default: return SDValue();
23810 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23811 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23812 isa<ConstantSDNode>(N0.getOperand(1)) &&
23813 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23814 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23815 SDValue N000 = N0.getOperand(0).getOperand(0);
23816 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23817 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23823 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23824 /// generation and convert it from being a bunch of shuffles and extracts
23825 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23826 /// storing the value and loading scalars back, while for x64 we should
23827 /// use 64-bit extracts and shifts.
23828 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23829 TargetLowering::DAGCombinerInfo &DCI) {
23830 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23833 SDValue InputVector = N->getOperand(0);
23834 SDLoc dl(InputVector);
23835 // Detect mmx to i32 conversion through a v2i32 elt extract.
23836 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23837 N->getValueType(0) == MVT::i32 &&
23838 InputVector.getValueType() == MVT::v2i32) {
23840 // The bitcast source is a direct mmx result.
23841 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23842 if (MMXSrc.getValueType() == MVT::x86mmx)
23843 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23844 N->getValueType(0),
23845 InputVector.getNode()->getOperand(0));
23847 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23848 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23849 MMXSrc.getValueType() == MVT::i64) {
23850 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23851 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23852 MMXSrcOp.getValueType() == MVT::v1i64 &&
23853 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23854 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23855 N->getValueType(0), MMXSrcOp.getOperand(0));
23859 EVT VT = N->getValueType(0);
23861 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23862 InputVector.getOpcode() == ISD::BITCAST &&
23863 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23864 uint64_t ExtractedElt =
23865 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23866 uint64_t InputValue =
23867 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23868 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23869 return DAG.getConstant(Res, dl, MVT::i1);
23871 // Only operate on vectors of 4 elements, where the alternative shuffling
23872 // gets to be more expensive.
23873 if (InputVector.getValueType() != MVT::v4i32)
23876 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23877 // single use which is a sign-extend or zero-extend, and all elements are
23879 SmallVector<SDNode *, 4> Uses;
23880 unsigned ExtractedElements = 0;
23881 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23882 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23883 if (UI.getUse().getResNo() != InputVector.getResNo())
23886 SDNode *Extract = *UI;
23887 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23890 if (Extract->getValueType(0) != MVT::i32)
23892 if (!Extract->hasOneUse())
23894 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23895 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23897 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23900 // Record which element was extracted.
23901 ExtractedElements |=
23902 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23904 Uses.push_back(Extract);
23907 // If not all the elements were used, this may not be worthwhile.
23908 if (ExtractedElements != 15)
23911 // Ok, we've now decided to do the transformation.
23912 // If 64-bit shifts are legal, use the extract-shift sequence,
23913 // otherwise bounce the vector off the cache.
23914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23917 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23918 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23919 auto &DL = DAG.getDataLayout();
23920 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23921 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23922 DAG.getConstant(0, dl, VecIdxTy));
23923 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23924 DAG.getConstant(1, dl, VecIdxTy));
23926 SDValue ShAmt = DAG.getConstant(
23927 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23928 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23929 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23930 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23931 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23932 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23933 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23935 // Store the value to a temporary stack slot.
23936 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23937 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23938 MachinePointerInfo(), false, false, 0);
23940 EVT ElementType = InputVector.getValueType().getVectorElementType();
23941 unsigned EltSize = ElementType.getSizeInBits() / 8;
23943 // Replace each use (extract) with a load of the appropriate element.
23944 for (unsigned i = 0; i < 4; ++i) {
23945 uint64_t Offset = EltSize * i;
23946 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23947 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23949 SDValue ScalarAddr =
23950 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23952 // Load the scalar.
23953 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23954 ScalarAddr, MachinePointerInfo(),
23955 false, false, false, 0);
23960 // Replace the extracts
23961 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23962 UE = Uses.end(); UI != UE; ++UI) {
23963 SDNode *Extract = *UI;
23965 SDValue Idx = Extract->getOperand(1);
23966 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23967 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23970 // The replacement was made in place; don't return anything.
23975 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23976 const X86Subtarget *Subtarget) {
23978 SDValue Cond = N->getOperand(0);
23979 SDValue LHS = N->getOperand(1);
23980 SDValue RHS = N->getOperand(2);
23982 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23983 SDValue CondSrc = Cond->getOperand(0);
23984 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23985 Cond = CondSrc->getOperand(0);
23988 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23991 // A vselect where all conditions and data are constants can be optimized into
23992 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23993 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23994 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23997 unsigned MaskValue = 0;
23998 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
24001 MVT VT = N->getSimpleValueType(0);
24002 unsigned NumElems = VT.getVectorNumElements();
24003 SmallVector<int, 8> ShuffleMask(NumElems, -1);
24004 for (unsigned i = 0; i < NumElems; ++i) {
24005 // Be sure we emit undef where we can.
24006 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
24007 ShuffleMask[i] = -1;
24009 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
24012 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24013 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
24015 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
24018 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
24020 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
24021 TargetLowering::DAGCombinerInfo &DCI,
24022 const X86Subtarget *Subtarget) {
24024 SDValue Cond = N->getOperand(0);
24025 // Get the LHS/RHS of the select.
24026 SDValue LHS = N->getOperand(1);
24027 SDValue RHS = N->getOperand(2);
24028 EVT VT = LHS.getValueType();
24029 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24031 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
24032 // instructions match the semantics of the common C idiom x<y?x:y but not
24033 // x<=y?x:y, because of how they handle negative zero (which can be
24034 // ignored in unsafe-math mode).
24035 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
24036 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
24037 VT != MVT::f80 && VT != MVT::f128 &&
24038 (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
24039 (Subtarget->hasSSE2() ||
24040 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
24041 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24043 unsigned Opcode = 0;
24044 // Check for x CC y ? x : y.
24045 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24046 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24050 // Converting this to a min would handle NaNs incorrectly, and swapping
24051 // the operands would cause it to handle comparisons between positive
24052 // and negative zero incorrectly.
24053 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
24054 if (!DAG.getTarget().Options.UnsafeFPMath &&
24055 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
24057 std::swap(LHS, RHS);
24059 Opcode = X86ISD::FMIN;
24062 // Converting this to a min would handle comparisons between positive
24063 // and negative zero incorrectly.
24064 if (!DAG.getTarget().Options.UnsafeFPMath &&
24065 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
24067 Opcode = X86ISD::FMIN;
24070 // Converting this to a min would handle both negative zeros and NaNs
24071 // incorrectly, but we can swap the operands to fix both.
24072 std::swap(LHS, RHS);
24076 Opcode = X86ISD::FMIN;
24080 // Converting this to a max would handle comparisons between positive
24081 // and negative zero incorrectly.
24082 if (!DAG.getTarget().Options.UnsafeFPMath &&
24083 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
24085 Opcode = X86ISD::FMAX;
24088 // Converting this to a max would handle NaNs incorrectly, and swapping
24089 // the operands would cause it to handle comparisons between positive
24090 // and negative zero incorrectly.
24091 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
24092 if (!DAG.getTarget().Options.UnsafeFPMath &&
24093 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
24095 std::swap(LHS, RHS);
24097 Opcode = X86ISD::FMAX;
24100 // Converting this to a max would handle both negative zeros and NaNs
24101 // incorrectly, but we can swap the operands to fix both.
24102 std::swap(LHS, RHS);
24106 Opcode = X86ISD::FMAX;
24109 // Check for x CC y ? y : x -- a min/max with reversed arms.
24110 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
24111 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
24115 // Converting this to a min would handle comparisons between positive
24116 // and negative zero incorrectly, and swapping the operands would
24117 // cause it to handle NaNs incorrectly.
24118 if (!DAG.getTarget().Options.UnsafeFPMath &&
24119 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
24120 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24122 std::swap(LHS, RHS);
24124 Opcode = X86ISD::FMIN;
24127 // Converting this to a min would handle NaNs incorrectly.
24128 if (!DAG.getTarget().Options.UnsafeFPMath &&
24129 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
24131 Opcode = X86ISD::FMIN;
24134 // Converting this to a min would handle both negative zeros and NaNs
24135 // incorrectly, but we can swap the operands to fix both.
24136 std::swap(LHS, RHS);
24140 Opcode = X86ISD::FMIN;
24144 // Converting this to a max would handle NaNs incorrectly.
24145 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24147 Opcode = X86ISD::FMAX;
24150 // Converting this to a max would handle comparisons between positive
24151 // and negative zero incorrectly, and swapping the operands would
24152 // cause it to handle NaNs incorrectly.
24153 if (!DAG.getTarget().Options.UnsafeFPMath &&
24154 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
24155 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24157 std::swap(LHS, RHS);
24159 Opcode = X86ISD::FMAX;
24162 // Converting this to a max would handle both negative zeros and NaNs
24163 // incorrectly, but we can swap the operands to fix both.
24164 std::swap(LHS, RHS);
24168 Opcode = X86ISD::FMAX;
24174 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
24177 EVT CondVT = Cond.getValueType();
24178 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
24179 CondVT.getVectorElementType() == MVT::i1) {
24180 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
24181 // lowering on KNL. In this case we convert it to
24182 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
24183 // The same situation for all 128 and 256-bit vectors of i8 and i16.
24184 // Since SKX these selects have a proper lowering.
24185 EVT OpVT = LHS.getValueType();
24186 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
24187 (OpVT.getVectorElementType() == MVT::i8 ||
24188 OpVT.getVectorElementType() == MVT::i16) &&
24189 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
24190 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
24191 DCI.AddToWorklist(Cond.getNode());
24192 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
24195 // If this is a select between two integer constants, try to do some
24197 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
24198 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
24199 // Don't do this for crazy integer types.
24200 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
24201 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
24202 // so that TrueC (the true value) is larger than FalseC.
24203 bool NeedsCondInvert = false;
24205 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
24206 // Efficiently invertible.
24207 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
24208 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
24209 isa<ConstantSDNode>(Cond.getOperand(1))))) {
24210 NeedsCondInvert = true;
24211 std::swap(TrueC, FalseC);
24214 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
24215 if (FalseC->getAPIntValue() == 0 &&
24216 TrueC->getAPIntValue().isPowerOf2()) {
24217 if (NeedsCondInvert) // Invert the condition if needed.
24218 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24219 DAG.getConstant(1, DL, Cond.getValueType()));
24221 // Zero extend the condition if needed.
24222 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
24224 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24225 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
24226 DAG.getConstant(ShAmt, DL, MVT::i8));
24229 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
24230 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24231 if (NeedsCondInvert) // Invert the condition if needed.
24232 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24233 DAG.getConstant(1, DL, Cond.getValueType()));
24235 // Zero extend the condition if needed.
24236 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24237 FalseC->getValueType(0), Cond);
24238 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24239 SDValue(FalseC, 0));
24242 // Optimize cases that will turn into an LEA instruction. This requires
24243 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24244 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24245 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24246 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24248 bool isFastMultiplier = false;
24250 switch ((unsigned char)Diff) {
24252 case 1: // result = add base, cond
24253 case 2: // result = lea base( , cond*2)
24254 case 3: // result = lea base(cond, cond*2)
24255 case 4: // result = lea base( , cond*4)
24256 case 5: // result = lea base(cond, cond*4)
24257 case 8: // result = lea base( , cond*8)
24258 case 9: // result = lea base(cond, cond*8)
24259 isFastMultiplier = true;
24264 if (isFastMultiplier) {
24265 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24266 if (NeedsCondInvert) // Invert the condition if needed.
24267 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24268 DAG.getConstant(1, DL, Cond.getValueType()));
24270 // Zero extend the condition if needed.
24271 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24273 // Scale the condition by the difference.
24275 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24276 DAG.getConstant(Diff, DL,
24277 Cond.getValueType()));
24279 // Add the base if non-zero.
24280 if (FalseC->getAPIntValue() != 0)
24281 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24282 SDValue(FalseC, 0));
24289 // Canonicalize max and min:
24290 // (x > y) ? x : y -> (x >= y) ? x : y
24291 // (x < y) ? x : y -> (x <= y) ? x : y
24292 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
24293 // the need for an extra compare
24294 // against zero. e.g.
24295 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
24297 // testl %edi, %edi
24299 // cmovgl %edi, %eax
24303 // cmovsl %eax, %edi
24304 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24305 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24306 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24307 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24312 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
24313 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
24314 Cond.getOperand(0), Cond.getOperand(1), NewCC);
24315 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
24320 // Early exit check
24321 if (!TLI.isTypeLegal(VT))
24324 // Match VSELECTs into subs with unsigned saturation.
24325 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24326 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
24327 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
24328 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
24329 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24331 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
24332 // left side invert the predicate to simplify logic below.
24334 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
24336 CC = ISD::getSetCCInverse(CC, true);
24337 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
24341 if (Other.getNode() && Other->getNumOperands() == 2 &&
24342 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
24343 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
24344 SDValue CondRHS = Cond->getOperand(1);
24346 // Look for a general sub with unsigned saturation first.
24347 // x >= y ? x-y : 0 --> subus x, y
24348 // x > y ? x-y : 0 --> subus x, y
24349 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
24350 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
24351 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
24353 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
24354 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
24355 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
24356 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
24357 // If the RHS is a constant we have to reverse the const
24358 // canonicalization.
24359 // x > C-1 ? x+-C : 0 --> subus x, C
24360 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24361 CondRHSConst->getAPIntValue() ==
24362 (-OpRHSConst->getAPIntValue() - 1))
24363 return DAG.getNode(
24364 X86ISD::SUBUS, DL, VT, OpLHS,
24365 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
24367 // Another special case: If C was a sign bit, the sub has been
24368 // canonicalized into a xor.
24369 // FIXME: Would it be better to use computeKnownBits to determine
24370 // whether it's safe to decanonicalize the xor?
24371 // x s< 0 ? x^C : 0 --> subus x, C
24372 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24373 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
24374 OpRHSConst->getAPIntValue().isSignBit())
24375 // Note that we have to rebuild the RHS constant here to ensure we
24376 // don't rely on particular values of undef lanes.
24377 return DAG.getNode(
24378 X86ISD::SUBUS, DL, VT, OpLHS,
24379 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24384 // Simplify vector selection if condition value type matches vselect
24386 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24387 assert(Cond.getValueType().isVector() &&
24388 "vector select expects a vector selector!");
24390 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24391 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24393 // Try invert the condition if true value is not all 1s and false value
24395 if (!TValIsAllOnes && !FValIsAllZeros &&
24396 // Check if the selector will be produced by CMPP*/PCMP*
24397 Cond.getOpcode() == ISD::SETCC &&
24398 // Check if SETCC has already been promoted
24399 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24401 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24402 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24404 if (TValIsAllZeros || FValIsAllOnes) {
24405 SDValue CC = Cond.getOperand(2);
24406 ISD::CondCode NewCC =
24407 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24408 Cond.getOperand(0).getValueType().isInteger());
24409 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24410 std::swap(LHS, RHS);
24411 TValIsAllOnes = FValIsAllOnes;
24412 FValIsAllZeros = TValIsAllZeros;
24416 if (TValIsAllOnes || FValIsAllZeros) {
24419 if (TValIsAllOnes && FValIsAllZeros)
24421 else if (TValIsAllOnes)
24423 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24424 else if (FValIsAllZeros)
24425 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24426 DAG.getBitcast(CondVT, LHS));
24428 return DAG.getBitcast(VT, Ret);
24432 // We should generate an X86ISD::BLENDI from a vselect if its argument
24433 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24434 // constants. This specific pattern gets generated when we split a
24435 // selector for a 512 bit vector in a machine without AVX512 (but with
24436 // 256-bit vectors), during legalization:
24438 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24440 // Iff we find this pattern and the build_vectors are built from
24441 // constants, we translate the vselect into a shuffle_vector that we
24442 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24443 if ((N->getOpcode() == ISD::VSELECT ||
24444 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24445 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24446 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24447 if (Shuffle.getNode())
24451 // If this is a *dynamic* select (non-constant condition) and we can match
24452 // this node with one of the variable blend instructions, restructure the
24453 // condition so that the blends can use the high bit of each element and use
24454 // SimplifyDemandedBits to simplify the condition operand.
24455 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24456 !DCI.isBeforeLegalize() &&
24457 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24458 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24460 // Don't optimize vector selects that map to mask-registers.
24464 // We can only handle the cases where VSELECT is directly legal on the
24465 // subtarget. We custom lower VSELECT nodes with constant conditions and
24466 // this makes it hard to see whether a dynamic VSELECT will correctly
24467 // lower, so we both check the operation's status and explicitly handle the
24468 // cases where a *dynamic* blend will fail even though a constant-condition
24469 // blend could be custom lowered.
24470 // FIXME: We should find a better way to handle this class of problems.
24471 // Potentially, we should combine constant-condition vselect nodes
24472 // pre-legalization into shuffles and not mark as many types as custom
24474 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24476 // FIXME: We don't support i16-element blends currently. We could and
24477 // should support them by making *all* the bits in the condition be set
24478 // rather than just the high bit and using an i8-element blend.
24479 if (VT.getVectorElementType() == MVT::i16)
24481 // Dynamic blending was only available from SSE4.1 onward.
24482 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24484 // Byte blends are only available in AVX2
24485 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24488 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24489 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24491 APInt KnownZero, KnownOne;
24492 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24493 DCI.isBeforeLegalizeOps());
24494 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24495 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24497 // If we changed the computation somewhere in the DAG, this change
24498 // will affect all users of Cond.
24499 // Make sure it is fine and update all the nodes so that we do not
24500 // use the generic VSELECT anymore. Otherwise, we may perform
24501 // wrong optimizations as we messed up with the actual expectation
24502 // for the vector boolean values.
24503 if (Cond != TLO.Old) {
24504 // Check all uses of that condition operand to check whether it will be
24505 // consumed by non-BLEND instructions, which may depend on all bits are
24507 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24509 if (I->getOpcode() != ISD::VSELECT)
24510 // TODO: Add other opcodes eventually lowered into BLEND.
24513 // Update all the users of the condition, before committing the change,
24514 // so that the VSELECT optimizations that expect the correct vector
24515 // boolean value will not be triggered.
24516 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24518 DAG.ReplaceAllUsesOfValueWith(
24520 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24521 Cond, I->getOperand(1), I->getOperand(2)));
24522 DCI.CommitTargetLoweringOpt(TLO);
24525 // At this point, only Cond is changed. Change the condition
24526 // just for N to keep the opportunity to optimize all other
24527 // users their own way.
24528 DAG.ReplaceAllUsesOfValueWith(
24530 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24531 TLO.New, N->getOperand(1), N->getOperand(2)));
24539 // Check whether a boolean test is testing a boolean value generated by
24540 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24543 // Simplify the following patterns:
24544 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24545 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24546 // to (Op EFLAGS Cond)
24548 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24549 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24550 // to (Op EFLAGS !Cond)
24552 // where Op could be BRCOND or CMOV.
24554 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24555 // Quit if not CMP and SUB with its value result used.
24556 if (Cmp.getOpcode() != X86ISD::CMP &&
24557 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24560 // Quit if not used as a boolean value.
24561 if (CC != X86::COND_E && CC != X86::COND_NE)
24564 // Check CMP operands. One of them should be 0 or 1 and the other should be
24565 // an SetCC or extended from it.
24566 SDValue Op1 = Cmp.getOperand(0);
24567 SDValue Op2 = Cmp.getOperand(1);
24570 const ConstantSDNode* C = nullptr;
24571 bool needOppositeCond = (CC == X86::COND_E);
24572 bool checkAgainstTrue = false; // Is it a comparison against 1?
24574 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24576 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24578 else // Quit if all operands are not constants.
24581 if (C->getZExtValue() == 1) {
24582 needOppositeCond = !needOppositeCond;
24583 checkAgainstTrue = true;
24584 } else if (C->getZExtValue() != 0)
24585 // Quit if the constant is neither 0 or 1.
24588 bool truncatedToBoolWithAnd = false;
24589 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24590 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24591 SetCC.getOpcode() == ISD::TRUNCATE ||
24592 SetCC.getOpcode() == ISD::AND) {
24593 if (SetCC.getOpcode() == ISD::AND) {
24595 if (isOneConstant(SetCC.getOperand(0)))
24597 if (isOneConstant(SetCC.getOperand(1)))
24601 SetCC = SetCC.getOperand(OpIdx);
24602 truncatedToBoolWithAnd = true;
24604 SetCC = SetCC.getOperand(0);
24607 switch (SetCC.getOpcode()) {
24608 case X86ISD::SETCC_CARRY:
24609 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24610 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24611 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24612 // truncated to i1 using 'and'.
24613 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24615 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24616 "Invalid use of SETCC_CARRY!");
24618 case X86ISD::SETCC:
24619 // Set the condition code or opposite one if necessary.
24620 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24621 if (needOppositeCond)
24622 CC = X86::GetOppositeBranchCondition(CC);
24623 return SetCC.getOperand(1);
24624 case X86ISD::CMOV: {
24625 // Check whether false/true value has canonical one, i.e. 0 or 1.
24626 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24627 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24628 // Quit if true value is not a constant.
24631 // Quit if false value is not a constant.
24633 SDValue Op = SetCC.getOperand(0);
24634 // Skip 'zext' or 'trunc' node.
24635 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24636 Op.getOpcode() == ISD::TRUNCATE)
24637 Op = Op.getOperand(0);
24638 // A special case for rdrand/rdseed, where 0 is set if false cond is
24640 if ((Op.getOpcode() != X86ISD::RDRAND &&
24641 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24644 // Quit if false value is not the constant 0 or 1.
24645 bool FValIsFalse = true;
24646 if (FVal && FVal->getZExtValue() != 0) {
24647 if (FVal->getZExtValue() != 1)
24649 // If FVal is 1, opposite cond is needed.
24650 needOppositeCond = !needOppositeCond;
24651 FValIsFalse = false;
24653 // Quit if TVal is not the constant opposite of FVal.
24654 if (FValIsFalse && TVal->getZExtValue() != 1)
24656 if (!FValIsFalse && TVal->getZExtValue() != 0)
24658 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24659 if (needOppositeCond)
24660 CC = X86::GetOppositeBranchCondition(CC);
24661 return SetCC.getOperand(3);
24668 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24670 /// (X86or (X86setcc) (X86setcc))
24671 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24672 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24673 X86::CondCode &CC1, SDValue &Flags,
24675 if (Cond->getOpcode() == X86ISD::CMP) {
24676 if (!isNullConstant(Cond->getOperand(1)))
24679 Cond = Cond->getOperand(0);
24684 SDValue SetCC0, SetCC1;
24685 switch (Cond->getOpcode()) {
24686 default: return false;
24693 SetCC0 = Cond->getOperand(0);
24694 SetCC1 = Cond->getOperand(1);
24698 // Make sure we have SETCC nodes, using the same flags value.
24699 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24700 SetCC1.getOpcode() != X86ISD::SETCC ||
24701 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24704 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24705 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24706 Flags = SetCC0->getOperand(1);
24710 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24711 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24712 TargetLowering::DAGCombinerInfo &DCI,
24713 const X86Subtarget *Subtarget) {
24716 // If the flag operand isn't dead, don't touch this CMOV.
24717 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24720 SDValue FalseOp = N->getOperand(0);
24721 SDValue TrueOp = N->getOperand(1);
24722 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24723 SDValue Cond = N->getOperand(3);
24725 if (CC == X86::COND_E || CC == X86::COND_NE) {
24726 switch (Cond.getOpcode()) {
24730 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24731 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24732 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24738 Flags = checkBoolTestSetCCCombine(Cond, CC);
24739 if (Flags.getNode() &&
24740 // Extra check as FCMOV only supports a subset of X86 cond.
24741 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24742 SDValue Ops[] = { FalseOp, TrueOp,
24743 DAG.getConstant(CC, DL, MVT::i8), Flags };
24744 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24747 // If this is a select between two integer constants, try to do some
24748 // optimizations. Note that the operands are ordered the opposite of SELECT
24750 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24751 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24752 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24753 // larger than FalseC (the false value).
24754 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24755 CC = X86::GetOppositeBranchCondition(CC);
24756 std::swap(TrueC, FalseC);
24757 std::swap(TrueOp, FalseOp);
24760 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24761 // This is efficient for any integer data type (including i8/i16) and
24763 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24764 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24765 DAG.getConstant(CC, DL, MVT::i8), Cond);
24767 // Zero extend the condition if needed.
24768 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24770 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24771 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24772 DAG.getConstant(ShAmt, DL, MVT::i8));
24773 if (N->getNumValues() == 2) // Dead flag value?
24774 return DCI.CombineTo(N, Cond, SDValue());
24778 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24779 // for any integer data type, including i8/i16.
24780 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24781 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24782 DAG.getConstant(CC, DL, MVT::i8), Cond);
24784 // Zero extend the condition if needed.
24785 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24786 FalseC->getValueType(0), Cond);
24787 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24788 SDValue(FalseC, 0));
24790 if (N->getNumValues() == 2) // Dead flag value?
24791 return DCI.CombineTo(N, Cond, SDValue());
24795 // Optimize cases that will turn into an LEA instruction. This requires
24796 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24797 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24798 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24799 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24801 bool isFastMultiplier = false;
24803 switch ((unsigned char)Diff) {
24805 case 1: // result = add base, cond
24806 case 2: // result = lea base( , cond*2)
24807 case 3: // result = lea base(cond, cond*2)
24808 case 4: // result = lea base( , cond*4)
24809 case 5: // result = lea base(cond, cond*4)
24810 case 8: // result = lea base( , cond*8)
24811 case 9: // result = lea base(cond, cond*8)
24812 isFastMultiplier = true;
24817 if (isFastMultiplier) {
24818 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24819 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24820 DAG.getConstant(CC, DL, MVT::i8), Cond);
24821 // Zero extend the condition if needed.
24822 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24824 // Scale the condition by the difference.
24826 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24827 DAG.getConstant(Diff, DL, Cond.getValueType()));
24829 // Add the base if non-zero.
24830 if (FalseC->getAPIntValue() != 0)
24831 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24832 SDValue(FalseC, 0));
24833 if (N->getNumValues() == 2) // Dead flag value?
24834 return DCI.CombineTo(N, Cond, SDValue());
24841 // Handle these cases:
24842 // (select (x != c), e, c) -> select (x != c), e, x),
24843 // (select (x == c), c, e) -> select (x == c), x, e)
24844 // where the c is an integer constant, and the "select" is the combination
24845 // of CMOV and CMP.
24847 // The rationale for this change is that the conditional-move from a constant
24848 // needs two instructions, however, conditional-move from a register needs
24849 // only one instruction.
24851 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24852 // some instruction-combining opportunities. This opt needs to be
24853 // postponed as late as possible.
24855 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24856 // the DCI.xxxx conditions are provided to postpone the optimization as
24857 // late as possible.
24859 ConstantSDNode *CmpAgainst = nullptr;
24860 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24861 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24862 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24864 if (CC == X86::COND_NE &&
24865 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24866 CC = X86::GetOppositeBranchCondition(CC);
24867 std::swap(TrueOp, FalseOp);
24870 if (CC == X86::COND_E &&
24871 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24872 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24873 DAG.getConstant(CC, DL, MVT::i8), Cond };
24874 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24879 // Fold and/or of setcc's to double CMOV:
24880 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24881 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24883 // This combine lets us generate:
24884 // cmovcc1 (jcc1 if we don't have CMOV)
24890 // cmovne (jne if we don't have CMOV)
24891 // When we can't use the CMOV instruction, it might increase branch
24893 // When we can use CMOV, or when there is no mispredict, this improves
24894 // throughput and reduces register pressure.
24896 if (CC == X86::COND_NE) {
24898 X86::CondCode CC0, CC1;
24900 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24902 std::swap(FalseOp, TrueOp);
24903 CC0 = X86::GetOppositeBranchCondition(CC0);
24904 CC1 = X86::GetOppositeBranchCondition(CC1);
24907 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24909 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24910 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24911 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24912 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24920 /// PerformMulCombine - Optimize a single multiply with constant into two
24921 /// in order to implement it with two cheaper instructions, e.g.
24922 /// LEA + SHL, LEA + LEA.
24923 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24924 TargetLowering::DAGCombinerInfo &DCI) {
24925 // An imul is usually smaller than the alternative sequence.
24926 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24929 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24932 EVT VT = N->getValueType(0);
24933 if (VT != MVT::i64 && VT != MVT::i32)
24936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24939 uint64_t MulAmt = C->getZExtValue();
24940 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24943 uint64_t MulAmt1 = 0;
24944 uint64_t MulAmt2 = 0;
24945 if ((MulAmt % 9) == 0) {
24947 MulAmt2 = MulAmt / 9;
24948 } else if ((MulAmt % 5) == 0) {
24950 MulAmt2 = MulAmt / 5;
24951 } else if ((MulAmt % 3) == 0) {
24953 MulAmt2 = MulAmt / 3;
24959 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24961 if (isPowerOf2_64(MulAmt2) &&
24962 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24963 // If second multiplifer is pow2, issue it first. We want the multiply by
24964 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24966 std::swap(MulAmt1, MulAmt2);
24968 if (isPowerOf2_64(MulAmt1))
24969 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24970 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24972 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24973 DAG.getConstant(MulAmt1, DL, VT));
24975 if (isPowerOf2_64(MulAmt2))
24976 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24977 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24979 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24980 DAG.getConstant(MulAmt2, DL, VT));
24984 assert(MulAmt != 0 && MulAmt != (VT == MVT::i64 ? UINT64_MAX : UINT32_MAX)
24985 && "Both cases that could cause potential overflows should have "
24986 "already been handled.");
24987 if (isPowerOf2_64(MulAmt - 1))
24988 // (mul x, 2^N + 1) => (add (shl x, N), x)
24989 NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
24990 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24991 DAG.getConstant(Log2_64(MulAmt - 1), DL,
24994 else if (isPowerOf2_64(MulAmt + 1))
24995 // (mul x, 2^N - 1) => (sub (shl x, N), x)
24996 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getNode(ISD::SHL, DL, VT,
24998 DAG.getConstant(Log2_64(MulAmt + 1),
24999 DL, MVT::i8)), N->getOperand(0));
25003 // Do not add new nodes to DAG combiner worklist.
25004 DCI.CombineTo(N, NewMul, false);
25009 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
25010 SDValue N0 = N->getOperand(0);
25011 SDValue N1 = N->getOperand(1);
25012 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
25013 EVT VT = N0.getValueType();
25015 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
25016 // since the result of setcc_c is all zero's or all ones.
25017 if (VT.isInteger() && !VT.isVector() &&
25018 N1C && N0.getOpcode() == ISD::AND &&
25019 N0.getOperand(1).getOpcode() == ISD::Constant) {
25020 SDValue N00 = N0.getOperand(0);
25021 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
25022 APInt ShAmt = N1C->getAPIntValue();
25023 Mask = Mask.shl(ShAmt);
25024 bool MaskOK = false;
25025 // We can handle cases concerning bit-widening nodes containing setcc_c if
25026 // we carefully interrogate the mask to make sure we are semantics
25028 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
25029 // of the underlying setcc_c operation if the setcc_c was zero extended.
25030 // Consider the following example:
25031 // zext(setcc_c) -> i32 0x0000FFFF
25032 // c1 -> i32 0x0000FFFF
25033 // c2 -> i32 0x00000001
25034 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
25035 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
25036 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25038 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
25039 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
25041 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
25042 N00.getOpcode() == ISD::ANY_EXTEND) &&
25043 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
25044 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
25046 if (MaskOK && Mask != 0) {
25048 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
25052 // Hardware support for vector shifts is sparse which makes us scalarize the
25053 // vector operations in many cases. Also, on sandybridge ADD is faster than
25055 // (shl V, 1) -> add V,V
25056 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
25057 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
25058 assert(N0.getValueType().isVector() && "Invalid vector shift type");
25059 // We shift all of the values by one. In many cases we do not have
25060 // hardware support for this operation. This is better expressed as an ADD
25062 if (N1SplatC->getAPIntValue() == 1)
25063 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
25069 static SDValue PerformSRACombine(SDNode *N, SelectionDAG &DAG) {
25070 SDValue N0 = N->getOperand(0);
25071 SDValue N1 = N->getOperand(1);
25072 EVT VT = N0.getValueType();
25073 unsigned Size = VT.getSizeInBits();
25075 // fold (ashr (shl, a, [56,48,32,24,16]), SarConst)
25076 // into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or
25077 // into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
25078 // depending on sign of (SarConst - [56,48,32,24,16])
25080 // sexts in X86 are MOVs. The MOVs have the same code size
25081 // as above SHIFTs (only SHIFT on 1 has lower code size).
25082 // However the MOVs have 2 advantages to a SHIFT:
25083 // 1. MOVs can write to a register that differs from source
25084 // 2. MOVs accept memory operands
25086 if (!VT.isInteger() || VT.isVector() || N1.getOpcode() != ISD::Constant ||
25087 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
25088 N0.getOperand(1).getOpcode() != ISD::Constant)
25091 SDValue N00 = N0.getOperand(0);
25092 SDValue N01 = N0.getOperand(1);
25093 APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue();
25094 APInt SarConst = (cast<ConstantSDNode>(N1))->getAPIntValue();
25095 EVT CVT = N1.getValueType();
25097 if (SarConst.isNegative())
25100 for (MVT SVT : MVT::integer_valuetypes()) {
25101 unsigned ShiftSize = SVT.getSizeInBits();
25102 // skipping types without corresponding sext/zext and
25103 // ShlConst that is not one of [56,48,32,24,16]
25104 if (ShiftSize < 8 || ShiftSize > 64 || ShlConst != Size - ShiftSize)
25108 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N00, DAG.getValueType(SVT));
25109 SarConst = SarConst - (Size - ShiftSize);
25112 else if (SarConst.isNegative())
25113 return DAG.getNode(ISD::SHL, DL, VT, NN,
25114 DAG.getConstant(-SarConst, DL, CVT));
25116 return DAG.getNode(ISD::SRA, DL, VT, NN,
25117 DAG.getConstant(SarConst, DL, CVT));
25122 /// \brief Returns a vector of 0s if the node in input is a vector logical
25123 /// shift by a constant amount which is known to be bigger than or equal
25124 /// to the vector element size in bits.
25125 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
25126 const X86Subtarget *Subtarget) {
25127 EVT VT = N->getValueType(0);
25129 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
25130 (!Subtarget->hasInt256() ||
25131 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
25134 SDValue Amt = N->getOperand(1);
25136 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
25137 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
25138 APInt ShiftAmt = AmtSplat->getAPIntValue();
25139 unsigned MaxAmount =
25140 VT.getSimpleVT().getVectorElementType().getSizeInBits();
25142 // SSE2/AVX2 logical shifts always return a vector of 0s
25143 // if the shift amount is bigger than or equal to
25144 // the element size. The constant shift amount will be
25145 // encoded as a 8-bit immediate.
25146 if (ShiftAmt.trunc(8).uge(MaxAmount))
25147 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);
25153 /// PerformShiftCombine - Combine shifts.
25154 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
25155 TargetLowering::DAGCombinerInfo &DCI,
25156 const X86Subtarget *Subtarget) {
25157 if (N->getOpcode() == ISD::SHL)
25158 if (SDValue V = PerformSHLCombine(N, DAG))
25161 if (N->getOpcode() == ISD::SRA)
25162 if (SDValue V = PerformSRACombine(N, DAG))
25165 // Try to fold this logical shift into a zero vector.
25166 if (N->getOpcode() != ISD::SRA)
25167 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
25173 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
25174 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
25175 // and friends. Likewise for OR -> CMPNEQSS.
25176 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
25177 TargetLowering::DAGCombinerInfo &DCI,
25178 const X86Subtarget *Subtarget) {
25181 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
25182 // we're requiring SSE2 for both.
25183 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
25184 SDValue N0 = N->getOperand(0);
25185 SDValue N1 = N->getOperand(1);
25186 SDValue CMP0 = N0->getOperand(1);
25187 SDValue CMP1 = N1->getOperand(1);
25190 // The SETCCs should both refer to the same CMP.
25191 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
25194 SDValue CMP00 = CMP0->getOperand(0);
25195 SDValue CMP01 = CMP0->getOperand(1);
25196 EVT VT = CMP00.getValueType();
25198 if (VT == MVT::f32 || VT == MVT::f64) {
25199 bool ExpectingFlags = false;
25200 // Check for any users that want flags:
25201 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
25202 !ExpectingFlags && UI != UE; ++UI)
25203 switch (UI->getOpcode()) {
25208 ExpectingFlags = true;
25210 case ISD::CopyToReg:
25211 case ISD::SIGN_EXTEND:
25212 case ISD::ZERO_EXTEND:
25213 case ISD::ANY_EXTEND:
25217 if (!ExpectingFlags) {
25218 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
25219 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
25221 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
25222 X86::CondCode tmp = cc0;
25227 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
25228 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
25229 // FIXME: need symbolic constants for these magic numbers.
25230 // See X86ATTInstPrinter.cpp:printSSECC().
25231 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
25232 if (Subtarget->hasAVX512()) {
25233 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
25235 DAG.getConstant(x86cc, DL, MVT::i8));
25236 if (N->getValueType(0) != MVT::i1)
25237 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
25241 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
25242 CMP00.getValueType(), CMP00, CMP01,
25243 DAG.getConstant(x86cc, DL,
25246 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
25247 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
25249 if (is64BitFP && !Subtarget->is64Bit()) {
25250 // On a 32-bit target, we cannot bitcast the 64-bit float to a
25251 // 64-bit integer, since that's not a legal type. Since
25252 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
25253 // bits, but can do this little dance to extract the lowest 32 bits
25254 // and work with those going forward.
25255 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
25257 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
25258 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
25259 Vector32, DAG.getIntPtrConstant(0, DL));
25263 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
25264 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
25265 DAG.getConstant(1, DL, IntVT));
25266 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
25268 return OneBitOfTruth;
25276 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
25277 /// so it can be folded inside ANDNP.
25278 static bool CanFoldXORWithAllOnes(const SDNode *N) {
25279 EVT VT = N->getValueType(0);
25281 // Match direct AllOnes for 128 and 256-bit vectors
25282 if (ISD::isBuildVectorAllOnes(N))
25285 // Look through a bit convert.
25286 if (N->getOpcode() == ISD::BITCAST)
25287 N = N->getOperand(0).getNode();
25289 // Sometimes the operand may come from a insert_subvector building a 256-bit
25291 if (VT.is256BitVector() &&
25292 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
25293 SDValue V1 = N->getOperand(0);
25294 SDValue V2 = N->getOperand(1);
25296 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
25297 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
25298 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
25299 ISD::isBuildVectorAllOnes(V2.getNode()))
25306 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
25307 // register. In most cases we actually compare or select YMM-sized registers
25308 // and mixing the two types creates horrible code. This method optimizes
25309 // some of the transition sequences.
25310 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
25311 TargetLowering::DAGCombinerInfo &DCI,
25312 const X86Subtarget *Subtarget) {
25313 EVT VT = N->getValueType(0);
25314 if (!VT.is256BitVector())
25317 assert((N->getOpcode() == ISD::ANY_EXTEND ||
25318 N->getOpcode() == ISD::ZERO_EXTEND ||
25319 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
25321 SDValue Narrow = N->getOperand(0);
25322 EVT NarrowVT = Narrow->getValueType(0);
25323 if (!NarrowVT.is128BitVector())
25326 if (Narrow->getOpcode() != ISD::XOR &&
25327 Narrow->getOpcode() != ISD::AND &&
25328 Narrow->getOpcode() != ISD::OR)
25331 SDValue N0 = Narrow->getOperand(0);
25332 SDValue N1 = Narrow->getOperand(1);
25335 // The Left side has to be a trunc.
25336 if (N0.getOpcode() != ISD::TRUNCATE)
25339 // The type of the truncated inputs.
25340 EVT WideVT = N0->getOperand(0)->getValueType(0);
25344 // The right side has to be a 'trunc' or a constant vector.
25345 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
25346 ConstantSDNode *RHSConstSplat = nullptr;
25347 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
25348 RHSConstSplat = RHSBV->getConstantSplatNode();
25349 if (!RHSTrunc && !RHSConstSplat)
25352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25354 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25357 // Set N0 and N1 to hold the inputs to the new wide operation.
25358 N0 = N0->getOperand(0);
25359 if (RHSConstSplat) {
25360 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
25361 SDValue(RHSConstSplat, 0));
25362 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
25363 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
25364 } else if (RHSTrunc) {
25365 N1 = N1->getOperand(0);
25368 // Generate the wide operation.
25369 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
25370 unsigned Opcode = N->getOpcode();
25372 case ISD::ANY_EXTEND:
25374 case ISD::ZERO_EXTEND: {
25375 unsigned InBits = NarrowVT.getScalarSizeInBits();
25376 APInt Mask = APInt::getAllOnesValue(InBits);
25377 Mask = Mask.zext(VT.getScalarSizeInBits());
25378 return DAG.getNode(ISD::AND, DL, VT,
25379 Op, DAG.getConstant(Mask, DL, VT));
25381 case ISD::SIGN_EXTEND:
25382 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
25383 Op, DAG.getValueType(NarrowVT));
25385 llvm_unreachable("Unexpected opcode");
25389 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
25390 TargetLowering::DAGCombinerInfo &DCI,
25391 const X86Subtarget *Subtarget) {
25392 SDValue N0 = N->getOperand(0);
25393 SDValue N1 = N->getOperand(1);
25396 // A vector zext_in_reg may be represented as a shuffle,
25397 // feeding into a bitcast (this represents anyext) feeding into
25398 // an and with a mask.
25399 // We'd like to try to combine that into a shuffle with zero
25400 // plus a bitcast, removing the and.
25401 if (N0.getOpcode() != ISD::BITCAST ||
25402 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
25405 // The other side of the AND should be a splat of 2^C, where C
25406 // is the number of bits in the source type.
25407 if (N1.getOpcode() == ISD::BITCAST)
25408 N1 = N1.getOperand(0);
25409 if (N1.getOpcode() != ISD::BUILD_VECTOR)
25411 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
25413 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
25414 EVT SrcType = Shuffle->getValueType(0);
25416 // We expect a single-source shuffle
25417 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
25420 unsigned SrcSize = SrcType.getScalarSizeInBits();
25422 APInt SplatValue, SplatUndef;
25423 unsigned SplatBitSize;
25425 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
25426 SplatBitSize, HasAnyUndefs))
25429 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
25430 // Make sure the splat matches the mask we expect
25431 if (SplatBitSize > ResSize ||
25432 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
25435 // Make sure the input and output size make sense
25436 if (SrcSize >= ResSize || ResSize % SrcSize)
25439 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
25440 // The number of u's between each two values depends on the ratio between
25441 // the source and dest type.
25442 unsigned ZextRatio = ResSize / SrcSize;
25443 bool IsZext = true;
25444 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
25445 if (i % ZextRatio) {
25446 if (Shuffle->getMaskElt(i) > 0) {
25452 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
25453 // Expected element number
25463 // Ok, perform the transformation - replace the shuffle with
25464 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25465 // (instead of undef) where the k elements come from the zero vector.
25466 SmallVector<int, 8> Mask;
25467 unsigned NumElems = SrcType.getVectorNumElements();
25468 for (unsigned i = 0; i < NumElems; ++i)
25470 Mask.push_back(NumElems);
25472 Mask.push_back(i / ZextRatio);
25474 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25475 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25476 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25479 /// If both input operands of a logic op are being cast from floating point
25480 /// types, try to convert this into a floating point logic node to avoid
25481 /// unnecessary moves from SSE to integer registers.
25482 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25483 const X86Subtarget *Subtarget) {
25484 unsigned FPOpcode = ISD::DELETED_NODE;
25485 if (N->getOpcode() == ISD::AND)
25486 FPOpcode = X86ISD::FAND;
25487 else if (N->getOpcode() == ISD::OR)
25488 FPOpcode = X86ISD::FOR;
25489 else if (N->getOpcode() == ISD::XOR)
25490 FPOpcode = X86ISD::FXOR;
25492 assert(FPOpcode != ISD::DELETED_NODE &&
25493 "Unexpected input node for FP logic conversion");
25495 EVT VT = N->getValueType(0);
25496 SDValue N0 = N->getOperand(0);
25497 SDValue N1 = N->getOperand(1);
25499 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25500 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25501 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25502 SDValue N00 = N0.getOperand(0);
25503 SDValue N10 = N1.getOperand(0);
25504 EVT N00Type = N00.getValueType();
25505 EVT N10Type = N10.getValueType();
25506 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25507 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25508 return DAG.getBitcast(VT, FPLogic);
25514 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25515 TargetLowering::DAGCombinerInfo &DCI,
25516 const X86Subtarget *Subtarget) {
25517 if (DCI.isBeforeLegalizeOps())
25520 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25523 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25526 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25529 EVT VT = N->getValueType(0);
25530 SDValue N0 = N->getOperand(0);
25531 SDValue N1 = N->getOperand(1);
25534 // Create BEXTR instructions
25535 // BEXTR is ((X >> imm) & (2**size-1))
25536 if (VT == MVT::i32 || VT == MVT::i64) {
25537 // Check for BEXTR.
25538 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25539 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25540 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25541 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25542 if (MaskNode && ShiftNode) {
25543 uint64_t Mask = MaskNode->getZExtValue();
25544 uint64_t Shift = ShiftNode->getZExtValue();
25545 if (isMask_64(Mask)) {
25546 uint64_t MaskSize = countPopulation(Mask);
25547 if (Shift + MaskSize <= VT.getSizeInBits())
25548 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25549 DAG.getConstant(Shift | (MaskSize << 8), DL,
25558 // Want to form ANDNP nodes:
25559 // 1) In the hopes of then easily combining them with OR and AND nodes
25560 // to form PBLEND/PSIGN.
25561 // 2) To match ANDN packed intrinsics
25562 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25565 // Check LHS for vnot
25566 if (N0.getOpcode() == ISD::XOR &&
25567 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25568 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25569 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25571 // Check RHS for vnot
25572 if (N1.getOpcode() == ISD::XOR &&
25573 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25574 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25575 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25580 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25581 TargetLowering::DAGCombinerInfo &DCI,
25582 const X86Subtarget *Subtarget) {
25583 if (DCI.isBeforeLegalizeOps())
25586 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25589 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25592 SDValue N0 = N->getOperand(0);
25593 SDValue N1 = N->getOperand(1);
25594 EVT VT = N->getValueType(0);
25596 // look for psign/blend
25597 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25598 if (!Subtarget->hasSSSE3() ||
25599 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25602 // Canonicalize pandn to RHS
25603 if (N0.getOpcode() == X86ISD::ANDNP)
25605 // or (and (m, y), (pandn m, x))
25606 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25607 SDValue Mask = N1.getOperand(0);
25608 SDValue X = N1.getOperand(1);
25610 if (N0.getOperand(0) == Mask)
25611 Y = N0.getOperand(1);
25612 if (N0.getOperand(1) == Mask)
25613 Y = N0.getOperand(0);
25615 // Check to see if the mask appeared in both the AND and ANDNP and
25619 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25620 // Look through mask bitcast.
25621 if (Mask.getOpcode() == ISD::BITCAST)
25622 Mask = Mask.getOperand(0);
25623 if (X.getOpcode() == ISD::BITCAST)
25624 X = X.getOperand(0);
25625 if (Y.getOpcode() == ISD::BITCAST)
25626 Y = Y.getOperand(0);
25628 EVT MaskVT = Mask.getValueType();
25630 // Validate that the Mask operand is a vector sra node.
25631 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25632 // there is no psrai.b
25633 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25634 unsigned SraAmt = ~0;
25635 if (Mask.getOpcode() == ISD::SRA) {
25636 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25637 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25638 SraAmt = AmtConst->getZExtValue();
25639 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25640 SDValue SraC = Mask.getOperand(1);
25641 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25643 if ((SraAmt + 1) != EltBits)
25648 // Now we know we at least have a plendvb with the mask val. See if
25649 // we can form a psignb/w/d.
25650 // psign = x.type == y.type == mask.type && y = sub(0, x);
25651 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25652 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25653 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25654 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25655 "Unsupported VT for PSIGN");
25656 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25657 return DAG.getBitcast(VT, Mask);
25659 // PBLENDVB only available on SSE 4.1
25660 if (!Subtarget->hasSSE41())
25663 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25665 X = DAG.getBitcast(BlendVT, X);
25666 Y = DAG.getBitcast(BlendVT, Y);
25667 Mask = DAG.getBitcast(BlendVT, Mask);
25668 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25669 return DAG.getBitcast(VT, Mask);
25673 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25676 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25677 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25679 // SHLD/SHRD instructions have lower register pressure, but on some
25680 // platforms they have higher latency than the equivalent
25681 // series of shifts/or that would otherwise be generated.
25682 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25683 // have higher latencies and we are not optimizing for size.
25684 if (!OptForSize && Subtarget->isSHLDSlow())
25687 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25689 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25691 if (!N0.hasOneUse() || !N1.hasOneUse())
25694 SDValue ShAmt0 = N0.getOperand(1);
25695 if (ShAmt0.getValueType() != MVT::i8)
25697 SDValue ShAmt1 = N1.getOperand(1);
25698 if (ShAmt1.getValueType() != MVT::i8)
25700 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25701 ShAmt0 = ShAmt0.getOperand(0);
25702 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25703 ShAmt1 = ShAmt1.getOperand(0);
25706 unsigned Opc = X86ISD::SHLD;
25707 SDValue Op0 = N0.getOperand(0);
25708 SDValue Op1 = N1.getOperand(0);
25709 if (ShAmt0.getOpcode() == ISD::SUB) {
25710 Opc = X86ISD::SHRD;
25711 std::swap(Op0, Op1);
25712 std::swap(ShAmt0, ShAmt1);
25715 unsigned Bits = VT.getSizeInBits();
25716 if (ShAmt1.getOpcode() == ISD::SUB) {
25717 SDValue Sum = ShAmt1.getOperand(0);
25718 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25719 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25720 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25721 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25722 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25723 return DAG.getNode(Opc, DL, VT,
25725 DAG.getNode(ISD::TRUNCATE, DL,
25728 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25729 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25731 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25732 return DAG.getNode(Opc, DL, VT,
25733 N0.getOperand(0), N1.getOperand(0),
25734 DAG.getNode(ISD::TRUNCATE, DL,
25741 // Generate NEG and CMOV for integer abs.
25742 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25743 EVT VT = N->getValueType(0);
25745 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25746 // 8-bit integer abs to NEG and CMOV.
25747 if (VT.isInteger() && VT.getSizeInBits() == 8)
25750 SDValue N0 = N->getOperand(0);
25751 SDValue N1 = N->getOperand(1);
25754 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25755 // and change it to SUB and CMOV.
25756 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25757 N0.getOpcode() == ISD::ADD &&
25758 N0.getOperand(1) == N1 &&
25759 N1.getOpcode() == ISD::SRA &&
25760 N1.getOperand(0) == N0.getOperand(0))
25761 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25762 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25763 // Generate SUB & CMOV.
25764 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25765 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25767 SDValue Ops[] = { N0.getOperand(0), Neg,
25768 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25769 SDValue(Neg.getNode(), 1) };
25770 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25775 // Try to turn tests against the signbit in the form of:
25776 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25779 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25780 // This is only worth doing if the output type is i8.
25781 if (N->getValueType(0) != MVT::i8)
25784 SDValue N0 = N->getOperand(0);
25785 SDValue N1 = N->getOperand(1);
25787 // We should be performing an xor against a truncated shift.
25788 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25791 // Make sure we are performing an xor against one.
25792 if (!isOneConstant(N1))
25795 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25796 SDValue Shift = N0.getOperand(0);
25797 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25800 // Make sure we are truncating from one of i16, i32 or i64.
25801 EVT ShiftTy = Shift.getValueType();
25802 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25805 // Make sure the shift amount extracts the sign bit.
25806 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25807 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25810 // Create a greater-than comparison against -1.
25811 // N.B. Using SETGE against 0 works but we want a canonical looking
25812 // comparison, using SETGT matches up with what TranslateX86CC.
25814 SDValue ShiftOp = Shift.getOperand(0);
25815 EVT ShiftOpTy = ShiftOp.getValueType();
25816 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25817 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25821 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25822 TargetLowering::DAGCombinerInfo &DCI,
25823 const X86Subtarget *Subtarget) {
25824 if (DCI.isBeforeLegalizeOps())
25827 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25830 if (Subtarget->hasCMov())
25831 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25834 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25840 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25841 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25842 /// X86ISD::AVG instruction.
25843 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25844 const X86Subtarget *Subtarget, SDLoc DL) {
25845 if (!VT.isVector() || !VT.isSimple())
25847 EVT InVT = In.getValueType();
25848 unsigned NumElems = VT.getVectorNumElements();
25850 EVT ScalarVT = VT.getVectorElementType();
25851 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25852 isPowerOf2_32(NumElems)))
25855 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25856 // than the original input type (i8/i16).
25857 EVT InScalarVT = InVT.getVectorElementType();
25858 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25861 if (Subtarget->hasAVX512()) {
25862 if (VT.getSizeInBits() > 512)
25864 } else if (Subtarget->hasAVX2()) {
25865 if (VT.getSizeInBits() > 256)
25868 if (VT.getSizeInBits() > 128)
25872 // Detect the following pattern:
25874 // %1 = zext <N x i8> %a to <N x i32>
25875 // %2 = zext <N x i8> %b to <N x i32>
25876 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25877 // %4 = add nuw nsw <N x i32> %3, %2
25878 // %5 = lshr <N x i32> %N, <i32 1 x N>
25879 // %6 = trunc <N x i32> %5 to <N x i8>
25881 // In AVX512, the last instruction can also be a trunc store.
25883 if (In.getOpcode() != ISD::SRL)
25886 // A lambda checking the given SDValue is a constant vector and each element
25887 // is in the range [Min, Max].
25888 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25889 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25890 if (!BV || !BV->isConstant())
25892 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25893 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25896 uint64_t Val = C->getZExtValue();
25897 if (Val < Min || Val > Max)
25903 // Check if each element of the vector is left-shifted by one.
25904 auto LHS = In.getOperand(0);
25905 auto RHS = In.getOperand(1);
25906 if (!IsConstVectorInRange(RHS, 1, 1))
25908 if (LHS.getOpcode() != ISD::ADD)
25911 // Detect a pattern of a + b + 1 where the order doesn't matter.
25912 SDValue Operands[3];
25913 Operands[0] = LHS.getOperand(0);
25914 Operands[1] = LHS.getOperand(1);
25916 // Take care of the case when one of the operands is a constant vector whose
25917 // element is in the range [1, 256].
25918 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25919 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25920 Operands[0].getOperand(0).getValueType() == VT) {
25921 // The pattern is detected. Subtract one from the constant vector, then
25922 // demote it and emit X86ISD::AVG instruction.
25923 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25924 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25925 SmallVector<SDValue, 8>(NumElems, One));
25926 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25927 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25928 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25932 if (Operands[0].getOpcode() == ISD::ADD)
25933 std::swap(Operands[0], Operands[1]);
25934 else if (Operands[1].getOpcode() != ISD::ADD)
25936 Operands[2] = Operands[1].getOperand(0);
25937 Operands[1] = Operands[1].getOperand(1);
25939 // Now we have three operands of two additions. Check that one of them is a
25940 // constant vector with ones, and the other two are promoted from i8/i16.
25941 for (int i = 0; i < 3; ++i) {
25942 if (!IsConstVectorInRange(Operands[i], 1, 1))
25944 std::swap(Operands[i], Operands[2]);
25946 // Check if Operands[0] and Operands[1] are results of type promotion.
25947 for (int j = 0; j < 2; ++j)
25948 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25949 Operands[j].getOperand(0).getValueType() != VT)
25952 // The pattern is detected, emit X86ISD::AVG instruction.
25953 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25954 Operands[1].getOperand(0));
25960 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25961 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25962 TargetLowering::DAGCombinerInfo &DCI,
25963 const X86Subtarget *Subtarget) {
25964 LoadSDNode *Ld = cast<LoadSDNode>(N);
25965 EVT RegVT = Ld->getValueType(0);
25966 EVT MemVT = Ld->getMemoryVT();
25968 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25970 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25971 // into two 16-byte operations.
25972 ISD::LoadExtType Ext = Ld->getExtensionType();
25974 unsigned AddressSpace = Ld->getAddressSpace();
25975 unsigned Alignment = Ld->getAlignment();
25976 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25977 Ext == ISD::NON_EXTLOAD &&
25978 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25979 AddressSpace, Alignment, &Fast) && !Fast) {
25980 unsigned NumElems = RegVT.getVectorNumElements();
25984 SDValue Ptr = Ld->getBasePtr();
25985 SDValue Increment =
25986 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25988 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25990 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25991 Ld->getPointerInfo(), Ld->isVolatile(),
25992 Ld->isNonTemporal(), Ld->isInvariant(),
25994 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25995 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25996 Ld->getPointerInfo(), Ld->isVolatile(),
25997 Ld->isNonTemporal(), Ld->isInvariant(),
25998 std::min(16U, Alignment));
25999 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
26001 Load2.getValue(1));
26003 SDValue NewVec = DAG.getUNDEF(RegVT);
26004 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
26005 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
26006 return DCI.CombineTo(N, NewVec, TF, true);
26012 /// PerformMLOADCombine - Resolve extending loads
26013 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
26014 TargetLowering::DAGCombinerInfo &DCI,
26015 const X86Subtarget *Subtarget) {
26016 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
26017 if (Mld->getExtensionType() != ISD::SEXTLOAD)
26020 EVT VT = Mld->getValueType(0);
26021 unsigned NumElems = VT.getVectorNumElements();
26022 EVT LdVT = Mld->getMemoryVT();
26025 assert(LdVT != VT && "Cannot extend to the same type");
26026 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
26027 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
26028 // From, To sizes and ElemCount must be pow of two
26029 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
26030 "Unexpected size for extending masked load");
26032 unsigned SizeRatio = ToSz / FromSz;
26033 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
26035 // Create a type on which we perform the shuffle
26036 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26037 LdVT.getScalarType(), NumElems*SizeRatio);
26038 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26040 // Convert Src0 value
26041 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
26042 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
26043 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26044 for (unsigned i = 0; i != NumElems; ++i)
26045 ShuffleVec[i] = i * SizeRatio;
26047 // Can't shuffle using an illegal type.
26048 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
26049 "WideVecVT should be legal");
26050 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
26051 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
26053 // Prepare the new mask
26055 SDValue Mask = Mld->getMask();
26056 if (Mask.getValueType() == VT) {
26057 // Mask and original value have the same type
26058 NewMask = DAG.getBitcast(WideVecVT, Mask);
26059 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26060 for (unsigned i = 0; i != NumElems; ++i)
26061 ShuffleVec[i] = i * SizeRatio;
26062 for (unsigned i = NumElems; i != NumElems * SizeRatio; ++i)
26063 ShuffleVec[i] = NumElems * SizeRatio;
26064 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
26065 DAG.getConstant(0, dl, WideVecVT),
26069 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
26070 unsigned WidenNumElts = NumElems*SizeRatio;
26071 unsigned MaskNumElts = VT.getVectorNumElements();
26072 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
26075 unsigned NumConcat = WidenNumElts / MaskNumElts;
26076 SmallVector<SDValue, 16> Ops(NumConcat);
26077 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
26079 for (unsigned i = 1; i != NumConcat; ++i)
26082 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
26085 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
26086 Mld->getBasePtr(), NewMask, WideSrc0,
26087 Mld->getMemoryVT(), Mld->getMemOperand(),
26089 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
26090 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
26092 /// PerformMSTORECombine - Resolve truncating stores
26093 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
26094 const X86Subtarget *Subtarget) {
26095 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
26096 if (!Mst->isTruncatingStore())
26099 EVT VT = Mst->getValue().getValueType();
26100 unsigned NumElems = VT.getVectorNumElements();
26101 EVT StVT = Mst->getMemoryVT();
26104 assert(StVT != VT && "Cannot truncate to the same type");
26105 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
26106 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
26108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26110 // The truncating store is legal in some cases. For example
26111 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
26112 // are designated for truncate store.
26113 // In this case we don't need any further transformations.
26114 if (TLI.isTruncStoreLegal(VT, StVT))
26117 // From, To sizes and ElemCount must be pow of two
26118 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
26119 "Unexpected size for truncating masked store");
26120 // We are going to use the original vector elt for storing.
26121 // Accumulated smaller vector elements must be a multiple of the store size.
26122 assert (((NumElems * FromSz) % ToSz) == 0 &&
26123 "Unexpected ratio for truncating masked store");
26125 unsigned SizeRatio = FromSz / ToSz;
26126 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
26128 // Create a type on which we perform the shuffle
26129 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26130 StVT.getScalarType(), NumElems*SizeRatio);
26132 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26134 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
26135 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26136 for (unsigned i = 0; i != NumElems; ++i)
26137 ShuffleVec[i] = i * SizeRatio;
26139 // Can't shuffle using an illegal type.
26140 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
26141 "WideVecVT should be legal");
26143 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26144 DAG.getUNDEF(WideVecVT),
26148 SDValue Mask = Mst->getMask();
26149 if (Mask.getValueType() == VT) {
26150 // Mask and original value have the same type
26151 NewMask = DAG.getBitcast(WideVecVT, Mask);
26152 for (unsigned i = 0; i != NumElems; ++i)
26153 ShuffleVec[i] = i * SizeRatio;
26154 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
26155 ShuffleVec[i] = NumElems*SizeRatio;
26156 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
26157 DAG.getConstant(0, dl, WideVecVT),
26161 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
26162 unsigned WidenNumElts = NumElems*SizeRatio;
26163 unsigned MaskNumElts = VT.getVectorNumElements();
26164 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
26167 unsigned NumConcat = WidenNumElts / MaskNumElts;
26168 SmallVector<SDValue, 16> Ops(NumConcat);
26169 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
26171 for (unsigned i = 1; i != NumConcat; ++i)
26174 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
26177 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal,
26178 Mst->getBasePtr(), NewMask, StVT,
26179 Mst->getMemOperand(), false);
26181 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
26182 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
26183 const X86Subtarget *Subtarget) {
26184 StoreSDNode *St = cast<StoreSDNode>(N);
26185 EVT VT = St->getValue().getValueType();
26186 EVT StVT = St->getMemoryVT();
26188 SDValue StoredVal = St->getOperand(1);
26189 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26191 // If we are saving a concatenation of two XMM registers and 32-byte stores
26192 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
26194 unsigned AddressSpace = St->getAddressSpace();
26195 unsigned Alignment = St->getAlignment();
26196 if (VT.is256BitVector() && StVT == VT &&
26197 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
26198 AddressSpace, Alignment, &Fast) && !Fast) {
26199 unsigned NumElems = VT.getVectorNumElements();
26203 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
26204 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
26207 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
26208 SDValue Ptr0 = St->getBasePtr();
26209 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
26211 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
26212 St->getPointerInfo(), St->isVolatile(),
26213 St->isNonTemporal(), Alignment);
26214 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
26215 St->getPointerInfo(), St->isVolatile(),
26216 St->isNonTemporal(),
26217 std::min(16U, Alignment));
26218 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
26221 // Optimize trunc store (of multiple scalars) to shuffle and store.
26222 // First, pack all of the elements in one place. Next, store to memory
26223 // in fewer chunks.
26224 if (St->isTruncatingStore() && VT.isVector()) {
26225 // Check if we can detect an AVG pattern from the truncation. If yes,
26226 // replace the trunc store by a normal store with the result of X86ISD::AVG
26229 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
26231 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
26232 St->getPointerInfo(), St->isVolatile(),
26233 St->isNonTemporal(), St->getAlignment());
26235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26236 unsigned NumElems = VT.getVectorNumElements();
26237 assert(StVT != VT && "Cannot truncate to the same type");
26238 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
26239 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
26241 // The truncating store is legal in some cases. For example
26242 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
26243 // are designated for truncate store.
26244 // In this case we don't need any further transformations.
26245 if (TLI.isTruncStoreLegal(VT, StVT))
26248 // From, To sizes and ElemCount must be pow of two
26249 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
26250 // We are going to use the original vector elt for storing.
26251 // Accumulated smaller vector elements must be a multiple of the store size.
26252 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
26254 unsigned SizeRatio = FromSz / ToSz;
26256 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
26258 // Create a type on which we perform the shuffle
26259 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26260 StVT.getScalarType(), NumElems*SizeRatio);
26262 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26264 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
26265 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
26266 for (unsigned i = 0; i != NumElems; ++i)
26267 ShuffleVec[i] = i * SizeRatio;
26269 // Can't shuffle using an illegal type.
26270 if (!TLI.isTypeLegal(WideVecVT))
26273 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26274 DAG.getUNDEF(WideVecVT),
26276 // At this point all of the data is stored at the bottom of the
26277 // register. We now need to save it to mem.
26279 // Find the largest store unit
26280 MVT StoreType = MVT::i8;
26281 for (MVT Tp : MVT::integer_valuetypes()) {
26282 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
26286 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
26287 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
26288 (64 <= NumElems * ToSz))
26289 StoreType = MVT::f64;
26291 // Bitcast the original vector into a vector of store-size units
26292 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
26293 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
26294 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
26295 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
26296 SmallVector<SDValue, 8> Chains;
26297 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
26298 TLI.getPointerTy(DAG.getDataLayout()));
26299 SDValue Ptr = St->getBasePtr();
26301 // Perform one or more big stores into memory.
26302 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
26303 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
26304 StoreType, ShuffWide,
26305 DAG.getIntPtrConstant(i, dl));
26306 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
26307 St->getPointerInfo(), St->isVolatile(),
26308 St->isNonTemporal(), St->getAlignment());
26309 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26310 Chains.push_back(Ch);
26313 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
26316 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
26317 // the FP state in cases where an emms may be missing.
26318 // A preferable solution to the general problem is to figure out the right
26319 // places to insert EMMS. This qualifies as a quick hack.
26321 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
26322 if (VT.getSizeInBits() != 64)
26325 const Function *F = DAG.getMachineFunction().getFunction();
26326 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
26328 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
26329 if ((VT.isVector() ||
26330 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
26331 isa<LoadSDNode>(St->getValue()) &&
26332 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
26333 St->getChain().hasOneUse() && !St->isVolatile()) {
26334 SDNode* LdVal = St->getValue().getNode();
26335 LoadSDNode *Ld = nullptr;
26336 int TokenFactorIndex = -1;
26337 SmallVector<SDValue, 8> Ops;
26338 SDNode* ChainVal = St->getChain().getNode();
26339 // Must be a store of a load. We currently handle two cases: the load
26340 // is a direct child, and it's under an intervening TokenFactor. It is
26341 // possible to dig deeper under nested TokenFactors.
26342 if (ChainVal == LdVal)
26343 Ld = cast<LoadSDNode>(St->getChain());
26344 else if (St->getValue().hasOneUse() &&
26345 ChainVal->getOpcode() == ISD::TokenFactor) {
26346 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
26347 if (ChainVal->getOperand(i).getNode() == LdVal) {
26348 TokenFactorIndex = i;
26349 Ld = cast<LoadSDNode>(St->getValue());
26351 Ops.push_back(ChainVal->getOperand(i));
26355 if (!Ld || !ISD::isNormalLoad(Ld))
26358 // If this is not the MMX case, i.e. we are just turning i64 load/store
26359 // into f64 load/store, avoid the transformation if there are multiple
26360 // uses of the loaded value.
26361 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
26366 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
26367 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
26369 if (Subtarget->is64Bit() || F64IsLegal) {
26370 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
26371 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
26372 Ld->getPointerInfo(), Ld->isVolatile(),
26373 Ld->isNonTemporal(), Ld->isInvariant(),
26374 Ld->getAlignment());
26375 SDValue NewChain = NewLd.getValue(1);
26376 if (TokenFactorIndex != -1) {
26377 Ops.push_back(NewChain);
26378 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26380 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
26381 St->getPointerInfo(),
26382 St->isVolatile(), St->isNonTemporal(),
26383 St->getAlignment());
26386 // Otherwise, lower to two pairs of 32-bit loads / stores.
26387 SDValue LoAddr = Ld->getBasePtr();
26388 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
26389 DAG.getConstant(4, LdDL, MVT::i32));
26391 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
26392 Ld->getPointerInfo(),
26393 Ld->isVolatile(), Ld->isNonTemporal(),
26394 Ld->isInvariant(), Ld->getAlignment());
26395 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
26396 Ld->getPointerInfo().getWithOffset(4),
26397 Ld->isVolatile(), Ld->isNonTemporal(),
26399 MinAlign(Ld->getAlignment(), 4));
26401 SDValue NewChain = LoLd.getValue(1);
26402 if (TokenFactorIndex != -1) {
26403 Ops.push_back(LoLd);
26404 Ops.push_back(HiLd);
26405 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26408 LoAddr = St->getBasePtr();
26409 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
26410 DAG.getConstant(4, StDL, MVT::i32));
26412 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
26413 St->getPointerInfo(),
26414 St->isVolatile(), St->isNonTemporal(),
26415 St->getAlignment());
26416 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
26417 St->getPointerInfo().getWithOffset(4),
26419 St->isNonTemporal(),
26420 MinAlign(St->getAlignment(), 4));
26421 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
26424 // This is similar to the above case, but here we handle a scalar 64-bit
26425 // integer store that is extracted from a vector on a 32-bit target.
26426 // If we have SSE2, then we can treat it like a floating-point double
26427 // to get past legalization. The execution dependencies fixup pass will
26428 // choose the optimal machine instruction for the store if this really is
26429 // an integer or v2f32 rather than an f64.
26430 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
26431 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26432 SDValue OldExtract = St->getOperand(1);
26433 SDValue ExtOp0 = OldExtract.getOperand(0);
26434 unsigned VecSize = ExtOp0.getValueSizeInBits();
26435 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
26436 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
26437 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
26438 BitCast, OldExtract.getOperand(1));
26439 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
26440 St->getPointerInfo(), St->isVolatile(),
26441 St->isNonTemporal(), St->getAlignment());
26447 /// Return 'true' if this vector operation is "horizontal"
26448 /// and return the operands for the horizontal operation in LHS and RHS. A
26449 /// horizontal operation performs the binary operation on successive elements
26450 /// of its first operand, then on successive elements of its second operand,
26451 /// returning the resulting values in a vector. For example, if
26452 /// A = < float a0, float a1, float a2, float a3 >
26454 /// B = < float b0, float b1, float b2, float b3 >
26455 /// then the result of doing a horizontal operation on A and B is
26456 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26457 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26458 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26459 /// set to A, RHS to B, and the routine returns 'true'.
26460 /// Note that the binary operation should have the property that if one of the
26461 /// operands is UNDEF then the result is UNDEF.
26462 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26463 // Look for the following pattern: if
26464 // A = < float a0, float a1, float a2, float a3 >
26465 // B = < float b0, float b1, float b2, float b3 >
26467 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26468 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26469 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26470 // which is A horizontal-op B.
26472 // At least one of the operands should be a vector shuffle.
26473 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26474 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26477 MVT VT = LHS.getSimpleValueType();
26479 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26480 "Unsupported vector type for horizontal add/sub");
26482 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26483 // operate independently on 128-bit lanes.
26484 unsigned NumElts = VT.getVectorNumElements();
26485 unsigned NumLanes = VT.getSizeInBits()/128;
26486 unsigned NumLaneElts = NumElts / NumLanes;
26487 assert((NumLaneElts % 2 == 0) &&
26488 "Vector type should have an even number of elements in each lane");
26489 unsigned HalfLaneElts = NumLaneElts/2;
26491 // View LHS in the form
26492 // LHS = VECTOR_SHUFFLE A, B, LMask
26493 // If LHS is not a shuffle then pretend it is the shuffle
26494 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26495 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26498 SmallVector<int, 16> LMask(NumElts);
26499 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26500 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26501 A = LHS.getOperand(0);
26502 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26503 B = LHS.getOperand(1);
26504 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26505 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26507 if (LHS.getOpcode() != ISD::UNDEF)
26509 for (unsigned i = 0; i != NumElts; ++i)
26513 // Likewise, view RHS in the form
26514 // RHS = VECTOR_SHUFFLE C, D, RMask
26516 SmallVector<int, 16> RMask(NumElts);
26517 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26518 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26519 C = RHS.getOperand(0);
26520 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26521 D = RHS.getOperand(1);
26522 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26523 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26525 if (RHS.getOpcode() != ISD::UNDEF)
26527 for (unsigned i = 0; i != NumElts; ++i)
26531 // Check that the shuffles are both shuffling the same vectors.
26532 if (!(A == C && B == D) && !(A == D && B == C))
26535 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26536 if (!A.getNode() && !B.getNode())
26539 // If A and B occur in reverse order in RHS, then "swap" them (which means
26540 // rewriting the mask).
26542 ShuffleVectorSDNode::commuteMask(RMask);
26544 // At this point LHS and RHS are equivalent to
26545 // LHS = VECTOR_SHUFFLE A, B, LMask
26546 // RHS = VECTOR_SHUFFLE A, B, RMask
26547 // Check that the masks correspond to performing a horizontal operation.
26548 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26549 for (unsigned i = 0; i != NumLaneElts; ++i) {
26550 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26552 // Ignore any UNDEF components.
26553 if (LIdx < 0 || RIdx < 0 ||
26554 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26555 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26558 // Check that successive elements are being operated on. If not, this is
26559 // not a horizontal operation.
26560 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26561 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26562 if (!(LIdx == Index && RIdx == Index + 1) &&
26563 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26568 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26569 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26573 /// Do target-specific dag combines on floating point adds.
26574 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26575 const X86Subtarget *Subtarget) {
26576 EVT VT = N->getValueType(0);
26577 SDValue LHS = N->getOperand(0);
26578 SDValue RHS = N->getOperand(1);
26580 // Try to synthesize horizontal adds from adds of shuffles.
26581 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26582 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26583 isHorizontalBinOp(LHS, RHS, true))
26584 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26588 /// Do target-specific dag combines on floating point subs.
26589 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26590 const X86Subtarget *Subtarget) {
26591 EVT VT = N->getValueType(0);
26592 SDValue LHS = N->getOperand(0);
26593 SDValue RHS = N->getOperand(1);
26595 // Try to synthesize horizontal subs from subs of shuffles.
26596 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26597 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26598 isHorizontalBinOp(LHS, RHS, false))
26599 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26603 /// Truncate a group of v4i32 into v16i8/v8i16 using X86ISD::PACKUS.
26605 combineVectorTruncationWithPACKUS(SDNode *N, SelectionDAG &DAG,
26606 SmallVector<SDValue, 8> &Regs) {
26607 assert(Regs.size() > 0 && (Regs[0].getValueType() == MVT::v4i32 ||
26608 Regs[0].getValueType() == MVT::v2i64));
26609 EVT OutVT = N->getValueType(0);
26610 EVT OutSVT = OutVT.getVectorElementType();
26611 EVT InVT = Regs[0].getValueType();
26612 EVT InSVT = InVT.getVectorElementType();
26615 // First, use mask to unset all bits that won't appear in the result.
26616 assert((OutSVT == MVT::i8 || OutSVT == MVT::i16) &&
26617 "OutSVT can only be either i8 or i16.");
26619 DAG.getConstant(OutSVT == MVT::i8 ? 0xFF : 0xFFFF, DL, InSVT);
26620 SDValue MaskVec = DAG.getNode(
26621 ISD::BUILD_VECTOR, DL, InVT,
26622 SmallVector<SDValue, 8>(InVT.getVectorNumElements(), MaskVal));
26623 for (auto &Reg : Regs)
26624 Reg = DAG.getNode(ISD::AND, DL, InVT, MaskVec, Reg);
26626 MVT UnpackedVT, PackedVT;
26627 if (OutSVT == MVT::i8) {
26628 UnpackedVT = MVT::v8i16;
26629 PackedVT = MVT::v16i8;
26631 UnpackedVT = MVT::v4i32;
26632 PackedVT = MVT::v8i16;
26635 // In each iteration, truncate the type by a half size.
26636 auto RegNum = Regs.size();
26637 for (unsigned j = 1, e = InSVT.getSizeInBits() / OutSVT.getSizeInBits();
26638 j < e; j *= 2, RegNum /= 2) {
26639 for (unsigned i = 0; i < RegNum; i++)
26640 Regs[i] = DAG.getNode(ISD::BITCAST, DL, UnpackedVT, Regs[i]);
26641 for (unsigned i = 0; i < RegNum / 2; i++)
26642 Regs[i] = DAG.getNode(X86ISD::PACKUS, DL, PackedVT, Regs[i * 2],
26646 // If the type of the result is v8i8, we need do one more X86ISD::PACKUS, and
26647 // then extract a subvector as the result since v8i8 is not a legal type.
26648 if (OutVT == MVT::v8i8) {
26649 Regs[0] = DAG.getNode(X86ISD::PACKUS, DL, PackedVT, Regs[0], Regs[0]);
26650 Regs[0] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, Regs[0],
26651 DAG.getIntPtrConstant(0, DL));
26653 } else if (RegNum > 1) {
26654 Regs.resize(RegNum);
26655 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Regs);
26660 /// Truncate a group of v4i32 into v8i16 using X86ISD::PACKSS.
26662 combineVectorTruncationWithPACKSS(SDNode *N, SelectionDAG &DAG,
26663 SmallVector<SDValue, 8> &Regs) {
26664 assert(Regs.size() > 0 && Regs[0].getValueType() == MVT::v4i32);
26665 EVT OutVT = N->getValueType(0);
26668 // Shift left by 16 bits, then arithmetic-shift right by 16 bits.
26669 SDValue ShAmt = DAG.getConstant(16, DL, MVT::i32);
26670 for (auto &Reg : Regs) {
26671 Reg = getTargetVShiftNode(X86ISD::VSHLI, DL, MVT::v4i32, Reg, ShAmt, DAG);
26672 Reg = getTargetVShiftNode(X86ISD::VSRAI, DL, MVT::v4i32, Reg, ShAmt, DAG);
26675 for (unsigned i = 0, e = Regs.size() / 2; i < e; i++)
26676 Regs[i] = DAG.getNode(X86ISD::PACKSS, DL, MVT::v8i16, Regs[i * 2],
26679 if (Regs.size() > 2) {
26680 Regs.resize(Regs.size() / 2);
26681 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Regs);
26686 /// This function transforms truncation from vXi32/vXi64 to vXi8/vXi16 into
26687 /// X86ISD::PACKUS/X86ISD::PACKSS operations. We do it here because after type
26688 /// legalization the truncation will be translated into a BUILD_VECTOR with each
26689 /// element that is extracted from a vector and then truncated, and it is
26690 /// diffcult to do this optimization based on them.
26691 static SDValue combineVectorTruncation(SDNode *N, SelectionDAG &DAG,
26692 const X86Subtarget *Subtarget) {
26693 EVT OutVT = N->getValueType(0);
26694 if (!OutVT.isVector())
26697 SDValue In = N->getOperand(0);
26698 if (!In.getValueType().isSimple())
26701 EVT InVT = In.getValueType();
26702 unsigned NumElems = OutVT.getVectorNumElements();
26704 // TODO: On AVX2, the behavior of X86ISD::PACKUS is different from that on
26705 // SSE2, and we need to take care of it specially.
26706 // AVX512 provides vpmovdb.
26707 if (!Subtarget->hasSSE2() || Subtarget->hasAVX2())
26710 EVT OutSVT = OutVT.getVectorElementType();
26711 EVT InSVT = InVT.getVectorElementType();
26712 if (!((InSVT == MVT::i32 || InSVT == MVT::i64) &&
26713 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && isPowerOf2_32(NumElems) &&
26717 // SSSE3's pshufb results in less instructions in the cases below.
26718 if (Subtarget->hasSSSE3() && NumElems == 8 &&
26719 ((OutSVT == MVT::i8 && InSVT != MVT::i64) ||
26720 (InSVT == MVT::i32 && OutSVT == MVT::i16)))
26725 // Split a long vector into vectors of legal type.
26726 unsigned RegNum = InVT.getSizeInBits() / 128;
26727 SmallVector<SDValue, 8> SubVec(RegNum);
26728 if (InSVT == MVT::i32) {
26729 for (unsigned i = 0; i < RegNum; i++)
26730 SubVec[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
26731 DAG.getIntPtrConstant(i * 4, DL));
26733 for (unsigned i = 0; i < RegNum; i++)
26734 SubVec[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
26735 DAG.getIntPtrConstant(i * 2, DL));
26738 // SSE2 provides PACKUS for only 2 x v8i16 -> v16i8 and SSE4.1 provides PAKCUS
26739 // for 2 x v4i32 -> v8i16. For SSSE3 and below, we need to use PACKSS to
26740 // truncate 2 x v4i32 to v8i16.
26741 if (Subtarget->hasSSE41() || OutSVT == MVT::i8)
26742 return combineVectorTruncationWithPACKUS(N, DAG, SubVec);
26743 else if (InSVT == MVT::i32)
26744 return combineVectorTruncationWithPACKSS(N, DAG, SubVec);
26749 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
26750 const X86Subtarget *Subtarget) {
26751 // Try to detect AVG pattern first.
26752 SDValue Avg = detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG,
26753 Subtarget, SDLoc(N));
26757 return combineVectorTruncation(N, DAG, Subtarget);
26760 /// Do target-specific dag combines on floating point negations.
26761 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26762 const X86Subtarget *Subtarget) {
26763 EVT VT = N->getValueType(0);
26764 EVT SVT = VT.getScalarType();
26765 SDValue Arg = N->getOperand(0);
26768 // Let legalize expand this if it isn't a legal type yet.
26769 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26772 // If we're negating a FMUL node on a target with FMA, then we can avoid the
26773 // use of a constant by performing (-0 - A*B) instead.
26774 // FIXME: Check rounding control flags as well once it becomes available.
26775 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26776 Arg->getFlags()->hasNoSignedZeros() && Subtarget->hasAnyFMA()) {
26777 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
26778 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26779 Arg.getOperand(1), Zero);
26782 // If we're negating a FMA node, then we can adjust the
26783 // instruction to include the extra negation.
26784 if (Arg.hasOneUse()) {
26785 switch (Arg.getOpcode()) {
26786 case X86ISD::FMADD:
26787 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26788 Arg.getOperand(1), Arg.getOperand(2));
26789 case X86ISD::FMSUB:
26790 return DAG.getNode(X86ISD::FNMADD, DL, VT, Arg.getOperand(0),
26791 Arg.getOperand(1), Arg.getOperand(2));
26792 case X86ISD::FNMADD:
26793 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0),
26794 Arg.getOperand(1), Arg.getOperand(2));
26795 case X86ISD::FNMSUB:
26796 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
26797 Arg.getOperand(1), Arg.getOperand(2));
26803 static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
26804 const X86Subtarget *Subtarget) {
26805 EVT VT = N->getValueType(0);
26806 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26807 // VXORPS, VORPS, VANDPS, VANDNPS are supported only under DQ extention.
26808 // These logic operations may be executed in the integer domain.
26810 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26811 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26813 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26814 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26815 unsigned IntOpcode = 0;
26816 switch (N->getOpcode()) {
26817 default: llvm_unreachable("Unexpected FP logic op");
26818 case X86ISD::FOR: IntOpcode = ISD::OR; break;
26819 case X86ISD::FXOR: IntOpcode = ISD::XOR; break;
26820 case X86ISD::FAND: IntOpcode = ISD::AND; break;
26821 case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
26823 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26824 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26828 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26829 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26830 const X86Subtarget *Subtarget) {
26831 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26833 // F[X]OR(0.0, x) -> x
26834 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26835 if (C->getValueAPF().isPosZero())
26836 return N->getOperand(1);
26838 // F[X]OR(x, 0.0) -> x
26839 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26840 if (C->getValueAPF().isPosZero())
26841 return N->getOperand(0);
26843 return lowerX86FPLogicOp(N, DAG, Subtarget);
26846 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26847 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26848 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26850 // Only perform optimizations if UnsafeMath is used.
26851 if (!DAG.getTarget().Options.UnsafeFPMath)
26854 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26855 // into FMINC and FMAXC, which are Commutative operations.
26856 unsigned NewOp = 0;
26857 switch (N->getOpcode()) {
26858 default: llvm_unreachable("unknown opcode");
26859 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26860 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26863 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26864 N->getOperand(0), N->getOperand(1));
26867 static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
26868 const X86Subtarget *Subtarget) {
26869 if (Subtarget->useSoftFloat())
26872 // TODO: Check for global or instruction-level "nnan". In that case, we
26873 // should be able to lower to FMAX/FMIN alone.
26874 // TODO: If an operand is already known to be a NaN or not a NaN, this
26875 // should be an optional swap and FMAX/FMIN.
26876 // TODO: Allow f64, vectors, and fminnum.
26878 EVT VT = N->getValueType(0);
26879 if (!(Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)))
26882 // This takes at least 3 instructions, so favor a library call when operating
26883 // on a scalar and minimizing code size.
26884 if (!VT.isVector() && DAG.getMachineFunction().getFunction()->optForMinSize())
26887 SDValue Op0 = N->getOperand(0);
26888 SDValue Op1 = N->getOperand(1);
26890 EVT SetCCType = DAG.getTargetLoweringInfo().getSetCCResultType(
26891 DAG.getDataLayout(), *DAG.getContext(), VT);
26893 // There are 4 possibilities involving NaN inputs, and these are the required
26897 // ----------------
26898 // Num | Max | Op0 |
26899 // Op0 ----------------
26900 // NaN | Op1 | NaN |
26901 // ----------------
26903 // The SSE FP max/min instructions were not designed for this case, but rather
26905 // Max = Op1 > Op0 ? Op1 : Op0
26907 // So they always return Op0 if either input is a NaN. However, we can still
26908 // use those instructions for fmaxnum by selecting away a NaN input.
26910 // If either operand is NaN, the 2nd source operand (Op0) is passed through.
26911 SDValue Max = DAG.getNode(X86ISD::FMAX, DL, VT, Op1, Op0);
26912 SDValue IsOp0Nan = DAG.getSetCC(DL, SetCCType , Op0, Op0, ISD::SETUO);
26914 // If Op0 is a NaN, select Op1. Otherwise, select the max. If both operands
26915 // are NaN, the NaN value of Op1 is the result.
26916 auto SelectOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT;
26917 return DAG.getNode(SelectOpcode, DL, VT, IsOp0Nan, Op1, Max);
26920 /// Do target-specific dag combines on X86ISD::FAND nodes.
26921 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
26922 const X86Subtarget *Subtarget) {
26923 // FAND(0.0, x) -> 0.0
26924 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26925 if (C->getValueAPF().isPosZero())
26926 return N->getOperand(0);
26928 // FAND(x, 0.0) -> 0.0
26929 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26930 if (C->getValueAPF().isPosZero())
26931 return N->getOperand(1);
26933 return lowerX86FPLogicOp(N, DAG, Subtarget);
26936 /// Do target-specific dag combines on X86ISD::FANDN nodes
26937 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
26938 const X86Subtarget *Subtarget) {
26939 // FANDN(0.0, x) -> x
26940 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26941 if (C->getValueAPF().isPosZero())
26942 return N->getOperand(1);
26944 // FANDN(x, 0.0) -> 0.0
26945 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26946 if (C->getValueAPF().isPosZero())
26947 return N->getOperand(1);
26949 return lowerX86FPLogicOp(N, DAG, Subtarget);
26952 static SDValue PerformBTCombine(SDNode *N,
26954 TargetLowering::DAGCombinerInfo &DCI) {
26955 // BT ignores high bits in the bit index operand.
26956 SDValue Op1 = N->getOperand(1);
26957 if (Op1.hasOneUse()) {
26958 unsigned BitWidth = Op1.getValueSizeInBits();
26959 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26960 APInt KnownZero, KnownOne;
26961 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26962 !DCI.isBeforeLegalizeOps());
26963 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26964 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26965 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26966 DCI.CommitTargetLoweringOpt(TLO);
26971 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26972 SDValue Op = N->getOperand(0);
26973 if (Op.getOpcode() == ISD::BITCAST)
26974 Op = Op.getOperand(0);
26975 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26976 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26977 VT.getVectorElementType().getSizeInBits() ==
26978 OpVT.getVectorElementType().getSizeInBits()) {
26979 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26984 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26985 const X86Subtarget *Subtarget) {
26986 EVT VT = N->getValueType(0);
26987 if (!VT.isVector())
26990 SDValue N0 = N->getOperand(0);
26991 SDValue N1 = N->getOperand(1);
26992 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26995 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26996 // both SSE and AVX2 since there is no sign-extended shift right
26997 // operation on a vector with 64-bit elements.
26998 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26999 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
27000 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
27001 N0.getOpcode() == ISD::SIGN_EXTEND)) {
27002 SDValue N00 = N0.getOperand(0);
27004 // EXTLOAD has a better solution on AVX2,
27005 // it may be replaced with X86ISD::VSEXT node.
27006 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
27007 if (!ISD::isNormalLoad(N00.getNode()))
27010 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
27011 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
27013 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
27019 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
27020 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
27021 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
27022 /// eliminate extend, add, and shift instructions.
27023 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
27024 const X86Subtarget *Subtarget) {
27025 // TODO: This should be valid for other integer types.
27026 EVT VT = Sext->getValueType(0);
27027 if (VT != MVT::i64)
27030 // We need an 'add nsw' feeding into the 'sext'.
27031 SDValue Add = Sext->getOperand(0);
27032 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
27035 // Having a constant operand to the 'add' ensures that we are not increasing
27036 // the instruction count because the constant is extended for free below.
27037 // A constant operand can also become the displacement field of an LEA.
27038 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
27042 // Don't make the 'add' bigger if there's no hope of combining it with some
27043 // other 'add' or 'shl' instruction.
27044 // TODO: It may be profitable to generate simpler LEA instructions in place
27045 // of single 'add' instructions, but the cost model for selecting an LEA
27046 // currently has a high threshold.
27047 bool HasLEAPotential = false;
27048 for (auto *User : Sext->uses()) {
27049 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
27050 HasLEAPotential = true;
27054 if (!HasLEAPotential)
27057 // Everything looks good, so pull the 'sext' ahead of the 'add'.
27058 int64_t AddConstant = AddOp1->getSExtValue();
27059 SDValue AddOp0 = Add.getOperand(0);
27060 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
27061 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
27063 // The wider add is guaranteed to not wrap because both operands are
27066 Flags.setNoSignedWrap(true);
27067 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
27070 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
27071 TargetLowering::DAGCombinerInfo &DCI,
27072 const X86Subtarget *Subtarget) {
27073 SDValue N0 = N->getOperand(0);
27074 EVT VT = N->getValueType(0);
27075 EVT SVT = VT.getScalarType();
27076 EVT InVT = N0.getValueType();
27077 EVT InSVT = InVT.getScalarType();
27080 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
27081 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
27082 // This exposes the sext to the sdivrem lowering, so that it directly extends
27083 // from AH (which we otherwise need to do contortions to access).
27084 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
27085 InVT == MVT::i8 && VT == MVT::i32) {
27086 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
27087 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
27088 N0.getOperand(0), N0.getOperand(1));
27089 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
27090 return R.getValue(1);
27093 if (!DCI.isBeforeLegalizeOps()) {
27094 if (InVT == MVT::i1) {
27095 SDValue Zero = DAG.getConstant(0, DL, VT);
27097 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
27098 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
27103 if (VT.isVector() && Subtarget->hasSSE2()) {
27104 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
27105 EVT InVT = N.getValueType();
27106 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
27107 Size / InVT.getScalarSizeInBits());
27108 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
27109 DAG.getUNDEF(InVT));
27111 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
27114 // If target-size is less than 128-bits, extend to a type that would extend
27115 // to 128 bits, extend that and extract the original target vector.
27116 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
27117 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27118 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27119 unsigned Scale = 128 / VT.getSizeInBits();
27121 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
27122 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
27123 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
27124 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
27125 DAG.getIntPtrConstant(0, DL));
27128 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
27129 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
27130 if (VT.getSizeInBits() == 128 &&
27131 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27132 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27133 SDValue ExOp = ExtendVecSize(DL, N0, 128);
27134 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
27137 // On pre-AVX2 targets, split into 128-bit nodes of
27138 // ISD::SIGN_EXTEND_VECTOR_INREG.
27139 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
27140 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27141 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27142 unsigned NumVecs = VT.getSizeInBits() / 128;
27143 unsigned NumSubElts = 128 / SVT.getSizeInBits();
27144 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
27145 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
27147 SmallVector<SDValue, 8> Opnds;
27148 for (unsigned i = 0, Offset = 0; i != NumVecs;
27149 ++i, Offset += NumSubElts) {
27150 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
27151 DAG.getIntPtrConstant(Offset, DL));
27152 SrcVec = ExtendVecSize(DL, SrcVec, 128);
27153 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
27154 Opnds.push_back(SrcVec);
27156 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
27160 if (Subtarget->hasAVX() && VT.is256BitVector())
27161 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
27164 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
27170 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
27171 const X86Subtarget* Subtarget) {
27173 EVT VT = N->getValueType(0);
27175 // Let legalize expand this if it isn't a legal type yet.
27176 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
27179 EVT ScalarVT = VT.getScalarType();
27180 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasAnyFMA())
27183 SDValue A = N->getOperand(0);
27184 SDValue B = N->getOperand(1);
27185 SDValue C = N->getOperand(2);
27187 bool NegA = (A.getOpcode() == ISD::FNEG);
27188 bool NegB = (B.getOpcode() == ISD::FNEG);
27189 bool NegC = (C.getOpcode() == ISD::FNEG);
27191 // Negative multiplication when NegA xor NegB
27192 bool NegMul = (NegA != NegB);
27194 A = A.getOperand(0);
27196 B = B.getOperand(0);
27198 C = C.getOperand(0);
27202 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
27204 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
27206 return DAG.getNode(Opcode, dl, VT, A, B, C);
27209 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
27210 TargetLowering::DAGCombinerInfo &DCI,
27211 const X86Subtarget *Subtarget) {
27212 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
27213 // (and (i32 x86isd::setcc_carry), 1)
27214 // This eliminates the zext. This transformation is necessary because
27215 // ISD::SETCC is always legalized to i8.
27217 SDValue N0 = N->getOperand(0);
27218 EVT VT = N->getValueType(0);
27220 if (N0.getOpcode() == ISD::AND &&
27222 N0.getOperand(0).hasOneUse()) {
27223 SDValue N00 = N0.getOperand(0);
27224 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27225 if (!isOneConstant(N0.getOperand(1)))
27227 return DAG.getNode(ISD::AND, dl, VT,
27228 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
27229 N00.getOperand(0), N00.getOperand(1)),
27230 DAG.getConstant(1, dl, VT));
27234 if (N0.getOpcode() == ISD::TRUNCATE &&
27236 N0.getOperand(0).hasOneUse()) {
27237 SDValue N00 = N0.getOperand(0);
27238 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27239 return DAG.getNode(ISD::AND, dl, VT,
27240 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
27241 N00.getOperand(0), N00.getOperand(1)),
27242 DAG.getConstant(1, dl, VT));
27246 if (VT.is256BitVector())
27247 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
27250 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
27251 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
27252 // This exposes the zext to the udivrem lowering, so that it directly extends
27253 // from AH (which we otherwise need to do contortions to access).
27254 if (N0.getOpcode() == ISD::UDIVREM &&
27255 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
27256 (VT == MVT::i32 || VT == MVT::i64)) {
27257 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
27258 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
27259 N0.getOperand(0), N0.getOperand(1));
27260 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
27261 return R.getValue(1);
27267 // Optimize x == -y --> x+y == 0
27268 // x != -y --> x+y != 0
27269 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
27270 const X86Subtarget* Subtarget) {
27271 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
27272 SDValue LHS = N->getOperand(0);
27273 SDValue RHS = N->getOperand(1);
27274 EVT VT = N->getValueType(0);
27277 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
27278 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
27279 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
27280 LHS.getOperand(1));
27281 return DAG.getSetCC(DL, N->getValueType(0), addV,
27282 DAG.getConstant(0, DL, addV.getValueType()), CC);
27284 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
27285 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
27286 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
27287 RHS.getOperand(1));
27288 return DAG.getSetCC(DL, N->getValueType(0), addV,
27289 DAG.getConstant(0, DL, addV.getValueType()), CC);
27292 if (VT.getScalarType() == MVT::i1 &&
27293 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
27295 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27296 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
27297 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
27299 if (!IsSEXT0 || !IsVZero1) {
27300 // Swap the operands and update the condition code.
27301 std::swap(LHS, RHS);
27302 CC = ISD::getSetCCSwappedOperands(CC);
27304 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27305 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
27306 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
27309 if (IsSEXT0 && IsVZero1) {
27310 assert(VT == LHS.getOperand(0).getValueType() &&
27311 "Uexpected operand type");
27312 if (CC == ISD::SETGT)
27313 return DAG.getConstant(0, DL, VT);
27314 if (CC == ISD::SETLE)
27315 return DAG.getConstant(1, DL, VT);
27316 if (CC == ISD::SETEQ || CC == ISD::SETGE)
27317 return DAG.getNOT(DL, LHS.getOperand(0), VT);
27319 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
27320 "Unexpected condition code!");
27321 return LHS.getOperand(0);
27328 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
27329 SDValue V0 = N->getOperand(0);
27330 SDValue V1 = N->getOperand(1);
27332 EVT VT = N->getValueType(0);
27334 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
27335 // operands and changing the mask to 1. This saves us a bunch of
27336 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
27337 // x86InstrInfo knows how to commute this back after instruction selection
27338 // if it would help register allocation.
27340 // TODO: If optimizing for size or a processor that doesn't suffer from
27341 // partial register update stalls, this should be transformed into a MOVSD
27342 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
27344 if (VT == MVT::v2f64)
27345 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
27346 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
27347 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
27348 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
27354 static SDValue PerformGatherScatterCombine(SDNode *N, SelectionDAG &DAG) {
27356 // Gather and Scatter instructions use k-registers for masks. The type of
27357 // the masks is v*i1. So the mask will be truncated anyway.
27358 // The SIGN_EXTEND_INREG my be dropped.
27359 SDValue Mask = N->getOperand(2);
27360 if (Mask.getOpcode() == ISD::SIGN_EXTEND_INREG) {
27361 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
27362 NewOps[2] = Mask.getOperand(0);
27363 DAG.UpdateNodeOperands(N, NewOps);
27368 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
27369 // as "sbb reg,reg", since it can be extended without zext and produces
27370 // an all-ones bit which is more useful than 0/1 in some cases.
27371 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
27374 return DAG.getNode(ISD::AND, DL, VT,
27375 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
27376 DAG.getConstant(X86::COND_B, DL, MVT::i8),
27378 DAG.getConstant(1, DL, VT));
27379 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
27380 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
27381 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
27382 DAG.getConstant(X86::COND_B, DL, MVT::i8),
27386 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
27387 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
27388 TargetLowering::DAGCombinerInfo &DCI,
27389 const X86Subtarget *Subtarget) {
27391 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
27392 SDValue EFLAGS = N->getOperand(1);
27394 if (CC == X86::COND_A) {
27395 // Try to convert COND_A into COND_B in an attempt to facilitate
27396 // materializing "setb reg".
27398 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
27399 // cannot take an immediate as its first operand.
27401 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
27402 EFLAGS.getValueType().isInteger() &&
27403 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
27404 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
27405 EFLAGS.getNode()->getVTList(),
27406 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
27407 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
27408 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
27412 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
27413 // a zext and produces an all-ones bit which is more useful than 0/1 in some
27415 if (CC == X86::COND_B)
27416 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
27418 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
27419 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
27420 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
27426 // Optimize branch condition evaluation.
27428 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
27429 TargetLowering::DAGCombinerInfo &DCI,
27430 const X86Subtarget *Subtarget) {
27432 SDValue Chain = N->getOperand(0);
27433 SDValue Dest = N->getOperand(1);
27434 SDValue EFLAGS = N->getOperand(3);
27435 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
27437 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
27438 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
27439 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
27446 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
27447 SelectionDAG &DAG) {
27448 // Take advantage of vector comparisons producing 0 or -1 in each lane to
27449 // optimize away operation when it's from a constant.
27451 // The general transformation is:
27452 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
27453 // AND(VECTOR_CMP(x,y), constant2)
27454 // constant2 = UNARYOP(constant)
27456 // Early exit if this isn't a vector operation, the operand of the
27457 // unary operation isn't a bitwise AND, or if the sizes of the operations
27458 // aren't the same.
27459 EVT VT = N->getValueType(0);
27460 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
27461 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
27462 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
27465 // Now check that the other operand of the AND is a constant. We could
27466 // make the transformation for non-constant splats as well, but it's unclear
27467 // that would be a benefit as it would not eliminate any operations, just
27468 // perform one more step in scalar code before moving to the vector unit.
27469 if (BuildVectorSDNode *BV =
27470 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
27471 // Bail out if the vector isn't a constant.
27472 if (!BV->isConstant())
27475 // Everything checks out. Build up the new and improved node.
27477 EVT IntVT = BV->getValueType(0);
27478 // Create a new constant of the appropriate type for the transformed
27480 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
27481 // The AND node needs bitcasts to/from an integer vector type around it.
27482 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
27483 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
27484 N->getOperand(0)->getOperand(0), MaskConst);
27485 SDValue Res = DAG.getBitcast(VT, NewAnd);
27492 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27493 const X86Subtarget *Subtarget) {
27494 SDValue Op0 = N->getOperand(0);
27495 EVT VT = N->getValueType(0);
27496 EVT InVT = Op0.getValueType();
27497 EVT InSVT = InVT.getScalarType();
27498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
27500 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
27501 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
27502 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27504 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27505 InVT.getVectorNumElements());
27506 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
27508 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
27509 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
27511 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27517 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27518 const X86Subtarget *Subtarget) {
27519 // First try to optimize away the conversion entirely when it's
27520 // conditionally from a constant. Vectors only.
27521 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
27524 // Now move on to more general possibilities.
27525 SDValue Op0 = N->getOperand(0);
27526 EVT VT = N->getValueType(0);
27527 EVT InVT = Op0.getValueType();
27528 EVT InSVT = InVT.getScalarType();
27530 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
27531 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
27532 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27534 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27535 InVT.getVectorNumElements());
27536 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
27537 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27540 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
27541 // a 32-bit target where SSE doesn't support i64->FP operations.
27542 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
27543 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
27544 EVT LdVT = Ld->getValueType(0);
27546 // This transformation is not supported if the result type is f16
27547 if (VT == MVT::f16)
27550 if (!Ld->isVolatile() && !VT.isVector() &&
27551 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
27552 !Subtarget->is64Bit() && LdVT == MVT::i64) {
27553 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
27554 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
27555 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
27562 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
27563 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
27564 X86TargetLowering::DAGCombinerInfo &DCI) {
27565 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
27566 // the result is either zero or one (depending on the input carry bit).
27567 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
27568 if (X86::isZeroNode(N->getOperand(0)) &&
27569 X86::isZeroNode(N->getOperand(1)) &&
27570 // We don't have a good way to replace an EFLAGS use, so only do this when
27572 SDValue(N, 1).use_empty()) {
27574 EVT VT = N->getValueType(0);
27575 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
27576 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
27577 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
27578 DAG.getConstant(X86::COND_B, DL,
27581 DAG.getConstant(1, DL, VT));
27582 return DCI.CombineTo(N, Res1, CarryOut);
27588 // fold (add Y, (sete X, 0)) -> adc 0, Y
27589 // (add Y, (setne X, 0)) -> sbb -1, Y
27590 // (sub (sete X, 0), Y) -> sbb 0, Y
27591 // (sub (setne X, 0), Y) -> adc -1, Y
27592 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
27595 // Look through ZExts.
27596 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
27597 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
27600 SDValue SetCC = Ext.getOperand(0);
27601 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27604 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
27605 if (CC != X86::COND_E && CC != X86::COND_NE)
27608 SDValue Cmp = SetCC.getOperand(1);
27609 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
27610 !X86::isZeroNode(Cmp.getOperand(1)) ||
27611 !Cmp.getOperand(0).getValueType().isInteger())
27614 SDValue CmpOp0 = Cmp.getOperand(0);
27615 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
27616 DAG.getConstant(1, DL, CmpOp0.getValueType()));
27618 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
27619 if (CC == X86::COND_NE)
27620 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
27621 DL, OtherVal.getValueType(), OtherVal,
27622 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
27624 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
27625 DL, OtherVal.getValueType(), OtherVal,
27626 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
27629 /// PerformADDCombine - Do target-specific dag combines on integer adds.
27630 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
27631 const X86Subtarget *Subtarget) {
27632 EVT VT = N->getValueType(0);
27633 SDValue Op0 = N->getOperand(0);
27634 SDValue Op1 = N->getOperand(1);
27636 // Try to synthesize horizontal adds from adds of shuffles.
27637 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27638 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27639 isHorizontalBinOp(Op0, Op1, true))
27640 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
27642 return OptimizeConditionalInDecrement(N, DAG);
27645 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
27646 const X86Subtarget *Subtarget) {
27647 SDValue Op0 = N->getOperand(0);
27648 SDValue Op1 = N->getOperand(1);
27650 // X86 can't encode an immediate LHS of a sub. See if we can push the
27651 // negation into a preceding instruction.
27652 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
27653 // If the RHS of the sub is a XOR with one use and a constant, invert the
27654 // immediate. Then add one to the LHS of the sub so we can turn
27655 // X-Y -> X+~Y+1, saving one register.
27656 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
27657 isa<ConstantSDNode>(Op1.getOperand(1))) {
27658 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
27659 EVT VT = Op0.getValueType();
27660 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
27662 DAG.getConstant(~XorC, SDLoc(Op1), VT));
27663 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
27664 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
27668 // Try to synthesize horizontal adds from adds of shuffles.
27669 EVT VT = N->getValueType(0);
27670 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27671 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27672 isHorizontalBinOp(Op0, Op1, true))
27673 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
27675 return OptimizeConditionalInDecrement(N, DAG);
27678 /// performVZEXTCombine - Performs build vector combines
27679 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27680 TargetLowering::DAGCombinerInfo &DCI,
27681 const X86Subtarget *Subtarget) {
27683 MVT VT = N->getSimpleValueType(0);
27684 SDValue Op = N->getOperand(0);
27685 MVT OpVT = Op.getSimpleValueType();
27686 MVT OpEltVT = OpVT.getVectorElementType();
27687 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
27689 // (vzext (bitcast (vzext (x)) -> (vzext x)
27691 while (V.getOpcode() == ISD::BITCAST)
27692 V = V.getOperand(0);
27694 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27695 MVT InnerVT = V.getSimpleValueType();
27696 MVT InnerEltVT = InnerVT.getVectorElementType();
27698 // If the element sizes match exactly, we can just do one larger vzext. This
27699 // is always an exact type match as vzext operates on integer types.
27700 if (OpEltVT == InnerEltVT) {
27701 assert(OpVT == InnerVT && "Types must match for vzext!");
27702 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27705 // The only other way we can combine them is if only a single element of the
27706 // inner vzext is used in the input to the outer vzext.
27707 if (InnerEltVT.getSizeInBits() < InputBits)
27710 // In this case, the inner vzext is completely dead because we're going to
27711 // only look at bits inside of the low element. Just do the outer vzext on
27712 // a bitcast of the input to the inner.
27713 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27716 // Check if we can bypass extracting and re-inserting an element of an input
27717 // vector. Essentially:
27718 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27719 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27720 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27721 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27722 SDValue ExtractedV = V.getOperand(0);
27723 SDValue OrigV = ExtractedV.getOperand(0);
27724 if (isNullConstant(ExtractedV.getOperand(1))) {
27725 MVT OrigVT = OrigV.getSimpleValueType();
27726 // Extract a subvector if necessary...
27727 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27728 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27729 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27730 OrigVT.getVectorNumElements() / Ratio);
27731 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27732 DAG.getIntPtrConstant(0, DL));
27734 Op = DAG.getBitcast(OpVT, OrigV);
27735 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27742 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27743 DAGCombinerInfo &DCI) const {
27744 SelectionDAG &DAG = DCI.DAG;
27745 switch (N->getOpcode()) {
27747 case ISD::EXTRACT_VECTOR_ELT:
27748 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27751 case X86ISD::SHRUNKBLEND:
27752 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27753 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27754 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27755 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27756 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27757 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27758 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27761 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27762 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27763 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27764 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27765 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27766 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27767 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27768 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27769 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27770 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27771 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27772 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27773 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27774 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27776 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27778 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27779 case ISD::FMAXNUM: return performFMaxNumCombine(N, DAG, Subtarget);
27780 case X86ISD::FAND: return PerformFANDCombine(N, DAG, Subtarget);
27781 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG, Subtarget);
27782 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27783 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27784 case ISD::ANY_EXTEND:
27785 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27786 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27787 case ISD::SIGN_EXTEND_INREG:
27788 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27789 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27790 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27791 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27792 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27793 case X86ISD::SHUFP: // Handle all target specific shuffles
27794 case X86ISD::PALIGNR:
27795 case X86ISD::UNPCKH:
27796 case X86ISD::UNPCKL:
27797 case X86ISD::MOVHLPS:
27798 case X86ISD::MOVLHPS:
27799 case X86ISD::PSHUFB:
27800 case X86ISD::PSHUFD:
27801 case X86ISD::PSHUFHW:
27802 case X86ISD::PSHUFLW:
27803 case X86ISD::MOVSS:
27804 case X86ISD::MOVSD:
27805 case X86ISD::VPERMILPI:
27806 case X86ISD::VPERM2X128:
27807 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27808 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27809 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27811 case ISD::MSCATTER: return PerformGatherScatterCombine(N, DAG);
27817 /// isTypeDesirableForOp - Return true if the target has native support for
27818 /// the specified value type and it is 'desirable' to use the type for the
27819 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27820 /// instruction encodings are longer and some i16 instructions are slow.
27821 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27822 if (!isTypeLegal(VT))
27824 if (VT != MVT::i16)
27831 case ISD::SIGN_EXTEND:
27832 case ISD::ZERO_EXTEND:
27833 case ISD::ANY_EXTEND:
27846 /// IsDesirableToPromoteOp - This method query the target whether it is
27847 /// beneficial for dag combiner to promote the specified node. If true, it
27848 /// should return the desired promotion type by reference.
27849 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27850 EVT VT = Op.getValueType();
27851 if (VT != MVT::i16)
27854 bool Promote = false;
27855 bool Commute = false;
27856 switch (Op.getOpcode()) {
27859 LoadSDNode *LD = cast<LoadSDNode>(Op);
27860 // If the non-extending load has a single use and it's not live out, then it
27861 // might be folded.
27862 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27863 Op.hasOneUse()*/) {
27864 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27865 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27866 // The only case where we'd want to promote LOAD (rather then it being
27867 // promoted as an operand is when it's only use is liveout.
27868 if (UI->getOpcode() != ISD::CopyToReg)
27875 case ISD::SIGN_EXTEND:
27876 case ISD::ZERO_EXTEND:
27877 case ISD::ANY_EXTEND:
27882 SDValue N0 = Op.getOperand(0);
27883 // Look out for (store (shl (load), x)).
27884 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27897 SDValue N0 = Op.getOperand(0);
27898 SDValue N1 = Op.getOperand(1);
27899 if (!Commute && MayFoldLoad(N1))
27901 // Avoid disabling potential load folding opportunities.
27902 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27904 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27914 //===----------------------------------------------------------------------===//
27915 // X86 Inline Assembly Support
27916 //===----------------------------------------------------------------------===//
27918 // Helper to match a string separated by whitespace.
27919 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27920 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27922 for (StringRef Piece : Pieces) {
27923 if (!S.startswith(Piece)) // Check if the piece matches.
27926 S = S.substr(Piece.size());
27927 StringRef::size_type Pos = S.find_first_not_of(" \t");
27928 if (Pos == 0) // We matched a prefix.
27937 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27939 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27940 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27941 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27942 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27944 if (AsmPieces.size() == 3)
27946 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27953 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27954 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27956 std::string AsmStr = IA->getAsmString();
27958 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27959 if (!Ty || Ty->getBitWidth() % 16 != 0)
27962 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27963 SmallVector<StringRef, 4> AsmPieces;
27964 SplitString(AsmStr, AsmPieces, ";\n");
27966 switch (AsmPieces.size()) {
27967 default: return false;
27969 // FIXME: this should verify that we are targeting a 486 or better. If not,
27970 // we will turn this bswap into something that will be lowered to logical
27971 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27972 // lower so don't worry about this.
27974 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27975 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27976 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27977 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27978 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27979 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27980 // No need to check constraints, nothing other than the equivalent of
27981 // "=r,0" would be valid here.
27982 return IntrinsicLowering::LowerToByteSwap(CI);
27985 // rorw $$8, ${0:w} --> llvm.bswap.i16
27986 if (CI->getType()->isIntegerTy(16) &&
27987 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27988 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27989 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27991 StringRef ConstraintsStr = IA->getConstraintString();
27992 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27993 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27994 if (clobbersFlagRegisters(AsmPieces))
27995 return IntrinsicLowering::LowerToByteSwap(CI);
27999 if (CI->getType()->isIntegerTy(32) &&
28000 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
28001 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
28002 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
28003 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
28005 StringRef ConstraintsStr = IA->getConstraintString();
28006 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
28007 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
28008 if (clobbersFlagRegisters(AsmPieces))
28009 return IntrinsicLowering::LowerToByteSwap(CI);
28012 if (CI->getType()->isIntegerTy(64)) {
28013 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
28014 if (Constraints.size() >= 2 &&
28015 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
28016 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
28017 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
28018 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
28019 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
28020 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
28021 return IntrinsicLowering::LowerToByteSwap(CI);
28029 /// getConstraintType - Given a constraint letter, return the type of
28030 /// constraint it is for this target.
28031 X86TargetLowering::ConstraintType
28032 X86TargetLowering::getConstraintType(StringRef Constraint) const {
28033 if (Constraint.size() == 1) {
28034 switch (Constraint[0]) {
28045 return C_RegisterClass;
28069 return TargetLowering::getConstraintType(Constraint);
28072 /// Examine constraint type and operand type and determine a weight value.
28073 /// This object must already have been set up with the operand type
28074 /// and the current alternative constraint selected.
28075 TargetLowering::ConstraintWeight
28076 X86TargetLowering::getSingleConstraintMatchWeight(
28077 AsmOperandInfo &info, const char *constraint) const {
28078 ConstraintWeight weight = CW_Invalid;
28079 Value *CallOperandVal = info.CallOperandVal;
28080 // If we don't have a value, we can't do a match,
28081 // but allow it at the lowest weight.
28082 if (!CallOperandVal)
28084 Type *type = CallOperandVal->getType();
28085 // Look at the constraint type.
28086 switch (*constraint) {
28088 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
28099 if (CallOperandVal->getType()->isIntegerTy())
28100 weight = CW_SpecificReg;
28105 if (type->isFloatingPointTy())
28106 weight = CW_SpecificReg;
28109 if (type->isX86_MMXTy() && Subtarget->hasMMX())
28110 weight = CW_SpecificReg;
28114 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
28115 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
28116 weight = CW_Register;
28119 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
28120 if (C->getZExtValue() <= 31)
28121 weight = CW_Constant;
28125 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28126 if (C->getZExtValue() <= 63)
28127 weight = CW_Constant;
28131 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28132 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
28133 weight = CW_Constant;
28137 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28138 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
28139 weight = CW_Constant;
28143 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28144 if (C->getZExtValue() <= 3)
28145 weight = CW_Constant;
28149 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28150 if (C->getZExtValue() <= 0xff)
28151 weight = CW_Constant;
28156 if (isa<ConstantFP>(CallOperandVal)) {
28157 weight = CW_Constant;
28161 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28162 if ((C->getSExtValue() >= -0x80000000LL) &&
28163 (C->getSExtValue() <= 0x7fffffffLL))
28164 weight = CW_Constant;
28168 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28169 if (C->getZExtValue() <= 0xffffffff)
28170 weight = CW_Constant;
28177 /// LowerXConstraint - try to replace an X constraint, which matches anything,
28178 /// with another that has more specific requirements based on the type of the
28179 /// corresponding operand.
28180 const char *X86TargetLowering::
28181 LowerXConstraint(EVT ConstraintVT) const {
28182 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
28183 // 'f' like normal targets.
28184 if (ConstraintVT.isFloatingPoint()) {
28185 if (Subtarget->hasSSE2())
28187 if (Subtarget->hasSSE1())
28191 return TargetLowering::LowerXConstraint(ConstraintVT);
28194 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
28195 /// vector. If it is invalid, don't add anything to Ops.
28196 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
28197 std::string &Constraint,
28198 std::vector<SDValue>&Ops,
28199 SelectionDAG &DAG) const {
28202 // Only support length 1 constraints for now.
28203 if (Constraint.length() > 1) return;
28205 char ConstraintLetter = Constraint[0];
28206 switch (ConstraintLetter) {
28209 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28210 if (C->getZExtValue() <= 31) {
28211 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28212 Op.getValueType());
28218 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28219 if (C->getZExtValue() <= 63) {
28220 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28221 Op.getValueType());
28227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28228 if (isInt<8>(C->getSExtValue())) {
28229 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28230 Op.getValueType());
28236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28237 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
28238 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
28239 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
28240 Op.getValueType());
28246 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28247 if (C->getZExtValue() <= 3) {
28248 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28249 Op.getValueType());
28255 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28256 if (C->getZExtValue() <= 255) {
28257 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28258 Op.getValueType());
28264 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28265 if (C->getZExtValue() <= 127) {
28266 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28267 Op.getValueType());
28273 // 32-bit signed value
28274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28275 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
28276 C->getSExtValue())) {
28277 // Widen to 64 bits here to get it sign extended.
28278 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
28281 // FIXME gcc accepts some relocatable values here too, but only in certain
28282 // memory models; it's complicated.
28287 // 32-bit unsigned value
28288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28289 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
28290 C->getZExtValue())) {
28291 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28292 Op.getValueType());
28296 // FIXME gcc accepts some relocatable values here too, but only in certain
28297 // memory models; it's complicated.
28301 // Literal immediates are always ok.
28302 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
28303 // Widen to 64 bits here to get it sign extended.
28304 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
28308 // In any sort of PIC mode addresses need to be computed at runtime by
28309 // adding in a register or some sort of table lookup. These can't
28310 // be used as immediates.
28311 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
28314 // If we are in non-pic codegen mode, we allow the address of a global (with
28315 // an optional displacement) to be used with 'i'.
28316 GlobalAddressSDNode *GA = nullptr;
28317 int64_t Offset = 0;
28319 // Match either (GA), (GA+C), (GA+C1+C2), etc.
28321 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
28322 Offset += GA->getOffset();
28324 } else if (Op.getOpcode() == ISD::ADD) {
28325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
28326 Offset += C->getZExtValue();
28327 Op = Op.getOperand(0);
28330 } else if (Op.getOpcode() == ISD::SUB) {
28331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
28332 Offset += -C->getZExtValue();
28333 Op = Op.getOperand(0);
28338 // Otherwise, this isn't something we can handle, reject it.
28342 const GlobalValue *GV = GA->getGlobal();
28343 // If we require an extra load to get this address, as in PIC mode, we
28344 // can't accept it.
28345 if (isGlobalStubReference(
28346 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
28349 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
28350 GA->getValueType(0), Offset);
28355 if (Result.getNode()) {
28356 Ops.push_back(Result);
28359 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
28362 std::pair<unsigned, const TargetRegisterClass *>
28363 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
28364 StringRef Constraint,
28366 // First, see if this is a constraint that directly corresponds to an LLVM
28368 if (Constraint.size() == 1) {
28369 // GCC Constraint Letters
28370 switch (Constraint[0]) {
28372 // TODO: Slight differences here in allocation order and leaving
28373 // RIP in the class. Do they matter any more here than they do
28374 // in the normal allocation?
28375 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
28376 if (Subtarget->is64Bit()) {
28377 if (VT == MVT::i32 || VT == MVT::f32)
28378 return std::make_pair(0U, &X86::GR32RegClass);
28379 if (VT == MVT::i16)
28380 return std::make_pair(0U, &X86::GR16RegClass);
28381 if (VT == MVT::i8 || VT == MVT::i1)
28382 return std::make_pair(0U, &X86::GR8RegClass);
28383 if (VT == MVT::i64 || VT == MVT::f64)
28384 return std::make_pair(0U, &X86::GR64RegClass);
28387 // 32-bit fallthrough
28388 case 'Q': // Q_REGS
28389 if (VT == MVT::i32 || VT == MVT::f32)
28390 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
28391 if (VT == MVT::i16)
28392 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
28393 if (VT == MVT::i8 || VT == MVT::i1)
28394 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
28395 if (VT == MVT::i64)
28396 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
28398 case 'r': // GENERAL_REGS
28399 case 'l': // INDEX_REGS
28400 if (VT == MVT::i8 || VT == MVT::i1)
28401 return std::make_pair(0U, &X86::GR8RegClass);
28402 if (VT == MVT::i16)
28403 return std::make_pair(0U, &X86::GR16RegClass);
28404 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
28405 return std::make_pair(0U, &X86::GR32RegClass);
28406 return std::make_pair(0U, &X86::GR64RegClass);
28407 case 'R': // LEGACY_REGS
28408 if (VT == MVT::i8 || VT == MVT::i1)
28409 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
28410 if (VT == MVT::i16)
28411 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
28412 if (VT == MVT::i32 || !Subtarget->is64Bit())
28413 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
28414 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
28415 case 'f': // FP Stack registers.
28416 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
28417 // value to the correct fpstack register class.
28418 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
28419 return std::make_pair(0U, &X86::RFP32RegClass);
28420 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
28421 return std::make_pair(0U, &X86::RFP64RegClass);
28422 return std::make_pair(0U, &X86::RFP80RegClass);
28423 case 'y': // MMX_REGS if MMX allowed.
28424 if (!Subtarget->hasMMX()) break;
28425 return std::make_pair(0U, &X86::VR64RegClass);
28426 case 'Y': // SSE_REGS if SSE2 allowed
28427 if (!Subtarget->hasSSE2()) break;
28429 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
28430 if (!Subtarget->hasSSE1()) break;
28432 switch (VT.SimpleTy) {
28434 // Scalar SSE types.
28437 return std::make_pair(0U, &X86::FR32RegClass);
28440 return std::make_pair(0U, &X86::FR64RegClass);
28441 // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
28449 return std::make_pair(0U, &X86::VR128RegClass);
28457 return std::make_pair(0U, &X86::VR256RegClass);
28462 return std::make_pair(0U, &X86::VR512RegClass);
28468 // Use the default implementation in TargetLowering to convert the register
28469 // constraint into a member of a register class.
28470 std::pair<unsigned, const TargetRegisterClass*> Res;
28471 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
28473 // Not found as a standard register?
28475 // Map st(0) -> st(7) -> ST0
28476 if (Constraint.size() == 7 && Constraint[0] == '{' &&
28477 tolower(Constraint[1]) == 's' &&
28478 tolower(Constraint[2]) == 't' &&
28479 Constraint[3] == '(' &&
28480 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
28481 Constraint[5] == ')' &&
28482 Constraint[6] == '}') {
28484 Res.first = X86::FP0+Constraint[4]-'0';
28485 Res.second = &X86::RFP80RegClass;
28489 // GCC allows "st(0)" to be called just plain "st".
28490 if (StringRef("{st}").equals_lower(Constraint)) {
28491 Res.first = X86::FP0;
28492 Res.second = &X86::RFP80RegClass;
28497 if (StringRef("{flags}").equals_lower(Constraint)) {
28498 Res.first = X86::EFLAGS;
28499 Res.second = &X86::CCRRegClass;
28503 // 'A' means EAX + EDX.
28504 if (Constraint == "A") {
28505 Res.first = X86::EAX;
28506 Res.second = &X86::GR32_ADRegClass;
28512 // Otherwise, check to see if this is a register class of the wrong value
28513 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
28514 // turn into {ax},{dx}.
28515 // MVT::Other is used to specify clobber names.
28516 if (Res.second->hasType(VT) || VT == MVT::Other)
28517 return Res; // Correct type already, nothing to do.
28519 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
28520 // return "eax". This should even work for things like getting 64bit integer
28521 // registers when given an f64 type.
28522 const TargetRegisterClass *Class = Res.second;
28523 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
28524 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
28525 unsigned Size = VT.getSizeInBits();
28526 if (Size == 1) Size = 8;
28527 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);
28529 Res.first = DestReg;
28530 Res.second = Size == 8 ? &X86::GR8RegClass
28531 : Size == 16 ? &X86::GR16RegClass
28532 : Size == 32 ? &X86::GR32RegClass
28533 : &X86::GR64RegClass;
28534 assert(Res.second->contains(Res.first) && "Register in register class");
28536 // No register found/type mismatch.
28538 Res.second = nullptr;
28540 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
28541 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
28542 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
28543 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
28544 Class == &X86::VR512RegClass) {
28545 // Handle references to XMM physical registers that got mapped into the
28546 // wrong class. This can happen with constraints like {xmm0} where the
28547 // target independent register mapper will just pick the first match it can
28548 // find, ignoring the required type.
28550 // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
28551 if (VT == MVT::f32 || VT == MVT::i32)
28552 Res.second = &X86::FR32RegClass;
28553 else if (VT == MVT::f64 || VT == MVT::i64)
28554 Res.second = &X86::FR64RegClass;
28555 else if (X86::VR128RegClass.hasType(VT))
28556 Res.second = &X86::VR128RegClass;
28557 else if (X86::VR256RegClass.hasType(VT))
28558 Res.second = &X86::VR256RegClass;
28559 else if (X86::VR512RegClass.hasType(VT))
28560 Res.second = &X86::VR512RegClass;
28562 // Type mismatch and not a clobber: Return an error;
28564 Res.second = nullptr;
28571 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
28572 const AddrMode &AM, Type *Ty,
28573 unsigned AS) const {
28574 // Scaling factors are not free at all.
28575 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
28576 // will take 2 allocations in the out of order engine instead of 1
28577 // for plain addressing mode, i.e. inst (reg1).
28579 // vaddps (%rsi,%drx), %ymm0, %ymm1
28580 // Requires two allocations (one for the load, one for the computation)
28582 // vaddps (%rsi), %ymm0, %ymm1
28583 // Requires just 1 allocation, i.e., freeing allocations for other operations
28584 // and having less micro operations to execute.
28586 // For some X86 architectures, this is even worse because for instance for
28587 // stores, the complex addressing mode forces the instruction to use the
28588 // "load" ports instead of the dedicated "store" port.
28589 // E.g., on Haswell:
28590 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
28591 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
28592 if (isLegalAddressingMode(DL, AM, Ty, AS))
28593 // Scale represents reg2 * scale, thus account for 1
28594 // as soon as we use a second register.
28595 return AM.Scale != 0;
28599 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
28600 // Integer division on x86 is expensive. However, when aggressively optimizing
28601 // for code size, we prefer to use a div instruction, as it is usually smaller
28602 // than the alternative sequence.
28603 // The exception to this is vector division. Since x86 doesn't have vector
28604 // integer division, leaving the division as-is is a loss even in terms of
28605 // size, because it will have to be scalarized, while the alternative code
28606 // sequence can be performed in vector form.
28607 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
28608 Attribute::MinSize);
28609 return OptSize && !VT.isVector();
28612 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
28613 TargetLowering::ArgListTy& Args) const {
28614 // The MCU psABI requires some arguments to be passed in-register.
28615 // For regular calls, the inreg arguments are marked by the front-end.
28616 // However, for compiler generated library calls, we have to patch this
28618 if (!Subtarget->isTargetMCU() || !Args.size())
28621 unsigned FreeRegs = 3;
28622 for (auto &Arg : Args) {
28623 // For library functions, we do not expect any fancy types.
28624 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
28625 unsigned SizeInRegs = (Size + 31) / 32;
28626 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
28629 Arg.isInReg = true;
28630 FreeRegs -= SizeInRegs;