1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3649 // If we don't have a symbolic displacement - we don't have any extra
3651 if (!hasSymbolicDisplacement)
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3708 llvm_unreachable("covered switch fell through?!");
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3758 switch (SetCCOpcode) {
3764 std::swap(LHS, RHS);
3768 // On a floating point condition, the flags are set as follows:
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3789 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETUNE: return X86::COND_INVALID;
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 for (i = 0; i != NumLaneElts; ++i) {
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4012 return isAlignrMask(Mask, VT, false);
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return isAlignrMask(Mask, VT, true);
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4036 Mask[i] = idx - NumElems;
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4093 if ((signed)(Idx - l) != MaskVal[i])
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4107 unsigned NumElems = VT.getVectorNumElements();
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4126 unsigned NumElems = VT.getVectorNumElements();
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4200 else if (Mask[i] == i + 4)
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4213 // Some special combinations that can be optimized.
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4238 if (!MatchEvenMask && !MatchOddMask)
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4286 if (!isUndefOrEqual(BitI1, NumElts))
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4324 if (isUndefOrEqual(BitI1, NumElts))
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, j))
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4405 if (!isUndefOrEqual(BitI1, j))
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 if (!VT.is128BitVector())
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4488 return MatchA && MatchB;
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4512 return (FstHalf | (SndHalf << 4));
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4527 Imm8 |= Mask[i] << (i*2);
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4601 if (!isUndefOrEqual(Mask[0], 0))
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4668 unsigned NumElts = VT.getVectorNumElements();
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4706 // The index should be aligned on a vecWidth-bit boundary.
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 bool X86::isZeroNode(SDValue Elt) {
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4951 if (VT.getVectorNumElements() != 4)
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4972 *LD = cast<LoadSDNode>(N);
4976 // Test whether the given value is a vector value which will be legalized
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::ConstantFP:
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i + NumElems);
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5257 return getLegalSplat(DAG, V1, EltNo);
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFB: {
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5374 DecodePSHUFBMask(RawMask, Mask);
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5397 DecodePSHUFBMask(C, Mask);
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5436 default: llvm_unreachable("unknown target shuffle node");
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5444 if (M >= (int)Mask.size())
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5484 int Elt = ShuffleMask[Index];
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5529 if (X86::isZeroNode(Elt))
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5556 if (Idx < (int)NumElems)
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5566 OpNum = SeenV1 ? 0 : 1;
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5587 // V1 = {X, A, B, C} 0
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5601 ShVal = SVOp->getOperand(OpSrc);
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5622 // 0 { A, B, X, X } = V2
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5636 ShVal = SVOp->getOperand(OpSrc);
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 V = DAG.getUNDEF(MVT::v8i16);
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 V = DAG.getUNDEF(MVT::v8i16);
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5783 else if (IncorrectIdx == -1U) {
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5809 /// getVShift - Return a vector logical shift node.
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5873 if ((Offset % RequiredAlign) & 3)
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5932 if (Elt.getOpcode() == ISD::UNDEF)
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6015 MVT VT = Op.getSimpleValueType();
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6024 switch (Op.getOpcode()) {
6026 // Unknown pattern found.
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6157 // Unsupported broadcast.
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6205 unsigned NumElems = Op.getNumOperands();
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6223 InsertIndices.push_back(i);
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6248 if (ExtractedFromVec == VecIn1)
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6254 if (!VecIn1.getNode())
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6309 if (In != Op.getOperand(0))
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6433 ExpectedVExtractIdx += 2;
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6586 if (InVec1 != Op1.getOperand(0))
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6652 if (!Subtarget->hasAVX())
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6708 // Convert this build_vector into a pair of horizontal binop followed by
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6736 // Convert this build_vector into two horizontal add/sub followed by
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6802 NonZeros |= (1 << i);
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 if (V.getNode()) return V;
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7015 V[i] = V[i*2]; // Must be a zero vector.
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 V[i] = DAG.getUNDEF(VT);
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7171 /// \brief Helper function to classify a mask as a single-input mask.
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 if (M >= (int)Mask.size())
7186 /// \brief Test whether there are elements crossing 128-bit lanes in this
7189 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7190 /// and we routinely test for these.
7191 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7192 int LaneSize = 128 / VT.getScalarSizeInBits();
7193 int Size = Mask.size();
7194 for (int i = 0; i < Size; ++i)
7195 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7200 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7202 /// This checks a shuffle mask to see if it is performing the same
7203 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7204 /// that it is also not lane-crossing. It may however involve a blend from the
7205 /// same lane of a second vector.
7207 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7208 /// non-trivial to compute in the face of undef lanes. The representation is
7209 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7210 /// entries from both V1 and V2 inputs to the wider mask.
7212 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7213 SmallVectorImpl<int> &RepeatedMask) {
7214 int LaneSize = 128 / VT.getScalarSizeInBits();
7215 RepeatedMask.resize(LaneSize, -1);
7216 int Size = Mask.size();
7217 for (int i = 0; i < Size; ++i) {
7220 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7221 // This entry crosses lanes, so there is no way to model this shuffle.
7224 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7225 if (RepeatedMask[i % LaneSize] == -1)
7226 // This is the first non-undef entry in this slot of a 128-bit lane.
7227 RepeatedMask[i % LaneSize] =
7228 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7229 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7230 // Found a mismatch with the repeated mask.
7236 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7237 // 2013 will allow us to use it as a non-type template parameter.
7240 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7242 /// See its documentation for details.
7243 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7244 if (Mask.size() != Args.size())
7246 for (int i = 0, e = Mask.size(); i < e; ++i) {
7247 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7248 if (Mask[i] != -1 && Mask[i] != *Args[i])
7256 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7259 /// This is a fast way to test a shuffle mask against a fixed pattern:
7261 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7263 /// It returns true if the mask is exactly as wide as the argument list, and
7264 /// each element of the mask is either -1 (signifying undef) or the value given
7265 /// in the argument.
7266 static const VariadicFunction1<
7267 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7269 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7271 /// This helper function produces an 8-bit shuffle immediate corresponding to
7272 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7273 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7276 /// NB: We rely heavily on "undef" masks preserving the input lane.
7277 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7278 SelectionDAG &DAG) {
7279 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7280 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7281 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7282 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7283 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7286 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7287 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7288 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7289 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7290 return DAG.getConstant(Imm, MVT::i8);
7293 /// \brief Try to emit a blend instruction for a shuffle.
7295 /// This doesn't do any checks for the availability of instructions for blending
7296 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7297 /// be matched in the backend with the type given. What it does check for is
7298 /// that the shuffle mask is in fact a blend.
7299 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 unsigned BlendMask = 0;
7305 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7306 if (Mask[i] >= Size) {
7307 if (Mask[i] != i + Size)
7308 return SDValue(); // Shuffled V2 input!
7309 BlendMask |= 1u << i;
7312 if (Mask[i] >= 0 && Mask[i] != i)
7313 return SDValue(); // Shuffled V1 input!
7315 switch (VT.SimpleTy) {
7320 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7321 DAG.getConstant(BlendMask, MVT::i8));
7325 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7329 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7330 // that instruction.
7331 if (Subtarget->hasAVX2()) {
7332 // Scale the blend by the number of 32-bit dwords per element.
7333 int Scale = VT.getScalarSizeInBits() / 32;
7335 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7336 if (Mask[i] >= Size)
7337 for (int j = 0; j < Scale; ++j)
7338 BlendMask |= 1u << (i * Scale + j);
7340 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7341 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7342 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7343 return DAG.getNode(ISD::BITCAST, DL, VT,
7344 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7345 DAG.getConstant(BlendMask, MVT::i8)));
7349 // For integer shuffles we need to expand the mask and cast the inputs to
7350 // v8i16s prior to blending.
7351 int Scale = 8 / VT.getVectorNumElements();
7353 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7354 if (Mask[i] >= Size)
7355 for (int j = 0; j < Scale; ++j)
7356 BlendMask |= 1u << (i * Scale + j);
7358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7359 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7362 DAG.getConstant(BlendMask, MVT::i8)));
7366 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 SmallVector<int, 8> RepeatedMask;
7368 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7369 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7370 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7372 for (int i = 0; i < 8; ++i)
7373 if (RepeatedMask[i] >= 16)
7374 BlendMask |= 1u << i;
7375 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7376 DAG.getConstant(BlendMask, MVT::i8));
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7382 SDValue PBLENDVMask[32];
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7386 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7387 for (int j = 0; j < Scale; ++j)
7388 PBLENDVMask[Scale * i + j] =
7389 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7390 : DAG.getConstant(Mask[i] < Size ? 0 : 0x80, MVT::i8);
7392 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7393 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7395 ISD::BITCAST, DL, VT,
7396 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7397 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PBLENDVMask),
7402 llvm_unreachable("Not a supported integer vector type!");
7406 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7407 /// unblended shuffles followed by an unshuffled blend.
7409 /// This matches the extremely common pattern for handling combined
7410 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7412 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7416 SelectionDAG &DAG) {
7417 // Shuffle the input elements into the desired positions in V1 and V2 and
7418 // blend them together.
7419 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7420 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7421 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7422 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7423 if (Mask[i] >= 0 && Mask[i] < Size) {
7424 V1Mask[i] = Mask[i];
7426 } else if (Mask[i] >= Size) {
7427 V2Mask[i] = Mask[i] - Size;
7428 BlendMask[i] = i + Size;
7431 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7432 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7433 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7436 /// \brief Try to lower a vector shuffle as a byte rotation.
7438 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7439 /// byte-rotation of a the concatentation of two vectors. This routine will
7440 /// try to generically lower a vector shuffle through such an instruction. It
7441 /// does not check for the availability of PALIGNR-based lowerings, only the
7442 /// applicability of this strategy to the given mask. This matches shuffle
7443 /// vectors that look like:
7445 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7447 /// Essentially it concatenates V1 and V2, shifts right by some number of
7448 /// elements, and takes the low elements as the result. Note that while this is
7449 /// specified as a *right shift* because x86 is little-endian, it is a *left
7450 /// rotate* of the vector lanes.
7452 /// Note that this only handles 128-bit vector widths currently.
7453 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7456 SelectionDAG &DAG) {
7457 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7459 // We need to detect various ways of spelling a rotation:
7460 // [11, 12, 13, 14, 15, 0, 1, 2]
7461 // [-1, 12, 13, 14, -1, -1, 1, -1]
7462 // [-1, -1, -1, -1, -1, -1, 1, 2]
7463 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7464 // [-1, 4, 5, 6, -1, -1, 9, -1]
7465 // [-1, 4, 5, 6, -1, -1, -1, -1]
7468 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7471 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7473 // Based on the mod-Size value of this mask element determine where
7474 // a rotated vector would have started.
7475 int StartIdx = i - (Mask[i] % Size);
7477 // The identity rotation isn't interesting, stop.
7480 // If we found the tail of a vector the rotation must be the missing
7481 // front. If we found the head of a vector, it must be how much of the head.
7482 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7485 Rotation = CandidateRotation;
7486 else if (Rotation != CandidateRotation)
7487 // The rotations don't match, so we can't match this mask.
7490 // Compute which value this mask is pointing at.
7491 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7493 // Compute which of the two target values this index should be assigned to.
7494 // This reflects whether the high elements are remaining or the low elements
7496 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7498 // Either set up this value if we've not encountered it before, or check
7499 // that it remains consistent.
7502 else if (TargetV != MaskV)
7503 // This may be a rotation, but it pulls from the inputs in some
7504 // unsupported interleaving.
7508 // Check that we successfully analyzed the mask, and normalize the results.
7509 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7510 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7516 // Cast the inputs to v16i8 to match PALIGNR.
7517 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7518 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7520 assert(VT.getSizeInBits() == 128 &&
7521 "Rotate-based lowering only supports 128-bit lowering!");
7522 assert(Mask.size() <= 16 &&
7523 "Can shuffle at most 16 bytes in a 128-bit vector!");
7524 // The actual rotate instruction rotates bytes, so we need to scale the
7525 // rotation based on how many bytes are in the vector.
7526 int Scale = 16 / Mask.size();
7528 return DAG.getNode(ISD::BITCAST, DL, VT,
7529 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7530 DAG.getConstant(Rotation * Scale, MVT::i8)));
7533 /// \brief Compute whether each element of a shuffle is zeroable.
7535 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7536 /// Either it is an undef element in the shuffle mask, the element of the input
7537 /// referenced is undef, or the element of the input referenced is known to be
7538 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7539 /// as many lanes with this technique as possible to simplify the remaining
7541 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7542 SDValue V1, SDValue V2) {
7543 SmallBitVector Zeroable(Mask.size(), false);
7545 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7546 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7548 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7550 // Handle the easy cases.
7551 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7556 // If this is an index into a build_vector node, dig out the input value and
7558 SDValue V = M < Size ? V1 : V2;
7559 if (V.getOpcode() != ISD::BUILD_VECTOR)
7562 SDValue Input = V.getOperand(M % Size);
7563 // The UNDEF opcode check really should be dead code here, but not quite
7564 // worth asserting on (it isn't invalid, just unexpected).
7565 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7572 /// \brief Lower a vector shuffle as a zero or any extension.
7574 /// Given a specific number of elements, element bit width, and extension
7575 /// stride, produce either a zero or any extension based on the available
7576 /// features of the subtarget.
7577 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7578 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7579 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7580 assert(Scale > 1 && "Need a scale to extend.");
7581 int EltBits = VT.getSizeInBits() / NumElements;
7582 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7583 "Only 8, 16, and 32 bit elements can be extended.");
7584 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7586 // Found a valid zext mask! Try various lowering strategies based on the
7587 // input type and available ISA extensions.
7588 if (Subtarget->hasSSE41()) {
7589 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7590 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7591 NumElements / Scale);
7592 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7593 return DAG.getNode(ISD::BITCAST, DL, VT,
7594 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7597 // For any extends we can cheat for larger element sizes and use shuffle
7598 // instructions that can fold with a load and/or copy.
7599 if (AnyExt && EltBits == 32) {
7600 int PSHUFDMask[4] = {0, -1, 1, -1};
7602 ISD::BITCAST, DL, VT,
7603 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7604 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7605 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7607 if (AnyExt && EltBits == 16 && Scale > 2) {
7608 int PSHUFDMask[4] = {0, -1, 0, -1};
7609 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7610 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7611 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7612 int PSHUFHWMask[4] = {1, -1, -1, -1};
7614 ISD::BITCAST, DL, VT,
7615 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7616 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7620 // If this would require more than 2 unpack instructions to expand, use
7621 // pshufb when available. We can only use more than 2 unpack instructions
7622 // when zero extending i8 elements which also makes it easier to use pshufb.
7623 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7624 assert(NumElements == 16 && "Unexpected byte vector width!");
7625 SDValue PSHUFBMask[16];
7626 for (int i = 0; i < 16; ++i)
7628 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7629 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7630 return DAG.getNode(ISD::BITCAST, DL, VT,
7631 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7632 DAG.getNode(ISD::BUILD_VECTOR, DL,
7633 MVT::v16i8, PSHUFBMask)));
7636 // Otherwise emit a sequence of unpacks.
7638 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7639 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7640 : getZeroVector(InputVT, Subtarget, DAG, DL);
7641 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7642 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7646 } while (Scale > 1);
7647 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7650 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7652 /// This routine will try to do everything in its power to cleverly lower
7653 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7654 /// check for the profitability of this lowering, it tries to aggressively
7655 /// match this pattern. It will use all of the micro-architectural details it
7656 /// can to emit an efficient lowering. It handles both blends with all-zero
7657 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7658 /// masking out later).
7660 /// The reason we have dedicated lowering for zext-style shuffles is that they
7661 /// are both incredibly common and often quite performance sensitive.
7662 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7663 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7664 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7665 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7667 int Bits = VT.getSizeInBits();
7668 int NumElements = Mask.size();
7670 // Define a helper function to check a particular ext-scale and lower to it if
7672 auto Lower = [&](int Scale) -> SDValue {
7675 for (int i = 0; i < NumElements; ++i) {
7677 continue; // Valid anywhere but doesn't tell us anything.
7678 if (i % Scale != 0) {
7679 // Each of the extend elements needs to be zeroable.
7683 // We no lorger are in the anyext case.
7688 // Each of the base elements needs to be consecutive indices into the
7689 // same input vector.
7690 SDValue V = Mask[i] < NumElements ? V1 : V2;
7693 else if (InputV != V)
7694 return SDValue(); // Flip-flopping inputs.
7696 if (Mask[i] % NumElements != i / Scale)
7697 return SDValue(); // Non-consecutive strided elemenst.
7700 // If we fail to find an input, we have a zero-shuffle which should always
7701 // have already been handled.
7702 // FIXME: Maybe handle this here in case during blending we end up with one?
7706 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7707 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7710 // The widest scale possible for extending is to a 64-bit integer.
7711 assert(Bits % 64 == 0 &&
7712 "The number of bits in a vector must be divisible by 64 on x86!");
7713 int NumExtElements = Bits / 64;
7715 // Each iteration, try extending the elements half as much, but into twice as
7717 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7718 assert(NumElements % NumExtElements == 0 &&
7719 "The input vector size must be divisble by the extended size.");
7720 if (SDValue V = Lower(NumElements / NumExtElements))
7724 // No viable ext lowering found.
7728 /// \brief Try to lower insertion of a single element into a zero vector.
7730 /// This is a common pattern that we have especially efficient patterns to lower
7731 /// across all subtarget feature sets.
7732 static SDValue lowerVectorShuffleAsElementInsertion(
7733 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7734 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7735 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7737 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7738 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7740 if (Mask.size() == 2) {
7741 if (!Zeroable[V2Index ^ 1]) {
7742 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7743 // with 2 to flip from {2,3} to {0,1} and vice versa.
7744 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7745 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7746 if (Zeroable[V2Index])
7747 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7753 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7754 if (i != V2Index && !Zeroable[i])
7755 return SDValue(); // Not inserting into a zero vector.
7758 // Step over any bitcasts on either input so we can scan the actual
7759 // BUILD_VECTOR nodes.
7760 while (V1.getOpcode() == ISD::BITCAST)
7761 V1 = V1.getOperand(0);
7762 while (V2.getOpcode() == ISD::BITCAST)
7763 V2 = V2.getOperand(0);
7765 // Check for a single input from a SCALAR_TO_VECTOR node.
7766 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7767 // all the smarts here sunk into that routine. However, the current
7768 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7769 // vector shuffle lowering is dead.
7770 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7771 Mask[V2Index] == (int)Mask.size()) ||
7772 V2.getOpcode() == ISD::BUILD_VECTOR))
7775 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7777 // First, we need to zext the scalar if it is smaller than an i32.
7779 MVT EltVT = VT.getVectorElementType();
7780 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7781 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7782 // Zero-extend directly to i32.
7784 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7787 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7788 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7790 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7793 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7794 // the desired position. Otherwise it is more efficient to do a vector
7795 // shift left. We know that we can do a vector shift left because all
7796 // the inputs are zero.
7797 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7798 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7799 V2Shuffle[V2Index] = 0;
7800 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7802 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7804 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7806 V2Index * EltVT.getSizeInBits(),
7807 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7808 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7814 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7816 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7817 /// support for floating point shuffles but not integer shuffles. These
7818 /// instructions will incur a domain crossing penalty on some chips though so
7819 /// it is better to avoid lowering through this for integer vectors where
7821 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7822 const X86Subtarget *Subtarget,
7823 SelectionDAG &DAG) {
7825 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7826 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7827 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7828 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7829 ArrayRef<int> Mask = SVOp->getMask();
7830 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7832 if (isSingleInputShuffleMask(Mask)) {
7833 // Straight shuffle of a single input vector. Simulate this by using the
7834 // single input as both of the "inputs" to this instruction..
7835 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7837 if (Subtarget->hasAVX()) {
7838 // If we have AVX, we can use VPERMILPS which will allow folding a load
7839 // into the shuffle.
7840 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7841 DAG.getConstant(SHUFPDMask, MVT::i8));
7844 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7845 DAG.getConstant(SHUFPDMask, MVT::i8));
7847 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7848 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7850 // Use dedicated unpack instructions for masks that match their pattern.
7851 if (isShuffleEquivalent(Mask, 0, 2))
7852 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7853 if (isShuffleEquivalent(Mask, 1, 3))
7854 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7856 // If we have a single input, insert that into V1 if we can do so cheaply.
7857 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7858 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7859 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7862 if (Subtarget->hasSSE41())
7863 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7867 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7868 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7869 DAG.getConstant(SHUFPDMask, MVT::i8));
7872 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7874 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7875 /// the integer unit to minimize domain crossing penalties. However, for blends
7876 /// it falls back to the floating point shuffle operation with appropriate bit
7878 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7879 const X86Subtarget *Subtarget,
7880 SelectionDAG &DAG) {
7882 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7883 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7884 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7886 ArrayRef<int> Mask = SVOp->getMask();
7887 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7889 if (isSingleInputShuffleMask(Mask)) {
7890 // Straight shuffle of a single input vector. For everything from SSE2
7891 // onward this has a single fast instruction with no scary immediates.
7892 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7893 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7894 int WidenedMask[4] = {
7895 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7896 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7898 ISD::BITCAST, DL, MVT::v2i64,
7899 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7900 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7903 // Use dedicated unpack instructions for masks that match their pattern.
7904 if (isShuffleEquivalent(Mask, 0, 2))
7905 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7906 if (isShuffleEquivalent(Mask, 1, 3))
7907 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7909 // If we have a single input from V2 insert that into V1 if we can do so
7911 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7912 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7913 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7916 if (Subtarget->hasSSE41())
7917 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7921 // Try to use rotation instructions if available.
7922 if (Subtarget->hasSSSE3())
7923 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7924 DL, MVT::v2i64, V1, V2, Mask, DAG))
7927 // We implement this with SHUFPD which is pretty lame because it will likely
7928 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7929 // However, all the alternatives are still more cycles and newer chips don't
7930 // have this problem. It would be really nice if x86 had better shuffles here.
7931 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7932 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7933 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7934 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7937 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7939 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7940 /// It makes no assumptions about whether this is the *best* lowering, it simply
7942 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7943 ArrayRef<int> Mask, SDValue V1,
7944 SDValue V2, SelectionDAG &DAG) {
7945 SDValue LowV = V1, HighV = V2;
7946 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7949 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7951 if (NumV2Elements == 1) {
7953 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7956 // Compute the index adjacent to V2Index and in the same half by toggling
7958 int V2AdjIndex = V2Index ^ 1;
7960 if (Mask[V2AdjIndex] == -1) {
7961 // Handles all the cases where we have a single V2 element and an undef.
7962 // This will only ever happen in the high lanes because we commute the
7963 // vector otherwise.
7965 std::swap(LowV, HighV);
7966 NewMask[V2Index] -= 4;
7968 // Handle the case where the V2 element ends up adjacent to a V1 element.
7969 // To make this work, blend them together as the first step.
7970 int V1Index = V2AdjIndex;
7971 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7972 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7973 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7975 // Now proceed to reconstruct the final blend as we have the necessary
7976 // high or low half formed.
7983 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7984 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7986 } else if (NumV2Elements == 2) {
7987 if (Mask[0] < 4 && Mask[1] < 4) {
7988 // Handle the easy case where we have V1 in the low lanes and V2 in the
7989 // high lanes. We never see this reversed because we sort the shuffle.
7993 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7994 // trying to place elements directly, just blend them and set up the final
7995 // shuffle to place them.
7997 // The first two blend mask elements are for V1, the second two are for
7999 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8000 Mask[2] < 4 ? Mask[2] : Mask[3],
8001 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8002 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8003 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8004 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8006 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8009 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8010 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8011 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8012 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8015 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8016 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8019 /// \brief Lower 4-lane 32-bit floating point shuffles.
8021 /// Uses instructions exclusively from the floating point unit to minimize
8022 /// domain crossing penalties, as these are sufficient to implement all v4f32
8024 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8025 const X86Subtarget *Subtarget,
8026 SelectionDAG &DAG) {
8028 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8029 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8030 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8031 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8032 ArrayRef<int> Mask = SVOp->getMask();
8033 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8036 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8038 if (NumV2Elements == 0) {
8039 if (Subtarget->hasAVX()) {
8040 // If we have AVX, we can use VPERMILPS which will allow folding a load
8041 // into the shuffle.
8042 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8043 getV4X86ShuffleImm8ForMask(Mask, DAG));
8046 // Otherwise, use a straight shuffle of a single input vector. We pass the
8047 // input vector to both operands to simulate this with a SHUFPS.
8048 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8049 getV4X86ShuffleImm8ForMask(Mask, DAG));
8052 // Use dedicated unpack instructions for masks that match their pattern.
8053 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8054 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8055 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8056 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8058 // There are special ways we can lower some single-element blends. However, we
8059 // have custom ways we can lower more complex single-element blends below that
8060 // we defer to if both this and BLENDPS fail to match, so restrict this to
8061 // when the V2 input is targeting element 0 of the mask -- that is the fast
8063 if (NumV2Elements == 1 && Mask[0] >= 4)
8064 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8065 Mask, Subtarget, DAG))
8068 if (Subtarget->hasSSE41())
8069 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8073 // Check for whether we can use INSERTPS to perform the blend. We only use
8074 // INSERTPS when the V1 elements are already in the correct locations
8075 // because otherwise we can just always use two SHUFPS instructions which
8076 // are much smaller to encode than a SHUFPS and an INSERTPS.
8077 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8079 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8082 // When using INSERTPS we can zero any lane of the destination. Collect
8083 // the zero inputs into a mask and drop them from the lanes of V1 which
8084 // actually need to be present as inputs to the INSERTPS.
8085 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8087 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8088 bool InsertNeedsShuffle = false;
8090 for (int i = 0; i < 4; ++i)
8094 } else if (Mask[i] != i) {
8095 InsertNeedsShuffle = true;
8100 // We don't want to use INSERTPS or other insertion techniques if it will
8101 // require shuffling anyways.
8102 if (!InsertNeedsShuffle) {
8103 // If all of V1 is zeroable, replace it with undef.
8104 if ((ZMask | 1 << V2Index) == 0xF)
8105 V1 = DAG.getUNDEF(MVT::v4f32);
8107 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8108 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8110 // Insert the V2 element into the desired position.
8111 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8112 DAG.getConstant(InsertPSMask, MVT::i8));
8116 // Otherwise fall back to a SHUFPS lowering strategy.
8117 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8120 /// \brief Lower 4-lane i32 vector shuffles.
8122 /// We try to handle these with integer-domain shuffles where we can, but for
8123 /// blends we use the floating point domain blend instructions.
8124 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8125 const X86Subtarget *Subtarget,
8126 SelectionDAG &DAG) {
8128 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8129 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8130 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8131 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8132 ArrayRef<int> Mask = SVOp->getMask();
8133 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8136 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8138 if (NumV2Elements == 0) {
8139 // Straight shuffle of a single input vector. For everything from SSE2
8140 // onward this has a single fast instruction with no scary immediates.
8141 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8142 // but we aren't actually going to use the UNPCK instruction because doing
8143 // so prevents folding a load into this instruction or making a copy.
8144 const int UnpackLoMask[] = {0, 0, 1, 1};
8145 const int UnpackHiMask[] = {2, 2, 3, 3};
8146 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8147 Mask = UnpackLoMask;
8148 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8149 Mask = UnpackHiMask;
8151 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8152 getV4X86ShuffleImm8ForMask(Mask, DAG));
8155 // Whenever we can lower this as a zext, that instruction is strictly faster
8156 // than any alternative.
8157 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8158 Mask, Subtarget, DAG))
8161 // Use dedicated unpack instructions for masks that match their pattern.
8162 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8163 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8164 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8165 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8167 // There are special ways we can lower some single-element blends.
8168 if (NumV2Elements == 1)
8169 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8170 Mask, Subtarget, DAG))
8173 if (Subtarget->hasSSE41())
8174 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8178 // Try to use rotation instructions if available.
8179 if (Subtarget->hasSSSE3())
8180 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8181 DL, MVT::v4i32, V1, V2, Mask, DAG))
8184 // We implement this with SHUFPS because it can blend from two vectors.
8185 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8186 // up the inputs, bypassing domain shift penalties that we would encur if we
8187 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8189 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8190 DAG.getVectorShuffle(
8192 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8193 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8196 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8197 /// shuffle lowering, and the most complex part.
8199 /// The lowering strategy is to try to form pairs of input lanes which are
8200 /// targeted at the same half of the final vector, and then use a dword shuffle
8201 /// to place them onto the right half, and finally unpack the paired lanes into
8202 /// their final position.
8204 /// The exact breakdown of how to form these dword pairs and align them on the
8205 /// correct sides is really tricky. See the comments within the function for
8206 /// more of the details.
8207 static SDValue lowerV8I16SingleInputVectorShuffle(
8208 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8209 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8210 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8211 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8212 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8214 SmallVector<int, 4> LoInputs;
8215 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8216 [](int M) { return M >= 0; });
8217 std::sort(LoInputs.begin(), LoInputs.end());
8218 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8219 SmallVector<int, 4> HiInputs;
8220 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8221 [](int M) { return M >= 0; });
8222 std::sort(HiInputs.begin(), HiInputs.end());
8223 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8225 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8226 int NumHToL = LoInputs.size() - NumLToL;
8228 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8229 int NumHToH = HiInputs.size() - NumLToH;
8230 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8231 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8232 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8233 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8235 // Use dedicated unpack instructions for masks that match their pattern.
8236 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8237 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8238 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8239 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8241 // Try to use rotation instructions if available.
8242 if (Subtarget->hasSSSE3())
8243 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8244 DL, MVT::v8i16, V, V, Mask, DAG))
8247 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8248 // such inputs we can swap two of the dwords across the half mark and end up
8249 // with <=2 inputs to each half in each half. Once there, we can fall through
8250 // to the generic code below. For example:
8252 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8253 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8255 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8256 // and an existing 2-into-2 on the other half. In this case we may have to
8257 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8258 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8259 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8260 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8261 // half than the one we target for fixing) will be fixed when we re-enter this
8262 // path. We will also combine away any sequence of PSHUFD instructions that
8263 // result into a single instruction. Here is an example of the tricky case:
8265 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8266 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8268 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8270 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8271 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8273 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8274 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8276 // The result is fine to be handled by the generic logic.
8277 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8278 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8279 int AOffset, int BOffset) {
8280 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8281 "Must call this with A having 3 or 1 inputs from the A half.");
8282 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8283 "Must call this with B having 1 or 3 inputs from the B half.");
8284 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8285 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8287 // Compute the index of dword with only one word among the three inputs in
8288 // a half by taking the sum of the half with three inputs and subtracting
8289 // the sum of the actual three inputs. The difference is the remaining
8292 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8293 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8294 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8295 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8296 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8297 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8298 int TripleNonInputIdx =
8299 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8300 TripleDWord = TripleNonInputIdx / 2;
8302 // We use xor with one to compute the adjacent DWord to whichever one the
8304 OneInputDWord = (OneInput / 2) ^ 1;
8306 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8307 // and BToA inputs. If there is also such a problem with the BToB and AToB
8308 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8309 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8310 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8311 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8312 // Compute how many inputs will be flipped by swapping these DWords. We
8314 // to balance this to ensure we don't form a 3-1 shuffle in the other
8316 int NumFlippedAToBInputs =
8317 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8318 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8319 int NumFlippedBToBInputs =
8320 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8321 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8322 if ((NumFlippedAToBInputs == 1 &&
8323 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8324 (NumFlippedBToBInputs == 1 &&
8325 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8326 // We choose whether to fix the A half or B half based on whether that
8327 // half has zero flipped inputs. At zero, we may not be able to fix it
8328 // with that half. We also bias towards fixing the B half because that
8329 // will more commonly be the high half, and we have to bias one way.
8330 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8331 ArrayRef<int> Inputs) {
8332 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8333 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8334 PinnedIdx ^ 1) != Inputs.end();
8335 // Determine whether the free index is in the flipped dword or the
8336 // unflipped dword based on where the pinned index is. We use this bit
8337 // in an xor to conditionally select the adjacent dword.
8338 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8339 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8340 FixFreeIdx) != Inputs.end();
8341 if (IsFixIdxInput == IsFixFreeIdxInput)
8343 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8344 FixFreeIdx) != Inputs.end();
8345 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8346 "We need to be changing the number of flipped inputs!");
8347 int PSHUFHalfMask[] = {0, 1, 2, 3};
8348 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8349 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8351 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8354 if (M != -1 && M == FixIdx)
8356 else if (M != -1 && M == FixFreeIdx)
8359 if (NumFlippedBToBInputs != 0) {
8361 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8362 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8364 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8366 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8367 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8372 int PSHUFDMask[] = {0, 1, 2, 3};
8373 PSHUFDMask[ADWord] = BDWord;
8374 PSHUFDMask[BDWord] = ADWord;
8375 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8376 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8377 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8378 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8380 // Adjust the mask to match the new locations of A and B.
8382 if (M != -1 && M/2 == ADWord)
8383 M = 2 * BDWord + M % 2;
8384 else if (M != -1 && M/2 == BDWord)
8385 M = 2 * ADWord + M % 2;
8387 // Recurse back into this routine to re-compute state now that this isn't
8388 // a 3 and 1 problem.
8389 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8392 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8393 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8394 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8395 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8397 // At this point there are at most two inputs to the low and high halves from
8398 // each half. That means the inputs can always be grouped into dwords and
8399 // those dwords can then be moved to the correct half with a dword shuffle.
8400 // We use at most one low and one high word shuffle to collect these paired
8401 // inputs into dwords, and finally a dword shuffle to place them.
8402 int PSHUFLMask[4] = {-1, -1, -1, -1};
8403 int PSHUFHMask[4] = {-1, -1, -1, -1};
8404 int PSHUFDMask[4] = {-1, -1, -1, -1};
8406 // First fix the masks for all the inputs that are staying in their
8407 // original halves. This will then dictate the targets of the cross-half
8409 auto fixInPlaceInputs =
8410 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8411 MutableArrayRef<int> SourceHalfMask,
8412 MutableArrayRef<int> HalfMask, int HalfOffset) {
8413 if (InPlaceInputs.empty())
8415 if (InPlaceInputs.size() == 1) {
8416 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8417 InPlaceInputs[0] - HalfOffset;
8418 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8421 if (IncomingInputs.empty()) {
8422 // Just fix all of the in place inputs.
8423 for (int Input : InPlaceInputs) {
8424 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8425 PSHUFDMask[Input / 2] = Input / 2;
8430 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8431 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8432 InPlaceInputs[0] - HalfOffset;
8433 // Put the second input next to the first so that they are packed into
8434 // a dword. We find the adjacent index by toggling the low bit.
8435 int AdjIndex = InPlaceInputs[0] ^ 1;
8436 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8437 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8438 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8440 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8441 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8443 // Now gather the cross-half inputs and place them into a free dword of
8444 // their target half.
8445 // FIXME: This operation could almost certainly be simplified dramatically to
8446 // look more like the 3-1 fixing operation.
8447 auto moveInputsToRightHalf = [&PSHUFDMask](
8448 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8449 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8450 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8452 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8453 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8455 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8457 int LowWord = Word & ~1;
8458 int HighWord = Word | 1;
8459 return isWordClobbered(SourceHalfMask, LowWord) ||
8460 isWordClobbered(SourceHalfMask, HighWord);
8463 if (IncomingInputs.empty())
8466 if (ExistingInputs.empty()) {
8467 // Map any dwords with inputs from them into the right half.
8468 for (int Input : IncomingInputs) {
8469 // If the source half mask maps over the inputs, turn those into
8470 // swaps and use the swapped lane.
8471 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8472 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8473 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8474 Input - SourceOffset;
8475 // We have to swap the uses in our half mask in one sweep.
8476 for (int &M : HalfMask)
8477 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8479 else if (M == Input)
8480 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8482 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8483 Input - SourceOffset &&
8484 "Previous placement doesn't match!");
8486 // Note that this correctly re-maps both when we do a swap and when
8487 // we observe the other side of the swap above. We rely on that to
8488 // avoid swapping the members of the input list directly.
8489 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8492 // Map the input's dword into the correct half.
8493 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8494 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8496 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8498 "Previous placement doesn't match!");
8501 // And just directly shift any other-half mask elements to be same-half
8502 // as we will have mirrored the dword containing the element into the
8503 // same position within that half.
8504 for (int &M : HalfMask)
8505 if (M >= SourceOffset && M < SourceOffset + 4) {
8506 M = M - SourceOffset + DestOffset;
8507 assert(M >= 0 && "This should never wrap below zero!");
8512 // Ensure we have the input in a viable dword of its current half. This
8513 // is particularly tricky because the original position may be clobbered
8514 // by inputs being moved and *staying* in that half.
8515 if (IncomingInputs.size() == 1) {
8516 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8517 int InputFixed = std::find(std::begin(SourceHalfMask),
8518 std::end(SourceHalfMask), -1) -
8519 std::begin(SourceHalfMask) + SourceOffset;
8520 SourceHalfMask[InputFixed - SourceOffset] =
8521 IncomingInputs[0] - SourceOffset;
8522 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8524 IncomingInputs[0] = InputFixed;
8526 } else if (IncomingInputs.size() == 2) {
8527 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8528 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8529 // We have two non-adjacent or clobbered inputs we need to extract from
8530 // the source half. To do this, we need to map them into some adjacent
8531 // dword slot in the source mask.
8532 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8533 IncomingInputs[1] - SourceOffset};
8535 // If there is a free slot in the source half mask adjacent to one of
8536 // the inputs, place the other input in it. We use (Index XOR 1) to
8537 // compute an adjacent index.
8538 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8539 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8540 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8541 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8542 InputsFixed[1] = InputsFixed[0] ^ 1;
8543 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8544 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8545 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8546 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8547 InputsFixed[0] = InputsFixed[1] ^ 1;
8548 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8549 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8550 // The two inputs are in the same DWord but it is clobbered and the
8551 // adjacent DWord isn't used at all. Move both inputs to the free
8553 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8554 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8555 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8556 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8558 // The only way we hit this point is if there is no clobbering
8559 // (because there are no off-half inputs to this half) and there is no
8560 // free slot adjacent to one of the inputs. In this case, we have to
8561 // swap an input with a non-input.
8562 for (int i = 0; i < 4; ++i)
8563 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8564 "We can't handle any clobbers here!");
8565 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8566 "Cannot have adjacent inputs here!");
8568 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8569 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8571 // We also have to update the final source mask in this case because
8572 // it may need to undo the above swap.
8573 for (int &M : FinalSourceHalfMask)
8574 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8575 M = InputsFixed[1] + SourceOffset;
8576 else if (M == InputsFixed[1] + SourceOffset)
8577 M = (InputsFixed[0] ^ 1) + SourceOffset;
8579 InputsFixed[1] = InputsFixed[0] ^ 1;
8582 // Point everything at the fixed inputs.
8583 for (int &M : HalfMask)
8584 if (M == IncomingInputs[0])
8585 M = InputsFixed[0] + SourceOffset;
8586 else if (M == IncomingInputs[1])
8587 M = InputsFixed[1] + SourceOffset;
8589 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8590 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8593 llvm_unreachable("Unhandled input size!");
8596 // Now hoist the DWord down to the right half.
8597 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8598 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8599 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8600 for (int &M : HalfMask)
8601 for (int Input : IncomingInputs)
8603 M = FreeDWord * 2 + Input % 2;
8605 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8606 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8607 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8608 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8610 // Now enact all the shuffles we've computed to move the inputs into their
8612 if (!isNoopShuffleMask(PSHUFLMask))
8613 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8614 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8615 if (!isNoopShuffleMask(PSHUFHMask))
8616 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8617 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8618 if (!isNoopShuffleMask(PSHUFDMask))
8619 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8620 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8621 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8622 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8624 // At this point, each half should contain all its inputs, and we can then
8625 // just shuffle them into their final position.
8626 assert(std::count_if(LoMask.begin(), LoMask.end(),
8627 [](int M) { return M >= 4; }) == 0 &&
8628 "Failed to lift all the high half inputs to the low mask!");
8629 assert(std::count_if(HiMask.begin(), HiMask.end(),
8630 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8631 "Failed to lift all the low half inputs to the high mask!");
8633 // Do a half shuffle for the low mask.
8634 if (!isNoopShuffleMask(LoMask))
8635 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8636 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8638 // Do a half shuffle with the high mask after shifting its values down.
8639 for (int &M : HiMask)
8642 if (!isNoopShuffleMask(HiMask))
8643 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8644 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8649 /// \brief Detect whether the mask pattern should be lowered through
8652 /// This essentially tests whether viewing the mask as an interleaving of two
8653 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8654 /// lowering it through interleaving is a significantly better strategy.
8655 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8656 int NumEvenInputs[2] = {0, 0};
8657 int NumOddInputs[2] = {0, 0};
8658 int NumLoInputs[2] = {0, 0};
8659 int NumHiInputs[2] = {0, 0};
8660 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8664 int InputIdx = Mask[i] >= Size;
8667 ++NumLoInputs[InputIdx];
8669 ++NumHiInputs[InputIdx];
8672 ++NumEvenInputs[InputIdx];
8674 ++NumOddInputs[InputIdx];
8677 // The minimum number of cross-input results for both the interleaved and
8678 // split cases. If interleaving results in fewer cross-input results, return
8680 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8681 NumEvenInputs[0] + NumOddInputs[1]);
8682 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8683 NumLoInputs[0] + NumHiInputs[1]);
8684 return InterleavedCrosses < SplitCrosses;
8687 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8689 /// This strategy only works when the inputs from each vector fit into a single
8690 /// half of that vector, and generally there are not so many inputs as to leave
8691 /// the in-place shuffles required highly constrained (and thus expensive). It
8692 /// shifts all the inputs into a single side of both input vectors and then
8693 /// uses an unpack to interleave these inputs in a single vector. At that
8694 /// point, we will fall back on the generic single input shuffle lowering.
8695 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8697 MutableArrayRef<int> Mask,
8698 const X86Subtarget *Subtarget,
8699 SelectionDAG &DAG) {
8700 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8701 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8702 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8703 for (int i = 0; i < 8; ++i)
8704 if (Mask[i] >= 0 && Mask[i] < 4)
8705 LoV1Inputs.push_back(i);
8706 else if (Mask[i] >= 4 && Mask[i] < 8)
8707 HiV1Inputs.push_back(i);
8708 else if (Mask[i] >= 8 && Mask[i] < 12)
8709 LoV2Inputs.push_back(i);
8710 else if (Mask[i] >= 12)
8711 HiV2Inputs.push_back(i);
8713 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8714 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8717 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8718 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8719 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8721 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8722 HiV1Inputs.size() + HiV2Inputs.size();
8724 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8725 ArrayRef<int> HiInputs, bool MoveToLo,
8727 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8728 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8729 if (BadInputs.empty())
8732 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8733 int MoveOffset = MoveToLo ? 0 : 4;
8735 if (GoodInputs.empty()) {
8736 for (int BadInput : BadInputs) {
8737 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8738 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8741 if (GoodInputs.size() == 2) {
8742 // If the low inputs are spread across two dwords, pack them into
8744 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8745 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8746 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8747 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8749 // Otherwise pin the good inputs.
8750 for (int GoodInput : GoodInputs)
8751 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8754 if (BadInputs.size() == 2) {
8755 // If we have two bad inputs then there may be either one or two good
8756 // inputs fixed in place. Find a fixed input, and then find the *other*
8757 // two adjacent indices by using modular arithmetic.
8759 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8760 [](int M) { return M >= 0; }) -
8761 std::begin(MoveMask);
8763 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8764 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8765 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8766 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8767 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8768 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8769 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8771 assert(BadInputs.size() == 1 && "All sizes handled");
8772 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8773 std::end(MoveMask), -1) -
8774 std::begin(MoveMask);
8775 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8776 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8780 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8783 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8785 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8788 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8789 // cross-half traffic in the final shuffle.
8791 // Munge the mask to be a single-input mask after the unpack merges the
8795 M = 2 * (M % 4) + (M / 8);
8797 return DAG.getVectorShuffle(
8798 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8799 DL, MVT::v8i16, V1, V2),
8800 DAG.getUNDEF(MVT::v8i16), Mask);
8803 /// \brief Generic lowering of 8-lane i16 shuffles.
8805 /// This handles both single-input shuffles and combined shuffle/blends with
8806 /// two inputs. The single input shuffles are immediately delegated to
8807 /// a dedicated lowering routine.
8809 /// The blends are lowered in one of three fundamental ways. If there are few
8810 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8811 /// of the input is significantly cheaper when lowered as an interleaving of
8812 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8813 /// halves of the inputs separately (making them have relatively few inputs)
8814 /// and then concatenate them.
8815 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8816 const X86Subtarget *Subtarget,
8817 SelectionDAG &DAG) {
8819 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8820 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8821 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8823 ArrayRef<int> OrigMask = SVOp->getMask();
8824 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8825 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8826 MutableArrayRef<int> Mask(MaskStorage);
8828 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8830 // Whenever we can lower this as a zext, that instruction is strictly faster
8831 // than any alternative.
8832 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8833 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8836 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8837 auto isV2 = [](int M) { return M >= 8; };
8839 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8840 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8842 if (NumV2Inputs == 0)
8843 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8845 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8846 "to be V1-input shuffles.");
8848 // There are special ways we can lower some single-element blends.
8849 if (NumV2Inputs == 1)
8850 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8851 Mask, Subtarget, DAG))
8854 if (Subtarget->hasSSE41())
8855 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8859 // Try to use rotation instructions if available.
8860 if (Subtarget->hasSSSE3())
8861 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8864 if (NumV1Inputs + NumV2Inputs <= 4)
8865 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8867 // Check whether an interleaving lowering is likely to be more efficient.
8868 // This isn't perfect but it is a strong heuristic that tends to work well on
8869 // the kinds of shuffles that show up in practice.
8871 // FIXME: Handle 1x, 2x, and 4x interleaving.
8872 if (shouldLowerAsInterleaving(Mask)) {
8873 // FIXME: Figure out whether we should pack these into the low or high
8876 int EMask[8], OMask[8];
8877 for (int i = 0; i < 4; ++i) {
8878 EMask[i] = Mask[2*i];
8879 OMask[i] = Mask[2*i + 1];
8884 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8885 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8887 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8890 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8891 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8893 for (int i = 0; i < 4; ++i) {
8894 LoBlendMask[i] = Mask[i];
8895 HiBlendMask[i] = Mask[i + 4];
8898 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8899 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8900 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8901 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8903 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8904 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8907 /// \brief Check whether a compaction lowering can be done by dropping even
8908 /// elements and compute how many times even elements must be dropped.
8910 /// This handles shuffles which take every Nth element where N is a power of
8911 /// two. Example shuffle masks:
8913 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8914 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8915 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8916 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8917 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8918 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8920 /// Any of these lanes can of course be undef.
8922 /// This routine only supports N <= 3.
8923 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8926 /// \returns N above, or the number of times even elements must be dropped if
8927 /// there is such a number. Otherwise returns zero.
8928 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8929 // Figure out whether we're looping over two inputs or just one.
8930 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8932 // The modulus for the shuffle vector entries is based on whether this is
8933 // a single input or not.
8934 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8935 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8936 "We should only be called with masks with a power-of-2 size!");
8938 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8940 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8941 // and 2^3 simultaneously. This is because we may have ambiguity with
8942 // partially undef inputs.
8943 bool ViableForN[3] = {true, true, true};
8945 for (int i = 0, e = Mask.size(); i < e; ++i) {
8946 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8951 bool IsAnyViable = false;
8952 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8953 if (ViableForN[j]) {
8956 // The shuffle mask must be equal to (i * 2^N) % M.
8957 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8960 ViableForN[j] = false;
8962 // Early exit if we exhaust the possible powers of two.
8967 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8971 // Return 0 as there is no viable power of two.
8975 /// \brief Generic lowering of v16i8 shuffles.
8977 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8978 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8979 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8980 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8982 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8983 const X86Subtarget *Subtarget,
8984 SelectionDAG &DAG) {
8986 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8987 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8988 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8989 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8990 ArrayRef<int> OrigMask = SVOp->getMask();
8991 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8993 // Try to use rotation instructions if available.
8994 if (Subtarget->hasSSSE3())
8995 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8999 // Try to use a zext lowering.
9000 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9001 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9004 int MaskStorage[16] = {
9005 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9006 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9007 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9008 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9009 MutableArrayRef<int> Mask(MaskStorage);
9010 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9011 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9014 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9016 // For single-input shuffles, there are some nicer lowering tricks we can use.
9017 if (NumV2Elements == 0) {
9018 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9019 // Notably, this handles splat and partial-splat shuffles more efficiently.
9020 // However, it only makes sense if the pre-duplication shuffle simplifies
9021 // things significantly. Currently, this means we need to be able to
9022 // express the pre-duplication shuffle as an i16 shuffle.
9024 // FIXME: We should check for other patterns which can be widened into an
9025 // i16 shuffle as well.
9026 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9027 for (int i = 0; i < 16; i += 2)
9028 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9033 auto tryToWidenViaDuplication = [&]() -> SDValue {
9034 if (!canWidenViaDuplication(Mask))
9036 SmallVector<int, 4> LoInputs;
9037 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9038 [](int M) { return M >= 0 && M < 8; });
9039 std::sort(LoInputs.begin(), LoInputs.end());
9040 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9042 SmallVector<int, 4> HiInputs;
9043 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9044 [](int M) { return M >= 8; });
9045 std::sort(HiInputs.begin(), HiInputs.end());
9046 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9049 bool TargetLo = LoInputs.size() >= HiInputs.size();
9050 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9051 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9053 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9054 SmallDenseMap<int, int, 8> LaneMap;
9055 for (int I : InPlaceInputs) {
9056 PreDupI16Shuffle[I/2] = I/2;
9059 int j = TargetLo ? 0 : 4, je = j + 4;
9060 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9061 // Check if j is already a shuffle of this input. This happens when
9062 // there are two adjacent bytes after we move the low one.
9063 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9064 // If we haven't yet mapped the input, search for a slot into which
9066 while (j < je && PreDupI16Shuffle[j] != -1)
9070 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9073 // Map this input with the i16 shuffle.
9074 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9077 // Update the lane map based on the mapping we ended up with.
9078 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9081 ISD::BITCAST, DL, MVT::v16i8,
9082 DAG.getVectorShuffle(MVT::v8i16, DL,
9083 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9084 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9086 // Unpack the bytes to form the i16s that will be shuffled into place.
9087 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9088 MVT::v16i8, V1, V1);
9090 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9091 for (int i = 0; i < 16; i += 2) {
9093 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9094 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
9097 ISD::BITCAST, DL, MVT::v16i8,
9098 DAG.getVectorShuffle(MVT::v8i16, DL,
9099 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9100 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9102 if (SDValue V = tryToWidenViaDuplication())
9106 // Check whether an interleaving lowering is likely to be more efficient.
9107 // This isn't perfect but it is a strong heuristic that tends to work well on
9108 // the kinds of shuffles that show up in practice.
9110 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9111 if (shouldLowerAsInterleaving(Mask)) {
9112 // FIXME: Figure out whether we should pack these into the low or high
9115 int EMask[16], OMask[16];
9116 for (int i = 0; i < 8; ++i) {
9117 EMask[i] = Mask[2*i];
9118 OMask[i] = Mask[2*i + 1];
9123 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9124 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9126 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9129 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9130 // with PSHUFB. It is important to do this before we attempt to generate any
9131 // blends but after all of the single-input lowerings. If the single input
9132 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9133 // want to preserve that and we can DAG combine any longer sequences into
9134 // a PSHUFB in the end. But once we start blending from multiple inputs,
9135 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9136 // and there are *very* few patterns that would actually be faster than the
9137 // PSHUFB approach because of its ability to zero lanes.
9139 // FIXME: The only exceptions to the above are blends which are exact
9140 // interleavings with direct instructions supporting them. We currently don't
9141 // handle those well here.
9142 if (Subtarget->hasSSSE3()) {
9145 for (int i = 0; i < 16; ++i)
9146 if (Mask[i] == -1) {
9147 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9149 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9151 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9153 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9154 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9155 if (isSingleInputShuffleMask(Mask))
9156 return V1; // Single inputs are easy.
9158 // Otherwise, blend the two.
9159 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9160 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9161 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9164 // There are special ways we can lower some single-element blends.
9165 if (NumV2Elements == 1)
9166 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9167 Mask, Subtarget, DAG))
9170 // Check whether a compaction lowering can be done. This handles shuffles
9171 // which take every Nth element for some even N. See the helper function for
9174 // We special case these as they can be particularly efficiently handled with
9175 // the PACKUSB instruction on x86 and they show up in common patterns of
9176 // rearranging bytes to truncate wide elements.
9177 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9178 // NumEvenDrops is the power of two stride of the elements. Another way of
9179 // thinking about it is that we need to drop the even elements this many
9180 // times to get the original input.
9181 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9183 // First we need to zero all the dropped bytes.
9184 assert(NumEvenDrops <= 3 &&
9185 "No support for dropping even elements more than 3 times.");
9186 // We use the mask type to pick which bytes are preserved based on how many
9187 // elements are dropped.
9188 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9189 SDValue ByteClearMask =
9190 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9191 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9192 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9194 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9196 // Now pack things back together.
9197 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9198 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9199 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9200 for (int i = 1; i < NumEvenDrops; ++i) {
9201 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9202 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9208 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9209 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9210 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9211 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9213 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9214 MutableArrayRef<int> V1HalfBlendMask,
9215 MutableArrayRef<int> V2HalfBlendMask) {
9216 for (int i = 0; i < 8; ++i)
9217 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9218 V1HalfBlendMask[i] = HalfMask[i];
9220 } else if (HalfMask[i] >= 16) {
9221 V2HalfBlendMask[i] = HalfMask[i] - 16;
9222 HalfMask[i] = i + 8;
9225 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9226 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9228 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9230 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9231 MutableArrayRef<int> HiBlendMask) {
9233 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9234 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9236 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9237 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9238 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9239 [](int M) { return M >= 0 && M % 2 == 1; })) {
9240 // Use a mask to drop the high bytes.
9241 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9242 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9243 DAG.getConstant(0x00FF, MVT::v8i16));
9245 // This will be a single vector shuffle instead of a blend so nuke V2.
9246 V2 = DAG.getUNDEF(MVT::v8i16);
9248 // Squash the masks to point directly into V1.
9249 for (int &M : LoBlendMask)
9252 for (int &M : HiBlendMask)
9256 // Otherwise just unpack the low half of V into V1 and the high half into
9257 // V2 so that we can blend them as i16s.
9258 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9259 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9260 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9261 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9264 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9265 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9266 return std::make_pair(BlendedLo, BlendedHi);
9268 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9269 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9270 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9272 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9273 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9275 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9278 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9280 /// This routine breaks down the specific type of 128-bit shuffle and
9281 /// dispatches to the lowering routines accordingly.
9282 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9283 MVT VT, const X86Subtarget *Subtarget,
9284 SelectionDAG &DAG) {
9285 switch (VT.SimpleTy) {
9287 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9289 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9291 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9293 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9295 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9297 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9300 llvm_unreachable("Unimplemented!");
9304 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9307 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9308 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9309 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9310 /// we encode the logic here for specific shuffle lowering routines to bail to
9311 /// when they exhaust the features avaible to more directly handle the shuffle.
9312 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9314 const X86Subtarget *Subtarget,
9315 SelectionDAG &DAG) {
9317 MVT VT = Op.getSimpleValueType();
9318 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9319 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9320 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9321 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9322 ArrayRef<int> Mask = SVOp->getMask();
9324 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9325 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9327 int NumElements = VT.getVectorNumElements();
9328 int SplitNumElements = NumElements / 2;
9329 MVT ScalarVT = VT.getScalarType();
9330 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9332 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9333 DAG.getIntPtrConstant(0));
9334 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9335 DAG.getIntPtrConstant(SplitNumElements));
9336 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9337 DAG.getIntPtrConstant(0));
9338 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9339 DAG.getIntPtrConstant(SplitNumElements));
9341 // Now create two 4-way blends of these half-width vectors.
9342 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9343 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9344 for (int i = 0; i < SplitNumElements; ++i) {
9345 int M = HalfMask[i];
9346 if (M >= NumElements) {
9347 V2BlendMask.push_back(M - NumElements);
9348 V1BlendMask.push_back(-1);
9349 BlendMask.push_back(SplitNumElements + i);
9350 } else if (M >= 0) {
9351 V2BlendMask.push_back(-1);
9352 V1BlendMask.push_back(M);
9353 BlendMask.push_back(i);
9355 V2BlendMask.push_back(-1);
9356 V1BlendMask.push_back(-1);
9357 BlendMask.push_back(-1);
9360 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9361 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9362 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9364 SDValue Lo = HalfBlend(LoMask);
9365 SDValue Hi = HalfBlend(HiMask);
9366 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9369 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9371 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9372 /// isn't available.
9373 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9374 const X86Subtarget *Subtarget,
9375 SelectionDAG &DAG) {
9377 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9378 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9380 ArrayRef<int> Mask = SVOp->getMask();
9381 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9383 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9384 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9386 if (isSingleInputShuffleMask(Mask)) {
9387 // Non-half-crossing single input shuffles can be lowerid with an
9388 // interleaved permutation.
9389 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9390 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9391 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9392 DAG.getConstant(VPERMILPMask, MVT::i8));
9395 // X86 has dedicated unpack instructions that can handle specific blend
9396 // operations: UNPCKH and UNPCKL.
9397 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9398 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9399 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9400 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9402 // If we have a single input to the zero element, insert that into V1 if we
9403 // can do so cheaply.
9405 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9406 if (NumV2Elements == 1 && Mask[0] >= 4)
9407 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9408 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9411 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9415 // Check if the blend happens to exactly fit that of SHUFPD.
9416 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9417 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9418 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9419 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9420 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9421 DAG.getConstant(SHUFPDMask, MVT::i8));
9423 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9424 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9425 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9426 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9427 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9428 DAG.getConstant(SHUFPDMask, MVT::i8));
9431 // Otherwise fall back on generic blend lowering.
9432 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9436 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9438 /// This routine is only called when we have AVX2 and thus a reasonable
9439 /// instruction set for v4i64 shuffling..
9440 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9441 const X86Subtarget *Subtarget,
9442 SelectionDAG &DAG) {
9444 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9445 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9446 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9447 ArrayRef<int> Mask = SVOp->getMask();
9448 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9449 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9451 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9455 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9456 // use lower latency instructions that will operate on both 128-bit lanes.
9457 SmallVector<int, 2> RepeatedMask;
9458 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9459 if (isSingleInputShuffleMask(Mask)) {
9460 int PSHUFDMask[] = {-1, -1, -1, -1};
9461 for (int i = 0; i < 2; ++i)
9462 if (RepeatedMask[i] >= 0) {
9463 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9464 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9467 ISD::BITCAST, DL, MVT::v4i64,
9468 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9469 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9470 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9473 // Use dedicated unpack instructions for masks that match their pattern.
9474 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9475 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9476 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9477 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9480 // AVX2 provides a direct instruction for permuting a single input across
9482 if (isSingleInputShuffleMask(Mask))
9483 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9484 getV4X86ShuffleImm8ForMask(Mask, DAG));
9486 // Otherwise fall back on generic blend lowering.
9487 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9491 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9493 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9494 /// isn't available.
9495 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9496 const X86Subtarget *Subtarget,
9497 SelectionDAG &DAG) {
9499 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9500 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9502 ArrayRef<int> Mask = SVOp->getMask();
9503 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9505 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9506 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9508 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9512 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9513 // options to efficiently lower the shuffle.
9514 SmallVector<int, 2> RepeatedMask;
9515 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9516 if (isSingleInputShuffleMask(Mask))
9517 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9518 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9520 // Use dedicated unpack instructions for masks that match their pattern.
9521 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9522 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9523 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9524 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9526 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9527 // have already handled any direct blends.
9528 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9529 for (int &M : SHUFPSMask)
9532 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9535 // If we have a single input shuffle with different shuffle patterns in the
9536 // two 128-bit lanes use the variable mask to VPERMILPS.
9537 if (isSingleInputShuffleMask(Mask)) {
9538 SDValue VPermMask[8];
9539 for (int i = 0; i < 8; ++i)
9540 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9541 : DAG.getConstant(Mask[i], MVT::i32);
9543 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9544 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9547 // Otherwise fall back on generic blend lowering.
9548 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9552 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9554 /// This routine is only called when we have AVX2 and thus a reasonable
9555 /// instruction set for v8i32 shuffling..
9556 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9557 const X86Subtarget *Subtarget,
9558 SelectionDAG &DAG) {
9560 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9561 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9562 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9563 ArrayRef<int> Mask = SVOp->getMask();
9564 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9565 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9567 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9571 // If the shuffle mask is repeated in each 128-bit lane we can use more
9572 // efficient instructions that mirror the shuffles across the two 128-bit
9574 SmallVector<int, 4> RepeatedMask;
9575 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9576 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9577 if (isSingleInputShuffleMask(Mask))
9578 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9579 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9581 // Use dedicated unpack instructions for masks that match their pattern.
9582 if (isShuffleEquivalent(Mask, 0, 8, 1, 9))
9583 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9584 if (isShuffleEquivalent(Mask, 2, 10, 3, 11))
9585 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9588 // If the shuffle patterns aren't repeated but it is a single input, directly
9589 // generate a cross-lane VPERMD instruction.
9590 if (isSingleInputShuffleMask(Mask)) {
9591 SDValue VPermMask[8];
9592 for (int i = 0; i < 8; ++i)
9593 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9594 : DAG.getConstant(Mask[i], MVT::i32);
9596 X86ISD::VPERMV, DL, MVT::v8i32,
9597 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9600 // Otherwise fall back on generic blend lowering.
9601 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9605 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9607 /// This routine is only called when we have AVX2 and thus a reasonable
9608 /// instruction set for v16i16 shuffling..
9609 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9610 const X86Subtarget *Subtarget,
9611 SelectionDAG &DAG) {
9613 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9614 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9615 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9616 ArrayRef<int> Mask = SVOp->getMask();
9617 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9618 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9620 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9624 // If the shuffle mask is repeated in each 128-bit lane we can use more
9625 // efficient instructions that mirror the shuffles across the two 128-bit
9627 SmallVector<int, 4> RepeatedMask;
9628 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9629 assert(RepeatedMask.size() == 8 && "Unexpected repeated mask size!");
9630 // FIXME: It might be worth it to call into the (terribly complex) v8i16
9633 // Use dedicated unpack instructions for masks that match their pattern.
9635 if (isShuffleEquivalent(Mask,
9636 // First 128-bit lane:
9637 0, 16, 1, 17, 2, 18, 3, 19,
9638 // Second 128-bit lane:
9639 8, 24, 9, 25, 10, 26, 11, 27))
9640 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9641 if (isShuffleEquivalent(Mask,
9642 // First 128-bit lane:
9643 4, 20, 5, 21, 6, 22, 7, 23,
9644 // Second 128-bit lane:
9645 12, 28, 13, 29, 14, 30, 15, 31))
9646 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9649 // There are no generalized cross-lane shuffle operations available on i16
9651 // FIXME: We should teach the "split and lower" path to do something more
9652 // clever, or do it ourselves here. The optimal lowering of cross-lane
9653 // shuffles I am aware of is to swap the lanes into a copy, shuffle both the
9654 // original and the copy, and then blend to pick up the cross-lane elements.
9655 // This is four instructions with a tree height of three which is better than
9656 // the worst case for a gather-cross-scatter approach such as used in SSE2
9657 // v8i16 lowering (where we don't have blends). While for cross-lane blends it
9658 // results in a blend tree, blends are very cheap in AVX2 and newer chips. We
9659 // might also want to special case situations where we can always do a single
9660 // VPERMD to produce a non-lane-crossing shuffle.
9661 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9662 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9664 if (isSingleInputShuffleMask(Mask)) {
9665 SDValue PSHUFBMask[32];
9666 for (int i = 0; i < 16; ++i) {
9667 if (Mask[i] == -1) {
9668 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9672 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9673 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9674 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9675 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9678 ISD::BITCAST, DL, MVT::v16i16,
9680 X86ISD::PSHUFB, DL, MVT::v32i8,
9681 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9682 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9685 // Otherwise fall back on generic blend lowering.
9686 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9690 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9692 /// This routine is only called when we have AVX2 and thus a reasonable
9693 /// instruction set for v32i8 shuffling..
9694 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9695 const X86Subtarget *Subtarget,
9696 SelectionDAG &DAG) {
9698 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9699 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9700 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9701 ArrayRef<int> Mask = SVOp->getMask();
9702 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9703 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9705 // There are no generalized cross-lane shuffle operations available on i16
9707 // FIXME: We should teach the "split and lower" path to do something more
9708 // clever, or do it ourselves here. The optimal lowering of cross-lane
9709 // shuffles I am aware of is to swap the lanes into a copy, shuffle both the
9710 // original and the copy, and then blend to pick up the cross-lane elements.
9711 // This is four instructions with a tree height of three which is better than
9712 // the worst case for a gather-cross-scatter approach such as used in SSE2
9713 // v8i16 lowering (where we don't have blends). While for cross-lane blends it
9714 // results in a blend tree, blends are very cheap in AVX2 and newer chips. We
9715 // might also want to special case situations where we can always do a single
9716 // VPERMD to produce a non-lane-crossing shuffle.
9717 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9718 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9720 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9724 // Use dedicated unpack instructions for masks that match their pattern.
9725 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9727 if (isShuffleEquivalent(
9729 // First 128-bit lane:
9730 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9731 // Second 128-bit lane:
9732 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9733 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9734 if (isShuffleEquivalent(
9736 // First 128-bit lane:
9737 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9738 // Second 128-bit lane:
9739 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9740 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9742 if (isSingleInputShuffleMask(Mask)) {
9743 SDValue PSHUFBMask[32];
9744 for (int i = 0; i < 32; ++i)
9747 ? DAG.getUNDEF(MVT::i8)
9748 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9751 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9752 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9755 // Otherwise fall back on generic blend lowering.
9756 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9760 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9762 /// This routine either breaks down the specific type of a 256-bit x86 vector
9763 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9764 /// together based on the available instructions.
9765 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9766 MVT VT, const X86Subtarget *Subtarget,
9767 SelectionDAG &DAG) {
9769 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9770 ArrayRef<int> Mask = SVOp->getMask();
9772 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9773 // check for those subtargets here and avoid much of the subtarget querying in
9774 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9775 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9776 // floating point types there eventually, just immediately cast everything to
9777 // a float and operate entirely in that domain.
9778 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9779 int ElementBits = VT.getScalarSizeInBits();
9780 if (ElementBits < 32)
9781 // No floating point type available, decompose into 128-bit vectors.
9782 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9784 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9785 VT.getVectorNumElements());
9786 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9787 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9788 return DAG.getNode(ISD::BITCAST, DL, VT,
9789 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9792 switch (VT.SimpleTy) {
9794 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9796 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9798 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9800 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9802 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9804 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9807 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9811 /// \brief Tiny helper function to test whether a shuffle mask could be
9812 /// simplified by widening the elements being shuffled.
9813 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9814 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9815 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9816 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9817 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9823 /// \brief Top-level lowering for x86 vector shuffles.
9825 /// This handles decomposition, canonicalization, and lowering of all x86
9826 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9827 /// above in helper routines. The canonicalization attempts to widen shuffles
9828 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9829 /// s.t. only one of the two inputs needs to be tested, etc.
9830 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9831 SelectionDAG &DAG) {
9832 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9833 ArrayRef<int> Mask = SVOp->getMask();
9834 SDValue V1 = Op.getOperand(0);
9835 SDValue V2 = Op.getOperand(1);
9836 MVT VT = Op.getSimpleValueType();
9837 int NumElements = VT.getVectorNumElements();
9840 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9842 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9843 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9844 if (V1IsUndef && V2IsUndef)
9845 return DAG.getUNDEF(VT);
9847 // When we create a shuffle node we put the UNDEF node to second operand,
9848 // but in some cases the first operand may be transformed to UNDEF.
9849 // In this case we should just commute the node.
9851 return DAG.getCommutedVectorShuffle(*SVOp);
9853 // Check for non-undef masks pointing at an undef vector and make the masks
9854 // undef as well. This makes it easier to match the shuffle based solely on
9858 if (M >= NumElements) {
9859 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9860 for (int &M : NewMask)
9861 if (M >= NumElements)
9863 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9866 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9867 // lanes but wider integers. We cap this to not form integers larger than i64
9868 // but it might be interesting to form i128 integers to handle flipping the
9869 // low and high halves of AVX 256-bit vectors.
9870 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9871 canWidenShuffleElements(Mask)) {
9872 SmallVector<int, 8> NewMask;
9873 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9874 NewMask.push_back(Mask[i] != -1
9876 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9878 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9879 VT.getVectorNumElements() / 2);
9880 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9881 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9882 return DAG.getNode(ISD::BITCAST, dl, VT,
9883 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9886 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9887 for (int M : SVOp->getMask())
9890 else if (M < NumElements)
9895 // Commute the shuffle as needed such that more elements come from V1 than
9896 // V2. This allows us to match the shuffle pattern strictly on how many
9897 // elements come from V1 without handling the symmetric cases.
9898 if (NumV2Elements > NumV1Elements)
9899 return DAG.getCommutedVectorShuffle(*SVOp);
9901 // When the number of V1 and V2 elements are the same, try to minimize the
9902 // number of uses of V2 in the low half of the vector. When that is tied,
9903 // ensure that the sum of indices for V1 is equal to or lower than the sum
9905 if (NumV1Elements == NumV2Elements) {
9906 int LowV1Elements = 0, LowV2Elements = 0;
9907 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9908 if (M >= NumElements)
9912 if (LowV2Elements > LowV1Elements)
9913 return DAG.getCommutedVectorShuffle(*SVOp);
9915 int SumV1Indices = 0, SumV2Indices = 0;
9916 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9917 if (SVOp->getMask()[i] >= NumElements)
9919 else if (SVOp->getMask()[i] >= 0)
9921 if (SumV2Indices < SumV1Indices)
9922 return DAG.getCommutedVectorShuffle(*SVOp);
9925 // For each vector width, delegate to a specialized lowering routine.
9926 if (VT.getSizeInBits() == 128)
9927 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9929 if (VT.getSizeInBits() == 256)
9930 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9932 llvm_unreachable("Unimplemented!");
9936 //===----------------------------------------------------------------------===//
9937 // Legacy vector shuffle lowering
9939 // This code is the legacy code handling vector shuffles until the above
9940 // replaces its functionality and performance.
9941 //===----------------------------------------------------------------------===//
9943 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9944 bool hasInt256, unsigned *MaskOut = nullptr) {
9945 MVT EltVT = VT.getVectorElementType();
9947 // There is no blend with immediate in AVX-512.
9948 if (VT.is512BitVector())
9951 if (!hasSSE41 || EltVT == MVT::i8)
9953 if (!hasInt256 && VT == MVT::v16i16)
9956 unsigned MaskValue = 0;
9957 unsigned NumElems = VT.getVectorNumElements();
9958 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9959 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9960 unsigned NumElemsInLane = NumElems / NumLanes;
9962 // Blend for v16i16 should be symetric for the both lanes.
9963 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9965 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9966 int EltIdx = MaskVals[i];
9968 if ((EltIdx < 0 || EltIdx == (int)i) &&
9969 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9972 if (((unsigned)EltIdx == (i + NumElems)) &&
9973 (SndLaneEltIdx < 0 ||
9974 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9975 MaskValue |= (1 << i);
9981 *MaskOut = MaskValue;
9985 // Try to lower a shuffle node into a simple blend instruction.
9986 // This function assumes isBlendMask returns true for this
9987 // SuffleVectorSDNode
9988 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9990 const X86Subtarget *Subtarget,
9991 SelectionDAG &DAG) {
9992 MVT VT = SVOp->getSimpleValueType(0);
9993 MVT EltVT = VT.getVectorElementType();
9994 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9995 Subtarget->hasInt256() && "Trying to lower a "
9996 "VECTOR_SHUFFLE to a Blend but "
9997 "with the wrong mask"));
9998 SDValue V1 = SVOp->getOperand(0);
9999 SDValue V2 = SVOp->getOperand(1);
10001 unsigned NumElems = VT.getVectorNumElements();
10003 // Convert i32 vectors to floating point if it is not AVX2.
10004 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10006 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10007 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10009 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10010 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10013 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10014 DAG.getConstant(MaskValue, MVT::i32));
10015 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10018 /// In vector type \p VT, return true if the element at index \p InputIdx
10019 /// falls on a different 128-bit lane than \p OutputIdx.
10020 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10021 unsigned OutputIdx) {
10022 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10023 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10026 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10027 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10028 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10029 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10031 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10032 SelectionDAG &DAG) {
10033 MVT VT = V1.getSimpleValueType();
10034 assert(VT.is128BitVector() || VT.is256BitVector());
10036 MVT EltVT = VT.getVectorElementType();
10037 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10038 unsigned NumElts = VT.getVectorNumElements();
10040 SmallVector<SDValue, 32> PshufbMask;
10041 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10042 int InputIdx = MaskVals[OutputIdx];
10043 unsigned InputByteIdx;
10045 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10046 InputByteIdx = 0x80;
10048 // Cross lane is not allowed.
10049 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10051 InputByteIdx = InputIdx * EltSizeInBytes;
10052 // Index is an byte offset within the 128-bit lane.
10053 InputByteIdx &= 0xf;
10056 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10057 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10058 if (InputByteIdx != 0x80)
10063 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10065 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10066 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10067 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10070 // v8i16 shuffles - Prefer shuffles in the following order:
10071 // 1. [all] pshuflw, pshufhw, optional move
10072 // 2. [ssse3] 1 x pshufb
10073 // 3. [ssse3] 2 x pshufb + 1 x por
10074 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10076 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10077 SelectionDAG &DAG) {
10078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10079 SDValue V1 = SVOp->getOperand(0);
10080 SDValue V2 = SVOp->getOperand(1);
10082 SmallVector<int, 8> MaskVals;
10084 // Determine if more than 1 of the words in each of the low and high quadwords
10085 // of the result come from the same quadword of one of the two inputs. Undef
10086 // mask values count as coming from any quadword, for better codegen.
10088 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10089 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10090 unsigned LoQuad[] = { 0, 0, 0, 0 };
10091 unsigned HiQuad[] = { 0, 0, 0, 0 };
10092 // Indices of quads used.
10093 std::bitset<4> InputQuads;
10094 for (unsigned i = 0; i < 8; ++i) {
10095 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10096 int EltIdx = SVOp->getMaskElt(i);
10097 MaskVals.push_back(EltIdx);
10105 ++Quad[EltIdx / 4];
10106 InputQuads.set(EltIdx / 4);
10109 int BestLoQuad = -1;
10110 unsigned MaxQuad = 1;
10111 for (unsigned i = 0; i < 4; ++i) {
10112 if (LoQuad[i] > MaxQuad) {
10114 MaxQuad = LoQuad[i];
10118 int BestHiQuad = -1;
10120 for (unsigned i = 0; i < 4; ++i) {
10121 if (HiQuad[i] > MaxQuad) {
10123 MaxQuad = HiQuad[i];
10127 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10128 // of the two input vectors, shuffle them into one input vector so only a
10129 // single pshufb instruction is necessary. If there are more than 2 input
10130 // quads, disable the next transformation since it does not help SSSE3.
10131 bool V1Used = InputQuads[0] || InputQuads[1];
10132 bool V2Used = InputQuads[2] || InputQuads[3];
10133 if (Subtarget->hasSSSE3()) {
10134 if (InputQuads.count() == 2 && V1Used && V2Used) {
10135 BestLoQuad = InputQuads[0] ? 0 : 1;
10136 BestHiQuad = InputQuads[2] ? 2 : 3;
10138 if (InputQuads.count() > 2) {
10144 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10145 // the shuffle mask. If a quad is scored as -1, that means that it contains
10146 // words from all 4 input quadwords.
10148 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10150 BestLoQuad < 0 ? 0 : BestLoQuad,
10151 BestHiQuad < 0 ? 1 : BestHiQuad
10153 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10154 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10155 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10156 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10158 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10159 // source words for the shuffle, to aid later transformations.
10160 bool AllWordsInNewV = true;
10161 bool InOrder[2] = { true, true };
10162 for (unsigned i = 0; i != 8; ++i) {
10163 int idx = MaskVals[i];
10165 InOrder[i/4] = false;
10166 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10168 AllWordsInNewV = false;
10172 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10173 if (AllWordsInNewV) {
10174 for (int i = 0; i != 8; ++i) {
10175 int idx = MaskVals[i];
10178 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10179 if ((idx != i) && idx < 4)
10181 if ((idx != i) && idx > 3)
10190 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10191 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10192 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10193 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10194 unsigned TargetMask = 0;
10195 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10196 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10198 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10199 getShufflePSHUFLWImmediate(SVOp);
10200 V1 = NewV.getOperand(0);
10201 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10205 // Promote splats to a larger type which usually leads to more efficient code.
10206 // FIXME: Is this true if pshufb is available?
10207 if (SVOp->isSplat())
10208 return PromoteSplat(SVOp, DAG);
10210 // If we have SSSE3, and all words of the result are from 1 input vector,
10211 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10212 // is present, fall back to case 4.
10213 if (Subtarget->hasSSSE3()) {
10214 SmallVector<SDValue,16> pshufbMask;
10216 // If we have elements from both input vectors, set the high bit of the
10217 // shuffle mask element to zero out elements that come from V2 in the V1
10218 // mask, and elements that come from V1 in the V2 mask, so that the two
10219 // results can be OR'd together.
10220 bool TwoInputs = V1Used && V2Used;
10221 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10223 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10225 // Calculate the shuffle mask for the second input, shuffle it, and
10226 // OR it with the first shuffled input.
10227 CommuteVectorShuffleMask(MaskVals, 8);
10228 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10229 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10230 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10233 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10234 // and update MaskVals with new element order.
10235 std::bitset<8> InOrder;
10236 if (BestLoQuad >= 0) {
10237 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10238 for (int i = 0; i != 4; ++i) {
10239 int idx = MaskVals[i];
10242 } else if ((idx / 4) == BestLoQuad) {
10243 MaskV[i] = idx & 3;
10247 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10250 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10251 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10252 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10253 NewV.getOperand(0),
10254 getShufflePSHUFLWImmediate(SVOp), DAG);
10258 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10259 // and update MaskVals with the new element order.
10260 if (BestHiQuad >= 0) {
10261 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10262 for (unsigned i = 4; i != 8; ++i) {
10263 int idx = MaskVals[i];
10266 } else if ((idx / 4) == BestHiQuad) {
10267 MaskV[i] = (idx & 3) + 4;
10271 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10274 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10275 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10276 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10277 NewV.getOperand(0),
10278 getShufflePSHUFHWImmediate(SVOp), DAG);
10282 // In case BestHi & BestLo were both -1, which means each quadword has a word
10283 // from each of the four input quadwords, calculate the InOrder bitvector now
10284 // before falling through to the insert/extract cleanup.
10285 if (BestLoQuad == -1 && BestHiQuad == -1) {
10287 for (int i = 0; i != 8; ++i)
10288 if (MaskVals[i] < 0 || MaskVals[i] == i)
10292 // The other elements are put in the right place using pextrw and pinsrw.
10293 for (unsigned i = 0; i != 8; ++i) {
10296 int EltIdx = MaskVals[i];
10299 SDValue ExtOp = (EltIdx < 8) ?
10300 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10301 DAG.getIntPtrConstant(EltIdx)) :
10302 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10303 DAG.getIntPtrConstant(EltIdx - 8));
10304 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10305 DAG.getIntPtrConstant(i));
10310 /// \brief v16i16 shuffles
10312 /// FIXME: We only support generation of a single pshufb currently. We can
10313 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10314 /// well (e.g 2 x pshufb + 1 x por).
10316 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10318 SDValue V1 = SVOp->getOperand(0);
10319 SDValue V2 = SVOp->getOperand(1);
10322 if (V2.getOpcode() != ISD::UNDEF)
10325 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10326 return getPSHUFB(MaskVals, V1, dl, DAG);
10329 // v16i8 shuffles - Prefer shuffles in the following order:
10330 // 1. [ssse3] 1 x pshufb
10331 // 2. [ssse3] 2 x pshufb + 1 x por
10332 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10333 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10334 const X86Subtarget* Subtarget,
10335 SelectionDAG &DAG) {
10336 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10337 SDValue V1 = SVOp->getOperand(0);
10338 SDValue V2 = SVOp->getOperand(1);
10340 ArrayRef<int> MaskVals = SVOp->getMask();
10342 // Promote splats to a larger type which usually leads to more efficient code.
10343 // FIXME: Is this true if pshufb is available?
10344 if (SVOp->isSplat())
10345 return PromoteSplat(SVOp, DAG);
10347 // If we have SSSE3, case 1 is generated when all result bytes come from
10348 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10349 // present, fall back to case 3.
10351 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10352 if (Subtarget->hasSSSE3()) {
10353 SmallVector<SDValue,16> pshufbMask;
10355 // If all result elements are from one input vector, then only translate
10356 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10358 // Otherwise, we have elements from both input vectors, and must zero out
10359 // elements that come from V2 in the first mask, and V1 in the second mask
10360 // so that we can OR them together.
10361 for (unsigned i = 0; i != 16; ++i) {
10362 int EltIdx = MaskVals[i];
10363 if (EltIdx < 0 || EltIdx >= 16)
10365 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10367 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10368 DAG.getNode(ISD::BUILD_VECTOR, dl,
10369 MVT::v16i8, pshufbMask));
10371 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10372 // the 2nd operand if it's undefined or zero.
10373 if (V2.getOpcode() == ISD::UNDEF ||
10374 ISD::isBuildVectorAllZeros(V2.getNode()))
10377 // Calculate the shuffle mask for the second input, shuffle it, and
10378 // OR it with the first shuffled input.
10379 pshufbMask.clear();
10380 for (unsigned i = 0; i != 16; ++i) {
10381 int EltIdx = MaskVals[i];
10382 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10383 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10385 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10386 DAG.getNode(ISD::BUILD_VECTOR, dl,
10387 MVT::v16i8, pshufbMask));
10388 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10391 // No SSSE3 - Calculate in place words and then fix all out of place words
10392 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10393 // the 16 different words that comprise the two doublequadword input vectors.
10394 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10395 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10397 for (int i = 0; i != 8; ++i) {
10398 int Elt0 = MaskVals[i*2];
10399 int Elt1 = MaskVals[i*2+1];
10401 // This word of the result is all undef, skip it.
10402 if (Elt0 < 0 && Elt1 < 0)
10405 // This word of the result is already in the correct place, skip it.
10406 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10409 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10410 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10413 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10414 // using a single extract together, load it and store it.
10415 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10416 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10417 DAG.getIntPtrConstant(Elt1 / 2));
10418 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10419 DAG.getIntPtrConstant(i));
10423 // If Elt1 is defined, extract it from the appropriate source. If the
10424 // source byte is not also odd, shift the extracted word left 8 bits
10425 // otherwise clear the bottom 8 bits if we need to do an or.
10427 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10428 DAG.getIntPtrConstant(Elt1 / 2));
10429 if ((Elt1 & 1) == 0)
10430 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10432 TLI.getShiftAmountTy(InsElt.getValueType())));
10433 else if (Elt0 >= 0)
10434 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10435 DAG.getConstant(0xFF00, MVT::i16));
10437 // If Elt0 is defined, extract it from the appropriate source. If the
10438 // source byte is not also even, shift the extracted word right 8 bits. If
10439 // Elt1 was also defined, OR the extracted values together before
10440 // inserting them in the result.
10442 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10443 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10444 if ((Elt0 & 1) != 0)
10445 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10447 TLI.getShiftAmountTy(InsElt0.getValueType())));
10448 else if (Elt1 >= 0)
10449 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10450 DAG.getConstant(0x00FF, MVT::i16));
10451 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10454 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10455 DAG.getIntPtrConstant(i));
10457 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10460 // v32i8 shuffles - Translate to VPSHUFB if possible.
10462 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10463 const X86Subtarget *Subtarget,
10464 SelectionDAG &DAG) {
10465 MVT VT = SVOp->getSimpleValueType(0);
10466 SDValue V1 = SVOp->getOperand(0);
10467 SDValue V2 = SVOp->getOperand(1);
10469 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10471 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10472 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10473 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10475 // VPSHUFB may be generated if
10476 // (1) one of input vector is undefined or zeroinitializer.
10477 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10478 // And (2) the mask indexes don't cross the 128-bit lane.
10479 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10480 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10483 if (V1IsAllZero && !V2IsAllZero) {
10484 CommuteVectorShuffleMask(MaskVals, 32);
10487 return getPSHUFB(MaskVals, V1, dl, DAG);
10490 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10491 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10492 /// done when every pair / quad of shuffle mask elements point to elements in
10493 /// the right sequence. e.g.
10494 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10496 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10497 SelectionDAG &DAG) {
10498 MVT VT = SVOp->getSimpleValueType(0);
10500 unsigned NumElems = VT.getVectorNumElements();
10503 switch (VT.SimpleTy) {
10504 default: llvm_unreachable("Unexpected!");
10507 return SDValue(SVOp, 0);
10508 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10509 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10510 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10511 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10512 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10513 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10516 SmallVector<int, 8> MaskVec;
10517 for (unsigned i = 0; i != NumElems; i += Scale) {
10519 for (unsigned j = 0; j != Scale; ++j) {
10520 int EltIdx = SVOp->getMaskElt(i+j);
10524 StartIdx = (EltIdx / Scale);
10525 if (EltIdx != (int)(StartIdx*Scale + j))
10528 MaskVec.push_back(StartIdx);
10531 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10532 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10533 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10536 /// getVZextMovL - Return a zero-extending vector move low node.
10538 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10539 SDValue SrcOp, SelectionDAG &DAG,
10540 const X86Subtarget *Subtarget, SDLoc dl) {
10541 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10542 LoadSDNode *LD = nullptr;
10543 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10544 LD = dyn_cast<LoadSDNode>(SrcOp);
10546 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10548 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10549 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10550 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10551 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10552 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10554 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10555 return DAG.getNode(ISD::BITCAST, dl, VT,
10556 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10557 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10559 SrcOp.getOperand(0)
10565 return DAG.getNode(ISD::BITCAST, dl, VT,
10566 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10567 DAG.getNode(ISD::BITCAST, dl,
10571 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10572 /// which could not be matched by any known target speficic shuffle
10574 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10576 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10577 if (NewOp.getNode())
10580 MVT VT = SVOp->getSimpleValueType(0);
10582 unsigned NumElems = VT.getVectorNumElements();
10583 unsigned NumLaneElems = NumElems / 2;
10586 MVT EltVT = VT.getVectorElementType();
10587 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10590 SmallVector<int, 16> Mask;
10591 for (unsigned l = 0; l < 2; ++l) {
10592 // Build a shuffle mask for the output, discovering on the fly which
10593 // input vectors to use as shuffle operands (recorded in InputUsed).
10594 // If building a suitable shuffle vector proves too hard, then bail
10595 // out with UseBuildVector set.
10596 bool UseBuildVector = false;
10597 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10598 unsigned LaneStart = l * NumLaneElems;
10599 for (unsigned i = 0; i != NumLaneElems; ++i) {
10600 // The mask element. This indexes into the input.
10601 int Idx = SVOp->getMaskElt(i+LaneStart);
10603 // the mask element does not index into any input vector.
10604 Mask.push_back(-1);
10608 // The input vector this mask element indexes into.
10609 int Input = Idx / NumLaneElems;
10611 // Turn the index into an offset from the start of the input vector.
10612 Idx -= Input * NumLaneElems;
10614 // Find or create a shuffle vector operand to hold this input.
10616 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10617 if (InputUsed[OpNo] == Input)
10618 // This input vector is already an operand.
10620 if (InputUsed[OpNo] < 0) {
10621 // Create a new operand for this input vector.
10622 InputUsed[OpNo] = Input;
10627 if (OpNo >= array_lengthof(InputUsed)) {
10628 // More than two input vectors used! Give up on trying to create a
10629 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10630 UseBuildVector = true;
10634 // Add the mask index for the new shuffle vector.
10635 Mask.push_back(Idx + OpNo * NumLaneElems);
10638 if (UseBuildVector) {
10639 SmallVector<SDValue, 16> SVOps;
10640 for (unsigned i = 0; i != NumLaneElems; ++i) {
10641 // The mask element. This indexes into the input.
10642 int Idx = SVOp->getMaskElt(i+LaneStart);
10644 SVOps.push_back(DAG.getUNDEF(EltVT));
10648 // The input vector this mask element indexes into.
10649 int Input = Idx / NumElems;
10651 // Turn the index into an offset from the start of the input vector.
10652 Idx -= Input * NumElems;
10654 // Extract the vector element by hand.
10655 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10656 SVOp->getOperand(Input),
10657 DAG.getIntPtrConstant(Idx)));
10660 // Construct the output using a BUILD_VECTOR.
10661 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10662 } else if (InputUsed[0] < 0) {
10663 // No input vectors were used! The result is undefined.
10664 Output[l] = DAG.getUNDEF(NVT);
10666 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10667 (InputUsed[0] % 2) * NumLaneElems,
10669 // If only one input was used, use an undefined vector for the other.
10670 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10671 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10672 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10673 // At least one input vector was used. Create a new shuffle vector.
10674 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10680 // Concatenate the result back
10681 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10684 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10685 /// 4 elements, and match them with several different shuffle types.
10687 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10688 SDValue V1 = SVOp->getOperand(0);
10689 SDValue V2 = SVOp->getOperand(1);
10691 MVT VT = SVOp->getSimpleValueType(0);
10693 assert(VT.is128BitVector() && "Unsupported vector size");
10695 std::pair<int, int> Locs[4];
10696 int Mask1[] = { -1, -1, -1, -1 };
10697 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10699 unsigned NumHi = 0;
10700 unsigned NumLo = 0;
10701 for (unsigned i = 0; i != 4; ++i) {
10702 int Idx = PermMask[i];
10704 Locs[i] = std::make_pair(-1, -1);
10706 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10708 Locs[i] = std::make_pair(0, NumLo);
10709 Mask1[NumLo] = Idx;
10712 Locs[i] = std::make_pair(1, NumHi);
10714 Mask1[2+NumHi] = Idx;
10720 if (NumLo <= 2 && NumHi <= 2) {
10721 // If no more than two elements come from either vector. This can be
10722 // implemented with two shuffles. First shuffle gather the elements.
10723 // The second shuffle, which takes the first shuffle as both of its
10724 // vector operands, put the elements into the right order.
10725 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10727 int Mask2[] = { -1, -1, -1, -1 };
10729 for (unsigned i = 0; i != 4; ++i)
10730 if (Locs[i].first != -1) {
10731 unsigned Idx = (i < 2) ? 0 : 4;
10732 Idx += Locs[i].first * 2 + Locs[i].second;
10736 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10739 if (NumLo == 3 || NumHi == 3) {
10740 // Otherwise, we must have three elements from one vector, call it X, and
10741 // one element from the other, call it Y. First, use a shufps to build an
10742 // intermediate vector with the one element from Y and the element from X
10743 // that will be in the same half in the final destination (the indexes don't
10744 // matter). Then, use a shufps to build the final vector, taking the half
10745 // containing the element from Y from the intermediate, and the other half
10748 // Normalize it so the 3 elements come from V1.
10749 CommuteVectorShuffleMask(PermMask, 4);
10753 // Find the element from V2.
10755 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10756 int Val = PermMask[HiIndex];
10763 Mask1[0] = PermMask[HiIndex];
10765 Mask1[2] = PermMask[HiIndex^1];
10767 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10769 if (HiIndex >= 2) {
10770 Mask1[0] = PermMask[0];
10771 Mask1[1] = PermMask[1];
10772 Mask1[2] = HiIndex & 1 ? 6 : 4;
10773 Mask1[3] = HiIndex & 1 ? 4 : 6;
10774 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10777 Mask1[0] = HiIndex & 1 ? 2 : 0;
10778 Mask1[1] = HiIndex & 1 ? 0 : 2;
10779 Mask1[2] = PermMask[2];
10780 Mask1[3] = PermMask[3];
10785 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10788 // Break it into (shuffle shuffle_hi, shuffle_lo).
10789 int LoMask[] = { -1, -1, -1, -1 };
10790 int HiMask[] = { -1, -1, -1, -1 };
10792 int *MaskPtr = LoMask;
10793 unsigned MaskIdx = 0;
10794 unsigned LoIdx = 0;
10795 unsigned HiIdx = 2;
10796 for (unsigned i = 0; i != 4; ++i) {
10803 int Idx = PermMask[i];
10805 Locs[i] = std::make_pair(-1, -1);
10806 } else if (Idx < 4) {
10807 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10808 MaskPtr[LoIdx] = Idx;
10811 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10812 MaskPtr[HiIdx] = Idx;
10817 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10818 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10819 int MaskOps[] = { -1, -1, -1, -1 };
10820 for (unsigned i = 0; i != 4; ++i)
10821 if (Locs[i].first != -1)
10822 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10823 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10826 static bool MayFoldVectorLoad(SDValue V) {
10827 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10828 V = V.getOperand(0);
10830 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10831 V = V.getOperand(0);
10832 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10833 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10834 // BUILD_VECTOR (load), undef
10835 V = V.getOperand(0);
10837 return MayFoldLoad(V);
10841 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10842 MVT VT = Op.getSimpleValueType();
10844 // Canonizalize to v2f64.
10845 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10846 return DAG.getNode(ISD::BITCAST, dl, VT,
10847 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10852 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10854 SDValue V1 = Op.getOperand(0);
10855 SDValue V2 = Op.getOperand(1);
10856 MVT VT = Op.getSimpleValueType();
10858 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10860 if (HasSSE2 && VT == MVT::v2f64)
10861 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10863 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10864 return DAG.getNode(ISD::BITCAST, dl, VT,
10865 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10866 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10867 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10871 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10872 SDValue V1 = Op.getOperand(0);
10873 SDValue V2 = Op.getOperand(1);
10874 MVT VT = Op.getSimpleValueType();
10876 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10877 "unsupported shuffle type");
10879 if (V2.getOpcode() == ISD::UNDEF)
10883 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10887 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10888 SDValue V1 = Op.getOperand(0);
10889 SDValue V2 = Op.getOperand(1);
10890 MVT VT = Op.getSimpleValueType();
10891 unsigned NumElems = VT.getVectorNumElements();
10893 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10894 // operand of these instructions is only memory, so check if there's a
10895 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10897 bool CanFoldLoad = false;
10899 // Trivial case, when V2 comes from a load.
10900 if (MayFoldVectorLoad(V2))
10901 CanFoldLoad = true;
10903 // When V1 is a load, it can be folded later into a store in isel, example:
10904 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10906 // (MOVLPSmr addr:$src1, VR128:$src2)
10907 // So, recognize this potential and also use MOVLPS or MOVLPD
10908 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10909 CanFoldLoad = true;
10911 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10913 if (HasSSE2 && NumElems == 2)
10914 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10917 // If we don't care about the second element, proceed to use movss.
10918 if (SVOp->getMaskElt(1) != -1)
10919 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10922 // movl and movlp will both match v2i64, but v2i64 is never matched by
10923 // movl earlier because we make it strict to avoid messing with the movlp load
10924 // folding logic (see the code above getMOVLP call). Match it here then,
10925 // this is horrible, but will stay like this until we move all shuffle
10926 // matching to x86 specific nodes. Note that for the 1st condition all
10927 // types are matched with movsd.
10929 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10930 // as to remove this logic from here, as much as possible
10931 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10932 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10933 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10936 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10938 // Invert the operand order and use SHUFPS to match it.
10939 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10940 getShuffleSHUFImmediate(SVOp), DAG);
10943 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10944 SelectionDAG &DAG) {
10946 MVT VT = Load->getSimpleValueType(0);
10947 MVT EVT = VT.getVectorElementType();
10948 SDValue Addr = Load->getOperand(1);
10949 SDValue NewAddr = DAG.getNode(
10950 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10951 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10954 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10955 DAG.getMachineFunction().getMachineMemOperand(
10956 Load->getMemOperand(), 0, EVT.getStoreSize()));
10960 // It is only safe to call this function if isINSERTPSMask is true for
10961 // this shufflevector mask.
10962 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10963 SelectionDAG &DAG) {
10964 // Generate an insertps instruction when inserting an f32 from memory onto a
10965 // v4f32 or when copying a member from one v4f32 to another.
10966 // We also use it for transferring i32 from one register to another,
10967 // since it simply copies the same bits.
10968 // If we're transferring an i32 from memory to a specific element in a
10969 // register, we output a generic DAG that will match the PINSRD
10971 MVT VT = SVOp->getSimpleValueType(0);
10972 MVT EVT = VT.getVectorElementType();
10973 SDValue V1 = SVOp->getOperand(0);
10974 SDValue V2 = SVOp->getOperand(1);
10975 auto Mask = SVOp->getMask();
10976 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10977 "unsupported vector type for insertps/pinsrd");
10979 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10980 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10981 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10985 unsigned DestIndex;
10989 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10992 // If we have 1 element from each vector, we have to check if we're
10993 // changing V1's element's place. If so, we're done. Otherwise, we
10994 // should assume we're changing V2's element's place and behave
10996 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10997 assert(DestIndex <= INT32_MAX && "truncated destination index");
10998 if (FromV1 == FromV2 &&
10999 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11003 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11006 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11007 "More than one element from V1 and from V2, or no elements from one "
11008 "of the vectors. This case should not have returned true from "
11013 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11016 // Get an index into the source vector in the range [0,4) (the mask is
11017 // in the range [0,8) because it can address V1 and V2)
11018 unsigned SrcIndex = Mask[DestIndex] % 4;
11019 if (MayFoldLoad(From)) {
11020 // Trivial case, when From comes from a load and is only used by the
11021 // shuffle. Make it use insertps from the vector that we need from that
11024 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11025 if (!NewLoad.getNode())
11028 if (EVT == MVT::f32) {
11029 // Create this as a scalar to vector to match the instruction pattern.
11030 SDValue LoadScalarToVector =
11031 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11032 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11033 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11035 } else { // EVT == MVT::i32
11036 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11037 // instruction, to match the PINSRD instruction, which loads an i32 to a
11038 // certain vector element.
11039 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11040 DAG.getConstant(DestIndex, MVT::i32));
11044 // Vector-element-to-vector
11045 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11046 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11049 // Reduce a vector shuffle to zext.
11050 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11051 SelectionDAG &DAG) {
11052 // PMOVZX is only available from SSE41.
11053 if (!Subtarget->hasSSE41())
11056 MVT VT = Op.getSimpleValueType();
11058 // Only AVX2 support 256-bit vector integer extending.
11059 if (!Subtarget->hasInt256() && VT.is256BitVector())
11062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11064 SDValue V1 = Op.getOperand(0);
11065 SDValue V2 = Op.getOperand(1);
11066 unsigned NumElems = VT.getVectorNumElements();
11068 // Extending is an unary operation and the element type of the source vector
11069 // won't be equal to or larger than i64.
11070 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11071 VT.getVectorElementType() == MVT::i64)
11074 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11075 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11076 while ((1U << Shift) < NumElems) {
11077 if (SVOp->getMaskElt(1U << Shift) == 1)
11080 // The maximal ratio is 8, i.e. from i8 to i64.
11085 // Check the shuffle mask.
11086 unsigned Mask = (1U << Shift) - 1;
11087 for (unsigned i = 0; i != NumElems; ++i) {
11088 int EltIdx = SVOp->getMaskElt(i);
11089 if ((i & Mask) != 0 && EltIdx != -1)
11091 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11095 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11096 MVT NeVT = MVT::getIntegerVT(NBits);
11097 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11099 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11102 // Simplify the operand as it's prepared to be fed into shuffle.
11103 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11104 if (V1.getOpcode() == ISD::BITCAST &&
11105 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11106 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11107 V1.getOperand(0).getOperand(0)
11108 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11109 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11110 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11111 ConstantSDNode *CIdx =
11112 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11113 // If it's foldable, i.e. normal load with single use, we will let code
11114 // selection to fold it. Otherwise, we will short the conversion sequence.
11115 if (CIdx && CIdx->getZExtValue() == 0 &&
11116 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11117 MVT FullVT = V.getSimpleValueType();
11118 MVT V1VT = V1.getSimpleValueType();
11119 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11120 // The "ext_vec_elt" node is wider than the result node.
11121 // In this case we should extract subvector from V.
11122 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11123 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11124 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11125 FullVT.getVectorNumElements()/Ratio);
11126 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11127 DAG.getIntPtrConstant(0));
11129 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11133 return DAG.getNode(ISD::BITCAST, DL, VT,
11134 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11137 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11138 SelectionDAG &DAG) {
11139 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11140 MVT VT = Op.getSimpleValueType();
11142 SDValue V1 = Op.getOperand(0);
11143 SDValue V2 = Op.getOperand(1);
11145 if (isZeroShuffle(SVOp))
11146 return getZeroVector(VT, Subtarget, DAG, dl);
11148 // Handle splat operations
11149 if (SVOp->isSplat()) {
11150 // Use vbroadcast whenever the splat comes from a foldable load
11151 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11152 if (Broadcast.getNode())
11156 // Check integer expanding shuffles.
11157 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11158 if (NewOp.getNode())
11161 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11163 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11164 VT == MVT::v32i8) {
11165 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11166 if (NewOp.getNode())
11167 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11168 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11169 // FIXME: Figure out a cleaner way to do this.
11170 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11171 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11172 if (NewOp.getNode()) {
11173 MVT NewVT = NewOp.getSimpleValueType();
11174 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11175 NewVT, true, false))
11176 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11179 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11180 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11181 if (NewOp.getNode()) {
11182 MVT NewVT = NewOp.getSimpleValueType();
11183 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11184 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11193 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11194 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11195 SDValue V1 = Op.getOperand(0);
11196 SDValue V2 = Op.getOperand(1);
11197 MVT VT = Op.getSimpleValueType();
11199 unsigned NumElems = VT.getVectorNumElements();
11200 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11201 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11202 bool V1IsSplat = false;
11203 bool V2IsSplat = false;
11204 bool HasSSE2 = Subtarget->hasSSE2();
11205 bool HasFp256 = Subtarget->hasFp256();
11206 bool HasInt256 = Subtarget->hasInt256();
11207 MachineFunction &MF = DAG.getMachineFunction();
11208 bool OptForSize = MF.getFunction()->getAttributes().
11209 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11211 // Check if we should use the experimental vector shuffle lowering. If so,
11212 // delegate completely to that code path.
11213 if (ExperimentalVectorShuffleLowering)
11214 return lowerVectorShuffle(Op, Subtarget, DAG);
11216 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11218 if (V1IsUndef && V2IsUndef)
11219 return DAG.getUNDEF(VT);
11221 // When we create a shuffle node we put the UNDEF node to second operand,
11222 // but in some cases the first operand may be transformed to UNDEF.
11223 // In this case we should just commute the node.
11225 return DAG.getCommutedVectorShuffle(*SVOp);
11227 // Vector shuffle lowering takes 3 steps:
11229 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11230 // narrowing and commutation of operands should be handled.
11231 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11233 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11234 // so the shuffle can be broken into other shuffles and the legalizer can
11235 // try the lowering again.
11237 // The general idea is that no vector_shuffle operation should be left to
11238 // be matched during isel, all of them must be converted to a target specific
11241 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11242 // narrowing and commutation of operands should be handled. The actual code
11243 // doesn't include all of those, work in progress...
11244 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11245 if (NewOp.getNode())
11248 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11250 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11251 // unpckh_undef). Only use pshufd if speed is more important than size.
11252 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11253 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11254 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11255 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11257 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11258 V2IsUndef && MayFoldVectorLoad(V1))
11259 return getMOVDDup(Op, dl, V1, DAG);
11261 if (isMOVHLPS_v_undef_Mask(M, VT))
11262 return getMOVHighToLow(Op, dl, DAG);
11264 // Use to match splats
11265 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11266 (VT == MVT::v2f64 || VT == MVT::v2i64))
11267 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11269 if (isPSHUFDMask(M, VT)) {
11270 // The actual implementation will match the mask in the if above and then
11271 // during isel it can match several different instructions, not only pshufd
11272 // as its name says, sad but true, emulate the behavior for now...
11273 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11274 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11276 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11278 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11279 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11281 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11282 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11285 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11289 if (isPALIGNRMask(M, VT, Subtarget))
11290 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11291 getShufflePALIGNRImmediate(SVOp),
11294 if (isVALIGNMask(M, VT, Subtarget))
11295 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11296 getShuffleVALIGNImmediate(SVOp),
11299 // Check if this can be converted into a logical shift.
11300 bool isLeft = false;
11301 unsigned ShAmt = 0;
11303 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11304 if (isShift && ShVal.hasOneUse()) {
11305 // If the shifted value has multiple uses, it may be cheaper to use
11306 // v_set0 + movlhps or movhlps, etc.
11307 MVT EltVT = VT.getVectorElementType();
11308 ShAmt *= EltVT.getSizeInBits();
11309 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11312 if (isMOVLMask(M, VT)) {
11313 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11314 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11315 if (!isMOVLPMask(M, VT)) {
11316 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11317 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11319 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11320 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11324 // FIXME: fold these into legal mask.
11325 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11326 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11328 if (isMOVHLPSMask(M, VT))
11329 return getMOVHighToLow(Op, dl, DAG);
11331 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11332 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11334 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11335 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11337 if (isMOVLPMask(M, VT))
11338 return getMOVLP(Op, dl, DAG, HasSSE2);
11340 if (ShouldXformToMOVHLPS(M, VT) ||
11341 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11342 return DAG.getCommutedVectorShuffle(*SVOp);
11345 // No better options. Use a vshldq / vsrldq.
11346 MVT EltVT = VT.getVectorElementType();
11347 ShAmt *= EltVT.getSizeInBits();
11348 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11351 bool Commuted = false;
11352 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11353 // 1,1,1,1 -> v8i16 though.
11354 BitVector UndefElements;
11355 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11356 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11358 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11359 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11362 // Canonicalize the splat or undef, if present, to be on the RHS.
11363 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11364 CommuteVectorShuffleMask(M, NumElems);
11366 std::swap(V1IsSplat, V2IsSplat);
11370 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11371 // Shuffling low element of v1 into undef, just return v1.
11374 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11375 // the instruction selector will not match, so get a canonical MOVL with
11376 // swapped operands to undo the commute.
11377 return getMOVL(DAG, dl, VT, V2, V1);
11380 if (isUNPCKLMask(M, VT, HasInt256))
11381 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11383 if (isUNPCKHMask(M, VT, HasInt256))
11384 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11387 // Normalize mask so all entries that point to V2 points to its first
11388 // element then try to match unpck{h|l} again. If match, return a
11389 // new vector_shuffle with the corrected mask.p
11390 SmallVector<int, 8> NewMask(M.begin(), M.end());
11391 NormalizeMask(NewMask, NumElems);
11392 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11393 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11394 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11395 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11399 // Commute is back and try unpck* again.
11400 // FIXME: this seems wrong.
11401 CommuteVectorShuffleMask(M, NumElems);
11403 std::swap(V1IsSplat, V2IsSplat);
11405 if (isUNPCKLMask(M, VT, HasInt256))
11406 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11408 if (isUNPCKHMask(M, VT, HasInt256))
11409 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11412 // Normalize the node to match x86 shuffle ops if needed
11413 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11414 return DAG.getCommutedVectorShuffle(*SVOp);
11416 // The checks below are all present in isShuffleMaskLegal, but they are
11417 // inlined here right now to enable us to directly emit target specific
11418 // nodes, and remove one by one until they don't return Op anymore.
11420 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11421 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11422 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11423 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11426 if (isPSHUFHWMask(M, VT, HasInt256))
11427 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11428 getShufflePSHUFHWImmediate(SVOp),
11431 if (isPSHUFLWMask(M, VT, HasInt256))
11432 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11433 getShufflePSHUFLWImmediate(SVOp),
11436 unsigned MaskValue;
11437 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11439 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11441 if (isSHUFPMask(M, VT))
11442 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11443 getShuffleSHUFImmediate(SVOp), DAG);
11445 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11446 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11447 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11448 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11450 //===--------------------------------------------------------------------===//
11451 // Generate target specific nodes for 128 or 256-bit shuffles only
11452 // supported in the AVX instruction set.
11455 // Handle VMOVDDUPY permutations
11456 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11457 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11459 // Handle VPERMILPS/D* permutations
11460 if (isVPERMILPMask(M, VT)) {
11461 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11462 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11463 getShuffleSHUFImmediate(SVOp), DAG);
11464 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11465 getShuffleSHUFImmediate(SVOp), DAG);
11469 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11470 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11471 Idx*(NumElems/2), DAG, dl);
11473 // Handle VPERM2F128/VPERM2I128 permutations
11474 if (isVPERM2X128Mask(M, VT, HasFp256))
11475 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11476 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11478 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11479 return getINSERTPS(SVOp, dl, DAG);
11482 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11483 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11485 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11486 VT.is512BitVector()) {
11487 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11488 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11489 SmallVector<SDValue, 16> permclMask;
11490 for (unsigned i = 0; i != NumElems; ++i) {
11491 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11494 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11496 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11497 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11498 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11499 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11500 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11503 //===--------------------------------------------------------------------===//
11504 // Since no target specific shuffle was selected for this generic one,
11505 // lower it into other known shuffles. FIXME: this isn't true yet, but
11506 // this is the plan.
11509 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11510 if (VT == MVT::v8i16) {
11511 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11512 if (NewOp.getNode())
11516 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11517 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11518 if (NewOp.getNode())
11522 if (VT == MVT::v16i8) {
11523 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11524 if (NewOp.getNode())
11528 if (VT == MVT::v32i8) {
11529 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11530 if (NewOp.getNode())
11534 // Handle all 128-bit wide vectors with 4 elements, and match them with
11535 // several different shuffle types.
11536 if (NumElems == 4 && VT.is128BitVector())
11537 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11539 // Handle general 256-bit shuffles
11540 if (VT.is256BitVector())
11541 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11546 // This function assumes its argument is a BUILD_VECTOR of constants or
11547 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11549 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11550 unsigned &MaskValue) {
11552 unsigned NumElems = BuildVector->getNumOperands();
11553 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11554 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11555 unsigned NumElemsInLane = NumElems / NumLanes;
11557 // Blend for v16i16 should be symetric for the both lanes.
11558 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11559 SDValue EltCond = BuildVector->getOperand(i);
11560 SDValue SndLaneEltCond =
11561 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11563 int Lane1Cond = -1, Lane2Cond = -1;
11564 if (isa<ConstantSDNode>(EltCond))
11565 Lane1Cond = !isZero(EltCond);
11566 if (isa<ConstantSDNode>(SndLaneEltCond))
11567 Lane2Cond = !isZero(SndLaneEltCond);
11569 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11570 // Lane1Cond != 0, means we want the first argument.
11571 // Lane1Cond == 0, means we want the second argument.
11572 // The encoding of this argument is 0 for the first argument, 1
11573 // for the second. Therefore, invert the condition.
11574 MaskValue |= !Lane1Cond << i;
11575 else if (Lane1Cond < 0)
11576 MaskValue |= !Lane2Cond << i;
11583 // Try to lower a vselect node into a simple blend instruction.
11584 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11585 SelectionDAG &DAG) {
11586 SDValue Cond = Op.getOperand(0);
11587 SDValue LHS = Op.getOperand(1);
11588 SDValue RHS = Op.getOperand(2);
11590 MVT VT = Op.getSimpleValueType();
11591 MVT EltVT = VT.getVectorElementType();
11592 unsigned NumElems = VT.getVectorNumElements();
11594 // There is no blend with immediate in AVX-512.
11595 if (VT.is512BitVector())
11598 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11600 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11603 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11606 // Check the mask for BLEND and build the value.
11607 unsigned MaskValue = 0;
11608 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11611 // Convert i32 vectors to floating point if it is not AVX2.
11612 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11614 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11615 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11617 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11618 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11621 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11622 DAG.getConstant(MaskValue, MVT::i32));
11623 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11626 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11627 // A vselect where all conditions and data are constants can be optimized into
11628 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11629 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11630 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11631 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11634 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11635 if (BlendOp.getNode())
11638 // Some types for vselect were previously set to Expand, not Legal or
11639 // Custom. Return an empty SDValue so we fall-through to Expand, after
11640 // the Custom lowering phase.
11641 MVT VT = Op.getSimpleValueType();
11642 switch (VT.SimpleTy) {
11647 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11652 // We couldn't create a "Blend with immediate" node.
11653 // This node should still be legal, but we'll have to emit a blendv*
11658 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11659 MVT VT = Op.getSimpleValueType();
11662 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11665 if (VT.getSizeInBits() == 8) {
11666 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11667 Op.getOperand(0), Op.getOperand(1));
11668 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11669 DAG.getValueType(VT));
11670 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11673 if (VT.getSizeInBits() == 16) {
11674 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11675 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11677 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11678 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11679 DAG.getNode(ISD::BITCAST, dl,
11682 Op.getOperand(1)));
11683 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11684 Op.getOperand(0), Op.getOperand(1));
11685 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11686 DAG.getValueType(VT));
11687 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11690 if (VT == MVT::f32) {
11691 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11692 // the result back to FR32 register. It's only worth matching if the
11693 // result has a single use which is a store or a bitcast to i32. And in
11694 // the case of a store, it's not worth it if the index is a constant 0,
11695 // because a MOVSSmr can be used instead, which is smaller and faster.
11696 if (!Op.hasOneUse())
11698 SDNode *User = *Op.getNode()->use_begin();
11699 if ((User->getOpcode() != ISD::STORE ||
11700 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11701 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11702 (User->getOpcode() != ISD::BITCAST ||
11703 User->getValueType(0) != MVT::i32))
11705 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11706 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11709 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11712 if (VT == MVT::i32 || VT == MVT::i64) {
11713 // ExtractPS/pextrq works with constant index.
11714 if (isa<ConstantSDNode>(Op.getOperand(1)))
11720 /// Extract one bit from mask vector, like v16i1 or v8i1.
11721 /// AVX-512 feature.
11723 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11724 SDValue Vec = Op.getOperand(0);
11726 MVT VecVT = Vec.getSimpleValueType();
11727 SDValue Idx = Op.getOperand(1);
11728 MVT EltVT = Op.getSimpleValueType();
11730 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11732 // variable index can't be handled in mask registers,
11733 // extend vector to VR512
11734 if (!isa<ConstantSDNode>(Idx)) {
11735 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11736 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11737 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11738 ExtVT.getVectorElementType(), Ext, Idx);
11739 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11742 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11743 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11744 unsigned MaxSift = rc->getSize()*8 - 1;
11745 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11746 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11747 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11748 DAG.getConstant(MaxSift, MVT::i8));
11749 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11750 DAG.getIntPtrConstant(0));
11754 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11755 SelectionDAG &DAG) const {
11757 SDValue Vec = Op.getOperand(0);
11758 MVT VecVT = Vec.getSimpleValueType();
11759 SDValue Idx = Op.getOperand(1);
11761 if (Op.getSimpleValueType() == MVT::i1)
11762 return ExtractBitFromMaskVector(Op, DAG);
11764 if (!isa<ConstantSDNode>(Idx)) {
11765 if (VecVT.is512BitVector() ||
11766 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11767 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11770 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11771 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11772 MaskEltVT.getSizeInBits());
11774 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11775 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11776 getZeroVector(MaskVT, Subtarget, DAG, dl),
11777 Idx, DAG.getConstant(0, getPointerTy()));
11778 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11779 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11780 Perm, DAG.getConstant(0, getPointerTy()));
11785 // If this is a 256-bit vector result, first extract the 128-bit vector and
11786 // then extract the element from the 128-bit vector.
11787 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11789 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11790 // Get the 128-bit vector.
11791 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11792 MVT EltVT = VecVT.getVectorElementType();
11794 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11796 //if (IdxVal >= NumElems/2)
11797 // IdxVal -= NumElems/2;
11798 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11799 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11800 DAG.getConstant(IdxVal, MVT::i32));
11803 assert(VecVT.is128BitVector() && "Unexpected vector length");
11805 if (Subtarget->hasSSE41()) {
11806 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11811 MVT VT = Op.getSimpleValueType();
11812 // TODO: handle v16i8.
11813 if (VT.getSizeInBits() == 16) {
11814 SDValue Vec = Op.getOperand(0);
11815 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11817 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11818 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11819 DAG.getNode(ISD::BITCAST, dl,
11821 Op.getOperand(1)));
11822 // Transform it so it match pextrw which produces a 32-bit result.
11823 MVT EltVT = MVT::i32;
11824 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11825 Op.getOperand(0), Op.getOperand(1));
11826 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11827 DAG.getValueType(VT));
11828 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11831 if (VT.getSizeInBits() == 32) {
11832 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11836 // SHUFPS the element to the lowest double word, then movss.
11837 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11838 MVT VVT = Op.getOperand(0).getSimpleValueType();
11839 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11840 DAG.getUNDEF(VVT), Mask);
11841 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11842 DAG.getIntPtrConstant(0));
11845 if (VT.getSizeInBits() == 64) {
11846 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11847 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11848 // to match extract_elt for f64.
11849 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11853 // UNPCKHPD the element to the lowest double word, then movsd.
11854 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11855 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11856 int Mask[2] = { 1, -1 };
11857 MVT VVT = Op.getOperand(0).getSimpleValueType();
11858 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11859 DAG.getUNDEF(VVT), Mask);
11860 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11861 DAG.getIntPtrConstant(0));
11867 /// Insert one bit to mask vector, like v16i1 or v8i1.
11868 /// AVX-512 feature.
11870 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11872 SDValue Vec = Op.getOperand(0);
11873 SDValue Elt = Op.getOperand(1);
11874 SDValue Idx = Op.getOperand(2);
11875 MVT VecVT = Vec.getSimpleValueType();
11877 if (!isa<ConstantSDNode>(Idx)) {
11878 // Non constant index. Extend source and destination,
11879 // insert element and then truncate the result.
11880 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11881 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11882 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11883 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11884 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11885 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11888 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11889 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11890 if (Vec.getOpcode() == ISD::UNDEF)
11891 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11892 DAG.getConstant(IdxVal, MVT::i8));
11893 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11894 unsigned MaxSift = rc->getSize()*8 - 1;
11895 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11896 DAG.getConstant(MaxSift, MVT::i8));
11897 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11898 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11899 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11902 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11903 SelectionDAG &DAG) const {
11904 MVT VT = Op.getSimpleValueType();
11905 MVT EltVT = VT.getVectorElementType();
11907 if (EltVT == MVT::i1)
11908 return InsertBitToMaskVector(Op, DAG);
11911 SDValue N0 = Op.getOperand(0);
11912 SDValue N1 = Op.getOperand(1);
11913 SDValue N2 = Op.getOperand(2);
11914 if (!isa<ConstantSDNode>(N2))
11916 auto *N2C = cast<ConstantSDNode>(N2);
11917 unsigned IdxVal = N2C->getZExtValue();
11919 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11920 // into that, and then insert the subvector back into the result.
11921 if (VT.is256BitVector() || VT.is512BitVector()) {
11922 // Get the desired 128-bit vector half.
11923 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11925 // Insert the element into the desired half.
11926 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11927 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11929 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11930 DAG.getConstant(IdxIn128, MVT::i32));
11932 // Insert the changed part back to the 256-bit vector
11933 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11935 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11937 if (Subtarget->hasSSE41()) {
11938 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11940 if (VT == MVT::v8i16) {
11941 Opc = X86ISD::PINSRW;
11943 assert(VT == MVT::v16i8);
11944 Opc = X86ISD::PINSRB;
11947 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11949 if (N1.getValueType() != MVT::i32)
11950 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11951 if (N2.getValueType() != MVT::i32)
11952 N2 = DAG.getIntPtrConstant(IdxVal);
11953 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11956 if (EltVT == MVT::f32) {
11957 // Bits [7:6] of the constant are the source select. This will always be
11958 // zero here. The DAG Combiner may combine an extract_elt index into
11960 // bits. For example (insert (extract, 3), 2) could be matched by
11962 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11963 // Bits [5:4] of the constant are the destination select. This is the
11964 // value of the incoming immediate.
11965 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11966 // combine either bitwise AND or insert of float 0.0 to set these bits.
11967 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11968 // Create this as a scalar to vector..
11969 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11970 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11973 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11974 // PINSR* works with constant index.
11979 if (EltVT == MVT::i8)
11982 if (EltVT.getSizeInBits() == 16) {
11983 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11984 // as its second argument.
11985 if (N1.getValueType() != MVT::i32)
11986 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11987 if (N2.getValueType() != MVT::i32)
11988 N2 = DAG.getIntPtrConstant(IdxVal);
11989 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11994 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11996 MVT OpVT = Op.getSimpleValueType();
11998 // If this is a 256-bit vector result, first insert into a 128-bit
11999 // vector and then insert into the 256-bit vector.
12000 if (!OpVT.is128BitVector()) {
12001 // Insert into a 128-bit vector.
12002 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12003 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12004 OpVT.getVectorNumElements() / SizeFactor);
12006 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12008 // Insert the 128-bit vector.
12009 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12012 if (OpVT == MVT::v1i64 &&
12013 Op.getOperand(0).getValueType() == MVT::i64)
12014 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12016 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12017 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12018 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12019 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12022 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12023 // a simple subregister reference or explicit instructions to grab
12024 // upper bits of a vector.
12025 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12026 SelectionDAG &DAG) {
12028 SDValue In = Op.getOperand(0);
12029 SDValue Idx = Op.getOperand(1);
12030 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12031 MVT ResVT = Op.getSimpleValueType();
12032 MVT InVT = In.getSimpleValueType();
12034 if (Subtarget->hasFp256()) {
12035 if (ResVT.is128BitVector() &&
12036 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12037 isa<ConstantSDNode>(Idx)) {
12038 return Extract128BitVector(In, IdxVal, DAG, dl);
12040 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12041 isa<ConstantSDNode>(Idx)) {
12042 return Extract256BitVector(In, IdxVal, DAG, dl);
12048 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12049 // simple superregister reference or explicit instructions to insert
12050 // the upper bits of a vector.
12051 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12052 SelectionDAG &DAG) {
12053 if (Subtarget->hasFp256()) {
12054 SDLoc dl(Op.getNode());
12055 SDValue Vec = Op.getNode()->getOperand(0);
12056 SDValue SubVec = Op.getNode()->getOperand(1);
12057 SDValue Idx = Op.getNode()->getOperand(2);
12059 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12060 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12061 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12062 isa<ConstantSDNode>(Idx)) {
12063 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12064 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12067 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12068 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12069 isa<ConstantSDNode>(Idx)) {
12070 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12071 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12077 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12078 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12079 // one of the above mentioned nodes. It has to be wrapped because otherwise
12080 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12081 // be used to form addressing mode. These wrapped nodes will be selected
12084 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12085 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12087 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12088 // global base reg.
12089 unsigned char OpFlag = 0;
12090 unsigned WrapperKind = X86ISD::Wrapper;
12091 CodeModel::Model M = DAG.getTarget().getCodeModel();
12093 if (Subtarget->isPICStyleRIPRel() &&
12094 (M == CodeModel::Small || M == CodeModel::Kernel))
12095 WrapperKind = X86ISD::WrapperRIP;
12096 else if (Subtarget->isPICStyleGOT())
12097 OpFlag = X86II::MO_GOTOFF;
12098 else if (Subtarget->isPICStyleStubPIC())
12099 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12101 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12102 CP->getAlignment(),
12103 CP->getOffset(), OpFlag);
12105 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12106 // With PIC, the address is actually $g + Offset.
12108 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12109 DAG.getNode(X86ISD::GlobalBaseReg,
12110 SDLoc(), getPointerTy()),
12117 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12118 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12120 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12121 // global base reg.
12122 unsigned char OpFlag = 0;
12123 unsigned WrapperKind = X86ISD::Wrapper;
12124 CodeModel::Model M = DAG.getTarget().getCodeModel();
12126 if (Subtarget->isPICStyleRIPRel() &&
12127 (M == CodeModel::Small || M == CodeModel::Kernel))
12128 WrapperKind = X86ISD::WrapperRIP;
12129 else if (Subtarget->isPICStyleGOT())
12130 OpFlag = X86II::MO_GOTOFF;
12131 else if (Subtarget->isPICStyleStubPIC())
12132 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12134 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12137 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12139 // With PIC, the address is actually $g + Offset.
12141 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12142 DAG.getNode(X86ISD::GlobalBaseReg,
12143 SDLoc(), getPointerTy()),
12150 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12151 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12153 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12154 // global base reg.
12155 unsigned char OpFlag = 0;
12156 unsigned WrapperKind = X86ISD::Wrapper;
12157 CodeModel::Model M = DAG.getTarget().getCodeModel();
12159 if (Subtarget->isPICStyleRIPRel() &&
12160 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12161 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12162 OpFlag = X86II::MO_GOTPCREL;
12163 WrapperKind = X86ISD::WrapperRIP;
12164 } else if (Subtarget->isPICStyleGOT()) {
12165 OpFlag = X86II::MO_GOT;
12166 } else if (Subtarget->isPICStyleStubPIC()) {
12167 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12168 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12169 OpFlag = X86II::MO_DARWIN_NONLAZY;
12172 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12175 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12177 // With PIC, the address is actually $g + Offset.
12178 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12179 !Subtarget->is64Bit()) {
12180 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12181 DAG.getNode(X86ISD::GlobalBaseReg,
12182 SDLoc(), getPointerTy()),
12186 // For symbols that require a load from a stub to get the address, emit the
12188 if (isGlobalStubReference(OpFlag))
12189 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12190 MachinePointerInfo::getGOT(), false, false, false, 0);
12196 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12197 // Create the TargetBlockAddressAddress node.
12198 unsigned char OpFlags =
12199 Subtarget->ClassifyBlockAddressReference();
12200 CodeModel::Model M = DAG.getTarget().getCodeModel();
12201 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12202 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12204 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12207 if (Subtarget->isPICStyleRIPRel() &&
12208 (M == CodeModel::Small || M == CodeModel::Kernel))
12209 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12211 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12213 // With PIC, the address is actually $g + Offset.
12214 if (isGlobalRelativeToPICBase(OpFlags)) {
12215 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12216 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12224 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12225 int64_t Offset, SelectionDAG &DAG) const {
12226 // Create the TargetGlobalAddress node, folding in the constant
12227 // offset if it is legal.
12228 unsigned char OpFlags =
12229 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12230 CodeModel::Model M = DAG.getTarget().getCodeModel();
12232 if (OpFlags == X86II::MO_NO_FLAG &&
12233 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12234 // A direct static reference to a global.
12235 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12238 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12241 if (Subtarget->isPICStyleRIPRel() &&
12242 (M == CodeModel::Small || M == CodeModel::Kernel))
12243 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12245 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12247 // With PIC, the address is actually $g + Offset.
12248 if (isGlobalRelativeToPICBase(OpFlags)) {
12249 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12250 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12254 // For globals that require a load from a stub to get the address, emit the
12256 if (isGlobalStubReference(OpFlags))
12257 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12258 MachinePointerInfo::getGOT(), false, false, false, 0);
12260 // If there was a non-zero offset that we didn't fold, create an explicit
12261 // addition for it.
12263 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12264 DAG.getConstant(Offset, getPointerTy()));
12270 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12271 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12272 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12273 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12277 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12278 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12279 unsigned char OperandFlags, bool LocalDynamic = false) {
12280 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12281 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12283 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12284 GA->getValueType(0),
12288 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12292 SDValue Ops[] = { Chain, TGA, *InFlag };
12293 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12295 SDValue Ops[] = { Chain, TGA };
12296 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12299 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12300 MFI->setAdjustsStack(true);
12302 SDValue Flag = Chain.getValue(1);
12303 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12306 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12308 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12311 SDLoc dl(GA); // ? function entry point might be better
12312 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12313 DAG.getNode(X86ISD::GlobalBaseReg,
12314 SDLoc(), PtrVT), InFlag);
12315 InFlag = Chain.getValue(1);
12317 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12320 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12322 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12324 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12325 X86::RAX, X86II::MO_TLSGD);
12328 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12334 // Get the start address of the TLS block for this module.
12335 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12336 .getInfo<X86MachineFunctionInfo>();
12337 MFI->incNumLocalDynamicTLSAccesses();
12341 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12342 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12345 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12346 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12347 InFlag = Chain.getValue(1);
12348 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12349 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12352 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12356 unsigned char OperandFlags = X86II::MO_DTPOFF;
12357 unsigned WrapperKind = X86ISD::Wrapper;
12358 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12359 GA->getValueType(0),
12360 GA->getOffset(), OperandFlags);
12361 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12363 // Add x@dtpoff with the base.
12364 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12367 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12368 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12369 const EVT PtrVT, TLSModel::Model model,
12370 bool is64Bit, bool isPIC) {
12373 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12374 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12375 is64Bit ? 257 : 256));
12377 SDValue ThreadPointer =
12378 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12379 MachinePointerInfo(Ptr), false, false, false, 0);
12381 unsigned char OperandFlags = 0;
12382 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12384 unsigned WrapperKind = X86ISD::Wrapper;
12385 if (model == TLSModel::LocalExec) {
12386 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12387 } else if (model == TLSModel::InitialExec) {
12389 OperandFlags = X86II::MO_GOTTPOFF;
12390 WrapperKind = X86ISD::WrapperRIP;
12392 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12395 llvm_unreachable("Unexpected model");
12398 // emit "addl x@ntpoff,%eax" (local exec)
12399 // or "addl x@indntpoff,%eax" (initial exec)
12400 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12402 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12403 GA->getOffset(), OperandFlags);
12404 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12406 if (model == TLSModel::InitialExec) {
12407 if (isPIC && !is64Bit) {
12408 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12409 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12413 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12414 MachinePointerInfo::getGOT(), false, false, false, 0);
12417 // The address of the thread local variable is the add of the thread
12418 // pointer with the offset of the variable.
12419 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12423 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12425 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12426 const GlobalValue *GV = GA->getGlobal();
12428 if (Subtarget->isTargetELF()) {
12429 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12432 case TLSModel::GeneralDynamic:
12433 if (Subtarget->is64Bit())
12434 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12435 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12436 case TLSModel::LocalDynamic:
12437 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12438 Subtarget->is64Bit());
12439 case TLSModel::InitialExec:
12440 case TLSModel::LocalExec:
12441 return LowerToTLSExecModel(
12442 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12443 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12445 llvm_unreachable("Unknown TLS model.");
12448 if (Subtarget->isTargetDarwin()) {
12449 // Darwin only has one model of TLS. Lower to that.
12450 unsigned char OpFlag = 0;
12451 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12452 X86ISD::WrapperRIP : X86ISD::Wrapper;
12454 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12455 // global base reg.
12456 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12457 !Subtarget->is64Bit();
12459 OpFlag = X86II::MO_TLVP_PIC_BASE;
12461 OpFlag = X86II::MO_TLVP;
12463 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12464 GA->getValueType(0),
12465 GA->getOffset(), OpFlag);
12466 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12468 // With PIC32, the address is actually $g + Offset.
12470 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12471 DAG.getNode(X86ISD::GlobalBaseReg,
12472 SDLoc(), getPointerTy()),
12475 // Lowering the machine isd will make sure everything is in the right
12477 SDValue Chain = DAG.getEntryNode();
12478 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12479 SDValue Args[] = { Chain, Offset };
12480 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12482 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12483 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12484 MFI->setAdjustsStack(true);
12486 // And our return value (tls address) is in the standard call return value
12488 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12489 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12490 Chain.getValue(1));
12493 if (Subtarget->isTargetKnownWindowsMSVC() ||
12494 Subtarget->isTargetWindowsGNU()) {
12495 // Just use the implicit TLS architecture
12496 // Need to generate someting similar to:
12497 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12499 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12500 // mov rcx, qword [rdx+rcx*8]
12501 // mov eax, .tls$:tlsvar
12502 // [rax+rcx] contains the address
12503 // Windows 64bit: gs:0x58
12504 // Windows 32bit: fs:__tls_array
12507 SDValue Chain = DAG.getEntryNode();
12509 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12510 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12511 // use its literal value of 0x2C.
12512 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12513 ? Type::getInt8PtrTy(*DAG.getContext(),
12515 : Type::getInt32PtrTy(*DAG.getContext(),
12519 Subtarget->is64Bit()
12520 ? DAG.getIntPtrConstant(0x58)
12521 : (Subtarget->isTargetWindowsGNU()
12522 ? DAG.getIntPtrConstant(0x2C)
12523 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12525 SDValue ThreadPointer =
12526 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12527 MachinePointerInfo(Ptr), false, false, false, 0);
12529 // Load the _tls_index variable
12530 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12531 if (Subtarget->is64Bit())
12532 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12533 IDX, MachinePointerInfo(), MVT::i32,
12534 false, false, false, 0);
12536 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12537 false, false, false, 0);
12539 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12541 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12543 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12544 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12545 false, false, false, 0);
12547 // Get the offset of start of .tls section
12548 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12549 GA->getValueType(0),
12550 GA->getOffset(), X86II::MO_SECREL);
12551 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12553 // The address of the thread local variable is the add of the thread
12554 // pointer with the offset of the variable.
12555 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12558 llvm_unreachable("TLS not implemented for this target.");
12561 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12562 /// and take a 2 x i32 value to shift plus a shift amount.
12563 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12564 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12565 MVT VT = Op.getSimpleValueType();
12566 unsigned VTBits = VT.getSizeInBits();
12568 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12569 SDValue ShOpLo = Op.getOperand(0);
12570 SDValue ShOpHi = Op.getOperand(1);
12571 SDValue ShAmt = Op.getOperand(2);
12572 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12573 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12575 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12576 DAG.getConstant(VTBits - 1, MVT::i8));
12577 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12578 DAG.getConstant(VTBits - 1, MVT::i8))
12579 : DAG.getConstant(0, VT);
12581 SDValue Tmp2, Tmp3;
12582 if (Op.getOpcode() == ISD::SHL_PARTS) {
12583 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12584 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12586 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12587 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12590 // If the shift amount is larger or equal than the width of a part we can't
12591 // rely on the results of shld/shrd. Insert a test and select the appropriate
12592 // values for large shift amounts.
12593 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12594 DAG.getConstant(VTBits, MVT::i8));
12595 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12596 AndNode, DAG.getConstant(0, MVT::i8));
12599 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12600 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12601 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12603 if (Op.getOpcode() == ISD::SHL_PARTS) {
12604 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12605 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12607 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12608 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12611 SDValue Ops[2] = { Lo, Hi };
12612 return DAG.getMergeValues(Ops, dl);
12615 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12616 SelectionDAG &DAG) const {
12617 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12619 if (SrcVT.isVector())
12622 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12623 "Unknown SINT_TO_FP to lower!");
12625 // These are really Legal; return the operand so the caller accepts it as
12627 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12629 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12630 Subtarget->is64Bit()) {
12635 unsigned Size = SrcVT.getSizeInBits()/8;
12636 MachineFunction &MF = DAG.getMachineFunction();
12637 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12638 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12639 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12641 MachinePointerInfo::getFixedStack(SSFI),
12643 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12646 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12648 SelectionDAG &DAG) const {
12652 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12654 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12656 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12658 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12660 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12661 MachineMemOperand *MMO;
12663 int SSFI = FI->getIndex();
12665 DAG.getMachineFunction()
12666 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12667 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12669 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12670 StackSlot = StackSlot.getOperand(1);
12672 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12673 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12675 Tys, Ops, SrcVT, MMO);
12678 Chain = Result.getValue(1);
12679 SDValue InFlag = Result.getValue(2);
12681 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12682 // shouldn't be necessary except that RFP cannot be live across
12683 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12684 MachineFunction &MF = DAG.getMachineFunction();
12685 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12686 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12687 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12688 Tys = DAG.getVTList(MVT::Other);
12690 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12692 MachineMemOperand *MMO =
12693 DAG.getMachineFunction()
12694 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12695 MachineMemOperand::MOStore, SSFISize, SSFISize);
12697 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12698 Ops, Op.getValueType(), MMO);
12699 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12700 MachinePointerInfo::getFixedStack(SSFI),
12701 false, false, false, 0);
12707 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12708 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12709 SelectionDAG &DAG) const {
12710 // This algorithm is not obvious. Here it is what we're trying to output:
12713 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12714 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12716 haddpd %xmm0, %xmm0
12718 pshufd $0x4e, %xmm0, %xmm1
12724 LLVMContext *Context = DAG.getContext();
12726 // Build some magic constants.
12727 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12728 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12729 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12731 SmallVector<Constant*,2> CV1;
12733 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12734 APInt(64, 0x4330000000000000ULL))));
12736 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12737 APInt(64, 0x4530000000000000ULL))));
12738 Constant *C1 = ConstantVector::get(CV1);
12739 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12741 // Load the 64-bit value into an XMM register.
12742 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12744 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12745 MachinePointerInfo::getConstantPool(),
12746 false, false, false, 16);
12747 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12748 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12751 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12752 MachinePointerInfo::getConstantPool(),
12753 false, false, false, 16);
12754 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12755 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12758 if (Subtarget->hasSSE3()) {
12759 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12760 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12762 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12763 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12765 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12766 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12770 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12771 DAG.getIntPtrConstant(0));
12774 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12775 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12776 SelectionDAG &DAG) const {
12778 // FP constant to bias correct the final result.
12779 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12782 // Load the 32-bit value into an XMM register.
12783 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12786 // Zero out the upper parts of the register.
12787 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12789 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12790 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12791 DAG.getIntPtrConstant(0));
12793 // Or the load with the bias.
12794 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12795 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12796 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12797 MVT::v2f64, Load)),
12798 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12799 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12800 MVT::v2f64, Bias)));
12801 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12802 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12803 DAG.getIntPtrConstant(0));
12805 // Subtract the bias.
12806 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12808 // Handle final rounding.
12809 EVT DestVT = Op.getValueType();
12811 if (DestVT.bitsLT(MVT::f64))
12812 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12813 DAG.getIntPtrConstant(0));
12814 if (DestVT.bitsGT(MVT::f64))
12815 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12817 // Handle final rounding.
12821 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12822 SelectionDAG &DAG) const {
12823 SDValue N0 = Op.getOperand(0);
12824 MVT SVT = N0.getSimpleValueType();
12827 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12828 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12829 "Custom UINT_TO_FP is not supported!");
12831 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12832 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12833 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12836 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12837 SelectionDAG &DAG) const {
12838 SDValue N0 = Op.getOperand(0);
12841 if (Op.getValueType().isVector())
12842 return lowerUINT_TO_FP_vec(Op, DAG);
12844 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12845 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12846 // the optimization here.
12847 if (DAG.SignBitIsZero(N0))
12848 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12850 MVT SrcVT = N0.getSimpleValueType();
12851 MVT DstVT = Op.getSimpleValueType();
12852 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12853 return LowerUINT_TO_FP_i64(Op, DAG);
12854 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12855 return LowerUINT_TO_FP_i32(Op, DAG);
12856 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12859 // Make a 64-bit buffer, and use it to build an FILD.
12860 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12861 if (SrcVT == MVT::i32) {
12862 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12863 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12864 getPointerTy(), StackSlot, WordOff);
12865 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12866 StackSlot, MachinePointerInfo(),
12868 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12869 OffsetSlot, MachinePointerInfo(),
12871 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12875 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12876 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12877 StackSlot, MachinePointerInfo(),
12879 // For i64 source, we need to add the appropriate power of 2 if the input
12880 // was negative. This is the same as the optimization in
12881 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12882 // we must be careful to do the computation in x87 extended precision, not
12883 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12884 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12885 MachineMemOperand *MMO =
12886 DAG.getMachineFunction()
12887 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12888 MachineMemOperand::MOLoad, 8, 8);
12890 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12891 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12892 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12895 APInt FF(32, 0x5F800000ULL);
12897 // Check whether the sign bit is set.
12898 SDValue SignSet = DAG.getSetCC(dl,
12899 getSetCCResultType(*DAG.getContext(), MVT::i64),
12900 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12903 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12904 SDValue FudgePtr = DAG.getConstantPool(
12905 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12908 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12909 SDValue Zero = DAG.getIntPtrConstant(0);
12910 SDValue Four = DAG.getIntPtrConstant(4);
12911 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12913 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12915 // Load the value out, extending it from f32 to f80.
12916 // FIXME: Avoid the extend by constructing the right constant pool?
12917 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12918 FudgePtr, MachinePointerInfo::getConstantPool(),
12919 MVT::f32, false, false, false, 4);
12920 // Extend everything to 80 bits to force it to be done on x87.
12921 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12922 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12925 std::pair<SDValue,SDValue>
12926 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12927 bool IsSigned, bool IsReplace) const {
12930 EVT DstTy = Op.getValueType();
12932 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12933 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12937 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12938 DstTy.getSimpleVT() >= MVT::i16 &&
12939 "Unknown FP_TO_INT to lower!");
12941 // These are really Legal.
12942 if (DstTy == MVT::i32 &&
12943 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12944 return std::make_pair(SDValue(), SDValue());
12945 if (Subtarget->is64Bit() &&
12946 DstTy == MVT::i64 &&
12947 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12948 return std::make_pair(SDValue(), SDValue());
12950 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12951 // stack slot, or into the FTOL runtime function.
12952 MachineFunction &MF = DAG.getMachineFunction();
12953 unsigned MemSize = DstTy.getSizeInBits()/8;
12954 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12955 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12958 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12959 Opc = X86ISD::WIN_FTOL;
12961 switch (DstTy.getSimpleVT().SimpleTy) {
12962 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12963 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12964 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12965 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12968 SDValue Chain = DAG.getEntryNode();
12969 SDValue Value = Op.getOperand(0);
12970 EVT TheVT = Op.getOperand(0).getValueType();
12971 // FIXME This causes a redundant load/store if the SSE-class value is already
12972 // in memory, such as if it is on the callstack.
12973 if (isScalarFPTypeInSSEReg(TheVT)) {
12974 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12975 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12976 MachinePointerInfo::getFixedStack(SSFI),
12978 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12980 Chain, StackSlot, DAG.getValueType(TheVT)
12983 MachineMemOperand *MMO =
12984 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12985 MachineMemOperand::MOLoad, MemSize, MemSize);
12986 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12987 Chain = Value.getValue(1);
12988 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12989 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12992 MachineMemOperand *MMO =
12993 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12994 MachineMemOperand::MOStore, MemSize, MemSize);
12996 if (Opc != X86ISD::WIN_FTOL) {
12997 // Build the FP_TO_INT*_IN_MEM
12998 SDValue Ops[] = { Chain, Value, StackSlot };
12999 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13001 return std::make_pair(FIST, StackSlot);
13003 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13004 DAG.getVTList(MVT::Other, MVT::Glue),
13006 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13007 MVT::i32, ftol.getValue(1));
13008 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13009 MVT::i32, eax.getValue(2));
13010 SDValue Ops[] = { eax, edx };
13011 SDValue pair = IsReplace
13012 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13013 : DAG.getMergeValues(Ops, DL);
13014 return std::make_pair(pair, SDValue());
13018 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13019 const X86Subtarget *Subtarget) {
13020 MVT VT = Op->getSimpleValueType(0);
13021 SDValue In = Op->getOperand(0);
13022 MVT InVT = In.getSimpleValueType();
13025 // Optimize vectors in AVX mode:
13028 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13029 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13030 // Concat upper and lower parts.
13033 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13034 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13035 // Concat upper and lower parts.
13038 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13039 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13040 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13043 if (Subtarget->hasInt256())
13044 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13046 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13047 SDValue Undef = DAG.getUNDEF(InVT);
13048 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13049 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13050 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13052 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13053 VT.getVectorNumElements()/2);
13055 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13056 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13058 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13061 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13062 SelectionDAG &DAG) {
13063 MVT VT = Op->getSimpleValueType(0);
13064 SDValue In = Op->getOperand(0);
13065 MVT InVT = In.getSimpleValueType();
13067 unsigned int NumElts = VT.getVectorNumElements();
13068 if (NumElts != 8 && NumElts != 16)
13071 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13072 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13074 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13076 // Now we have only mask extension
13077 assert(InVT.getVectorElementType() == MVT::i1);
13078 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13079 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13080 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13081 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13082 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13083 MachinePointerInfo::getConstantPool(),
13084 false, false, false, Alignment);
13086 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13087 if (VT.is512BitVector())
13089 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13092 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13093 SelectionDAG &DAG) {
13094 if (Subtarget->hasFp256()) {
13095 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13103 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13104 SelectionDAG &DAG) {
13106 MVT VT = Op.getSimpleValueType();
13107 SDValue In = Op.getOperand(0);
13108 MVT SVT = In.getSimpleValueType();
13110 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13111 return LowerZERO_EXTEND_AVX512(Op, DAG);
13113 if (Subtarget->hasFp256()) {
13114 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13119 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13120 VT.getVectorNumElements() != SVT.getVectorNumElements());
13124 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13126 MVT VT = Op.getSimpleValueType();
13127 SDValue In = Op.getOperand(0);
13128 MVT InVT = In.getSimpleValueType();
13130 if (VT == MVT::i1) {
13131 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13132 "Invalid scalar TRUNCATE operation");
13133 if (InVT.getSizeInBits() >= 32)
13135 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13136 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13138 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13139 "Invalid TRUNCATE operation");
13141 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13142 if (VT.getVectorElementType().getSizeInBits() >=8)
13143 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13145 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13146 unsigned NumElts = InVT.getVectorNumElements();
13147 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13148 if (InVT.getSizeInBits() < 512) {
13149 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13150 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13154 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13155 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13156 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13157 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13158 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13159 MachinePointerInfo::getConstantPool(),
13160 false, false, false, Alignment);
13161 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13162 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13163 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13166 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13167 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13168 if (Subtarget->hasInt256()) {
13169 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13170 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13171 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13173 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13174 DAG.getIntPtrConstant(0));
13177 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13178 DAG.getIntPtrConstant(0));
13179 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13180 DAG.getIntPtrConstant(2));
13181 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13182 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13183 static const int ShufMask[] = {0, 2, 4, 6};
13184 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13187 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13188 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13189 if (Subtarget->hasInt256()) {
13190 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13192 SmallVector<SDValue,32> pshufbMask;
13193 for (unsigned i = 0; i < 2; ++i) {
13194 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13195 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13196 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13197 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13198 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13199 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13200 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13201 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13202 for (unsigned j = 0; j < 8; ++j)
13203 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13205 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13206 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13207 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13209 static const int ShufMask[] = {0, 2, -1, -1};
13210 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13212 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13213 DAG.getIntPtrConstant(0));
13214 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13217 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13218 DAG.getIntPtrConstant(0));
13220 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13221 DAG.getIntPtrConstant(4));
13223 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13224 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13226 // The PSHUFB mask:
13227 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13228 -1, -1, -1, -1, -1, -1, -1, -1};
13230 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13231 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13232 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13234 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13235 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13237 // The MOVLHPS Mask:
13238 static const int ShufMask2[] = {0, 1, 4, 5};
13239 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13240 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13243 // Handle truncation of V256 to V128 using shuffles.
13244 if (!VT.is128BitVector() || !InVT.is256BitVector())
13247 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13249 unsigned NumElems = VT.getVectorNumElements();
13250 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13252 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13253 // Prepare truncation shuffle mask
13254 for (unsigned i = 0; i != NumElems; ++i)
13255 MaskVec[i] = i * 2;
13256 SDValue V = DAG.getVectorShuffle(NVT, DL,
13257 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13258 DAG.getUNDEF(NVT), &MaskVec[0]);
13259 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13260 DAG.getIntPtrConstant(0));
13263 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13264 SelectionDAG &DAG) const {
13265 assert(!Op.getSimpleValueType().isVector());
13267 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13268 /*IsSigned=*/ true, /*IsReplace=*/ false);
13269 SDValue FIST = Vals.first, StackSlot = Vals.second;
13270 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13271 if (!FIST.getNode()) return Op;
13273 if (StackSlot.getNode())
13274 // Load the result.
13275 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13276 FIST, StackSlot, MachinePointerInfo(),
13277 false, false, false, 0);
13279 // The node is the result.
13283 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13284 SelectionDAG &DAG) const {
13285 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13286 /*IsSigned=*/ false, /*IsReplace=*/ false);
13287 SDValue FIST = Vals.first, StackSlot = Vals.second;
13288 assert(FIST.getNode() && "Unexpected failure");
13290 if (StackSlot.getNode())
13291 // Load the result.
13292 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13293 FIST, StackSlot, MachinePointerInfo(),
13294 false, false, false, 0);
13296 // The node is the result.
13300 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13302 MVT VT = Op.getSimpleValueType();
13303 SDValue In = Op.getOperand(0);
13304 MVT SVT = In.getSimpleValueType();
13306 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13308 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13309 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13310 In, DAG.getUNDEF(SVT)));
13313 // The only differences between FABS and FNEG are the mask and the logic op.
13314 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13315 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13316 "Wrong opcode for lowering FABS or FNEG.");
13318 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13320 MVT VT = Op.getSimpleValueType();
13321 // Assume scalar op for initialization; update for vector if needed.
13322 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13323 // generate a 16-byte vector constant and logic op even for the scalar case.
13324 // Using a 16-byte mask allows folding the load of the mask with
13325 // the logic op, so it can save (~4 bytes) on code size.
13327 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13328 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13329 // decide if we should generate a 16-byte constant mask when we only need 4 or
13330 // 8 bytes for the scalar case.
13331 if (VT.isVector()) {
13332 EltVT = VT.getVectorElementType();
13333 NumElts = VT.getVectorNumElements();
13336 unsigned EltBits = EltVT.getSizeInBits();
13337 LLVMContext *Context = DAG.getContext();
13338 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13340 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13341 Constant *C = ConstantInt::get(*Context, MaskElt);
13342 C = ConstantVector::getSplat(NumElts, C);
13343 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13344 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13345 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13346 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13347 MachinePointerInfo::getConstantPool(),
13348 false, false, false, Alignment);
13350 if (VT.isVector()) {
13351 // For a vector, cast operands to a vector type, perform the logic op,
13352 // and cast the result back to the original value type.
13353 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13354 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13355 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13356 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13357 return DAG.getNode(ISD::BITCAST, dl, VT,
13358 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13360 // If not vector, then scalar.
13361 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13362 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13365 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13367 LLVMContext *Context = DAG.getContext();
13368 SDValue Op0 = Op.getOperand(0);
13369 SDValue Op1 = Op.getOperand(1);
13371 MVT VT = Op.getSimpleValueType();
13372 MVT SrcVT = Op1.getSimpleValueType();
13374 // If second operand is smaller, extend it first.
13375 if (SrcVT.bitsLT(VT)) {
13376 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13379 // And if it is bigger, shrink it first.
13380 if (SrcVT.bitsGT(VT)) {
13381 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13385 // At this point the operands and the result should have the same
13386 // type, and that won't be f80 since that is not custom lowered.
13388 // First get the sign bit of second operand.
13389 SmallVector<Constant*,4> CV;
13390 if (SrcVT == MVT::f64) {
13391 const fltSemantics &Sem = APFloat::IEEEdouble;
13392 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13393 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13395 const fltSemantics &Sem = APFloat::IEEEsingle;
13396 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13397 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13398 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13399 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13401 Constant *C = ConstantVector::get(CV);
13402 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13403 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13404 MachinePointerInfo::getConstantPool(),
13405 false, false, false, 16);
13406 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13408 // Shift sign bit right or left if the two operands have different types.
13409 if (SrcVT.bitsGT(VT)) {
13410 // Op0 is MVT::f32, Op1 is MVT::f64.
13411 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13412 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13413 DAG.getConstant(32, MVT::i32));
13414 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13415 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13416 DAG.getIntPtrConstant(0));
13419 // Clear first operand sign bit.
13421 if (VT == MVT::f64) {
13422 const fltSemantics &Sem = APFloat::IEEEdouble;
13423 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13424 APInt(64, ~(1ULL << 63)))));
13425 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13427 const fltSemantics &Sem = APFloat::IEEEsingle;
13428 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13429 APInt(32, ~(1U << 31)))));
13430 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13431 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13432 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13434 C = ConstantVector::get(CV);
13435 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13436 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13437 MachinePointerInfo::getConstantPool(),
13438 false, false, false, 16);
13439 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13441 // Or the value with the sign bit.
13442 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13445 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13446 SDValue N0 = Op.getOperand(0);
13448 MVT VT = Op.getSimpleValueType();
13450 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13451 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13452 DAG.getConstant(1, VT));
13453 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13456 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13458 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13459 SelectionDAG &DAG) {
13460 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13462 if (!Subtarget->hasSSE41())
13465 if (!Op->hasOneUse())
13468 SDNode *N = Op.getNode();
13471 SmallVector<SDValue, 8> Opnds;
13472 DenseMap<SDValue, unsigned> VecInMap;
13473 SmallVector<SDValue, 8> VecIns;
13474 EVT VT = MVT::Other;
13476 // Recognize a special case where a vector is casted into wide integer to
13478 Opnds.push_back(N->getOperand(0));
13479 Opnds.push_back(N->getOperand(1));
13481 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13482 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13483 // BFS traverse all OR'd operands.
13484 if (I->getOpcode() == ISD::OR) {
13485 Opnds.push_back(I->getOperand(0));
13486 Opnds.push_back(I->getOperand(1));
13487 // Re-evaluate the number of nodes to be traversed.
13488 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13492 // Quit if a non-EXTRACT_VECTOR_ELT
13493 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13496 // Quit if without a constant index.
13497 SDValue Idx = I->getOperand(1);
13498 if (!isa<ConstantSDNode>(Idx))
13501 SDValue ExtractedFromVec = I->getOperand(0);
13502 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13503 if (M == VecInMap.end()) {
13504 VT = ExtractedFromVec.getValueType();
13505 // Quit if not 128/256-bit vector.
13506 if (!VT.is128BitVector() && !VT.is256BitVector())
13508 // Quit if not the same type.
13509 if (VecInMap.begin() != VecInMap.end() &&
13510 VT != VecInMap.begin()->first.getValueType())
13512 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13513 VecIns.push_back(ExtractedFromVec);
13515 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13518 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13519 "Not extracted from 128-/256-bit vector.");
13521 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13523 for (DenseMap<SDValue, unsigned>::const_iterator
13524 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13525 // Quit if not all elements are used.
13526 if (I->second != FullMask)
13530 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13532 // Cast all vectors into TestVT for PTEST.
13533 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13534 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13536 // If more than one full vectors are evaluated, OR them first before PTEST.
13537 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13538 // Each iteration will OR 2 nodes and append the result until there is only
13539 // 1 node left, i.e. the final OR'd value of all vectors.
13540 SDValue LHS = VecIns[Slot];
13541 SDValue RHS = VecIns[Slot + 1];
13542 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13545 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13546 VecIns.back(), VecIns.back());
13549 /// \brief return true if \c Op has a use that doesn't just read flags.
13550 static bool hasNonFlagsUse(SDValue Op) {
13551 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13553 SDNode *User = *UI;
13554 unsigned UOpNo = UI.getOperandNo();
13555 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13556 // Look pass truncate.
13557 UOpNo = User->use_begin().getOperandNo();
13558 User = *User->use_begin();
13561 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13562 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13568 /// Emit nodes that will be selected as "test Op0,Op0", or something
13570 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13571 SelectionDAG &DAG) const {
13572 if (Op.getValueType() == MVT::i1)
13573 // KORTEST instruction should be selected
13574 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13575 DAG.getConstant(0, Op.getValueType()));
13577 // CF and OF aren't always set the way we want. Determine which
13578 // of these we need.
13579 bool NeedCF = false;
13580 bool NeedOF = false;
13583 case X86::COND_A: case X86::COND_AE:
13584 case X86::COND_B: case X86::COND_BE:
13587 case X86::COND_G: case X86::COND_GE:
13588 case X86::COND_L: case X86::COND_LE:
13589 case X86::COND_O: case X86::COND_NO: {
13590 // Check if we really need to set the
13591 // Overflow flag. If NoSignedWrap is present
13592 // that is not actually needed.
13593 switch (Op->getOpcode()) {
13598 const BinaryWithFlagsSDNode *BinNode =
13599 cast<BinaryWithFlagsSDNode>(Op.getNode());
13600 if (BinNode->hasNoSignedWrap())
13610 // See if we can use the EFLAGS value from the operand instead of
13611 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13612 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13613 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13614 // Emit a CMP with 0, which is the TEST pattern.
13615 //if (Op.getValueType() == MVT::i1)
13616 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13617 // DAG.getConstant(0, MVT::i1));
13618 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13619 DAG.getConstant(0, Op.getValueType()));
13621 unsigned Opcode = 0;
13622 unsigned NumOperands = 0;
13624 // Truncate operations may prevent the merge of the SETCC instruction
13625 // and the arithmetic instruction before it. Attempt to truncate the operands
13626 // of the arithmetic instruction and use a reduced bit-width instruction.
13627 bool NeedTruncation = false;
13628 SDValue ArithOp = Op;
13629 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13630 SDValue Arith = Op->getOperand(0);
13631 // Both the trunc and the arithmetic op need to have one user each.
13632 if (Arith->hasOneUse())
13633 switch (Arith.getOpcode()) {
13640 NeedTruncation = true;
13646 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13647 // which may be the result of a CAST. We use the variable 'Op', which is the
13648 // non-casted variable when we check for possible users.
13649 switch (ArithOp.getOpcode()) {
13651 // Due to an isel shortcoming, be conservative if this add is likely to be
13652 // selected as part of a load-modify-store instruction. When the root node
13653 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13654 // uses of other nodes in the match, such as the ADD in this case. This
13655 // leads to the ADD being left around and reselected, with the result being
13656 // two adds in the output. Alas, even if none our users are stores, that
13657 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13658 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13659 // climbing the DAG back to the root, and it doesn't seem to be worth the
13661 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13662 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13663 if (UI->getOpcode() != ISD::CopyToReg &&
13664 UI->getOpcode() != ISD::SETCC &&
13665 UI->getOpcode() != ISD::STORE)
13668 if (ConstantSDNode *C =
13669 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13670 // An add of one will be selected as an INC.
13671 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13672 Opcode = X86ISD::INC;
13677 // An add of negative one (subtract of one) will be selected as a DEC.
13678 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13679 Opcode = X86ISD::DEC;
13685 // Otherwise use a regular EFLAGS-setting add.
13686 Opcode = X86ISD::ADD;
13691 // If we have a constant logical shift that's only used in a comparison
13692 // against zero turn it into an equivalent AND. This allows turning it into
13693 // a TEST instruction later.
13694 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13695 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13696 EVT VT = Op.getValueType();
13697 unsigned BitWidth = VT.getSizeInBits();
13698 unsigned ShAmt = Op->getConstantOperandVal(1);
13699 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13701 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13702 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13703 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13704 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13706 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13707 DAG.getConstant(Mask, VT));
13708 DAG.ReplaceAllUsesWith(Op, New);
13714 // If the primary and result isn't used, don't bother using X86ISD::AND,
13715 // because a TEST instruction will be better.
13716 if (!hasNonFlagsUse(Op))
13722 // Due to the ISEL shortcoming noted above, be conservative if this op is
13723 // likely to be selected as part of a load-modify-store instruction.
13724 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13725 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13726 if (UI->getOpcode() == ISD::STORE)
13729 // Otherwise use a regular EFLAGS-setting instruction.
13730 switch (ArithOp.getOpcode()) {
13731 default: llvm_unreachable("unexpected operator!");
13732 case ISD::SUB: Opcode = X86ISD::SUB; break;
13733 case ISD::XOR: Opcode = X86ISD::XOR; break;
13734 case ISD::AND: Opcode = X86ISD::AND; break;
13736 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13737 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13738 if (EFLAGS.getNode())
13741 Opcode = X86ISD::OR;
13755 return SDValue(Op.getNode(), 1);
13761 // If we found that truncation is beneficial, perform the truncation and
13763 if (NeedTruncation) {
13764 EVT VT = Op.getValueType();
13765 SDValue WideVal = Op->getOperand(0);
13766 EVT WideVT = WideVal.getValueType();
13767 unsigned ConvertedOp = 0;
13768 // Use a target machine opcode to prevent further DAGCombine
13769 // optimizations that may separate the arithmetic operations
13770 // from the setcc node.
13771 switch (WideVal.getOpcode()) {
13773 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13774 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13775 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13776 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13777 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13781 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13782 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13783 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13784 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13785 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13791 // Emit a CMP with 0, which is the TEST pattern.
13792 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13793 DAG.getConstant(0, Op.getValueType()));
13795 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13796 SmallVector<SDValue, 4> Ops;
13797 for (unsigned i = 0; i != NumOperands; ++i)
13798 Ops.push_back(Op.getOperand(i));
13800 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13801 DAG.ReplaceAllUsesWith(Op, New);
13802 return SDValue(New.getNode(), 1);
13805 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13807 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13808 SDLoc dl, SelectionDAG &DAG) const {
13809 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13810 if (C->getAPIntValue() == 0)
13811 return EmitTest(Op0, X86CC, dl, DAG);
13813 if (Op0.getValueType() == MVT::i1)
13814 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13817 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13818 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13819 // Do the comparison at i32 if it's smaller, besides the Atom case.
13820 // This avoids subregister aliasing issues. Keep the smaller reference
13821 // if we're optimizing for size, however, as that'll allow better folding
13822 // of memory operations.
13823 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13824 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13825 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13826 !Subtarget->isAtom()) {
13827 unsigned ExtendOp =
13828 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13829 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13830 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13832 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13833 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13834 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13836 return SDValue(Sub.getNode(), 1);
13838 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13841 /// Convert a comparison if required by the subtarget.
13842 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13843 SelectionDAG &DAG) const {
13844 // If the subtarget does not support the FUCOMI instruction, floating-point
13845 // comparisons have to be converted.
13846 if (Subtarget->hasCMov() ||
13847 Cmp.getOpcode() != X86ISD::CMP ||
13848 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13849 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13852 // The instruction selector will select an FUCOM instruction instead of
13853 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13854 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13855 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13857 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13858 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13859 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13860 DAG.getConstant(8, MVT::i8));
13861 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13862 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13865 static bool isAllOnes(SDValue V) {
13866 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13867 return C && C->isAllOnesValue();
13870 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13871 /// if it's possible.
13872 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13873 SDLoc dl, SelectionDAG &DAG) const {
13874 SDValue Op0 = And.getOperand(0);
13875 SDValue Op1 = And.getOperand(1);
13876 if (Op0.getOpcode() == ISD::TRUNCATE)
13877 Op0 = Op0.getOperand(0);
13878 if (Op1.getOpcode() == ISD::TRUNCATE)
13879 Op1 = Op1.getOperand(0);
13882 if (Op1.getOpcode() == ISD::SHL)
13883 std::swap(Op0, Op1);
13884 if (Op0.getOpcode() == ISD::SHL) {
13885 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13886 if (And00C->getZExtValue() == 1) {
13887 // If we looked past a truncate, check that it's only truncating away
13889 unsigned BitWidth = Op0.getValueSizeInBits();
13890 unsigned AndBitWidth = And.getValueSizeInBits();
13891 if (BitWidth > AndBitWidth) {
13893 DAG.computeKnownBits(Op0, Zeros, Ones);
13894 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13898 RHS = Op0.getOperand(1);
13900 } else if (Op1.getOpcode() == ISD::Constant) {
13901 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13902 uint64_t AndRHSVal = AndRHS->getZExtValue();
13903 SDValue AndLHS = Op0;
13905 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13906 LHS = AndLHS.getOperand(0);
13907 RHS = AndLHS.getOperand(1);
13910 // Use BT if the immediate can't be encoded in a TEST instruction.
13911 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13913 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13917 if (LHS.getNode()) {
13918 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13919 // instruction. Since the shift amount is in-range-or-undefined, we know
13920 // that doing a bittest on the i32 value is ok. We extend to i32 because
13921 // the encoding for the i16 version is larger than the i32 version.
13922 // Also promote i16 to i32 for performance / code size reason.
13923 if (LHS.getValueType() == MVT::i8 ||
13924 LHS.getValueType() == MVT::i16)
13925 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13927 // If the operand types disagree, extend the shift amount to match. Since
13928 // BT ignores high bits (like shifts) we can use anyextend.
13929 if (LHS.getValueType() != RHS.getValueType())
13930 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13932 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13933 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13934 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13935 DAG.getConstant(Cond, MVT::i8), BT);
13941 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13943 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13948 // SSE Condition code mapping:
13957 switch (SetCCOpcode) {
13958 default: llvm_unreachable("Unexpected SETCC condition");
13960 case ISD::SETEQ: SSECC = 0; break;
13962 case ISD::SETGT: Swap = true; // Fallthrough
13964 case ISD::SETOLT: SSECC = 1; break;
13966 case ISD::SETGE: Swap = true; // Fallthrough
13968 case ISD::SETOLE: SSECC = 2; break;
13969 case ISD::SETUO: SSECC = 3; break;
13971 case ISD::SETNE: SSECC = 4; break;
13972 case ISD::SETULE: Swap = true; // Fallthrough
13973 case ISD::SETUGE: SSECC = 5; break;
13974 case ISD::SETULT: Swap = true; // Fallthrough
13975 case ISD::SETUGT: SSECC = 6; break;
13976 case ISD::SETO: SSECC = 7; break;
13978 case ISD::SETONE: SSECC = 8; break;
13981 std::swap(Op0, Op1);
13986 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13987 // ones, and then concatenate the result back.
13988 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13989 MVT VT = Op.getSimpleValueType();
13991 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13992 "Unsupported value type for operation");
13994 unsigned NumElems = VT.getVectorNumElements();
13996 SDValue CC = Op.getOperand(2);
13998 // Extract the LHS vectors
13999 SDValue LHS = Op.getOperand(0);
14000 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14001 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14003 // Extract the RHS vectors
14004 SDValue RHS = Op.getOperand(1);
14005 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14006 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14008 // Issue the operation on the smaller types and concatenate the result back
14009 MVT EltVT = VT.getVectorElementType();
14010 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14011 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14012 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14013 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14016 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14017 const X86Subtarget *Subtarget) {
14018 SDValue Op0 = Op.getOperand(0);
14019 SDValue Op1 = Op.getOperand(1);
14020 SDValue CC = Op.getOperand(2);
14021 MVT VT = Op.getSimpleValueType();
14024 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14025 Op.getValueType().getScalarType() == MVT::i1 &&
14026 "Cannot set masked compare for this operation");
14028 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14030 bool Unsigned = false;
14033 switch (SetCCOpcode) {
14034 default: llvm_unreachable("Unexpected SETCC condition");
14035 case ISD::SETNE: SSECC = 4; break;
14036 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14037 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14038 case ISD::SETLT: Swap = true; //fall-through
14039 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14040 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14041 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14042 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14043 case ISD::SETULE: Unsigned = true; //fall-through
14044 case ISD::SETLE: SSECC = 2; break;
14048 std::swap(Op0, Op1);
14050 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14051 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14052 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14053 DAG.getConstant(SSECC, MVT::i8));
14056 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14057 /// operand \p Op1. If non-trivial (for example because it's not constant)
14058 /// return an empty value.
14059 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14061 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14065 MVT VT = Op1.getSimpleValueType();
14066 MVT EVT = VT.getVectorElementType();
14067 unsigned n = VT.getVectorNumElements();
14068 SmallVector<SDValue, 8> ULTOp1;
14070 for (unsigned i = 0; i < n; ++i) {
14071 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14072 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14075 // Avoid underflow.
14076 APInt Val = Elt->getAPIntValue();
14080 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14083 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14086 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14087 SelectionDAG &DAG) {
14088 SDValue Op0 = Op.getOperand(0);
14089 SDValue Op1 = Op.getOperand(1);
14090 SDValue CC = Op.getOperand(2);
14091 MVT VT = Op.getSimpleValueType();
14092 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14093 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14098 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14099 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14102 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14103 unsigned Opc = X86ISD::CMPP;
14104 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14105 assert(VT.getVectorNumElements() <= 16);
14106 Opc = X86ISD::CMPM;
14108 // In the two special cases we can't handle, emit two comparisons.
14111 unsigned CombineOpc;
14112 if (SetCCOpcode == ISD::SETUEQ) {
14113 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14115 assert(SetCCOpcode == ISD::SETONE);
14116 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14119 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14120 DAG.getConstant(CC0, MVT::i8));
14121 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14122 DAG.getConstant(CC1, MVT::i8));
14123 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14125 // Handle all other FP comparisons here.
14126 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14127 DAG.getConstant(SSECC, MVT::i8));
14130 // Break 256-bit integer vector compare into smaller ones.
14131 if (VT.is256BitVector() && !Subtarget->hasInt256())
14132 return Lower256IntVSETCC(Op, DAG);
14134 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14135 EVT OpVT = Op1.getValueType();
14136 if (Subtarget->hasAVX512()) {
14137 if (Op1.getValueType().is512BitVector() ||
14138 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14139 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14140 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14142 // In AVX-512 architecture setcc returns mask with i1 elements,
14143 // But there is no compare instruction for i8 and i16 elements in KNL.
14144 // We are not talking about 512-bit operands in this case, these
14145 // types are illegal.
14147 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14148 OpVT.getVectorElementType().getSizeInBits() >= 8))
14149 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14150 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14153 // We are handling one of the integer comparisons here. Since SSE only has
14154 // GT and EQ comparisons for integer, swapping operands and multiple
14155 // operations may be required for some comparisons.
14157 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14158 bool Subus = false;
14160 switch (SetCCOpcode) {
14161 default: llvm_unreachable("Unexpected SETCC condition");
14162 case ISD::SETNE: Invert = true;
14163 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14164 case ISD::SETLT: Swap = true;
14165 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14166 case ISD::SETGE: Swap = true;
14167 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14168 Invert = true; break;
14169 case ISD::SETULT: Swap = true;
14170 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14171 FlipSigns = true; break;
14172 case ISD::SETUGE: Swap = true;
14173 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14174 FlipSigns = true; Invert = true; break;
14177 // Special case: Use min/max operations for SETULE/SETUGE
14178 MVT VET = VT.getVectorElementType();
14180 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14181 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14184 switch (SetCCOpcode) {
14186 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14187 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14190 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14193 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14194 if (!MinMax && hasSubus) {
14195 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14197 // t = psubus Op0, Op1
14198 // pcmpeq t, <0..0>
14199 switch (SetCCOpcode) {
14201 case ISD::SETULT: {
14202 // If the comparison is against a constant we can turn this into a
14203 // setule. With psubus, setule does not require a swap. This is
14204 // beneficial because the constant in the register is no longer
14205 // destructed as the destination so it can be hoisted out of a loop.
14206 // Only do this pre-AVX since vpcmp* is no longer destructive.
14207 if (Subtarget->hasAVX())
14209 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14210 if (ULEOp1.getNode()) {
14212 Subus = true; Invert = false; Swap = false;
14216 // Psubus is better than flip-sign because it requires no inversion.
14217 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14218 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14222 Opc = X86ISD::SUBUS;
14228 std::swap(Op0, Op1);
14230 // Check that the operation in question is available (most are plain SSE2,
14231 // but PCMPGTQ and PCMPEQQ have different requirements).
14232 if (VT == MVT::v2i64) {
14233 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14234 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14236 // First cast everything to the right type.
14237 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14238 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14240 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14241 // bits of the inputs before performing those operations. The lower
14242 // compare is always unsigned.
14245 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14247 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14248 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14249 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14250 Sign, Zero, Sign, Zero);
14252 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14253 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14255 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14256 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14257 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14259 // Create masks for only the low parts/high parts of the 64 bit integers.
14260 static const int MaskHi[] = { 1, 1, 3, 3 };
14261 static const int MaskLo[] = { 0, 0, 2, 2 };
14262 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14263 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14264 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14266 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14267 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14270 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14272 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14275 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14276 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14277 // pcmpeqd + pshufd + pand.
14278 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14280 // First cast everything to the right type.
14281 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14282 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14285 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14287 // Make sure the lower and upper halves are both all-ones.
14288 static const int Mask[] = { 1, 0, 3, 2 };
14289 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14290 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14293 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14295 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14299 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14300 // bits of the inputs before performing those operations.
14302 EVT EltVT = VT.getVectorElementType();
14303 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14304 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14305 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14308 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14310 // If the logical-not of the result is required, perform that now.
14312 Result = DAG.getNOT(dl, Result, VT);
14315 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14318 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14319 getZeroVector(VT, Subtarget, DAG, dl));
14324 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14326 MVT VT = Op.getSimpleValueType();
14328 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14330 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14331 && "SetCC type must be 8-bit or 1-bit integer");
14332 SDValue Op0 = Op.getOperand(0);
14333 SDValue Op1 = Op.getOperand(1);
14335 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14337 // Optimize to BT if possible.
14338 // Lower (X & (1 << N)) == 0 to BT(X, N).
14339 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14340 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14341 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14342 Op1.getOpcode() == ISD::Constant &&
14343 cast<ConstantSDNode>(Op1)->isNullValue() &&
14344 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14345 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14346 if (NewSetCC.getNode())
14350 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14352 if (Op1.getOpcode() == ISD::Constant &&
14353 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14354 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14355 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14357 // If the input is a setcc, then reuse the input setcc or use a new one with
14358 // the inverted condition.
14359 if (Op0.getOpcode() == X86ISD::SETCC) {
14360 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14361 bool Invert = (CC == ISD::SETNE) ^
14362 cast<ConstantSDNode>(Op1)->isNullValue();
14366 CCode = X86::GetOppositeBranchCondition(CCode);
14367 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14368 DAG.getConstant(CCode, MVT::i8),
14369 Op0.getOperand(1));
14371 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14375 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14376 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14377 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14379 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14380 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14383 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14384 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14385 if (X86CC == X86::COND_INVALID)
14388 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14389 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14390 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14391 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14393 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14397 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14398 static bool isX86LogicalCmp(SDValue Op) {
14399 unsigned Opc = Op.getNode()->getOpcode();
14400 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14401 Opc == X86ISD::SAHF)
14403 if (Op.getResNo() == 1 &&
14404 (Opc == X86ISD::ADD ||
14405 Opc == X86ISD::SUB ||
14406 Opc == X86ISD::ADC ||
14407 Opc == X86ISD::SBB ||
14408 Opc == X86ISD::SMUL ||
14409 Opc == X86ISD::UMUL ||
14410 Opc == X86ISD::INC ||
14411 Opc == X86ISD::DEC ||
14412 Opc == X86ISD::OR ||
14413 Opc == X86ISD::XOR ||
14414 Opc == X86ISD::AND))
14417 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14423 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14424 if (V.getOpcode() != ISD::TRUNCATE)
14427 SDValue VOp0 = V.getOperand(0);
14428 unsigned InBits = VOp0.getValueSizeInBits();
14429 unsigned Bits = V.getValueSizeInBits();
14430 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14433 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14434 bool addTest = true;
14435 SDValue Cond = Op.getOperand(0);
14436 SDValue Op1 = Op.getOperand(1);
14437 SDValue Op2 = Op.getOperand(2);
14439 EVT VT = Op1.getValueType();
14442 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14443 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14444 // sequence later on.
14445 if (Cond.getOpcode() == ISD::SETCC &&
14446 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14447 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14448 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14449 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14450 int SSECC = translateX86FSETCC(
14451 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14454 if (Subtarget->hasAVX512()) {
14455 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14456 DAG.getConstant(SSECC, MVT::i8));
14457 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14459 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14460 DAG.getConstant(SSECC, MVT::i8));
14461 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14462 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14463 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14467 if (Cond.getOpcode() == ISD::SETCC) {
14468 SDValue NewCond = LowerSETCC(Cond, DAG);
14469 if (NewCond.getNode())
14473 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14474 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14475 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14476 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14477 if (Cond.getOpcode() == X86ISD::SETCC &&
14478 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14479 isZero(Cond.getOperand(1).getOperand(1))) {
14480 SDValue Cmp = Cond.getOperand(1);
14482 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14484 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14485 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14486 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14488 SDValue CmpOp0 = Cmp.getOperand(0);
14489 // Apply further optimizations for special cases
14490 // (select (x != 0), -1, 0) -> neg & sbb
14491 // (select (x == 0), 0, -1) -> neg & sbb
14492 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14493 if (YC->isNullValue() &&
14494 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14495 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14496 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14497 DAG.getConstant(0, CmpOp0.getValueType()),
14499 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14500 DAG.getConstant(X86::COND_B, MVT::i8),
14501 SDValue(Neg.getNode(), 1));
14505 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14506 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14507 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14509 SDValue Res = // Res = 0 or -1.
14510 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14511 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14513 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14514 Res = DAG.getNOT(DL, Res, Res.getValueType());
14516 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14517 if (!N2C || !N2C->isNullValue())
14518 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14523 // Look past (and (setcc_carry (cmp ...)), 1).
14524 if (Cond.getOpcode() == ISD::AND &&
14525 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14526 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14527 if (C && C->getAPIntValue() == 1)
14528 Cond = Cond.getOperand(0);
14531 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14532 // setting operand in place of the X86ISD::SETCC.
14533 unsigned CondOpcode = Cond.getOpcode();
14534 if (CondOpcode == X86ISD::SETCC ||
14535 CondOpcode == X86ISD::SETCC_CARRY) {
14536 CC = Cond.getOperand(0);
14538 SDValue Cmp = Cond.getOperand(1);
14539 unsigned Opc = Cmp.getOpcode();
14540 MVT VT = Op.getSimpleValueType();
14542 bool IllegalFPCMov = false;
14543 if (VT.isFloatingPoint() && !VT.isVector() &&
14544 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14545 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14547 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14548 Opc == X86ISD::BT) { // FIXME
14552 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14553 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14554 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14555 Cond.getOperand(0).getValueType() != MVT::i8)) {
14556 SDValue LHS = Cond.getOperand(0);
14557 SDValue RHS = Cond.getOperand(1);
14558 unsigned X86Opcode;
14561 switch (CondOpcode) {
14562 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14563 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14564 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14565 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14566 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14567 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14568 default: llvm_unreachable("unexpected overflowing operator");
14570 if (CondOpcode == ISD::UMULO)
14571 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14574 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14576 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14578 if (CondOpcode == ISD::UMULO)
14579 Cond = X86Op.getValue(2);
14581 Cond = X86Op.getValue(1);
14583 CC = DAG.getConstant(X86Cond, MVT::i8);
14588 // Look pass the truncate if the high bits are known zero.
14589 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14590 Cond = Cond.getOperand(0);
14592 // We know the result of AND is compared against zero. Try to match
14594 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14595 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14596 if (NewSetCC.getNode()) {
14597 CC = NewSetCC.getOperand(0);
14598 Cond = NewSetCC.getOperand(1);
14605 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14606 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14609 // a < b ? -1 : 0 -> RES = ~setcc_carry
14610 // a < b ? 0 : -1 -> RES = setcc_carry
14611 // a >= b ? -1 : 0 -> RES = setcc_carry
14612 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14613 if (Cond.getOpcode() == X86ISD::SUB) {
14614 Cond = ConvertCmpIfNecessary(Cond, DAG);
14615 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14617 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14618 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14619 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14620 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14621 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14622 return DAG.getNOT(DL, Res, Res.getValueType());
14627 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14628 // widen the cmov and push the truncate through. This avoids introducing a new
14629 // branch during isel and doesn't add any extensions.
14630 if (Op.getValueType() == MVT::i8 &&
14631 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14632 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14633 if (T1.getValueType() == T2.getValueType() &&
14634 // Blacklist CopyFromReg to avoid partial register stalls.
14635 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14636 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14637 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14638 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14642 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14643 // condition is true.
14644 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14645 SDValue Ops[] = { Op2, Op1, CC, Cond };
14646 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14649 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14650 MVT VT = Op->getSimpleValueType(0);
14651 SDValue In = Op->getOperand(0);
14652 MVT InVT = In.getSimpleValueType();
14655 unsigned int NumElts = VT.getVectorNumElements();
14656 if (NumElts != 8 && NumElts != 16)
14659 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14660 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14662 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14663 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14665 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14666 Constant *C = ConstantInt::get(*DAG.getContext(),
14667 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14669 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14670 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14671 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14672 MachinePointerInfo::getConstantPool(),
14673 false, false, false, Alignment);
14674 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14675 if (VT.is512BitVector())
14677 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14680 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14681 SelectionDAG &DAG) {
14682 MVT VT = Op->getSimpleValueType(0);
14683 SDValue In = Op->getOperand(0);
14684 MVT InVT = In.getSimpleValueType();
14687 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14688 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14690 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14691 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14692 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14695 if (Subtarget->hasInt256())
14696 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14698 // Optimize vectors in AVX mode
14699 // Sign extend v8i16 to v8i32 and
14702 // Divide input vector into two parts
14703 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14704 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14705 // concat the vectors to original VT
14707 unsigned NumElems = InVT.getVectorNumElements();
14708 SDValue Undef = DAG.getUNDEF(InVT);
14710 SmallVector<int,8> ShufMask1(NumElems, -1);
14711 for (unsigned i = 0; i != NumElems/2; ++i)
14714 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14716 SmallVector<int,8> ShufMask2(NumElems, -1);
14717 for (unsigned i = 0; i != NumElems/2; ++i)
14718 ShufMask2[i] = i + NumElems/2;
14720 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14722 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14723 VT.getVectorNumElements()/2);
14725 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14726 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14728 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14731 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14732 // may emit an illegal shuffle but the expansion is still better than scalar
14733 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14734 // we'll emit a shuffle and a arithmetic shift.
14735 // TODO: It is possible to support ZExt by zeroing the undef values during
14736 // the shuffle phase or after the shuffle.
14737 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14738 SelectionDAG &DAG) {
14739 MVT RegVT = Op.getSimpleValueType();
14740 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14741 assert(RegVT.isInteger() &&
14742 "We only custom lower integer vector sext loads.");
14744 // Nothing useful we can do without SSE2 shuffles.
14745 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14747 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14749 EVT MemVT = Ld->getMemoryVT();
14750 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14751 unsigned RegSz = RegVT.getSizeInBits();
14753 ISD::LoadExtType Ext = Ld->getExtensionType();
14755 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14756 && "Only anyext and sext are currently implemented.");
14757 assert(MemVT != RegVT && "Cannot extend to the same type");
14758 assert(MemVT.isVector() && "Must load a vector from memory");
14760 unsigned NumElems = RegVT.getVectorNumElements();
14761 unsigned MemSz = MemVT.getSizeInBits();
14762 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14764 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14765 // The only way in which we have a legal 256-bit vector result but not the
14766 // integer 256-bit operations needed to directly lower a sextload is if we
14767 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14768 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14769 // correctly legalized. We do this late to allow the canonical form of
14770 // sextload to persist throughout the rest of the DAG combiner -- it wants
14771 // to fold together any extensions it can, and so will fuse a sign_extend
14772 // of an sextload into a sextload targeting a wider value.
14774 if (MemSz == 128) {
14775 // Just switch this to a normal load.
14776 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14777 "it must be a legal 128-bit vector "
14779 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14780 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14781 Ld->isInvariant(), Ld->getAlignment());
14783 assert(MemSz < 128 &&
14784 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14785 // Do an sext load to a 128-bit vector type. We want to use the same
14786 // number of elements, but elements half as wide. This will end up being
14787 // recursively lowered by this routine, but will succeed as we definitely
14788 // have all the necessary features if we're using AVX1.
14790 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14791 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14793 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14794 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14795 Ld->isNonTemporal(), Ld->isInvariant(),
14796 Ld->getAlignment());
14799 // Replace chain users with the new chain.
14800 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14801 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14803 // Finally, do a normal sign-extend to the desired register.
14804 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14807 // All sizes must be a power of two.
14808 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14809 "Non-power-of-two elements are not custom lowered!");
14811 // Attempt to load the original value using scalar loads.
14812 // Find the largest scalar type that divides the total loaded size.
14813 MVT SclrLoadTy = MVT::i8;
14814 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14815 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14816 MVT Tp = (MVT::SimpleValueType)tp;
14817 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14822 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14823 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14825 SclrLoadTy = MVT::f64;
14827 // Calculate the number of scalar loads that we need to perform
14828 // in order to load our vector from memory.
14829 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14831 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14832 "Can only lower sext loads with a single scalar load!");
14834 unsigned loadRegZize = RegSz;
14835 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14838 // Represent our vector as a sequence of elements which are the
14839 // largest scalar that we can load.
14840 EVT LoadUnitVecVT = EVT::getVectorVT(
14841 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14843 // Represent the data using the same element type that is stored in
14844 // memory. In practice, we ''widen'' MemVT.
14846 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14847 loadRegZize / MemVT.getScalarType().getSizeInBits());
14849 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14850 "Invalid vector type");
14852 // We can't shuffle using an illegal type.
14853 assert(TLI.isTypeLegal(WideVecVT) &&
14854 "We only lower types that form legal widened vector types");
14856 SmallVector<SDValue, 8> Chains;
14857 SDValue Ptr = Ld->getBasePtr();
14858 SDValue Increment =
14859 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14860 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14862 for (unsigned i = 0; i < NumLoads; ++i) {
14863 // Perform a single load.
14864 SDValue ScalarLoad =
14865 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14866 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14867 Ld->getAlignment());
14868 Chains.push_back(ScalarLoad.getValue(1));
14869 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14870 // another round of DAGCombining.
14872 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14874 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14875 ScalarLoad, DAG.getIntPtrConstant(i));
14877 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14880 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14882 // Bitcast the loaded value to a vector of the original element type, in
14883 // the size of the target vector type.
14884 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14885 unsigned SizeRatio = RegSz / MemSz;
14887 if (Ext == ISD::SEXTLOAD) {
14888 // If we have SSE4.1, we can directly emit a VSEXT node.
14889 if (Subtarget->hasSSE41()) {
14890 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14891 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14895 // Otherwise we'll shuffle the small elements in the high bits of the
14896 // larger type and perform an arithmetic shift. If the shift is not legal
14897 // it's better to scalarize.
14898 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14899 "We can't implement a sext load without an arithmetic right shift!");
14901 // Redistribute the loaded elements into the different locations.
14902 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14903 for (unsigned i = 0; i != NumElems; ++i)
14904 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14906 SDValue Shuff = DAG.getVectorShuffle(
14907 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14909 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14911 // Build the arithmetic shift.
14912 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14913 MemVT.getVectorElementType().getSizeInBits();
14915 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14917 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14921 // Redistribute the loaded elements into the different locations.
14922 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14923 for (unsigned i = 0; i != NumElems; ++i)
14924 ShuffleVec[i * SizeRatio] = i;
14926 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14927 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14929 // Bitcast to the requested type.
14930 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14931 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14935 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14936 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14937 // from the AND / OR.
14938 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14939 Opc = Op.getOpcode();
14940 if (Opc != ISD::OR && Opc != ISD::AND)
14942 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14943 Op.getOperand(0).hasOneUse() &&
14944 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14945 Op.getOperand(1).hasOneUse());
14948 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14949 // 1 and that the SETCC node has a single use.
14950 static bool isXor1OfSetCC(SDValue Op) {
14951 if (Op.getOpcode() != ISD::XOR)
14953 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14954 if (N1C && N1C->getAPIntValue() == 1) {
14955 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14956 Op.getOperand(0).hasOneUse();
14961 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14962 bool addTest = true;
14963 SDValue Chain = Op.getOperand(0);
14964 SDValue Cond = Op.getOperand(1);
14965 SDValue Dest = Op.getOperand(2);
14968 bool Inverted = false;
14970 if (Cond.getOpcode() == ISD::SETCC) {
14971 // Check for setcc([su]{add,sub,mul}o == 0).
14972 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14973 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14974 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14975 Cond.getOperand(0).getResNo() == 1 &&
14976 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14977 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14978 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14979 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14980 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14981 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14983 Cond = Cond.getOperand(0);
14985 SDValue NewCond = LowerSETCC(Cond, DAG);
14986 if (NewCond.getNode())
14991 // FIXME: LowerXALUO doesn't handle these!!
14992 else if (Cond.getOpcode() == X86ISD::ADD ||
14993 Cond.getOpcode() == X86ISD::SUB ||
14994 Cond.getOpcode() == X86ISD::SMUL ||
14995 Cond.getOpcode() == X86ISD::UMUL)
14996 Cond = LowerXALUO(Cond, DAG);
14999 // Look pass (and (setcc_carry (cmp ...)), 1).
15000 if (Cond.getOpcode() == ISD::AND &&
15001 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15002 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15003 if (C && C->getAPIntValue() == 1)
15004 Cond = Cond.getOperand(0);
15007 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15008 // setting operand in place of the X86ISD::SETCC.
15009 unsigned CondOpcode = Cond.getOpcode();
15010 if (CondOpcode == X86ISD::SETCC ||
15011 CondOpcode == X86ISD::SETCC_CARRY) {
15012 CC = Cond.getOperand(0);
15014 SDValue Cmp = Cond.getOperand(1);
15015 unsigned Opc = Cmp.getOpcode();
15016 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15017 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15021 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15025 // These can only come from an arithmetic instruction with overflow,
15026 // e.g. SADDO, UADDO.
15027 Cond = Cond.getNode()->getOperand(1);
15033 CondOpcode = Cond.getOpcode();
15034 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15035 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15036 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15037 Cond.getOperand(0).getValueType() != MVT::i8)) {
15038 SDValue LHS = Cond.getOperand(0);
15039 SDValue RHS = Cond.getOperand(1);
15040 unsigned X86Opcode;
15043 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15044 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15046 switch (CondOpcode) {
15047 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15049 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15051 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15054 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15055 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15059 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15062 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15063 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15064 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15065 default: llvm_unreachable("unexpected overflowing operator");
15068 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15069 if (CondOpcode == ISD::UMULO)
15070 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15073 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15075 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15077 if (CondOpcode == ISD::UMULO)
15078 Cond = X86Op.getValue(2);
15080 Cond = X86Op.getValue(1);
15082 CC = DAG.getConstant(X86Cond, MVT::i8);
15086 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15087 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15088 if (CondOpc == ISD::OR) {
15089 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15090 // two branches instead of an explicit OR instruction with a
15092 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15093 isX86LogicalCmp(Cmp)) {
15094 CC = Cond.getOperand(0).getOperand(0);
15095 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15096 Chain, Dest, CC, Cmp);
15097 CC = Cond.getOperand(1).getOperand(0);
15101 } else { // ISD::AND
15102 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15103 // two branches instead of an explicit AND instruction with a
15104 // separate test. However, we only do this if this block doesn't
15105 // have a fall-through edge, because this requires an explicit
15106 // jmp when the condition is false.
15107 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15108 isX86LogicalCmp(Cmp) &&
15109 Op.getNode()->hasOneUse()) {
15110 X86::CondCode CCode =
15111 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15112 CCode = X86::GetOppositeBranchCondition(CCode);
15113 CC = DAG.getConstant(CCode, MVT::i8);
15114 SDNode *User = *Op.getNode()->use_begin();
15115 // Look for an unconditional branch following this conditional branch.
15116 // We need this because we need to reverse the successors in order
15117 // to implement FCMP_OEQ.
15118 if (User->getOpcode() == ISD::BR) {
15119 SDValue FalseBB = User->getOperand(1);
15121 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15122 assert(NewBR == User);
15126 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15127 Chain, Dest, CC, Cmp);
15128 X86::CondCode CCode =
15129 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15130 CCode = X86::GetOppositeBranchCondition(CCode);
15131 CC = DAG.getConstant(CCode, MVT::i8);
15137 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15138 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15139 // It should be transformed during dag combiner except when the condition
15140 // is set by a arithmetics with overflow node.
15141 X86::CondCode CCode =
15142 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15143 CCode = X86::GetOppositeBranchCondition(CCode);
15144 CC = DAG.getConstant(CCode, MVT::i8);
15145 Cond = Cond.getOperand(0).getOperand(1);
15147 } else if (Cond.getOpcode() == ISD::SETCC &&
15148 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15149 // For FCMP_OEQ, we can emit
15150 // two branches instead of an explicit AND instruction with a
15151 // separate test. However, we only do this if this block doesn't
15152 // have a fall-through edge, because this requires an explicit
15153 // jmp when the condition is false.
15154 if (Op.getNode()->hasOneUse()) {
15155 SDNode *User = *Op.getNode()->use_begin();
15156 // Look for an unconditional branch following this conditional branch.
15157 // We need this because we need to reverse the successors in order
15158 // to implement FCMP_OEQ.
15159 if (User->getOpcode() == ISD::BR) {
15160 SDValue FalseBB = User->getOperand(1);
15162 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15163 assert(NewBR == User);
15167 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15168 Cond.getOperand(0), Cond.getOperand(1));
15169 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15170 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15171 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15172 Chain, Dest, CC, Cmp);
15173 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15178 } else if (Cond.getOpcode() == ISD::SETCC &&
15179 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15180 // For FCMP_UNE, we can emit
15181 // two branches instead of an explicit AND instruction with a
15182 // separate test. However, we only do this if this block doesn't
15183 // have a fall-through edge, because this requires an explicit
15184 // jmp when the condition is false.
15185 if (Op.getNode()->hasOneUse()) {
15186 SDNode *User = *Op.getNode()->use_begin();
15187 // Look for an unconditional branch following this conditional branch.
15188 // We need this because we need to reverse the successors in order
15189 // to implement FCMP_UNE.
15190 if (User->getOpcode() == ISD::BR) {
15191 SDValue FalseBB = User->getOperand(1);
15193 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15194 assert(NewBR == User);
15197 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15198 Cond.getOperand(0), Cond.getOperand(1));
15199 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15200 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15201 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15202 Chain, Dest, CC, Cmp);
15203 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15213 // Look pass the truncate if the high bits are known zero.
15214 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15215 Cond = Cond.getOperand(0);
15217 // We know the result of AND is compared against zero. Try to match
15219 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15220 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15221 if (NewSetCC.getNode()) {
15222 CC = NewSetCC.getOperand(0);
15223 Cond = NewSetCC.getOperand(1);
15230 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15231 CC = DAG.getConstant(X86Cond, MVT::i8);
15232 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15234 Cond = ConvertCmpIfNecessary(Cond, DAG);
15235 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15236 Chain, Dest, CC, Cond);
15239 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15240 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15241 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15242 // that the guard pages used by the OS virtual memory manager are allocated in
15243 // correct sequence.
15245 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15246 SelectionDAG &DAG) const {
15247 MachineFunction &MF = DAG.getMachineFunction();
15248 bool SplitStack = MF.shouldSplitStack();
15249 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15255 SDNode* Node = Op.getNode();
15257 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15258 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15259 " not tell us which reg is the stack pointer!");
15260 EVT VT = Node->getValueType(0);
15261 SDValue Tmp1 = SDValue(Node, 0);
15262 SDValue Tmp2 = SDValue(Node, 1);
15263 SDValue Tmp3 = Node->getOperand(2);
15264 SDValue Chain = Tmp1.getOperand(0);
15266 // Chain the dynamic stack allocation so that it doesn't modify the stack
15267 // pointer when other instructions are using the stack.
15268 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15271 SDValue Size = Tmp2.getOperand(1);
15272 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15273 Chain = SP.getValue(1);
15274 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15275 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15276 unsigned StackAlign = TFI.getStackAlignment();
15277 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15278 if (Align > StackAlign)
15279 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15280 DAG.getConstant(-(uint64_t)Align, VT));
15281 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15283 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15284 DAG.getIntPtrConstant(0, true), SDValue(),
15287 SDValue Ops[2] = { Tmp1, Tmp2 };
15288 return DAG.getMergeValues(Ops, dl);
15292 SDValue Chain = Op.getOperand(0);
15293 SDValue Size = Op.getOperand(1);
15294 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15295 EVT VT = Op.getNode()->getValueType(0);
15297 bool Is64Bit = Subtarget->is64Bit();
15298 EVT SPTy = getPointerTy();
15301 MachineRegisterInfo &MRI = MF.getRegInfo();
15304 // The 64 bit implementation of segmented stacks needs to clobber both r10
15305 // r11. This makes it impossible to use it along with nested parameters.
15306 const Function *F = MF.getFunction();
15308 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15310 if (I->hasNestAttr())
15311 report_fatal_error("Cannot use segmented stacks with functions that "
15312 "have nested arguments.");
15315 const TargetRegisterClass *AddrRegClass =
15316 getRegClassFor(getPointerTy());
15317 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15318 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15319 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15320 DAG.getRegister(Vreg, SPTy));
15321 SDValue Ops1[2] = { Value, Chain };
15322 return DAG.getMergeValues(Ops1, dl);
15325 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15327 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15328 Flag = Chain.getValue(1);
15329 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15331 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15333 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15334 DAG.getSubtarget().getRegisterInfo());
15335 unsigned SPReg = RegInfo->getStackRegister();
15336 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15337 Chain = SP.getValue(1);
15340 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15341 DAG.getConstant(-(uint64_t)Align, VT));
15342 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15345 SDValue Ops1[2] = { SP, Chain };
15346 return DAG.getMergeValues(Ops1, dl);
15350 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15351 MachineFunction &MF = DAG.getMachineFunction();
15352 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15354 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15357 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15358 // vastart just stores the address of the VarArgsFrameIndex slot into the
15359 // memory location argument.
15360 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15362 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15363 MachinePointerInfo(SV), false, false, 0);
15367 // gp_offset (0 - 6 * 8)
15368 // fp_offset (48 - 48 + 8 * 16)
15369 // overflow_arg_area (point to parameters coming in memory).
15371 SmallVector<SDValue, 8> MemOps;
15372 SDValue FIN = Op.getOperand(1);
15374 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15375 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15377 FIN, MachinePointerInfo(SV), false, false, 0);
15378 MemOps.push_back(Store);
15381 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15382 FIN, DAG.getIntPtrConstant(4));
15383 Store = DAG.getStore(Op.getOperand(0), DL,
15384 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15386 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15387 MemOps.push_back(Store);
15389 // Store ptr to overflow_arg_area
15390 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15391 FIN, DAG.getIntPtrConstant(4));
15392 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15394 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15395 MachinePointerInfo(SV, 8),
15397 MemOps.push_back(Store);
15399 // Store ptr to reg_save_area.
15400 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15401 FIN, DAG.getIntPtrConstant(8));
15402 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15404 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15405 MachinePointerInfo(SV, 16), false, false, 0);
15406 MemOps.push_back(Store);
15407 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15410 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15411 assert(Subtarget->is64Bit() &&
15412 "LowerVAARG only handles 64-bit va_arg!");
15413 assert((Subtarget->isTargetLinux() ||
15414 Subtarget->isTargetDarwin()) &&
15415 "Unhandled target in LowerVAARG");
15416 assert(Op.getNode()->getNumOperands() == 4);
15417 SDValue Chain = Op.getOperand(0);
15418 SDValue SrcPtr = Op.getOperand(1);
15419 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15420 unsigned Align = Op.getConstantOperandVal(3);
15423 EVT ArgVT = Op.getNode()->getValueType(0);
15424 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15425 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15428 // Decide which area this value should be read from.
15429 // TODO: Implement the AMD64 ABI in its entirety. This simple
15430 // selection mechanism works only for the basic types.
15431 if (ArgVT == MVT::f80) {
15432 llvm_unreachable("va_arg for f80 not yet implemented");
15433 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15434 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15435 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15436 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15438 llvm_unreachable("Unhandled argument type in LowerVAARG");
15441 if (ArgMode == 2) {
15442 // Sanity Check: Make sure using fp_offset makes sense.
15443 assert(!DAG.getTarget().Options.UseSoftFloat &&
15444 !(DAG.getMachineFunction()
15445 .getFunction()->getAttributes()
15446 .hasAttribute(AttributeSet::FunctionIndex,
15447 Attribute::NoImplicitFloat)) &&
15448 Subtarget->hasSSE1());
15451 // Insert VAARG_64 node into the DAG
15452 // VAARG_64 returns two values: Variable Argument Address, Chain
15453 SmallVector<SDValue, 11> InstOps;
15454 InstOps.push_back(Chain);
15455 InstOps.push_back(SrcPtr);
15456 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15457 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15458 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15459 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15460 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15461 VTs, InstOps, MVT::i64,
15462 MachinePointerInfo(SV),
15464 /*Volatile=*/false,
15466 /*WriteMem=*/true);
15467 Chain = VAARG.getValue(1);
15469 // Load the next argument and return it
15470 return DAG.getLoad(ArgVT, dl,
15473 MachinePointerInfo(),
15474 false, false, false, 0);
15477 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15478 SelectionDAG &DAG) {
15479 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15480 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15481 SDValue Chain = Op.getOperand(0);
15482 SDValue DstPtr = Op.getOperand(1);
15483 SDValue SrcPtr = Op.getOperand(2);
15484 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15485 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15488 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15489 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15491 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15494 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15495 // amount is a constant. Takes immediate version of shift as input.
15496 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15497 SDValue SrcOp, uint64_t ShiftAmt,
15498 SelectionDAG &DAG) {
15499 MVT ElementType = VT.getVectorElementType();
15501 // Fold this packed shift into its first operand if ShiftAmt is 0.
15505 // Check for ShiftAmt >= element width
15506 if (ShiftAmt >= ElementType.getSizeInBits()) {
15507 if (Opc == X86ISD::VSRAI)
15508 ShiftAmt = ElementType.getSizeInBits() - 1;
15510 return DAG.getConstant(0, VT);
15513 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15514 && "Unknown target vector shift-by-constant node");
15516 // Fold this packed vector shift into a build vector if SrcOp is a
15517 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15518 if (VT == SrcOp.getSimpleValueType() &&
15519 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15520 SmallVector<SDValue, 8> Elts;
15521 unsigned NumElts = SrcOp->getNumOperands();
15522 ConstantSDNode *ND;
15525 default: llvm_unreachable(nullptr);
15526 case X86ISD::VSHLI:
15527 for (unsigned i=0; i!=NumElts; ++i) {
15528 SDValue CurrentOp = SrcOp->getOperand(i);
15529 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15530 Elts.push_back(CurrentOp);
15533 ND = cast<ConstantSDNode>(CurrentOp);
15534 const APInt &C = ND->getAPIntValue();
15535 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15538 case X86ISD::VSRLI:
15539 for (unsigned i=0; i!=NumElts; ++i) {
15540 SDValue CurrentOp = SrcOp->getOperand(i);
15541 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15542 Elts.push_back(CurrentOp);
15545 ND = cast<ConstantSDNode>(CurrentOp);
15546 const APInt &C = ND->getAPIntValue();
15547 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15550 case X86ISD::VSRAI:
15551 for (unsigned i=0; i!=NumElts; ++i) {
15552 SDValue CurrentOp = SrcOp->getOperand(i);
15553 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15554 Elts.push_back(CurrentOp);
15557 ND = cast<ConstantSDNode>(CurrentOp);
15558 const APInt &C = ND->getAPIntValue();
15559 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15564 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15567 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15570 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15571 // may or may not be a constant. Takes immediate version of shift as input.
15572 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15573 SDValue SrcOp, SDValue ShAmt,
15574 SelectionDAG &DAG) {
15575 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15577 // Catch shift-by-constant.
15578 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15579 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15580 CShAmt->getZExtValue(), DAG);
15582 // Change opcode to non-immediate version
15584 default: llvm_unreachable("Unknown target vector shift node");
15585 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15586 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15587 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15590 // Need to build a vector containing shift amount
15591 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15594 ShOps[1] = DAG.getConstant(0, MVT::i32);
15595 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15596 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15598 // The return type has to be a 128-bit type with the same element
15599 // type as the input type.
15600 MVT EltVT = VT.getVectorElementType();
15601 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15603 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15604 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15607 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15608 /// necessary casting for \p Mask when lowering masking intrinsics.
15609 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15610 SDValue PreservedSrc, SelectionDAG &DAG) {
15611 EVT VT = Op.getValueType();
15612 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15613 MVT::i1, VT.getVectorNumElements());
15616 assert(MaskVT.isSimple() && "invalid mask type");
15617 return DAG.getNode(ISD::VSELECT, dl, VT,
15618 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15622 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15624 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15625 case Intrinsic::x86_fma_vfmadd_ps:
15626 case Intrinsic::x86_fma_vfmadd_pd:
15627 case Intrinsic::x86_fma_vfmadd_ps_256:
15628 case Intrinsic::x86_fma_vfmadd_pd_256:
15629 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15630 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15631 return X86ISD::FMADD;
15632 case Intrinsic::x86_fma_vfmsub_ps:
15633 case Intrinsic::x86_fma_vfmsub_pd:
15634 case Intrinsic::x86_fma_vfmsub_ps_256:
15635 case Intrinsic::x86_fma_vfmsub_pd_256:
15636 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15637 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15638 return X86ISD::FMSUB;
15639 case Intrinsic::x86_fma_vfnmadd_ps:
15640 case Intrinsic::x86_fma_vfnmadd_pd:
15641 case Intrinsic::x86_fma_vfnmadd_ps_256:
15642 case Intrinsic::x86_fma_vfnmadd_pd_256:
15643 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15644 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15645 return X86ISD::FNMADD;
15646 case Intrinsic::x86_fma_vfnmsub_ps:
15647 case Intrinsic::x86_fma_vfnmsub_pd:
15648 case Intrinsic::x86_fma_vfnmsub_ps_256:
15649 case Intrinsic::x86_fma_vfnmsub_pd_256:
15650 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15651 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15652 return X86ISD::FNMSUB;
15653 case Intrinsic::x86_fma_vfmaddsub_ps:
15654 case Intrinsic::x86_fma_vfmaddsub_pd:
15655 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15656 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15657 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15658 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15659 return X86ISD::FMADDSUB;
15660 case Intrinsic::x86_fma_vfmsubadd_ps:
15661 case Intrinsic::x86_fma_vfmsubadd_pd:
15662 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15663 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15664 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15665 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15666 return X86ISD::FMSUBADD;
15670 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15672 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15674 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15676 switch(IntrData->Type) {
15677 case INTR_TYPE_1OP:
15678 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15679 case INTR_TYPE_2OP:
15680 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15682 case INTR_TYPE_3OP:
15683 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15684 Op.getOperand(2), Op.getOperand(3));
15685 case COMI: { // Comparison intrinsics
15686 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15687 SDValue LHS = Op.getOperand(1);
15688 SDValue RHS = Op.getOperand(2);
15689 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15690 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15691 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15692 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15693 DAG.getConstant(X86CC, MVT::i8), Cond);
15694 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15697 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15698 Op.getOperand(1), Op.getOperand(2), DAG);
15705 default: return SDValue(); // Don't custom lower most intrinsics.
15707 // Arithmetic intrinsics.
15708 case Intrinsic::x86_sse2_pmulu_dq:
15709 case Intrinsic::x86_avx2_pmulu_dq:
15710 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15711 Op.getOperand(1), Op.getOperand(2));
15713 case Intrinsic::x86_sse41_pmuldq:
15714 case Intrinsic::x86_avx2_pmul_dq:
15715 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15716 Op.getOperand(1), Op.getOperand(2));
15718 case Intrinsic::x86_sse2_pmulhu_w:
15719 case Intrinsic::x86_avx2_pmulhu_w:
15720 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15721 Op.getOperand(1), Op.getOperand(2));
15723 case Intrinsic::x86_sse2_pmulh_w:
15724 case Intrinsic::x86_avx2_pmulh_w:
15725 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15726 Op.getOperand(1), Op.getOperand(2));
15728 // SSE/SSE2/AVX floating point max/min intrinsics.
15729 case Intrinsic::x86_sse_max_ps:
15730 case Intrinsic::x86_sse2_max_pd:
15731 case Intrinsic::x86_avx_max_ps_256:
15732 case Intrinsic::x86_avx_max_pd_256:
15733 case Intrinsic::x86_sse_min_ps:
15734 case Intrinsic::x86_sse2_min_pd:
15735 case Intrinsic::x86_avx_min_ps_256:
15736 case Intrinsic::x86_avx_min_pd_256: {
15739 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15740 case Intrinsic::x86_sse_max_ps:
15741 case Intrinsic::x86_sse2_max_pd:
15742 case Intrinsic::x86_avx_max_ps_256:
15743 case Intrinsic::x86_avx_max_pd_256:
15744 Opcode = X86ISD::FMAX;
15746 case Intrinsic::x86_sse_min_ps:
15747 case Intrinsic::x86_sse2_min_pd:
15748 case Intrinsic::x86_avx_min_ps_256:
15749 case Intrinsic::x86_avx_min_pd_256:
15750 Opcode = X86ISD::FMIN;
15753 return DAG.getNode(Opcode, dl, Op.getValueType(),
15754 Op.getOperand(1), Op.getOperand(2));
15757 // AVX2 variable shift intrinsics
15758 case Intrinsic::x86_avx2_psllv_d:
15759 case Intrinsic::x86_avx2_psllv_q:
15760 case Intrinsic::x86_avx2_psllv_d_256:
15761 case Intrinsic::x86_avx2_psllv_q_256:
15762 case Intrinsic::x86_avx2_psrlv_d:
15763 case Intrinsic::x86_avx2_psrlv_q:
15764 case Intrinsic::x86_avx2_psrlv_d_256:
15765 case Intrinsic::x86_avx2_psrlv_q_256:
15766 case Intrinsic::x86_avx2_psrav_d:
15767 case Intrinsic::x86_avx2_psrav_d_256: {
15770 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15771 case Intrinsic::x86_avx2_psllv_d:
15772 case Intrinsic::x86_avx2_psllv_q:
15773 case Intrinsic::x86_avx2_psllv_d_256:
15774 case Intrinsic::x86_avx2_psllv_q_256:
15777 case Intrinsic::x86_avx2_psrlv_d:
15778 case Intrinsic::x86_avx2_psrlv_q:
15779 case Intrinsic::x86_avx2_psrlv_d_256:
15780 case Intrinsic::x86_avx2_psrlv_q_256:
15783 case Intrinsic::x86_avx2_psrav_d:
15784 case Intrinsic::x86_avx2_psrav_d_256:
15788 return DAG.getNode(Opcode, dl, Op.getValueType(),
15789 Op.getOperand(1), Op.getOperand(2));
15792 case Intrinsic::x86_sse2_packssdw_128:
15793 case Intrinsic::x86_sse2_packsswb_128:
15794 case Intrinsic::x86_avx2_packssdw:
15795 case Intrinsic::x86_avx2_packsswb:
15796 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15797 Op.getOperand(1), Op.getOperand(2));
15799 case Intrinsic::x86_sse2_packuswb_128:
15800 case Intrinsic::x86_sse41_packusdw:
15801 case Intrinsic::x86_avx2_packuswb:
15802 case Intrinsic::x86_avx2_packusdw:
15803 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15804 Op.getOperand(1), Op.getOperand(2));
15806 case Intrinsic::x86_ssse3_pshuf_b_128:
15807 case Intrinsic::x86_avx2_pshuf_b:
15808 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15809 Op.getOperand(1), Op.getOperand(2));
15811 case Intrinsic::x86_sse2_pshuf_d:
15812 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15813 Op.getOperand(1), Op.getOperand(2));
15815 case Intrinsic::x86_sse2_pshufl_w:
15816 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15817 Op.getOperand(1), Op.getOperand(2));
15819 case Intrinsic::x86_sse2_pshufh_w:
15820 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15821 Op.getOperand(1), Op.getOperand(2));
15823 case Intrinsic::x86_ssse3_psign_b_128:
15824 case Intrinsic::x86_ssse3_psign_w_128:
15825 case Intrinsic::x86_ssse3_psign_d_128:
15826 case Intrinsic::x86_avx2_psign_b:
15827 case Intrinsic::x86_avx2_psign_w:
15828 case Intrinsic::x86_avx2_psign_d:
15829 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15830 Op.getOperand(1), Op.getOperand(2));
15832 case Intrinsic::x86_avx2_permd:
15833 case Intrinsic::x86_avx2_permps:
15834 // Operands intentionally swapped. Mask is last operand to intrinsic,
15835 // but second operand for node/instruction.
15836 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15837 Op.getOperand(2), Op.getOperand(1));
15839 case Intrinsic::x86_avx512_mask_valign_q_512:
15840 case Intrinsic::x86_avx512_mask_valign_d_512:
15841 // Vector source operands are swapped.
15842 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15843 Op.getValueType(), Op.getOperand(2),
15846 Op.getOperand(5), Op.getOperand(4), DAG);
15848 // ptest and testp intrinsics. The intrinsic these come from are designed to
15849 // return an integer value, not just an instruction so lower it to the ptest
15850 // or testp pattern and a setcc for the result.
15851 case Intrinsic::x86_sse41_ptestz:
15852 case Intrinsic::x86_sse41_ptestc:
15853 case Intrinsic::x86_sse41_ptestnzc:
15854 case Intrinsic::x86_avx_ptestz_256:
15855 case Intrinsic::x86_avx_ptestc_256:
15856 case Intrinsic::x86_avx_ptestnzc_256:
15857 case Intrinsic::x86_avx_vtestz_ps:
15858 case Intrinsic::x86_avx_vtestc_ps:
15859 case Intrinsic::x86_avx_vtestnzc_ps:
15860 case Intrinsic::x86_avx_vtestz_pd:
15861 case Intrinsic::x86_avx_vtestc_pd:
15862 case Intrinsic::x86_avx_vtestnzc_pd:
15863 case Intrinsic::x86_avx_vtestz_ps_256:
15864 case Intrinsic::x86_avx_vtestc_ps_256:
15865 case Intrinsic::x86_avx_vtestnzc_ps_256:
15866 case Intrinsic::x86_avx_vtestz_pd_256:
15867 case Intrinsic::x86_avx_vtestc_pd_256:
15868 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15869 bool IsTestPacked = false;
15872 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15873 case Intrinsic::x86_avx_vtestz_ps:
15874 case Intrinsic::x86_avx_vtestz_pd:
15875 case Intrinsic::x86_avx_vtestz_ps_256:
15876 case Intrinsic::x86_avx_vtestz_pd_256:
15877 IsTestPacked = true; // Fallthrough
15878 case Intrinsic::x86_sse41_ptestz:
15879 case Intrinsic::x86_avx_ptestz_256:
15881 X86CC = X86::COND_E;
15883 case Intrinsic::x86_avx_vtestc_ps:
15884 case Intrinsic::x86_avx_vtestc_pd:
15885 case Intrinsic::x86_avx_vtestc_ps_256:
15886 case Intrinsic::x86_avx_vtestc_pd_256:
15887 IsTestPacked = true; // Fallthrough
15888 case Intrinsic::x86_sse41_ptestc:
15889 case Intrinsic::x86_avx_ptestc_256:
15891 X86CC = X86::COND_B;
15893 case Intrinsic::x86_avx_vtestnzc_ps:
15894 case Intrinsic::x86_avx_vtestnzc_pd:
15895 case Intrinsic::x86_avx_vtestnzc_ps_256:
15896 case Intrinsic::x86_avx_vtestnzc_pd_256:
15897 IsTestPacked = true; // Fallthrough
15898 case Intrinsic::x86_sse41_ptestnzc:
15899 case Intrinsic::x86_avx_ptestnzc_256:
15901 X86CC = X86::COND_A;
15905 SDValue LHS = Op.getOperand(1);
15906 SDValue RHS = Op.getOperand(2);
15907 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15908 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15909 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15910 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15911 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15913 case Intrinsic::x86_avx512_kortestz_w:
15914 case Intrinsic::x86_avx512_kortestc_w: {
15915 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15916 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15917 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15918 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15919 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15920 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15921 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15924 case Intrinsic::x86_sse42_pcmpistria128:
15925 case Intrinsic::x86_sse42_pcmpestria128:
15926 case Intrinsic::x86_sse42_pcmpistric128:
15927 case Intrinsic::x86_sse42_pcmpestric128:
15928 case Intrinsic::x86_sse42_pcmpistrio128:
15929 case Intrinsic::x86_sse42_pcmpestrio128:
15930 case Intrinsic::x86_sse42_pcmpistris128:
15931 case Intrinsic::x86_sse42_pcmpestris128:
15932 case Intrinsic::x86_sse42_pcmpistriz128:
15933 case Intrinsic::x86_sse42_pcmpestriz128: {
15937 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15938 case Intrinsic::x86_sse42_pcmpistria128:
15939 Opcode = X86ISD::PCMPISTRI;
15940 X86CC = X86::COND_A;
15942 case Intrinsic::x86_sse42_pcmpestria128:
15943 Opcode = X86ISD::PCMPESTRI;
15944 X86CC = X86::COND_A;
15946 case Intrinsic::x86_sse42_pcmpistric128:
15947 Opcode = X86ISD::PCMPISTRI;
15948 X86CC = X86::COND_B;
15950 case Intrinsic::x86_sse42_pcmpestric128:
15951 Opcode = X86ISD::PCMPESTRI;
15952 X86CC = X86::COND_B;
15954 case Intrinsic::x86_sse42_pcmpistrio128:
15955 Opcode = X86ISD::PCMPISTRI;
15956 X86CC = X86::COND_O;
15958 case Intrinsic::x86_sse42_pcmpestrio128:
15959 Opcode = X86ISD::PCMPESTRI;
15960 X86CC = X86::COND_O;
15962 case Intrinsic::x86_sse42_pcmpistris128:
15963 Opcode = X86ISD::PCMPISTRI;
15964 X86CC = X86::COND_S;
15966 case Intrinsic::x86_sse42_pcmpestris128:
15967 Opcode = X86ISD::PCMPESTRI;
15968 X86CC = X86::COND_S;
15970 case Intrinsic::x86_sse42_pcmpistriz128:
15971 Opcode = X86ISD::PCMPISTRI;
15972 X86CC = X86::COND_E;
15974 case Intrinsic::x86_sse42_pcmpestriz128:
15975 Opcode = X86ISD::PCMPESTRI;
15976 X86CC = X86::COND_E;
15979 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15980 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15981 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15982 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15983 DAG.getConstant(X86CC, MVT::i8),
15984 SDValue(PCMP.getNode(), 1));
15985 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15988 case Intrinsic::x86_sse42_pcmpistri128:
15989 case Intrinsic::x86_sse42_pcmpestri128: {
15991 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15992 Opcode = X86ISD::PCMPISTRI;
15994 Opcode = X86ISD::PCMPESTRI;
15996 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15997 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15998 return DAG.getNode(Opcode, dl, VTs, NewOps);
16001 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16002 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16003 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16004 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16005 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16006 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16007 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16008 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16009 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16010 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16011 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16012 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16013 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16014 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16015 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16016 dl, Op.getValueType(),
16020 Op.getOperand(4), Op.getOperand(1), DAG);
16025 case Intrinsic::x86_fma_vfmadd_ps:
16026 case Intrinsic::x86_fma_vfmadd_pd:
16027 case Intrinsic::x86_fma_vfmsub_ps:
16028 case Intrinsic::x86_fma_vfmsub_pd:
16029 case Intrinsic::x86_fma_vfnmadd_ps:
16030 case Intrinsic::x86_fma_vfnmadd_pd:
16031 case Intrinsic::x86_fma_vfnmsub_ps:
16032 case Intrinsic::x86_fma_vfnmsub_pd:
16033 case Intrinsic::x86_fma_vfmaddsub_ps:
16034 case Intrinsic::x86_fma_vfmaddsub_pd:
16035 case Intrinsic::x86_fma_vfmsubadd_ps:
16036 case Intrinsic::x86_fma_vfmsubadd_pd:
16037 case Intrinsic::x86_fma_vfmadd_ps_256:
16038 case Intrinsic::x86_fma_vfmadd_pd_256:
16039 case Intrinsic::x86_fma_vfmsub_ps_256:
16040 case Intrinsic::x86_fma_vfmsub_pd_256:
16041 case Intrinsic::x86_fma_vfnmadd_ps_256:
16042 case Intrinsic::x86_fma_vfnmadd_pd_256:
16043 case Intrinsic::x86_fma_vfnmsub_ps_256:
16044 case Intrinsic::x86_fma_vfnmsub_pd_256:
16045 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16046 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16047 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16048 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16049 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16050 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16054 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16055 SDValue Src, SDValue Mask, SDValue Base,
16056 SDValue Index, SDValue ScaleOp, SDValue Chain,
16057 const X86Subtarget * Subtarget) {
16059 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16060 assert(C && "Invalid scale type");
16061 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16062 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16063 Index.getSimpleValueType().getVectorNumElements());
16065 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16067 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16069 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16070 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16071 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16072 SDValue Segment = DAG.getRegister(0, MVT::i32);
16073 if (Src.getOpcode() == ISD::UNDEF)
16074 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16075 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16076 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16077 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16078 return DAG.getMergeValues(RetOps, dl);
16081 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16082 SDValue Src, SDValue Mask, SDValue Base,
16083 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16085 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16086 assert(C && "Invalid scale type");
16087 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16088 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16089 SDValue Segment = DAG.getRegister(0, MVT::i32);
16090 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16091 Index.getSimpleValueType().getVectorNumElements());
16093 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16095 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16097 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16098 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16099 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16100 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16101 return SDValue(Res, 1);
16104 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16105 SDValue Mask, SDValue Base, SDValue Index,
16106 SDValue ScaleOp, SDValue Chain) {
16108 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16109 assert(C && "Invalid scale type");
16110 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16111 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16112 SDValue Segment = DAG.getRegister(0, MVT::i32);
16114 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16116 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16118 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16120 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16121 //SDVTList VTs = DAG.getVTList(MVT::Other);
16122 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16123 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16124 return SDValue(Res, 0);
16127 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16128 // read performance monitor counters (x86_rdpmc).
16129 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16130 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16131 SmallVectorImpl<SDValue> &Results) {
16132 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16133 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16136 // The ECX register is used to select the index of the performance counter
16138 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16140 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16142 // Reads the content of a 64-bit performance counter and returns it in the
16143 // registers EDX:EAX.
16144 if (Subtarget->is64Bit()) {
16145 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16146 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16149 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16150 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16153 Chain = HI.getValue(1);
16155 if (Subtarget->is64Bit()) {
16156 // The EAX register is loaded with the low-order 32 bits. The EDX register
16157 // is loaded with the supported high-order bits of the counter.
16158 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16159 DAG.getConstant(32, MVT::i8));
16160 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16161 Results.push_back(Chain);
16165 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16166 SDValue Ops[] = { LO, HI };
16167 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16168 Results.push_back(Pair);
16169 Results.push_back(Chain);
16172 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16173 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16174 // also used to custom lower READCYCLECOUNTER nodes.
16175 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16176 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16177 SmallVectorImpl<SDValue> &Results) {
16178 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16179 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16182 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16183 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16184 // and the EAX register is loaded with the low-order 32 bits.
16185 if (Subtarget->is64Bit()) {
16186 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16187 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16190 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16191 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16194 SDValue Chain = HI.getValue(1);
16196 if (Opcode == X86ISD::RDTSCP_DAG) {
16197 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16199 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16200 // the ECX register. Add 'ecx' explicitly to the chain.
16201 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16203 // Explicitly store the content of ECX at the location passed in input
16204 // to the 'rdtscp' intrinsic.
16205 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16206 MachinePointerInfo(), false, false, 0);
16209 if (Subtarget->is64Bit()) {
16210 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16211 // the EAX register is loaded with the low-order 32 bits.
16212 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16213 DAG.getConstant(32, MVT::i8));
16214 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16215 Results.push_back(Chain);
16219 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16220 SDValue Ops[] = { LO, HI };
16221 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16222 Results.push_back(Pair);
16223 Results.push_back(Chain);
16226 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16227 SelectionDAG &DAG) {
16228 SmallVector<SDValue, 2> Results;
16230 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16232 return DAG.getMergeValues(Results, DL);
16236 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16237 SelectionDAG &DAG) {
16238 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16240 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16245 switch(IntrData->Type) {
16247 llvm_unreachable("Unknown Intrinsic Type");
16251 // Emit the node with the right value type.
16252 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16253 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16255 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16256 // Otherwise return the value from Rand, which is always 0, casted to i32.
16257 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16258 DAG.getConstant(1, Op->getValueType(1)),
16259 DAG.getConstant(X86::COND_B, MVT::i32),
16260 SDValue(Result.getNode(), 1) };
16261 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16262 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16265 // Return { result, isValid, chain }.
16266 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16267 SDValue(Result.getNode(), 2));
16270 //gather(v1, mask, index, base, scale);
16271 SDValue Chain = Op.getOperand(0);
16272 SDValue Src = Op.getOperand(2);
16273 SDValue Base = Op.getOperand(3);
16274 SDValue Index = Op.getOperand(4);
16275 SDValue Mask = Op.getOperand(5);
16276 SDValue Scale = Op.getOperand(6);
16277 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16281 //scatter(base, mask, index, v1, scale);
16282 SDValue Chain = Op.getOperand(0);
16283 SDValue Base = Op.getOperand(2);
16284 SDValue Mask = Op.getOperand(3);
16285 SDValue Index = Op.getOperand(4);
16286 SDValue Src = Op.getOperand(5);
16287 SDValue Scale = Op.getOperand(6);
16288 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16291 SDValue Hint = Op.getOperand(6);
16293 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16294 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16295 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16296 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16297 SDValue Chain = Op.getOperand(0);
16298 SDValue Mask = Op.getOperand(2);
16299 SDValue Index = Op.getOperand(3);
16300 SDValue Base = Op.getOperand(4);
16301 SDValue Scale = Op.getOperand(5);
16302 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16304 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16306 SmallVector<SDValue, 2> Results;
16307 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16308 return DAG.getMergeValues(Results, dl);
16310 // Read Performance Monitoring Counters.
16312 SmallVector<SDValue, 2> Results;
16313 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16314 return DAG.getMergeValues(Results, dl);
16316 // XTEST intrinsics.
16318 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16319 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16320 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16321 DAG.getConstant(X86::COND_NE, MVT::i8),
16323 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16324 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16325 Ret, SDValue(InTrans.getNode(), 1));
16329 SmallVector<SDValue, 2> Results;
16330 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16331 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16332 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16333 DAG.getConstant(-1, MVT::i8));
16334 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16335 Op.getOperand(4), GenCF.getValue(1));
16336 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16337 Op.getOperand(5), MachinePointerInfo(),
16339 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16340 DAG.getConstant(X86::COND_B, MVT::i8),
16342 Results.push_back(SetCC);
16343 Results.push_back(Store);
16344 return DAG.getMergeValues(Results, dl);
16349 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16350 SelectionDAG &DAG) const {
16351 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16352 MFI->setReturnAddressIsTaken(true);
16354 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16357 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16359 EVT PtrVT = getPointerTy();
16362 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16363 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16364 DAG.getSubtarget().getRegisterInfo());
16365 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16366 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16367 DAG.getNode(ISD::ADD, dl, PtrVT,
16368 FrameAddr, Offset),
16369 MachinePointerInfo(), false, false, false, 0);
16372 // Just load the return address.
16373 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16374 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16375 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16378 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16379 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16380 MFI->setFrameAddressIsTaken(true);
16382 EVT VT = Op.getValueType();
16383 SDLoc dl(Op); // FIXME probably not meaningful
16384 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16385 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16386 DAG.getSubtarget().getRegisterInfo());
16387 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16388 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16389 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16390 "Invalid Frame Register!");
16391 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16393 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16394 MachinePointerInfo(),
16395 false, false, false, 0);
16399 // FIXME? Maybe this could be a TableGen attribute on some registers and
16400 // this table could be generated automatically from RegInfo.
16401 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16403 unsigned Reg = StringSwitch<unsigned>(RegName)
16404 .Case("esp", X86::ESP)
16405 .Case("rsp", X86::RSP)
16409 report_fatal_error("Invalid register name global variable");
16412 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16413 SelectionDAG &DAG) const {
16414 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16415 DAG.getSubtarget().getRegisterInfo());
16416 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16419 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16420 SDValue Chain = Op.getOperand(0);
16421 SDValue Offset = Op.getOperand(1);
16422 SDValue Handler = Op.getOperand(2);
16425 EVT PtrVT = getPointerTy();
16426 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16427 DAG.getSubtarget().getRegisterInfo());
16428 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16429 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16430 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16431 "Invalid Frame Register!");
16432 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16433 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16435 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16436 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16437 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16438 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16440 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16442 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16443 DAG.getRegister(StoreAddrReg, PtrVT));
16446 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16447 SelectionDAG &DAG) const {
16449 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16450 DAG.getVTList(MVT::i32, MVT::Other),
16451 Op.getOperand(0), Op.getOperand(1));
16454 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16455 SelectionDAG &DAG) const {
16457 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16458 Op.getOperand(0), Op.getOperand(1));
16461 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16462 return Op.getOperand(0);
16465 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16466 SelectionDAG &DAG) const {
16467 SDValue Root = Op.getOperand(0);
16468 SDValue Trmp = Op.getOperand(1); // trampoline
16469 SDValue FPtr = Op.getOperand(2); // nested function
16470 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16473 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16474 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16476 if (Subtarget->is64Bit()) {
16477 SDValue OutChains[6];
16479 // Large code-model.
16480 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16481 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16483 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16484 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16486 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16488 // Load the pointer to the nested function into R11.
16489 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16490 SDValue Addr = Trmp;
16491 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16492 Addr, MachinePointerInfo(TrmpAddr),
16495 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16496 DAG.getConstant(2, MVT::i64));
16497 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16498 MachinePointerInfo(TrmpAddr, 2),
16501 // Load the 'nest' parameter value into R10.
16502 // R10 is specified in X86CallingConv.td
16503 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16504 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16505 DAG.getConstant(10, MVT::i64));
16506 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16507 Addr, MachinePointerInfo(TrmpAddr, 10),
16510 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16511 DAG.getConstant(12, MVT::i64));
16512 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16513 MachinePointerInfo(TrmpAddr, 12),
16516 // Jump to the nested function.
16517 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16518 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16519 DAG.getConstant(20, MVT::i64));
16520 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16521 Addr, MachinePointerInfo(TrmpAddr, 20),
16524 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16525 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16526 DAG.getConstant(22, MVT::i64));
16527 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16528 MachinePointerInfo(TrmpAddr, 22),
16531 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16533 const Function *Func =
16534 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16535 CallingConv::ID CC = Func->getCallingConv();
16540 llvm_unreachable("Unsupported calling convention");
16541 case CallingConv::C:
16542 case CallingConv::X86_StdCall: {
16543 // Pass 'nest' parameter in ECX.
16544 // Must be kept in sync with X86CallingConv.td
16545 NestReg = X86::ECX;
16547 // Check that ECX wasn't needed by an 'inreg' parameter.
16548 FunctionType *FTy = Func->getFunctionType();
16549 const AttributeSet &Attrs = Func->getAttributes();
16551 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16552 unsigned InRegCount = 0;
16555 for (FunctionType::param_iterator I = FTy->param_begin(),
16556 E = FTy->param_end(); I != E; ++I, ++Idx)
16557 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16558 // FIXME: should only count parameters that are lowered to integers.
16559 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16561 if (InRegCount > 2) {
16562 report_fatal_error("Nest register in use - reduce number of inreg"
16568 case CallingConv::X86_FastCall:
16569 case CallingConv::X86_ThisCall:
16570 case CallingConv::Fast:
16571 // Pass 'nest' parameter in EAX.
16572 // Must be kept in sync with X86CallingConv.td
16573 NestReg = X86::EAX;
16577 SDValue OutChains[4];
16578 SDValue Addr, Disp;
16580 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16581 DAG.getConstant(10, MVT::i32));
16582 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16584 // This is storing the opcode for MOV32ri.
16585 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16586 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16587 OutChains[0] = DAG.getStore(Root, dl,
16588 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16589 Trmp, MachinePointerInfo(TrmpAddr),
16592 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16593 DAG.getConstant(1, MVT::i32));
16594 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16595 MachinePointerInfo(TrmpAddr, 1),
16598 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16599 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16600 DAG.getConstant(5, MVT::i32));
16601 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16602 MachinePointerInfo(TrmpAddr, 5),
16605 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16606 DAG.getConstant(6, MVT::i32));
16607 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16608 MachinePointerInfo(TrmpAddr, 6),
16611 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16615 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16616 SelectionDAG &DAG) const {
16618 The rounding mode is in bits 11:10 of FPSR, and has the following
16620 00 Round to nearest
16625 FLT_ROUNDS, on the other hand, expects the following:
16632 To perform the conversion, we do:
16633 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16636 MachineFunction &MF = DAG.getMachineFunction();
16637 const TargetMachine &TM = MF.getTarget();
16638 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16639 unsigned StackAlignment = TFI.getStackAlignment();
16640 MVT VT = Op.getSimpleValueType();
16643 // Save FP Control Word to stack slot
16644 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16645 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16647 MachineMemOperand *MMO =
16648 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16649 MachineMemOperand::MOStore, 2, 2);
16651 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16652 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16653 DAG.getVTList(MVT::Other),
16654 Ops, MVT::i16, MMO);
16656 // Load FP Control Word from stack slot
16657 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16658 MachinePointerInfo(), false, false, false, 0);
16660 // Transform as necessary
16662 DAG.getNode(ISD::SRL, DL, MVT::i16,
16663 DAG.getNode(ISD::AND, DL, MVT::i16,
16664 CWD, DAG.getConstant(0x800, MVT::i16)),
16665 DAG.getConstant(11, MVT::i8));
16667 DAG.getNode(ISD::SRL, DL, MVT::i16,
16668 DAG.getNode(ISD::AND, DL, MVT::i16,
16669 CWD, DAG.getConstant(0x400, MVT::i16)),
16670 DAG.getConstant(9, MVT::i8));
16673 DAG.getNode(ISD::AND, DL, MVT::i16,
16674 DAG.getNode(ISD::ADD, DL, MVT::i16,
16675 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16676 DAG.getConstant(1, MVT::i16)),
16677 DAG.getConstant(3, MVT::i16));
16679 return DAG.getNode((VT.getSizeInBits() < 16 ?
16680 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16683 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16684 MVT VT = Op.getSimpleValueType();
16686 unsigned NumBits = VT.getSizeInBits();
16689 Op = Op.getOperand(0);
16690 if (VT == MVT::i8) {
16691 // Zero extend to i32 since there is not an i8 bsr.
16693 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16696 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16697 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16698 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16700 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16703 DAG.getConstant(NumBits+NumBits-1, OpVT),
16704 DAG.getConstant(X86::COND_E, MVT::i8),
16707 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16709 // Finally xor with NumBits-1.
16710 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16713 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16717 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16718 MVT VT = Op.getSimpleValueType();
16720 unsigned NumBits = VT.getSizeInBits();
16723 Op = Op.getOperand(0);
16724 if (VT == MVT::i8) {
16725 // Zero extend to i32 since there is not an i8 bsr.
16727 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16730 // Issue a bsr (scan bits in reverse).
16731 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16732 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16734 // And xor with NumBits-1.
16735 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16738 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16742 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16743 MVT VT = Op.getSimpleValueType();
16744 unsigned NumBits = VT.getSizeInBits();
16746 Op = Op.getOperand(0);
16748 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16749 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16750 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16752 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16755 DAG.getConstant(NumBits, VT),
16756 DAG.getConstant(X86::COND_E, MVT::i8),
16759 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16762 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16763 // ones, and then concatenate the result back.
16764 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16765 MVT VT = Op.getSimpleValueType();
16767 assert(VT.is256BitVector() && VT.isInteger() &&
16768 "Unsupported value type for operation");
16770 unsigned NumElems = VT.getVectorNumElements();
16773 // Extract the LHS vectors
16774 SDValue LHS = Op.getOperand(0);
16775 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16776 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16778 // Extract the RHS vectors
16779 SDValue RHS = Op.getOperand(1);
16780 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16781 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16783 MVT EltVT = VT.getVectorElementType();
16784 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16786 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16787 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16788 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16791 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16792 assert(Op.getSimpleValueType().is256BitVector() &&
16793 Op.getSimpleValueType().isInteger() &&
16794 "Only handle AVX 256-bit vector integer operation");
16795 return Lower256IntArith(Op, DAG);
16798 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16799 assert(Op.getSimpleValueType().is256BitVector() &&
16800 Op.getSimpleValueType().isInteger() &&
16801 "Only handle AVX 256-bit vector integer operation");
16802 return Lower256IntArith(Op, DAG);
16805 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16806 SelectionDAG &DAG) {
16808 MVT VT = Op.getSimpleValueType();
16810 // Decompose 256-bit ops into smaller 128-bit ops.
16811 if (VT.is256BitVector() && !Subtarget->hasInt256())
16812 return Lower256IntArith(Op, DAG);
16814 SDValue A = Op.getOperand(0);
16815 SDValue B = Op.getOperand(1);
16817 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16818 if (VT == MVT::v4i32) {
16819 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16820 "Should not custom lower when pmuldq is available!");
16822 // Extract the odd parts.
16823 static const int UnpackMask[] = { 1, -1, 3, -1 };
16824 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16825 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16827 // Multiply the even parts.
16828 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16829 // Now multiply odd parts.
16830 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16832 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16833 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16835 // Merge the two vectors back together with a shuffle. This expands into 2
16837 static const int ShufMask[] = { 0, 4, 2, 6 };
16838 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16841 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16842 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16844 // Ahi = psrlqi(a, 32);
16845 // Bhi = psrlqi(b, 32);
16847 // AloBlo = pmuludq(a, b);
16848 // AloBhi = pmuludq(a, Bhi);
16849 // AhiBlo = pmuludq(Ahi, b);
16851 // AloBhi = psllqi(AloBhi, 32);
16852 // AhiBlo = psllqi(AhiBlo, 32);
16853 // return AloBlo + AloBhi + AhiBlo;
16855 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16856 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16858 // Bit cast to 32-bit vectors for MULUDQ
16859 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16860 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16861 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16862 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16863 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16864 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16866 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16867 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16868 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16870 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16871 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16873 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16874 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16877 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16878 assert(Subtarget->isTargetWin64() && "Unexpected target");
16879 EVT VT = Op.getValueType();
16880 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16881 "Unexpected return type for lowering");
16885 switch (Op->getOpcode()) {
16886 default: llvm_unreachable("Unexpected request for libcall!");
16887 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16888 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16889 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16890 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16891 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16892 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16896 SDValue InChain = DAG.getEntryNode();
16898 TargetLowering::ArgListTy Args;
16899 TargetLowering::ArgListEntry Entry;
16900 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16901 EVT ArgVT = Op->getOperand(i).getValueType();
16902 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16903 "Unexpected argument type for lowering");
16904 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16905 Entry.Node = StackPtr;
16906 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16908 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16909 Entry.Ty = PointerType::get(ArgTy,0);
16910 Entry.isSExt = false;
16911 Entry.isZExt = false;
16912 Args.push_back(Entry);
16915 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16918 TargetLowering::CallLoweringInfo CLI(DAG);
16919 CLI.setDebugLoc(dl).setChain(InChain)
16920 .setCallee(getLibcallCallingConv(LC),
16921 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16922 Callee, std::move(Args), 0)
16923 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16925 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16926 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16929 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16930 SelectionDAG &DAG) {
16931 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16932 EVT VT = Op0.getValueType();
16935 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16936 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16938 // PMULxD operations multiply each even value (starting at 0) of LHS with
16939 // the related value of RHS and produce a widen result.
16940 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16941 // => <2 x i64> <ae|cg>
16943 // In other word, to have all the results, we need to perform two PMULxD:
16944 // 1. one with the even values.
16945 // 2. one with the odd values.
16946 // To achieve #2, with need to place the odd values at an even position.
16948 // Place the odd value at an even position (basically, shift all values 1
16949 // step to the left):
16950 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16951 // <a|b|c|d> => <b|undef|d|undef>
16952 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16953 // <e|f|g|h> => <f|undef|h|undef>
16954 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16956 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16958 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16959 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16961 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16962 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16963 // => <2 x i64> <ae|cg>
16964 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16965 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16966 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16967 // => <2 x i64> <bf|dh>
16968 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16969 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16971 // Shuffle it back into the right order.
16972 SDValue Highs, Lows;
16973 if (VT == MVT::v8i32) {
16974 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16975 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16976 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16977 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16979 const int HighMask[] = {1, 5, 3, 7};
16980 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16981 const int LowMask[] = {0, 4, 2, 6};
16982 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16985 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16986 // unsigned multiply.
16987 if (IsSigned && !Subtarget->hasSSE41()) {
16989 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16990 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16991 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16992 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16993 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16995 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16996 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16999 // The first result of MUL_LOHI is actually the low value, followed by the
17001 SDValue Ops[] = {Lows, Highs};
17002 return DAG.getMergeValues(Ops, dl);
17005 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17006 const X86Subtarget *Subtarget) {
17007 MVT VT = Op.getSimpleValueType();
17009 SDValue R = Op.getOperand(0);
17010 SDValue Amt = Op.getOperand(1);
17012 // Optimize shl/srl/sra with constant shift amount.
17013 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17014 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17015 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17017 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17018 (Subtarget->hasInt256() &&
17019 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17020 (Subtarget->hasAVX512() &&
17021 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17022 if (Op.getOpcode() == ISD::SHL)
17023 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17025 if (Op.getOpcode() == ISD::SRL)
17026 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17028 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17029 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17033 if (VT == MVT::v16i8) {
17034 if (Op.getOpcode() == ISD::SHL) {
17035 // Make a large shift.
17036 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17037 MVT::v8i16, R, ShiftAmt,
17039 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17040 // Zero out the rightmost bits.
17041 SmallVector<SDValue, 16> V(16,
17042 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17044 return DAG.getNode(ISD::AND, dl, VT, SHL,
17045 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17047 if (Op.getOpcode() == ISD::SRL) {
17048 // Make a large shift.
17049 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17050 MVT::v8i16, R, ShiftAmt,
17052 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17053 // Zero out the leftmost bits.
17054 SmallVector<SDValue, 16> V(16,
17055 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17057 return DAG.getNode(ISD::AND, dl, VT, SRL,
17058 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17060 if (Op.getOpcode() == ISD::SRA) {
17061 if (ShiftAmt == 7) {
17062 // R s>> 7 === R s< 0
17063 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17064 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17067 // R s>> a === ((R u>> a) ^ m) - m
17068 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17069 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17071 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17072 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17073 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17076 llvm_unreachable("Unknown shift opcode.");
17079 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17080 if (Op.getOpcode() == ISD::SHL) {
17081 // Make a large shift.
17082 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17083 MVT::v16i16, R, ShiftAmt,
17085 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17086 // Zero out the rightmost bits.
17087 SmallVector<SDValue, 32> V(32,
17088 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17090 return DAG.getNode(ISD::AND, dl, VT, SHL,
17091 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17093 if (Op.getOpcode() == ISD::SRL) {
17094 // Make a large shift.
17095 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17096 MVT::v16i16, R, ShiftAmt,
17098 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17099 // Zero out the leftmost bits.
17100 SmallVector<SDValue, 32> V(32,
17101 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17103 return DAG.getNode(ISD::AND, dl, VT, SRL,
17104 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17106 if (Op.getOpcode() == ISD::SRA) {
17107 if (ShiftAmt == 7) {
17108 // R s>> 7 === R s< 0
17109 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17110 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17113 // R s>> a === ((R u>> a) ^ m) - m
17114 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17115 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17117 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17118 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17119 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17122 llvm_unreachable("Unknown shift opcode.");
17127 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17128 if (!Subtarget->is64Bit() &&
17129 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17130 Amt.getOpcode() == ISD::BITCAST &&
17131 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17132 Amt = Amt.getOperand(0);
17133 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17134 VT.getVectorNumElements();
17135 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17136 uint64_t ShiftAmt = 0;
17137 for (unsigned i = 0; i != Ratio; ++i) {
17138 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17142 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17144 // Check remaining shift amounts.
17145 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17146 uint64_t ShAmt = 0;
17147 for (unsigned j = 0; j != Ratio; ++j) {
17148 ConstantSDNode *C =
17149 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17153 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17155 if (ShAmt != ShiftAmt)
17158 switch (Op.getOpcode()) {
17160 llvm_unreachable("Unknown shift opcode!");
17162 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17165 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17168 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17176 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17177 const X86Subtarget* Subtarget) {
17178 MVT VT = Op.getSimpleValueType();
17180 SDValue R = Op.getOperand(0);
17181 SDValue Amt = Op.getOperand(1);
17183 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17184 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17185 (Subtarget->hasInt256() &&
17186 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17187 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17188 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17190 EVT EltVT = VT.getVectorElementType();
17192 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17193 unsigned NumElts = VT.getVectorNumElements();
17195 for (i = 0; i != NumElts; ++i) {
17196 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17200 for (j = i; j != NumElts; ++j) {
17201 SDValue Arg = Amt.getOperand(j);
17202 if (Arg.getOpcode() == ISD::UNDEF) continue;
17203 if (Arg != Amt.getOperand(i))
17206 if (i != NumElts && j == NumElts)
17207 BaseShAmt = Amt.getOperand(i);
17209 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17210 Amt = Amt.getOperand(0);
17211 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17212 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17213 SDValue InVec = Amt.getOperand(0);
17214 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17215 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17217 for (; i != NumElts; ++i) {
17218 SDValue Arg = InVec.getOperand(i);
17219 if (Arg.getOpcode() == ISD::UNDEF) continue;
17223 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17224 if (ConstantSDNode *C =
17225 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17226 unsigned SplatIdx =
17227 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17228 if (C->getZExtValue() == SplatIdx)
17229 BaseShAmt = InVec.getOperand(1);
17232 if (!BaseShAmt.getNode())
17233 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17234 DAG.getIntPtrConstant(0));
17238 if (BaseShAmt.getNode()) {
17239 if (EltVT.bitsGT(MVT::i32))
17240 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17241 else if (EltVT.bitsLT(MVT::i32))
17242 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17244 switch (Op.getOpcode()) {
17246 llvm_unreachable("Unknown shift opcode!");
17248 switch (VT.SimpleTy) {
17249 default: return SDValue();
17258 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17261 switch (VT.SimpleTy) {
17262 default: return SDValue();
17269 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17272 switch (VT.SimpleTy) {
17273 default: return SDValue();
17282 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17288 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17289 if (!Subtarget->is64Bit() &&
17290 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17291 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17292 Amt.getOpcode() == ISD::BITCAST &&
17293 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17294 Amt = Amt.getOperand(0);
17295 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17296 VT.getVectorNumElements();
17297 std::vector<SDValue> Vals(Ratio);
17298 for (unsigned i = 0; i != Ratio; ++i)
17299 Vals[i] = Amt.getOperand(i);
17300 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17301 for (unsigned j = 0; j != Ratio; ++j)
17302 if (Vals[j] != Amt.getOperand(i + j))
17305 switch (Op.getOpcode()) {
17307 llvm_unreachable("Unknown shift opcode!");
17309 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17311 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17313 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17320 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17321 SelectionDAG &DAG) {
17322 MVT VT = Op.getSimpleValueType();
17324 SDValue R = Op.getOperand(0);
17325 SDValue Amt = Op.getOperand(1);
17328 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17329 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17331 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17335 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17339 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17341 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17342 if (Subtarget->hasInt256()) {
17343 if (Op.getOpcode() == ISD::SRL &&
17344 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17345 VT == MVT::v4i64 || VT == MVT::v8i32))
17347 if (Op.getOpcode() == ISD::SHL &&
17348 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17349 VT == MVT::v4i64 || VT == MVT::v8i32))
17351 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17355 // If possible, lower this packed shift into a vector multiply instead of
17356 // expanding it into a sequence of scalar shifts.
17357 // Do this only if the vector shift count is a constant build_vector.
17358 if (Op.getOpcode() == ISD::SHL &&
17359 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17360 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17361 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17362 SmallVector<SDValue, 8> Elts;
17363 EVT SVT = VT.getScalarType();
17364 unsigned SVTBits = SVT.getSizeInBits();
17365 const APInt &One = APInt(SVTBits, 1);
17366 unsigned NumElems = VT.getVectorNumElements();
17368 for (unsigned i=0; i !=NumElems; ++i) {
17369 SDValue Op = Amt->getOperand(i);
17370 if (Op->getOpcode() == ISD::UNDEF) {
17371 Elts.push_back(Op);
17375 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17376 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17377 uint64_t ShAmt = C.getZExtValue();
17378 if (ShAmt >= SVTBits) {
17379 Elts.push_back(DAG.getUNDEF(SVT));
17382 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17384 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17385 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17388 // Lower SHL with variable shift amount.
17389 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17390 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17392 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17393 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17394 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17395 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17398 // If possible, lower this shift as a sequence of two shifts by
17399 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17401 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17403 // Could be rewritten as:
17404 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17406 // The advantage is that the two shifts from the example would be
17407 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17408 // the vector shift into four scalar shifts plus four pairs of vector
17410 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17411 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17412 unsigned TargetOpcode = X86ISD::MOVSS;
17413 bool CanBeSimplified;
17414 // The splat value for the first packed shift (the 'X' from the example).
17415 SDValue Amt1 = Amt->getOperand(0);
17416 // The splat value for the second packed shift (the 'Y' from the example).
17417 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17418 Amt->getOperand(2);
17420 // See if it is possible to replace this node with a sequence of
17421 // two shifts followed by a MOVSS/MOVSD
17422 if (VT == MVT::v4i32) {
17423 // Check if it is legal to use a MOVSS.
17424 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17425 Amt2 == Amt->getOperand(3);
17426 if (!CanBeSimplified) {
17427 // Otherwise, check if we can still simplify this node using a MOVSD.
17428 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17429 Amt->getOperand(2) == Amt->getOperand(3);
17430 TargetOpcode = X86ISD::MOVSD;
17431 Amt2 = Amt->getOperand(2);
17434 // Do similar checks for the case where the machine value type
17436 CanBeSimplified = Amt1 == Amt->getOperand(1);
17437 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17438 CanBeSimplified = Amt2 == Amt->getOperand(i);
17440 if (!CanBeSimplified) {
17441 TargetOpcode = X86ISD::MOVSD;
17442 CanBeSimplified = true;
17443 Amt2 = Amt->getOperand(4);
17444 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17445 CanBeSimplified = Amt1 == Amt->getOperand(i);
17446 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17447 CanBeSimplified = Amt2 == Amt->getOperand(j);
17451 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17452 isa<ConstantSDNode>(Amt2)) {
17453 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17454 EVT CastVT = MVT::v4i32;
17456 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17457 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17459 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17460 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17461 if (TargetOpcode == X86ISD::MOVSD)
17462 CastVT = MVT::v2i64;
17463 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17464 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17465 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17467 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17471 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17472 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17475 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17476 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17478 // Turn 'a' into a mask suitable for VSELECT
17479 SDValue VSelM = DAG.getConstant(0x80, VT);
17480 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17481 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17483 SDValue CM1 = DAG.getConstant(0x0f, VT);
17484 SDValue CM2 = DAG.getConstant(0x3f, VT);
17486 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17487 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17488 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17489 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17490 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17493 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17494 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17495 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17497 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17498 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17499 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17500 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17501 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17504 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17505 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17506 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17508 // return VSELECT(r, r+r, a);
17509 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17510 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17514 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17515 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17516 // solution better.
17517 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17518 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17520 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17521 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17522 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17523 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17524 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17527 // Decompose 256-bit shifts into smaller 128-bit shifts.
17528 if (VT.is256BitVector()) {
17529 unsigned NumElems = VT.getVectorNumElements();
17530 MVT EltVT = VT.getVectorElementType();
17531 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17533 // Extract the two vectors
17534 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17535 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17537 // Recreate the shift amount vectors
17538 SDValue Amt1, Amt2;
17539 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17540 // Constant shift amount
17541 SmallVector<SDValue, 4> Amt1Csts;
17542 SmallVector<SDValue, 4> Amt2Csts;
17543 for (unsigned i = 0; i != NumElems/2; ++i)
17544 Amt1Csts.push_back(Amt->getOperand(i));
17545 for (unsigned i = NumElems/2; i != NumElems; ++i)
17546 Amt2Csts.push_back(Amt->getOperand(i));
17548 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17549 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17551 // Variable shift amount
17552 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17553 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17556 // Issue new vector shifts for the smaller types
17557 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17558 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17560 // Concatenate the result back
17561 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17567 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17568 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17569 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17570 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17571 // has only one use.
17572 SDNode *N = Op.getNode();
17573 SDValue LHS = N->getOperand(0);
17574 SDValue RHS = N->getOperand(1);
17575 unsigned BaseOp = 0;
17578 switch (Op.getOpcode()) {
17579 default: llvm_unreachable("Unknown ovf instruction!");
17581 // A subtract of one will be selected as a INC. Note that INC doesn't
17582 // set CF, so we can't do this for UADDO.
17583 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17585 BaseOp = X86ISD::INC;
17586 Cond = X86::COND_O;
17589 BaseOp = X86ISD::ADD;
17590 Cond = X86::COND_O;
17593 BaseOp = X86ISD::ADD;
17594 Cond = X86::COND_B;
17597 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17598 // set CF, so we can't do this for USUBO.
17599 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17601 BaseOp = X86ISD::DEC;
17602 Cond = X86::COND_O;
17605 BaseOp = X86ISD::SUB;
17606 Cond = X86::COND_O;
17609 BaseOp = X86ISD::SUB;
17610 Cond = X86::COND_B;
17613 BaseOp = X86ISD::SMUL;
17614 Cond = X86::COND_O;
17616 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17617 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17619 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17622 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17623 DAG.getConstant(X86::COND_O, MVT::i32),
17624 SDValue(Sum.getNode(), 2));
17626 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17630 // Also sets EFLAGS.
17631 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17632 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17635 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17636 DAG.getConstant(Cond, MVT::i32),
17637 SDValue(Sum.getNode(), 1));
17639 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17642 // Sign extension of the low part of vector elements. This may be used either
17643 // when sign extend instructions are not available or if the vector element
17644 // sizes already match the sign-extended size. If the vector elements are in
17645 // their pre-extended size and sign extend instructions are available, that will
17646 // be handled by LowerSIGN_EXTEND.
17647 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17648 SelectionDAG &DAG) const {
17650 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17651 MVT VT = Op.getSimpleValueType();
17653 if (!Subtarget->hasSSE2() || !VT.isVector())
17656 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17657 ExtraVT.getScalarType().getSizeInBits();
17659 switch (VT.SimpleTy) {
17660 default: return SDValue();
17663 if (!Subtarget->hasFp256())
17665 if (!Subtarget->hasInt256()) {
17666 // needs to be split
17667 unsigned NumElems = VT.getVectorNumElements();
17669 // Extract the LHS vectors
17670 SDValue LHS = Op.getOperand(0);
17671 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17672 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17674 MVT EltVT = VT.getVectorElementType();
17675 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17677 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17678 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17679 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17681 SDValue Extra = DAG.getValueType(ExtraVT);
17683 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17684 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17686 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17691 SDValue Op0 = Op.getOperand(0);
17693 // This is a sign extension of some low part of vector elements without
17694 // changing the size of the vector elements themselves:
17695 // Shift-Left + Shift-Right-Algebraic.
17696 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17698 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17704 /// Returns true if the operand type is exactly twice the native width, and
17705 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17706 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17707 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17708 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17709 const X86Subtarget &Subtarget =
17710 getTargetMachine().getSubtarget<X86Subtarget>();
17711 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17714 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17715 else if (OpWidth == 128)
17716 return Subtarget.hasCmpxchg16b();
17721 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17722 return needsCmpXchgNb(SI->getValueOperand()->getType());
17725 // Note: this turns large loads into lock cmpxchg8b/16b.
17726 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17727 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17728 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17729 return needsCmpXchgNb(PTy->getElementType());
17732 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17733 const X86Subtarget &Subtarget =
17734 getTargetMachine().getSubtarget<X86Subtarget>();
17735 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17736 const Type *MemType = AI->getType();
17738 // If the operand is too big, we must see if cmpxchg8/16b is available
17739 // and default to library calls otherwise.
17740 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17741 return needsCmpXchgNb(MemType);
17743 AtomicRMWInst::BinOp Op = AI->getOperation();
17746 llvm_unreachable("Unknown atomic operation");
17747 case AtomicRMWInst::Xchg:
17748 case AtomicRMWInst::Add:
17749 case AtomicRMWInst::Sub:
17750 // It's better to use xadd, xsub or xchg for these in all cases.
17752 case AtomicRMWInst::Or:
17753 case AtomicRMWInst::And:
17754 case AtomicRMWInst::Xor:
17755 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17756 // prefix to a normal instruction for these operations.
17757 return !AI->use_empty();
17758 case AtomicRMWInst::Nand:
17759 case AtomicRMWInst::Max:
17760 case AtomicRMWInst::Min:
17761 case AtomicRMWInst::UMax:
17762 case AtomicRMWInst::UMin:
17763 // These always require a non-trivial set of data operations on x86. We must
17764 // use a cmpxchg loop.
17769 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17770 SelectionDAG &DAG) {
17772 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17773 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17774 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17775 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17777 // The only fence that needs an instruction is a sequentially-consistent
17778 // cross-thread fence.
17779 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17780 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17781 // no-sse2). There isn't any reason to disable it if the target processor
17783 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17784 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17786 SDValue Chain = Op.getOperand(0);
17787 SDValue Zero = DAG.getConstant(0, MVT::i32);
17789 DAG.getRegister(X86::ESP, MVT::i32), // Base
17790 DAG.getTargetConstant(1, MVT::i8), // Scale
17791 DAG.getRegister(0, MVT::i32), // Index
17792 DAG.getTargetConstant(0, MVT::i32), // Disp
17793 DAG.getRegister(0, MVT::i32), // Segment.
17797 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17798 return SDValue(Res, 0);
17801 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17802 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17805 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17806 SelectionDAG &DAG) {
17807 MVT T = Op.getSimpleValueType();
17811 switch(T.SimpleTy) {
17812 default: llvm_unreachable("Invalid value type!");
17813 case MVT::i8: Reg = X86::AL; size = 1; break;
17814 case MVT::i16: Reg = X86::AX; size = 2; break;
17815 case MVT::i32: Reg = X86::EAX; size = 4; break;
17817 assert(Subtarget->is64Bit() && "Node not type legal!");
17818 Reg = X86::RAX; size = 8;
17821 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17822 Op.getOperand(2), SDValue());
17823 SDValue Ops[] = { cpIn.getValue(0),
17826 DAG.getTargetConstant(size, MVT::i8),
17827 cpIn.getValue(1) };
17828 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17829 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17830 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17834 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17835 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17836 MVT::i32, cpOut.getValue(2));
17837 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17838 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17840 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17841 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17842 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17846 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17847 SelectionDAG &DAG) {
17848 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17849 MVT DstVT = Op.getSimpleValueType();
17851 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17852 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17853 if (DstVT != MVT::f64)
17854 // This conversion needs to be expanded.
17857 SDValue InVec = Op->getOperand(0);
17859 unsigned NumElts = SrcVT.getVectorNumElements();
17860 EVT SVT = SrcVT.getVectorElementType();
17862 // Widen the vector in input in the case of MVT::v2i32.
17863 // Example: from MVT::v2i32 to MVT::v4i32.
17864 SmallVector<SDValue, 16> Elts;
17865 for (unsigned i = 0, e = NumElts; i != e; ++i)
17866 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17867 DAG.getIntPtrConstant(i)));
17869 // Explicitly mark the extra elements as Undef.
17870 SDValue Undef = DAG.getUNDEF(SVT);
17871 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17872 Elts.push_back(Undef);
17874 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17875 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17876 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17877 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17878 DAG.getIntPtrConstant(0));
17881 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17882 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17883 assert((DstVT == MVT::i64 ||
17884 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17885 "Unexpected custom BITCAST");
17886 // i64 <=> MMX conversions are Legal.
17887 if (SrcVT==MVT::i64 && DstVT.isVector())
17889 if (DstVT==MVT::i64 && SrcVT.isVector())
17891 // MMX <=> MMX conversions are Legal.
17892 if (SrcVT.isVector() && DstVT.isVector())
17894 // All other conversions need to be expanded.
17898 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17899 SDNode *Node = Op.getNode();
17901 EVT T = Node->getValueType(0);
17902 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17903 DAG.getConstant(0, T), Node->getOperand(2));
17904 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17905 cast<AtomicSDNode>(Node)->getMemoryVT(),
17906 Node->getOperand(0),
17907 Node->getOperand(1), negOp,
17908 cast<AtomicSDNode>(Node)->getMemOperand(),
17909 cast<AtomicSDNode>(Node)->getOrdering(),
17910 cast<AtomicSDNode>(Node)->getSynchScope());
17913 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17914 SDNode *Node = Op.getNode();
17916 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17918 // Convert seq_cst store -> xchg
17919 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17920 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17921 // (The only way to get a 16-byte store is cmpxchg16b)
17922 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17923 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17924 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17925 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17926 cast<AtomicSDNode>(Node)->getMemoryVT(),
17927 Node->getOperand(0),
17928 Node->getOperand(1), Node->getOperand(2),
17929 cast<AtomicSDNode>(Node)->getMemOperand(),
17930 cast<AtomicSDNode>(Node)->getOrdering(),
17931 cast<AtomicSDNode>(Node)->getSynchScope());
17932 return Swap.getValue(1);
17934 // Other atomic stores have a simple pattern.
17938 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17939 EVT VT = Op.getNode()->getSimpleValueType(0);
17941 // Let legalize expand this if it isn't a legal type yet.
17942 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17945 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17948 bool ExtraOp = false;
17949 switch (Op.getOpcode()) {
17950 default: llvm_unreachable("Invalid code");
17951 case ISD::ADDC: Opc = X86ISD::ADD; break;
17952 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17953 case ISD::SUBC: Opc = X86ISD::SUB; break;
17954 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17958 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17960 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17961 Op.getOperand(1), Op.getOperand(2));
17964 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17965 SelectionDAG &DAG) {
17966 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17968 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17969 // which returns the values as { float, float } (in XMM0) or
17970 // { double, double } (which is returned in XMM0, XMM1).
17972 SDValue Arg = Op.getOperand(0);
17973 EVT ArgVT = Arg.getValueType();
17974 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17976 TargetLowering::ArgListTy Args;
17977 TargetLowering::ArgListEntry Entry;
17981 Entry.isSExt = false;
17982 Entry.isZExt = false;
17983 Args.push_back(Entry);
17985 bool isF64 = ArgVT == MVT::f64;
17986 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17987 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17988 // the results are returned via SRet in memory.
17989 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17990 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17991 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17993 Type *RetTy = isF64
17994 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17995 : (Type*)VectorType::get(ArgTy, 4);
17997 TargetLowering::CallLoweringInfo CLI(DAG);
17998 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17999 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18001 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18004 // Returned in xmm0 and xmm1.
18005 return CallResult.first;
18007 // Returned in bits 0:31 and 32:64 xmm0.
18008 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18009 CallResult.first, DAG.getIntPtrConstant(0));
18010 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18011 CallResult.first, DAG.getIntPtrConstant(1));
18012 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18013 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18016 /// LowerOperation - Provide custom lowering hooks for some operations.
18018 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18019 switch (Op.getOpcode()) {
18020 default: llvm_unreachable("Should not custom lower this!");
18021 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18022 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18023 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18024 return LowerCMP_SWAP(Op, Subtarget, DAG);
18025 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18026 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18027 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18028 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18029 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18030 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18031 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18032 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18033 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18034 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18035 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18036 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18037 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18038 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18039 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18040 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18041 case ISD::SHL_PARTS:
18042 case ISD::SRA_PARTS:
18043 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18044 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18045 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18046 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18047 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18048 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18049 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18050 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18051 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18052 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18053 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18055 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18056 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18057 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18058 case ISD::SETCC: return LowerSETCC(Op, DAG);
18059 case ISD::SELECT: return LowerSELECT(Op, DAG);
18060 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18061 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18062 case ISD::VASTART: return LowerVASTART(Op, DAG);
18063 case ISD::VAARG: return LowerVAARG(Op, DAG);
18064 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18065 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18066 case ISD::INTRINSIC_VOID:
18067 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18068 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18069 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18070 case ISD::FRAME_TO_ARGS_OFFSET:
18071 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18072 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18073 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18074 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18075 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18076 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18077 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18078 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18079 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18080 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18081 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18082 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18083 case ISD::UMUL_LOHI:
18084 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18087 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18093 case ISD::UMULO: return LowerXALUO(Op, DAG);
18094 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18095 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18099 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18100 case ISD::ADD: return LowerADD(Op, DAG);
18101 case ISD::SUB: return LowerSUB(Op, DAG);
18102 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18106 /// ReplaceNodeResults - Replace a node with an illegal result type
18107 /// with a new node built out of custom code.
18108 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18109 SmallVectorImpl<SDValue>&Results,
18110 SelectionDAG &DAG) const {
18112 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18113 switch (N->getOpcode()) {
18115 llvm_unreachable("Do not know how to custom type legalize this operation!");
18116 case ISD::SIGN_EXTEND_INREG:
18121 // We don't want to expand or promote these.
18128 case ISD::UDIVREM: {
18129 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18130 Results.push_back(V);
18133 case ISD::FP_TO_SINT:
18134 case ISD::FP_TO_UINT: {
18135 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18137 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18140 std::pair<SDValue,SDValue> Vals =
18141 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18142 SDValue FIST = Vals.first, StackSlot = Vals.second;
18143 if (FIST.getNode()) {
18144 EVT VT = N->getValueType(0);
18145 // Return a load from the stack slot.
18146 if (StackSlot.getNode())
18147 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18148 MachinePointerInfo(),
18149 false, false, false, 0));
18151 Results.push_back(FIST);
18155 case ISD::UINT_TO_FP: {
18156 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18157 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18158 N->getValueType(0) != MVT::v2f32)
18160 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18162 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18164 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18165 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18166 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18167 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18168 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18169 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18172 case ISD::FP_ROUND: {
18173 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18175 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18176 Results.push_back(V);
18179 case ISD::INTRINSIC_W_CHAIN: {
18180 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18182 default : llvm_unreachable("Do not know how to custom type "
18183 "legalize this intrinsic operation!");
18184 case Intrinsic::x86_rdtsc:
18185 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18187 case Intrinsic::x86_rdtscp:
18188 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18190 case Intrinsic::x86_rdpmc:
18191 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18194 case ISD::READCYCLECOUNTER: {
18195 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18198 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18199 EVT T = N->getValueType(0);
18200 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18201 bool Regs64bit = T == MVT::i128;
18202 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18203 SDValue cpInL, cpInH;
18204 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18205 DAG.getConstant(0, HalfT));
18206 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18207 DAG.getConstant(1, HalfT));
18208 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18209 Regs64bit ? X86::RAX : X86::EAX,
18211 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18212 Regs64bit ? X86::RDX : X86::EDX,
18213 cpInH, cpInL.getValue(1));
18214 SDValue swapInL, swapInH;
18215 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18216 DAG.getConstant(0, HalfT));
18217 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18218 DAG.getConstant(1, HalfT));
18219 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18220 Regs64bit ? X86::RBX : X86::EBX,
18221 swapInL, cpInH.getValue(1));
18222 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18223 Regs64bit ? X86::RCX : X86::ECX,
18224 swapInH, swapInL.getValue(1));
18225 SDValue Ops[] = { swapInH.getValue(0),
18227 swapInH.getValue(1) };
18228 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18229 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18230 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18231 X86ISD::LCMPXCHG8_DAG;
18232 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18233 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18234 Regs64bit ? X86::RAX : X86::EAX,
18235 HalfT, Result.getValue(1));
18236 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18237 Regs64bit ? X86::RDX : X86::EDX,
18238 HalfT, cpOutL.getValue(2));
18239 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18241 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18242 MVT::i32, cpOutH.getValue(2));
18244 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18245 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18246 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18248 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18249 Results.push_back(Success);
18250 Results.push_back(EFLAGS.getValue(1));
18253 case ISD::ATOMIC_SWAP:
18254 case ISD::ATOMIC_LOAD_ADD:
18255 case ISD::ATOMIC_LOAD_SUB:
18256 case ISD::ATOMIC_LOAD_AND:
18257 case ISD::ATOMIC_LOAD_OR:
18258 case ISD::ATOMIC_LOAD_XOR:
18259 case ISD::ATOMIC_LOAD_NAND:
18260 case ISD::ATOMIC_LOAD_MIN:
18261 case ISD::ATOMIC_LOAD_MAX:
18262 case ISD::ATOMIC_LOAD_UMIN:
18263 case ISD::ATOMIC_LOAD_UMAX:
18264 case ISD::ATOMIC_LOAD: {
18265 // Delegate to generic TypeLegalization. Situations we can really handle
18266 // should have already been dealt with by AtomicExpandPass.cpp.
18269 case ISD::BITCAST: {
18270 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18271 EVT DstVT = N->getValueType(0);
18272 EVT SrcVT = N->getOperand(0)->getValueType(0);
18274 if (SrcVT != MVT::f64 ||
18275 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18278 unsigned NumElts = DstVT.getVectorNumElements();
18279 EVT SVT = DstVT.getVectorElementType();
18280 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18281 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18282 MVT::v2f64, N->getOperand(0));
18283 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18285 if (ExperimentalVectorWideningLegalization) {
18286 // If we are legalizing vectors by widening, we already have the desired
18287 // legal vector type, just return it.
18288 Results.push_back(ToVecInt);
18292 SmallVector<SDValue, 8> Elts;
18293 for (unsigned i = 0, e = NumElts; i != e; ++i)
18294 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18295 ToVecInt, DAG.getIntPtrConstant(i)));
18297 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18302 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18304 default: return nullptr;
18305 case X86ISD::BSF: return "X86ISD::BSF";
18306 case X86ISD::BSR: return "X86ISD::BSR";
18307 case X86ISD::SHLD: return "X86ISD::SHLD";
18308 case X86ISD::SHRD: return "X86ISD::SHRD";
18309 case X86ISD::FAND: return "X86ISD::FAND";
18310 case X86ISD::FANDN: return "X86ISD::FANDN";
18311 case X86ISD::FOR: return "X86ISD::FOR";
18312 case X86ISD::FXOR: return "X86ISD::FXOR";
18313 case X86ISD::FSRL: return "X86ISD::FSRL";
18314 case X86ISD::FILD: return "X86ISD::FILD";
18315 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18316 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18317 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18318 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18319 case X86ISD::FLD: return "X86ISD::FLD";
18320 case X86ISD::FST: return "X86ISD::FST";
18321 case X86ISD::CALL: return "X86ISD::CALL";
18322 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18323 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18324 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18325 case X86ISD::BT: return "X86ISD::BT";
18326 case X86ISD::CMP: return "X86ISD::CMP";
18327 case X86ISD::COMI: return "X86ISD::COMI";
18328 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18329 case X86ISD::CMPM: return "X86ISD::CMPM";
18330 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18331 case X86ISD::SETCC: return "X86ISD::SETCC";
18332 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18333 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18334 case X86ISD::CMOV: return "X86ISD::CMOV";
18335 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18336 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18337 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18338 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18339 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18340 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18341 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18342 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18343 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18344 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18345 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18346 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18347 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18348 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18349 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18350 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18351 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18352 case X86ISD::HADD: return "X86ISD::HADD";
18353 case X86ISD::HSUB: return "X86ISD::HSUB";
18354 case X86ISD::FHADD: return "X86ISD::FHADD";
18355 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18356 case X86ISD::UMAX: return "X86ISD::UMAX";
18357 case X86ISD::UMIN: return "X86ISD::UMIN";
18358 case X86ISD::SMAX: return "X86ISD::SMAX";
18359 case X86ISD::SMIN: return "X86ISD::SMIN";
18360 case X86ISD::FMAX: return "X86ISD::FMAX";
18361 case X86ISD::FMIN: return "X86ISD::FMIN";
18362 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18363 case X86ISD::FMINC: return "X86ISD::FMINC";
18364 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18365 case X86ISD::FRCP: return "X86ISD::FRCP";
18366 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18367 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18368 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18369 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18370 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18371 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18372 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18373 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18374 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18375 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18376 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18377 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18378 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18379 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18380 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18381 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18382 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18383 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18384 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18385 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18386 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18387 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18388 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18389 case X86ISD::VSHL: return "X86ISD::VSHL";
18390 case X86ISD::VSRL: return "X86ISD::VSRL";
18391 case X86ISD::VSRA: return "X86ISD::VSRA";
18392 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18393 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18394 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18395 case X86ISD::CMPP: return "X86ISD::CMPP";
18396 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18397 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18398 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18399 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18400 case X86ISD::ADD: return "X86ISD::ADD";
18401 case X86ISD::SUB: return "X86ISD::SUB";
18402 case X86ISD::ADC: return "X86ISD::ADC";
18403 case X86ISD::SBB: return "X86ISD::SBB";
18404 case X86ISD::SMUL: return "X86ISD::SMUL";
18405 case X86ISD::UMUL: return "X86ISD::UMUL";
18406 case X86ISD::INC: return "X86ISD::INC";
18407 case X86ISD::DEC: return "X86ISD::DEC";
18408 case X86ISD::OR: return "X86ISD::OR";
18409 case X86ISD::XOR: return "X86ISD::XOR";
18410 case X86ISD::AND: return "X86ISD::AND";
18411 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18412 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18413 case X86ISD::PTEST: return "X86ISD::PTEST";
18414 case X86ISD::TESTP: return "X86ISD::TESTP";
18415 case X86ISD::TESTM: return "X86ISD::TESTM";
18416 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18417 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18418 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18419 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18420 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18421 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18422 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18423 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18424 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18425 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18426 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18427 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18428 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18429 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18430 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18431 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18432 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18433 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18434 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18435 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18436 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18437 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18438 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18439 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18440 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18441 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18442 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18443 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18444 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18445 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18446 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18447 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18448 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18449 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18450 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18451 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18452 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18453 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18454 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18455 case X86ISD::SAHF: return "X86ISD::SAHF";
18456 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18457 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18458 case X86ISD::FMADD: return "X86ISD::FMADD";
18459 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18460 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18461 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18462 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18463 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18464 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18465 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18466 case X86ISD::XTEST: return "X86ISD::XTEST";
18470 // isLegalAddressingMode - Return true if the addressing mode represented
18471 // by AM is legal for this target, for a load/store of the specified type.
18472 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18474 // X86 supports extremely general addressing modes.
18475 CodeModel::Model M = getTargetMachine().getCodeModel();
18476 Reloc::Model R = getTargetMachine().getRelocationModel();
18478 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18479 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18484 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18486 // If a reference to this global requires an extra load, we can't fold it.
18487 if (isGlobalStubReference(GVFlags))
18490 // If BaseGV requires a register for the PIC base, we cannot also have a
18491 // BaseReg specified.
18492 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18495 // If lower 4G is not available, then we must use rip-relative addressing.
18496 if ((M != CodeModel::Small || R != Reloc::Static) &&
18497 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18501 switch (AM.Scale) {
18507 // These scales always work.
18512 // These scales are formed with basereg+scalereg. Only accept if there is
18517 default: // Other stuff never works.
18524 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18525 unsigned Bits = Ty->getScalarSizeInBits();
18527 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18528 // particularly cheaper than those without.
18532 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18533 // variable shifts just as cheap as scalar ones.
18534 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18537 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18538 // fully general vector.
18542 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18543 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18545 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18546 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18547 return NumBits1 > NumBits2;
18550 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18551 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18554 if (!isTypeLegal(EVT::getEVT(Ty1)))
18557 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18559 // Assuming the caller doesn't have a zeroext or signext return parameter,
18560 // truncation all the way down to i1 is valid.
18564 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18565 return isInt<32>(Imm);
18568 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18569 // Can also use sub to handle negated immediates.
18570 return isInt<32>(Imm);
18573 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18574 if (!VT1.isInteger() || !VT2.isInteger())
18576 unsigned NumBits1 = VT1.getSizeInBits();
18577 unsigned NumBits2 = VT2.getSizeInBits();
18578 return NumBits1 > NumBits2;
18581 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18582 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18583 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18586 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18587 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18588 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18591 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18592 EVT VT1 = Val.getValueType();
18593 if (isZExtFree(VT1, VT2))
18596 if (Val.getOpcode() != ISD::LOAD)
18599 if (!VT1.isSimple() || !VT1.isInteger() ||
18600 !VT2.isSimple() || !VT2.isInteger())
18603 switch (VT1.getSimpleVT().SimpleTy) {
18608 // X86 has 8, 16, and 32-bit zero-extending loads.
18616 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18617 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18620 VT = VT.getScalarType();
18622 if (!VT.isSimple())
18625 switch (VT.getSimpleVT().SimpleTy) {
18636 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18637 // i16 instructions are longer (0x66 prefix) and potentially slower.
18638 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18641 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18642 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18643 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18644 /// are assumed to be legal.
18646 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18648 if (!VT.isSimple())
18651 MVT SVT = VT.getSimpleVT();
18653 // Very little shuffling can be done for 64-bit vectors right now.
18654 if (VT.getSizeInBits() == 64)
18657 // If this is a single-input shuffle with no 128 bit lane crossings we can
18658 // lower it into pshufb.
18659 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18660 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18661 bool isLegal = true;
18662 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18663 if (M[I] >= (int)SVT.getVectorNumElements() ||
18664 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18673 // FIXME: blends, shifts.
18674 return (SVT.getVectorNumElements() == 2 ||
18675 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18676 isMOVLMask(M, SVT) ||
18677 isMOVHLPSMask(M, SVT) ||
18678 isSHUFPMask(M, SVT) ||
18679 isPSHUFDMask(M, SVT) ||
18680 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18681 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18682 isPALIGNRMask(M, SVT, Subtarget) ||
18683 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18684 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18685 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18686 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18687 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18691 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18693 if (!VT.isSimple())
18696 MVT SVT = VT.getSimpleVT();
18697 unsigned NumElts = SVT.getVectorNumElements();
18698 // FIXME: This collection of masks seems suspect.
18701 if (NumElts == 4 && SVT.is128BitVector()) {
18702 return (isMOVLMask(Mask, SVT) ||
18703 isCommutedMOVLMask(Mask, SVT, true) ||
18704 isSHUFPMask(Mask, SVT) ||
18705 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18710 //===----------------------------------------------------------------------===//
18711 // X86 Scheduler Hooks
18712 //===----------------------------------------------------------------------===//
18714 /// Utility function to emit xbegin specifying the start of an RTM region.
18715 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18716 const TargetInstrInfo *TII) {
18717 DebugLoc DL = MI->getDebugLoc();
18719 const BasicBlock *BB = MBB->getBasicBlock();
18720 MachineFunction::iterator I = MBB;
18723 // For the v = xbegin(), we generate
18734 MachineBasicBlock *thisMBB = MBB;
18735 MachineFunction *MF = MBB->getParent();
18736 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18737 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18738 MF->insert(I, mainMBB);
18739 MF->insert(I, sinkMBB);
18741 // Transfer the remainder of BB and its successor edges to sinkMBB.
18742 sinkMBB->splice(sinkMBB->begin(), MBB,
18743 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18744 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18748 // # fallthrough to mainMBB
18749 // # abortion to sinkMBB
18750 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18751 thisMBB->addSuccessor(mainMBB);
18752 thisMBB->addSuccessor(sinkMBB);
18756 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18757 mainMBB->addSuccessor(sinkMBB);
18760 // EAX is live into the sinkMBB
18761 sinkMBB->addLiveIn(X86::EAX);
18762 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18763 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18766 MI->eraseFromParent();
18770 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18771 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18772 // in the .td file.
18773 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18774 const TargetInstrInfo *TII) {
18776 switch (MI->getOpcode()) {
18777 default: llvm_unreachable("illegal opcode!");
18778 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18779 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18780 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18781 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18782 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18783 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18784 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18785 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18788 DebugLoc dl = MI->getDebugLoc();
18789 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18791 unsigned NumArgs = MI->getNumOperands();
18792 for (unsigned i = 1; i < NumArgs; ++i) {
18793 MachineOperand &Op = MI->getOperand(i);
18794 if (!(Op.isReg() && Op.isImplicit()))
18795 MIB.addOperand(Op);
18797 if (MI->hasOneMemOperand())
18798 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18800 BuildMI(*BB, MI, dl,
18801 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18802 .addReg(X86::XMM0);
18804 MI->eraseFromParent();
18808 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18809 // defs in an instruction pattern
18810 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18811 const TargetInstrInfo *TII) {
18813 switch (MI->getOpcode()) {
18814 default: llvm_unreachable("illegal opcode!");
18815 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18816 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18817 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18818 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18819 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18820 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18821 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18822 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18825 DebugLoc dl = MI->getDebugLoc();
18826 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18828 unsigned NumArgs = MI->getNumOperands(); // remove the results
18829 for (unsigned i = 1; i < NumArgs; ++i) {
18830 MachineOperand &Op = MI->getOperand(i);
18831 if (!(Op.isReg() && Op.isImplicit()))
18832 MIB.addOperand(Op);
18834 if (MI->hasOneMemOperand())
18835 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18837 BuildMI(*BB, MI, dl,
18838 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18841 MI->eraseFromParent();
18845 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18846 const TargetInstrInfo *TII,
18847 const X86Subtarget* Subtarget) {
18848 DebugLoc dl = MI->getDebugLoc();
18850 // Address into RAX/EAX, other two args into ECX, EDX.
18851 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18852 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18853 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18854 for (int i = 0; i < X86::AddrNumOperands; ++i)
18855 MIB.addOperand(MI->getOperand(i));
18857 unsigned ValOps = X86::AddrNumOperands;
18858 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18859 .addReg(MI->getOperand(ValOps).getReg());
18860 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18861 .addReg(MI->getOperand(ValOps+1).getReg());
18863 // The instruction doesn't actually take any operands though.
18864 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18866 MI->eraseFromParent(); // The pseudo is gone now.
18870 MachineBasicBlock *
18871 X86TargetLowering::EmitVAARG64WithCustomInserter(
18873 MachineBasicBlock *MBB) const {
18874 // Emit va_arg instruction on X86-64.
18876 // Operands to this pseudo-instruction:
18877 // 0 ) Output : destination address (reg)
18878 // 1-5) Input : va_list address (addr, i64mem)
18879 // 6 ) ArgSize : Size (in bytes) of vararg type
18880 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18881 // 8 ) Align : Alignment of type
18882 // 9 ) EFLAGS (implicit-def)
18884 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18885 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18887 unsigned DestReg = MI->getOperand(0).getReg();
18888 MachineOperand &Base = MI->getOperand(1);
18889 MachineOperand &Scale = MI->getOperand(2);
18890 MachineOperand &Index = MI->getOperand(3);
18891 MachineOperand &Disp = MI->getOperand(4);
18892 MachineOperand &Segment = MI->getOperand(5);
18893 unsigned ArgSize = MI->getOperand(6).getImm();
18894 unsigned ArgMode = MI->getOperand(7).getImm();
18895 unsigned Align = MI->getOperand(8).getImm();
18897 // Memory Reference
18898 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18899 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18900 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18902 // Machine Information
18903 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18904 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18905 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18906 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18907 DebugLoc DL = MI->getDebugLoc();
18909 // struct va_list {
18912 // i64 overflow_area (address)
18913 // i64 reg_save_area (address)
18915 // sizeof(va_list) = 24
18916 // alignment(va_list) = 8
18918 unsigned TotalNumIntRegs = 6;
18919 unsigned TotalNumXMMRegs = 8;
18920 bool UseGPOffset = (ArgMode == 1);
18921 bool UseFPOffset = (ArgMode == 2);
18922 unsigned MaxOffset = TotalNumIntRegs * 8 +
18923 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18925 /* Align ArgSize to a multiple of 8 */
18926 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18927 bool NeedsAlign = (Align > 8);
18929 MachineBasicBlock *thisMBB = MBB;
18930 MachineBasicBlock *overflowMBB;
18931 MachineBasicBlock *offsetMBB;
18932 MachineBasicBlock *endMBB;
18934 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18935 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18936 unsigned OffsetReg = 0;
18938 if (!UseGPOffset && !UseFPOffset) {
18939 // If we only pull from the overflow region, we don't create a branch.
18940 // We don't need to alter control flow.
18941 OffsetDestReg = 0; // unused
18942 OverflowDestReg = DestReg;
18944 offsetMBB = nullptr;
18945 overflowMBB = thisMBB;
18948 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18949 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18950 // If not, pull from overflow_area. (branch to overflowMBB)
18955 // offsetMBB overflowMBB
18960 // Registers for the PHI in endMBB
18961 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18962 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18964 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18965 MachineFunction *MF = MBB->getParent();
18966 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18967 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18968 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18970 MachineFunction::iterator MBBIter = MBB;
18973 // Insert the new basic blocks
18974 MF->insert(MBBIter, offsetMBB);
18975 MF->insert(MBBIter, overflowMBB);
18976 MF->insert(MBBIter, endMBB);
18978 // Transfer the remainder of MBB and its successor edges to endMBB.
18979 endMBB->splice(endMBB->begin(), thisMBB,
18980 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18981 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18983 // Make offsetMBB and overflowMBB successors of thisMBB
18984 thisMBB->addSuccessor(offsetMBB);
18985 thisMBB->addSuccessor(overflowMBB);
18987 // endMBB is a successor of both offsetMBB and overflowMBB
18988 offsetMBB->addSuccessor(endMBB);
18989 overflowMBB->addSuccessor(endMBB);
18991 // Load the offset value into a register
18992 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18993 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18997 .addDisp(Disp, UseFPOffset ? 4 : 0)
18998 .addOperand(Segment)
18999 .setMemRefs(MMOBegin, MMOEnd);
19001 // Check if there is enough room left to pull this argument.
19002 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19004 .addImm(MaxOffset + 8 - ArgSizeA8);
19006 // Branch to "overflowMBB" if offset >= max
19007 // Fall through to "offsetMBB" otherwise
19008 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19009 .addMBB(overflowMBB);
19012 // In offsetMBB, emit code to use the reg_save_area.
19014 assert(OffsetReg != 0);
19016 // Read the reg_save_area address.
19017 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19018 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19023 .addOperand(Segment)
19024 .setMemRefs(MMOBegin, MMOEnd);
19026 // Zero-extend the offset
19027 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19028 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19031 .addImm(X86::sub_32bit);
19033 // Add the offset to the reg_save_area to get the final address.
19034 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19035 .addReg(OffsetReg64)
19036 .addReg(RegSaveReg);
19038 // Compute the offset for the next argument
19039 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19040 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19042 .addImm(UseFPOffset ? 16 : 8);
19044 // Store it back into the va_list.
19045 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19049 .addDisp(Disp, UseFPOffset ? 4 : 0)
19050 .addOperand(Segment)
19051 .addReg(NextOffsetReg)
19052 .setMemRefs(MMOBegin, MMOEnd);
19055 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19060 // Emit code to use overflow area
19063 // Load the overflow_area address into a register.
19064 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19065 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19070 .addOperand(Segment)
19071 .setMemRefs(MMOBegin, MMOEnd);
19073 // If we need to align it, do so. Otherwise, just copy the address
19074 // to OverflowDestReg.
19076 // Align the overflow address
19077 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19078 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19080 // aligned_addr = (addr + (align-1)) & ~(align-1)
19081 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19082 .addReg(OverflowAddrReg)
19085 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19087 .addImm(~(uint64_t)(Align-1));
19089 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19090 .addReg(OverflowAddrReg);
19093 // Compute the next overflow address after this argument.
19094 // (the overflow address should be kept 8-byte aligned)
19095 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19096 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19097 .addReg(OverflowDestReg)
19098 .addImm(ArgSizeA8);
19100 // Store the new overflow address.
19101 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19106 .addOperand(Segment)
19107 .addReg(NextAddrReg)
19108 .setMemRefs(MMOBegin, MMOEnd);
19110 // If we branched, emit the PHI to the front of endMBB.
19112 BuildMI(*endMBB, endMBB->begin(), DL,
19113 TII->get(X86::PHI), DestReg)
19114 .addReg(OffsetDestReg).addMBB(offsetMBB)
19115 .addReg(OverflowDestReg).addMBB(overflowMBB);
19118 // Erase the pseudo instruction
19119 MI->eraseFromParent();
19124 MachineBasicBlock *
19125 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19127 MachineBasicBlock *MBB) const {
19128 // Emit code to save XMM registers to the stack. The ABI says that the
19129 // number of registers to save is given in %al, so it's theoretically
19130 // possible to do an indirect jump trick to avoid saving all of them,
19131 // however this code takes a simpler approach and just executes all
19132 // of the stores if %al is non-zero. It's less code, and it's probably
19133 // easier on the hardware branch predictor, and stores aren't all that
19134 // expensive anyway.
19136 // Create the new basic blocks. One block contains all the XMM stores,
19137 // and one block is the final destination regardless of whether any
19138 // stores were performed.
19139 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19140 MachineFunction *F = MBB->getParent();
19141 MachineFunction::iterator MBBIter = MBB;
19143 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19144 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19145 F->insert(MBBIter, XMMSaveMBB);
19146 F->insert(MBBIter, EndMBB);
19148 // Transfer the remainder of MBB and its successor edges to EndMBB.
19149 EndMBB->splice(EndMBB->begin(), MBB,
19150 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19151 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19153 // The original block will now fall through to the XMM save block.
19154 MBB->addSuccessor(XMMSaveMBB);
19155 // The XMMSaveMBB will fall through to the end block.
19156 XMMSaveMBB->addSuccessor(EndMBB);
19158 // Now add the instructions.
19159 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19160 DebugLoc DL = MI->getDebugLoc();
19162 unsigned CountReg = MI->getOperand(0).getReg();
19163 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19164 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19166 if (!Subtarget->isTargetWin64()) {
19167 // If %al is 0, branch around the XMM save block.
19168 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19169 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19170 MBB->addSuccessor(EndMBB);
19173 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19174 // that was just emitted, but clearly shouldn't be "saved".
19175 assert((MI->getNumOperands() <= 3 ||
19176 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19177 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19178 && "Expected last argument to be EFLAGS");
19179 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19180 // In the XMM save block, save all the XMM argument registers.
19181 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19182 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19183 MachineMemOperand *MMO =
19184 F->getMachineMemOperand(
19185 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19186 MachineMemOperand::MOStore,
19187 /*Size=*/16, /*Align=*/16);
19188 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19189 .addFrameIndex(RegSaveFrameIndex)
19190 .addImm(/*Scale=*/1)
19191 .addReg(/*IndexReg=*/0)
19192 .addImm(/*Disp=*/Offset)
19193 .addReg(/*Segment=*/0)
19194 .addReg(MI->getOperand(i).getReg())
19195 .addMemOperand(MMO);
19198 MI->eraseFromParent(); // The pseudo instruction is gone now.
19203 // The EFLAGS operand of SelectItr might be missing a kill marker
19204 // because there were multiple uses of EFLAGS, and ISel didn't know
19205 // which to mark. Figure out whether SelectItr should have had a
19206 // kill marker, and set it if it should. Returns the correct kill
19208 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19209 MachineBasicBlock* BB,
19210 const TargetRegisterInfo* TRI) {
19211 // Scan forward through BB for a use/def of EFLAGS.
19212 MachineBasicBlock::iterator miI(std::next(SelectItr));
19213 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19214 const MachineInstr& mi = *miI;
19215 if (mi.readsRegister(X86::EFLAGS))
19217 if (mi.definesRegister(X86::EFLAGS))
19218 break; // Should have kill-flag - update below.
19221 // If we hit the end of the block, check whether EFLAGS is live into a
19223 if (miI == BB->end()) {
19224 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19225 sEnd = BB->succ_end();
19226 sItr != sEnd; ++sItr) {
19227 MachineBasicBlock* succ = *sItr;
19228 if (succ->isLiveIn(X86::EFLAGS))
19233 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19234 // out. SelectMI should have a kill flag on EFLAGS.
19235 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19239 MachineBasicBlock *
19240 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19241 MachineBasicBlock *BB) const {
19242 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19243 DebugLoc DL = MI->getDebugLoc();
19245 // To "insert" a SELECT_CC instruction, we actually have to insert the
19246 // diamond control-flow pattern. The incoming instruction knows the
19247 // destination vreg to set, the condition code register to branch on, the
19248 // true/false values to select between, and a branch opcode to use.
19249 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19250 MachineFunction::iterator It = BB;
19256 // cmpTY ccX, r1, r2
19258 // fallthrough --> copy0MBB
19259 MachineBasicBlock *thisMBB = BB;
19260 MachineFunction *F = BB->getParent();
19261 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19262 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19263 F->insert(It, copy0MBB);
19264 F->insert(It, sinkMBB);
19266 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19267 // live into the sink and copy blocks.
19268 const TargetRegisterInfo *TRI =
19269 BB->getParent()->getSubtarget().getRegisterInfo();
19270 if (!MI->killsRegister(X86::EFLAGS) &&
19271 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19272 copy0MBB->addLiveIn(X86::EFLAGS);
19273 sinkMBB->addLiveIn(X86::EFLAGS);
19276 // Transfer the remainder of BB and its successor edges to sinkMBB.
19277 sinkMBB->splice(sinkMBB->begin(), BB,
19278 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19279 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19281 // Add the true and fallthrough blocks as its successors.
19282 BB->addSuccessor(copy0MBB);
19283 BB->addSuccessor(sinkMBB);
19285 // Create the conditional branch instruction.
19287 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19288 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19291 // %FalseValue = ...
19292 // # fallthrough to sinkMBB
19293 copy0MBB->addSuccessor(sinkMBB);
19296 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19298 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19299 TII->get(X86::PHI), MI->getOperand(0).getReg())
19300 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19301 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19303 MI->eraseFromParent(); // The pseudo instruction is gone now.
19307 MachineBasicBlock *
19308 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19309 MachineBasicBlock *BB) const {
19310 MachineFunction *MF = BB->getParent();
19311 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19312 DebugLoc DL = MI->getDebugLoc();
19313 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19315 assert(MF->shouldSplitStack());
19317 const bool Is64Bit = Subtarget->is64Bit();
19318 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19320 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19321 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19324 // ... [Till the alloca]
19325 // If stacklet is not large enough, jump to mallocMBB
19328 // Allocate by subtracting from RSP
19329 // Jump to continueMBB
19332 // Allocate by call to runtime
19336 // [rest of original BB]
19339 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19340 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19341 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19343 MachineRegisterInfo &MRI = MF->getRegInfo();
19344 const TargetRegisterClass *AddrRegClass =
19345 getRegClassFor(getPointerTy());
19347 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19348 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19349 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19350 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19351 sizeVReg = MI->getOperand(1).getReg(),
19352 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19354 MachineFunction::iterator MBBIter = BB;
19357 MF->insert(MBBIter, bumpMBB);
19358 MF->insert(MBBIter, mallocMBB);
19359 MF->insert(MBBIter, continueMBB);
19361 continueMBB->splice(continueMBB->begin(), BB,
19362 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19363 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19365 // Add code to the main basic block to check if the stack limit has been hit,
19366 // and if so, jump to mallocMBB otherwise to bumpMBB.
19367 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19368 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19369 .addReg(tmpSPVReg).addReg(sizeVReg);
19370 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19371 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19372 .addReg(SPLimitVReg);
19373 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19375 // bumpMBB simply decreases the stack pointer, since we know the current
19376 // stacklet has enough space.
19377 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19378 .addReg(SPLimitVReg);
19379 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19380 .addReg(SPLimitVReg);
19381 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19383 // Calls into a routine in libgcc to allocate more space from the heap.
19384 const uint32_t *RegMask = MF->getTarget()
19385 .getSubtargetImpl()
19386 ->getRegisterInfo()
19387 ->getCallPreservedMask(CallingConv::C);
19389 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19391 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19392 .addExternalSymbol("__morestack_allocate_stack_space")
19393 .addRegMask(RegMask)
19394 .addReg(X86::RDI, RegState::Implicit)
19395 .addReg(X86::RAX, RegState::ImplicitDefine);
19396 } else if (Is64Bit) {
19397 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19399 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19400 .addExternalSymbol("__morestack_allocate_stack_space")
19401 .addRegMask(RegMask)
19402 .addReg(X86::EDI, RegState::Implicit)
19403 .addReg(X86::EAX, RegState::ImplicitDefine);
19405 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19407 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19408 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19409 .addExternalSymbol("__morestack_allocate_stack_space")
19410 .addRegMask(RegMask)
19411 .addReg(X86::EAX, RegState::ImplicitDefine);
19415 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19418 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19419 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19420 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19422 // Set up the CFG correctly.
19423 BB->addSuccessor(bumpMBB);
19424 BB->addSuccessor(mallocMBB);
19425 mallocMBB->addSuccessor(continueMBB);
19426 bumpMBB->addSuccessor(continueMBB);
19428 // Take care of the PHI nodes.
19429 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19430 MI->getOperand(0).getReg())
19431 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19432 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19434 // Delete the original pseudo instruction.
19435 MI->eraseFromParent();
19438 return continueMBB;
19441 MachineBasicBlock *
19442 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19443 MachineBasicBlock *BB) const {
19444 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19445 DebugLoc DL = MI->getDebugLoc();
19447 assert(!Subtarget->isTargetMacho());
19449 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19450 // non-trivial part is impdef of ESP.
19452 if (Subtarget->isTargetWin64()) {
19453 if (Subtarget->isTargetCygMing()) {
19454 // ___chkstk(Mingw64):
19455 // Clobbers R10, R11, RAX and EFLAGS.
19457 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19458 .addExternalSymbol("___chkstk")
19459 .addReg(X86::RAX, RegState::Implicit)
19460 .addReg(X86::RSP, RegState::Implicit)
19461 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19462 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19463 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19465 // __chkstk(MSVCRT): does not update stack pointer.
19466 // Clobbers R10, R11 and EFLAGS.
19467 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19468 .addExternalSymbol("__chkstk")
19469 .addReg(X86::RAX, RegState::Implicit)
19470 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19471 // RAX has the offset to be subtracted from RSP.
19472 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19477 const char *StackProbeSymbol =
19478 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19480 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19481 .addExternalSymbol(StackProbeSymbol)
19482 .addReg(X86::EAX, RegState::Implicit)
19483 .addReg(X86::ESP, RegState::Implicit)
19484 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19485 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19486 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19489 MI->eraseFromParent(); // The pseudo instruction is gone now.
19493 MachineBasicBlock *
19494 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19495 MachineBasicBlock *BB) const {
19496 // This is pretty easy. We're taking the value that we received from
19497 // our load from the relocation, sticking it in either RDI (x86-64)
19498 // or EAX and doing an indirect call. The return value will then
19499 // be in the normal return register.
19500 MachineFunction *F = BB->getParent();
19501 const X86InstrInfo *TII =
19502 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19503 DebugLoc DL = MI->getDebugLoc();
19505 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19506 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19508 // Get a register mask for the lowered call.
19509 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19510 // proper register mask.
19511 const uint32_t *RegMask = F->getTarget()
19512 .getSubtargetImpl()
19513 ->getRegisterInfo()
19514 ->getCallPreservedMask(CallingConv::C);
19515 if (Subtarget->is64Bit()) {
19516 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19517 TII->get(X86::MOV64rm), X86::RDI)
19519 .addImm(0).addReg(0)
19520 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19521 MI->getOperand(3).getTargetFlags())
19523 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19524 addDirectMem(MIB, X86::RDI);
19525 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19526 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19527 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19528 TII->get(X86::MOV32rm), X86::EAX)
19530 .addImm(0).addReg(0)
19531 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19532 MI->getOperand(3).getTargetFlags())
19534 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19535 addDirectMem(MIB, X86::EAX);
19536 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19538 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19539 TII->get(X86::MOV32rm), X86::EAX)
19540 .addReg(TII->getGlobalBaseReg(F))
19541 .addImm(0).addReg(0)
19542 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19543 MI->getOperand(3).getTargetFlags())
19545 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19546 addDirectMem(MIB, X86::EAX);
19547 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19550 MI->eraseFromParent(); // The pseudo instruction is gone now.
19554 MachineBasicBlock *
19555 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19556 MachineBasicBlock *MBB) const {
19557 DebugLoc DL = MI->getDebugLoc();
19558 MachineFunction *MF = MBB->getParent();
19559 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19560 MachineRegisterInfo &MRI = MF->getRegInfo();
19562 const BasicBlock *BB = MBB->getBasicBlock();
19563 MachineFunction::iterator I = MBB;
19566 // Memory Reference
19567 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19568 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19571 unsigned MemOpndSlot = 0;
19573 unsigned CurOp = 0;
19575 DstReg = MI->getOperand(CurOp++).getReg();
19576 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19577 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19578 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19579 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19581 MemOpndSlot = CurOp;
19583 MVT PVT = getPointerTy();
19584 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19585 "Invalid Pointer Size!");
19587 // For v = setjmp(buf), we generate
19590 // buf[LabelOffset] = restoreMBB
19591 // SjLjSetup restoreMBB
19597 // v = phi(main, restore)
19602 MachineBasicBlock *thisMBB = MBB;
19603 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19604 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19605 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19606 MF->insert(I, mainMBB);
19607 MF->insert(I, sinkMBB);
19608 MF->push_back(restoreMBB);
19610 MachineInstrBuilder MIB;
19612 // Transfer the remainder of BB and its successor edges to sinkMBB.
19613 sinkMBB->splice(sinkMBB->begin(), MBB,
19614 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19615 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19618 unsigned PtrStoreOpc = 0;
19619 unsigned LabelReg = 0;
19620 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19621 Reloc::Model RM = MF->getTarget().getRelocationModel();
19622 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19623 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19625 // Prepare IP either in reg or imm.
19626 if (!UseImmLabel) {
19627 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19628 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19629 LabelReg = MRI.createVirtualRegister(PtrRC);
19630 if (Subtarget->is64Bit()) {
19631 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19635 .addMBB(restoreMBB)
19638 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19639 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19640 .addReg(XII->getGlobalBaseReg(MF))
19643 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19647 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19649 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19650 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19651 if (i == X86::AddrDisp)
19652 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19654 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19657 MIB.addReg(LabelReg);
19659 MIB.addMBB(restoreMBB);
19660 MIB.setMemRefs(MMOBegin, MMOEnd);
19662 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19663 .addMBB(restoreMBB);
19665 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19666 MF->getSubtarget().getRegisterInfo());
19667 MIB.addRegMask(RegInfo->getNoPreservedMask());
19668 thisMBB->addSuccessor(mainMBB);
19669 thisMBB->addSuccessor(restoreMBB);
19673 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19674 mainMBB->addSuccessor(sinkMBB);
19677 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19678 TII->get(X86::PHI), DstReg)
19679 .addReg(mainDstReg).addMBB(mainMBB)
19680 .addReg(restoreDstReg).addMBB(restoreMBB);
19683 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19684 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19685 restoreMBB->addSuccessor(sinkMBB);
19687 MI->eraseFromParent();
19691 MachineBasicBlock *
19692 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19693 MachineBasicBlock *MBB) const {
19694 DebugLoc DL = MI->getDebugLoc();
19695 MachineFunction *MF = MBB->getParent();
19696 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19697 MachineRegisterInfo &MRI = MF->getRegInfo();
19699 // Memory Reference
19700 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19701 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19703 MVT PVT = getPointerTy();
19704 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19705 "Invalid Pointer Size!");
19707 const TargetRegisterClass *RC =
19708 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19709 unsigned Tmp = MRI.createVirtualRegister(RC);
19710 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19711 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19712 MF->getSubtarget().getRegisterInfo());
19713 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19714 unsigned SP = RegInfo->getStackRegister();
19716 MachineInstrBuilder MIB;
19718 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19719 const int64_t SPOffset = 2 * PVT.getStoreSize();
19721 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19722 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19725 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19726 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19727 MIB.addOperand(MI->getOperand(i));
19728 MIB.setMemRefs(MMOBegin, MMOEnd);
19730 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19731 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19732 if (i == X86::AddrDisp)
19733 MIB.addDisp(MI->getOperand(i), LabelOffset);
19735 MIB.addOperand(MI->getOperand(i));
19737 MIB.setMemRefs(MMOBegin, MMOEnd);
19739 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19740 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19741 if (i == X86::AddrDisp)
19742 MIB.addDisp(MI->getOperand(i), SPOffset);
19744 MIB.addOperand(MI->getOperand(i));
19746 MIB.setMemRefs(MMOBegin, MMOEnd);
19748 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19750 MI->eraseFromParent();
19754 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19755 // accumulator loops. Writing back to the accumulator allows the coalescer
19756 // to remove extra copies in the loop.
19757 MachineBasicBlock *
19758 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19759 MachineBasicBlock *MBB) const {
19760 MachineOperand &AddendOp = MI->getOperand(3);
19762 // Bail out early if the addend isn't a register - we can't switch these.
19763 if (!AddendOp.isReg())
19766 MachineFunction &MF = *MBB->getParent();
19767 MachineRegisterInfo &MRI = MF.getRegInfo();
19769 // Check whether the addend is defined by a PHI:
19770 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19771 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19772 if (!AddendDef.isPHI())
19775 // Look for the following pattern:
19777 // %addend = phi [%entry, 0], [%loop, %result]
19779 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19783 // %addend = phi [%entry, 0], [%loop, %result]
19785 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19787 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19788 assert(AddendDef.getOperand(i).isReg());
19789 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19790 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19791 if (&PHISrcInst == MI) {
19792 // Found a matching instruction.
19793 unsigned NewFMAOpc = 0;
19794 switch (MI->getOpcode()) {
19795 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19796 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19797 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19798 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19799 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19800 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19801 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19802 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19803 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19804 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19805 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19806 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19807 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19808 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19809 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19810 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19811 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19812 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19813 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19814 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19815 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19816 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19817 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19818 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19819 default: llvm_unreachable("Unrecognized FMA variant.");
19822 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19823 MachineInstrBuilder MIB =
19824 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19825 .addOperand(MI->getOperand(0))
19826 .addOperand(MI->getOperand(3))
19827 .addOperand(MI->getOperand(2))
19828 .addOperand(MI->getOperand(1));
19829 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19830 MI->eraseFromParent();
19837 MachineBasicBlock *
19838 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19839 MachineBasicBlock *BB) const {
19840 switch (MI->getOpcode()) {
19841 default: llvm_unreachable("Unexpected instr type to insert");
19842 case X86::TAILJMPd64:
19843 case X86::TAILJMPr64:
19844 case X86::TAILJMPm64:
19845 llvm_unreachable("TAILJMP64 would not be touched here.");
19846 case X86::TCRETURNdi64:
19847 case X86::TCRETURNri64:
19848 case X86::TCRETURNmi64:
19850 case X86::WIN_ALLOCA:
19851 return EmitLoweredWinAlloca(MI, BB);
19852 case X86::SEG_ALLOCA_32:
19853 case X86::SEG_ALLOCA_64:
19854 return EmitLoweredSegAlloca(MI, BB);
19855 case X86::TLSCall_32:
19856 case X86::TLSCall_64:
19857 return EmitLoweredTLSCall(MI, BB);
19858 case X86::CMOV_GR8:
19859 case X86::CMOV_FR32:
19860 case X86::CMOV_FR64:
19861 case X86::CMOV_V4F32:
19862 case X86::CMOV_V2F64:
19863 case X86::CMOV_V2I64:
19864 case X86::CMOV_V8F32:
19865 case X86::CMOV_V4F64:
19866 case X86::CMOV_V4I64:
19867 case X86::CMOV_V16F32:
19868 case X86::CMOV_V8F64:
19869 case X86::CMOV_V8I64:
19870 case X86::CMOV_GR16:
19871 case X86::CMOV_GR32:
19872 case X86::CMOV_RFP32:
19873 case X86::CMOV_RFP64:
19874 case X86::CMOV_RFP80:
19875 return EmitLoweredSelect(MI, BB);
19877 case X86::FP32_TO_INT16_IN_MEM:
19878 case X86::FP32_TO_INT32_IN_MEM:
19879 case X86::FP32_TO_INT64_IN_MEM:
19880 case X86::FP64_TO_INT16_IN_MEM:
19881 case X86::FP64_TO_INT32_IN_MEM:
19882 case X86::FP64_TO_INT64_IN_MEM:
19883 case X86::FP80_TO_INT16_IN_MEM:
19884 case X86::FP80_TO_INT32_IN_MEM:
19885 case X86::FP80_TO_INT64_IN_MEM: {
19886 MachineFunction *F = BB->getParent();
19887 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19888 DebugLoc DL = MI->getDebugLoc();
19890 // Change the floating point control register to use "round towards zero"
19891 // mode when truncating to an integer value.
19892 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19893 addFrameReference(BuildMI(*BB, MI, DL,
19894 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19896 // Load the old value of the high byte of the control word...
19898 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19899 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19902 // Set the high part to be round to zero...
19903 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19906 // Reload the modified control word now...
19907 addFrameReference(BuildMI(*BB, MI, DL,
19908 TII->get(X86::FLDCW16m)), CWFrameIdx);
19910 // Restore the memory image of control word to original value
19911 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19914 // Get the X86 opcode to use.
19916 switch (MI->getOpcode()) {
19917 default: llvm_unreachable("illegal opcode!");
19918 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19919 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19920 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19921 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19922 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19923 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19924 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19925 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19926 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19930 MachineOperand &Op = MI->getOperand(0);
19932 AM.BaseType = X86AddressMode::RegBase;
19933 AM.Base.Reg = Op.getReg();
19935 AM.BaseType = X86AddressMode::FrameIndexBase;
19936 AM.Base.FrameIndex = Op.getIndex();
19938 Op = MI->getOperand(1);
19940 AM.Scale = Op.getImm();
19941 Op = MI->getOperand(2);
19943 AM.IndexReg = Op.getImm();
19944 Op = MI->getOperand(3);
19945 if (Op.isGlobal()) {
19946 AM.GV = Op.getGlobal();
19948 AM.Disp = Op.getImm();
19950 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19951 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19953 // Reload the original control word now.
19954 addFrameReference(BuildMI(*BB, MI, DL,
19955 TII->get(X86::FLDCW16m)), CWFrameIdx);
19957 MI->eraseFromParent(); // The pseudo instruction is gone now.
19960 // String/text processing lowering.
19961 case X86::PCMPISTRM128REG:
19962 case X86::VPCMPISTRM128REG:
19963 case X86::PCMPISTRM128MEM:
19964 case X86::VPCMPISTRM128MEM:
19965 case X86::PCMPESTRM128REG:
19966 case X86::VPCMPESTRM128REG:
19967 case X86::PCMPESTRM128MEM:
19968 case X86::VPCMPESTRM128MEM:
19969 assert(Subtarget->hasSSE42() &&
19970 "Target must have SSE4.2 or AVX features enabled");
19971 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19973 // String/text processing lowering.
19974 case X86::PCMPISTRIREG:
19975 case X86::VPCMPISTRIREG:
19976 case X86::PCMPISTRIMEM:
19977 case X86::VPCMPISTRIMEM:
19978 case X86::PCMPESTRIREG:
19979 case X86::VPCMPESTRIREG:
19980 case X86::PCMPESTRIMEM:
19981 case X86::VPCMPESTRIMEM:
19982 assert(Subtarget->hasSSE42() &&
19983 "Target must have SSE4.2 or AVX features enabled");
19984 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19986 // Thread synchronization.
19988 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19993 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19995 case X86::VASTART_SAVE_XMM_REGS:
19996 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19998 case X86::VAARG_64:
19999 return EmitVAARG64WithCustomInserter(MI, BB);
20001 case X86::EH_SjLj_SetJmp32:
20002 case X86::EH_SjLj_SetJmp64:
20003 return emitEHSjLjSetJmp(MI, BB);
20005 case X86::EH_SjLj_LongJmp32:
20006 case X86::EH_SjLj_LongJmp64:
20007 return emitEHSjLjLongJmp(MI, BB);
20009 case TargetOpcode::STACKMAP:
20010 case TargetOpcode::PATCHPOINT:
20011 return emitPatchPoint(MI, BB);
20013 case X86::VFMADDPDr213r:
20014 case X86::VFMADDPSr213r:
20015 case X86::VFMADDSDr213r:
20016 case X86::VFMADDSSr213r:
20017 case X86::VFMSUBPDr213r:
20018 case X86::VFMSUBPSr213r:
20019 case X86::VFMSUBSDr213r:
20020 case X86::VFMSUBSSr213r:
20021 case X86::VFNMADDPDr213r:
20022 case X86::VFNMADDPSr213r:
20023 case X86::VFNMADDSDr213r:
20024 case X86::VFNMADDSSr213r:
20025 case X86::VFNMSUBPDr213r:
20026 case X86::VFNMSUBPSr213r:
20027 case X86::VFNMSUBSDr213r:
20028 case X86::VFNMSUBSSr213r:
20029 case X86::VFMADDPDr213rY:
20030 case X86::VFMADDPSr213rY:
20031 case X86::VFMSUBPDr213rY:
20032 case X86::VFMSUBPSr213rY:
20033 case X86::VFNMADDPDr213rY:
20034 case X86::VFNMADDPSr213rY:
20035 case X86::VFNMSUBPDr213rY:
20036 case X86::VFNMSUBPSr213rY:
20037 return emitFMA3Instr(MI, BB);
20041 //===----------------------------------------------------------------------===//
20042 // X86 Optimization Hooks
20043 //===----------------------------------------------------------------------===//
20045 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20048 const SelectionDAG &DAG,
20049 unsigned Depth) const {
20050 unsigned BitWidth = KnownZero.getBitWidth();
20051 unsigned Opc = Op.getOpcode();
20052 assert((Opc >= ISD::BUILTIN_OP_END ||
20053 Opc == ISD::INTRINSIC_WO_CHAIN ||
20054 Opc == ISD::INTRINSIC_W_CHAIN ||
20055 Opc == ISD::INTRINSIC_VOID) &&
20056 "Should use MaskedValueIsZero if you don't know whether Op"
20057 " is a target node!");
20059 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20073 // These nodes' second result is a boolean.
20074 if (Op.getResNo() == 0)
20077 case X86ISD::SETCC:
20078 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20080 case ISD::INTRINSIC_WO_CHAIN: {
20081 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20082 unsigned NumLoBits = 0;
20085 case Intrinsic::x86_sse_movmsk_ps:
20086 case Intrinsic::x86_avx_movmsk_ps_256:
20087 case Intrinsic::x86_sse2_movmsk_pd:
20088 case Intrinsic::x86_avx_movmsk_pd_256:
20089 case Intrinsic::x86_mmx_pmovmskb:
20090 case Intrinsic::x86_sse2_pmovmskb_128:
20091 case Intrinsic::x86_avx2_pmovmskb: {
20092 // High bits of movmskp{s|d}, pmovmskb are known zero.
20094 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20095 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20096 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20097 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20098 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20099 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20100 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20101 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20103 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20112 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20114 const SelectionDAG &,
20115 unsigned Depth) const {
20116 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20117 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20118 return Op.getValueType().getScalarType().getSizeInBits();
20124 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20125 /// node is a GlobalAddress + offset.
20126 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20127 const GlobalValue* &GA,
20128 int64_t &Offset) const {
20129 if (N->getOpcode() == X86ISD::Wrapper) {
20130 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20131 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20132 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20136 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20139 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20140 /// same as extracting the high 128-bit part of 256-bit vector and then
20141 /// inserting the result into the low part of a new 256-bit vector
20142 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20143 EVT VT = SVOp->getValueType(0);
20144 unsigned NumElems = VT.getVectorNumElements();
20146 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20147 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20148 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20149 SVOp->getMaskElt(j) >= 0)
20155 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20156 /// same as extracting the low 128-bit part of 256-bit vector and then
20157 /// inserting the result into the high part of a new 256-bit vector
20158 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20159 EVT VT = SVOp->getValueType(0);
20160 unsigned NumElems = VT.getVectorNumElements();
20162 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20163 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20164 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20165 SVOp->getMaskElt(j) >= 0)
20171 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20172 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20173 TargetLowering::DAGCombinerInfo &DCI,
20174 const X86Subtarget* Subtarget) {
20176 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20177 SDValue V1 = SVOp->getOperand(0);
20178 SDValue V2 = SVOp->getOperand(1);
20179 EVT VT = SVOp->getValueType(0);
20180 unsigned NumElems = VT.getVectorNumElements();
20182 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20183 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20187 // V UNDEF BUILD_VECTOR UNDEF
20189 // CONCAT_VECTOR CONCAT_VECTOR
20192 // RESULT: V + zero extended
20194 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20195 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20196 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20199 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20202 // To match the shuffle mask, the first half of the mask should
20203 // be exactly the first vector, and all the rest a splat with the
20204 // first element of the second one.
20205 for (unsigned i = 0; i != NumElems/2; ++i)
20206 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20207 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20210 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20211 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20212 if (Ld->hasNUsesOfValue(1, 0)) {
20213 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20214 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20216 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20218 Ld->getPointerInfo(),
20219 Ld->getAlignment(),
20220 false/*isVolatile*/, true/*ReadMem*/,
20221 false/*WriteMem*/);
20223 // Make sure the newly-created LOAD is in the same position as Ld in
20224 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20225 // and update uses of Ld's output chain to use the TokenFactor.
20226 if (Ld->hasAnyUseOfValue(1)) {
20227 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20228 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20229 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20230 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20231 SDValue(ResNode.getNode(), 1));
20234 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20238 // Emit a zeroed vector and insert the desired subvector on its
20240 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20241 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20242 return DCI.CombineTo(N, InsV);
20245 //===--------------------------------------------------------------------===//
20246 // Combine some shuffles into subvector extracts and inserts:
20249 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20250 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20251 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20252 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20253 return DCI.CombineTo(N, InsV);
20256 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20257 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20258 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20259 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20260 return DCI.CombineTo(N, InsV);
20266 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20269 /// This is the leaf of the recursive combinine below. When we have found some
20270 /// chain of single-use x86 shuffle instructions and accumulated the combined
20271 /// shuffle mask represented by them, this will try to pattern match that mask
20272 /// into either a single instruction if there is a special purpose instruction
20273 /// for this operation, or into a PSHUFB instruction which is a fully general
20274 /// instruction but should only be used to replace chains over a certain depth.
20275 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20276 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20277 TargetLowering::DAGCombinerInfo &DCI,
20278 const X86Subtarget *Subtarget) {
20279 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20281 // Find the operand that enters the chain. Note that multiple uses are OK
20282 // here, we're not going to remove the operand we find.
20283 SDValue Input = Op.getOperand(0);
20284 while (Input.getOpcode() == ISD::BITCAST)
20285 Input = Input.getOperand(0);
20287 MVT VT = Input.getSimpleValueType();
20288 MVT RootVT = Root.getSimpleValueType();
20291 // Just remove no-op shuffle masks.
20292 if (Mask.size() == 1) {
20293 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20298 // Use the float domain if the operand type is a floating point type.
20299 bool FloatDomain = VT.isFloatingPoint();
20301 // For floating point shuffles, we don't have free copies in the shuffle
20302 // instructions or the ability to load as part of the instruction, so
20303 // canonicalize their shuffles to UNPCK or MOV variants.
20305 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20306 // vectors because it can have a load folded into it that UNPCK cannot. This
20307 // doesn't preclude something switching to the shorter encoding post-RA.
20309 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20310 bool Lo = Mask.equals(0, 0);
20313 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20314 // is no slower than UNPCKLPD but has the option to fold the input operand
20315 // into even an unaligned memory load.
20316 if (Lo && Subtarget->hasSSE3()) {
20317 Shuffle = X86ISD::MOVDDUP;
20318 ShuffleVT = MVT::v2f64;
20320 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20321 // than the UNPCK variants.
20322 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20323 ShuffleVT = MVT::v4f32;
20325 if (Depth == 1 && Root->getOpcode() == Shuffle)
20326 return false; // Nothing to do!
20327 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20328 DCI.AddToWorklist(Op.getNode());
20329 if (Shuffle == X86ISD::MOVDDUP)
20330 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20332 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20333 DCI.AddToWorklist(Op.getNode());
20334 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20338 if (Subtarget->hasSSE3() &&
20339 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20340 bool Lo = Mask.equals(0, 0, 2, 2);
20341 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20342 MVT ShuffleVT = MVT::v4f32;
20343 if (Depth == 1 && Root->getOpcode() == Shuffle)
20344 return false; // Nothing to do!
20345 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20346 DCI.AddToWorklist(Op.getNode());
20347 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20348 DCI.AddToWorklist(Op.getNode());
20349 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20353 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20354 bool Lo = Mask.equals(0, 0, 1, 1);
20355 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20356 MVT ShuffleVT = MVT::v4f32;
20357 if (Depth == 1 && Root->getOpcode() == Shuffle)
20358 return false; // Nothing to do!
20359 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20360 DCI.AddToWorklist(Op.getNode());
20361 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20362 DCI.AddToWorklist(Op.getNode());
20363 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20369 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20370 // variants as none of these have single-instruction variants that are
20371 // superior to the UNPCK formulation.
20372 if (!FloatDomain &&
20373 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20374 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20375 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20376 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20378 bool Lo = Mask[0] == 0;
20379 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20380 if (Depth == 1 && Root->getOpcode() == Shuffle)
20381 return false; // Nothing to do!
20383 switch (Mask.size()) {
20385 ShuffleVT = MVT::v8i16;
20388 ShuffleVT = MVT::v16i8;
20391 llvm_unreachable("Impossible mask size!");
20393 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20394 DCI.AddToWorklist(Op.getNode());
20395 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20396 DCI.AddToWorklist(Op.getNode());
20397 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20402 // Don't try to re-form single instruction chains under any circumstances now
20403 // that we've done encoding canonicalization for them.
20407 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20408 // can replace them with a single PSHUFB instruction profitably. Intel's
20409 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20410 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20411 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20412 SmallVector<SDValue, 16> PSHUFBMask;
20413 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20414 int Ratio = 16 / Mask.size();
20415 for (unsigned i = 0; i < 16; ++i) {
20416 if (Mask[i / Ratio] == SM_SentinelUndef) {
20417 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20420 int M = Mask[i / Ratio] != SM_SentinelZero
20421 ? Ratio * Mask[i / Ratio] + i % Ratio
20423 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20425 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20426 DCI.AddToWorklist(Op.getNode());
20427 SDValue PSHUFBMaskOp =
20428 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20429 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20430 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20431 DCI.AddToWorklist(Op.getNode());
20432 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20437 // Failed to find any combines.
20441 /// \brief Fully generic combining of x86 shuffle instructions.
20443 /// This should be the last combine run over the x86 shuffle instructions. Once
20444 /// they have been fully optimized, this will recursively consider all chains
20445 /// of single-use shuffle instructions, build a generic model of the cumulative
20446 /// shuffle operation, and check for simpler instructions which implement this
20447 /// operation. We use this primarily for two purposes:
20449 /// 1) Collapse generic shuffles to specialized single instructions when
20450 /// equivalent. In most cases, this is just an encoding size win, but
20451 /// sometimes we will collapse multiple generic shuffles into a single
20452 /// special-purpose shuffle.
20453 /// 2) Look for sequences of shuffle instructions with 3 or more total
20454 /// instructions, and replace them with the slightly more expensive SSSE3
20455 /// PSHUFB instruction if available. We do this as the last combining step
20456 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20457 /// a suitable short sequence of other instructions. The PHUFB will either
20458 /// use a register or have to read from memory and so is slightly (but only
20459 /// slightly) more expensive than the other shuffle instructions.
20461 /// Because this is inherently a quadratic operation (for each shuffle in
20462 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20463 /// This should never be an issue in practice as the shuffle lowering doesn't
20464 /// produce sequences of more than 8 instructions.
20466 /// FIXME: We will currently miss some cases where the redundant shuffling
20467 /// would simplify under the threshold for PSHUFB formation because of
20468 /// combine-ordering. To fix this, we should do the redundant instruction
20469 /// combining in this recursive walk.
20470 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20471 ArrayRef<int> RootMask,
20472 int Depth, bool HasPSHUFB,
20474 TargetLowering::DAGCombinerInfo &DCI,
20475 const X86Subtarget *Subtarget) {
20476 // Bound the depth of our recursive combine because this is ultimately
20477 // quadratic in nature.
20481 // Directly rip through bitcasts to find the underlying operand.
20482 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20483 Op = Op.getOperand(0);
20485 MVT VT = Op.getSimpleValueType();
20486 if (!VT.isVector())
20487 return false; // Bail if we hit a non-vector.
20488 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20489 // version should be added.
20490 if (VT.getSizeInBits() != 128)
20493 assert(Root.getSimpleValueType().isVector() &&
20494 "Shuffles operate on vector types!");
20495 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20496 "Can only combine shuffles of the same vector register size.");
20498 if (!isTargetShuffle(Op.getOpcode()))
20500 SmallVector<int, 16> OpMask;
20502 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20503 // We only can combine unary shuffles which we can decode the mask for.
20504 if (!HaveMask || !IsUnary)
20507 assert(VT.getVectorNumElements() == OpMask.size() &&
20508 "Different mask size from vector size!");
20509 assert(((RootMask.size() > OpMask.size() &&
20510 RootMask.size() % OpMask.size() == 0) ||
20511 (OpMask.size() > RootMask.size() &&
20512 OpMask.size() % RootMask.size() == 0) ||
20513 OpMask.size() == RootMask.size()) &&
20514 "The smaller number of elements must divide the larger.");
20515 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20516 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20517 assert(((RootRatio == 1 && OpRatio == 1) ||
20518 (RootRatio == 1) != (OpRatio == 1)) &&
20519 "Must not have a ratio for both incoming and op masks!");
20521 SmallVector<int, 16> Mask;
20522 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20524 // Merge this shuffle operation's mask into our accumulated mask. Note that
20525 // this shuffle's mask will be the first applied to the input, followed by the
20526 // root mask to get us all the way to the root value arrangement. The reason
20527 // for this order is that we are recursing up the operation chain.
20528 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20529 int RootIdx = i / RootRatio;
20530 if (RootMask[RootIdx] < 0) {
20531 // This is a zero or undef lane, we're done.
20532 Mask.push_back(RootMask[RootIdx]);
20536 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20537 int OpIdx = RootMaskedIdx / OpRatio;
20538 if (OpMask[OpIdx] < 0) {
20539 // The incoming lanes are zero or undef, it doesn't matter which ones we
20541 Mask.push_back(OpMask[OpIdx]);
20545 // Ok, we have non-zero lanes, map them through.
20546 Mask.push_back(OpMask[OpIdx] * OpRatio +
20547 RootMaskedIdx % OpRatio);
20550 // See if we can recurse into the operand to combine more things.
20551 switch (Op.getOpcode()) {
20552 case X86ISD::PSHUFB:
20554 case X86ISD::PSHUFD:
20555 case X86ISD::PSHUFHW:
20556 case X86ISD::PSHUFLW:
20557 if (Op.getOperand(0).hasOneUse() &&
20558 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20559 HasPSHUFB, DAG, DCI, Subtarget))
20563 case X86ISD::UNPCKL:
20564 case X86ISD::UNPCKH:
20565 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20566 // We can't check for single use, we have to check that this shuffle is the only user.
20567 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20568 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20569 HasPSHUFB, DAG, DCI, Subtarget))
20574 // Minor canonicalization of the accumulated shuffle mask to make it easier
20575 // to match below. All this does is detect masks with squential pairs of
20576 // elements, and shrink them to the half-width mask. It does this in a loop
20577 // so it will reduce the size of the mask to the minimal width mask which
20578 // performs an equivalent shuffle.
20579 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20580 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20581 Mask[i] = Mask[2 * i] / 2;
20582 Mask.resize(Mask.size() / 2);
20585 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20589 /// \brief Get the PSHUF-style mask from PSHUF node.
20591 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20592 /// PSHUF-style masks that can be reused with such instructions.
20593 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20594 SmallVector<int, 4> Mask;
20596 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20600 switch (N.getOpcode()) {
20601 case X86ISD::PSHUFD:
20603 case X86ISD::PSHUFLW:
20606 case X86ISD::PSHUFHW:
20607 Mask.erase(Mask.begin(), Mask.begin() + 4);
20608 for (int &M : Mask)
20612 llvm_unreachable("No valid shuffle instruction found!");
20616 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20618 /// We walk up the chain and look for a combinable shuffle, skipping over
20619 /// shuffles that we could hoist this shuffle's transformation past without
20620 /// altering anything.
20622 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20624 TargetLowering::DAGCombinerInfo &DCI) {
20625 assert(N.getOpcode() == X86ISD::PSHUFD &&
20626 "Called with something other than an x86 128-bit half shuffle!");
20629 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20630 // of the shuffles in the chain so that we can form a fresh chain to replace
20632 SmallVector<SDValue, 8> Chain;
20633 SDValue V = N.getOperand(0);
20634 for (; V.hasOneUse(); V = V.getOperand(0)) {
20635 switch (V.getOpcode()) {
20637 return SDValue(); // Nothing combined!
20640 // Skip bitcasts as we always know the type for the target specific
20644 case X86ISD::PSHUFD:
20645 // Found another dword shuffle.
20648 case X86ISD::PSHUFLW:
20649 // Check that the low words (being shuffled) are the identity in the
20650 // dword shuffle, and the high words are self-contained.
20651 if (Mask[0] != 0 || Mask[1] != 1 ||
20652 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20655 Chain.push_back(V);
20658 case X86ISD::PSHUFHW:
20659 // Check that the high words (being shuffled) are the identity in the
20660 // dword shuffle, and the low words are self-contained.
20661 if (Mask[2] != 2 || Mask[3] != 3 ||
20662 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20665 Chain.push_back(V);
20668 case X86ISD::UNPCKL:
20669 case X86ISD::UNPCKH:
20670 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20671 // shuffle into a preceding word shuffle.
20672 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20675 // Search for a half-shuffle which we can combine with.
20676 unsigned CombineOp =
20677 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20678 if (V.getOperand(0) != V.getOperand(1) ||
20679 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20681 Chain.push_back(V);
20682 V = V.getOperand(0);
20684 switch (V.getOpcode()) {
20686 return SDValue(); // Nothing to combine.
20688 case X86ISD::PSHUFLW:
20689 case X86ISD::PSHUFHW:
20690 if (V.getOpcode() == CombineOp)
20693 Chain.push_back(V);
20697 V = V.getOperand(0);
20701 } while (V.hasOneUse());
20704 // Break out of the loop if we break out of the switch.
20708 if (!V.hasOneUse())
20709 // We fell out of the loop without finding a viable combining instruction.
20712 // Merge this node's mask and our incoming mask.
20713 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20714 for (int &M : Mask)
20716 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20717 getV4X86ShuffleImm8ForMask(Mask, DAG));
20719 // Rebuild the chain around this new shuffle.
20720 while (!Chain.empty()) {
20721 SDValue W = Chain.pop_back_val();
20723 if (V.getValueType() != W.getOperand(0).getValueType())
20724 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20726 switch (W.getOpcode()) {
20728 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20730 case X86ISD::UNPCKL:
20731 case X86ISD::UNPCKH:
20732 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20735 case X86ISD::PSHUFD:
20736 case X86ISD::PSHUFLW:
20737 case X86ISD::PSHUFHW:
20738 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20742 if (V.getValueType() != N.getValueType())
20743 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20745 // Return the new chain to replace N.
20749 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20751 /// We walk up the chain, skipping shuffles of the other half and looking
20752 /// through shuffles which switch halves trying to find a shuffle of the same
20753 /// pair of dwords.
20754 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20756 TargetLowering::DAGCombinerInfo &DCI) {
20758 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20759 "Called with something other than an x86 128-bit half shuffle!");
20761 unsigned CombineOpcode = N.getOpcode();
20763 // Walk up a single-use chain looking for a combinable shuffle.
20764 SDValue V = N.getOperand(0);
20765 for (; V.hasOneUse(); V = V.getOperand(0)) {
20766 switch (V.getOpcode()) {
20768 return false; // Nothing combined!
20771 // Skip bitcasts as we always know the type for the target specific
20775 case X86ISD::PSHUFLW:
20776 case X86ISD::PSHUFHW:
20777 if (V.getOpcode() == CombineOpcode)
20780 // Other-half shuffles are no-ops.
20783 // Break out of the loop if we break out of the switch.
20787 if (!V.hasOneUse())
20788 // We fell out of the loop without finding a viable combining instruction.
20791 // Combine away the bottom node as its shuffle will be accumulated into
20792 // a preceding shuffle.
20793 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20795 // Record the old value.
20798 // Merge this node's mask and our incoming mask (adjusted to account for all
20799 // the pshufd instructions encountered).
20800 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20801 for (int &M : Mask)
20803 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20804 getV4X86ShuffleImm8ForMask(Mask, DAG));
20806 // Check that the shuffles didn't cancel each other out. If not, we need to
20807 // combine to the new one.
20809 // Replace the combinable shuffle with the combined one, updating all users
20810 // so that we re-evaluate the chain here.
20811 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20816 /// \brief Try to combine x86 target specific shuffles.
20817 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20818 TargetLowering::DAGCombinerInfo &DCI,
20819 const X86Subtarget *Subtarget) {
20821 MVT VT = N.getSimpleValueType();
20822 SmallVector<int, 4> Mask;
20824 switch (N.getOpcode()) {
20825 case X86ISD::PSHUFD:
20826 case X86ISD::PSHUFLW:
20827 case X86ISD::PSHUFHW:
20828 Mask = getPSHUFShuffleMask(N);
20829 assert(Mask.size() == 4);
20835 // Nuke no-op shuffles that show up after combining.
20836 if (isNoopShuffleMask(Mask))
20837 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20839 // Look for simplifications involving one or two shuffle instructions.
20840 SDValue V = N.getOperand(0);
20841 switch (N.getOpcode()) {
20844 case X86ISD::PSHUFLW:
20845 case X86ISD::PSHUFHW:
20846 assert(VT == MVT::v8i16);
20849 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20850 return SDValue(); // We combined away this shuffle, so we're done.
20852 // See if this reduces to a PSHUFD which is no more expensive and can
20853 // combine with more operations.
20854 if (canWidenShuffleElements(Mask)) {
20855 int DMask[] = {-1, -1, -1, -1};
20856 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20857 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20858 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20859 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20860 DCI.AddToWorklist(V.getNode());
20861 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20862 getV4X86ShuffleImm8ForMask(DMask, DAG));
20863 DCI.AddToWorklist(V.getNode());
20864 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20867 // Look for shuffle patterns which can be implemented as a single unpack.
20868 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20869 // only works when we have a PSHUFD followed by two half-shuffles.
20870 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20871 (V.getOpcode() == X86ISD::PSHUFLW ||
20872 V.getOpcode() == X86ISD::PSHUFHW) &&
20873 V.getOpcode() != N.getOpcode() &&
20875 SDValue D = V.getOperand(0);
20876 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20877 D = D.getOperand(0);
20878 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20879 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20880 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20881 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20882 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20884 for (int i = 0; i < 4; ++i) {
20885 WordMask[i + NOffset] = Mask[i] + NOffset;
20886 WordMask[i + VOffset] = VMask[i] + VOffset;
20888 // Map the word mask through the DWord mask.
20890 for (int i = 0; i < 8; ++i)
20891 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20892 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20893 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20894 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20895 std::begin(UnpackLoMask)) ||
20896 std::equal(std::begin(MappedMask), std::end(MappedMask),
20897 std::begin(UnpackHiMask))) {
20898 // We can replace all three shuffles with an unpack.
20899 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20900 DCI.AddToWorklist(V.getNode());
20901 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20903 DL, MVT::v8i16, V, V);
20910 case X86ISD::PSHUFD:
20911 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20920 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20922 /// We combine this directly on the abstract vector shuffle nodes so it is
20923 /// easier to generically match. We also insert dummy vector shuffle nodes for
20924 /// the operands which explicitly discard the lanes which are unused by this
20925 /// operation to try to flow through the rest of the combiner the fact that
20926 /// they're unused.
20927 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20929 EVT VT = N->getValueType(0);
20931 // We only handle target-independent shuffles.
20932 // FIXME: It would be easy and harmless to use the target shuffle mask
20933 // extraction tool to support more.
20934 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20937 auto *SVN = cast<ShuffleVectorSDNode>(N);
20938 ArrayRef<int> Mask = SVN->getMask();
20939 SDValue V1 = N->getOperand(0);
20940 SDValue V2 = N->getOperand(1);
20942 // We require the first shuffle operand to be the SUB node, and the second to
20943 // be the ADD node.
20944 // FIXME: We should support the commuted patterns.
20945 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20948 // If there are other uses of these operations we can't fold them.
20949 if (!V1->hasOneUse() || !V2->hasOneUse())
20952 // Ensure that both operations have the same operands. Note that we can
20953 // commute the FADD operands.
20954 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20955 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20956 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20959 // We're looking for blends between FADD and FSUB nodes. We insist on these
20960 // nodes being lined up in a specific expected pattern.
20961 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20962 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20963 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20966 // Only specific types are legal at this point, assert so we notice if and
20967 // when these change.
20968 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20969 VT == MVT::v4f64) &&
20970 "Unknown vector type encountered!");
20972 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20975 /// PerformShuffleCombine - Performs several different shuffle combines.
20976 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20977 TargetLowering::DAGCombinerInfo &DCI,
20978 const X86Subtarget *Subtarget) {
20980 SDValue N0 = N->getOperand(0);
20981 SDValue N1 = N->getOperand(1);
20982 EVT VT = N->getValueType(0);
20984 // Don't create instructions with illegal types after legalize types has run.
20985 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20986 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20989 // If we have legalized the vector types, look for blends of FADD and FSUB
20990 // nodes that we can fuse into an ADDSUB node.
20991 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20992 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20995 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20996 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20997 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20998 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21000 // During Type Legalization, when promoting illegal vector types,
21001 // the backend might introduce new shuffle dag nodes and bitcasts.
21003 // This code performs the following transformation:
21004 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21005 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21007 // We do this only if both the bitcast and the BINOP dag nodes have
21008 // one use. Also, perform this transformation only if the new binary
21009 // operation is legal. This is to avoid introducing dag nodes that
21010 // potentially need to be further expanded (or custom lowered) into a
21011 // less optimal sequence of dag nodes.
21012 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21013 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21014 N0.getOpcode() == ISD::BITCAST) {
21015 SDValue BC0 = N0.getOperand(0);
21016 EVT SVT = BC0.getValueType();
21017 unsigned Opcode = BC0.getOpcode();
21018 unsigned NumElts = VT.getVectorNumElements();
21020 if (BC0.hasOneUse() && SVT.isVector() &&
21021 SVT.getVectorNumElements() * 2 == NumElts &&
21022 TLI.isOperationLegal(Opcode, VT)) {
21023 bool CanFold = false;
21035 unsigned SVTNumElts = SVT.getVectorNumElements();
21036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21037 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21038 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21039 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21040 CanFold = SVOp->getMaskElt(i) < 0;
21043 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21044 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21045 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21046 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21051 // Only handle 128 wide vector from here on.
21052 if (!VT.is128BitVector())
21055 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21056 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21057 // consecutive, non-overlapping, and in the right order.
21058 SmallVector<SDValue, 16> Elts;
21059 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21060 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21062 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21066 if (isTargetShuffle(N->getOpcode())) {
21068 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21069 if (Shuffle.getNode())
21072 // Try recursively combining arbitrary sequences of x86 shuffle
21073 // instructions into higher-order shuffles. We do this after combining
21074 // specific PSHUF instruction sequences into their minimal form so that we
21075 // can evaluate how many specialized shuffle instructions are involved in
21076 // a particular chain.
21077 SmallVector<int, 1> NonceMask; // Just a placeholder.
21078 NonceMask.push_back(0);
21079 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21080 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21082 return SDValue(); // This routine will use CombineTo to replace N.
21088 /// PerformTruncateCombine - Converts truncate operation to
21089 /// a sequence of vector shuffle operations.
21090 /// It is possible when we truncate 256-bit vector to 128-bit vector
21091 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21092 TargetLowering::DAGCombinerInfo &DCI,
21093 const X86Subtarget *Subtarget) {
21097 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21098 /// specific shuffle of a load can be folded into a single element load.
21099 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21100 /// shuffles have been customed lowered so we need to handle those here.
21101 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21102 TargetLowering::DAGCombinerInfo &DCI) {
21103 if (DCI.isBeforeLegalizeOps())
21106 SDValue InVec = N->getOperand(0);
21107 SDValue EltNo = N->getOperand(1);
21109 if (!isa<ConstantSDNode>(EltNo))
21112 EVT VT = InVec.getValueType();
21114 if (InVec.getOpcode() == ISD::BITCAST) {
21115 // Don't duplicate a load with other uses.
21116 if (!InVec.hasOneUse())
21118 EVT BCVT = InVec.getOperand(0).getValueType();
21119 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21121 InVec = InVec.getOperand(0);
21124 if (!isTargetShuffle(InVec.getOpcode()))
21127 // Don't duplicate a load with other uses.
21128 if (!InVec.hasOneUse())
21131 SmallVector<int, 16> ShuffleMask;
21133 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21137 // Select the input vector, guarding against out of range extract vector.
21138 unsigned NumElems = VT.getVectorNumElements();
21139 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21140 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21141 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21142 : InVec.getOperand(1);
21144 // If inputs to shuffle are the same for both ops, then allow 2 uses
21145 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21147 if (LdNode.getOpcode() == ISD::BITCAST) {
21148 // Don't duplicate a load with other uses.
21149 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21152 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21153 LdNode = LdNode.getOperand(0);
21156 if (!ISD::isNormalLoad(LdNode.getNode()))
21159 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21161 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21164 EVT EltVT = N->getValueType(0);
21165 // If there's a bitcast before the shuffle, check if the load type and
21166 // alignment is valid.
21167 unsigned Align = LN0->getAlignment();
21168 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21169 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21170 EltVT.getTypeForEVT(*DAG.getContext()));
21172 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21175 // All checks match so transform back to vector_shuffle so that DAG combiner
21176 // can finish the job
21179 // Create shuffle node taking into account the case that its a unary shuffle
21180 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21181 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21182 InVec.getOperand(0), Shuffle,
21184 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21185 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21189 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21190 /// generation and convert it from being a bunch of shuffles and extracts
21191 /// to a simple store and scalar loads to extract the elements.
21192 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21193 TargetLowering::DAGCombinerInfo &DCI) {
21194 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21195 if (NewOp.getNode())
21198 SDValue InputVector = N->getOperand(0);
21200 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21201 // from mmx to v2i32 has a single usage.
21202 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21203 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21204 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21205 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21206 N->getValueType(0),
21207 InputVector.getNode()->getOperand(0));
21209 // Only operate on vectors of 4 elements, where the alternative shuffling
21210 // gets to be more expensive.
21211 if (InputVector.getValueType() != MVT::v4i32)
21214 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21215 // single use which is a sign-extend or zero-extend, and all elements are
21217 SmallVector<SDNode *, 4> Uses;
21218 unsigned ExtractedElements = 0;
21219 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21220 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21221 if (UI.getUse().getResNo() != InputVector.getResNo())
21224 SDNode *Extract = *UI;
21225 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21228 if (Extract->getValueType(0) != MVT::i32)
21230 if (!Extract->hasOneUse())
21232 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21233 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21235 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21238 // Record which element was extracted.
21239 ExtractedElements |=
21240 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21242 Uses.push_back(Extract);
21245 // If not all the elements were used, this may not be worthwhile.
21246 if (ExtractedElements != 15)
21249 // Ok, we've now decided to do the transformation.
21250 SDLoc dl(InputVector);
21252 // Store the value to a temporary stack slot.
21253 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21254 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21255 MachinePointerInfo(), false, false, 0);
21257 // Replace each use (extract) with a load of the appropriate element.
21258 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21259 UE = Uses.end(); UI != UE; ++UI) {
21260 SDNode *Extract = *UI;
21262 // cOMpute the element's address.
21263 SDValue Idx = Extract->getOperand(1);
21265 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21266 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21268 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21270 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21271 StackPtr, OffsetVal);
21273 // Load the scalar.
21274 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21275 ScalarAddr, MachinePointerInfo(),
21276 false, false, false, 0);
21278 // Replace the exact with the load.
21279 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21282 // The replacement was made in place; don't return anything.
21286 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21287 static std::pair<unsigned, bool>
21288 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21289 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21290 if (!VT.isVector())
21291 return std::make_pair(0, false);
21293 bool NeedSplit = false;
21294 switch (VT.getSimpleVT().SimpleTy) {
21295 default: return std::make_pair(0, false);
21299 if (!Subtarget->hasAVX2())
21301 if (!Subtarget->hasAVX())
21302 return std::make_pair(0, false);
21307 if (!Subtarget->hasSSE2())
21308 return std::make_pair(0, false);
21311 // SSE2 has only a small subset of the operations.
21312 bool hasUnsigned = Subtarget->hasSSE41() ||
21313 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21314 bool hasSigned = Subtarget->hasSSE41() ||
21315 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21317 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21320 // Check for x CC y ? x : y.
21321 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21322 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21327 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21330 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21333 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21336 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21338 // Check for x CC y ? y : x -- a min/max with reversed arms.
21339 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21340 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21345 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21348 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21351 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21354 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21358 return std::make_pair(Opc, NeedSplit);
21362 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21363 const X86Subtarget *Subtarget) {
21365 SDValue Cond = N->getOperand(0);
21366 SDValue LHS = N->getOperand(1);
21367 SDValue RHS = N->getOperand(2);
21369 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21370 SDValue CondSrc = Cond->getOperand(0);
21371 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21372 Cond = CondSrc->getOperand(0);
21375 MVT VT = N->getSimpleValueType(0);
21376 MVT EltVT = VT.getVectorElementType();
21377 unsigned NumElems = VT.getVectorNumElements();
21378 // There is no blend with immediate in AVX-512.
21379 if (VT.is512BitVector())
21382 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21384 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21387 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21390 // A vselect where all conditions and data are constants can be optimized into
21391 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21392 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21393 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21396 unsigned MaskValue = 0;
21397 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21400 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21401 for (unsigned i = 0; i < NumElems; ++i) {
21402 // Be sure we emit undef where we can.
21403 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21404 ShuffleMask[i] = -1;
21406 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21409 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21412 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21414 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21415 TargetLowering::DAGCombinerInfo &DCI,
21416 const X86Subtarget *Subtarget) {
21418 SDValue Cond = N->getOperand(0);
21419 // Get the LHS/RHS of the select.
21420 SDValue LHS = N->getOperand(1);
21421 SDValue RHS = N->getOperand(2);
21422 EVT VT = LHS.getValueType();
21423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21425 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21426 // instructions match the semantics of the common C idiom x<y?x:y but not
21427 // x<=y?x:y, because of how they handle negative zero (which can be
21428 // ignored in unsafe-math mode).
21429 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21430 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21431 (Subtarget->hasSSE2() ||
21432 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21433 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21435 unsigned Opcode = 0;
21436 // Check for x CC y ? x : y.
21437 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21438 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21442 // Converting this to a min would handle NaNs incorrectly, and swapping
21443 // the operands would cause it to handle comparisons between positive
21444 // and negative zero incorrectly.
21445 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21446 if (!DAG.getTarget().Options.UnsafeFPMath &&
21447 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21449 std::swap(LHS, RHS);
21451 Opcode = X86ISD::FMIN;
21454 // Converting this to a min would handle comparisons between positive
21455 // and negative zero incorrectly.
21456 if (!DAG.getTarget().Options.UnsafeFPMath &&
21457 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21459 Opcode = X86ISD::FMIN;
21462 // Converting this to a min would handle both negative zeros and NaNs
21463 // incorrectly, but we can swap the operands to fix both.
21464 std::swap(LHS, RHS);
21468 Opcode = X86ISD::FMIN;
21472 // Converting this to a max would handle comparisons between positive
21473 // and negative zero incorrectly.
21474 if (!DAG.getTarget().Options.UnsafeFPMath &&
21475 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21477 Opcode = X86ISD::FMAX;
21480 // Converting this to a max would handle NaNs incorrectly, and swapping
21481 // the operands would cause it to handle comparisons between positive
21482 // and negative zero incorrectly.
21483 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21484 if (!DAG.getTarget().Options.UnsafeFPMath &&
21485 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21487 std::swap(LHS, RHS);
21489 Opcode = X86ISD::FMAX;
21492 // Converting this to a max would handle both negative zeros and NaNs
21493 // incorrectly, but we can swap the operands to fix both.
21494 std::swap(LHS, RHS);
21498 Opcode = X86ISD::FMAX;
21501 // Check for x CC y ? y : x -- a min/max with reversed arms.
21502 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21503 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21507 // Converting this to a min would handle comparisons between positive
21508 // and negative zero incorrectly, and swapping the operands would
21509 // cause it to handle NaNs incorrectly.
21510 if (!DAG.getTarget().Options.UnsafeFPMath &&
21511 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21512 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21514 std::swap(LHS, RHS);
21516 Opcode = X86ISD::FMIN;
21519 // Converting this to a min would handle NaNs incorrectly.
21520 if (!DAG.getTarget().Options.UnsafeFPMath &&
21521 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21523 Opcode = X86ISD::FMIN;
21526 // Converting this to a min would handle both negative zeros and NaNs
21527 // incorrectly, but we can swap the operands to fix both.
21528 std::swap(LHS, RHS);
21532 Opcode = X86ISD::FMIN;
21536 // Converting this to a max would handle NaNs incorrectly.
21537 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21539 Opcode = X86ISD::FMAX;
21542 // Converting this to a max would handle comparisons between positive
21543 // and negative zero incorrectly, and swapping the operands would
21544 // cause it to handle NaNs incorrectly.
21545 if (!DAG.getTarget().Options.UnsafeFPMath &&
21546 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21547 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21549 std::swap(LHS, RHS);
21551 Opcode = X86ISD::FMAX;
21554 // Converting this to a max would handle both negative zeros and NaNs
21555 // incorrectly, but we can swap the operands to fix both.
21556 std::swap(LHS, RHS);
21560 Opcode = X86ISD::FMAX;
21566 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21569 EVT CondVT = Cond.getValueType();
21570 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21571 CondVT.getVectorElementType() == MVT::i1) {
21572 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21573 // lowering on KNL. In this case we convert it to
21574 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21575 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21576 // Since SKX these selects have a proper lowering.
21577 EVT OpVT = LHS.getValueType();
21578 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21579 (OpVT.getVectorElementType() == MVT::i8 ||
21580 OpVT.getVectorElementType() == MVT::i16) &&
21581 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21582 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21583 DCI.AddToWorklist(Cond.getNode());
21584 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21587 // If this is a select between two integer constants, try to do some
21589 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21590 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21591 // Don't do this for crazy integer types.
21592 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21593 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21594 // so that TrueC (the true value) is larger than FalseC.
21595 bool NeedsCondInvert = false;
21597 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21598 // Efficiently invertible.
21599 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21600 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21601 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21602 NeedsCondInvert = true;
21603 std::swap(TrueC, FalseC);
21606 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21607 if (FalseC->getAPIntValue() == 0 &&
21608 TrueC->getAPIntValue().isPowerOf2()) {
21609 if (NeedsCondInvert) // Invert the condition if needed.
21610 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21611 DAG.getConstant(1, Cond.getValueType()));
21613 // Zero extend the condition if needed.
21614 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21616 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21617 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21618 DAG.getConstant(ShAmt, MVT::i8));
21621 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21622 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21623 if (NeedsCondInvert) // Invert the condition if needed.
21624 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21625 DAG.getConstant(1, Cond.getValueType()));
21627 // Zero extend the condition if needed.
21628 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21629 FalseC->getValueType(0), Cond);
21630 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21631 SDValue(FalseC, 0));
21634 // Optimize cases that will turn into an LEA instruction. This requires
21635 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21636 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21637 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21638 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21640 bool isFastMultiplier = false;
21642 switch ((unsigned char)Diff) {
21644 case 1: // result = add base, cond
21645 case 2: // result = lea base( , cond*2)
21646 case 3: // result = lea base(cond, cond*2)
21647 case 4: // result = lea base( , cond*4)
21648 case 5: // result = lea base(cond, cond*4)
21649 case 8: // result = lea base( , cond*8)
21650 case 9: // result = lea base(cond, cond*8)
21651 isFastMultiplier = true;
21656 if (isFastMultiplier) {
21657 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21658 if (NeedsCondInvert) // Invert the condition if needed.
21659 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21660 DAG.getConstant(1, Cond.getValueType()));
21662 // Zero extend the condition if needed.
21663 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21665 // Scale the condition by the difference.
21667 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21668 DAG.getConstant(Diff, Cond.getValueType()));
21670 // Add the base if non-zero.
21671 if (FalseC->getAPIntValue() != 0)
21672 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21673 SDValue(FalseC, 0));
21680 // Canonicalize max and min:
21681 // (x > y) ? x : y -> (x >= y) ? x : y
21682 // (x < y) ? x : y -> (x <= y) ? x : y
21683 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21684 // the need for an extra compare
21685 // against zero. e.g.
21686 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21688 // testl %edi, %edi
21690 // cmovgl %edi, %eax
21694 // cmovsl %eax, %edi
21695 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21696 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21697 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21698 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21703 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21704 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21705 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21706 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21711 // Early exit check
21712 if (!TLI.isTypeLegal(VT))
21715 // Match VSELECTs into subs with unsigned saturation.
21716 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21717 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21718 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21719 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21720 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21722 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21723 // left side invert the predicate to simplify logic below.
21725 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21727 CC = ISD::getSetCCInverse(CC, true);
21728 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21732 if (Other.getNode() && Other->getNumOperands() == 2 &&
21733 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21734 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21735 SDValue CondRHS = Cond->getOperand(1);
21737 // Look for a general sub with unsigned saturation first.
21738 // x >= y ? x-y : 0 --> subus x, y
21739 // x > y ? x-y : 0 --> subus x, y
21740 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21741 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21742 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21744 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21745 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21746 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21747 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21748 // If the RHS is a constant we have to reverse the const
21749 // canonicalization.
21750 // x > C-1 ? x+-C : 0 --> subus x, C
21751 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21752 CondRHSConst->getAPIntValue() ==
21753 (-OpRHSConst->getAPIntValue() - 1))
21754 return DAG.getNode(
21755 X86ISD::SUBUS, DL, VT, OpLHS,
21756 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21758 // Another special case: If C was a sign bit, the sub has been
21759 // canonicalized into a xor.
21760 // FIXME: Would it be better to use computeKnownBits to determine
21761 // whether it's safe to decanonicalize the xor?
21762 // x s< 0 ? x^C : 0 --> subus x, C
21763 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21764 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21765 OpRHSConst->getAPIntValue().isSignBit())
21766 // Note that we have to rebuild the RHS constant here to ensure we
21767 // don't rely on particular values of undef lanes.
21768 return DAG.getNode(
21769 X86ISD::SUBUS, DL, VT, OpLHS,
21770 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21775 // Try to match a min/max vector operation.
21776 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21777 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21778 unsigned Opc = ret.first;
21779 bool NeedSplit = ret.second;
21781 if (Opc && NeedSplit) {
21782 unsigned NumElems = VT.getVectorNumElements();
21783 // Extract the LHS vectors
21784 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21785 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21787 // Extract the RHS vectors
21788 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21789 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21791 // Create min/max for each subvector
21792 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21793 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21795 // Merge the result
21796 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21798 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21801 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21802 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21803 // Check if SETCC has already been promoted
21804 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21805 // Check that condition value type matches vselect operand type
21808 assert(Cond.getValueType().isVector() &&
21809 "vector select expects a vector selector!");
21811 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21812 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21814 if (!TValIsAllOnes && !FValIsAllZeros) {
21815 // Try invert the condition if true value is not all 1s and false value
21817 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21818 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21820 if (TValIsAllZeros || FValIsAllOnes) {
21821 SDValue CC = Cond.getOperand(2);
21822 ISD::CondCode NewCC =
21823 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21824 Cond.getOperand(0).getValueType().isInteger());
21825 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21826 std::swap(LHS, RHS);
21827 TValIsAllOnes = FValIsAllOnes;
21828 FValIsAllZeros = TValIsAllZeros;
21832 if (TValIsAllOnes || FValIsAllZeros) {
21835 if (TValIsAllOnes && FValIsAllZeros)
21837 else if (TValIsAllOnes)
21838 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21839 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21840 else if (FValIsAllZeros)
21841 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21842 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21844 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21848 // Try to fold this VSELECT into a MOVSS/MOVSD
21849 if (N->getOpcode() == ISD::VSELECT &&
21850 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21851 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21852 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21853 bool CanFold = false;
21854 unsigned NumElems = Cond.getNumOperands();
21858 if (isZero(Cond.getOperand(0))) {
21861 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21862 // fold (vselect <0,-1> -> (movsd A, B)
21863 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21864 CanFold = isAllOnes(Cond.getOperand(i));
21865 } else if (isAllOnes(Cond.getOperand(0))) {
21869 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21870 // fold (vselect <-1,0> -> (movsd B, A)
21871 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21872 CanFold = isZero(Cond.getOperand(i));
21876 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21877 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21878 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21881 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21882 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21883 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21884 // (v2i64 (bitcast B)))))
21886 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21887 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21888 // (v2f64 (bitcast B)))))
21890 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21891 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21892 // (v2i64 (bitcast A)))))
21894 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21895 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21896 // (v2f64 (bitcast A)))))
21898 CanFold = (isZero(Cond.getOperand(0)) &&
21899 isZero(Cond.getOperand(1)) &&
21900 isAllOnes(Cond.getOperand(2)) &&
21901 isAllOnes(Cond.getOperand(3)));
21903 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21904 isAllOnes(Cond.getOperand(1)) &&
21905 isZero(Cond.getOperand(2)) &&
21906 isZero(Cond.getOperand(3))) {
21908 std::swap(LHS, RHS);
21912 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21913 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21914 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21915 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21917 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21923 // If we know that this node is legal then we know that it is going to be
21924 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21925 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21926 // to simplify previous instructions.
21927 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21928 !DCI.isBeforeLegalize() &&
21929 // We explicitly check against v8i16 and v16i16 because, although
21930 // they're marked as Custom, they might only be legal when Cond is a
21931 // build_vector of constants. This will be taken care in a later
21933 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21934 VT != MVT::v8i16)) {
21935 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21937 // Don't optimize vector selects that map to mask-registers.
21941 // Check all uses of that condition operand to check whether it will be
21942 // consumed by non-BLEND instructions, which may depend on all bits are set
21944 for (SDNode::use_iterator I = Cond->use_begin(),
21945 E = Cond->use_end(); I != E; ++I)
21946 if (I->getOpcode() != ISD::VSELECT)
21947 // TODO: Add other opcodes eventually lowered into BLEND.
21950 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21951 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21953 APInt KnownZero, KnownOne;
21954 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21955 DCI.isBeforeLegalizeOps());
21956 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21957 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21958 DCI.CommitTargetLoweringOpt(TLO);
21961 // We should generate an X86ISD::BLENDI from a vselect if its argument
21962 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21963 // constants. This specific pattern gets generated when we split a
21964 // selector for a 512 bit vector in a machine without AVX512 (but with
21965 // 256-bit vectors), during legalization:
21967 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21969 // Iff we find this pattern and the build_vectors are built from
21970 // constants, we translate the vselect into a shuffle_vector that we
21971 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21972 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21973 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21974 if (Shuffle.getNode())
21981 // Check whether a boolean test is testing a boolean value generated by
21982 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21985 // Simplify the following patterns:
21986 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21987 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21988 // to (Op EFLAGS Cond)
21990 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21991 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21992 // to (Op EFLAGS !Cond)
21994 // where Op could be BRCOND or CMOV.
21996 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21997 // Quit if not CMP and SUB with its value result used.
21998 if (Cmp.getOpcode() != X86ISD::CMP &&
21999 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22002 // Quit if not used as a boolean value.
22003 if (CC != X86::COND_E && CC != X86::COND_NE)
22006 // Check CMP operands. One of them should be 0 or 1 and the other should be
22007 // an SetCC or extended from it.
22008 SDValue Op1 = Cmp.getOperand(0);
22009 SDValue Op2 = Cmp.getOperand(1);
22012 const ConstantSDNode* C = nullptr;
22013 bool needOppositeCond = (CC == X86::COND_E);
22014 bool checkAgainstTrue = false; // Is it a comparison against 1?
22016 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22018 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22020 else // Quit if all operands are not constants.
22023 if (C->getZExtValue() == 1) {
22024 needOppositeCond = !needOppositeCond;
22025 checkAgainstTrue = true;
22026 } else if (C->getZExtValue() != 0)
22027 // Quit if the constant is neither 0 or 1.
22030 bool truncatedToBoolWithAnd = false;
22031 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22032 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22033 SetCC.getOpcode() == ISD::TRUNCATE ||
22034 SetCC.getOpcode() == ISD::AND) {
22035 if (SetCC.getOpcode() == ISD::AND) {
22037 ConstantSDNode *CS;
22038 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22039 CS->getZExtValue() == 1)
22041 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22042 CS->getZExtValue() == 1)
22046 SetCC = SetCC.getOperand(OpIdx);
22047 truncatedToBoolWithAnd = true;
22049 SetCC = SetCC.getOperand(0);
22052 switch (SetCC.getOpcode()) {
22053 case X86ISD::SETCC_CARRY:
22054 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22055 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22056 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22057 // truncated to i1 using 'and'.
22058 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22060 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22061 "Invalid use of SETCC_CARRY!");
22063 case X86ISD::SETCC:
22064 // Set the condition code or opposite one if necessary.
22065 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22066 if (needOppositeCond)
22067 CC = X86::GetOppositeBranchCondition(CC);
22068 return SetCC.getOperand(1);
22069 case X86ISD::CMOV: {
22070 // Check whether false/true value has canonical one, i.e. 0 or 1.
22071 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22072 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22073 // Quit if true value is not a constant.
22076 // Quit if false value is not a constant.
22078 SDValue Op = SetCC.getOperand(0);
22079 // Skip 'zext' or 'trunc' node.
22080 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22081 Op.getOpcode() == ISD::TRUNCATE)
22082 Op = Op.getOperand(0);
22083 // A special case for rdrand/rdseed, where 0 is set if false cond is
22085 if ((Op.getOpcode() != X86ISD::RDRAND &&
22086 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22089 // Quit if false value is not the constant 0 or 1.
22090 bool FValIsFalse = true;
22091 if (FVal && FVal->getZExtValue() != 0) {
22092 if (FVal->getZExtValue() != 1)
22094 // If FVal is 1, opposite cond is needed.
22095 needOppositeCond = !needOppositeCond;
22096 FValIsFalse = false;
22098 // Quit if TVal is not the constant opposite of FVal.
22099 if (FValIsFalse && TVal->getZExtValue() != 1)
22101 if (!FValIsFalse && TVal->getZExtValue() != 0)
22103 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22104 if (needOppositeCond)
22105 CC = X86::GetOppositeBranchCondition(CC);
22106 return SetCC.getOperand(3);
22113 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22114 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22115 TargetLowering::DAGCombinerInfo &DCI,
22116 const X86Subtarget *Subtarget) {
22119 // If the flag operand isn't dead, don't touch this CMOV.
22120 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22123 SDValue FalseOp = N->getOperand(0);
22124 SDValue TrueOp = N->getOperand(1);
22125 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22126 SDValue Cond = N->getOperand(3);
22128 if (CC == X86::COND_E || CC == X86::COND_NE) {
22129 switch (Cond.getOpcode()) {
22133 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22134 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22135 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22141 Flags = checkBoolTestSetCCCombine(Cond, CC);
22142 if (Flags.getNode() &&
22143 // Extra check as FCMOV only supports a subset of X86 cond.
22144 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22145 SDValue Ops[] = { FalseOp, TrueOp,
22146 DAG.getConstant(CC, MVT::i8), Flags };
22147 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22150 // If this is a select between two integer constants, try to do some
22151 // optimizations. Note that the operands are ordered the opposite of SELECT
22153 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22154 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22155 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22156 // larger than FalseC (the false value).
22157 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22158 CC = X86::GetOppositeBranchCondition(CC);
22159 std::swap(TrueC, FalseC);
22160 std::swap(TrueOp, FalseOp);
22163 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22164 // This is efficient for any integer data type (including i8/i16) and
22166 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22167 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22168 DAG.getConstant(CC, MVT::i8), Cond);
22170 // Zero extend the condition if needed.
22171 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22173 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22174 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22175 DAG.getConstant(ShAmt, MVT::i8));
22176 if (N->getNumValues() == 2) // Dead flag value?
22177 return DCI.CombineTo(N, Cond, SDValue());
22181 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22182 // for any integer data type, including i8/i16.
22183 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22184 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22185 DAG.getConstant(CC, MVT::i8), Cond);
22187 // Zero extend the condition if needed.
22188 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22189 FalseC->getValueType(0), Cond);
22190 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22191 SDValue(FalseC, 0));
22193 if (N->getNumValues() == 2) // Dead flag value?
22194 return DCI.CombineTo(N, Cond, SDValue());
22198 // Optimize cases that will turn into an LEA instruction. This requires
22199 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22200 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22201 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22202 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22204 bool isFastMultiplier = false;
22206 switch ((unsigned char)Diff) {
22208 case 1: // result = add base, cond
22209 case 2: // result = lea base( , cond*2)
22210 case 3: // result = lea base(cond, cond*2)
22211 case 4: // result = lea base( , cond*4)
22212 case 5: // result = lea base(cond, cond*4)
22213 case 8: // result = lea base( , cond*8)
22214 case 9: // result = lea base(cond, cond*8)
22215 isFastMultiplier = true;
22220 if (isFastMultiplier) {
22221 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22222 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22223 DAG.getConstant(CC, MVT::i8), Cond);
22224 // Zero extend the condition if needed.
22225 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22227 // Scale the condition by the difference.
22229 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22230 DAG.getConstant(Diff, Cond.getValueType()));
22232 // Add the base if non-zero.
22233 if (FalseC->getAPIntValue() != 0)
22234 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22235 SDValue(FalseC, 0));
22236 if (N->getNumValues() == 2) // Dead flag value?
22237 return DCI.CombineTo(N, Cond, SDValue());
22244 // Handle these cases:
22245 // (select (x != c), e, c) -> select (x != c), e, x),
22246 // (select (x == c), c, e) -> select (x == c), x, e)
22247 // where the c is an integer constant, and the "select" is the combination
22248 // of CMOV and CMP.
22250 // The rationale for this change is that the conditional-move from a constant
22251 // needs two instructions, however, conditional-move from a register needs
22252 // only one instruction.
22254 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22255 // some instruction-combining opportunities. This opt needs to be
22256 // postponed as late as possible.
22258 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22259 // the DCI.xxxx conditions are provided to postpone the optimization as
22260 // late as possible.
22262 ConstantSDNode *CmpAgainst = nullptr;
22263 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22264 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22265 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22267 if (CC == X86::COND_NE &&
22268 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22269 CC = X86::GetOppositeBranchCondition(CC);
22270 std::swap(TrueOp, FalseOp);
22273 if (CC == X86::COND_E &&
22274 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22275 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22276 DAG.getConstant(CC, MVT::i8), Cond };
22277 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22285 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22286 const X86Subtarget *Subtarget) {
22287 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22289 default: return SDValue();
22290 // SSE/AVX/AVX2 blend intrinsics.
22291 case Intrinsic::x86_avx2_pblendvb:
22292 case Intrinsic::x86_avx2_pblendw:
22293 case Intrinsic::x86_avx2_pblendd_128:
22294 case Intrinsic::x86_avx2_pblendd_256:
22295 // Don't try to simplify this intrinsic if we don't have AVX2.
22296 if (!Subtarget->hasAVX2())
22299 case Intrinsic::x86_avx_blend_pd_256:
22300 case Intrinsic::x86_avx_blend_ps_256:
22301 case Intrinsic::x86_avx_blendv_pd_256:
22302 case Intrinsic::x86_avx_blendv_ps_256:
22303 // Don't try to simplify this intrinsic if we don't have AVX.
22304 if (!Subtarget->hasAVX())
22307 case Intrinsic::x86_sse41_pblendw:
22308 case Intrinsic::x86_sse41_blendpd:
22309 case Intrinsic::x86_sse41_blendps:
22310 case Intrinsic::x86_sse41_blendvps:
22311 case Intrinsic::x86_sse41_blendvpd:
22312 case Intrinsic::x86_sse41_pblendvb: {
22313 SDValue Op0 = N->getOperand(1);
22314 SDValue Op1 = N->getOperand(2);
22315 SDValue Mask = N->getOperand(3);
22317 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22318 if (!Subtarget->hasSSE41())
22321 // fold (blend A, A, Mask) -> A
22324 // fold (blend A, B, allZeros) -> A
22325 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22327 // fold (blend A, B, allOnes) -> B
22328 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22331 // Simplify the case where the mask is a constant i32 value.
22332 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22333 if (C->isNullValue())
22335 if (C->isAllOnesValue())
22342 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22343 case Intrinsic::x86_sse2_psrai_w:
22344 case Intrinsic::x86_sse2_psrai_d:
22345 case Intrinsic::x86_avx2_psrai_w:
22346 case Intrinsic::x86_avx2_psrai_d:
22347 case Intrinsic::x86_sse2_psra_w:
22348 case Intrinsic::x86_sse2_psra_d:
22349 case Intrinsic::x86_avx2_psra_w:
22350 case Intrinsic::x86_avx2_psra_d: {
22351 SDValue Op0 = N->getOperand(1);
22352 SDValue Op1 = N->getOperand(2);
22353 EVT VT = Op0.getValueType();
22354 assert(VT.isVector() && "Expected a vector type!");
22356 if (isa<BuildVectorSDNode>(Op1))
22357 Op1 = Op1.getOperand(0);
22359 if (!isa<ConstantSDNode>(Op1))
22362 EVT SVT = VT.getVectorElementType();
22363 unsigned SVTBits = SVT.getSizeInBits();
22365 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22366 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22367 uint64_t ShAmt = C.getZExtValue();
22369 // Don't try to convert this shift into a ISD::SRA if the shift
22370 // count is bigger than or equal to the element size.
22371 if (ShAmt >= SVTBits)
22374 // Trivial case: if the shift count is zero, then fold this
22375 // into the first operand.
22379 // Replace this packed shift intrinsic with a target independent
22381 SDValue Splat = DAG.getConstant(C, VT);
22382 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22387 /// PerformMulCombine - Optimize a single multiply with constant into two
22388 /// in order to implement it with two cheaper instructions, e.g.
22389 /// LEA + SHL, LEA + LEA.
22390 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22391 TargetLowering::DAGCombinerInfo &DCI) {
22392 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22395 EVT VT = N->getValueType(0);
22396 if (VT != MVT::i64)
22399 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22402 uint64_t MulAmt = C->getZExtValue();
22403 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22406 uint64_t MulAmt1 = 0;
22407 uint64_t MulAmt2 = 0;
22408 if ((MulAmt % 9) == 0) {
22410 MulAmt2 = MulAmt / 9;
22411 } else if ((MulAmt % 5) == 0) {
22413 MulAmt2 = MulAmt / 5;
22414 } else if ((MulAmt % 3) == 0) {
22416 MulAmt2 = MulAmt / 3;
22419 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22422 if (isPowerOf2_64(MulAmt2) &&
22423 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22424 // If second multiplifer is pow2, issue it first. We want the multiply by
22425 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22427 std::swap(MulAmt1, MulAmt2);
22430 if (isPowerOf2_64(MulAmt1))
22431 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22432 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22434 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22435 DAG.getConstant(MulAmt1, VT));
22437 if (isPowerOf2_64(MulAmt2))
22438 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22439 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22441 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22442 DAG.getConstant(MulAmt2, VT));
22444 // Do not add new nodes to DAG combiner worklist.
22445 DCI.CombineTo(N, NewMul, false);
22450 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22451 SDValue N0 = N->getOperand(0);
22452 SDValue N1 = N->getOperand(1);
22453 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22454 EVT VT = N0.getValueType();
22456 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22457 // since the result of setcc_c is all zero's or all ones.
22458 if (VT.isInteger() && !VT.isVector() &&
22459 N1C && N0.getOpcode() == ISD::AND &&
22460 N0.getOperand(1).getOpcode() == ISD::Constant) {
22461 SDValue N00 = N0.getOperand(0);
22462 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22463 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22464 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22465 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22466 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22467 APInt ShAmt = N1C->getAPIntValue();
22468 Mask = Mask.shl(ShAmt);
22470 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22471 N00, DAG.getConstant(Mask, VT));
22475 // Hardware support for vector shifts is sparse which makes us scalarize the
22476 // vector operations in many cases. Also, on sandybridge ADD is faster than
22478 // (shl V, 1) -> add V,V
22479 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22480 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22481 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22482 // We shift all of the values by one. In many cases we do not have
22483 // hardware support for this operation. This is better expressed as an ADD
22485 if (N1SplatC->getZExtValue() == 1)
22486 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22492 /// \brief Returns a vector of 0s if the node in input is a vector logical
22493 /// shift by a constant amount which is known to be bigger than or equal
22494 /// to the vector element size in bits.
22495 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22496 const X86Subtarget *Subtarget) {
22497 EVT VT = N->getValueType(0);
22499 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22500 (!Subtarget->hasInt256() ||
22501 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22504 SDValue Amt = N->getOperand(1);
22506 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22507 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22508 APInt ShiftAmt = AmtSplat->getAPIntValue();
22509 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22511 // SSE2/AVX2 logical shifts always return a vector of 0s
22512 // if the shift amount is bigger than or equal to
22513 // the element size. The constant shift amount will be
22514 // encoded as a 8-bit immediate.
22515 if (ShiftAmt.trunc(8).uge(MaxAmount))
22516 return getZeroVector(VT, Subtarget, DAG, DL);
22522 /// PerformShiftCombine - Combine shifts.
22523 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22524 TargetLowering::DAGCombinerInfo &DCI,
22525 const X86Subtarget *Subtarget) {
22526 if (N->getOpcode() == ISD::SHL) {
22527 SDValue V = PerformSHLCombine(N, DAG);
22528 if (V.getNode()) return V;
22531 if (N->getOpcode() != ISD::SRA) {
22532 // Try to fold this logical shift into a zero vector.
22533 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22534 if (V.getNode()) return V;
22540 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22541 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22542 // and friends. Likewise for OR -> CMPNEQSS.
22543 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22544 TargetLowering::DAGCombinerInfo &DCI,
22545 const X86Subtarget *Subtarget) {
22548 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22549 // we're requiring SSE2 for both.
22550 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22551 SDValue N0 = N->getOperand(0);
22552 SDValue N1 = N->getOperand(1);
22553 SDValue CMP0 = N0->getOperand(1);
22554 SDValue CMP1 = N1->getOperand(1);
22557 // The SETCCs should both refer to the same CMP.
22558 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22561 SDValue CMP00 = CMP0->getOperand(0);
22562 SDValue CMP01 = CMP0->getOperand(1);
22563 EVT VT = CMP00.getValueType();
22565 if (VT == MVT::f32 || VT == MVT::f64) {
22566 bool ExpectingFlags = false;
22567 // Check for any users that want flags:
22568 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22569 !ExpectingFlags && UI != UE; ++UI)
22570 switch (UI->getOpcode()) {
22575 ExpectingFlags = true;
22577 case ISD::CopyToReg:
22578 case ISD::SIGN_EXTEND:
22579 case ISD::ZERO_EXTEND:
22580 case ISD::ANY_EXTEND:
22584 if (!ExpectingFlags) {
22585 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22586 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22588 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22589 X86::CondCode tmp = cc0;
22594 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22595 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22596 // FIXME: need symbolic constants for these magic numbers.
22597 // See X86ATTInstPrinter.cpp:printSSECC().
22598 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22599 if (Subtarget->hasAVX512()) {
22600 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22601 CMP01, DAG.getConstant(x86cc, MVT::i8));
22602 if (N->getValueType(0) != MVT::i1)
22603 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22607 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22608 CMP00.getValueType(), CMP00, CMP01,
22609 DAG.getConstant(x86cc, MVT::i8));
22611 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22612 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22614 if (is64BitFP && !Subtarget->is64Bit()) {
22615 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22616 // 64-bit integer, since that's not a legal type. Since
22617 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22618 // bits, but can do this little dance to extract the lowest 32 bits
22619 // and work with those going forward.
22620 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22622 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22624 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22625 Vector32, DAG.getIntPtrConstant(0));
22629 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22630 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22631 DAG.getConstant(1, IntVT));
22632 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22633 return OneBitOfTruth;
22641 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22642 /// so it can be folded inside ANDNP.
22643 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22644 EVT VT = N->getValueType(0);
22646 // Match direct AllOnes for 128 and 256-bit vectors
22647 if (ISD::isBuildVectorAllOnes(N))
22650 // Look through a bit convert.
22651 if (N->getOpcode() == ISD::BITCAST)
22652 N = N->getOperand(0).getNode();
22654 // Sometimes the operand may come from a insert_subvector building a 256-bit
22656 if (VT.is256BitVector() &&
22657 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22658 SDValue V1 = N->getOperand(0);
22659 SDValue V2 = N->getOperand(1);
22661 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22662 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22663 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22664 ISD::isBuildVectorAllOnes(V2.getNode()))
22671 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22672 // register. In most cases we actually compare or select YMM-sized registers
22673 // and mixing the two types creates horrible code. This method optimizes
22674 // some of the transition sequences.
22675 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22676 TargetLowering::DAGCombinerInfo &DCI,
22677 const X86Subtarget *Subtarget) {
22678 EVT VT = N->getValueType(0);
22679 if (!VT.is256BitVector())
22682 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22683 N->getOpcode() == ISD::ZERO_EXTEND ||
22684 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22686 SDValue Narrow = N->getOperand(0);
22687 EVT NarrowVT = Narrow->getValueType(0);
22688 if (!NarrowVT.is128BitVector())
22691 if (Narrow->getOpcode() != ISD::XOR &&
22692 Narrow->getOpcode() != ISD::AND &&
22693 Narrow->getOpcode() != ISD::OR)
22696 SDValue N0 = Narrow->getOperand(0);
22697 SDValue N1 = Narrow->getOperand(1);
22700 // The Left side has to be a trunc.
22701 if (N0.getOpcode() != ISD::TRUNCATE)
22704 // The type of the truncated inputs.
22705 EVT WideVT = N0->getOperand(0)->getValueType(0);
22709 // The right side has to be a 'trunc' or a constant vector.
22710 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22711 ConstantSDNode *RHSConstSplat = nullptr;
22712 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22713 RHSConstSplat = RHSBV->getConstantSplatNode();
22714 if (!RHSTrunc && !RHSConstSplat)
22717 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22719 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22722 // Set N0 and N1 to hold the inputs to the new wide operation.
22723 N0 = N0->getOperand(0);
22724 if (RHSConstSplat) {
22725 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22726 SDValue(RHSConstSplat, 0));
22727 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22728 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22729 } else if (RHSTrunc) {
22730 N1 = N1->getOperand(0);
22733 // Generate the wide operation.
22734 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22735 unsigned Opcode = N->getOpcode();
22737 case ISD::ANY_EXTEND:
22739 case ISD::ZERO_EXTEND: {
22740 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22741 APInt Mask = APInt::getAllOnesValue(InBits);
22742 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22743 return DAG.getNode(ISD::AND, DL, VT,
22744 Op, DAG.getConstant(Mask, VT));
22746 case ISD::SIGN_EXTEND:
22747 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22748 Op, DAG.getValueType(NarrowVT));
22750 llvm_unreachable("Unexpected opcode");
22754 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22755 TargetLowering::DAGCombinerInfo &DCI,
22756 const X86Subtarget *Subtarget) {
22757 EVT VT = N->getValueType(0);
22758 if (DCI.isBeforeLegalizeOps())
22761 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22765 // Create BEXTR instructions
22766 // BEXTR is ((X >> imm) & (2**size-1))
22767 if (VT == MVT::i32 || VT == MVT::i64) {
22768 SDValue N0 = N->getOperand(0);
22769 SDValue N1 = N->getOperand(1);
22772 // Check for BEXTR.
22773 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22774 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22775 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22776 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22777 if (MaskNode && ShiftNode) {
22778 uint64_t Mask = MaskNode->getZExtValue();
22779 uint64_t Shift = ShiftNode->getZExtValue();
22780 if (isMask_64(Mask)) {
22781 uint64_t MaskSize = CountPopulation_64(Mask);
22782 if (Shift + MaskSize <= VT.getSizeInBits())
22783 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22784 DAG.getConstant(Shift | (MaskSize << 8), VT));
22792 // Want to form ANDNP nodes:
22793 // 1) In the hopes of then easily combining them with OR and AND nodes
22794 // to form PBLEND/PSIGN.
22795 // 2) To match ANDN packed intrinsics
22796 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22799 SDValue N0 = N->getOperand(0);
22800 SDValue N1 = N->getOperand(1);
22803 // Check LHS for vnot
22804 if (N0.getOpcode() == ISD::XOR &&
22805 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22806 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22807 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22809 // Check RHS for vnot
22810 if (N1.getOpcode() == ISD::XOR &&
22811 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22812 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22813 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22818 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22819 TargetLowering::DAGCombinerInfo &DCI,
22820 const X86Subtarget *Subtarget) {
22821 if (DCI.isBeforeLegalizeOps())
22824 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22828 SDValue N0 = N->getOperand(0);
22829 SDValue N1 = N->getOperand(1);
22830 EVT VT = N->getValueType(0);
22832 // look for psign/blend
22833 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22834 if (!Subtarget->hasSSSE3() ||
22835 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22838 // Canonicalize pandn to RHS
22839 if (N0.getOpcode() == X86ISD::ANDNP)
22841 // or (and (m, y), (pandn m, x))
22842 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22843 SDValue Mask = N1.getOperand(0);
22844 SDValue X = N1.getOperand(1);
22846 if (N0.getOperand(0) == Mask)
22847 Y = N0.getOperand(1);
22848 if (N0.getOperand(1) == Mask)
22849 Y = N0.getOperand(0);
22851 // Check to see if the mask appeared in both the AND and ANDNP and
22855 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22856 // Look through mask bitcast.
22857 if (Mask.getOpcode() == ISD::BITCAST)
22858 Mask = Mask.getOperand(0);
22859 if (X.getOpcode() == ISD::BITCAST)
22860 X = X.getOperand(0);
22861 if (Y.getOpcode() == ISD::BITCAST)
22862 Y = Y.getOperand(0);
22864 EVT MaskVT = Mask.getValueType();
22866 // Validate that the Mask operand is a vector sra node.
22867 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22868 // there is no psrai.b
22869 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22870 unsigned SraAmt = ~0;
22871 if (Mask.getOpcode() == ISD::SRA) {
22872 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22873 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22874 SraAmt = AmtConst->getZExtValue();
22875 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22876 SDValue SraC = Mask.getOperand(1);
22877 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22879 if ((SraAmt + 1) != EltBits)
22884 // Now we know we at least have a plendvb with the mask val. See if
22885 // we can form a psignb/w/d.
22886 // psign = x.type == y.type == mask.type && y = sub(0, x);
22887 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22888 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22889 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22890 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22891 "Unsupported VT for PSIGN");
22892 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22893 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22895 // PBLENDVB only available on SSE 4.1
22896 if (!Subtarget->hasSSE41())
22899 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22901 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22902 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22903 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22904 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22905 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22909 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22912 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22913 MachineFunction &MF = DAG.getMachineFunction();
22914 bool OptForSize = MF.getFunction()->getAttributes().
22915 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22917 // SHLD/SHRD instructions have lower register pressure, but on some
22918 // platforms they have higher latency than the equivalent
22919 // series of shifts/or that would otherwise be generated.
22920 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22921 // have higher latencies and we are not optimizing for size.
22922 if (!OptForSize && Subtarget->isSHLDSlow())
22925 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22927 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22929 if (!N0.hasOneUse() || !N1.hasOneUse())
22932 SDValue ShAmt0 = N0.getOperand(1);
22933 if (ShAmt0.getValueType() != MVT::i8)
22935 SDValue ShAmt1 = N1.getOperand(1);
22936 if (ShAmt1.getValueType() != MVT::i8)
22938 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22939 ShAmt0 = ShAmt0.getOperand(0);
22940 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22941 ShAmt1 = ShAmt1.getOperand(0);
22944 unsigned Opc = X86ISD::SHLD;
22945 SDValue Op0 = N0.getOperand(0);
22946 SDValue Op1 = N1.getOperand(0);
22947 if (ShAmt0.getOpcode() == ISD::SUB) {
22948 Opc = X86ISD::SHRD;
22949 std::swap(Op0, Op1);
22950 std::swap(ShAmt0, ShAmt1);
22953 unsigned Bits = VT.getSizeInBits();
22954 if (ShAmt1.getOpcode() == ISD::SUB) {
22955 SDValue Sum = ShAmt1.getOperand(0);
22956 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22957 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22958 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22959 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22960 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22961 return DAG.getNode(Opc, DL, VT,
22963 DAG.getNode(ISD::TRUNCATE, DL,
22966 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22967 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22969 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22970 return DAG.getNode(Opc, DL, VT,
22971 N0.getOperand(0), N1.getOperand(0),
22972 DAG.getNode(ISD::TRUNCATE, DL,
22979 // Generate NEG and CMOV for integer abs.
22980 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22981 EVT VT = N->getValueType(0);
22983 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22984 // 8-bit integer abs to NEG and CMOV.
22985 if (VT.isInteger() && VT.getSizeInBits() == 8)
22988 SDValue N0 = N->getOperand(0);
22989 SDValue N1 = N->getOperand(1);
22992 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22993 // and change it to SUB and CMOV.
22994 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22995 N0.getOpcode() == ISD::ADD &&
22996 N0.getOperand(1) == N1 &&
22997 N1.getOpcode() == ISD::SRA &&
22998 N1.getOperand(0) == N0.getOperand(0))
22999 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23000 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23001 // Generate SUB & CMOV.
23002 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23003 DAG.getConstant(0, VT), N0.getOperand(0));
23005 SDValue Ops[] = { N0.getOperand(0), Neg,
23006 DAG.getConstant(X86::COND_GE, MVT::i8),
23007 SDValue(Neg.getNode(), 1) };
23008 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23013 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23014 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23015 TargetLowering::DAGCombinerInfo &DCI,
23016 const X86Subtarget *Subtarget) {
23017 if (DCI.isBeforeLegalizeOps())
23020 if (Subtarget->hasCMov()) {
23021 SDValue RV = performIntegerAbsCombine(N, DAG);
23029 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23030 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23031 TargetLowering::DAGCombinerInfo &DCI,
23032 const X86Subtarget *Subtarget) {
23033 LoadSDNode *Ld = cast<LoadSDNode>(N);
23034 EVT RegVT = Ld->getValueType(0);
23035 EVT MemVT = Ld->getMemoryVT();
23037 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23039 // On Sandybridge unaligned 256bit loads are inefficient.
23040 ISD::LoadExtType Ext = Ld->getExtensionType();
23041 unsigned Alignment = Ld->getAlignment();
23042 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23043 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23044 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23045 unsigned NumElems = RegVT.getVectorNumElements();
23049 SDValue Ptr = Ld->getBasePtr();
23050 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23052 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23054 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23055 Ld->getPointerInfo(), Ld->isVolatile(),
23056 Ld->isNonTemporal(), Ld->isInvariant(),
23058 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23059 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23060 Ld->getPointerInfo(), Ld->isVolatile(),
23061 Ld->isNonTemporal(), Ld->isInvariant(),
23062 std::min(16U, Alignment));
23063 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23065 Load2.getValue(1));
23067 SDValue NewVec = DAG.getUNDEF(RegVT);
23068 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23069 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23070 return DCI.CombineTo(N, NewVec, TF, true);
23076 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23077 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23078 const X86Subtarget *Subtarget) {
23079 StoreSDNode *St = cast<StoreSDNode>(N);
23080 EVT VT = St->getValue().getValueType();
23081 EVT StVT = St->getMemoryVT();
23083 SDValue StoredVal = St->getOperand(1);
23084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23086 // If we are saving a concatenation of two XMM registers, perform two stores.
23087 // On Sandy Bridge, 256-bit memory operations are executed by two
23088 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23089 // memory operation.
23090 unsigned Alignment = St->getAlignment();
23091 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23092 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23093 StVT == VT && !IsAligned) {
23094 unsigned NumElems = VT.getVectorNumElements();
23098 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23099 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23101 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23102 SDValue Ptr0 = St->getBasePtr();
23103 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23105 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23106 St->getPointerInfo(), St->isVolatile(),
23107 St->isNonTemporal(), Alignment);
23108 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23109 St->getPointerInfo(), St->isVolatile(),
23110 St->isNonTemporal(),
23111 std::min(16U, Alignment));
23112 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23115 // Optimize trunc store (of multiple scalars) to shuffle and store.
23116 // First, pack all of the elements in one place. Next, store to memory
23117 // in fewer chunks.
23118 if (St->isTruncatingStore() && VT.isVector()) {
23119 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23120 unsigned NumElems = VT.getVectorNumElements();
23121 assert(StVT != VT && "Cannot truncate to the same type");
23122 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23123 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23125 // From, To sizes and ElemCount must be pow of two
23126 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23127 // We are going to use the original vector elt for storing.
23128 // Accumulated smaller vector elements must be a multiple of the store size.
23129 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23131 unsigned SizeRatio = FromSz / ToSz;
23133 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23135 // Create a type on which we perform the shuffle
23136 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23137 StVT.getScalarType(), NumElems*SizeRatio);
23139 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23141 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23142 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23143 for (unsigned i = 0; i != NumElems; ++i)
23144 ShuffleVec[i] = i * SizeRatio;
23146 // Can't shuffle using an illegal type.
23147 if (!TLI.isTypeLegal(WideVecVT))
23150 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23151 DAG.getUNDEF(WideVecVT),
23153 // At this point all of the data is stored at the bottom of the
23154 // register. We now need to save it to mem.
23156 // Find the largest store unit
23157 MVT StoreType = MVT::i8;
23158 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23159 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23160 MVT Tp = (MVT::SimpleValueType)tp;
23161 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23165 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23166 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23167 (64 <= NumElems * ToSz))
23168 StoreType = MVT::f64;
23170 // Bitcast the original vector into a vector of store-size units
23171 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23172 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23173 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23174 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23175 SmallVector<SDValue, 8> Chains;
23176 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23177 TLI.getPointerTy());
23178 SDValue Ptr = St->getBasePtr();
23180 // Perform one or more big stores into memory.
23181 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23182 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23183 StoreType, ShuffWide,
23184 DAG.getIntPtrConstant(i));
23185 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23186 St->getPointerInfo(), St->isVolatile(),
23187 St->isNonTemporal(), St->getAlignment());
23188 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23189 Chains.push_back(Ch);
23192 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23195 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23196 // the FP state in cases where an emms may be missing.
23197 // A preferable solution to the general problem is to figure out the right
23198 // places to insert EMMS. This qualifies as a quick hack.
23200 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23201 if (VT.getSizeInBits() != 64)
23204 const Function *F = DAG.getMachineFunction().getFunction();
23205 bool NoImplicitFloatOps = F->getAttributes().
23206 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23207 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23208 && Subtarget->hasSSE2();
23209 if ((VT.isVector() ||
23210 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23211 isa<LoadSDNode>(St->getValue()) &&
23212 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23213 St->getChain().hasOneUse() && !St->isVolatile()) {
23214 SDNode* LdVal = St->getValue().getNode();
23215 LoadSDNode *Ld = nullptr;
23216 int TokenFactorIndex = -1;
23217 SmallVector<SDValue, 8> Ops;
23218 SDNode* ChainVal = St->getChain().getNode();
23219 // Must be a store of a load. We currently handle two cases: the load
23220 // is a direct child, and it's under an intervening TokenFactor. It is
23221 // possible to dig deeper under nested TokenFactors.
23222 if (ChainVal == LdVal)
23223 Ld = cast<LoadSDNode>(St->getChain());
23224 else if (St->getValue().hasOneUse() &&
23225 ChainVal->getOpcode() == ISD::TokenFactor) {
23226 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23227 if (ChainVal->getOperand(i).getNode() == LdVal) {
23228 TokenFactorIndex = i;
23229 Ld = cast<LoadSDNode>(St->getValue());
23231 Ops.push_back(ChainVal->getOperand(i));
23235 if (!Ld || !ISD::isNormalLoad(Ld))
23238 // If this is not the MMX case, i.e. we are just turning i64 load/store
23239 // into f64 load/store, avoid the transformation if there are multiple
23240 // uses of the loaded value.
23241 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23246 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23247 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23249 if (Subtarget->is64Bit() || F64IsLegal) {
23250 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23251 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23252 Ld->getPointerInfo(), Ld->isVolatile(),
23253 Ld->isNonTemporal(), Ld->isInvariant(),
23254 Ld->getAlignment());
23255 SDValue NewChain = NewLd.getValue(1);
23256 if (TokenFactorIndex != -1) {
23257 Ops.push_back(NewChain);
23258 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23260 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23261 St->getPointerInfo(),
23262 St->isVolatile(), St->isNonTemporal(),
23263 St->getAlignment());
23266 // Otherwise, lower to two pairs of 32-bit loads / stores.
23267 SDValue LoAddr = Ld->getBasePtr();
23268 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23269 DAG.getConstant(4, MVT::i32));
23271 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23272 Ld->getPointerInfo(),
23273 Ld->isVolatile(), Ld->isNonTemporal(),
23274 Ld->isInvariant(), Ld->getAlignment());
23275 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23276 Ld->getPointerInfo().getWithOffset(4),
23277 Ld->isVolatile(), Ld->isNonTemporal(),
23279 MinAlign(Ld->getAlignment(), 4));
23281 SDValue NewChain = LoLd.getValue(1);
23282 if (TokenFactorIndex != -1) {
23283 Ops.push_back(LoLd);
23284 Ops.push_back(HiLd);
23285 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23288 LoAddr = St->getBasePtr();
23289 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23290 DAG.getConstant(4, MVT::i32));
23292 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23293 St->getPointerInfo(),
23294 St->isVolatile(), St->isNonTemporal(),
23295 St->getAlignment());
23296 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23297 St->getPointerInfo().getWithOffset(4),
23299 St->isNonTemporal(),
23300 MinAlign(St->getAlignment(), 4));
23301 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23306 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23307 /// and return the operands for the horizontal operation in LHS and RHS. A
23308 /// horizontal operation performs the binary operation on successive elements
23309 /// of its first operand, then on successive elements of its second operand,
23310 /// returning the resulting values in a vector. For example, if
23311 /// A = < float a0, float a1, float a2, float a3 >
23313 /// B = < float b0, float b1, float b2, float b3 >
23314 /// then the result of doing a horizontal operation on A and B is
23315 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23316 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23317 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23318 /// set to A, RHS to B, and the routine returns 'true'.
23319 /// Note that the binary operation should have the property that if one of the
23320 /// operands is UNDEF then the result is UNDEF.
23321 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23322 // Look for the following pattern: if
23323 // A = < float a0, float a1, float a2, float a3 >
23324 // B = < float b0, float b1, float b2, float b3 >
23326 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23327 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23328 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23329 // which is A horizontal-op B.
23331 // At least one of the operands should be a vector shuffle.
23332 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23333 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23336 MVT VT = LHS.getSimpleValueType();
23338 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23339 "Unsupported vector type for horizontal add/sub");
23341 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23342 // operate independently on 128-bit lanes.
23343 unsigned NumElts = VT.getVectorNumElements();
23344 unsigned NumLanes = VT.getSizeInBits()/128;
23345 unsigned NumLaneElts = NumElts / NumLanes;
23346 assert((NumLaneElts % 2 == 0) &&
23347 "Vector type should have an even number of elements in each lane");
23348 unsigned HalfLaneElts = NumLaneElts/2;
23350 // View LHS in the form
23351 // LHS = VECTOR_SHUFFLE A, B, LMask
23352 // If LHS is not a shuffle then pretend it is the shuffle
23353 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23354 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23357 SmallVector<int, 16> LMask(NumElts);
23358 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23359 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23360 A = LHS.getOperand(0);
23361 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23362 B = LHS.getOperand(1);
23363 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23364 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23366 if (LHS.getOpcode() != ISD::UNDEF)
23368 for (unsigned i = 0; i != NumElts; ++i)
23372 // Likewise, view RHS in the form
23373 // RHS = VECTOR_SHUFFLE C, D, RMask
23375 SmallVector<int, 16> RMask(NumElts);
23376 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23377 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23378 C = RHS.getOperand(0);
23379 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23380 D = RHS.getOperand(1);
23381 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23382 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23384 if (RHS.getOpcode() != ISD::UNDEF)
23386 for (unsigned i = 0; i != NumElts; ++i)
23390 // Check that the shuffles are both shuffling the same vectors.
23391 if (!(A == C && B == D) && !(A == D && B == C))
23394 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23395 if (!A.getNode() && !B.getNode())
23398 // If A and B occur in reverse order in RHS, then "swap" them (which means
23399 // rewriting the mask).
23401 CommuteVectorShuffleMask(RMask, NumElts);
23403 // At this point LHS and RHS are equivalent to
23404 // LHS = VECTOR_SHUFFLE A, B, LMask
23405 // RHS = VECTOR_SHUFFLE A, B, RMask
23406 // Check that the masks correspond to performing a horizontal operation.
23407 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23408 for (unsigned i = 0; i != NumLaneElts; ++i) {
23409 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23411 // Ignore any UNDEF components.
23412 if (LIdx < 0 || RIdx < 0 ||
23413 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23414 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23417 // Check that successive elements are being operated on. If not, this is
23418 // not a horizontal operation.
23419 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23420 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23421 if (!(LIdx == Index && RIdx == Index + 1) &&
23422 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23427 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23428 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23432 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23433 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23434 const X86Subtarget *Subtarget) {
23435 EVT VT = N->getValueType(0);
23436 SDValue LHS = N->getOperand(0);
23437 SDValue RHS = N->getOperand(1);
23439 // Try to synthesize horizontal adds from adds of shuffles.
23440 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23441 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23442 isHorizontalBinOp(LHS, RHS, true))
23443 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23447 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23448 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23449 const X86Subtarget *Subtarget) {
23450 EVT VT = N->getValueType(0);
23451 SDValue LHS = N->getOperand(0);
23452 SDValue RHS = N->getOperand(1);
23454 // Try to synthesize horizontal subs from subs of shuffles.
23455 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23456 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23457 isHorizontalBinOp(LHS, RHS, false))
23458 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23462 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23463 /// X86ISD::FXOR nodes.
23464 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23465 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23466 // F[X]OR(0.0, x) -> x
23467 // F[X]OR(x, 0.0) -> x
23468 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23469 if (C->getValueAPF().isPosZero())
23470 return N->getOperand(1);
23471 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23472 if (C->getValueAPF().isPosZero())
23473 return N->getOperand(0);
23477 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23478 /// X86ISD::FMAX nodes.
23479 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23480 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23482 // Only perform optimizations if UnsafeMath is used.
23483 if (!DAG.getTarget().Options.UnsafeFPMath)
23486 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23487 // into FMINC and FMAXC, which are Commutative operations.
23488 unsigned NewOp = 0;
23489 switch (N->getOpcode()) {
23490 default: llvm_unreachable("unknown opcode");
23491 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23492 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23495 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23496 N->getOperand(0), N->getOperand(1));
23499 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23500 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23501 // FAND(0.0, x) -> 0.0
23502 // FAND(x, 0.0) -> 0.0
23503 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23504 if (C->getValueAPF().isPosZero())
23505 return N->getOperand(0);
23506 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23507 if (C->getValueAPF().isPosZero())
23508 return N->getOperand(1);
23512 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23513 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23514 // FANDN(x, 0.0) -> 0.0
23515 // FANDN(0.0, x) -> x
23516 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23517 if (C->getValueAPF().isPosZero())
23518 return N->getOperand(1);
23519 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23520 if (C->getValueAPF().isPosZero())
23521 return N->getOperand(1);
23525 static SDValue PerformBTCombine(SDNode *N,
23527 TargetLowering::DAGCombinerInfo &DCI) {
23528 // BT ignores high bits in the bit index operand.
23529 SDValue Op1 = N->getOperand(1);
23530 if (Op1.hasOneUse()) {
23531 unsigned BitWidth = Op1.getValueSizeInBits();
23532 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23533 APInt KnownZero, KnownOne;
23534 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23535 !DCI.isBeforeLegalizeOps());
23536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23537 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23538 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23539 DCI.CommitTargetLoweringOpt(TLO);
23544 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23545 SDValue Op = N->getOperand(0);
23546 if (Op.getOpcode() == ISD::BITCAST)
23547 Op = Op.getOperand(0);
23548 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23549 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23550 VT.getVectorElementType().getSizeInBits() ==
23551 OpVT.getVectorElementType().getSizeInBits()) {
23552 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23557 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23558 const X86Subtarget *Subtarget) {
23559 EVT VT = N->getValueType(0);
23560 if (!VT.isVector())
23563 SDValue N0 = N->getOperand(0);
23564 SDValue N1 = N->getOperand(1);
23565 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23568 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23569 // both SSE and AVX2 since there is no sign-extended shift right
23570 // operation on a vector with 64-bit elements.
23571 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23572 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23573 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23574 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23575 SDValue N00 = N0.getOperand(0);
23577 // EXTLOAD has a better solution on AVX2,
23578 // it may be replaced with X86ISD::VSEXT node.
23579 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23580 if (!ISD::isNormalLoad(N00.getNode()))
23583 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23584 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23586 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23592 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23593 TargetLowering::DAGCombinerInfo &DCI,
23594 const X86Subtarget *Subtarget) {
23595 if (!DCI.isBeforeLegalizeOps())
23598 if (!Subtarget->hasFp256())
23601 EVT VT = N->getValueType(0);
23602 if (VT.isVector() && VT.getSizeInBits() == 256) {
23603 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23611 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23612 const X86Subtarget* Subtarget) {
23614 EVT VT = N->getValueType(0);
23616 // Let legalize expand this if it isn't a legal type yet.
23617 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23620 EVT ScalarVT = VT.getScalarType();
23621 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23622 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23625 SDValue A = N->getOperand(0);
23626 SDValue B = N->getOperand(1);
23627 SDValue C = N->getOperand(2);
23629 bool NegA = (A.getOpcode() == ISD::FNEG);
23630 bool NegB = (B.getOpcode() == ISD::FNEG);
23631 bool NegC = (C.getOpcode() == ISD::FNEG);
23633 // Negative multiplication when NegA xor NegB
23634 bool NegMul = (NegA != NegB);
23636 A = A.getOperand(0);
23638 B = B.getOperand(0);
23640 C = C.getOperand(0);
23644 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23646 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23648 return DAG.getNode(Opcode, dl, VT, A, B, C);
23651 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23652 TargetLowering::DAGCombinerInfo &DCI,
23653 const X86Subtarget *Subtarget) {
23654 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23655 // (and (i32 x86isd::setcc_carry), 1)
23656 // This eliminates the zext. This transformation is necessary because
23657 // ISD::SETCC is always legalized to i8.
23659 SDValue N0 = N->getOperand(0);
23660 EVT VT = N->getValueType(0);
23662 if (N0.getOpcode() == ISD::AND &&
23664 N0.getOperand(0).hasOneUse()) {
23665 SDValue N00 = N0.getOperand(0);
23666 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23667 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23668 if (!C || C->getZExtValue() != 1)
23670 return DAG.getNode(ISD::AND, dl, VT,
23671 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23672 N00.getOperand(0), N00.getOperand(1)),
23673 DAG.getConstant(1, VT));
23677 if (N0.getOpcode() == ISD::TRUNCATE &&
23679 N0.getOperand(0).hasOneUse()) {
23680 SDValue N00 = N0.getOperand(0);
23681 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23682 return DAG.getNode(ISD::AND, dl, VT,
23683 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23684 N00.getOperand(0), N00.getOperand(1)),
23685 DAG.getConstant(1, VT));
23688 if (VT.is256BitVector()) {
23689 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23697 // Optimize x == -y --> x+y == 0
23698 // x != -y --> x+y != 0
23699 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23700 const X86Subtarget* Subtarget) {
23701 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23702 SDValue LHS = N->getOperand(0);
23703 SDValue RHS = N->getOperand(1);
23704 EVT VT = N->getValueType(0);
23707 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23708 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23709 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23710 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23711 LHS.getValueType(), RHS, LHS.getOperand(1));
23712 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23713 addV, DAG.getConstant(0, addV.getValueType()), CC);
23715 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23716 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23717 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23718 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23719 RHS.getValueType(), LHS, RHS.getOperand(1));
23720 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23721 addV, DAG.getConstant(0, addV.getValueType()), CC);
23724 if (VT.getScalarType() == MVT::i1) {
23725 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23726 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23727 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23728 if (!IsSEXT0 && !IsVZero0)
23730 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23731 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23732 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23734 if (!IsSEXT1 && !IsVZero1)
23737 if (IsSEXT0 && IsVZero1) {
23738 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23739 if (CC == ISD::SETEQ)
23740 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23741 return LHS.getOperand(0);
23743 if (IsSEXT1 && IsVZero0) {
23744 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23745 if (CC == ISD::SETEQ)
23746 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23747 return RHS.getOperand(0);
23754 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23755 const X86Subtarget *Subtarget) {
23757 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23758 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23759 "X86insertps is only defined for v4x32");
23761 SDValue Ld = N->getOperand(1);
23762 if (MayFoldLoad(Ld)) {
23763 // Extract the countS bits from the immediate so we can get the proper
23764 // address when narrowing the vector load to a specific element.
23765 // When the second source op is a memory address, interps doesn't use
23766 // countS and just gets an f32 from that address.
23767 unsigned DestIndex =
23768 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23769 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23773 // Create this as a scalar to vector to match the instruction pattern.
23774 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23775 // countS bits are ignored when loading from memory on insertps, which
23776 // means we don't need to explicitly set them to 0.
23777 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23778 LoadScalarToVector, N->getOperand(2));
23781 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23782 // as "sbb reg,reg", since it can be extended without zext and produces
23783 // an all-ones bit which is more useful than 0/1 in some cases.
23784 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23787 return DAG.getNode(ISD::AND, DL, VT,
23788 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23789 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23790 DAG.getConstant(1, VT));
23791 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23792 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23793 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23794 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23797 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23798 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23799 TargetLowering::DAGCombinerInfo &DCI,
23800 const X86Subtarget *Subtarget) {
23802 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23803 SDValue EFLAGS = N->getOperand(1);
23805 if (CC == X86::COND_A) {
23806 // Try to convert COND_A into COND_B in an attempt to facilitate
23807 // materializing "setb reg".
23809 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23810 // cannot take an immediate as its first operand.
23812 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23813 EFLAGS.getValueType().isInteger() &&
23814 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23815 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23816 EFLAGS.getNode()->getVTList(),
23817 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23818 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23819 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23823 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23824 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23826 if (CC == X86::COND_B)
23827 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23831 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23832 if (Flags.getNode()) {
23833 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23834 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23840 // Optimize branch condition evaluation.
23842 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23843 TargetLowering::DAGCombinerInfo &DCI,
23844 const X86Subtarget *Subtarget) {
23846 SDValue Chain = N->getOperand(0);
23847 SDValue Dest = N->getOperand(1);
23848 SDValue EFLAGS = N->getOperand(3);
23849 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23853 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23854 if (Flags.getNode()) {
23855 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23856 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23863 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23864 SelectionDAG &DAG) {
23865 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23866 // optimize away operation when it's from a constant.
23868 // The general transformation is:
23869 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23870 // AND(VECTOR_CMP(x,y), constant2)
23871 // constant2 = UNARYOP(constant)
23873 // Early exit if this isn't a vector operation, the operand of the
23874 // unary operation isn't a bitwise AND, or if the sizes of the operations
23875 // aren't the same.
23876 EVT VT = N->getValueType(0);
23877 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23878 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23879 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23882 // Now check that the other operand of the AND is a constant. We could
23883 // make the transformation for non-constant splats as well, but it's unclear
23884 // that would be a benefit as it would not eliminate any operations, just
23885 // perform one more step in scalar code before moving to the vector unit.
23886 if (BuildVectorSDNode *BV =
23887 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23888 // Bail out if the vector isn't a constant.
23889 if (!BV->isConstant())
23892 // Everything checks out. Build up the new and improved node.
23894 EVT IntVT = BV->getValueType(0);
23895 // Create a new constant of the appropriate type for the transformed
23897 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23898 // The AND node needs bitcasts to/from an integer vector type around it.
23899 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23900 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23901 N->getOperand(0)->getOperand(0), MaskConst);
23902 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23909 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23910 const X86TargetLowering *XTLI) {
23911 // First try to optimize away the conversion entirely when it's
23912 // conditionally from a constant. Vectors only.
23913 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23914 if (Res != SDValue())
23917 // Now move on to more general possibilities.
23918 SDValue Op0 = N->getOperand(0);
23919 EVT InVT = Op0->getValueType(0);
23921 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23922 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23924 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23925 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23926 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23929 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23930 // a 32-bit target where SSE doesn't support i64->FP operations.
23931 if (Op0.getOpcode() == ISD::LOAD) {
23932 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23933 EVT VT = Ld->getValueType(0);
23934 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23935 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23936 !XTLI->getSubtarget()->is64Bit() &&
23938 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23939 Ld->getChain(), Op0, DAG);
23940 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23947 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23948 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23949 X86TargetLowering::DAGCombinerInfo &DCI) {
23950 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23951 // the result is either zero or one (depending on the input carry bit).
23952 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23953 if (X86::isZeroNode(N->getOperand(0)) &&
23954 X86::isZeroNode(N->getOperand(1)) &&
23955 // We don't have a good way to replace an EFLAGS use, so only do this when
23957 SDValue(N, 1).use_empty()) {
23959 EVT VT = N->getValueType(0);
23960 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23961 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23962 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23963 DAG.getConstant(X86::COND_B,MVT::i8),
23965 DAG.getConstant(1, VT));
23966 return DCI.CombineTo(N, Res1, CarryOut);
23972 // fold (add Y, (sete X, 0)) -> adc 0, Y
23973 // (add Y, (setne X, 0)) -> sbb -1, Y
23974 // (sub (sete X, 0), Y) -> sbb 0, Y
23975 // (sub (setne X, 0), Y) -> adc -1, Y
23976 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23979 // Look through ZExts.
23980 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23981 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23984 SDValue SetCC = Ext.getOperand(0);
23985 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23988 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23989 if (CC != X86::COND_E && CC != X86::COND_NE)
23992 SDValue Cmp = SetCC.getOperand(1);
23993 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23994 !X86::isZeroNode(Cmp.getOperand(1)) ||
23995 !Cmp.getOperand(0).getValueType().isInteger())
23998 SDValue CmpOp0 = Cmp.getOperand(0);
23999 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24000 DAG.getConstant(1, CmpOp0.getValueType()));
24002 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24003 if (CC == X86::COND_NE)
24004 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24005 DL, OtherVal.getValueType(), OtherVal,
24006 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24007 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24008 DL, OtherVal.getValueType(), OtherVal,
24009 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24012 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24013 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24014 const X86Subtarget *Subtarget) {
24015 EVT VT = N->getValueType(0);
24016 SDValue Op0 = N->getOperand(0);
24017 SDValue Op1 = N->getOperand(1);
24019 // Try to synthesize horizontal adds from adds of shuffles.
24020 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24021 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24022 isHorizontalBinOp(Op0, Op1, true))
24023 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24025 return OptimizeConditionalInDecrement(N, DAG);
24028 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24029 const X86Subtarget *Subtarget) {
24030 SDValue Op0 = N->getOperand(0);
24031 SDValue Op1 = N->getOperand(1);
24033 // X86 can't encode an immediate LHS of a sub. See if we can push the
24034 // negation into a preceding instruction.
24035 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24036 // If the RHS of the sub is a XOR with one use and a constant, invert the
24037 // immediate. Then add one to the LHS of the sub so we can turn
24038 // X-Y -> X+~Y+1, saving one register.
24039 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24040 isa<ConstantSDNode>(Op1.getOperand(1))) {
24041 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24042 EVT VT = Op0.getValueType();
24043 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24045 DAG.getConstant(~XorC, VT));
24046 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24047 DAG.getConstant(C->getAPIntValue()+1, VT));
24051 // Try to synthesize horizontal adds from adds of shuffles.
24052 EVT VT = N->getValueType(0);
24053 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24054 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24055 isHorizontalBinOp(Op0, Op1, true))
24056 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24058 return OptimizeConditionalInDecrement(N, DAG);
24061 /// performVZEXTCombine - Performs build vector combines
24062 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24063 TargetLowering::DAGCombinerInfo &DCI,
24064 const X86Subtarget *Subtarget) {
24065 // (vzext (bitcast (vzext (x)) -> (vzext x)
24066 SDValue In = N->getOperand(0);
24067 while (In.getOpcode() == ISD::BITCAST)
24068 In = In.getOperand(0);
24070 if (In.getOpcode() != X86ISD::VZEXT)
24073 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24077 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24078 DAGCombinerInfo &DCI) const {
24079 SelectionDAG &DAG = DCI.DAG;
24080 switch (N->getOpcode()) {
24082 case ISD::EXTRACT_VECTOR_ELT:
24083 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24085 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24086 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24087 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24088 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24089 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24090 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24093 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24094 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24095 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24096 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24097 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24098 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24099 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24100 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24101 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24103 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24105 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24106 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24107 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24108 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24109 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24110 case ISD::ANY_EXTEND:
24111 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24112 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24113 case ISD::SIGN_EXTEND_INREG:
24114 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24115 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24116 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24117 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24118 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24119 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24120 case X86ISD::SHUFP: // Handle all target specific shuffles
24121 case X86ISD::PALIGNR:
24122 case X86ISD::UNPCKH:
24123 case X86ISD::UNPCKL:
24124 case X86ISD::MOVHLPS:
24125 case X86ISD::MOVLHPS:
24126 case X86ISD::PSHUFB:
24127 case X86ISD::PSHUFD:
24128 case X86ISD::PSHUFHW:
24129 case X86ISD::PSHUFLW:
24130 case X86ISD::MOVSS:
24131 case X86ISD::MOVSD:
24132 case X86ISD::VPERMILPI:
24133 case X86ISD::VPERM2X128:
24134 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24135 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24136 case ISD::INTRINSIC_WO_CHAIN:
24137 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24138 case X86ISD::INSERTPS:
24139 return PerformINSERTPSCombine(N, DAG, Subtarget);
24140 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24146 /// isTypeDesirableForOp - Return true if the target has native support for
24147 /// the specified value type and it is 'desirable' to use the type for the
24148 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24149 /// instruction encodings are longer and some i16 instructions are slow.
24150 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24151 if (!isTypeLegal(VT))
24153 if (VT != MVT::i16)
24160 case ISD::SIGN_EXTEND:
24161 case ISD::ZERO_EXTEND:
24162 case ISD::ANY_EXTEND:
24175 /// IsDesirableToPromoteOp - This method query the target whether it is
24176 /// beneficial for dag combiner to promote the specified node. If true, it
24177 /// should return the desired promotion type by reference.
24178 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24179 EVT VT = Op.getValueType();
24180 if (VT != MVT::i16)
24183 bool Promote = false;
24184 bool Commute = false;
24185 switch (Op.getOpcode()) {
24188 LoadSDNode *LD = cast<LoadSDNode>(Op);
24189 // If the non-extending load has a single use and it's not live out, then it
24190 // might be folded.
24191 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24192 Op.hasOneUse()*/) {
24193 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24194 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24195 // The only case where we'd want to promote LOAD (rather then it being
24196 // promoted as an operand is when it's only use is liveout.
24197 if (UI->getOpcode() != ISD::CopyToReg)
24204 case ISD::SIGN_EXTEND:
24205 case ISD::ZERO_EXTEND:
24206 case ISD::ANY_EXTEND:
24211 SDValue N0 = Op.getOperand(0);
24212 // Look out for (store (shl (load), x)).
24213 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24226 SDValue N0 = Op.getOperand(0);
24227 SDValue N1 = Op.getOperand(1);
24228 if (!Commute && MayFoldLoad(N1))
24230 // Avoid disabling potential load folding opportunities.
24231 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24233 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24243 //===----------------------------------------------------------------------===//
24244 // X86 Inline Assembly Support
24245 //===----------------------------------------------------------------------===//
24248 // Helper to match a string separated by whitespace.
24249 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24250 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24252 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24253 StringRef piece(*args[i]);
24254 if (!s.startswith(piece)) // Check if the piece matches.
24257 s = s.substr(piece.size());
24258 StringRef::size_type pos = s.find_first_not_of(" \t");
24259 if (pos == 0) // We matched a prefix.
24267 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24270 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24272 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24273 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24274 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24275 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24277 if (AsmPieces.size() == 3)
24279 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24286 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24287 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24289 std::string AsmStr = IA->getAsmString();
24291 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24292 if (!Ty || Ty->getBitWidth() % 16 != 0)
24295 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24296 SmallVector<StringRef, 4> AsmPieces;
24297 SplitString(AsmStr, AsmPieces, ";\n");
24299 switch (AsmPieces.size()) {
24300 default: return false;
24302 // FIXME: this should verify that we are targeting a 486 or better. If not,
24303 // we will turn this bswap into something that will be lowered to logical
24304 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24305 // lower so don't worry about this.
24307 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24308 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24309 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24310 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24311 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24312 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24313 // No need to check constraints, nothing other than the equivalent of
24314 // "=r,0" would be valid here.
24315 return IntrinsicLowering::LowerToByteSwap(CI);
24318 // rorw $$8, ${0:w} --> llvm.bswap.i16
24319 if (CI->getType()->isIntegerTy(16) &&
24320 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24321 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24322 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24324 const std::string &ConstraintsStr = IA->getConstraintString();
24325 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24326 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24327 if (clobbersFlagRegisters(AsmPieces))
24328 return IntrinsicLowering::LowerToByteSwap(CI);
24332 if (CI->getType()->isIntegerTy(32) &&
24333 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24334 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24335 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24336 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24338 const std::string &ConstraintsStr = IA->getConstraintString();
24339 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24340 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24341 if (clobbersFlagRegisters(AsmPieces))
24342 return IntrinsicLowering::LowerToByteSwap(CI);
24345 if (CI->getType()->isIntegerTy(64)) {
24346 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24347 if (Constraints.size() >= 2 &&
24348 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24349 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24350 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24351 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24352 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24353 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24354 return IntrinsicLowering::LowerToByteSwap(CI);
24362 /// getConstraintType - Given a constraint letter, return the type of
24363 /// constraint it is for this target.
24364 X86TargetLowering::ConstraintType
24365 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24366 if (Constraint.size() == 1) {
24367 switch (Constraint[0]) {
24378 return C_RegisterClass;
24402 return TargetLowering::getConstraintType(Constraint);
24405 /// Examine constraint type and operand type and determine a weight value.
24406 /// This object must already have been set up with the operand type
24407 /// and the current alternative constraint selected.
24408 TargetLowering::ConstraintWeight
24409 X86TargetLowering::getSingleConstraintMatchWeight(
24410 AsmOperandInfo &info, const char *constraint) const {
24411 ConstraintWeight weight = CW_Invalid;
24412 Value *CallOperandVal = info.CallOperandVal;
24413 // If we don't have a value, we can't do a match,
24414 // but allow it at the lowest weight.
24415 if (!CallOperandVal)
24417 Type *type = CallOperandVal->getType();
24418 // Look at the constraint type.
24419 switch (*constraint) {
24421 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24432 if (CallOperandVal->getType()->isIntegerTy())
24433 weight = CW_SpecificReg;
24438 if (type->isFloatingPointTy())
24439 weight = CW_SpecificReg;
24442 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24443 weight = CW_SpecificReg;
24447 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24448 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24449 weight = CW_Register;
24452 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24453 if (C->getZExtValue() <= 31)
24454 weight = CW_Constant;
24458 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24459 if (C->getZExtValue() <= 63)
24460 weight = CW_Constant;
24464 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24465 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24466 weight = CW_Constant;
24470 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24471 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24472 weight = CW_Constant;
24476 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24477 if (C->getZExtValue() <= 3)
24478 weight = CW_Constant;
24482 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24483 if (C->getZExtValue() <= 0xff)
24484 weight = CW_Constant;
24489 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24490 weight = CW_Constant;
24494 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24495 if ((C->getSExtValue() >= -0x80000000LL) &&
24496 (C->getSExtValue() <= 0x7fffffffLL))
24497 weight = CW_Constant;
24501 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24502 if (C->getZExtValue() <= 0xffffffff)
24503 weight = CW_Constant;
24510 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24511 /// with another that has more specific requirements based on the type of the
24512 /// corresponding operand.
24513 const char *X86TargetLowering::
24514 LowerXConstraint(EVT ConstraintVT) const {
24515 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24516 // 'f' like normal targets.
24517 if (ConstraintVT.isFloatingPoint()) {
24518 if (Subtarget->hasSSE2())
24520 if (Subtarget->hasSSE1())
24524 return TargetLowering::LowerXConstraint(ConstraintVT);
24527 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24528 /// vector. If it is invalid, don't add anything to Ops.
24529 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24530 std::string &Constraint,
24531 std::vector<SDValue>&Ops,
24532 SelectionDAG &DAG) const {
24535 // Only support length 1 constraints for now.
24536 if (Constraint.length() > 1) return;
24538 char ConstraintLetter = Constraint[0];
24539 switch (ConstraintLetter) {
24542 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24543 if (C->getZExtValue() <= 31) {
24544 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24550 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24551 if (C->getZExtValue() <= 63) {
24552 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24558 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24559 if (isInt<8>(C->getSExtValue())) {
24560 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24566 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24567 if (C->getZExtValue() <= 255) {
24568 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24574 // 32-bit signed value
24575 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24576 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24577 C->getSExtValue())) {
24578 // Widen to 64 bits here to get it sign extended.
24579 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24582 // FIXME gcc accepts some relocatable values here too, but only in certain
24583 // memory models; it's complicated.
24588 // 32-bit unsigned value
24589 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24590 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24591 C->getZExtValue())) {
24592 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24596 // FIXME gcc accepts some relocatable values here too, but only in certain
24597 // memory models; it's complicated.
24601 // Literal immediates are always ok.
24602 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24603 // Widen to 64 bits here to get it sign extended.
24604 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24608 // In any sort of PIC mode addresses need to be computed at runtime by
24609 // adding in a register or some sort of table lookup. These can't
24610 // be used as immediates.
24611 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24614 // If we are in non-pic codegen mode, we allow the address of a global (with
24615 // an optional displacement) to be used with 'i'.
24616 GlobalAddressSDNode *GA = nullptr;
24617 int64_t Offset = 0;
24619 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24621 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24622 Offset += GA->getOffset();
24624 } else if (Op.getOpcode() == ISD::ADD) {
24625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24626 Offset += C->getZExtValue();
24627 Op = Op.getOperand(0);
24630 } else if (Op.getOpcode() == ISD::SUB) {
24631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24632 Offset += -C->getZExtValue();
24633 Op = Op.getOperand(0);
24638 // Otherwise, this isn't something we can handle, reject it.
24642 const GlobalValue *GV = GA->getGlobal();
24643 // If we require an extra load to get this address, as in PIC mode, we
24644 // can't accept it.
24645 if (isGlobalStubReference(
24646 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24649 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24650 GA->getValueType(0), Offset);
24655 if (Result.getNode()) {
24656 Ops.push_back(Result);
24659 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24662 std::pair<unsigned, const TargetRegisterClass*>
24663 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24665 // First, see if this is a constraint that directly corresponds to an LLVM
24667 if (Constraint.size() == 1) {
24668 // GCC Constraint Letters
24669 switch (Constraint[0]) {
24671 // TODO: Slight differences here in allocation order and leaving
24672 // RIP in the class. Do they matter any more here than they do
24673 // in the normal allocation?
24674 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24675 if (Subtarget->is64Bit()) {
24676 if (VT == MVT::i32 || VT == MVT::f32)
24677 return std::make_pair(0U, &X86::GR32RegClass);
24678 if (VT == MVT::i16)
24679 return std::make_pair(0U, &X86::GR16RegClass);
24680 if (VT == MVT::i8 || VT == MVT::i1)
24681 return std::make_pair(0U, &X86::GR8RegClass);
24682 if (VT == MVT::i64 || VT == MVT::f64)
24683 return std::make_pair(0U, &X86::GR64RegClass);
24686 // 32-bit fallthrough
24687 case 'Q': // Q_REGS
24688 if (VT == MVT::i32 || VT == MVT::f32)
24689 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24690 if (VT == MVT::i16)
24691 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24692 if (VT == MVT::i8 || VT == MVT::i1)
24693 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24694 if (VT == MVT::i64)
24695 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24697 case 'r': // GENERAL_REGS
24698 case 'l': // INDEX_REGS
24699 if (VT == MVT::i8 || VT == MVT::i1)
24700 return std::make_pair(0U, &X86::GR8RegClass);
24701 if (VT == MVT::i16)
24702 return std::make_pair(0U, &X86::GR16RegClass);
24703 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24704 return std::make_pair(0U, &X86::GR32RegClass);
24705 return std::make_pair(0U, &X86::GR64RegClass);
24706 case 'R': // LEGACY_REGS
24707 if (VT == MVT::i8 || VT == MVT::i1)
24708 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24709 if (VT == MVT::i16)
24710 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24711 if (VT == MVT::i32 || !Subtarget->is64Bit())
24712 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24713 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24714 case 'f': // FP Stack registers.
24715 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24716 // value to the correct fpstack register class.
24717 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24718 return std::make_pair(0U, &X86::RFP32RegClass);
24719 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24720 return std::make_pair(0U, &X86::RFP64RegClass);
24721 return std::make_pair(0U, &X86::RFP80RegClass);
24722 case 'y': // MMX_REGS if MMX allowed.
24723 if (!Subtarget->hasMMX()) break;
24724 return std::make_pair(0U, &X86::VR64RegClass);
24725 case 'Y': // SSE_REGS if SSE2 allowed
24726 if (!Subtarget->hasSSE2()) break;
24728 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24729 if (!Subtarget->hasSSE1()) break;
24731 switch (VT.SimpleTy) {
24733 // Scalar SSE types.
24736 return std::make_pair(0U, &X86::FR32RegClass);
24739 return std::make_pair(0U, &X86::FR64RegClass);
24747 return std::make_pair(0U, &X86::VR128RegClass);
24755 return std::make_pair(0U, &X86::VR256RegClass);
24760 return std::make_pair(0U, &X86::VR512RegClass);
24766 // Use the default implementation in TargetLowering to convert the register
24767 // constraint into a member of a register class.
24768 std::pair<unsigned, const TargetRegisterClass*> Res;
24769 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24771 // Not found as a standard register?
24773 // Map st(0) -> st(7) -> ST0
24774 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24775 tolower(Constraint[1]) == 's' &&
24776 tolower(Constraint[2]) == 't' &&
24777 Constraint[3] == '(' &&
24778 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24779 Constraint[5] == ')' &&
24780 Constraint[6] == '}') {
24782 Res.first = X86::FP0+Constraint[4]-'0';
24783 Res.second = &X86::RFP80RegClass;
24787 // GCC allows "st(0)" to be called just plain "st".
24788 if (StringRef("{st}").equals_lower(Constraint)) {
24789 Res.first = X86::FP0;
24790 Res.second = &X86::RFP80RegClass;
24795 if (StringRef("{flags}").equals_lower(Constraint)) {
24796 Res.first = X86::EFLAGS;
24797 Res.second = &X86::CCRRegClass;
24801 // 'A' means EAX + EDX.
24802 if (Constraint == "A") {
24803 Res.first = X86::EAX;
24804 Res.second = &X86::GR32_ADRegClass;
24810 // Otherwise, check to see if this is a register class of the wrong value
24811 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24812 // turn into {ax},{dx}.
24813 if (Res.second->hasType(VT))
24814 return Res; // Correct type already, nothing to do.
24816 // All of the single-register GCC register classes map their values onto
24817 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24818 // really want an 8-bit or 32-bit register, map to the appropriate register
24819 // class and return the appropriate register.
24820 if (Res.second == &X86::GR16RegClass) {
24821 if (VT == MVT::i8 || VT == MVT::i1) {
24822 unsigned DestReg = 0;
24823 switch (Res.first) {
24825 case X86::AX: DestReg = X86::AL; break;
24826 case X86::DX: DestReg = X86::DL; break;
24827 case X86::CX: DestReg = X86::CL; break;
24828 case X86::BX: DestReg = X86::BL; break;
24831 Res.first = DestReg;
24832 Res.second = &X86::GR8RegClass;
24834 } else if (VT == MVT::i32 || VT == MVT::f32) {
24835 unsigned DestReg = 0;
24836 switch (Res.first) {
24838 case X86::AX: DestReg = X86::EAX; break;
24839 case X86::DX: DestReg = X86::EDX; break;
24840 case X86::CX: DestReg = X86::ECX; break;
24841 case X86::BX: DestReg = X86::EBX; break;
24842 case X86::SI: DestReg = X86::ESI; break;
24843 case X86::DI: DestReg = X86::EDI; break;
24844 case X86::BP: DestReg = X86::EBP; break;
24845 case X86::SP: DestReg = X86::ESP; break;
24848 Res.first = DestReg;
24849 Res.second = &X86::GR32RegClass;
24851 } else if (VT == MVT::i64 || VT == MVT::f64) {
24852 unsigned DestReg = 0;
24853 switch (Res.first) {
24855 case X86::AX: DestReg = X86::RAX; break;
24856 case X86::DX: DestReg = X86::RDX; break;
24857 case X86::CX: DestReg = X86::RCX; break;
24858 case X86::BX: DestReg = X86::RBX; break;
24859 case X86::SI: DestReg = X86::RSI; break;
24860 case X86::DI: DestReg = X86::RDI; break;
24861 case X86::BP: DestReg = X86::RBP; break;
24862 case X86::SP: DestReg = X86::RSP; break;
24865 Res.first = DestReg;
24866 Res.second = &X86::GR64RegClass;
24869 } else if (Res.second == &X86::FR32RegClass ||
24870 Res.second == &X86::FR64RegClass ||
24871 Res.second == &X86::VR128RegClass ||
24872 Res.second == &X86::VR256RegClass ||
24873 Res.second == &X86::FR32XRegClass ||
24874 Res.second == &X86::FR64XRegClass ||
24875 Res.second == &X86::VR128XRegClass ||
24876 Res.second == &X86::VR256XRegClass ||
24877 Res.second == &X86::VR512RegClass) {
24878 // Handle references to XMM physical registers that got mapped into the
24879 // wrong class. This can happen with constraints like {xmm0} where the
24880 // target independent register mapper will just pick the first match it can
24881 // find, ignoring the required type.
24883 if (VT == MVT::f32 || VT == MVT::i32)
24884 Res.second = &X86::FR32RegClass;
24885 else if (VT == MVT::f64 || VT == MVT::i64)
24886 Res.second = &X86::FR64RegClass;
24887 else if (X86::VR128RegClass.hasType(VT))
24888 Res.second = &X86::VR128RegClass;
24889 else if (X86::VR256RegClass.hasType(VT))
24890 Res.second = &X86::VR256RegClass;
24891 else if (X86::VR512RegClass.hasType(VT))
24892 Res.second = &X86::VR512RegClass;
24898 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24900 // Scaling factors are not free at all.
24901 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24902 // will take 2 allocations in the out of order engine instead of 1
24903 // for plain addressing mode, i.e. inst (reg1).
24905 // vaddps (%rsi,%drx), %ymm0, %ymm1
24906 // Requires two allocations (one for the load, one for the computation)
24908 // vaddps (%rsi), %ymm0, %ymm1
24909 // Requires just 1 allocation, i.e., freeing allocations for other operations
24910 // and having less micro operations to execute.
24912 // For some X86 architectures, this is even worse because for instance for
24913 // stores, the complex addressing mode forces the instruction to use the
24914 // "load" ports instead of the dedicated "store" port.
24915 // E.g., on Haswell:
24916 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24917 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24918 if (isLegalAddressingMode(AM, Ty))
24919 // Scale represents reg2 * scale, thus account for 1
24920 // as soon as we use a second register.
24921 return AM.Scale != 0;
24925 bool X86TargetLowering::isTargetFTOL() const {
24926 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();