1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCExpr.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
53 STATISTIC(NumTailCalls, "Number of tail calls");
56 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
58 // Disable16Bit - 16-bit operations typically have a larger encoding than
59 // corresponding 32-bit instructions, and 16-bit code is slow on some
60 // processors. This is an experimental flag to disable 16-bit operations
61 // (which forces them to be Legalized to 32-bit operations).
63 Disable16Bit("disable-16bit", cl::Hidden,
64 cl::desc("Disable use of 16-bit instructions"));
66 // Forward declarations.
67 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
70 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
71 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
72 default: llvm_unreachable("unknown subtarget type");
73 case X86Subtarget::isDarwin:
74 if (TM.getSubtarget<X86Subtarget>().is64Bit())
75 return new X8664_MachoTargetObjectFile();
76 return new X8632_MachoTargetObjectFile();
77 case X86Subtarget::isELF:
78 return new TargetLoweringObjectFileELF();
79 case X86Subtarget::isMingw:
80 case X86Subtarget::isCygwin:
81 case X86Subtarget::isWindows:
82 return new TargetLoweringObjectFileCOFF();
87 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
88 : TargetLowering(TM, createTLOF(TM)) {
89 Subtarget = &TM.getSubtarget<X86Subtarget>();
90 X86ScalarSSEf64 = Subtarget->hasSSE2();
91 X86ScalarSSEf32 = Subtarget->hasSSE1();
92 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
94 RegInfo = TM.getRegisterInfo();
97 // Set up the TargetLowering object.
99 // X86 is weird, it always uses i8 for shift amounts and setcc results.
100 setShiftAmountType(MVT::i8);
101 setBooleanContents(ZeroOrOneBooleanContent);
102 setSchedulingPreference(SchedulingForRegPressure);
103 setStackPointerRegisterToSaveRestore(X86StackPtr);
105 if (Subtarget->isTargetDarwin()) {
106 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
107 setUseUnderscoreSetJmp(false);
108 setUseUnderscoreLongJmp(false);
109 } else if (Subtarget->isTargetMingw()) {
110 // MS runtime is weird: it exports _setjmp, but longjmp!
111 setUseUnderscoreSetJmp(true);
112 setUseUnderscoreLongJmp(false);
114 setUseUnderscoreSetJmp(true);
115 setUseUnderscoreLongJmp(true);
118 // Set up the register classes.
119 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
121 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
122 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
123 if (Subtarget->is64Bit())
124 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
126 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
128 // We don't accept any truncstore of integer registers.
129 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
131 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
132 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
134 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
135 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
136 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
138 // SETOEQ and SETUNE require checking two conditions.
139 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
140 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
141 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
142 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
143 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
144 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
146 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
148 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
149 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
150 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
152 if (Subtarget->is64Bit()) {
153 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
154 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
155 } else if (!UseSoftFloat) {
156 if (X86ScalarSSEf64) {
157 // We have an impenetrably clever algorithm for ui64->double only.
158 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
160 // We have an algorithm for SSE2, and we turn this into a 64-bit
161 // FILD for other targets.
162 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
165 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
167 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
171 // SSE has no i16 to fp conversion, only i32
172 if (X86ScalarSSEf32) {
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 // f32 and f64 cases are Legal, f80 case is not
175 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
177 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
185 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
186 // are Legal, f80 is custom lowered.
187 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
188 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
190 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
192 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
195 if (X86ScalarSSEf32) {
196 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
197 // f32 and f64 cases are Legal, f80 case is not
198 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
200 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
204 // Handle FP_TO_UINT by promoting the destination to a larger signed
206 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
207 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
208 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
210 if (Subtarget->is64Bit()) {
211 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
212 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
213 } else if (!UseSoftFloat) {
214 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
215 // Expand FP_TO_UINT into a select.
216 // FIXME: We would like to use a Custom expander here eventually to do
217 // the optimal thing for SSE vs. the default expansion in the legalizer.
218 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
220 // With SSE3 we can use fisttpll to convert to a signed i64; without
221 // SSE, we're stuck with a fistpll.
222 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
225 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
226 if (!X86ScalarSSEf64) {
227 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
228 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
231 // Scalar integer divide and remainder are lowered to use operations that
232 // produce two results, to match the available instructions. This exposes
233 // the two-result form to trivial CSE, which is able to combine x/y and x%y
234 // into a single instruction.
236 // Scalar integer multiply-high is also lowered to use two-result
237 // operations, to match the available instructions. However, plain multiply
238 // (low) operations are left as Legal, as there are single-result
239 // instructions for this in x86. Using the two-result multiply instructions
240 // when both high and low results are needed must be arranged by dagcombine.
241 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
242 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
243 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
244 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
245 setOperationAction(ISD::SREM , MVT::i8 , Expand);
246 setOperationAction(ISD::UREM , MVT::i8 , Expand);
247 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
248 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
249 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
250 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
251 setOperationAction(ISD::SREM , MVT::i16 , Expand);
252 setOperationAction(ISD::UREM , MVT::i16 , Expand);
253 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
254 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
255 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
256 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
257 setOperationAction(ISD::SREM , MVT::i32 , Expand);
258 setOperationAction(ISD::UREM , MVT::i32 , Expand);
259 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
260 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
261 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
262 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
263 setOperationAction(ISD::SREM , MVT::i64 , Expand);
264 setOperationAction(ISD::UREM , MVT::i64 , Expand);
266 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
267 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
268 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
269 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
270 if (Subtarget->is64Bit())
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
275 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
276 setOperationAction(ISD::FREM , MVT::f32 , Expand);
277 setOperationAction(ISD::FREM , MVT::f64 , Expand);
278 setOperationAction(ISD::FREM , MVT::f80 , Expand);
279 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
281 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
282 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
286 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
287 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
292 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
293 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
294 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
295 if (Subtarget->is64Bit()) {
296 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
297 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
298 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
301 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
302 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
304 // These should be promoted to a larger select which is supported.
305 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
306 // X86 wants to expand cmov itself.
307 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
309 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
311 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
312 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
313 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
314 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
315 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
316 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
318 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
320 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
321 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
322 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
323 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
324 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
325 if (Subtarget->is64Bit()) {
326 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
327 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
329 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
332 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
333 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
334 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
335 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
336 if (Subtarget->is64Bit())
337 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
338 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
339 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
340 if (Subtarget->is64Bit()) {
341 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
342 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
343 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
344 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
345 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
347 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
348 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
349 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
350 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
351 if (Subtarget->is64Bit()) {
352 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
353 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
354 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
357 if (Subtarget->hasSSE1())
358 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
360 if (!Subtarget->hasSSE2())
361 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
363 // Expand certain atomics
364 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
365 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
366 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
374 if (!Subtarget->is64Bit()) {
375 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
376 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
384 // FIXME - use subtarget debug flags
385 if (!Subtarget->isTargetDarwin() &&
386 !Subtarget->isTargetELF() &&
387 !Subtarget->isTargetCygMing()) {
388 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
391 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
392 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
393 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
394 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
395 if (Subtarget->is64Bit()) {
396 setExceptionPointerRegister(X86::RAX);
397 setExceptionSelectorRegister(X86::RDX);
399 setExceptionPointerRegister(X86::EAX);
400 setExceptionSelectorRegister(X86::EDX);
402 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
403 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
405 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
407 setOperationAction(ISD::TRAP, MVT::Other, Legal);
409 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
410 setOperationAction(ISD::VASTART , MVT::Other, Custom);
411 setOperationAction(ISD::VAEND , MVT::Other, Expand);
412 if (Subtarget->is64Bit()) {
413 setOperationAction(ISD::VAARG , MVT::Other, Custom);
414 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
416 setOperationAction(ISD::VAARG , MVT::Other, Expand);
417 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
420 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
421 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
422 if (Subtarget->is64Bit())
423 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
424 if (Subtarget->isTargetCygMing())
425 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
427 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
429 if (!UseSoftFloat && X86ScalarSSEf64) {
430 // f32 and f64 use SSE.
431 // Set up the FP register classes.
432 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
433 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
435 // Use ANDPD to simulate FABS.
436 setOperationAction(ISD::FABS , MVT::f64, Custom);
437 setOperationAction(ISD::FABS , MVT::f32, Custom);
439 // Use XORP to simulate FNEG.
440 setOperationAction(ISD::FNEG , MVT::f64, Custom);
441 setOperationAction(ISD::FNEG , MVT::f32, Custom);
443 // Use ANDPD and ORPD to simulate FCOPYSIGN.
444 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
445 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
447 // We don't support sin/cos/fmod
448 setOperationAction(ISD::FSIN , MVT::f64, Expand);
449 setOperationAction(ISD::FCOS , MVT::f64, Expand);
450 setOperationAction(ISD::FSIN , MVT::f32, Expand);
451 setOperationAction(ISD::FCOS , MVT::f32, Expand);
453 // Expand FP immediates into loads from the stack, except for the special
455 addLegalFPImmediate(APFloat(+0.0)); // xorpd
456 addLegalFPImmediate(APFloat(+0.0f)); // xorps
457 } else if (!UseSoftFloat && X86ScalarSSEf32) {
458 // Use SSE for f32, x87 for f64.
459 // Set up the FP register classes.
460 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
461 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
463 // Use ANDPS to simulate FABS.
464 setOperationAction(ISD::FABS , MVT::f32, Custom);
466 // Use XORP to simulate FNEG.
467 setOperationAction(ISD::FNEG , MVT::f32, Custom);
469 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
471 // Use ANDPS and ORPS to simulate FCOPYSIGN.
472 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
473 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
475 // We don't support sin/cos/fmod
476 setOperationAction(ISD::FSIN , MVT::f32, Expand);
477 setOperationAction(ISD::FCOS , MVT::f32, Expand);
479 // Special cases we handle for FP constants.
480 addLegalFPImmediate(APFloat(+0.0f)); // xorps
481 addLegalFPImmediate(APFloat(+0.0)); // FLD0
482 addLegalFPImmediate(APFloat(+1.0)); // FLD1
483 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
484 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
487 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
488 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
490 } else if (!UseSoftFloat) {
491 // f32 and f64 in x87.
492 // Set up the FP register classes.
493 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
494 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
496 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
497 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
498 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
499 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
502 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
503 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
505 addLegalFPImmediate(APFloat(+0.0)); // FLD0
506 addLegalFPImmediate(APFloat(+1.0)); // FLD1
507 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
508 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
509 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
510 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
511 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
512 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
515 // Long double always uses X87.
517 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
518 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
519 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
522 APFloat TmpFlt(+0.0);
523 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
525 addLegalFPImmediate(TmpFlt); // FLD0
527 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
528 APFloat TmpFlt2(+1.0);
529 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
531 addLegalFPImmediate(TmpFlt2); // FLD1
532 TmpFlt2.changeSign();
533 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
537 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
538 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
542 // Always use a library call for pow.
543 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
544 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
545 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
547 setOperationAction(ISD::FLOG, MVT::f80, Expand);
548 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
549 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
550 setOperationAction(ISD::FEXP, MVT::f80, Expand);
551 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
553 // First set operation action for all vector types to either promote
554 // (for widening) or expand (for scalarization). Then we will selectively
555 // turn on ones that can be effectively codegen'd.
556 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
557 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
558 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
573 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
574 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
607 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
608 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
610 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
611 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
612 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
613 setTruncStoreAction((MVT::SimpleValueType)VT,
614 (MVT::SimpleValueType)InnerVT, Expand);
615 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
616 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
617 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
620 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
621 // with -msoft-float, disable use of MMX as well.
622 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
623 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
624 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
625 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
626 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
627 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
629 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
630 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
631 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
632 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
634 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
635 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
636 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
637 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
639 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
640 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
642 setOperationAction(ISD::AND, MVT::v8i8, Promote);
643 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
644 setOperationAction(ISD::AND, MVT::v4i16, Promote);
645 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
646 setOperationAction(ISD::AND, MVT::v2i32, Promote);
647 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
648 setOperationAction(ISD::AND, MVT::v1i64, Legal);
650 setOperationAction(ISD::OR, MVT::v8i8, Promote);
651 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
652 setOperationAction(ISD::OR, MVT::v4i16, Promote);
653 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
654 setOperationAction(ISD::OR, MVT::v2i32, Promote);
655 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
656 setOperationAction(ISD::OR, MVT::v1i64, Legal);
658 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
659 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
660 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
661 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
662 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
663 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
664 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
666 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
667 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
668 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
669 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
670 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
671 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
672 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
673 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
674 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
676 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
679 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
680 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
682 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
687 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
688 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
689 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
692 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
694 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
695 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
696 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
697 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
698 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
699 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
700 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
703 if (!UseSoftFloat && Subtarget->hasSSE1()) {
704 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
706 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
707 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
708 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
709 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
710 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
711 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
712 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
713 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
714 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
715 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
716 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
717 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
720 if (!UseSoftFloat && Subtarget->hasSSE2()) {
721 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
723 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
724 // registers cannot be used even for integer operations.
725 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
726 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
727 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
728 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
730 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
731 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
732 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
733 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
734 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
735 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
736 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
737 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
738 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
739 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
740 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
741 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
742 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
743 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
744 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
745 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
747 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
748 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
749 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
754 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
764 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
765 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
766 EVT VT = (MVT::SimpleValueType)i;
767 // Do not attempt to custom lower non-power-of-2 vectors
768 if (!isPowerOf2_32(VT.getVectorNumElements()))
770 // Do not attempt to custom lower non-128-bit vectors
771 if (!VT.is128BitVector())
773 setOperationAction(ISD::BUILD_VECTOR,
774 VT.getSimpleVT().SimpleTy, Custom);
775 setOperationAction(ISD::VECTOR_SHUFFLE,
776 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
778 VT.getSimpleVT().SimpleTy, Custom);
781 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
782 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
783 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
788 if (Subtarget->is64Bit()) {
789 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
790 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
793 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
794 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
795 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
798 // Do not attempt to promote non-128-bit vectors
799 if (!VT.is128BitVector()) {
802 setOperationAction(ISD::AND, SVT, Promote);
803 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
804 setOperationAction(ISD::OR, SVT, Promote);
805 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
806 setOperationAction(ISD::XOR, SVT, Promote);
807 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
808 setOperationAction(ISD::LOAD, SVT, Promote);
809 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
810 setOperationAction(ISD::SELECT, SVT, Promote);
811 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
814 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
816 // Custom lower v2i64 and v2f64 selects.
817 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
818 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
819 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
820 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
822 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
823 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
824 if (!DisableMMX && Subtarget->hasMMX()) {
825 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
826 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
830 if (Subtarget->hasSSE41()) {
831 // FIXME: Do we need to handle scalar-to-vector here?
832 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
834 // i8 and i16 vectors are custom , because the source register and source
835 // source memory operand types are not the same width. f32 vectors are
836 // custom since the immediate controlling the insert encodes additional
838 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
844 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
845 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
848 if (Subtarget->is64Bit()) {
849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
854 if (Subtarget->hasSSE42()) {
855 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
858 if (!UseSoftFloat && Subtarget->hasAVX()) {
859 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
860 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
861 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
862 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
864 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
865 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
866 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
867 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
868 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
869 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
870 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
871 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
872 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
873 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
874 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
875 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
876 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
877 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
878 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
880 // Operations to consider commented out -v16i16 v32i8
881 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
882 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
883 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
884 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
885 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
886 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
887 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
888 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
889 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
890 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
891 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
892 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
893 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
894 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
896 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
897 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
898 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
899 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
901 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
902 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
903 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
905 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
907 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
908 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
909 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
910 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
912 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
915 // Not sure we want to do this since there are no 256-bit integer
918 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
919 // This includes 256-bit vectors
920 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
921 EVT VT = (MVT::SimpleValueType)i;
923 // Do not attempt to custom lower non-power-of-2 vectors
924 if (!isPowerOf2_32(VT.getVectorNumElements()))
927 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
928 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
929 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
932 if (Subtarget->is64Bit()) {
933 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
934 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
939 // Not sure we want to do this since there are no 256-bit integer
942 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
943 // Including 256-bit vectors
944 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
945 EVT VT = (MVT::SimpleValueType)i;
947 if (!VT.is256BitVector()) {
950 setOperationAction(ISD::AND, VT, Promote);
951 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
952 setOperationAction(ISD::OR, VT, Promote);
953 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
954 setOperationAction(ISD::XOR, VT, Promote);
955 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
956 setOperationAction(ISD::LOAD, VT, Promote);
957 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
958 setOperationAction(ISD::SELECT, VT, Promote);
959 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
962 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
966 // We want to custom lower some of our intrinsics.
967 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
969 // Add/Sub/Mul with overflow operations are custom lowered.
970 setOperationAction(ISD::SADDO, MVT::i32, Custom);
971 setOperationAction(ISD::SADDO, MVT::i64, Custom);
972 setOperationAction(ISD::UADDO, MVT::i32, Custom);
973 setOperationAction(ISD::UADDO, MVT::i64, Custom);
974 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
975 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
976 setOperationAction(ISD::USUBO, MVT::i32, Custom);
977 setOperationAction(ISD::USUBO, MVT::i64, Custom);
978 setOperationAction(ISD::SMULO, MVT::i32, Custom);
979 setOperationAction(ISD::SMULO, MVT::i64, Custom);
981 if (!Subtarget->is64Bit()) {
982 // These libcalls are not available in 32-bit.
983 setLibcallName(RTLIB::SHL_I128, 0);
984 setLibcallName(RTLIB::SRL_I128, 0);
985 setLibcallName(RTLIB::SRA_I128, 0);
988 // We have target-specific dag combine patterns for the following nodes:
989 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
990 setTargetDAGCombine(ISD::BUILD_VECTOR);
991 setTargetDAGCombine(ISD::SELECT);
992 setTargetDAGCombine(ISD::SHL);
993 setTargetDAGCombine(ISD::SRA);
994 setTargetDAGCombine(ISD::SRL);
995 setTargetDAGCombine(ISD::OR);
996 setTargetDAGCombine(ISD::STORE);
997 setTargetDAGCombine(ISD::MEMBARRIER);
998 setTargetDAGCombine(ISD::ZERO_EXTEND);
999 if (Subtarget->is64Bit())
1000 setTargetDAGCombine(ISD::MUL);
1002 computeRegisterProperties();
1004 // Divide and reminder operations have no vector equivalent and can
1005 // trap. Do a custom widening for these operations in which we never
1006 // generate more divides/remainder than the original vector width.
1007 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1008 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
1009 if (!isTypeLegal((MVT::SimpleValueType)VT)) {
1010 setOperationAction(ISD::SDIV, (MVT::SimpleValueType) VT, Custom);
1011 setOperationAction(ISD::UDIV, (MVT::SimpleValueType) VT, Custom);
1012 setOperationAction(ISD::SREM, (MVT::SimpleValueType) VT, Custom);
1013 setOperationAction(ISD::UREM, (MVT::SimpleValueType) VT, Custom);
1017 // FIXME: These should be based on subtarget info. Plus, the values should
1018 // be smaller when we are in optimizing for size mode.
1019 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1020 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1021 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1022 setPrefLoopAlignment(16);
1023 benefitFromCodePlacementOpt = true;
1027 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1032 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1033 /// the desired ByVal argument alignment.
1034 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1037 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1038 if (VTy->getBitWidth() == 128)
1040 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1041 unsigned EltAlign = 0;
1042 getMaxByValAlign(ATy->getElementType(), EltAlign);
1043 if (EltAlign > MaxAlign)
1044 MaxAlign = EltAlign;
1045 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1046 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1047 unsigned EltAlign = 0;
1048 getMaxByValAlign(STy->getElementType(i), EltAlign);
1049 if (EltAlign > MaxAlign)
1050 MaxAlign = EltAlign;
1058 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1059 /// function arguments in the caller parameter area. For X86, aggregates
1060 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1061 /// are at 4-byte boundaries.
1062 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1063 if (Subtarget->is64Bit()) {
1064 // Max of 8 and alignment of type.
1065 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1072 if (Subtarget->hasSSE1())
1073 getMaxByValAlign(Ty, Align);
1077 /// getOptimalMemOpType - Returns the target specific optimal type for load
1078 /// and store operations as a result of memset, memcpy, and memmove
1079 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1082 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1083 bool isSrcConst, bool isSrcStr,
1084 SelectionDAG &DAG) const {
1085 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1086 // linux. This is because the stack realignment code can't handle certain
1087 // cases like PR2962. This should be removed when PR2962 is fixed.
1088 const Function *F = DAG.getMachineFunction().getFunction();
1089 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1090 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1091 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1093 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1096 if (Subtarget->is64Bit() && Size >= 8)
1101 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1102 /// current function. The returned value is a member of the
1103 /// MachineJumpTableInfo::JTEntryKind enum.
1104 unsigned X86TargetLowering::getJumpTableEncoding() const {
1105 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1107 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1108 Subtarget->isPICStyleGOT())
1109 return MachineJumpTableInfo::EK_Custom32;
1111 // Otherwise, use the normal jump table encoding heuristics.
1112 return TargetLowering::getJumpTableEncoding();
1115 /// getPICBaseSymbol - Return the X86-32 PIC base.
1117 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1118 MCContext &Ctx) const {
1119 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1120 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1121 Twine(MF->getFunctionNumber())+"$pb");
1126 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1127 const MachineBasicBlock *MBB,
1128 unsigned uid,MCContext &Ctx) const{
1129 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1130 Subtarget->isPICStyleGOT());
1131 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1134 // FIXME: @GOTOFF should be a property of MCSymbolRefExpr not in the MCSymbol.
1135 std::string Name = MBB->getSymbol(Ctx)->getName() + "@GOTOFF";
1136 return MCSymbolRefExpr::Create(Ctx.GetOrCreateSymbol(StringRef(Name)), Ctx);
1139 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1141 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1142 SelectionDAG &DAG) const {
1143 if (!Subtarget->is64Bit())
1144 // This doesn't have DebugLoc associated with it, but is not really the
1145 // same as a Register.
1146 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1151 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1152 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1154 const MCExpr *X86TargetLowering::
1155 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1156 MCContext &Ctx) const {
1157 // X86-64 uses RIP relative addressing based on the jump table label.
1158 if (Subtarget->isPICStyleRIPRel())
1159 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1161 // Otherwise, the reference is relative to the PIC base.
1162 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1165 /// getFunctionAlignment - Return the Log2 alignment of this function.
1166 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1167 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1170 //===----------------------------------------------------------------------===//
1171 // Return Value Calling Convention Implementation
1172 //===----------------------------------------------------------------------===//
1174 #include "X86GenCallingConv.inc"
1177 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1178 const SmallVectorImpl<EVT> &OutTys,
1179 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1180 SelectionDAG &DAG) {
1181 SmallVector<CCValAssign, 16> RVLocs;
1182 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1183 RVLocs, *DAG.getContext());
1184 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1188 X86TargetLowering::LowerReturn(SDValue Chain,
1189 CallingConv::ID CallConv, bool isVarArg,
1190 const SmallVectorImpl<ISD::OutputArg> &Outs,
1191 DebugLoc dl, SelectionDAG &DAG) {
1193 SmallVector<CCValAssign, 16> RVLocs;
1194 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1195 RVLocs, *DAG.getContext());
1196 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1198 // Add the regs to the liveout set for the function.
1199 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1200 for (unsigned i = 0; i != RVLocs.size(); ++i)
1201 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1202 MRI.addLiveOut(RVLocs[i].getLocReg());
1206 SmallVector<SDValue, 6> RetOps;
1207 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1208 // Operand #1 = Bytes To Pop
1209 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1211 // Copy the result values into the output registers.
1212 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1213 CCValAssign &VA = RVLocs[i];
1214 assert(VA.isRegLoc() && "Can only return in registers!");
1215 SDValue ValToCopy = Outs[i].Val;
1217 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1218 // the RET instruction and handled by the FP Stackifier.
1219 if (VA.getLocReg() == X86::ST0 ||
1220 VA.getLocReg() == X86::ST1) {
1221 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1222 // change the value to the FP stack register class.
1223 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1224 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1225 RetOps.push_back(ValToCopy);
1226 // Don't emit a copytoreg.
1230 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1231 // which is returned in RAX / RDX.
1232 if (Subtarget->is64Bit()) {
1233 EVT ValVT = ValToCopy.getValueType();
1234 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1235 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1236 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1237 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1241 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1242 Flag = Chain.getValue(1);
1245 // The x86-64 ABI for returning structs by value requires that we copy
1246 // the sret argument into %rax for the return. We saved the argument into
1247 // a virtual register in the entry block, so now we copy the value out
1249 if (Subtarget->is64Bit() &&
1250 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1251 MachineFunction &MF = DAG.getMachineFunction();
1252 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1253 unsigned Reg = FuncInfo->getSRetReturnReg();
1255 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64));
1256 FuncInfo->setSRetReturnReg(Reg);
1258 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1260 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1261 Flag = Chain.getValue(1);
1263 // RAX now acts like a return value.
1264 MRI.addLiveOut(X86::RAX);
1267 RetOps[0] = Chain; // Update chain.
1269 // Add the flag if we have it.
1271 RetOps.push_back(Flag);
1273 return DAG.getNode(X86ISD::RET_FLAG, dl,
1274 MVT::Other, &RetOps[0], RetOps.size());
1277 /// LowerCallResult - Lower the result values of a call into the
1278 /// appropriate copies out of appropriate physical registers.
1281 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1282 CallingConv::ID CallConv, bool isVarArg,
1283 const SmallVectorImpl<ISD::InputArg> &Ins,
1284 DebugLoc dl, SelectionDAG &DAG,
1285 SmallVectorImpl<SDValue> &InVals) {
1287 // Assign locations to each value returned by this call.
1288 SmallVector<CCValAssign, 16> RVLocs;
1289 bool Is64Bit = Subtarget->is64Bit();
1290 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1291 RVLocs, *DAG.getContext());
1292 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1294 // Copy all of the result registers out of their specified physreg.
1295 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1296 CCValAssign &VA = RVLocs[i];
1297 EVT CopyVT = VA.getValVT();
1299 // If this is x86-64, and we disabled SSE, we can't return FP values
1300 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1301 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1302 llvm_report_error("SSE register return with SSE disabled");
1305 // If this is a call to a function that returns an fp value on the floating
1306 // point stack, but where we prefer to use the value in xmm registers, copy
1307 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1308 if ((VA.getLocReg() == X86::ST0 ||
1309 VA.getLocReg() == X86::ST1) &&
1310 isScalarFPTypeInSSEReg(VA.getValVT())) {
1315 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1316 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1317 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1318 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1319 MVT::v2i64, InFlag).getValue(1);
1320 Val = Chain.getValue(0);
1321 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1322 Val, DAG.getConstant(0, MVT::i64));
1324 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1325 MVT::i64, InFlag).getValue(1);
1326 Val = Chain.getValue(0);
1328 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1330 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1331 CopyVT, InFlag).getValue(1);
1332 Val = Chain.getValue(0);
1334 InFlag = Chain.getValue(2);
1336 if (CopyVT != VA.getValVT()) {
1337 // Round the F80 the right size, which also moves to the appropriate xmm
1339 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1340 // This truncation won't change the value.
1341 DAG.getIntPtrConstant(1));
1344 InVals.push_back(Val);
1351 //===----------------------------------------------------------------------===//
1352 // C & StdCall & Fast Calling Convention implementation
1353 //===----------------------------------------------------------------------===//
1354 // StdCall calling convention seems to be standard for many Windows' API
1355 // routines and around. It differs from C calling convention just a little:
1356 // callee should clean up the stack, not caller. Symbols should be also
1357 // decorated in some fancy way :) It doesn't support any vector arguments.
1358 // For info on fast calling convention see Fast Calling Convention (tail call)
1359 // implementation LowerX86_32FastCCCallTo.
1361 /// CallIsStructReturn - Determines whether a call uses struct return
1363 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1367 return Outs[0].Flags.isSRet();
1370 /// ArgsAreStructReturn - Determines whether a function uses struct
1371 /// return semantics.
1373 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1377 return Ins[0].Flags.isSRet();
1380 /// IsCalleePop - Determines whether the callee is required to pop its
1381 /// own arguments. Callee pop is necessary to support tail calls.
1382 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1386 switch (CallingConv) {
1389 case CallingConv::X86_StdCall:
1390 return !Subtarget->is64Bit();
1391 case CallingConv::X86_FastCall:
1392 return !Subtarget->is64Bit();
1393 case CallingConv::Fast:
1394 return PerformTailCallOpt;
1398 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1399 /// given CallingConvention value.
1400 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1401 if (Subtarget->is64Bit()) {
1402 if (Subtarget->isTargetWin64())
1403 return CC_X86_Win64_C;
1408 if (CC == CallingConv::X86_FastCall)
1409 return CC_X86_32_FastCall;
1410 else if (CC == CallingConv::Fast)
1411 return CC_X86_32_FastCC;
1416 /// NameDecorationForCallConv - Selects the appropriate decoration to
1417 /// apply to a MachineFunction containing a given calling convention.
1419 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1420 if (CallConv == CallingConv::X86_FastCall)
1422 else if (CallConv == CallingConv::X86_StdCall)
1428 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1429 /// by "Src" to address "Dst" with size and alignment information specified by
1430 /// the specific parameter attribute. The copy will be passed as a byval
1431 /// function parameter.
1433 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1434 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1436 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1437 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1438 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1441 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1442 /// a tailcall target by changing its ABI.
1443 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1444 return PerformTailCallOpt && CC == CallingConv::Fast;
1448 X86TargetLowering::LowerMemArgument(SDValue Chain,
1449 CallingConv::ID CallConv,
1450 const SmallVectorImpl<ISD::InputArg> &Ins,
1451 DebugLoc dl, SelectionDAG &DAG,
1452 const CCValAssign &VA,
1453 MachineFrameInfo *MFI,
1455 // Create the nodes corresponding to a load from this parameter slot.
1456 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1457 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1458 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1461 // If value is passed by pointer we have address passed instead of the value
1463 if (VA.getLocInfo() == CCValAssign::Indirect)
1464 ValVT = VA.getLocVT();
1466 ValVT = VA.getValVT();
1468 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1469 // changed with more analysis.
1470 // In case of tail call optimization mark all arguments mutable. Since they
1471 // could be overwritten by lowering of arguments in case of a tail call.
1472 if (Flags.isByVal()) {
1473 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1474 VA.getLocMemOffset(), isImmutable, false);
1475 return DAG.getFrameIndex(FI, getPointerTy());
1477 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1478 VA.getLocMemOffset(), isImmutable, false);
1479 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1480 return DAG.getLoad(ValVT, dl, Chain, FIN,
1481 PseudoSourceValue::getFixedStack(FI), 0);
1486 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1487 CallingConv::ID CallConv,
1489 const SmallVectorImpl<ISD::InputArg> &Ins,
1492 SmallVectorImpl<SDValue> &InVals) {
1494 MachineFunction &MF = DAG.getMachineFunction();
1495 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1497 const Function* Fn = MF.getFunction();
1498 if (Fn->hasExternalLinkage() &&
1499 Subtarget->isTargetCygMing() &&
1500 Fn->getName() == "main")
1501 FuncInfo->setForceFramePointer(true);
1503 // Decorate the function name.
1504 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1506 MachineFrameInfo *MFI = MF.getFrameInfo();
1507 bool Is64Bit = Subtarget->is64Bit();
1508 bool IsWin64 = Subtarget->isTargetWin64();
1510 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1511 "Var args not supported with calling convention fastcc");
1513 // Assign locations to all of the incoming arguments.
1514 SmallVector<CCValAssign, 16> ArgLocs;
1515 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1516 ArgLocs, *DAG.getContext());
1517 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1519 unsigned LastVal = ~0U;
1521 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1522 CCValAssign &VA = ArgLocs[i];
1523 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1525 assert(VA.getValNo() != LastVal &&
1526 "Don't support value assigned to multiple locs yet");
1527 LastVal = VA.getValNo();
1529 if (VA.isRegLoc()) {
1530 EVT RegVT = VA.getLocVT();
1531 TargetRegisterClass *RC = NULL;
1532 if (RegVT == MVT::i32)
1533 RC = X86::GR32RegisterClass;
1534 else if (Is64Bit && RegVT == MVT::i64)
1535 RC = X86::GR64RegisterClass;
1536 else if (RegVT == MVT::f32)
1537 RC = X86::FR32RegisterClass;
1538 else if (RegVT == MVT::f64)
1539 RC = X86::FR64RegisterClass;
1540 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1541 RC = X86::VR128RegisterClass;
1542 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1543 RC = X86::VR64RegisterClass;
1545 llvm_unreachable("Unknown argument type!");
1547 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1548 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1550 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1551 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1553 if (VA.getLocInfo() == CCValAssign::SExt)
1554 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1555 DAG.getValueType(VA.getValVT()));
1556 else if (VA.getLocInfo() == CCValAssign::ZExt)
1557 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1558 DAG.getValueType(VA.getValVT()));
1559 else if (VA.getLocInfo() == CCValAssign::BCvt)
1560 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1562 if (VA.isExtInLoc()) {
1563 // Handle MMX values passed in XMM regs.
1564 if (RegVT.isVector()) {
1565 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1566 ArgValue, DAG.getConstant(0, MVT::i64));
1567 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1569 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1572 assert(VA.isMemLoc());
1573 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1576 // If value is passed via pointer - do a load.
1577 if (VA.getLocInfo() == CCValAssign::Indirect)
1578 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1580 InVals.push_back(ArgValue);
1583 // The x86-64 ABI for returning structs by value requires that we copy
1584 // the sret argument into %rax for the return. Save the argument into
1585 // a virtual register so that we can access it from the return points.
1586 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1587 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1588 unsigned Reg = FuncInfo->getSRetReturnReg();
1590 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1591 FuncInfo->setSRetReturnReg(Reg);
1593 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1594 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1597 unsigned StackSize = CCInfo.getNextStackOffset();
1598 // Align stack specially for tail calls.
1599 if (FuncIsMadeTailCallSafe(CallConv))
1600 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1602 // If the function takes variable number of arguments, make a frame index for
1603 // the start of the first vararg value... for expansion of llvm.va_start.
1605 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1606 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1609 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1611 // FIXME: We should really autogenerate these arrays
1612 static const unsigned GPR64ArgRegsWin64[] = {
1613 X86::RCX, X86::RDX, X86::R8, X86::R9
1615 static const unsigned XMMArgRegsWin64[] = {
1616 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1618 static const unsigned GPR64ArgRegs64Bit[] = {
1619 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1621 static const unsigned XMMArgRegs64Bit[] = {
1622 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1623 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1625 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1628 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1629 GPR64ArgRegs = GPR64ArgRegsWin64;
1630 XMMArgRegs = XMMArgRegsWin64;
1632 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1633 GPR64ArgRegs = GPR64ArgRegs64Bit;
1634 XMMArgRegs = XMMArgRegs64Bit;
1636 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1638 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1641 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1642 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1643 "SSE register cannot be used when SSE is disabled!");
1644 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1645 "SSE register cannot be used when SSE is disabled!");
1646 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1647 // Kernel mode asks for SSE to be disabled, so don't push them
1649 TotalNumXMMRegs = 0;
1651 // For X86-64, if there are vararg parameters that are passed via
1652 // registers, then we must store them to their spots on the stack so they
1653 // may be loaded by deferencing the result of va_next.
1654 VarArgsGPOffset = NumIntRegs * 8;
1655 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1656 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1657 TotalNumXMMRegs * 16, 16,
1660 // Store the integer parameter registers.
1661 SmallVector<SDValue, 8> MemOps;
1662 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1663 unsigned Offset = VarArgsGPOffset;
1664 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1665 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1666 DAG.getIntPtrConstant(Offset));
1667 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1668 X86::GR64RegisterClass);
1669 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1671 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1672 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1674 MemOps.push_back(Store);
1678 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1679 // Now store the XMM (fp + vector) parameter registers.
1680 SmallVector<SDValue, 11> SaveXMMOps;
1681 SaveXMMOps.push_back(Chain);
1683 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1684 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1685 SaveXMMOps.push_back(ALVal);
1687 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1688 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1690 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1691 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1692 X86::VR128RegisterClass);
1693 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1694 SaveXMMOps.push_back(Val);
1696 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1698 &SaveXMMOps[0], SaveXMMOps.size()));
1701 if (!MemOps.empty())
1702 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1703 &MemOps[0], MemOps.size());
1707 // Some CCs need callee pop.
1708 if (IsCalleePop(isVarArg, CallConv)) {
1709 BytesToPopOnReturn = StackSize; // Callee pops everything.
1711 BytesToPopOnReturn = 0; // Callee pops nothing.
1712 // If this is an sret function, the return should pop the hidden pointer.
1713 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1714 BytesToPopOnReturn = 4;
1718 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1719 if (CallConv == CallingConv::X86_FastCall)
1720 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1723 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1729 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1730 SDValue StackPtr, SDValue Arg,
1731 DebugLoc dl, SelectionDAG &DAG,
1732 const CCValAssign &VA,
1733 ISD::ArgFlagsTy Flags) {
1734 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1735 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1736 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1737 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1738 if (Flags.isByVal()) {
1739 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1741 return DAG.getStore(Chain, dl, Arg, PtrOff,
1742 PseudoSourceValue::getStack(), LocMemOffset);
1745 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1746 /// optimization is performed and it is required.
1748 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1749 SDValue &OutRetAddr, SDValue Chain,
1750 bool IsTailCall, bool Is64Bit,
1751 int FPDiff, DebugLoc dl) {
1752 if (!IsTailCall || FPDiff==0) return Chain;
1754 // Adjust the Return address stack slot.
1755 EVT VT = getPointerTy();
1756 OutRetAddr = getReturnAddressFrameIndex(DAG);
1758 // Load the "old" Return address.
1759 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1760 return SDValue(OutRetAddr.getNode(), 1);
1763 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1764 /// optimization is performed and it is required (FPDiff!=0).
1766 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1767 SDValue Chain, SDValue RetAddrFrIdx,
1768 bool Is64Bit, int FPDiff, DebugLoc dl) {
1769 // Store the return address to the appropriate stack slot.
1770 if (!FPDiff) return Chain;
1771 // Calculate the new stack slot for the return address.
1772 int SlotSize = Is64Bit ? 8 : 4;
1773 int NewReturnAddrFI =
1774 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, true,false);
1775 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1776 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1777 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1778 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1783 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1784 CallingConv::ID CallConv, bool isVarArg,
1786 const SmallVectorImpl<ISD::OutputArg> &Outs,
1787 const SmallVectorImpl<ISD::InputArg> &Ins,
1788 DebugLoc dl, SelectionDAG &DAG,
1789 SmallVectorImpl<SDValue> &InVals) {
1790 MachineFunction &MF = DAG.getMachineFunction();
1791 bool Is64Bit = Subtarget->is64Bit();
1792 bool IsStructRet = CallIsStructReturn(Outs);
1793 bool IsSibcall = false;
1796 // Check if it's really possible to do a tail call.
1797 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
1799 if (!PerformTailCallOpt && isTailCall)
1803 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1804 "Var args not supported with calling convention fastcc");
1806 // Analyze operands of the call, assigning locations to each operand.
1807 SmallVector<CCValAssign, 16> ArgLocs;
1808 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1809 ArgLocs, *DAG.getContext());
1810 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1812 // Get a count of how many bytes are to be pushed on the stack.
1813 unsigned NumBytes = CCInfo.getNextStackOffset();
1814 if (FuncIsMadeTailCallSafe(CallConv))
1815 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1817 // This is a sibcall. The memory operands are available in caller's
1818 // own caller's stack.
1825 // Lower arguments at fp - stackoffset + fpdiff.
1826 unsigned NumBytesCallerPushed =
1827 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1828 FPDiff = NumBytesCallerPushed - NumBytes;
1830 // Set the delta of movement of the returnaddr stackslot.
1831 // But only set if delta is greater than previous delta.
1832 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1833 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1836 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1838 SDValue RetAddrFrIdx;
1839 // Load return adress for tail calls.
1840 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1843 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1844 SmallVector<SDValue, 8> MemOpChains;
1847 // Walk the register/memloc assignments, inserting copies/loads. In the case
1848 // of tail call optimization arguments are handle later.
1849 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1850 CCValAssign &VA = ArgLocs[i];
1851 EVT RegVT = VA.getLocVT();
1852 SDValue Arg = Outs[i].Val;
1853 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1854 bool isByVal = Flags.isByVal();
1856 // Promote the value if needed.
1857 switch (VA.getLocInfo()) {
1858 default: llvm_unreachable("Unknown loc info!");
1859 case CCValAssign::Full: break;
1860 case CCValAssign::SExt:
1861 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1863 case CCValAssign::ZExt:
1864 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1866 case CCValAssign::AExt:
1867 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1868 // Special case: passing MMX values in XMM registers.
1869 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1870 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1871 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1873 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1875 case CCValAssign::BCvt:
1876 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1878 case CCValAssign::Indirect: {
1879 // Store the argument.
1880 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1881 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1882 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1883 PseudoSourceValue::getFixedStack(FI), 0);
1889 if (VA.isRegLoc()) {
1890 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1891 } else if ((!isTailCall || isByVal) && !IsSibcall) {
1892 assert(VA.isMemLoc());
1893 if (StackPtr.getNode() == 0)
1894 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1895 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1896 dl, DAG, VA, Flags));
1900 if (!MemOpChains.empty())
1901 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1902 &MemOpChains[0], MemOpChains.size());
1904 // Build a sequence of copy-to-reg nodes chained together with token chain
1905 // and flag operands which copy the outgoing args into registers.
1907 // Tail call byval lowering might overwrite argument registers so in case of
1908 // tail call optimization the copies to registers are lowered later.
1910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1911 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1912 RegsToPass[i].second, InFlag);
1913 InFlag = Chain.getValue(1);
1917 if (Subtarget->isPICStyleGOT()) {
1918 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1921 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1922 DAG.getNode(X86ISD::GlobalBaseReg,
1923 DebugLoc::getUnknownLoc(),
1926 InFlag = Chain.getValue(1);
1928 // If we are tail calling and generating PIC/GOT style code load the
1929 // address of the callee into ECX. The value in ecx is used as target of
1930 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1931 // for tail calls on PIC/GOT architectures. Normally we would just put the
1932 // address of GOT into ebx and then call target@PLT. But for tail calls
1933 // ebx would be restored (since ebx is callee saved) before jumping to the
1936 // Note: The actual moving to ECX is done further down.
1937 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1938 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1939 !G->getGlobal()->hasProtectedVisibility())
1940 Callee = LowerGlobalAddress(Callee, DAG);
1941 else if (isa<ExternalSymbolSDNode>(Callee))
1942 Callee = LowerExternalSymbol(Callee, DAG);
1946 if (Is64Bit && isVarArg) {
1947 // From AMD64 ABI document:
1948 // For calls that may call functions that use varargs or stdargs
1949 // (prototype-less calls or calls to functions containing ellipsis (...) in
1950 // the declaration) %al is used as hidden argument to specify the number
1951 // of SSE registers used. The contents of %al do not need to match exactly
1952 // the number of registers, but must be an ubound on the number of SSE
1953 // registers used and is in the range 0 - 8 inclusive.
1955 // FIXME: Verify this on Win64
1956 // Count the number of XMM registers allocated.
1957 static const unsigned XMMArgRegs[] = {
1958 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1959 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1961 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1962 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1963 && "SSE registers cannot be used when SSE is disabled");
1965 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1966 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1967 InFlag = Chain.getValue(1);
1971 // For tail calls lower the arguments to the 'real' stack slot.
1973 // Force all the incoming stack arguments to be loaded from the stack
1974 // before any new outgoing arguments are stored to the stack, because the
1975 // outgoing stack slots may alias the incoming argument stack slots, and
1976 // the alias isn't otherwise explicit. This is slightly more conservative
1977 // than necessary, because it means that each store effectively depends
1978 // on every argument instead of just those arguments it would clobber.
1979 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1981 SmallVector<SDValue, 8> MemOpChains2;
1984 // Do not flag preceeding copytoreg stuff together with the following stuff.
1986 if (PerformTailCallOpt) {
1987 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1988 CCValAssign &VA = ArgLocs[i];
1991 assert(VA.isMemLoc());
1992 SDValue Arg = Outs[i].Val;
1993 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1994 // Create frame index.
1995 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1996 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1997 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1998 FIN = DAG.getFrameIndex(FI, getPointerTy());
2000 if (Flags.isByVal()) {
2001 // Copy relative to framepointer.
2002 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2003 if (StackPtr.getNode() == 0)
2004 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2006 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2008 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2012 // Store relative to framepointer.
2013 MemOpChains2.push_back(
2014 DAG.getStore(ArgChain, dl, Arg, FIN,
2015 PseudoSourceValue::getFixedStack(FI), 0));
2020 if (!MemOpChains2.empty())
2021 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2022 &MemOpChains2[0], MemOpChains2.size());
2024 // Copy arguments to their registers.
2025 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2026 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2027 RegsToPass[i].second, InFlag);
2028 InFlag = Chain.getValue(1);
2032 // Store the return address to the appropriate stack slot.
2033 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2037 bool WasGlobalOrExternal = false;
2038 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2039 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2040 // In the 64-bit large code model, we have to make all calls
2041 // through a register, since the call instruction's 32-bit
2042 // pc-relative offset may not be large enough to hold the whole
2044 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2045 WasGlobalOrExternal = true;
2046 // If the callee is a GlobalAddress node (quite common, every direct call
2047 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2050 // We should use extra load for direct calls to dllimported functions in
2052 GlobalValue *GV = G->getGlobal();
2053 if (!GV->hasDLLImportLinkage()) {
2054 unsigned char OpFlags = 0;
2056 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2057 // external symbols most go through the PLT in PIC mode. If the symbol
2058 // has hidden or protected visibility, or if it is static or local, then
2059 // we don't need to use the PLT - we can directly call it.
2060 if (Subtarget->isTargetELF() &&
2061 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2062 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2063 OpFlags = X86II::MO_PLT;
2064 } else if (Subtarget->isPICStyleStubAny() &&
2065 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2066 Subtarget->getDarwinVers() < 9) {
2067 // PC-relative references to external symbols should go through $stub,
2068 // unless we're building with the leopard linker or later, which
2069 // automatically synthesizes these stubs.
2070 OpFlags = X86II::MO_DARWIN_STUB;
2073 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2074 G->getOffset(), OpFlags);
2076 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2077 WasGlobalOrExternal = true;
2078 unsigned char OpFlags = 0;
2080 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2081 // symbols should go through the PLT.
2082 if (Subtarget->isTargetELF() &&
2083 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2084 OpFlags = X86II::MO_PLT;
2085 } else if (Subtarget->isPICStyleStubAny() &&
2086 Subtarget->getDarwinVers() < 9) {
2087 // PC-relative references to external symbols should go through $stub,
2088 // unless we're building with the leopard linker or later, which
2089 // automatically synthesizes these stubs.
2090 OpFlags = X86II::MO_DARWIN_STUB;
2093 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2097 if (isTailCall && !WasGlobalOrExternal) {
2098 // Force the address into a (call preserved) caller-saved register since
2099 // tailcall must happen after callee-saved registers are poped.
2100 // FIXME: Give it a special register class that contains caller-saved
2101 // register instead?
2102 unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl,
2104 DAG.getRegister(TCReg, getPointerTy()),
2106 Callee = DAG.getRegister(TCReg, getPointerTy());
2109 // Returns a chain & a flag for retval copy to use.
2110 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2111 SmallVector<SDValue, 8> Ops;
2114 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2115 DAG.getIntPtrConstant(0, true), InFlag);
2116 InFlag = Chain.getValue(1);
2119 Ops.push_back(Chain);
2120 Ops.push_back(Callee);
2123 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2125 // Add argument registers to the end of the list so that they are known live
2127 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2128 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2129 RegsToPass[i].second.getValueType()));
2131 // Add an implicit use GOT pointer in EBX.
2132 if (!isTailCall && Subtarget->isPICStyleGOT())
2133 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2135 // Add an implicit use of AL for x86 vararg functions.
2136 if (Is64Bit && isVarArg)
2137 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2139 if (InFlag.getNode())
2140 Ops.push_back(InFlag);
2143 // If this is the first return lowered for this function, add the regs
2144 // to the liveout set for the function.
2145 if (MF.getRegInfo().liveout_empty()) {
2146 SmallVector<CCValAssign, 16> RVLocs;
2147 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2149 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2150 for (unsigned i = 0; i != RVLocs.size(); ++i)
2151 if (RVLocs[i].isRegLoc())
2152 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2155 assert(((Callee.getOpcode() == ISD::Register &&
2156 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2157 cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) ||
2158 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2159 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2160 "Expecting a global address, external symbol, or scratch register");
2162 return DAG.getNode(X86ISD::TC_RETURN, dl,
2163 NodeTys, &Ops[0], Ops.size());
2166 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2167 InFlag = Chain.getValue(1);
2169 // Create the CALLSEQ_END node.
2170 unsigned NumBytesForCalleeToPush;
2171 if (IsCalleePop(isVarArg, CallConv))
2172 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2173 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2174 // If this is is a call to a struct-return function, the callee
2175 // pops the hidden struct pointer, so we have to push it back.
2176 // This is common for Darwin/X86, Linux & Mingw32 targets.
2177 NumBytesForCalleeToPush = 4;
2179 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2181 // Returns a flag for retval copy to use.
2182 Chain = DAG.getCALLSEQ_END(Chain,
2183 DAG.getIntPtrConstant(NumBytes, true),
2184 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2187 InFlag = Chain.getValue(1);
2189 // Handle result values, copying them out of physregs into vregs that we
2191 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2192 Ins, dl, DAG, InVals);
2196 //===----------------------------------------------------------------------===//
2197 // Fast Calling Convention (tail call) implementation
2198 //===----------------------------------------------------------------------===//
2200 // Like std call, callee cleans arguments, convention except that ECX is
2201 // reserved for storing the tail called function address. Only 2 registers are
2202 // free for argument passing (inreg). Tail call optimization is performed
2204 // * tailcallopt is enabled
2205 // * caller/callee are fastcc
2206 // On X86_64 architecture with GOT-style position independent code only local
2207 // (within module) calls are supported at the moment.
2208 // To keep the stack aligned according to platform abi the function
2209 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2210 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2211 // If a tail called function callee has more arguments than the caller the
2212 // caller needs to make sure that there is room to move the RETADDR to. This is
2213 // achieved by reserving an area the size of the argument delta right after the
2214 // original REtADDR, but before the saved framepointer or the spilled registers
2215 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2227 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2228 /// for a 16 byte align requirement.
2229 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2230 SelectionDAG& DAG) {
2231 MachineFunction &MF = DAG.getMachineFunction();
2232 const TargetMachine &TM = MF.getTarget();
2233 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2234 unsigned StackAlignment = TFI.getStackAlignment();
2235 uint64_t AlignMask = StackAlignment - 1;
2236 int64_t Offset = StackSize;
2237 uint64_t SlotSize = TD->getPointerSize();
2238 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2239 // Number smaller than 12 so just add the difference.
2240 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2242 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2243 Offset = ((~AlignMask) & Offset) + StackAlignment +
2244 (StackAlignment-SlotSize);
2249 /// MatchingStackOffset - Return true if the given stack call argument is
2250 /// already available in the same position (relatively) of the caller's
2251 /// incoming argument stack.
2253 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2254 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2255 const X86InstrInfo *TII) {
2257 if (Arg.getOpcode() == ISD::CopyFromReg) {
2258 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2259 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2261 MachineInstr *Def = MRI->getVRegDef(VR);
2264 if (!Flags.isByVal()) {
2265 if (!TII->isLoadFromStackSlot(Def, FI))
2268 unsigned Opcode = Def->getOpcode();
2269 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2270 Def->getOperand(1).isFI()) {
2271 FI = Def->getOperand(1).getIndex();
2272 if (MFI->getObjectSize(FI) != Flags.getByValSize())
2278 LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg);
2281 SDValue Ptr = Ld->getBasePtr();
2282 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2285 FI = FINode->getIndex();
2288 if (!MFI->isFixedObjectIndex(FI))
2290 return Offset == MFI->getObjectOffset(FI);
2293 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2294 /// for tail call optimization. Targets which want to do tail call
2295 /// optimization should implement this function.
2297 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2298 CallingConv::ID CalleeCC,
2300 const SmallVectorImpl<ISD::OutputArg> &Outs,
2301 const SmallVectorImpl<ISD::InputArg> &Ins,
2302 SelectionDAG& DAG) const {
2303 if (CalleeCC != CallingConv::Fast &&
2304 CalleeCC != CallingConv::C)
2307 // If -tailcallopt is specified, make fastcc functions tail-callable.
2308 const Function *CallerF = DAG.getMachineFunction().getFunction();
2309 if (PerformTailCallOpt) {
2310 if (CalleeCC == CallingConv::Fast &&
2311 CallerF->getCallingConv() == CalleeCC)
2316 // Look for obvious safe cases to perform tail call optimization that does not
2317 // requite ABI changes. This is what gcc calls sibcall.
2319 // Do not tail call optimize vararg calls for now.
2323 // If the callee takes no arguments then go on to check the results of the
2325 if (!Outs.empty()) {
2326 // Check if stack adjustment is needed. For now, do not do this if any
2327 // argument is passed on the stack.
2328 SmallVector<CCValAssign, 16> ArgLocs;
2329 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2330 ArgLocs, *DAG.getContext());
2331 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2332 if (CCInfo.getNextStackOffset()) {
2333 MachineFunction &MF = DAG.getMachineFunction();
2334 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2336 if (Subtarget->isTargetWin64())
2337 // Win64 ABI has additional complications.
2340 // Check if the arguments are already laid out in the right way as
2341 // the caller's fixed stack objects.
2342 MachineFrameInfo *MFI = MF.getFrameInfo();
2343 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2344 const X86InstrInfo *TII =
2345 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2346 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2347 CCValAssign &VA = ArgLocs[i];
2348 EVT RegVT = VA.getLocVT();
2349 SDValue Arg = Outs[i].Val;
2350 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2351 if (VA.getLocInfo() == CCValAssign::Indirect)
2353 if (!VA.isRegLoc()) {
2354 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2366 X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
2368 DenseMap<const Value *, unsigned> &vm,
2369 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2370 DenseMap<const AllocaInst *, int> &am
2372 , SmallSet<Instruction*, 8> &cil
2375 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2383 //===----------------------------------------------------------------------===//
2384 // Other Lowering Hooks
2385 //===----------------------------------------------------------------------===//
2388 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 int ReturnAddrIndex = FuncInfo->getRAIndex();
2393 if (ReturnAddrIndex == 0) {
2394 // Set up a frame object for the return address.
2395 uint64_t SlotSize = TD->getPointerSize();
2396 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2398 FuncInfo->setRAIndex(ReturnAddrIndex);
2401 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2405 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2406 bool hasSymbolicDisplacement) {
2407 // Offset should fit into 32 bit immediate field.
2408 if (!isInt32(Offset))
2411 // If we don't have a symbolic displacement - we don't have any extra
2413 if (!hasSymbolicDisplacement)
2416 // FIXME: Some tweaks might be needed for medium code model.
2417 if (M != CodeModel::Small && M != CodeModel::Kernel)
2420 // For small code model we assume that latest object is 16MB before end of 31
2421 // bits boundary. We may also accept pretty large negative constants knowing
2422 // that all objects are in the positive half of address space.
2423 if (M == CodeModel::Small && Offset < 16*1024*1024)
2426 // For kernel code model we know that all object resist in the negative half
2427 // of 32bits address space. We may not accept negative offsets, since they may
2428 // be just off and we may accept pretty large positive ones.
2429 if (M == CodeModel::Kernel && Offset > 0)
2435 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2436 /// specific condition code, returning the condition code and the LHS/RHS of the
2437 /// comparison to make.
2438 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2439 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2441 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2442 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2443 // X > -1 -> X == 0, jump !sign.
2444 RHS = DAG.getConstant(0, RHS.getValueType());
2445 return X86::COND_NS;
2446 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2447 // X < 0 -> X == 0, jump on sign.
2449 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2451 RHS = DAG.getConstant(0, RHS.getValueType());
2452 return X86::COND_LE;
2456 switch (SetCCOpcode) {
2457 default: llvm_unreachable("Invalid integer condition!");
2458 case ISD::SETEQ: return X86::COND_E;
2459 case ISD::SETGT: return X86::COND_G;
2460 case ISD::SETGE: return X86::COND_GE;
2461 case ISD::SETLT: return X86::COND_L;
2462 case ISD::SETLE: return X86::COND_LE;
2463 case ISD::SETNE: return X86::COND_NE;
2464 case ISD::SETULT: return X86::COND_B;
2465 case ISD::SETUGT: return X86::COND_A;
2466 case ISD::SETULE: return X86::COND_BE;
2467 case ISD::SETUGE: return X86::COND_AE;
2471 // First determine if it is required or is profitable to flip the operands.
2473 // If LHS is a foldable load, but RHS is not, flip the condition.
2474 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2475 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2476 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2477 std::swap(LHS, RHS);
2480 switch (SetCCOpcode) {
2486 std::swap(LHS, RHS);
2490 // On a floating point condition, the flags are set as follows:
2492 // 0 | 0 | 0 | X > Y
2493 // 0 | 0 | 1 | X < Y
2494 // 1 | 0 | 0 | X == Y
2495 // 1 | 1 | 1 | unordered
2496 switch (SetCCOpcode) {
2497 default: llvm_unreachable("Condcode should be pre-legalized away");
2499 case ISD::SETEQ: return X86::COND_E;
2500 case ISD::SETOLT: // flipped
2502 case ISD::SETGT: return X86::COND_A;
2503 case ISD::SETOLE: // flipped
2505 case ISD::SETGE: return X86::COND_AE;
2506 case ISD::SETUGT: // flipped
2508 case ISD::SETLT: return X86::COND_B;
2509 case ISD::SETUGE: // flipped
2511 case ISD::SETLE: return X86::COND_BE;
2513 case ISD::SETNE: return X86::COND_NE;
2514 case ISD::SETUO: return X86::COND_P;
2515 case ISD::SETO: return X86::COND_NP;
2517 case ISD::SETUNE: return X86::COND_INVALID;
2521 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2522 /// code. Current x86 isa includes the following FP cmov instructions:
2523 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2524 static bool hasFPCMov(unsigned X86CC) {
2540 /// isFPImmLegal - Returns true if the target can instruction select the
2541 /// specified FP immediate natively. If false, the legalizer will
2542 /// materialize the FP immediate as a load from a constant pool.
2543 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2544 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2545 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2551 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2552 /// the specified range (L, H].
2553 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2554 return (Val < 0) || (Val >= Low && Val < Hi);
2557 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2558 /// specified value.
2559 static bool isUndefOrEqual(int Val, int CmpVal) {
2560 if (Val < 0 || Val == CmpVal)
2565 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2566 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2567 /// the second operand.
2568 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2569 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2570 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2571 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2572 return (Mask[0] < 2 && Mask[1] < 2);
2576 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2577 SmallVector<int, 8> M;
2579 return ::isPSHUFDMask(M, N->getValueType(0));
2582 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2583 /// is suitable for input to PSHUFHW.
2584 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2585 if (VT != MVT::v8i16)
2588 // Lower quadword copied in order or undef.
2589 for (int i = 0; i != 4; ++i)
2590 if (Mask[i] >= 0 && Mask[i] != i)
2593 // Upper quadword shuffled.
2594 for (int i = 4; i != 8; ++i)
2595 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2601 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2602 SmallVector<int, 8> M;
2604 return ::isPSHUFHWMask(M, N->getValueType(0));
2607 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2608 /// is suitable for input to PSHUFLW.
2609 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2610 if (VT != MVT::v8i16)
2613 // Upper quadword copied in order.
2614 for (int i = 4; i != 8; ++i)
2615 if (Mask[i] >= 0 && Mask[i] != i)
2618 // Lower quadword shuffled.
2619 for (int i = 0; i != 4; ++i)
2626 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2627 SmallVector<int, 8> M;
2629 return ::isPSHUFLWMask(M, N->getValueType(0));
2632 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2633 /// is suitable for input to PALIGNR.
2634 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2636 int i, e = VT.getVectorNumElements();
2638 // Do not handle v2i64 / v2f64 shuffles with palignr.
2639 if (e < 4 || !hasSSSE3)
2642 for (i = 0; i != e; ++i)
2646 // All undef, not a palignr.
2650 // Determine if it's ok to perform a palignr with only the LHS, since we
2651 // don't have access to the actual shuffle elements to see if RHS is undef.
2652 bool Unary = Mask[i] < (int)e;
2653 bool NeedsUnary = false;
2655 int s = Mask[i] - i;
2657 // Check the rest of the elements to see if they are consecutive.
2658 for (++i; i != e; ++i) {
2663 Unary = Unary && (m < (int)e);
2664 NeedsUnary = NeedsUnary || (m < s);
2666 if (NeedsUnary && !Unary)
2668 if (Unary && m != ((s+i) & (e-1)))
2670 if (!Unary && m != (s+i))
2676 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2677 SmallVector<int, 8> M;
2679 return ::isPALIGNRMask(M, N->getValueType(0), true);
2682 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2683 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2684 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2685 int NumElems = VT.getVectorNumElements();
2686 if (NumElems != 2 && NumElems != 4)
2689 int Half = NumElems / 2;
2690 for (int i = 0; i < Half; ++i)
2691 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2693 for (int i = Half; i < NumElems; ++i)
2694 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2700 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2701 SmallVector<int, 8> M;
2703 return ::isSHUFPMask(M, N->getValueType(0));
2706 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2707 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2708 /// half elements to come from vector 1 (which would equal the dest.) and
2709 /// the upper half to come from vector 2.
2710 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2711 int NumElems = VT.getVectorNumElements();
2713 if (NumElems != 2 && NumElems != 4)
2716 int Half = NumElems / 2;
2717 for (int i = 0; i < Half; ++i)
2718 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2720 for (int i = Half; i < NumElems; ++i)
2721 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2726 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2727 SmallVector<int, 8> M;
2729 return isCommutedSHUFPMask(M, N->getValueType(0));
2732 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2733 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2734 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2735 if (N->getValueType(0).getVectorNumElements() != 4)
2738 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2739 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2740 isUndefOrEqual(N->getMaskElt(1), 7) &&
2741 isUndefOrEqual(N->getMaskElt(2), 2) &&
2742 isUndefOrEqual(N->getMaskElt(3), 3);
2745 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2746 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2748 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2749 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2754 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2755 isUndefOrEqual(N->getMaskElt(1), 3) &&
2756 isUndefOrEqual(N->getMaskElt(2), 2) &&
2757 isUndefOrEqual(N->getMaskElt(3), 3);
2760 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2761 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2762 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2763 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2765 if (NumElems != 2 && NumElems != 4)
2768 for (unsigned i = 0; i < NumElems/2; ++i)
2769 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2772 for (unsigned i = NumElems/2; i < NumElems; ++i)
2773 if (!isUndefOrEqual(N->getMaskElt(i), i))
2779 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2780 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2781 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2782 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2784 if (NumElems != 2 && NumElems != 4)
2787 for (unsigned i = 0; i < NumElems/2; ++i)
2788 if (!isUndefOrEqual(N->getMaskElt(i), i))
2791 for (unsigned i = 0; i < NumElems/2; ++i)
2792 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2798 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2799 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2800 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2801 bool V2IsSplat = false) {
2802 int NumElts = VT.getVectorNumElements();
2803 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2806 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2808 int BitI1 = Mask[i+1];
2809 if (!isUndefOrEqual(BitI, j))
2812 if (!isUndefOrEqual(BitI1, NumElts))
2815 if (!isUndefOrEqual(BitI1, j + NumElts))
2822 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2823 SmallVector<int, 8> M;
2825 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2828 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2829 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2830 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2831 bool V2IsSplat = false) {
2832 int NumElts = VT.getVectorNumElements();
2833 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2836 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2838 int BitI1 = Mask[i+1];
2839 if (!isUndefOrEqual(BitI, j + NumElts/2))
2842 if (isUndefOrEqual(BitI1, NumElts))
2845 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2852 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2853 SmallVector<int, 8> M;
2855 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2858 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2859 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2861 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2862 int NumElems = VT.getVectorNumElements();
2863 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2866 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2868 int BitI1 = Mask[i+1];
2869 if (!isUndefOrEqual(BitI, j))
2871 if (!isUndefOrEqual(BitI1, j))
2877 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2878 SmallVector<int, 8> M;
2880 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2883 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2884 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2886 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2887 int NumElems = VT.getVectorNumElements();
2888 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2891 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2893 int BitI1 = Mask[i+1];
2894 if (!isUndefOrEqual(BitI, j))
2896 if (!isUndefOrEqual(BitI1, j))
2902 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2903 SmallVector<int, 8> M;
2905 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2908 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2909 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2910 /// MOVSD, and MOVD, i.e. setting the lowest element.
2911 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2912 if (VT.getVectorElementType().getSizeInBits() < 32)
2915 int NumElts = VT.getVectorNumElements();
2917 if (!isUndefOrEqual(Mask[0], NumElts))
2920 for (int i = 1; i < NumElts; ++i)
2921 if (!isUndefOrEqual(Mask[i], i))
2927 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2928 SmallVector<int, 8> M;
2930 return ::isMOVLMask(M, N->getValueType(0));
2933 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2934 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2935 /// element of vector 2 and the other elements to come from vector 1 in order.
2936 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2937 bool V2IsSplat = false, bool V2IsUndef = false) {
2938 int NumOps = VT.getVectorNumElements();
2939 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2942 if (!isUndefOrEqual(Mask[0], 0))
2945 for (int i = 1; i < NumOps; ++i)
2946 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2947 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2948 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2954 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2955 bool V2IsUndef = false) {
2956 SmallVector<int, 8> M;
2958 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2961 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2962 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2963 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2964 if (N->getValueType(0).getVectorNumElements() != 4)
2967 // Expect 1, 1, 3, 3
2968 for (unsigned i = 0; i < 2; ++i) {
2969 int Elt = N->getMaskElt(i);
2970 if (Elt >= 0 && Elt != 1)
2975 for (unsigned i = 2; i < 4; ++i) {
2976 int Elt = N->getMaskElt(i);
2977 if (Elt >= 0 && Elt != 3)
2982 // Don't use movshdup if it can be done with a shufps.
2983 // FIXME: verify that matching u, u, 3, 3 is what we want.
2987 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2988 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2989 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2990 if (N->getValueType(0).getVectorNumElements() != 4)
2993 // Expect 0, 0, 2, 2
2994 for (unsigned i = 0; i < 2; ++i)
2995 if (N->getMaskElt(i) > 0)
2999 for (unsigned i = 2; i < 4; ++i) {
3000 int Elt = N->getMaskElt(i);
3001 if (Elt >= 0 && Elt != 2)
3006 // Don't use movsldup if it can be done with a shufps.
3010 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3011 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3012 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3013 int e = N->getValueType(0).getVectorNumElements() / 2;
3015 for (int i = 0; i < e; ++i)
3016 if (!isUndefOrEqual(N->getMaskElt(i), i))
3018 for (int i = 0; i < e; ++i)
3019 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3024 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3025 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3026 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3027 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3028 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3030 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3032 for (int i = 0; i < NumOperands; ++i) {
3033 int Val = SVOp->getMaskElt(NumOperands-i-1);
3034 if (Val < 0) Val = 0;
3035 if (Val >= NumOperands) Val -= NumOperands;
3037 if (i != NumOperands - 1)
3043 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3044 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3045 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3048 // 8 nodes, but we only care about the last 4.
3049 for (unsigned i = 7; i >= 4; --i) {
3050 int Val = SVOp->getMaskElt(i);
3059 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3060 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3061 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3064 // 8 nodes, but we only care about the first 4.
3065 for (int i = 3; i >= 0; --i) {
3066 int Val = SVOp->getMaskElt(i);
3075 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3076 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3077 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3079 EVT VVT = N->getValueType(0);
3080 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3084 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3085 Val = SVOp->getMaskElt(i);
3089 return (Val - i) * EltSize;
3092 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3094 bool X86::isZeroNode(SDValue Elt) {
3095 return ((isa<ConstantSDNode>(Elt) &&
3096 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
3097 (isa<ConstantFPSDNode>(Elt) &&
3098 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3101 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3102 /// their permute mask.
3103 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3104 SelectionDAG &DAG) {
3105 EVT VT = SVOp->getValueType(0);
3106 unsigned NumElems = VT.getVectorNumElements();
3107 SmallVector<int, 8> MaskVec;
3109 for (unsigned i = 0; i != NumElems; ++i) {
3110 int idx = SVOp->getMaskElt(i);
3112 MaskVec.push_back(idx);
3113 else if (idx < (int)NumElems)
3114 MaskVec.push_back(idx + NumElems);
3116 MaskVec.push_back(idx - NumElems);
3118 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3119 SVOp->getOperand(0), &MaskVec[0]);
3122 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3123 /// the two vector operands have swapped position.
3124 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3125 unsigned NumElems = VT.getVectorNumElements();
3126 for (unsigned i = 0; i != NumElems; ++i) {
3130 else if (idx < (int)NumElems)
3131 Mask[i] = idx + NumElems;
3133 Mask[i] = idx - NumElems;
3137 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3138 /// match movhlps. The lower half elements should come from upper half of
3139 /// V1 (and in order), and the upper half elements should come from the upper
3140 /// half of V2 (and in order).
3141 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3142 if (Op->getValueType(0).getVectorNumElements() != 4)
3144 for (unsigned i = 0, e = 2; i != e; ++i)
3145 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3147 for (unsigned i = 2; i != 4; ++i)
3148 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3153 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3154 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3156 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3157 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3159 N = N->getOperand(0).getNode();
3160 if (!ISD::isNON_EXTLoad(N))
3163 *LD = cast<LoadSDNode>(N);
3167 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3168 /// match movlp{s|d}. The lower half elements should come from lower half of
3169 /// V1 (and in order), and the upper half elements should come from the upper
3170 /// half of V2 (and in order). And since V1 will become the source of the
3171 /// MOVLP, it must be either a vector load or a scalar load to vector.
3172 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3173 ShuffleVectorSDNode *Op) {
3174 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3176 // Is V2 is a vector load, don't do this transformation. We will try to use
3177 // load folding shufps op.
3178 if (ISD::isNON_EXTLoad(V2))
3181 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3183 if (NumElems != 2 && NumElems != 4)
3185 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3186 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3188 for (unsigned i = NumElems/2; i != NumElems; ++i)
3189 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3194 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3196 static bool isSplatVector(SDNode *N) {
3197 if (N->getOpcode() != ISD::BUILD_VECTOR)
3200 SDValue SplatValue = N->getOperand(0);
3201 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3202 if (N->getOperand(i) != SplatValue)
3207 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3208 /// to an zero vector.
3209 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3210 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3211 SDValue V1 = N->getOperand(0);
3212 SDValue V2 = N->getOperand(1);
3213 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3214 for (unsigned i = 0; i != NumElems; ++i) {
3215 int Idx = N->getMaskElt(i);
3216 if (Idx >= (int)NumElems) {
3217 unsigned Opc = V2.getOpcode();
3218 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3220 if (Opc != ISD::BUILD_VECTOR ||
3221 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3223 } else if (Idx >= 0) {
3224 unsigned Opc = V1.getOpcode();
3225 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3227 if (Opc != ISD::BUILD_VECTOR ||
3228 !X86::isZeroNode(V1.getOperand(Idx)))
3235 /// getZeroVector - Returns a vector of specified type with all zero elements.
3237 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3239 assert(VT.isVector() && "Expected a vector type");
3241 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3242 // type. This ensures they get CSE'd.
3244 if (VT.getSizeInBits() == 64) { // MMX
3245 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3246 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3247 } else if (HasSSE2) { // SSE2
3248 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3249 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3251 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3254 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3257 /// getOnesVector - Returns a vector of specified type with all bits set.
3259 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3260 assert(VT.isVector() && "Expected a vector type");
3262 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3263 // type. This ensures they get CSE'd.
3264 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3266 if (VT.getSizeInBits() == 64) // MMX
3267 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3270 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3274 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3275 /// that point to V2 points to its first element.
3276 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3277 EVT VT = SVOp->getValueType(0);
3278 unsigned NumElems = VT.getVectorNumElements();
3280 bool Changed = false;
3281 SmallVector<int, 8> MaskVec;
3282 SVOp->getMask(MaskVec);
3284 for (unsigned i = 0; i != NumElems; ++i) {
3285 if (MaskVec[i] > (int)NumElems) {
3286 MaskVec[i] = NumElems;
3291 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3292 SVOp->getOperand(1), &MaskVec[0]);
3293 return SDValue(SVOp, 0);
3296 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3297 /// operation of specified width.
3298 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3300 unsigned NumElems = VT.getVectorNumElements();
3301 SmallVector<int, 8> Mask;
3302 Mask.push_back(NumElems);
3303 for (unsigned i = 1; i != NumElems; ++i)
3305 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3308 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3309 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3311 unsigned NumElems = VT.getVectorNumElements();
3312 SmallVector<int, 8> Mask;
3313 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3315 Mask.push_back(i + NumElems);
3317 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3320 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3321 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3323 unsigned NumElems = VT.getVectorNumElements();
3324 unsigned Half = NumElems/2;
3325 SmallVector<int, 8> Mask;
3326 for (unsigned i = 0; i != Half; ++i) {
3327 Mask.push_back(i + Half);
3328 Mask.push_back(i + NumElems + Half);
3330 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3333 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3334 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3336 if (SV->getValueType(0).getVectorNumElements() <= 4)
3337 return SDValue(SV, 0);
3339 EVT PVT = MVT::v4f32;
3340 EVT VT = SV->getValueType(0);
3341 DebugLoc dl = SV->getDebugLoc();
3342 SDValue V1 = SV->getOperand(0);
3343 int NumElems = VT.getVectorNumElements();
3344 int EltNo = SV->getSplatIndex();
3346 // unpack elements to the correct location
3347 while (NumElems > 4) {
3348 if (EltNo < NumElems/2) {
3349 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3351 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3352 EltNo -= NumElems/2;
3357 // Perform the splat.
3358 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3359 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3360 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3361 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3364 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3365 /// vector of zero or undef vector. This produces a shuffle where the low
3366 /// element of V2 is swizzled into the zero/undef vector, landing at element
3367 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3368 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3369 bool isZero, bool HasSSE2,
3370 SelectionDAG &DAG) {
3371 EVT VT = V2.getValueType();
3373 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3374 unsigned NumElems = VT.getVectorNumElements();
3375 SmallVector<int, 16> MaskVec;
3376 for (unsigned i = 0; i != NumElems; ++i)
3377 // If this is the insertion idx, put the low elt of V2 here.
3378 MaskVec.push_back(i == Idx ? NumElems : i);
3379 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3382 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3383 /// a shuffle that is zero.
3385 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3386 bool Low, SelectionDAG &DAG) {
3387 unsigned NumZeros = 0;
3388 for (int i = 0; i < NumElems; ++i) {
3389 unsigned Index = Low ? i : NumElems-i-1;
3390 int Idx = SVOp->getMaskElt(Index);
3395 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3396 if (Elt.getNode() && X86::isZeroNode(Elt))
3404 /// isVectorShift - Returns true if the shuffle can be implemented as a
3405 /// logical left or right shift of a vector.
3406 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3407 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3408 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3409 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3412 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3415 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3419 bool SeenV1 = false;
3420 bool SeenV2 = false;
3421 for (int i = NumZeros; i < NumElems; ++i) {
3422 int Val = isLeft ? (i - NumZeros) : i;
3423 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3435 if (SeenV1 && SeenV2)
3438 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3444 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3446 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3447 unsigned NumNonZero, unsigned NumZero,
3448 SelectionDAG &DAG, TargetLowering &TLI) {
3452 DebugLoc dl = Op.getDebugLoc();
3455 for (unsigned i = 0; i < 16; ++i) {
3456 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3457 if (ThisIsNonZero && First) {
3459 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3461 V = DAG.getUNDEF(MVT::v8i16);
3466 SDValue ThisElt(0, 0), LastElt(0, 0);
3467 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3468 if (LastIsNonZero) {
3469 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3470 MVT::i16, Op.getOperand(i-1));
3472 if (ThisIsNonZero) {
3473 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3474 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3475 ThisElt, DAG.getConstant(8, MVT::i8));
3477 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3481 if (ThisElt.getNode())
3482 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3483 DAG.getIntPtrConstant(i/2));
3487 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3490 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3492 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3493 unsigned NumNonZero, unsigned NumZero,
3494 SelectionDAG &DAG, TargetLowering &TLI) {
3498 DebugLoc dl = Op.getDebugLoc();
3501 for (unsigned i = 0; i < 8; ++i) {
3502 bool isNonZero = (NonZeros & (1 << i)) != 0;
3506 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3508 V = DAG.getUNDEF(MVT::v8i16);
3511 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3512 MVT::v8i16, V, Op.getOperand(i),
3513 DAG.getIntPtrConstant(i));
3520 /// getVShift - Return a vector logical shift node.
3522 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3523 unsigned NumBits, SelectionDAG &DAG,
3524 const TargetLowering &TLI, DebugLoc dl) {
3525 bool isMMX = VT.getSizeInBits() == 64;
3526 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3527 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3528 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3529 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3530 DAG.getNode(Opc, dl, ShVT, SrcOp,
3531 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3535 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3536 SelectionDAG &DAG) {
3538 // Check if the scalar load can be widened into a vector load. And if
3539 // the address is "base + cst" see if the cst can be "absorbed" into
3540 // the shuffle mask.
3541 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3542 SDValue Ptr = LD->getBasePtr();
3543 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3545 EVT PVT = LD->getValueType(0);
3546 if (PVT != MVT::i32 && PVT != MVT::f32)
3551 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3552 FI = FINode->getIndex();
3554 } else if (Ptr.getOpcode() == ISD::ADD &&
3555 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3556 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3557 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3558 Offset = Ptr.getConstantOperandVal(1);
3559 Ptr = Ptr.getOperand(0);
3564 SDValue Chain = LD->getChain();
3565 // Make sure the stack object alignment is at least 16.
3566 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3567 if (DAG.InferPtrAlignment(Ptr) < 16) {
3568 if (MFI->isFixedObjectIndex(FI)) {
3569 // Can't change the alignment. FIXME: It's possible to compute
3570 // the exact stack offset and reference FI + adjust offset instead.
3571 // If someone *really* cares about this. That's the way to implement it.
3574 MFI->setObjectAlignment(FI, 16);
3578 // (Offset % 16) must be multiple of 4. Then address is then
3579 // Ptr + (Offset & ~15).
3582 if ((Offset % 16) & 3)
3584 int64_t StartOffset = Offset & ~15;
3586 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3587 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3589 int EltNo = (Offset - StartOffset) >> 2;
3590 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3591 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3592 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0);
3593 // Canonicalize it to a v4i32 shuffle.
3594 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3595 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3596 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3597 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3604 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3605 DebugLoc dl = Op.getDebugLoc();
3606 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3607 if (ISD::isBuildVectorAllZeros(Op.getNode())
3608 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3609 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3610 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3611 // eliminated on x86-32 hosts.
3612 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3615 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3616 return getOnesVector(Op.getValueType(), DAG, dl);
3617 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3620 EVT VT = Op.getValueType();
3621 EVT ExtVT = VT.getVectorElementType();
3622 unsigned EVTBits = ExtVT.getSizeInBits();
3624 unsigned NumElems = Op.getNumOperands();
3625 unsigned NumZero = 0;
3626 unsigned NumNonZero = 0;
3627 unsigned NonZeros = 0;
3628 bool IsAllConstants = true;
3629 SmallSet<SDValue, 8> Values;
3630 for (unsigned i = 0; i < NumElems; ++i) {
3631 SDValue Elt = Op.getOperand(i);
3632 if (Elt.getOpcode() == ISD::UNDEF)
3635 if (Elt.getOpcode() != ISD::Constant &&
3636 Elt.getOpcode() != ISD::ConstantFP)
3637 IsAllConstants = false;
3638 if (X86::isZeroNode(Elt))
3641 NonZeros |= (1 << i);
3646 if (NumNonZero == 0) {
3647 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3648 return DAG.getUNDEF(VT);
3651 // Special case for single non-zero, non-undef, element.
3652 if (NumNonZero == 1) {
3653 unsigned Idx = CountTrailingZeros_32(NonZeros);
3654 SDValue Item = Op.getOperand(Idx);
3656 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3657 // the value are obviously zero, truncate the value to i32 and do the
3658 // insertion that way. Only do this if the value is non-constant or if the
3659 // value is a constant being inserted into element 0. It is cheaper to do
3660 // a constant pool load than it is to do a movd + shuffle.
3661 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3662 (!IsAllConstants || Idx == 0)) {
3663 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3664 // Handle MMX and SSE both.
3665 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3666 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3668 // Truncate the value (which may itself be a constant) to i32, and
3669 // convert it to a vector with movd (S2V+shuffle to zero extend).
3670 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3671 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3672 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3673 Subtarget->hasSSE2(), DAG);
3675 // Now we have our 32-bit value zero extended in the low element of
3676 // a vector. If Idx != 0, swizzle it into place.
3678 SmallVector<int, 4> Mask;
3679 Mask.push_back(Idx);
3680 for (unsigned i = 1; i != VecElts; ++i)
3682 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3683 DAG.getUNDEF(Item.getValueType()),
3686 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3690 // If we have a constant or non-constant insertion into the low element of
3691 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3692 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3693 // depending on what the source datatype is.
3696 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3697 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3698 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3699 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3700 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3701 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3703 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3704 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3705 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3706 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3707 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3708 Subtarget->hasSSE2(), DAG);
3709 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3713 // Is it a vector logical left shift?
3714 if (NumElems == 2 && Idx == 1 &&
3715 X86::isZeroNode(Op.getOperand(0)) &&
3716 !X86::isZeroNode(Op.getOperand(1))) {
3717 unsigned NumBits = VT.getSizeInBits();
3718 return getVShift(true, VT,
3719 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3720 VT, Op.getOperand(1)),
3721 NumBits/2, DAG, *this, dl);
3724 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3727 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3728 // is a non-constant being inserted into an element other than the low one,
3729 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3730 // movd/movss) to move this into the low element, then shuffle it into
3732 if (EVTBits == 32) {
3733 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3735 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3736 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3737 Subtarget->hasSSE2(), DAG);
3738 SmallVector<int, 8> MaskVec;
3739 for (unsigned i = 0; i < NumElems; i++)
3740 MaskVec.push_back(i == Idx ? 0 : 1);
3741 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3745 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3746 if (Values.size() == 1) {
3747 if (EVTBits == 32) {
3748 // Instead of a shuffle like this:
3749 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3750 // Check if it's possible to issue this instead.
3751 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3752 unsigned Idx = CountTrailingZeros_32(NonZeros);
3753 SDValue Item = Op.getOperand(Idx);
3754 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3755 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3760 // A vector full of immediates; various special cases are already
3761 // handled, so this is best done with a single constant-pool load.
3765 // Let legalizer expand 2-wide build_vectors.
3766 if (EVTBits == 64) {
3767 if (NumNonZero == 1) {
3768 // One half is zero or undef.
3769 unsigned Idx = CountTrailingZeros_32(NonZeros);
3770 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3771 Op.getOperand(Idx));
3772 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3773 Subtarget->hasSSE2(), DAG);
3778 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3779 if (EVTBits == 8 && NumElems == 16) {
3780 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3782 if (V.getNode()) return V;
3785 if (EVTBits == 16 && NumElems == 8) {
3786 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3788 if (V.getNode()) return V;
3791 // If element VT is == 32 bits, turn it into a number of shuffles.
3792 SmallVector<SDValue, 8> V;
3794 if (NumElems == 4 && NumZero > 0) {
3795 for (unsigned i = 0; i < 4; ++i) {
3796 bool isZero = !(NonZeros & (1 << i));
3798 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3800 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3803 for (unsigned i = 0; i < 2; ++i) {
3804 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3807 V[i] = V[i*2]; // Must be a zero vector.
3810 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3813 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3816 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3821 SmallVector<int, 8> MaskVec;
3822 bool Reverse = (NonZeros & 0x3) == 2;
3823 for (unsigned i = 0; i < 2; ++i)
3824 MaskVec.push_back(Reverse ? 1-i : i);
3825 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3826 for (unsigned i = 0; i < 2; ++i)
3827 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3828 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3831 if (Values.size() > 2) {
3832 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3833 // values to be inserted is equal to the number of elements, in which case
3834 // use the unpack code below in the hopes of matching the consecutive elts
3835 // load merge pattern for shuffles.
3836 // FIXME: We could probably just check that here directly.
3837 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3838 getSubtarget()->hasSSE41()) {
3839 V[0] = DAG.getUNDEF(VT);
3840 for (unsigned i = 0; i < NumElems; ++i)
3841 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3842 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3843 Op.getOperand(i), DAG.getIntPtrConstant(i));
3846 // Expand into a number of unpckl*.
3848 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3849 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3850 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3851 for (unsigned i = 0; i < NumElems; ++i)
3852 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3854 while (NumElems != 0) {
3855 for (unsigned i = 0; i < NumElems; ++i)
3856 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3866 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3867 // We support concatenate two MMX registers and place them in a MMX
3868 // register. This is better than doing a stack convert.
3869 DebugLoc dl = Op.getDebugLoc();
3870 EVT ResVT = Op.getValueType();
3871 assert(Op.getNumOperands() == 2);
3872 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
3873 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
3875 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
3876 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3877 InVec = Op.getOperand(1);
3878 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3879 unsigned NumElts = ResVT.getVectorNumElements();
3880 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3881 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
3882 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
3884 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
3885 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3886 Mask[0] = 0; Mask[1] = 2;
3887 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
3889 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3892 // v8i16 shuffles - Prefer shuffles in the following order:
3893 // 1. [all] pshuflw, pshufhw, optional move
3894 // 2. [ssse3] 1 x pshufb
3895 // 3. [ssse3] 2 x pshufb + 1 x por
3896 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3898 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3899 SelectionDAG &DAG, X86TargetLowering &TLI) {
3900 SDValue V1 = SVOp->getOperand(0);
3901 SDValue V2 = SVOp->getOperand(1);
3902 DebugLoc dl = SVOp->getDebugLoc();
3903 SmallVector<int, 8> MaskVals;
3905 // Determine if more than 1 of the words in each of the low and high quadwords
3906 // of the result come from the same quadword of one of the two inputs. Undef
3907 // mask values count as coming from any quadword, for better codegen.
3908 SmallVector<unsigned, 4> LoQuad(4);
3909 SmallVector<unsigned, 4> HiQuad(4);
3910 BitVector InputQuads(4);
3911 for (unsigned i = 0; i < 8; ++i) {
3912 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3913 int EltIdx = SVOp->getMaskElt(i);
3914 MaskVals.push_back(EltIdx);
3923 InputQuads.set(EltIdx / 4);
3926 int BestLoQuad = -1;
3927 unsigned MaxQuad = 1;
3928 for (unsigned i = 0; i < 4; ++i) {
3929 if (LoQuad[i] > MaxQuad) {
3931 MaxQuad = LoQuad[i];
3935 int BestHiQuad = -1;
3937 for (unsigned i = 0; i < 4; ++i) {
3938 if (HiQuad[i] > MaxQuad) {
3940 MaxQuad = HiQuad[i];
3944 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3945 // of the two input vectors, shuffle them into one input vector so only a
3946 // single pshufb instruction is necessary. If There are more than 2 input
3947 // quads, disable the next transformation since it does not help SSSE3.
3948 bool V1Used = InputQuads[0] || InputQuads[1];
3949 bool V2Used = InputQuads[2] || InputQuads[3];
3950 if (TLI.getSubtarget()->hasSSSE3()) {
3951 if (InputQuads.count() == 2 && V1Used && V2Used) {
3952 BestLoQuad = InputQuads.find_first();
3953 BestHiQuad = InputQuads.find_next(BestLoQuad);
3955 if (InputQuads.count() > 2) {
3961 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3962 // the shuffle mask. If a quad is scored as -1, that means that it contains
3963 // words from all 4 input quadwords.
3965 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3966 SmallVector<int, 8> MaskV;
3967 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3968 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3969 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3970 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3971 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3972 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3974 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3975 // source words for the shuffle, to aid later transformations.
3976 bool AllWordsInNewV = true;
3977 bool InOrder[2] = { true, true };
3978 for (unsigned i = 0; i != 8; ++i) {
3979 int idx = MaskVals[i];
3981 InOrder[i/4] = false;
3982 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3984 AllWordsInNewV = false;
3988 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3989 if (AllWordsInNewV) {
3990 for (int i = 0; i != 8; ++i) {
3991 int idx = MaskVals[i];
3994 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3995 if ((idx != i) && idx < 4)
3997 if ((idx != i) && idx > 3)
4006 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4007 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4008 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4009 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4010 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4014 // If we have SSSE3, and all words of the result are from 1 input vector,
4015 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4016 // is present, fall back to case 4.
4017 if (TLI.getSubtarget()->hasSSSE3()) {
4018 SmallVector<SDValue,16> pshufbMask;
4020 // If we have elements from both input vectors, set the high bit of the
4021 // shuffle mask element to zero out elements that come from V2 in the V1
4022 // mask, and elements that come from V1 in the V2 mask, so that the two
4023 // results can be OR'd together.
4024 bool TwoInputs = V1Used && V2Used;
4025 for (unsigned i = 0; i != 8; ++i) {
4026 int EltIdx = MaskVals[i] * 2;
4027 if (TwoInputs && (EltIdx >= 16)) {
4028 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4029 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4032 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4033 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4035 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4036 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4037 DAG.getNode(ISD::BUILD_VECTOR, dl,
4038 MVT::v16i8, &pshufbMask[0], 16));
4040 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4042 // Calculate the shuffle mask for the second input, shuffle it, and
4043 // OR it with the first shuffled input.
4045 for (unsigned i = 0; i != 8; ++i) {
4046 int EltIdx = MaskVals[i] * 2;
4048 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4049 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4052 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4053 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4055 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4056 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4057 DAG.getNode(ISD::BUILD_VECTOR, dl,
4058 MVT::v16i8, &pshufbMask[0], 16));
4059 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4060 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4063 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4064 // and update MaskVals with new element order.
4065 BitVector InOrder(8);
4066 if (BestLoQuad >= 0) {
4067 SmallVector<int, 8> MaskV;
4068 for (int i = 0; i != 4; ++i) {
4069 int idx = MaskVals[i];
4071 MaskV.push_back(-1);
4073 } else if ((idx / 4) == BestLoQuad) {
4074 MaskV.push_back(idx & 3);
4077 MaskV.push_back(-1);
4080 for (unsigned i = 4; i != 8; ++i)
4082 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4086 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4087 // and update MaskVals with the new element order.
4088 if (BestHiQuad >= 0) {
4089 SmallVector<int, 8> MaskV;
4090 for (unsigned i = 0; i != 4; ++i)
4092 for (unsigned i = 4; i != 8; ++i) {
4093 int idx = MaskVals[i];
4095 MaskV.push_back(-1);
4097 } else if ((idx / 4) == BestHiQuad) {
4098 MaskV.push_back((idx & 3) + 4);
4101 MaskV.push_back(-1);
4104 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4108 // In case BestHi & BestLo were both -1, which means each quadword has a word
4109 // from each of the four input quadwords, calculate the InOrder bitvector now
4110 // before falling through to the insert/extract cleanup.
4111 if (BestLoQuad == -1 && BestHiQuad == -1) {
4113 for (int i = 0; i != 8; ++i)
4114 if (MaskVals[i] < 0 || MaskVals[i] == i)
4118 // The other elements are put in the right place using pextrw and pinsrw.
4119 for (unsigned i = 0; i != 8; ++i) {
4122 int EltIdx = MaskVals[i];
4125 SDValue ExtOp = (EltIdx < 8)
4126 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4127 DAG.getIntPtrConstant(EltIdx))
4128 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4129 DAG.getIntPtrConstant(EltIdx - 8));
4130 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4131 DAG.getIntPtrConstant(i));
4136 // v16i8 shuffles - Prefer shuffles in the following order:
4137 // 1. [ssse3] 1 x pshufb
4138 // 2. [ssse3] 2 x pshufb + 1 x por
4139 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4141 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4142 SelectionDAG &DAG, X86TargetLowering &TLI) {
4143 SDValue V1 = SVOp->getOperand(0);
4144 SDValue V2 = SVOp->getOperand(1);
4145 DebugLoc dl = SVOp->getDebugLoc();
4146 SmallVector<int, 16> MaskVals;
4147 SVOp->getMask(MaskVals);
4149 // If we have SSSE3, case 1 is generated when all result bytes come from
4150 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4151 // present, fall back to case 3.
4152 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4155 for (unsigned i = 0; i < 16; ++i) {
4156 int EltIdx = MaskVals[i];
4165 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4166 if (TLI.getSubtarget()->hasSSSE3()) {
4167 SmallVector<SDValue,16> pshufbMask;
4169 // If all result elements are from one input vector, then only translate
4170 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4172 // Otherwise, we have elements from both input vectors, and must zero out
4173 // elements that come from V2 in the first mask, and V1 in the second mask
4174 // so that we can OR them together.
4175 bool TwoInputs = !(V1Only || V2Only);
4176 for (unsigned i = 0; i != 16; ++i) {
4177 int EltIdx = MaskVals[i];
4178 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4179 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4182 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4184 // If all the elements are from V2, assign it to V1 and return after
4185 // building the first pshufb.
4188 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4189 DAG.getNode(ISD::BUILD_VECTOR, dl,
4190 MVT::v16i8, &pshufbMask[0], 16));
4194 // Calculate the shuffle mask for the second input, shuffle it, and
4195 // OR it with the first shuffled input.
4197 for (unsigned i = 0; i != 16; ++i) {
4198 int EltIdx = MaskVals[i];
4200 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4203 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4205 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4206 DAG.getNode(ISD::BUILD_VECTOR, dl,
4207 MVT::v16i8, &pshufbMask[0], 16));
4208 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4211 // No SSSE3 - Calculate in place words and then fix all out of place words
4212 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4213 // the 16 different words that comprise the two doublequadword input vectors.
4214 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4215 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4216 SDValue NewV = V2Only ? V2 : V1;
4217 for (int i = 0; i != 8; ++i) {
4218 int Elt0 = MaskVals[i*2];
4219 int Elt1 = MaskVals[i*2+1];
4221 // This word of the result is all undef, skip it.
4222 if (Elt0 < 0 && Elt1 < 0)
4225 // This word of the result is already in the correct place, skip it.
4226 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4228 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4231 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4232 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4235 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4236 // using a single extract together, load it and store it.
4237 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4238 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4239 DAG.getIntPtrConstant(Elt1 / 2));
4240 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4241 DAG.getIntPtrConstant(i));
4245 // If Elt1 is defined, extract it from the appropriate source. If the
4246 // source byte is not also odd, shift the extracted word left 8 bits
4247 // otherwise clear the bottom 8 bits if we need to do an or.
4249 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4250 DAG.getIntPtrConstant(Elt1 / 2));
4251 if ((Elt1 & 1) == 0)
4252 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4253 DAG.getConstant(8, TLI.getShiftAmountTy()));
4255 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4256 DAG.getConstant(0xFF00, MVT::i16));
4258 // If Elt0 is defined, extract it from the appropriate source. If the
4259 // source byte is not also even, shift the extracted word right 8 bits. If
4260 // Elt1 was also defined, OR the extracted values together before
4261 // inserting them in the result.
4263 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4264 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4265 if ((Elt0 & 1) != 0)
4266 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4267 DAG.getConstant(8, TLI.getShiftAmountTy()));
4269 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4270 DAG.getConstant(0x00FF, MVT::i16));
4271 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4274 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4275 DAG.getIntPtrConstant(i));
4277 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4280 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4281 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4282 /// done when every pair / quad of shuffle mask elements point to elements in
4283 /// the right sequence. e.g.
4284 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4286 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4288 TargetLowering &TLI, DebugLoc dl) {
4289 EVT VT = SVOp->getValueType(0);
4290 SDValue V1 = SVOp->getOperand(0);
4291 SDValue V2 = SVOp->getOperand(1);
4292 unsigned NumElems = VT.getVectorNumElements();
4293 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4294 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4295 EVT MaskEltVT = MaskVT.getVectorElementType();
4297 switch (VT.getSimpleVT().SimpleTy) {
4298 default: assert(false && "Unexpected!");
4299 case MVT::v4f32: NewVT = MVT::v2f64; break;
4300 case MVT::v4i32: NewVT = MVT::v2i64; break;
4301 case MVT::v8i16: NewVT = MVT::v4i32; break;
4302 case MVT::v16i8: NewVT = MVT::v4i32; break;
4305 if (NewWidth == 2) {
4311 int Scale = NumElems / NewWidth;
4312 SmallVector<int, 8> MaskVec;
4313 for (unsigned i = 0; i < NumElems; i += Scale) {
4315 for (int j = 0; j < Scale; ++j) {
4316 int EltIdx = SVOp->getMaskElt(i+j);
4320 StartIdx = EltIdx - (EltIdx % Scale);
4321 if (EltIdx != StartIdx + j)
4325 MaskVec.push_back(-1);
4327 MaskVec.push_back(StartIdx / Scale);
4330 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4331 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4332 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4335 /// getVZextMovL - Return a zero-extending vector move low node.
4337 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4338 SDValue SrcOp, SelectionDAG &DAG,
4339 const X86Subtarget *Subtarget, DebugLoc dl) {
4340 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4341 LoadSDNode *LD = NULL;
4342 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4343 LD = dyn_cast<LoadSDNode>(SrcOp);
4345 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4347 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4348 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4349 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4350 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4351 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4353 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4354 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4355 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4356 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4364 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4365 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4366 DAG.getNode(ISD::BIT_CONVERT, dl,
4370 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4373 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4374 SDValue V1 = SVOp->getOperand(0);
4375 SDValue V2 = SVOp->getOperand(1);
4376 DebugLoc dl = SVOp->getDebugLoc();
4377 EVT VT = SVOp->getValueType(0);
4379 SmallVector<std::pair<int, int>, 8> Locs;
4381 SmallVector<int, 8> Mask1(4U, -1);
4382 SmallVector<int, 8> PermMask;
4383 SVOp->getMask(PermMask);
4387 for (unsigned i = 0; i != 4; ++i) {
4388 int Idx = PermMask[i];
4390 Locs[i] = std::make_pair(-1, -1);
4392 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4394 Locs[i] = std::make_pair(0, NumLo);
4398 Locs[i] = std::make_pair(1, NumHi);
4400 Mask1[2+NumHi] = Idx;
4406 if (NumLo <= 2 && NumHi <= 2) {
4407 // If no more than two elements come from either vector. This can be
4408 // implemented with two shuffles. First shuffle gather the elements.
4409 // The second shuffle, which takes the first shuffle as both of its
4410 // vector operands, put the elements into the right order.
4411 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4413 SmallVector<int, 8> Mask2(4U, -1);
4415 for (unsigned i = 0; i != 4; ++i) {
4416 if (Locs[i].first == -1)
4419 unsigned Idx = (i < 2) ? 0 : 4;
4420 Idx += Locs[i].first * 2 + Locs[i].second;
4425 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4426 } else if (NumLo == 3 || NumHi == 3) {
4427 // Otherwise, we must have three elements from one vector, call it X, and
4428 // one element from the other, call it Y. First, use a shufps to build an
4429 // intermediate vector with the one element from Y and the element from X
4430 // that will be in the same half in the final destination (the indexes don't
4431 // matter). Then, use a shufps to build the final vector, taking the half
4432 // containing the element from Y from the intermediate, and the other half
4435 // Normalize it so the 3 elements come from V1.
4436 CommuteVectorShuffleMask(PermMask, VT);
4440 // Find the element from V2.
4442 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4443 int Val = PermMask[HiIndex];
4450 Mask1[0] = PermMask[HiIndex];
4452 Mask1[2] = PermMask[HiIndex^1];
4454 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4457 Mask1[0] = PermMask[0];
4458 Mask1[1] = PermMask[1];
4459 Mask1[2] = HiIndex & 1 ? 6 : 4;
4460 Mask1[3] = HiIndex & 1 ? 4 : 6;
4461 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4463 Mask1[0] = HiIndex & 1 ? 2 : 0;
4464 Mask1[1] = HiIndex & 1 ? 0 : 2;
4465 Mask1[2] = PermMask[2];
4466 Mask1[3] = PermMask[3];
4471 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4475 // Break it into (shuffle shuffle_hi, shuffle_lo).
4477 SmallVector<int,8> LoMask(4U, -1);
4478 SmallVector<int,8> HiMask(4U, -1);
4480 SmallVector<int,8> *MaskPtr = &LoMask;
4481 unsigned MaskIdx = 0;
4484 for (unsigned i = 0; i != 4; ++i) {
4491 int Idx = PermMask[i];
4493 Locs[i] = std::make_pair(-1, -1);
4494 } else if (Idx < 4) {
4495 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4496 (*MaskPtr)[LoIdx] = Idx;
4499 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4500 (*MaskPtr)[HiIdx] = Idx;
4505 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4506 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4507 SmallVector<int, 8> MaskOps;
4508 for (unsigned i = 0; i != 4; ++i) {
4509 if (Locs[i].first == -1) {
4510 MaskOps.push_back(-1);
4512 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4513 MaskOps.push_back(Idx);
4516 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4520 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4521 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4522 SDValue V1 = Op.getOperand(0);
4523 SDValue V2 = Op.getOperand(1);
4524 EVT VT = Op.getValueType();
4525 DebugLoc dl = Op.getDebugLoc();
4526 unsigned NumElems = VT.getVectorNumElements();
4527 bool isMMX = VT.getSizeInBits() == 64;
4528 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4529 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4530 bool V1IsSplat = false;
4531 bool V2IsSplat = false;
4533 if (isZeroShuffle(SVOp))
4534 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4536 // Promote splats to v4f32.
4537 if (SVOp->isSplat()) {
4538 if (isMMX || NumElems < 4)
4540 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4543 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4545 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4546 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4547 if (NewOp.getNode())
4548 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4549 LowerVECTOR_SHUFFLE(NewOp, DAG));
4550 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4551 // FIXME: Figure out a cleaner way to do this.
4552 // Try to make use of movq to zero out the top part.
4553 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4554 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4555 if (NewOp.getNode()) {
4556 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4557 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4558 DAG, Subtarget, dl);
4560 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4561 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4562 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4563 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4564 DAG, Subtarget, dl);
4568 if (X86::isPSHUFDMask(SVOp))
4571 // Check if this can be converted into a logical shift.
4572 bool isLeft = false;
4575 bool isShift = getSubtarget()->hasSSE2() &&
4576 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4577 if (isShift && ShVal.hasOneUse()) {
4578 // If the shifted value has multiple uses, it may be cheaper to use
4579 // v_set0 + movlhps or movhlps, etc.
4580 EVT EltVT = VT.getVectorElementType();
4581 ShAmt *= EltVT.getSizeInBits();
4582 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4585 if (X86::isMOVLMask(SVOp)) {
4588 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4589 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4594 // FIXME: fold these into legal mask.
4595 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4596 X86::isMOVSLDUPMask(SVOp) ||
4597 X86::isMOVHLPSMask(SVOp) ||
4598 X86::isMOVLHPSMask(SVOp) ||
4599 X86::isMOVLPMask(SVOp)))
4602 if (ShouldXformToMOVHLPS(SVOp) ||
4603 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4604 return CommuteVectorShuffle(SVOp, DAG);
4607 // No better options. Use a vshl / vsrl.
4608 EVT EltVT = VT.getVectorElementType();
4609 ShAmt *= EltVT.getSizeInBits();
4610 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4613 bool Commuted = false;
4614 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4615 // 1,1,1,1 -> v8i16 though.
4616 V1IsSplat = isSplatVector(V1.getNode());
4617 V2IsSplat = isSplatVector(V2.getNode());
4619 // Canonicalize the splat or undef, if present, to be on the RHS.
4620 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4621 Op = CommuteVectorShuffle(SVOp, DAG);
4622 SVOp = cast<ShuffleVectorSDNode>(Op);
4623 V1 = SVOp->getOperand(0);
4624 V2 = SVOp->getOperand(1);
4625 std::swap(V1IsSplat, V2IsSplat);
4626 std::swap(V1IsUndef, V2IsUndef);
4630 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4631 // Shuffling low element of v1 into undef, just return v1.
4634 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4635 // the instruction selector will not match, so get a canonical MOVL with
4636 // swapped operands to undo the commute.
4637 return getMOVL(DAG, dl, VT, V2, V1);
4640 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4641 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4642 X86::isUNPCKLMask(SVOp) ||
4643 X86::isUNPCKHMask(SVOp))
4647 // Normalize mask so all entries that point to V2 points to its first
4648 // element then try to match unpck{h|l} again. If match, return a
4649 // new vector_shuffle with the corrected mask.
4650 SDValue NewMask = NormalizeMask(SVOp, DAG);
4651 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4652 if (NSVOp != SVOp) {
4653 if (X86::isUNPCKLMask(NSVOp, true)) {
4655 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4662 // Commute is back and try unpck* again.
4663 // FIXME: this seems wrong.
4664 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4665 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4666 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4667 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4668 X86::isUNPCKLMask(NewSVOp) ||
4669 X86::isUNPCKHMask(NewSVOp))
4673 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4675 // Normalize the node to match x86 shuffle ops if needed
4676 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4677 return CommuteVectorShuffle(SVOp, DAG);
4679 // Check for legal shuffle and return?
4680 SmallVector<int, 16> PermMask;
4681 SVOp->getMask(PermMask);
4682 if (isShuffleMaskLegal(PermMask, VT))
4685 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4686 if (VT == MVT::v8i16) {
4687 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4688 if (NewOp.getNode())
4692 if (VT == MVT::v16i8) {
4693 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4694 if (NewOp.getNode())
4698 // Handle all 4 wide cases with a number of shuffles except for MMX.
4699 if (NumElems == 4 && !isMMX)
4700 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4706 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4707 SelectionDAG &DAG) {
4708 EVT VT = Op.getValueType();
4709 DebugLoc dl = Op.getDebugLoc();
4710 if (VT.getSizeInBits() == 8) {
4711 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4712 Op.getOperand(0), Op.getOperand(1));
4713 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4714 DAG.getValueType(VT));
4715 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4716 } else if (VT.getSizeInBits() == 16) {
4717 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4718 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4720 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4721 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4722 DAG.getNode(ISD::BIT_CONVERT, dl,
4726 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4727 Op.getOperand(0), Op.getOperand(1));
4728 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4729 DAG.getValueType(VT));
4730 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4731 } else if (VT == MVT::f32) {
4732 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4733 // the result back to FR32 register. It's only worth matching if the
4734 // result has a single use which is a store or a bitcast to i32. And in
4735 // the case of a store, it's not worth it if the index is a constant 0,
4736 // because a MOVSSmr can be used instead, which is smaller and faster.
4737 if (!Op.hasOneUse())
4739 SDNode *User = *Op.getNode()->use_begin();
4740 if ((User->getOpcode() != ISD::STORE ||
4741 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4742 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4743 (User->getOpcode() != ISD::BIT_CONVERT ||
4744 User->getValueType(0) != MVT::i32))
4746 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4747 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4750 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4751 } else if (VT == MVT::i32) {
4752 // ExtractPS works with constant index.
4753 if (isa<ConstantSDNode>(Op.getOperand(1)))
4761 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4762 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4765 if (Subtarget->hasSSE41()) {
4766 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4771 EVT VT = Op.getValueType();
4772 DebugLoc dl = Op.getDebugLoc();
4773 // TODO: handle v16i8.
4774 if (VT.getSizeInBits() == 16) {
4775 SDValue Vec = Op.getOperand(0);
4776 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4778 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4779 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4780 DAG.getNode(ISD::BIT_CONVERT, dl,
4783 // Transform it so it match pextrw which produces a 32-bit result.
4784 EVT EltVT = MVT::i32;
4785 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4786 Op.getOperand(0), Op.getOperand(1));
4787 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4788 DAG.getValueType(VT));
4789 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4790 } else if (VT.getSizeInBits() == 32) {
4791 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4795 // SHUFPS the element to the lowest double word, then movss.
4796 int Mask[4] = { Idx, -1, -1, -1 };
4797 EVT VVT = Op.getOperand(0).getValueType();
4798 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4799 DAG.getUNDEF(VVT), Mask);
4800 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4801 DAG.getIntPtrConstant(0));
4802 } else if (VT.getSizeInBits() == 64) {
4803 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4804 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4805 // to match extract_elt for f64.
4806 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4810 // UNPCKHPD the element to the lowest double word, then movsd.
4811 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4812 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4813 int Mask[2] = { 1, -1 };
4814 EVT VVT = Op.getOperand(0).getValueType();
4815 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4816 DAG.getUNDEF(VVT), Mask);
4817 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4818 DAG.getIntPtrConstant(0));
4825 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4826 EVT VT = Op.getValueType();
4827 EVT EltVT = VT.getVectorElementType();
4828 DebugLoc dl = Op.getDebugLoc();
4830 SDValue N0 = Op.getOperand(0);
4831 SDValue N1 = Op.getOperand(1);
4832 SDValue N2 = Op.getOperand(2);
4834 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4835 isa<ConstantSDNode>(N2)) {
4836 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4838 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4840 if (N1.getValueType() != MVT::i32)
4841 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4842 if (N2.getValueType() != MVT::i32)
4843 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4844 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4845 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4846 // Bits [7:6] of the constant are the source select. This will always be
4847 // zero here. The DAG Combiner may combine an extract_elt index into these
4848 // bits. For example (insert (extract, 3), 2) could be matched by putting
4849 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4850 // Bits [5:4] of the constant are the destination select. This is the
4851 // value of the incoming immediate.
4852 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4853 // combine either bitwise AND or insert of float 0.0 to set these bits.
4854 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4855 // Create this as a scalar to vector..
4856 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4857 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4858 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4859 // PINSR* works with constant index.
4866 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4867 EVT VT = Op.getValueType();
4868 EVT EltVT = VT.getVectorElementType();
4870 if (Subtarget->hasSSE41())
4871 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4873 if (EltVT == MVT::i8)
4876 DebugLoc dl = Op.getDebugLoc();
4877 SDValue N0 = Op.getOperand(0);
4878 SDValue N1 = Op.getOperand(1);
4879 SDValue N2 = Op.getOperand(2);
4881 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4882 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4883 // as its second argument.
4884 if (N1.getValueType() != MVT::i32)
4885 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4886 if (N2.getValueType() != MVT::i32)
4887 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4888 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4894 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4895 DebugLoc dl = Op.getDebugLoc();
4896 if (Op.getValueType() == MVT::v2f32)
4897 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4899 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4900 Op.getOperand(0))));
4902 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4903 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4905 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4906 EVT VT = MVT::v2i32;
4907 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4914 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4915 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4918 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4919 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4920 // one of the above mentioned nodes. It has to be wrapped because otherwise
4921 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4922 // be used to form addressing mode. These wrapped nodes will be selected
4925 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4926 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4928 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4930 unsigned char OpFlag = 0;
4931 unsigned WrapperKind = X86ISD::Wrapper;
4932 CodeModel::Model M = getTargetMachine().getCodeModel();
4934 if (Subtarget->isPICStyleRIPRel() &&
4935 (M == CodeModel::Small || M == CodeModel::Kernel))
4936 WrapperKind = X86ISD::WrapperRIP;
4937 else if (Subtarget->isPICStyleGOT())
4938 OpFlag = X86II::MO_GOTOFF;
4939 else if (Subtarget->isPICStyleStubPIC())
4940 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4942 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4944 CP->getOffset(), OpFlag);
4945 DebugLoc DL = CP->getDebugLoc();
4946 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4947 // With PIC, the address is actually $g + Offset.
4949 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4950 DAG.getNode(X86ISD::GlobalBaseReg,
4951 DebugLoc::getUnknownLoc(), getPointerTy()),
4958 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4959 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4961 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4963 unsigned char OpFlag = 0;
4964 unsigned WrapperKind = X86ISD::Wrapper;
4965 CodeModel::Model M = getTargetMachine().getCodeModel();
4967 if (Subtarget->isPICStyleRIPRel() &&
4968 (M == CodeModel::Small || M == CodeModel::Kernel))
4969 WrapperKind = X86ISD::WrapperRIP;
4970 else if (Subtarget->isPICStyleGOT())
4971 OpFlag = X86II::MO_GOTOFF;
4972 else if (Subtarget->isPICStyleStubPIC())
4973 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4975 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4977 DebugLoc DL = JT->getDebugLoc();
4978 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4980 // With PIC, the address is actually $g + Offset.
4982 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4983 DAG.getNode(X86ISD::GlobalBaseReg,
4984 DebugLoc::getUnknownLoc(), getPointerTy()),
4992 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4993 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4995 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4997 unsigned char OpFlag = 0;
4998 unsigned WrapperKind = X86ISD::Wrapper;
4999 CodeModel::Model M = getTargetMachine().getCodeModel();
5001 if (Subtarget->isPICStyleRIPRel() &&
5002 (M == CodeModel::Small || M == CodeModel::Kernel))
5003 WrapperKind = X86ISD::WrapperRIP;
5004 else if (Subtarget->isPICStyleGOT())
5005 OpFlag = X86II::MO_GOTOFF;
5006 else if (Subtarget->isPICStyleStubPIC())
5007 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5009 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5011 DebugLoc DL = Op.getDebugLoc();
5012 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5015 // With PIC, the address is actually $g + Offset.
5016 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5017 !Subtarget->is64Bit()) {
5018 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5019 DAG.getNode(X86ISD::GlobalBaseReg,
5020 DebugLoc::getUnknownLoc(),
5029 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
5030 // Create the TargetBlockAddressAddress node.
5031 unsigned char OpFlags =
5032 Subtarget->ClassifyBlockAddressReference();
5033 CodeModel::Model M = getTargetMachine().getCodeModel();
5034 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5035 DebugLoc dl = Op.getDebugLoc();
5036 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5037 /*isTarget=*/true, OpFlags);
5039 if (Subtarget->isPICStyleRIPRel() &&
5040 (M == CodeModel::Small || M == CodeModel::Kernel))
5041 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5043 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5045 // With PIC, the address is actually $g + Offset.
5046 if (isGlobalRelativeToPICBase(OpFlags)) {
5047 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5048 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5056 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5058 SelectionDAG &DAG) const {
5059 // Create the TargetGlobalAddress node, folding in the constant
5060 // offset if it is legal.
5061 unsigned char OpFlags =
5062 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5063 CodeModel::Model M = getTargetMachine().getCodeModel();
5065 if (OpFlags == X86II::MO_NO_FLAG &&
5066 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5067 // A direct static reference to a global.
5068 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5071 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5074 if (Subtarget->isPICStyleRIPRel() &&
5075 (M == CodeModel::Small || M == CodeModel::Kernel))
5076 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5078 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5080 // With PIC, the address is actually $g + Offset.
5081 if (isGlobalRelativeToPICBase(OpFlags)) {
5082 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5083 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5087 // For globals that require a load from a stub to get the address, emit the
5089 if (isGlobalStubReference(OpFlags))
5090 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5091 PseudoSourceValue::getGOT(), 0);
5093 // If there was a non-zero offset that we didn't fold, create an explicit
5096 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5097 DAG.getConstant(Offset, getPointerTy()));
5103 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
5104 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5105 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5106 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5110 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5111 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5112 unsigned char OperandFlags) {
5113 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5114 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5115 DebugLoc dl = GA->getDebugLoc();
5116 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5117 GA->getValueType(0),
5121 SDValue Ops[] = { Chain, TGA, *InFlag };
5122 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5124 SDValue Ops[] = { Chain, TGA };
5125 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5128 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5129 MFI->setHasCalls(true);
5131 SDValue Flag = Chain.getValue(1);
5132 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5135 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5137 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5140 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5141 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5142 DAG.getNode(X86ISD::GlobalBaseReg,
5143 DebugLoc::getUnknownLoc(),
5145 InFlag = Chain.getValue(1);
5147 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5150 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5152 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5154 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5155 X86::RAX, X86II::MO_TLSGD);
5158 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5159 // "local exec" model.
5160 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5161 const EVT PtrVT, TLSModel::Model model,
5163 DebugLoc dl = GA->getDebugLoc();
5164 // Get the Thread Pointer
5165 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5166 DebugLoc::getUnknownLoc(), PtrVT,
5167 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5170 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5173 unsigned char OperandFlags = 0;
5174 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5176 unsigned WrapperKind = X86ISD::Wrapper;
5177 if (model == TLSModel::LocalExec) {
5178 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5179 } else if (is64Bit) {
5180 assert(model == TLSModel::InitialExec);
5181 OperandFlags = X86II::MO_GOTTPOFF;
5182 WrapperKind = X86ISD::WrapperRIP;
5184 assert(model == TLSModel::InitialExec);
5185 OperandFlags = X86II::MO_INDNTPOFF;
5188 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5190 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5191 GA->getOffset(), OperandFlags);
5192 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5194 if (model == TLSModel::InitialExec)
5195 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5196 PseudoSourceValue::getGOT(), 0);
5198 // The address of the thread local variable is the add of the thread
5199 // pointer with the offset of the variable.
5200 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5204 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5205 // TODO: implement the "local dynamic" model
5206 // TODO: implement the "initial exec"model for pic executables
5207 assert(Subtarget->isTargetELF() &&
5208 "TLS not implemented for non-ELF targets");
5209 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5210 const GlobalValue *GV = GA->getGlobal();
5212 // If GV is an alias then use the aliasee for determining
5213 // thread-localness.
5214 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5215 GV = GA->resolveAliasedGlobal(false);
5217 TLSModel::Model model = getTLSModel(GV,
5218 getTargetMachine().getRelocationModel());
5221 case TLSModel::GeneralDynamic:
5222 case TLSModel::LocalDynamic: // not implemented
5223 if (Subtarget->is64Bit())
5224 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5225 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5227 case TLSModel::InitialExec:
5228 case TLSModel::LocalExec:
5229 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5230 Subtarget->is64Bit());
5233 llvm_unreachable("Unreachable");
5238 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5239 /// take a 2 x i32 value to shift plus a shift amount.
5240 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5241 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5242 EVT VT = Op.getValueType();
5243 unsigned VTBits = VT.getSizeInBits();
5244 DebugLoc dl = Op.getDebugLoc();
5245 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5246 SDValue ShOpLo = Op.getOperand(0);
5247 SDValue ShOpHi = Op.getOperand(1);
5248 SDValue ShAmt = Op.getOperand(2);
5249 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5250 DAG.getConstant(VTBits - 1, MVT::i8))
5251 : DAG.getConstant(0, VT);
5254 if (Op.getOpcode() == ISD::SHL_PARTS) {
5255 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5256 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5258 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5259 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5262 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5263 DAG.getConstant(VTBits, MVT::i8));
5264 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5265 AndNode, DAG.getConstant(0, MVT::i8));
5268 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5269 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5270 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5272 if (Op.getOpcode() == ISD::SHL_PARTS) {
5273 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5274 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5276 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5277 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5280 SDValue Ops[2] = { Lo, Hi };
5281 return DAG.getMergeValues(Ops, 2, dl);
5284 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5285 EVT SrcVT = Op.getOperand(0).getValueType();
5287 if (SrcVT.isVector()) {
5288 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5294 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5295 "Unknown SINT_TO_FP to lower!");
5297 // These are really Legal; return the operand so the caller accepts it as
5299 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5301 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5302 Subtarget->is64Bit()) {
5306 DebugLoc dl = Op.getDebugLoc();
5307 unsigned Size = SrcVT.getSizeInBits()/8;
5308 MachineFunction &MF = DAG.getMachineFunction();
5309 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5310 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5311 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5313 PseudoSourceValue::getFixedStack(SSFI), 0);
5314 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5317 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5319 SelectionDAG &DAG) {
5321 DebugLoc dl = Op.getDebugLoc();
5323 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5325 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5327 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5328 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5329 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5330 Tys, Ops, array_lengthof(Ops));
5333 Chain = Result.getValue(1);
5334 SDValue InFlag = Result.getValue(2);
5336 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5337 // shouldn't be necessary except that RFP cannot be live across
5338 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5339 MachineFunction &MF = DAG.getMachineFunction();
5340 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5341 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5342 Tys = DAG.getVTList(MVT::Other);
5344 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5346 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5347 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5348 PseudoSourceValue::getFixedStack(SSFI), 0);
5354 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5355 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5356 // This algorithm is not obvious. Here it is in C code, more or less:
5358 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5359 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5360 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5362 // Copy ints to xmm registers.
5363 __m128i xh = _mm_cvtsi32_si128( hi );
5364 __m128i xl = _mm_cvtsi32_si128( lo );
5366 // Combine into low half of a single xmm register.
5367 __m128i x = _mm_unpacklo_epi32( xh, xl );
5371 // Merge in appropriate exponents to give the integer bits the right
5373 x = _mm_unpacklo_epi32( x, exp );
5375 // Subtract away the biases to deal with the IEEE-754 double precision
5377 d = _mm_sub_pd( (__m128d) x, bias );
5379 // All conversions up to here are exact. The correctly rounded result is
5380 // calculated using the current rounding mode using the following
5382 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5383 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5384 // store doesn't really need to be here (except
5385 // maybe to zero the other double)
5390 DebugLoc dl = Op.getDebugLoc();
5391 LLVMContext *Context = DAG.getContext();
5393 // Build some magic constants.
5394 std::vector<Constant*> CV0;
5395 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5396 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5397 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5398 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5399 Constant *C0 = ConstantVector::get(CV0);
5400 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5402 std::vector<Constant*> CV1;
5404 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5406 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5407 Constant *C1 = ConstantVector::get(CV1);
5408 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5410 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5411 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5413 DAG.getIntPtrConstant(1)));
5414 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5415 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5417 DAG.getIntPtrConstant(0)));
5418 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5419 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5420 PseudoSourceValue::getConstantPool(), 0,
5422 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5423 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5424 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5425 PseudoSourceValue::getConstantPool(), 0,
5427 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5429 // Add the halves; easiest way is to swap them into another reg first.
5430 int ShufMask[2] = { 1, -1 };
5431 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5432 DAG.getUNDEF(MVT::v2f64), ShufMask);
5433 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5434 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5435 DAG.getIntPtrConstant(0));
5438 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5439 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5440 DebugLoc dl = Op.getDebugLoc();
5441 // FP constant to bias correct the final result.
5442 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5445 // Load the 32-bit value into an XMM register.
5446 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5447 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5449 DAG.getIntPtrConstant(0)));
5451 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5452 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5453 DAG.getIntPtrConstant(0));
5455 // Or the load with the bias.
5456 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5457 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5458 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5460 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5461 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5462 MVT::v2f64, Bias)));
5463 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5464 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5465 DAG.getIntPtrConstant(0));
5467 // Subtract the bias.
5468 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5470 // Handle final rounding.
5471 EVT DestVT = Op.getValueType();
5473 if (DestVT.bitsLT(MVT::f64)) {
5474 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5475 DAG.getIntPtrConstant(0));
5476 } else if (DestVT.bitsGT(MVT::f64)) {
5477 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5480 // Handle final rounding.
5484 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5485 SDValue N0 = Op.getOperand(0);
5486 DebugLoc dl = Op.getDebugLoc();
5488 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5489 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5490 // the optimization here.
5491 if (DAG.SignBitIsZero(N0))
5492 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5494 EVT SrcVT = N0.getValueType();
5495 if (SrcVT == MVT::i64) {
5496 // We only handle SSE2 f64 target here; caller can expand the rest.
5497 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5500 return LowerUINT_TO_FP_i64(Op, DAG);
5501 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5502 return LowerUINT_TO_FP_i32(Op, DAG);
5505 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5507 // Make a 64-bit buffer, and use it to build an FILD.
5508 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5509 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5510 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5511 getPointerTy(), StackSlot, WordOff);
5512 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5513 StackSlot, NULL, 0);
5514 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5515 OffsetSlot, NULL, 0);
5516 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5519 std::pair<SDValue,SDValue> X86TargetLowering::
5520 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5521 DebugLoc dl = Op.getDebugLoc();
5523 EVT DstTy = Op.getValueType();
5526 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5530 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5531 DstTy.getSimpleVT() >= MVT::i16 &&
5532 "Unknown FP_TO_SINT to lower!");
5534 // These are really Legal.
5535 if (DstTy == MVT::i32 &&
5536 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5537 return std::make_pair(SDValue(), SDValue());
5538 if (Subtarget->is64Bit() &&
5539 DstTy == MVT::i64 &&
5540 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5541 return std::make_pair(SDValue(), SDValue());
5543 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5545 MachineFunction &MF = DAG.getMachineFunction();
5546 unsigned MemSize = DstTy.getSizeInBits()/8;
5547 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5548 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5551 switch (DstTy.getSimpleVT().SimpleTy) {
5552 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5553 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5554 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5555 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5558 SDValue Chain = DAG.getEntryNode();
5559 SDValue Value = Op.getOperand(0);
5560 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5561 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5562 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5563 PseudoSourceValue::getFixedStack(SSFI), 0);
5564 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5566 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5568 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5569 Chain = Value.getValue(1);
5570 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5571 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5574 // Build the FP_TO_INT*_IN_MEM
5575 SDValue Ops[] = { Chain, Value, StackSlot };
5576 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5578 return std::make_pair(FIST, StackSlot);
5581 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5582 if (Op.getValueType().isVector()) {
5583 if (Op.getValueType() == MVT::v2i32 &&
5584 Op.getOperand(0).getValueType() == MVT::v2f64) {
5590 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5591 SDValue FIST = Vals.first, StackSlot = Vals.second;
5592 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5593 if (FIST.getNode() == 0) return Op;
5596 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5597 FIST, StackSlot, NULL, 0);
5600 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5601 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5602 SDValue FIST = Vals.first, StackSlot = Vals.second;
5603 assert(FIST.getNode() && "Unexpected failure");
5606 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5607 FIST, StackSlot, NULL, 0);
5610 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5611 LLVMContext *Context = DAG.getContext();
5612 DebugLoc dl = Op.getDebugLoc();
5613 EVT VT = Op.getValueType();
5616 EltVT = VT.getVectorElementType();
5617 std::vector<Constant*> CV;
5618 if (EltVT == MVT::f64) {
5619 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5623 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5629 Constant *C = ConstantVector::get(CV);
5630 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5631 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5632 PseudoSourceValue::getConstantPool(), 0,
5634 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5637 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5638 LLVMContext *Context = DAG.getContext();
5639 DebugLoc dl = Op.getDebugLoc();
5640 EVT VT = Op.getValueType();
5643 EltVT = VT.getVectorElementType();
5644 std::vector<Constant*> CV;
5645 if (EltVT == MVT::f64) {
5646 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5650 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5656 Constant *C = ConstantVector::get(CV);
5657 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5658 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5659 PseudoSourceValue::getConstantPool(), 0,
5661 if (VT.isVector()) {
5662 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5663 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5664 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5666 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5668 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5672 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5673 LLVMContext *Context = DAG.getContext();
5674 SDValue Op0 = Op.getOperand(0);
5675 SDValue Op1 = Op.getOperand(1);
5676 DebugLoc dl = Op.getDebugLoc();
5677 EVT VT = Op.getValueType();
5678 EVT SrcVT = Op1.getValueType();
5680 // If second operand is smaller, extend it first.
5681 if (SrcVT.bitsLT(VT)) {
5682 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5685 // And if it is bigger, shrink it first.
5686 if (SrcVT.bitsGT(VT)) {
5687 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5691 // At this point the operands and the result should have the same
5692 // type, and that won't be f80 since that is not custom lowered.
5694 // First get the sign bit of second operand.
5695 std::vector<Constant*> CV;
5696 if (SrcVT == MVT::f64) {
5697 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5698 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5700 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5701 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5702 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5703 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5705 Constant *C = ConstantVector::get(CV);
5706 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5707 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5708 PseudoSourceValue::getConstantPool(), 0,
5710 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5712 // Shift sign bit right or left if the two operands have different types.
5713 if (SrcVT.bitsGT(VT)) {
5714 // Op0 is MVT::f32, Op1 is MVT::f64.
5715 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5716 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5717 DAG.getConstant(32, MVT::i32));
5718 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5719 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5720 DAG.getIntPtrConstant(0));
5723 // Clear first operand sign bit.
5725 if (VT == MVT::f64) {
5726 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5727 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5729 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5730 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5731 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5732 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5734 C = ConstantVector::get(CV);
5735 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5736 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5737 PseudoSourceValue::getConstantPool(), 0,
5739 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5741 // Or the value with the sign bit.
5742 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5745 /// Emit nodes that will be selected as "test Op0,Op0", or something
5747 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5748 SelectionDAG &DAG) {
5749 DebugLoc dl = Op.getDebugLoc();
5751 // CF and OF aren't always set the way we want. Determine which
5752 // of these we need.
5753 bool NeedCF = false;
5754 bool NeedOF = false;
5756 case X86::COND_A: case X86::COND_AE:
5757 case X86::COND_B: case X86::COND_BE:
5760 case X86::COND_G: case X86::COND_GE:
5761 case X86::COND_L: case X86::COND_LE:
5762 case X86::COND_O: case X86::COND_NO:
5768 // See if we can use the EFLAGS value from the operand instead of
5769 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5770 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5771 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5772 unsigned Opcode = 0;
5773 unsigned NumOperands = 0;
5774 switch (Op.getNode()->getOpcode()) {
5776 // Due to an isel shortcoming, be conservative if this add is likely to
5777 // be selected as part of a load-modify-store instruction. When the root
5778 // node in a match is a store, isel doesn't know how to remap non-chain
5779 // non-flag uses of other nodes in the match, such as the ADD in this
5780 // case. This leads to the ADD being left around and reselected, with
5781 // the result being two adds in the output.
5782 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5783 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5784 if (UI->getOpcode() == ISD::STORE)
5786 if (ConstantSDNode *C =
5787 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5788 // An add of one will be selected as an INC.
5789 if (C->getAPIntValue() == 1) {
5790 Opcode = X86ISD::INC;
5794 // An add of negative one (subtract of one) will be selected as a DEC.
5795 if (C->getAPIntValue().isAllOnesValue()) {
5796 Opcode = X86ISD::DEC;
5801 // Otherwise use a regular EFLAGS-setting add.
5802 Opcode = X86ISD::ADD;
5806 // If the primary and result isn't used, don't bother using X86ISD::AND,
5807 // because a TEST instruction will be better.
5808 bool NonFlagUse = false;
5809 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5810 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
5812 unsigned UOpNo = UI.getOperandNo();
5813 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
5814 // Look pass truncate.
5815 UOpNo = User->use_begin().getOperandNo();
5816 User = *User->use_begin();
5818 if (User->getOpcode() != ISD::BRCOND &&
5819 User->getOpcode() != ISD::SETCC &&
5820 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
5832 // Due to the ISEL shortcoming noted above, be conservative if this op is
5833 // likely to be selected as part of a load-modify-store instruction.
5834 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5835 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5836 if (UI->getOpcode() == ISD::STORE)
5838 // Otherwise use a regular EFLAGS-setting instruction.
5839 switch (Op.getNode()->getOpcode()) {
5840 case ISD::SUB: Opcode = X86ISD::SUB; break;
5841 case ISD::OR: Opcode = X86ISD::OR; break;
5842 case ISD::XOR: Opcode = X86ISD::XOR; break;
5843 case ISD::AND: Opcode = X86ISD::AND; break;
5844 default: llvm_unreachable("unexpected operator!");
5855 return SDValue(Op.getNode(), 1);
5861 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5862 SmallVector<SDValue, 4> Ops;
5863 for (unsigned i = 0; i != NumOperands; ++i)
5864 Ops.push_back(Op.getOperand(i));
5865 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5866 DAG.ReplaceAllUsesWith(Op, New);
5867 return SDValue(New.getNode(), 1);
5871 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5872 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5873 DAG.getConstant(0, Op.getValueType()));
5876 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5878 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5879 SelectionDAG &DAG) {
5880 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5881 if (C->getAPIntValue() == 0)
5882 return EmitTest(Op0, X86CC, DAG);
5884 DebugLoc dl = Op0.getDebugLoc();
5885 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5888 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
5889 /// if it's possible.
5890 static SDValue LowerToBT(SDValue Op0, ISD::CondCode CC,
5891 DebugLoc dl, SelectionDAG &DAG) {
5893 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5894 if (ConstantSDNode *Op010C =
5895 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5896 if (Op010C->getZExtValue() == 1) {
5897 LHS = Op0.getOperand(0);
5898 RHS = Op0.getOperand(1).getOperand(1);
5900 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5901 if (ConstantSDNode *Op000C =
5902 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5903 if (Op000C->getZExtValue() == 1) {
5904 LHS = Op0.getOperand(1);
5905 RHS = Op0.getOperand(0).getOperand(1);
5907 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5908 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5909 SDValue AndLHS = Op0.getOperand(0);
5910 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5911 LHS = AndLHS.getOperand(0);
5912 RHS = AndLHS.getOperand(1);
5916 if (LHS.getNode()) {
5917 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5918 // instruction. Since the shift amount is in-range-or-undefined, we know
5919 // that doing a bittest on the i16 value is ok. We extend to i32 because
5920 // the encoding for the i16 version is larger than the i32 version.
5921 if (LHS.getValueType() == MVT::i8)
5922 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5924 // If the operand types disagree, extend the shift amount to match. Since
5925 // BT ignores high bits (like shifts) we can use anyextend.
5926 if (LHS.getValueType() != RHS.getValueType())
5927 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5929 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5930 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5931 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5932 DAG.getConstant(Cond, MVT::i8), BT);
5938 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5939 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5940 SDValue Op0 = Op.getOperand(0);
5941 SDValue Op1 = Op.getOperand(1);
5942 DebugLoc dl = Op.getDebugLoc();
5943 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5945 // Optimize to BT if possible.
5946 // Lower (X & (1 << N)) == 0 to BT(X, N).
5947 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5948 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5949 if (Op0.getOpcode() == ISD::AND &&
5951 Op1.getOpcode() == ISD::Constant &&
5952 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5953 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5954 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
5955 if (NewSetCC.getNode())
5959 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5960 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5961 if (X86CC == X86::COND_INVALID)
5964 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5966 // Use sbb x, x to materialize carry bit into a GPR.
5967 if (X86CC == X86::COND_B)
5968 return DAG.getNode(ISD::AND, dl, MVT::i8,
5969 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5970 DAG.getConstant(X86CC, MVT::i8), Cond),
5971 DAG.getConstant(1, MVT::i8));
5973 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5974 DAG.getConstant(X86CC, MVT::i8), Cond);
5977 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5979 SDValue Op0 = Op.getOperand(0);
5980 SDValue Op1 = Op.getOperand(1);
5981 SDValue CC = Op.getOperand(2);
5982 EVT VT = Op.getValueType();
5983 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5984 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5985 DebugLoc dl = Op.getDebugLoc();
5989 EVT VT0 = Op0.getValueType();
5990 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5991 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5994 switch (SetCCOpcode) {
5997 case ISD::SETEQ: SSECC = 0; break;
5999 case ISD::SETGT: Swap = true; // Fallthrough
6001 case ISD::SETOLT: SSECC = 1; break;
6003 case ISD::SETGE: Swap = true; // Fallthrough
6005 case ISD::SETOLE: SSECC = 2; break;
6006 case ISD::SETUO: SSECC = 3; break;
6008 case ISD::SETNE: SSECC = 4; break;
6009 case ISD::SETULE: Swap = true;
6010 case ISD::SETUGE: SSECC = 5; break;
6011 case ISD::SETULT: Swap = true;
6012 case ISD::SETUGT: SSECC = 6; break;
6013 case ISD::SETO: SSECC = 7; break;
6016 std::swap(Op0, Op1);
6018 // In the two special cases we can't handle, emit two comparisons.
6020 if (SetCCOpcode == ISD::SETUEQ) {
6022 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6023 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6024 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6026 else if (SetCCOpcode == ISD::SETONE) {
6028 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6029 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6030 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6032 llvm_unreachable("Illegal FP comparison");
6034 // Handle all other FP comparisons here.
6035 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6038 // We are handling one of the integer comparisons here. Since SSE only has
6039 // GT and EQ comparisons for integer, swapping operands and multiple
6040 // operations may be required for some comparisons.
6041 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6042 bool Swap = false, Invert = false, FlipSigns = false;
6044 switch (VT.getSimpleVT().SimpleTy) {
6047 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6049 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6051 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6052 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6055 switch (SetCCOpcode) {
6057 case ISD::SETNE: Invert = true;
6058 case ISD::SETEQ: Opc = EQOpc; break;
6059 case ISD::SETLT: Swap = true;
6060 case ISD::SETGT: Opc = GTOpc; break;
6061 case ISD::SETGE: Swap = true;
6062 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6063 case ISD::SETULT: Swap = true;
6064 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6065 case ISD::SETUGE: Swap = true;
6066 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6069 std::swap(Op0, Op1);
6071 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6072 // bits of the inputs before performing those operations.
6074 EVT EltVT = VT.getVectorElementType();
6075 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6077 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6078 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6080 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6081 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6084 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6086 // If the logical-not of the result is required, perform that now.
6088 Result = DAG.getNOT(dl, Result, VT);
6093 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6094 static bool isX86LogicalCmp(SDValue Op) {
6095 unsigned Opc = Op.getNode()->getOpcode();
6096 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6098 if (Op.getResNo() == 1 &&
6099 (Opc == X86ISD::ADD ||
6100 Opc == X86ISD::SUB ||
6101 Opc == X86ISD::SMUL ||
6102 Opc == X86ISD::UMUL ||
6103 Opc == X86ISD::INC ||
6104 Opc == X86ISD::DEC ||
6105 Opc == X86ISD::OR ||
6106 Opc == X86ISD::XOR ||
6107 Opc == X86ISD::AND))
6113 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
6114 bool addTest = true;
6115 SDValue Cond = Op.getOperand(0);
6116 DebugLoc dl = Op.getDebugLoc();
6119 if (Cond.getOpcode() == ISD::SETCC) {
6120 SDValue NewCond = LowerSETCC(Cond, DAG);
6121 if (NewCond.getNode())
6125 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6126 SDValue Op1 = Op.getOperand(1);
6127 SDValue Op2 = Op.getOperand(2);
6128 if (Cond.getOpcode() == X86ISD::SETCC &&
6129 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6130 SDValue Cmp = Cond.getOperand(1);
6131 if (Cmp.getOpcode() == X86ISD::CMP) {
6132 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6133 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6134 ConstantSDNode *RHSC =
6135 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6136 if (N1C && N1C->isAllOnesValue() &&
6137 N2C && N2C->isNullValue() &&
6138 RHSC && RHSC->isNullValue()) {
6139 SDValue CmpOp0 = Cmp.getOperand(0);
6140 Cmp = DAG.getNode(X86ISD::CMP, dl, CmpOp0.getValueType(),
6141 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6142 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6143 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6148 // Look pass (and (setcc_carry (cmp ...)), 1).
6149 if (Cond.getOpcode() == ISD::AND &&
6150 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6151 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6152 if (C && C->getAPIntValue() == 1)
6153 Cond = Cond.getOperand(0);
6156 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6157 // setting operand in place of the X86ISD::SETCC.
6158 if (Cond.getOpcode() == X86ISD::SETCC ||
6159 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6160 CC = Cond.getOperand(0);
6162 SDValue Cmp = Cond.getOperand(1);
6163 unsigned Opc = Cmp.getOpcode();
6164 EVT VT = Op.getValueType();
6166 bool IllegalFPCMov = false;
6167 if (VT.isFloatingPoint() && !VT.isVector() &&
6168 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6169 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6171 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6172 Opc == X86ISD::BT) { // FIXME
6179 // Look pass the truncate.
6180 if (Cond.getOpcode() == ISD::TRUNCATE)
6181 Cond = Cond.getOperand(0);
6183 // We know the result of AND is compared against zero. Try to match
6185 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6186 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6187 if (NewSetCC.getNode()) {
6188 CC = NewSetCC.getOperand(0);
6189 Cond = NewSetCC.getOperand(1);
6196 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6197 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6200 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6201 // condition is true.
6202 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6203 SDValue Ops[] = { Op2, Op1, CC, Cond };
6204 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6207 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6208 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6209 // from the AND / OR.
6210 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6211 Opc = Op.getOpcode();
6212 if (Opc != ISD::OR && Opc != ISD::AND)
6214 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6215 Op.getOperand(0).hasOneUse() &&
6216 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6217 Op.getOperand(1).hasOneUse());
6220 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6221 // 1 and that the SETCC node has a single use.
6222 static bool isXor1OfSetCC(SDValue Op) {
6223 if (Op.getOpcode() != ISD::XOR)
6225 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6226 if (N1C && N1C->getAPIntValue() == 1) {
6227 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6228 Op.getOperand(0).hasOneUse();
6233 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
6234 bool addTest = true;
6235 SDValue Chain = Op.getOperand(0);
6236 SDValue Cond = Op.getOperand(1);
6237 SDValue Dest = Op.getOperand(2);
6238 DebugLoc dl = Op.getDebugLoc();
6241 if (Cond.getOpcode() == ISD::SETCC) {
6242 SDValue NewCond = LowerSETCC(Cond, DAG);
6243 if (NewCond.getNode())
6247 // FIXME: LowerXALUO doesn't handle these!!
6248 else if (Cond.getOpcode() == X86ISD::ADD ||
6249 Cond.getOpcode() == X86ISD::SUB ||
6250 Cond.getOpcode() == X86ISD::SMUL ||
6251 Cond.getOpcode() == X86ISD::UMUL)
6252 Cond = LowerXALUO(Cond, DAG);
6255 // Look pass (and (setcc_carry (cmp ...)), 1).
6256 if (Cond.getOpcode() == ISD::AND &&
6257 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6259 if (C && C->getAPIntValue() == 1)
6260 Cond = Cond.getOperand(0);
6263 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6264 // setting operand in place of the X86ISD::SETCC.
6265 if (Cond.getOpcode() == X86ISD::SETCC ||
6266 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6267 CC = Cond.getOperand(0);
6269 SDValue Cmp = Cond.getOperand(1);
6270 unsigned Opc = Cmp.getOpcode();
6271 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6272 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6276 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6280 // These can only come from an arithmetic instruction with overflow,
6281 // e.g. SADDO, UADDO.
6282 Cond = Cond.getNode()->getOperand(1);
6289 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6290 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6291 if (CondOpc == ISD::OR) {
6292 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6293 // two branches instead of an explicit OR instruction with a
6295 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6296 isX86LogicalCmp(Cmp)) {
6297 CC = Cond.getOperand(0).getOperand(0);
6298 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6299 Chain, Dest, CC, Cmp);
6300 CC = Cond.getOperand(1).getOperand(0);
6304 } else { // ISD::AND
6305 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6306 // two branches instead of an explicit AND instruction with a
6307 // separate test. However, we only do this if this block doesn't
6308 // have a fall-through edge, because this requires an explicit
6309 // jmp when the condition is false.
6310 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6311 isX86LogicalCmp(Cmp) &&
6312 Op.getNode()->hasOneUse()) {
6313 X86::CondCode CCode =
6314 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6315 CCode = X86::GetOppositeBranchCondition(CCode);
6316 CC = DAG.getConstant(CCode, MVT::i8);
6317 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6318 // Look for an unconditional branch following this conditional branch.
6319 // We need this because we need to reverse the successors in order
6320 // to implement FCMP_OEQ.
6321 if (User.getOpcode() == ISD::BR) {
6322 SDValue FalseBB = User.getOperand(1);
6324 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6325 assert(NewBR == User);
6328 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6329 Chain, Dest, CC, Cmp);
6330 X86::CondCode CCode =
6331 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6332 CCode = X86::GetOppositeBranchCondition(CCode);
6333 CC = DAG.getConstant(CCode, MVT::i8);
6339 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6340 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6341 // It should be transformed during dag combiner except when the condition
6342 // is set by a arithmetics with overflow node.
6343 X86::CondCode CCode =
6344 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6345 CCode = X86::GetOppositeBranchCondition(CCode);
6346 CC = DAG.getConstant(CCode, MVT::i8);
6347 Cond = Cond.getOperand(0).getOperand(1);
6353 // Look pass the truncate.
6354 if (Cond.getOpcode() == ISD::TRUNCATE)
6355 Cond = Cond.getOperand(0);
6357 // We know the result of AND is compared against zero. Try to match
6359 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6360 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6361 if (NewSetCC.getNode()) {
6362 CC = NewSetCC.getOperand(0);
6363 Cond = NewSetCC.getOperand(1);
6370 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6371 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6373 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6374 Chain, Dest, CC, Cond);
6378 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6379 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6380 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6381 // that the guard pages used by the OS virtual memory manager are allocated in
6382 // correct sequence.
6384 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6385 SelectionDAG &DAG) {
6386 assert(Subtarget->isTargetCygMing() &&
6387 "This should be used only on Cygwin/Mingw targets");
6388 DebugLoc dl = Op.getDebugLoc();
6391 SDValue Chain = Op.getOperand(0);
6392 SDValue Size = Op.getOperand(1);
6393 // FIXME: Ensure alignment here
6397 EVT IntPtr = getPointerTy();
6398 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6400 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6402 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6403 Flag = Chain.getValue(1);
6405 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6406 SDValue Ops[] = { Chain,
6407 DAG.getTargetExternalSymbol("_alloca", IntPtr),
6408 DAG.getRegister(X86::EAX, IntPtr),
6409 DAG.getRegister(X86StackPtr, SPTy),
6411 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6412 Flag = Chain.getValue(1);
6414 Chain = DAG.getCALLSEQ_END(Chain,
6415 DAG.getIntPtrConstant(0, true),
6416 DAG.getIntPtrConstant(0, true),
6419 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6421 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6422 return DAG.getMergeValues(Ops1, 2, dl);
6426 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6428 SDValue Dst, SDValue Src,
6429 SDValue Size, unsigned Align,
6431 uint64_t DstSVOff) {
6432 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6434 // If not DWORD aligned or size is more than the threshold, call the library.
6435 // The libc version is likely to be faster for these cases. It can use the
6436 // address value and run time information about the CPU.
6437 if ((Align & 3) != 0 ||
6439 ConstantSize->getZExtValue() >
6440 getSubtarget()->getMaxInlineSizeThreshold()) {
6441 SDValue InFlag(0, 0);
6443 // Check to see if there is a specialized entry-point for memory zeroing.
6444 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6446 if (const char *bzeroEntry = V &&
6447 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6448 EVT IntPtr = getPointerTy();
6449 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6450 TargetLowering::ArgListTy Args;
6451 TargetLowering::ArgListEntry Entry;
6453 Entry.Ty = IntPtrTy;
6454 Args.push_back(Entry);
6456 Args.push_back(Entry);
6457 std::pair<SDValue,SDValue> CallResult =
6458 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6459 false, false, false, false,
6460 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6461 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl,
6462 DAG.GetOrdering(Chain.getNode()));
6463 return CallResult.second;
6466 // Otherwise have the target-independent code call memset.
6470 uint64_t SizeVal = ConstantSize->getZExtValue();
6471 SDValue InFlag(0, 0);
6474 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6475 unsigned BytesLeft = 0;
6476 bool TwoRepStos = false;
6479 uint64_t Val = ValC->getZExtValue() & 255;
6481 // If the value is a constant, then we can potentially use larger sets.
6482 switch (Align & 3) {
6483 case 2: // WORD aligned
6486 Val = (Val << 8) | Val;
6488 case 0: // DWORD aligned
6491 Val = (Val << 8) | Val;
6492 Val = (Val << 16) | Val;
6493 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6496 Val = (Val << 32) | Val;
6499 default: // Byte aligned
6502 Count = DAG.getIntPtrConstant(SizeVal);
6506 if (AVT.bitsGT(MVT::i8)) {
6507 unsigned UBytes = AVT.getSizeInBits() / 8;
6508 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6509 BytesLeft = SizeVal % UBytes;
6512 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6514 InFlag = Chain.getValue(1);
6517 Count = DAG.getIntPtrConstant(SizeVal);
6518 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6519 InFlag = Chain.getValue(1);
6522 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6525 InFlag = Chain.getValue(1);
6526 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6529 InFlag = Chain.getValue(1);
6531 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6532 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6533 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6536 InFlag = Chain.getValue(1);
6538 EVT CVT = Count.getValueType();
6539 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6540 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6541 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6544 InFlag = Chain.getValue(1);
6545 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6546 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6547 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6548 } else if (BytesLeft) {
6549 // Handle the last 1 - 7 bytes.
6550 unsigned Offset = SizeVal - BytesLeft;
6551 EVT AddrVT = Dst.getValueType();
6552 EVT SizeVT = Size.getValueType();
6554 Chain = DAG.getMemset(Chain, dl,
6555 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6556 DAG.getConstant(Offset, AddrVT)),
6558 DAG.getConstant(BytesLeft, SizeVT),
6559 Align, DstSV, DstSVOff + Offset);
6562 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6567 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6568 SDValue Chain, SDValue Dst, SDValue Src,
6569 SDValue Size, unsigned Align,
6571 const Value *DstSV, uint64_t DstSVOff,
6572 const Value *SrcSV, uint64_t SrcSVOff) {
6573 // This requires the copy size to be a constant, preferrably
6574 // within a subtarget-specific limit.
6575 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6578 uint64_t SizeVal = ConstantSize->getZExtValue();
6579 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6582 /// If not DWORD aligned, call the library.
6583 if ((Align & 3) != 0)
6588 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6591 unsigned UBytes = AVT.getSizeInBits() / 8;
6592 unsigned CountVal = SizeVal / UBytes;
6593 SDValue Count = DAG.getIntPtrConstant(CountVal);
6594 unsigned BytesLeft = SizeVal % UBytes;
6596 SDValue InFlag(0, 0);
6597 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6600 InFlag = Chain.getValue(1);
6601 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6604 InFlag = Chain.getValue(1);
6605 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6608 InFlag = Chain.getValue(1);
6610 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6611 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6612 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6613 array_lengthof(Ops));
6615 SmallVector<SDValue, 4> Results;
6616 Results.push_back(RepMovs);
6618 // Handle the last 1 - 7 bytes.
6619 unsigned Offset = SizeVal - BytesLeft;
6620 EVT DstVT = Dst.getValueType();
6621 EVT SrcVT = Src.getValueType();
6622 EVT SizeVT = Size.getValueType();
6623 Results.push_back(DAG.getMemcpy(Chain, dl,
6624 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6625 DAG.getConstant(Offset, DstVT)),
6626 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6627 DAG.getConstant(Offset, SrcVT)),
6628 DAG.getConstant(BytesLeft, SizeVT),
6629 Align, AlwaysInline,
6630 DstSV, DstSVOff + Offset,
6631 SrcSV, SrcSVOff + Offset));
6634 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6635 &Results[0], Results.size());
6638 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6639 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6640 DebugLoc dl = Op.getDebugLoc();
6642 if (!Subtarget->is64Bit()) {
6643 // vastart just stores the address of the VarArgsFrameIndex slot into the
6644 // memory location argument.
6645 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6646 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6650 // gp_offset (0 - 6 * 8)
6651 // fp_offset (48 - 48 + 8 * 16)
6652 // overflow_arg_area (point to parameters coming in memory).
6654 SmallVector<SDValue, 8> MemOps;
6655 SDValue FIN = Op.getOperand(1);
6657 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6658 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6660 MemOps.push_back(Store);
6663 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6664 FIN, DAG.getIntPtrConstant(4));
6665 Store = DAG.getStore(Op.getOperand(0), dl,
6666 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6668 MemOps.push_back(Store);
6670 // Store ptr to overflow_arg_area
6671 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6672 FIN, DAG.getIntPtrConstant(4));
6673 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6674 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6675 MemOps.push_back(Store);
6677 // Store ptr to reg_save_area.
6678 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6679 FIN, DAG.getIntPtrConstant(8));
6680 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6681 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6682 MemOps.push_back(Store);
6683 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6684 &MemOps[0], MemOps.size());
6687 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6688 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6689 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6690 SDValue Chain = Op.getOperand(0);
6691 SDValue SrcPtr = Op.getOperand(1);
6692 SDValue SrcSV = Op.getOperand(2);
6694 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6698 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6699 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6700 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6701 SDValue Chain = Op.getOperand(0);
6702 SDValue DstPtr = Op.getOperand(1);
6703 SDValue SrcPtr = Op.getOperand(2);
6704 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6705 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6706 DebugLoc dl = Op.getDebugLoc();
6708 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6709 DAG.getIntPtrConstant(24), 8, false,
6710 DstSV, 0, SrcSV, 0);
6714 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6715 DebugLoc dl = Op.getDebugLoc();
6716 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6718 default: return SDValue(); // Don't custom lower most intrinsics.
6719 // Comparison intrinsics.
6720 case Intrinsic::x86_sse_comieq_ss:
6721 case Intrinsic::x86_sse_comilt_ss:
6722 case Intrinsic::x86_sse_comile_ss:
6723 case Intrinsic::x86_sse_comigt_ss:
6724 case Intrinsic::x86_sse_comige_ss:
6725 case Intrinsic::x86_sse_comineq_ss:
6726 case Intrinsic::x86_sse_ucomieq_ss:
6727 case Intrinsic::x86_sse_ucomilt_ss:
6728 case Intrinsic::x86_sse_ucomile_ss:
6729 case Intrinsic::x86_sse_ucomigt_ss:
6730 case Intrinsic::x86_sse_ucomige_ss:
6731 case Intrinsic::x86_sse_ucomineq_ss:
6732 case Intrinsic::x86_sse2_comieq_sd:
6733 case Intrinsic::x86_sse2_comilt_sd:
6734 case Intrinsic::x86_sse2_comile_sd:
6735 case Intrinsic::x86_sse2_comigt_sd:
6736 case Intrinsic::x86_sse2_comige_sd:
6737 case Intrinsic::x86_sse2_comineq_sd:
6738 case Intrinsic::x86_sse2_ucomieq_sd:
6739 case Intrinsic::x86_sse2_ucomilt_sd:
6740 case Intrinsic::x86_sse2_ucomile_sd:
6741 case Intrinsic::x86_sse2_ucomigt_sd:
6742 case Intrinsic::x86_sse2_ucomige_sd:
6743 case Intrinsic::x86_sse2_ucomineq_sd: {
6745 ISD::CondCode CC = ISD::SETCC_INVALID;
6748 case Intrinsic::x86_sse_comieq_ss:
6749 case Intrinsic::x86_sse2_comieq_sd:
6753 case Intrinsic::x86_sse_comilt_ss:
6754 case Intrinsic::x86_sse2_comilt_sd:
6758 case Intrinsic::x86_sse_comile_ss:
6759 case Intrinsic::x86_sse2_comile_sd:
6763 case Intrinsic::x86_sse_comigt_ss:
6764 case Intrinsic::x86_sse2_comigt_sd:
6768 case Intrinsic::x86_sse_comige_ss:
6769 case Intrinsic::x86_sse2_comige_sd:
6773 case Intrinsic::x86_sse_comineq_ss:
6774 case Intrinsic::x86_sse2_comineq_sd:
6778 case Intrinsic::x86_sse_ucomieq_ss:
6779 case Intrinsic::x86_sse2_ucomieq_sd:
6780 Opc = X86ISD::UCOMI;
6783 case Intrinsic::x86_sse_ucomilt_ss:
6784 case Intrinsic::x86_sse2_ucomilt_sd:
6785 Opc = X86ISD::UCOMI;
6788 case Intrinsic::x86_sse_ucomile_ss:
6789 case Intrinsic::x86_sse2_ucomile_sd:
6790 Opc = X86ISD::UCOMI;
6793 case Intrinsic::x86_sse_ucomigt_ss:
6794 case Intrinsic::x86_sse2_ucomigt_sd:
6795 Opc = X86ISD::UCOMI;
6798 case Intrinsic::x86_sse_ucomige_ss:
6799 case Intrinsic::x86_sse2_ucomige_sd:
6800 Opc = X86ISD::UCOMI;
6803 case Intrinsic::x86_sse_ucomineq_ss:
6804 case Intrinsic::x86_sse2_ucomineq_sd:
6805 Opc = X86ISD::UCOMI;
6810 SDValue LHS = Op.getOperand(1);
6811 SDValue RHS = Op.getOperand(2);
6812 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6813 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6814 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6815 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6816 DAG.getConstant(X86CC, MVT::i8), Cond);
6817 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6819 // ptest intrinsics. The intrinsic these come from are designed to return
6820 // an integer value, not just an instruction so lower it to the ptest
6821 // pattern and a setcc for the result.
6822 case Intrinsic::x86_sse41_ptestz:
6823 case Intrinsic::x86_sse41_ptestc:
6824 case Intrinsic::x86_sse41_ptestnzc:{
6827 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6828 case Intrinsic::x86_sse41_ptestz:
6830 X86CC = X86::COND_E;
6832 case Intrinsic::x86_sse41_ptestc:
6834 X86CC = X86::COND_B;
6836 case Intrinsic::x86_sse41_ptestnzc:
6838 X86CC = X86::COND_A;
6842 SDValue LHS = Op.getOperand(1);
6843 SDValue RHS = Op.getOperand(2);
6844 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6845 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6846 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6847 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6850 // Fix vector shift instructions where the last operand is a non-immediate
6852 case Intrinsic::x86_sse2_pslli_w:
6853 case Intrinsic::x86_sse2_pslli_d:
6854 case Intrinsic::x86_sse2_pslli_q:
6855 case Intrinsic::x86_sse2_psrli_w:
6856 case Intrinsic::x86_sse2_psrli_d:
6857 case Intrinsic::x86_sse2_psrli_q:
6858 case Intrinsic::x86_sse2_psrai_w:
6859 case Intrinsic::x86_sse2_psrai_d:
6860 case Intrinsic::x86_mmx_pslli_w:
6861 case Intrinsic::x86_mmx_pslli_d:
6862 case Intrinsic::x86_mmx_pslli_q:
6863 case Intrinsic::x86_mmx_psrli_w:
6864 case Intrinsic::x86_mmx_psrli_d:
6865 case Intrinsic::x86_mmx_psrli_q:
6866 case Intrinsic::x86_mmx_psrai_w:
6867 case Intrinsic::x86_mmx_psrai_d: {
6868 SDValue ShAmt = Op.getOperand(2);
6869 if (isa<ConstantSDNode>(ShAmt))
6872 unsigned NewIntNo = 0;
6873 EVT ShAmtVT = MVT::v4i32;
6875 case Intrinsic::x86_sse2_pslli_w:
6876 NewIntNo = Intrinsic::x86_sse2_psll_w;
6878 case Intrinsic::x86_sse2_pslli_d:
6879 NewIntNo = Intrinsic::x86_sse2_psll_d;
6881 case Intrinsic::x86_sse2_pslli_q:
6882 NewIntNo = Intrinsic::x86_sse2_psll_q;
6884 case Intrinsic::x86_sse2_psrli_w:
6885 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6887 case Intrinsic::x86_sse2_psrli_d:
6888 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6890 case Intrinsic::x86_sse2_psrli_q:
6891 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6893 case Intrinsic::x86_sse2_psrai_w:
6894 NewIntNo = Intrinsic::x86_sse2_psra_w;
6896 case Intrinsic::x86_sse2_psrai_d:
6897 NewIntNo = Intrinsic::x86_sse2_psra_d;
6900 ShAmtVT = MVT::v2i32;
6902 case Intrinsic::x86_mmx_pslli_w:
6903 NewIntNo = Intrinsic::x86_mmx_psll_w;
6905 case Intrinsic::x86_mmx_pslli_d:
6906 NewIntNo = Intrinsic::x86_mmx_psll_d;
6908 case Intrinsic::x86_mmx_pslli_q:
6909 NewIntNo = Intrinsic::x86_mmx_psll_q;
6911 case Intrinsic::x86_mmx_psrli_w:
6912 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6914 case Intrinsic::x86_mmx_psrli_d:
6915 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6917 case Intrinsic::x86_mmx_psrli_q:
6918 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6920 case Intrinsic::x86_mmx_psrai_w:
6921 NewIntNo = Intrinsic::x86_mmx_psra_w;
6923 case Intrinsic::x86_mmx_psrai_d:
6924 NewIntNo = Intrinsic::x86_mmx_psra_d;
6926 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6932 // The vector shift intrinsics with scalars uses 32b shift amounts but
6933 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6937 ShOps[1] = DAG.getConstant(0, MVT::i32);
6938 if (ShAmtVT == MVT::v4i32) {
6939 ShOps[2] = DAG.getUNDEF(MVT::i32);
6940 ShOps[3] = DAG.getUNDEF(MVT::i32);
6941 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6943 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6946 EVT VT = Op.getValueType();
6947 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6948 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6949 DAG.getConstant(NewIntNo, MVT::i32),
6950 Op.getOperand(1), ShAmt);
6955 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6956 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6957 DebugLoc dl = Op.getDebugLoc();
6960 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6962 DAG.getConstant(TD->getPointerSize(),
6963 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6964 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6965 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6970 // Just load the return address.
6971 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6972 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6973 RetAddrFI, NULL, 0);
6976 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6977 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6978 MFI->setFrameAddressIsTaken(true);
6979 EVT VT = Op.getValueType();
6980 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6981 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6982 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6983 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6985 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6989 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6990 SelectionDAG &DAG) {
6991 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6994 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6996 MachineFunction &MF = DAG.getMachineFunction();
6997 SDValue Chain = Op.getOperand(0);
6998 SDValue Offset = Op.getOperand(1);
6999 SDValue Handler = Op.getOperand(2);
7000 DebugLoc dl = Op.getDebugLoc();
7002 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7004 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7006 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7007 DAG.getIntPtrConstant(-TD->getPointerSize()));
7008 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7009 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
7010 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7011 MF.getRegInfo().addLiveOut(StoreAddrReg);
7013 return DAG.getNode(X86ISD::EH_RETURN, dl,
7015 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7018 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7019 SelectionDAG &DAG) {
7020 SDValue Root = Op.getOperand(0);
7021 SDValue Trmp = Op.getOperand(1); // trampoline
7022 SDValue FPtr = Op.getOperand(2); // nested function
7023 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7024 DebugLoc dl = Op.getDebugLoc();
7026 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7028 const X86InstrInfo *TII =
7029 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
7031 if (Subtarget->is64Bit()) {
7032 SDValue OutChains[6];
7034 // Large code-model.
7036 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
7037 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
7039 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7040 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7042 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7044 // Load the pointer to the nested function into R11.
7045 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7046 SDValue Addr = Trmp;
7047 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7050 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7051 DAG.getConstant(2, MVT::i64));
7052 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
7054 // Load the 'nest' parameter value into R10.
7055 // R10 is specified in X86CallingConv.td
7056 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7057 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7058 DAG.getConstant(10, MVT::i64));
7059 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7060 Addr, TrmpAddr, 10);
7062 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7063 DAG.getConstant(12, MVT::i64));
7064 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
7066 // Jump to the nested function.
7067 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7068 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7069 DAG.getConstant(20, MVT::i64));
7070 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7071 Addr, TrmpAddr, 20);
7073 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7074 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7075 DAG.getConstant(22, MVT::i64));
7076 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7080 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7081 return DAG.getMergeValues(Ops, 2, dl);
7083 const Function *Func =
7084 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7085 CallingConv::ID CC = Func->getCallingConv();
7090 llvm_unreachable("Unsupported calling convention");
7091 case CallingConv::C:
7092 case CallingConv::X86_StdCall: {
7093 // Pass 'nest' parameter in ECX.
7094 // Must be kept in sync with X86CallingConv.td
7097 // Check that ECX wasn't needed by an 'inreg' parameter.
7098 const FunctionType *FTy = Func->getFunctionType();
7099 const AttrListPtr &Attrs = Func->getAttributes();
7101 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7102 unsigned InRegCount = 0;
7105 for (FunctionType::param_iterator I = FTy->param_begin(),
7106 E = FTy->param_end(); I != E; ++I, ++Idx)
7107 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7108 // FIXME: should only count parameters that are lowered to integers.
7109 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7111 if (InRegCount > 2) {
7112 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
7117 case CallingConv::X86_FastCall:
7118 case CallingConv::Fast:
7119 // Pass 'nest' parameter in EAX.
7120 // Must be kept in sync with X86CallingConv.td
7125 SDValue OutChains[4];
7128 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7129 DAG.getConstant(10, MVT::i32));
7130 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7132 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
7133 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7134 OutChains[0] = DAG.getStore(Root, dl,
7135 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7138 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7139 DAG.getConstant(1, MVT::i32));
7140 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
7142 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
7143 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7144 DAG.getConstant(5, MVT::i32));
7145 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7146 TrmpAddr, 5, false, 1);
7148 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7149 DAG.getConstant(6, MVT::i32));
7150 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
7153 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7154 return DAG.getMergeValues(Ops, 2, dl);
7158 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
7160 The rounding mode is in bits 11:10 of FPSR, and has the following
7167 FLT_ROUNDS, on the other hand, expects the following:
7174 To perform the conversion, we do:
7175 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7178 MachineFunction &MF = DAG.getMachineFunction();
7179 const TargetMachine &TM = MF.getTarget();
7180 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7181 unsigned StackAlignment = TFI.getStackAlignment();
7182 EVT VT = Op.getValueType();
7183 DebugLoc dl = Op.getDebugLoc();
7185 // Save FP Control Word to stack slot
7186 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7187 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7189 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7190 DAG.getEntryNode(), StackSlot);
7192 // Load FP Control Word from stack slot
7193 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
7195 // Transform as necessary
7197 DAG.getNode(ISD::SRL, dl, MVT::i16,
7198 DAG.getNode(ISD::AND, dl, MVT::i16,
7199 CWD, DAG.getConstant(0x800, MVT::i16)),
7200 DAG.getConstant(11, MVT::i8));
7202 DAG.getNode(ISD::SRL, dl, MVT::i16,
7203 DAG.getNode(ISD::AND, dl, MVT::i16,
7204 CWD, DAG.getConstant(0x400, MVT::i16)),
7205 DAG.getConstant(9, MVT::i8));
7208 DAG.getNode(ISD::AND, dl, MVT::i16,
7209 DAG.getNode(ISD::ADD, dl, MVT::i16,
7210 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7211 DAG.getConstant(1, MVT::i16)),
7212 DAG.getConstant(3, MVT::i16));
7215 return DAG.getNode((VT.getSizeInBits() < 16 ?
7216 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7219 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
7220 EVT VT = Op.getValueType();
7222 unsigned NumBits = VT.getSizeInBits();
7223 DebugLoc dl = Op.getDebugLoc();
7225 Op = Op.getOperand(0);
7226 if (VT == MVT::i8) {
7227 // Zero extend to i32 since there is not an i8 bsr.
7229 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7232 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7233 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7234 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7236 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7239 DAG.getConstant(NumBits+NumBits-1, OpVT),
7240 DAG.getConstant(X86::COND_E, MVT::i8),
7243 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7245 // Finally xor with NumBits-1.
7246 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7249 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7253 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
7254 EVT VT = Op.getValueType();
7256 unsigned NumBits = VT.getSizeInBits();
7257 DebugLoc dl = Op.getDebugLoc();
7259 Op = Op.getOperand(0);
7260 if (VT == MVT::i8) {
7262 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7265 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7266 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7267 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7269 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7272 DAG.getConstant(NumBits, OpVT),
7273 DAG.getConstant(X86::COND_E, MVT::i8),
7276 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7279 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7283 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7284 EVT VT = Op.getValueType();
7285 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7286 DebugLoc dl = Op.getDebugLoc();
7288 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7289 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7290 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7291 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7292 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7294 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7295 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7296 // return AloBlo + AloBhi + AhiBlo;
7298 SDValue A = Op.getOperand(0);
7299 SDValue B = Op.getOperand(1);
7301 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7302 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7303 A, DAG.getConstant(32, MVT::i32));
7304 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7305 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7306 B, DAG.getConstant(32, MVT::i32));
7307 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7308 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7310 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7311 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7313 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7314 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7316 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7317 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7318 AloBhi, DAG.getConstant(32, MVT::i32));
7319 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7320 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7321 AhiBlo, DAG.getConstant(32, MVT::i32));
7322 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7323 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7328 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7329 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7330 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7331 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7332 // has only one use.
7333 SDNode *N = Op.getNode();
7334 SDValue LHS = N->getOperand(0);
7335 SDValue RHS = N->getOperand(1);
7336 unsigned BaseOp = 0;
7338 DebugLoc dl = Op.getDebugLoc();
7340 switch (Op.getOpcode()) {
7341 default: llvm_unreachable("Unknown ovf instruction!");
7343 // A subtract of one will be selected as a INC. Note that INC doesn't
7344 // set CF, so we can't do this for UADDO.
7345 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7346 if (C->getAPIntValue() == 1) {
7347 BaseOp = X86ISD::INC;
7351 BaseOp = X86ISD::ADD;
7355 BaseOp = X86ISD::ADD;
7359 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7360 // set CF, so we can't do this for USUBO.
7361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7362 if (C->getAPIntValue() == 1) {
7363 BaseOp = X86ISD::DEC;
7367 BaseOp = X86ISD::SUB;
7371 BaseOp = X86ISD::SUB;
7375 BaseOp = X86ISD::SMUL;
7379 BaseOp = X86ISD::UMUL;
7384 // Also sets EFLAGS.
7385 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7386 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7389 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7390 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7392 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7396 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7397 EVT T = Op.getValueType();
7398 DebugLoc dl = Op.getDebugLoc();
7401 switch(T.getSimpleVT().SimpleTy) {
7403 assert(false && "Invalid value type!");
7404 case MVT::i8: Reg = X86::AL; size = 1; break;
7405 case MVT::i16: Reg = X86::AX; size = 2; break;
7406 case MVT::i32: Reg = X86::EAX; size = 4; break;
7408 assert(Subtarget->is64Bit() && "Node not type legal!");
7409 Reg = X86::RAX; size = 8;
7412 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7413 Op.getOperand(2), SDValue());
7414 SDValue Ops[] = { cpIn.getValue(0),
7417 DAG.getTargetConstant(size, MVT::i8),
7419 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7420 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7422 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7426 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7427 SelectionDAG &DAG) {
7428 assert(Subtarget->is64Bit() && "Result not type legalized?");
7429 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7430 SDValue TheChain = Op.getOperand(0);
7431 DebugLoc dl = Op.getDebugLoc();
7432 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7433 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7434 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7436 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7437 DAG.getConstant(32, MVT::i8));
7439 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7442 return DAG.getMergeValues(Ops, 2, dl);
7445 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7446 SDNode *Node = Op.getNode();
7447 DebugLoc dl = Node->getDebugLoc();
7448 EVT T = Node->getValueType(0);
7449 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7450 DAG.getConstant(0, T), Node->getOperand(2));
7451 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7452 cast<AtomicSDNode>(Node)->getMemoryVT(),
7453 Node->getOperand(0),
7454 Node->getOperand(1), negOp,
7455 cast<AtomicSDNode>(Node)->getSrcValue(),
7456 cast<AtomicSDNode>(Node)->getAlignment());
7459 /// LowerOperation - Provide custom lowering hooks for some operations.
7461 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7462 switch (Op.getOpcode()) {
7463 default: llvm_unreachable("Should not custom lower this!");
7464 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7465 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7466 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7467 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7468 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7469 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7470 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7471 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7472 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7473 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7474 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7475 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7476 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7477 case ISD::SHL_PARTS:
7478 case ISD::SRA_PARTS:
7479 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7480 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7481 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7482 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7483 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7484 case ISD::FABS: return LowerFABS(Op, DAG);
7485 case ISD::FNEG: return LowerFNEG(Op, DAG);
7486 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7487 case ISD::SETCC: return LowerSETCC(Op, DAG);
7488 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7489 case ISD::SELECT: return LowerSELECT(Op, DAG);
7490 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7491 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7492 case ISD::VASTART: return LowerVASTART(Op, DAG);
7493 case ISD::VAARG: return LowerVAARG(Op, DAG);
7494 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7495 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7496 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7497 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7498 case ISD::FRAME_TO_ARGS_OFFSET:
7499 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7500 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7501 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7502 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7503 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7504 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7505 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7506 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7512 case ISD::UMULO: return LowerXALUO(Op, DAG);
7513 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7517 void X86TargetLowering::
7518 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7519 SelectionDAG &DAG, unsigned NewOp) {
7520 EVT T = Node->getValueType(0);
7521 DebugLoc dl = Node->getDebugLoc();
7522 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7524 SDValue Chain = Node->getOperand(0);
7525 SDValue In1 = Node->getOperand(1);
7526 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7527 Node->getOperand(2), DAG.getIntPtrConstant(0));
7528 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7529 Node->getOperand(2), DAG.getIntPtrConstant(1));
7530 SDValue Ops[] = { Chain, In1, In2L, In2H };
7531 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7533 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7534 cast<MemSDNode>(Node)->getMemOperand());
7535 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7536 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7537 Results.push_back(Result.getValue(2));
7540 /// ReplaceNodeResults - Replace a node with an illegal result type
7541 /// with a new node built out of custom code.
7542 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7543 SmallVectorImpl<SDValue>&Results,
7544 SelectionDAG &DAG) {
7545 DebugLoc dl = N->getDebugLoc();
7546 switch (N->getOpcode()) {
7548 assert(false && "Do not know how to custom type legalize this operation!");
7550 case ISD::FP_TO_SINT: {
7551 std::pair<SDValue,SDValue> Vals =
7552 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7553 SDValue FIST = Vals.first, StackSlot = Vals.second;
7554 if (FIST.getNode() != 0) {
7555 EVT VT = N->getValueType(0);
7556 // Return a load from the stack slot.
7557 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7561 case ISD::READCYCLECOUNTER: {
7562 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7563 SDValue TheChain = N->getOperand(0);
7564 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7565 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7567 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7569 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7570 SDValue Ops[] = { eax, edx };
7571 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7572 Results.push_back(edx.getValue(1));
7579 EVT WidenVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
7580 Results.push_back(DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()));
7583 case ISD::ATOMIC_CMP_SWAP: {
7584 EVT T = N->getValueType(0);
7585 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7586 SDValue cpInL, cpInH;
7587 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7588 DAG.getConstant(0, MVT::i32));
7589 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7590 DAG.getConstant(1, MVT::i32));
7591 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7592 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7594 SDValue swapInL, swapInH;
7595 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7596 DAG.getConstant(0, MVT::i32));
7597 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7598 DAG.getConstant(1, MVT::i32));
7599 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7601 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7602 swapInL.getValue(1));
7603 SDValue Ops[] = { swapInH.getValue(0),
7605 swapInH.getValue(1) };
7606 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7607 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7608 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7609 MVT::i32, Result.getValue(1));
7610 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7611 MVT::i32, cpOutL.getValue(2));
7612 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7613 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7614 Results.push_back(cpOutH.getValue(1));
7617 case ISD::ATOMIC_LOAD_ADD:
7618 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7620 case ISD::ATOMIC_LOAD_AND:
7621 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7623 case ISD::ATOMIC_LOAD_NAND:
7624 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7626 case ISD::ATOMIC_LOAD_OR:
7627 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7629 case ISD::ATOMIC_LOAD_SUB:
7630 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7632 case ISD::ATOMIC_LOAD_XOR:
7633 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7635 case ISD::ATOMIC_SWAP:
7636 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7641 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7643 default: return NULL;
7644 case X86ISD::BSF: return "X86ISD::BSF";
7645 case X86ISD::BSR: return "X86ISD::BSR";
7646 case X86ISD::SHLD: return "X86ISD::SHLD";
7647 case X86ISD::SHRD: return "X86ISD::SHRD";
7648 case X86ISD::FAND: return "X86ISD::FAND";
7649 case X86ISD::FOR: return "X86ISD::FOR";
7650 case X86ISD::FXOR: return "X86ISD::FXOR";
7651 case X86ISD::FSRL: return "X86ISD::FSRL";
7652 case X86ISD::FILD: return "X86ISD::FILD";
7653 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7654 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7655 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7656 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7657 case X86ISD::FLD: return "X86ISD::FLD";
7658 case X86ISD::FST: return "X86ISD::FST";
7659 case X86ISD::CALL: return "X86ISD::CALL";
7660 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7661 case X86ISD::BT: return "X86ISD::BT";
7662 case X86ISD::CMP: return "X86ISD::CMP";
7663 case X86ISD::COMI: return "X86ISD::COMI";
7664 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7665 case X86ISD::SETCC: return "X86ISD::SETCC";
7666 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7667 case X86ISD::CMOV: return "X86ISD::CMOV";
7668 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7669 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7670 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7671 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7672 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7673 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7674 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7675 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7676 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7677 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7678 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7679 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7680 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7681 case X86ISD::FMAX: return "X86ISD::FMAX";
7682 case X86ISD::FMIN: return "X86ISD::FMIN";
7683 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7684 case X86ISD::FRCP: return "X86ISD::FRCP";
7685 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7686 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7687 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7688 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7689 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7690 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7691 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7692 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7693 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7694 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7695 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7696 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7697 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7698 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7699 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7700 case X86ISD::VSHL: return "X86ISD::VSHL";
7701 case X86ISD::VSRL: return "X86ISD::VSRL";
7702 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7703 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7704 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7705 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7706 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7707 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7708 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7709 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7710 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7711 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7712 case X86ISD::ADD: return "X86ISD::ADD";
7713 case X86ISD::SUB: return "X86ISD::SUB";
7714 case X86ISD::SMUL: return "X86ISD::SMUL";
7715 case X86ISD::UMUL: return "X86ISD::UMUL";
7716 case X86ISD::INC: return "X86ISD::INC";
7717 case X86ISD::DEC: return "X86ISD::DEC";
7718 case X86ISD::OR: return "X86ISD::OR";
7719 case X86ISD::XOR: return "X86ISD::XOR";
7720 case X86ISD::AND: return "X86ISD::AND";
7721 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7722 case X86ISD::PTEST: return "X86ISD::PTEST";
7723 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7727 // isLegalAddressingMode - Return true if the addressing mode represented
7728 // by AM is legal for this target, for a load/store of the specified type.
7729 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7730 const Type *Ty) const {
7731 // X86 supports extremely general addressing modes.
7732 CodeModel::Model M = getTargetMachine().getCodeModel();
7734 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7735 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7740 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7742 // If a reference to this global requires an extra load, we can't fold it.
7743 if (isGlobalStubReference(GVFlags))
7746 // If BaseGV requires a register for the PIC base, we cannot also have a
7747 // BaseReg specified.
7748 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7751 // If lower 4G is not available, then we must use rip-relative addressing.
7752 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7762 // These scales always work.
7767 // These scales are formed with basereg+scalereg. Only accept if there is
7772 default: // Other stuff never works.
7780 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7781 if (!Ty1->isInteger() || !Ty2->isInteger())
7783 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7784 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7785 if (NumBits1 <= NumBits2)
7787 return Subtarget->is64Bit() || NumBits1 < 64;
7790 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7791 if (!VT1.isInteger() || !VT2.isInteger())
7793 unsigned NumBits1 = VT1.getSizeInBits();
7794 unsigned NumBits2 = VT2.getSizeInBits();
7795 if (NumBits1 <= NumBits2)
7797 return Subtarget->is64Bit() || NumBits1 < 64;
7800 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7801 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7802 return Ty1->isInteger(32) && Ty2->isInteger(64) && Subtarget->is64Bit();
7805 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7806 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7807 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7810 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7811 // i16 instructions are longer (0x66 prefix) and potentially slower.
7812 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7815 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7816 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7817 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7818 /// are assumed to be legal.
7820 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7822 // Only do shuffles on 128-bit vector types for now.
7823 if (VT.getSizeInBits() == 64)
7826 // FIXME: pshufb, blends, shifts.
7827 return (VT.getVectorNumElements() == 2 ||
7828 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7829 isMOVLMask(M, VT) ||
7830 isSHUFPMask(M, VT) ||
7831 isPSHUFDMask(M, VT) ||
7832 isPSHUFHWMask(M, VT) ||
7833 isPSHUFLWMask(M, VT) ||
7834 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7835 isUNPCKLMask(M, VT) ||
7836 isUNPCKHMask(M, VT) ||
7837 isUNPCKL_v_undef_Mask(M, VT) ||
7838 isUNPCKH_v_undef_Mask(M, VT));
7842 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7844 unsigned NumElts = VT.getVectorNumElements();
7845 // FIXME: This collection of masks seems suspect.
7848 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7849 return (isMOVLMask(Mask, VT) ||
7850 isCommutedMOVLMask(Mask, VT, true) ||
7851 isSHUFPMask(Mask, VT) ||
7852 isCommutedSHUFPMask(Mask, VT));
7857 //===----------------------------------------------------------------------===//
7858 // X86 Scheduler Hooks
7859 //===----------------------------------------------------------------------===//
7861 // private utility function
7863 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7864 MachineBasicBlock *MBB,
7872 TargetRegisterClass *RC,
7873 bool invSrc) const {
7874 // For the atomic bitwise operator, we generate
7877 // ld t1 = [bitinstr.addr]
7878 // op t2 = t1, [bitinstr.val]
7880 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7882 // fallthrough -->nextMBB
7883 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7884 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7885 MachineFunction::iterator MBBIter = MBB;
7888 /// First build the CFG
7889 MachineFunction *F = MBB->getParent();
7890 MachineBasicBlock *thisMBB = MBB;
7891 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7892 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7893 F->insert(MBBIter, newMBB);
7894 F->insert(MBBIter, nextMBB);
7896 // Move all successors to thisMBB to nextMBB
7897 nextMBB->transferSuccessors(thisMBB);
7899 // Update thisMBB to fall through to newMBB
7900 thisMBB->addSuccessor(newMBB);
7902 // newMBB jumps to itself and fall through to nextMBB
7903 newMBB->addSuccessor(nextMBB);
7904 newMBB->addSuccessor(newMBB);
7906 // Insert instructions into newMBB based on incoming instruction
7907 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7908 "unexpected number of operands");
7909 DebugLoc dl = bInstr->getDebugLoc();
7910 MachineOperand& destOper = bInstr->getOperand(0);
7911 MachineOperand* argOpers[2 + X86AddrNumOperands];
7912 int numArgs = bInstr->getNumOperands() - 1;
7913 for (int i=0; i < numArgs; ++i)
7914 argOpers[i] = &bInstr->getOperand(i+1);
7916 // x86 address has 4 operands: base, index, scale, and displacement
7917 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7918 int valArgIndx = lastAddrIndx + 1;
7920 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7921 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7922 for (int i=0; i <= lastAddrIndx; ++i)
7923 (*MIB).addOperand(*argOpers[i]);
7925 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7927 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7932 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7933 assert((argOpers[valArgIndx]->isReg() ||
7934 argOpers[valArgIndx]->isImm()) &&
7936 if (argOpers[valArgIndx]->isReg())
7937 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7939 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7941 (*MIB).addOperand(*argOpers[valArgIndx]);
7943 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7946 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7947 for (int i=0; i <= lastAddrIndx; ++i)
7948 (*MIB).addOperand(*argOpers[i]);
7950 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7951 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7952 bInstr->memoperands_end());
7954 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7958 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7960 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7964 // private utility function: 64 bit atomics on 32 bit host.
7966 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7967 MachineBasicBlock *MBB,
7972 bool invSrc) const {
7973 // For the atomic bitwise operator, we generate
7974 // thisMBB (instructions are in pairs, except cmpxchg8b)
7975 // ld t1,t2 = [bitinstr.addr]
7977 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7978 // op t5, t6 <- out1, out2, [bitinstr.val]
7979 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7980 // mov ECX, EBX <- t5, t6
7981 // mov EAX, EDX <- t1, t2
7982 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7983 // mov t3, t4 <- EAX, EDX
7985 // result in out1, out2
7986 // fallthrough -->nextMBB
7988 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7989 const unsigned LoadOpc = X86::MOV32rm;
7990 const unsigned copyOpc = X86::MOV32rr;
7991 const unsigned NotOpc = X86::NOT32r;
7992 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7993 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7994 MachineFunction::iterator MBBIter = MBB;
7997 /// First build the CFG
7998 MachineFunction *F = MBB->getParent();
7999 MachineBasicBlock *thisMBB = MBB;
8000 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8001 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8002 F->insert(MBBIter, newMBB);
8003 F->insert(MBBIter, nextMBB);
8005 // Move all successors to thisMBB to nextMBB
8006 nextMBB->transferSuccessors(thisMBB);
8008 // Update thisMBB to fall through to newMBB
8009 thisMBB->addSuccessor(newMBB);
8011 // newMBB jumps to itself and fall through to nextMBB
8012 newMBB->addSuccessor(nextMBB);
8013 newMBB->addSuccessor(newMBB);
8015 DebugLoc dl = bInstr->getDebugLoc();
8016 // Insert instructions into newMBB based on incoming instruction
8017 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8018 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
8019 "unexpected number of operands");
8020 MachineOperand& dest1Oper = bInstr->getOperand(0);
8021 MachineOperand& dest2Oper = bInstr->getOperand(1);
8022 MachineOperand* argOpers[2 + X86AddrNumOperands];
8023 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
8024 argOpers[i] = &bInstr->getOperand(i+2);
8026 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8027 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8029 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8030 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8031 for (int i=0; i <= lastAddrIndx; ++i)
8032 (*MIB).addOperand(*argOpers[i]);
8033 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8034 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8035 // add 4 to displacement.
8036 for (int i=0; i <= lastAddrIndx-2; ++i)
8037 (*MIB).addOperand(*argOpers[i]);
8038 MachineOperand newOp3 = *(argOpers[3]);
8040 newOp3.setImm(newOp3.getImm()+4);
8042 newOp3.setOffset(newOp3.getOffset()+4);
8043 (*MIB).addOperand(newOp3);
8044 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8046 // t3/4 are defined later, at the bottom of the loop
8047 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8048 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8049 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8050 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8051 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8052 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8054 // The subsequent operations should be using the destination registers of
8055 //the PHI instructions.
8057 t1 = F->getRegInfo().createVirtualRegister(RC);
8058 t2 = F->getRegInfo().createVirtualRegister(RC);
8059 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8060 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8062 t1 = dest1Oper.getReg();
8063 t2 = dest2Oper.getReg();
8066 int valArgIndx = lastAddrIndx + 1;
8067 assert((argOpers[valArgIndx]->isReg() ||
8068 argOpers[valArgIndx]->isImm()) &&
8070 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8071 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8072 if (argOpers[valArgIndx]->isReg())
8073 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8075 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8076 if (regOpcL != X86::MOV32rr)
8078 (*MIB).addOperand(*argOpers[valArgIndx]);
8079 assert(argOpers[valArgIndx + 1]->isReg() ==
8080 argOpers[valArgIndx]->isReg());
8081 assert(argOpers[valArgIndx + 1]->isImm() ==
8082 argOpers[valArgIndx]->isImm());
8083 if (argOpers[valArgIndx + 1]->isReg())
8084 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8086 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8087 if (regOpcH != X86::MOV32rr)
8089 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8091 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8093 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8096 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8098 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8101 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8102 for (int i=0; i <= lastAddrIndx; ++i)
8103 (*MIB).addOperand(*argOpers[i]);
8105 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8106 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8107 bInstr->memoperands_end());
8109 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8110 MIB.addReg(X86::EAX);
8111 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8112 MIB.addReg(X86::EDX);
8115 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
8117 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8121 // private utility function
8123 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8124 MachineBasicBlock *MBB,
8125 unsigned cmovOpc) const {
8126 // For the atomic min/max operator, we generate
8129 // ld t1 = [min/max.addr]
8130 // mov t2 = [min/max.val]
8132 // cmov[cond] t2 = t1
8134 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8136 // fallthrough -->nextMBB
8138 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8139 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8140 MachineFunction::iterator MBBIter = MBB;
8143 /// First build the CFG
8144 MachineFunction *F = MBB->getParent();
8145 MachineBasicBlock *thisMBB = MBB;
8146 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8147 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8148 F->insert(MBBIter, newMBB);
8149 F->insert(MBBIter, nextMBB);
8151 // Move all successors of thisMBB to nextMBB
8152 nextMBB->transferSuccessors(thisMBB);
8154 // Update thisMBB to fall through to newMBB
8155 thisMBB->addSuccessor(newMBB);
8157 // newMBB jumps to newMBB and fall through to nextMBB
8158 newMBB->addSuccessor(nextMBB);
8159 newMBB->addSuccessor(newMBB);
8161 DebugLoc dl = mInstr->getDebugLoc();
8162 // Insert instructions into newMBB based on incoming instruction
8163 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8164 "unexpected number of operands");
8165 MachineOperand& destOper = mInstr->getOperand(0);
8166 MachineOperand* argOpers[2 + X86AddrNumOperands];
8167 int numArgs = mInstr->getNumOperands() - 1;
8168 for (int i=0; i < numArgs; ++i)
8169 argOpers[i] = &mInstr->getOperand(i+1);
8171 // x86 address has 4 operands: base, index, scale, and displacement
8172 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8173 int valArgIndx = lastAddrIndx + 1;
8175 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8176 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8177 for (int i=0; i <= lastAddrIndx; ++i)
8178 (*MIB).addOperand(*argOpers[i]);
8180 // We only support register and immediate values
8181 assert((argOpers[valArgIndx]->isReg() ||
8182 argOpers[valArgIndx]->isImm()) &&
8185 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8186 if (argOpers[valArgIndx]->isReg())
8187 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8189 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8190 (*MIB).addOperand(*argOpers[valArgIndx]);
8192 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8195 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8200 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8201 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8205 // Cmp and exchange if none has modified the memory location
8206 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8207 for (int i=0; i <= lastAddrIndx; ++i)
8208 (*MIB).addOperand(*argOpers[i]);
8210 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8211 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8212 mInstr->memoperands_end());
8214 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8215 MIB.addReg(X86::EAX);
8218 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
8220 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
8224 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8225 // all of this code can be replaced with that in the .td file.
8227 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8228 unsigned numArgs, bool memArg) const {
8230 MachineFunction *F = BB->getParent();
8231 DebugLoc dl = MI->getDebugLoc();
8232 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8236 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8238 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8240 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8242 for (unsigned i = 0; i < numArgs; ++i) {
8243 MachineOperand &Op = MI->getOperand(i+1);
8245 if (!(Op.isReg() && Op.isImplicit()))
8249 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8252 F->DeleteMachineInstr(MI);
8258 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8260 MachineBasicBlock *MBB) const {
8261 // Emit code to save XMM registers to the stack. The ABI says that the
8262 // number of registers to save is given in %al, so it's theoretically
8263 // possible to do an indirect jump trick to avoid saving all of them,
8264 // however this code takes a simpler approach and just executes all
8265 // of the stores if %al is non-zero. It's less code, and it's probably
8266 // easier on the hardware branch predictor, and stores aren't all that
8267 // expensive anyway.
8269 // Create the new basic blocks. One block contains all the XMM stores,
8270 // and one block is the final destination regardless of whether any
8271 // stores were performed.
8272 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8273 MachineFunction *F = MBB->getParent();
8274 MachineFunction::iterator MBBIter = MBB;
8276 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8277 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8278 F->insert(MBBIter, XMMSaveMBB);
8279 F->insert(MBBIter, EndMBB);
8282 // Move any original successors of MBB to the end block.
8283 EndMBB->transferSuccessors(MBB);
8284 // The original block will now fall through to the XMM save block.
8285 MBB->addSuccessor(XMMSaveMBB);
8286 // The XMMSaveMBB will fall through to the end block.
8287 XMMSaveMBB->addSuccessor(EndMBB);
8289 // Now add the instructions.
8290 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8291 DebugLoc DL = MI->getDebugLoc();
8293 unsigned CountReg = MI->getOperand(0).getReg();
8294 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8295 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8297 if (!Subtarget->isTargetWin64()) {
8298 // If %al is 0, branch around the XMM save block.
8299 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8300 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
8301 MBB->addSuccessor(EndMBB);
8304 // In the XMM save block, save all the XMM argument registers.
8305 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8306 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8307 MachineMemOperand *MMO =
8308 F->getMachineMemOperand(
8309 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8310 MachineMemOperand::MOStore, Offset,
8311 /*Size=*/16, /*Align=*/16);
8312 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8313 .addFrameIndex(RegSaveFrameIndex)
8314 .addImm(/*Scale=*/1)
8315 .addReg(/*IndexReg=*/0)
8316 .addImm(/*Disp=*/Offset)
8317 .addReg(/*Segment=*/0)
8318 .addReg(MI->getOperand(i).getReg())
8319 .addMemOperand(MMO);
8322 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8328 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8329 MachineBasicBlock *BB,
8330 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8331 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8332 DebugLoc DL = MI->getDebugLoc();
8334 // To "insert" a SELECT_CC instruction, we actually have to insert the
8335 // diamond control-flow pattern. The incoming instruction knows the
8336 // destination vreg to set, the condition code register to branch on, the
8337 // true/false values to select between, and a branch opcode to use.
8338 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8339 MachineFunction::iterator It = BB;
8345 // cmpTY ccX, r1, r2
8347 // fallthrough --> copy0MBB
8348 MachineBasicBlock *thisMBB = BB;
8349 MachineFunction *F = BB->getParent();
8350 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8351 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8353 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8354 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8355 F->insert(It, copy0MBB);
8356 F->insert(It, sinkMBB);
8357 // Update machine-CFG edges by first adding all successors of the current
8358 // block to the new block which will contain the Phi node for the select.
8359 // Also inform sdisel of the edge changes.
8360 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8361 E = BB->succ_end(); I != E; ++I) {
8362 EM->insert(std::make_pair(*I, sinkMBB));
8363 sinkMBB->addSuccessor(*I);
8365 // Next, remove all successors of the current block, and add the true
8366 // and fallthrough blocks as its successors.
8367 while (!BB->succ_empty())
8368 BB->removeSuccessor(BB->succ_begin());
8369 // Add the true and fallthrough blocks as its successors.
8370 BB->addSuccessor(copy0MBB);
8371 BB->addSuccessor(sinkMBB);
8374 // %FalseValue = ...
8375 // # fallthrough to sinkMBB
8378 // Update machine-CFG edges
8379 BB->addSuccessor(sinkMBB);
8382 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8385 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8386 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8387 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8389 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8395 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8396 MachineBasicBlock *BB,
8397 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8398 switch (MI->getOpcode()) {
8399 default: assert(false && "Unexpected instr type to insert");
8401 case X86::CMOV_V1I64:
8402 case X86::CMOV_FR32:
8403 case X86::CMOV_FR64:
8404 case X86::CMOV_V4F32:
8405 case X86::CMOV_V2F64:
8406 case X86::CMOV_V2I64:
8407 return EmitLoweredSelect(MI, BB, EM);
8409 case X86::FP32_TO_INT16_IN_MEM:
8410 case X86::FP32_TO_INT32_IN_MEM:
8411 case X86::FP32_TO_INT64_IN_MEM:
8412 case X86::FP64_TO_INT16_IN_MEM:
8413 case X86::FP64_TO_INT32_IN_MEM:
8414 case X86::FP64_TO_INT64_IN_MEM:
8415 case X86::FP80_TO_INT16_IN_MEM:
8416 case X86::FP80_TO_INT32_IN_MEM:
8417 case X86::FP80_TO_INT64_IN_MEM: {
8418 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8419 DebugLoc DL = MI->getDebugLoc();
8421 // Change the floating point control register to use "round towards zero"
8422 // mode when truncating to an integer value.
8423 MachineFunction *F = BB->getParent();
8424 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8425 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8427 // Load the old value of the high byte of the control word...
8429 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8430 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8433 // Set the high part to be round to zero...
8434 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8437 // Reload the modified control word now...
8438 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8440 // Restore the memory image of control word to original value
8441 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8444 // Get the X86 opcode to use.
8446 switch (MI->getOpcode()) {
8447 default: llvm_unreachable("illegal opcode!");
8448 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8449 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8450 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8451 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8452 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8453 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8454 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8455 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8456 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8460 MachineOperand &Op = MI->getOperand(0);
8462 AM.BaseType = X86AddressMode::RegBase;
8463 AM.Base.Reg = Op.getReg();
8465 AM.BaseType = X86AddressMode::FrameIndexBase;
8466 AM.Base.FrameIndex = Op.getIndex();
8468 Op = MI->getOperand(1);
8470 AM.Scale = Op.getImm();
8471 Op = MI->getOperand(2);
8473 AM.IndexReg = Op.getImm();
8474 Op = MI->getOperand(3);
8475 if (Op.isGlobal()) {
8476 AM.GV = Op.getGlobal();
8478 AM.Disp = Op.getImm();
8480 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8481 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8483 // Reload the original control word now.
8484 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8486 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8489 // String/text processing lowering.
8490 case X86::PCMPISTRM128REG:
8491 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8492 case X86::PCMPISTRM128MEM:
8493 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8494 case X86::PCMPESTRM128REG:
8495 return EmitPCMP(MI, BB, 5, false /* in mem */);
8496 case X86::PCMPESTRM128MEM:
8497 return EmitPCMP(MI, BB, 5, true /* in mem */);
8500 case X86::ATOMAND32:
8501 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8502 X86::AND32ri, X86::MOV32rm,
8503 X86::LCMPXCHG32, X86::MOV32rr,
8504 X86::NOT32r, X86::EAX,
8505 X86::GR32RegisterClass);
8507 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8508 X86::OR32ri, X86::MOV32rm,
8509 X86::LCMPXCHG32, X86::MOV32rr,
8510 X86::NOT32r, X86::EAX,
8511 X86::GR32RegisterClass);
8512 case X86::ATOMXOR32:
8513 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8514 X86::XOR32ri, X86::MOV32rm,
8515 X86::LCMPXCHG32, X86::MOV32rr,
8516 X86::NOT32r, X86::EAX,
8517 X86::GR32RegisterClass);
8518 case X86::ATOMNAND32:
8519 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8520 X86::AND32ri, X86::MOV32rm,
8521 X86::LCMPXCHG32, X86::MOV32rr,
8522 X86::NOT32r, X86::EAX,
8523 X86::GR32RegisterClass, true);
8524 case X86::ATOMMIN32:
8525 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8526 case X86::ATOMMAX32:
8527 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8528 case X86::ATOMUMIN32:
8529 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8530 case X86::ATOMUMAX32:
8531 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8533 case X86::ATOMAND16:
8534 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8535 X86::AND16ri, X86::MOV16rm,
8536 X86::LCMPXCHG16, X86::MOV16rr,
8537 X86::NOT16r, X86::AX,
8538 X86::GR16RegisterClass);
8540 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8541 X86::OR16ri, X86::MOV16rm,
8542 X86::LCMPXCHG16, X86::MOV16rr,
8543 X86::NOT16r, X86::AX,
8544 X86::GR16RegisterClass);
8545 case X86::ATOMXOR16:
8546 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8547 X86::XOR16ri, X86::MOV16rm,
8548 X86::LCMPXCHG16, X86::MOV16rr,
8549 X86::NOT16r, X86::AX,
8550 X86::GR16RegisterClass);
8551 case X86::ATOMNAND16:
8552 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8553 X86::AND16ri, X86::MOV16rm,
8554 X86::LCMPXCHG16, X86::MOV16rr,
8555 X86::NOT16r, X86::AX,
8556 X86::GR16RegisterClass, true);
8557 case X86::ATOMMIN16:
8558 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8559 case X86::ATOMMAX16:
8560 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8561 case X86::ATOMUMIN16:
8562 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8563 case X86::ATOMUMAX16:
8564 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8567 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8568 X86::AND8ri, X86::MOV8rm,
8569 X86::LCMPXCHG8, X86::MOV8rr,
8570 X86::NOT8r, X86::AL,
8571 X86::GR8RegisterClass);
8573 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8574 X86::OR8ri, X86::MOV8rm,
8575 X86::LCMPXCHG8, X86::MOV8rr,
8576 X86::NOT8r, X86::AL,
8577 X86::GR8RegisterClass);
8579 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8580 X86::XOR8ri, X86::MOV8rm,
8581 X86::LCMPXCHG8, X86::MOV8rr,
8582 X86::NOT8r, X86::AL,
8583 X86::GR8RegisterClass);
8584 case X86::ATOMNAND8:
8585 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8586 X86::AND8ri, X86::MOV8rm,
8587 X86::LCMPXCHG8, X86::MOV8rr,
8588 X86::NOT8r, X86::AL,
8589 X86::GR8RegisterClass, true);
8590 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8591 // This group is for 64-bit host.
8592 case X86::ATOMAND64:
8593 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8594 X86::AND64ri32, X86::MOV64rm,
8595 X86::LCMPXCHG64, X86::MOV64rr,
8596 X86::NOT64r, X86::RAX,
8597 X86::GR64RegisterClass);
8599 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8600 X86::OR64ri32, X86::MOV64rm,
8601 X86::LCMPXCHG64, X86::MOV64rr,
8602 X86::NOT64r, X86::RAX,
8603 X86::GR64RegisterClass);
8604 case X86::ATOMXOR64:
8605 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8606 X86::XOR64ri32, X86::MOV64rm,
8607 X86::LCMPXCHG64, X86::MOV64rr,
8608 X86::NOT64r, X86::RAX,
8609 X86::GR64RegisterClass);
8610 case X86::ATOMNAND64:
8611 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8612 X86::AND64ri32, X86::MOV64rm,
8613 X86::LCMPXCHG64, X86::MOV64rr,
8614 X86::NOT64r, X86::RAX,
8615 X86::GR64RegisterClass, true);
8616 case X86::ATOMMIN64:
8617 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8618 case X86::ATOMMAX64:
8619 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8620 case X86::ATOMUMIN64:
8621 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8622 case X86::ATOMUMAX64:
8623 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8625 // This group does 64-bit operations on a 32-bit host.
8626 case X86::ATOMAND6432:
8627 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8628 X86::AND32rr, X86::AND32rr,
8629 X86::AND32ri, X86::AND32ri,
8631 case X86::ATOMOR6432:
8632 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8633 X86::OR32rr, X86::OR32rr,
8634 X86::OR32ri, X86::OR32ri,
8636 case X86::ATOMXOR6432:
8637 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8638 X86::XOR32rr, X86::XOR32rr,
8639 X86::XOR32ri, X86::XOR32ri,
8641 case X86::ATOMNAND6432:
8642 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8643 X86::AND32rr, X86::AND32rr,
8644 X86::AND32ri, X86::AND32ri,
8646 case X86::ATOMADD6432:
8647 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8648 X86::ADD32rr, X86::ADC32rr,
8649 X86::ADD32ri, X86::ADC32ri,
8651 case X86::ATOMSUB6432:
8652 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8653 X86::SUB32rr, X86::SBB32rr,
8654 X86::SUB32ri, X86::SBB32ri,
8656 case X86::ATOMSWAP6432:
8657 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8658 X86::MOV32rr, X86::MOV32rr,
8659 X86::MOV32ri, X86::MOV32ri,
8661 case X86::VASTART_SAVE_XMM_REGS:
8662 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8666 //===----------------------------------------------------------------------===//
8667 // X86 Optimization Hooks
8668 //===----------------------------------------------------------------------===//
8670 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8674 const SelectionDAG &DAG,
8675 unsigned Depth) const {
8676 unsigned Opc = Op.getOpcode();
8677 assert((Opc >= ISD::BUILTIN_OP_END ||
8678 Opc == ISD::INTRINSIC_WO_CHAIN ||
8679 Opc == ISD::INTRINSIC_W_CHAIN ||
8680 Opc == ISD::INTRINSIC_VOID) &&
8681 "Should use MaskedValueIsZero if you don't know whether Op"
8682 " is a target node!");
8684 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8696 // These nodes' second result is a boolean.
8697 if (Op.getResNo() == 0)
8701 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8702 Mask.getBitWidth() - 1);
8707 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8708 /// node is a GlobalAddress + offset.
8709 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8710 GlobalValue* &GA, int64_t &Offset) const{
8711 if (N->getOpcode() == X86ISD::Wrapper) {
8712 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8713 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8714 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8718 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8721 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8722 EVT EltVT, LoadSDNode *&LDBase,
8723 unsigned &LastLoadedElt,
8724 SelectionDAG &DAG, MachineFrameInfo *MFI,
8725 const TargetLowering &TLI) {
8727 LastLoadedElt = -1U;
8728 for (unsigned i = 0; i < NumElems; ++i) {
8729 if (N->getMaskElt(i) < 0) {
8735 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8736 if (!Elt.getNode() ||
8737 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8740 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8742 LDBase = cast<LoadSDNode>(Elt.getNode());
8746 if (Elt.getOpcode() == ISD::UNDEF)
8749 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8750 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8757 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8758 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8759 /// if the load addresses are consecutive, non-overlapping, and in the right
8760 /// order. In the case of v2i64, it will see if it can rewrite the
8761 /// shuffle to be an appropriate build vector so it can take advantage of
8762 // performBuildVectorCombine.
8763 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8764 const TargetLowering &TLI) {
8765 DebugLoc dl = N->getDebugLoc();
8766 EVT VT = N->getValueType(0);
8767 EVT EltVT = VT.getVectorElementType();
8768 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8769 unsigned NumElems = VT.getVectorNumElements();
8771 if (VT.getSizeInBits() != 128)
8774 // Try to combine a vector_shuffle into a 128-bit load.
8775 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8776 LoadSDNode *LD = NULL;
8777 unsigned LastLoadedElt;
8778 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8782 if (LastLoadedElt == NumElems - 1) {
8783 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8784 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8785 LD->getSrcValue(), LD->getSrcValueOffset(),
8787 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8788 LD->getSrcValue(), LD->getSrcValueOffset(),
8789 LD->isVolatile(), LD->getAlignment());
8790 } else if (NumElems == 4 && LastLoadedElt == 1) {
8791 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8792 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8793 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8794 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8799 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8800 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8801 const X86Subtarget *Subtarget) {
8802 DebugLoc DL = N->getDebugLoc();
8803 SDValue Cond = N->getOperand(0);
8804 // Get the LHS/RHS of the select.
8805 SDValue LHS = N->getOperand(1);
8806 SDValue RHS = N->getOperand(2);
8808 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8809 // instructions have the peculiarity that if either operand is a NaN,
8810 // they chose what we call the RHS operand (and as such are not symmetric).
8811 // It happens that this matches the semantics of the common C idiom
8812 // x<y?x:y and related forms, so we can recognize these cases.
8813 if (Subtarget->hasSSE2() &&
8814 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8815 Cond.getOpcode() == ISD::SETCC) {
8816 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8818 unsigned Opcode = 0;
8819 // Check for x CC y ? x : y.
8820 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8824 // This can be a min if we can prove that at least one of the operands
8826 if (!FiniteOnlyFPMath()) {
8827 if (DAG.isKnownNeverNaN(RHS)) {
8828 // Put the potential NaN in the RHS so that SSE will preserve it.
8829 std::swap(LHS, RHS);
8830 } else if (!DAG.isKnownNeverNaN(LHS))
8833 Opcode = X86ISD::FMIN;
8836 // This can be a min if we can prove that at least one of the operands
8838 if (!FiniteOnlyFPMath()) {
8839 if (DAG.isKnownNeverNaN(LHS)) {
8840 // Put the potential NaN in the RHS so that SSE will preserve it.
8841 std::swap(LHS, RHS);
8842 } else if (!DAG.isKnownNeverNaN(RHS))
8845 Opcode = X86ISD::FMIN;
8848 // This can be a min, but if either operand is a NaN we need it to
8849 // preserve the original LHS.
8850 std::swap(LHS, RHS);
8854 Opcode = X86ISD::FMIN;
8858 // This can be a max if we can prove that at least one of the operands
8860 if (!FiniteOnlyFPMath()) {
8861 if (DAG.isKnownNeverNaN(LHS)) {
8862 // Put the potential NaN in the RHS so that SSE will preserve it.
8863 std::swap(LHS, RHS);
8864 } else if (!DAG.isKnownNeverNaN(RHS))
8867 Opcode = X86ISD::FMAX;
8870 // This can be a max if we can prove that at least one of the operands
8872 if (!FiniteOnlyFPMath()) {
8873 if (DAG.isKnownNeverNaN(RHS)) {
8874 // Put the potential NaN in the RHS so that SSE will preserve it.
8875 std::swap(LHS, RHS);
8876 } else if (!DAG.isKnownNeverNaN(LHS))
8879 Opcode = X86ISD::FMAX;
8882 // This can be a max, but if either operand is a NaN we need it to
8883 // preserve the original LHS.
8884 std::swap(LHS, RHS);
8888 Opcode = X86ISD::FMAX;
8891 // Check for x CC y ? y : x -- a min/max with reversed arms.
8892 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8896 // This can be a min if we can prove that at least one of the operands
8898 if (!FiniteOnlyFPMath()) {
8899 if (DAG.isKnownNeverNaN(RHS)) {
8900 // Put the potential NaN in the RHS so that SSE will preserve it.
8901 std::swap(LHS, RHS);
8902 } else if (!DAG.isKnownNeverNaN(LHS))
8905 Opcode = X86ISD::FMIN;
8908 // This can be a min if we can prove that at least one of the operands
8910 if (!FiniteOnlyFPMath()) {
8911 if (DAG.isKnownNeverNaN(LHS)) {
8912 // Put the potential NaN in the RHS so that SSE will preserve it.
8913 std::swap(LHS, RHS);
8914 } else if (!DAG.isKnownNeverNaN(RHS))
8917 Opcode = X86ISD::FMIN;
8920 // This can be a min, but if either operand is a NaN we need it to
8921 // preserve the original LHS.
8922 std::swap(LHS, RHS);
8926 Opcode = X86ISD::FMIN;
8930 // This can be a max if we can prove that at least one of the operands
8932 if (!FiniteOnlyFPMath()) {
8933 if (DAG.isKnownNeverNaN(LHS)) {
8934 // Put the potential NaN in the RHS so that SSE will preserve it.
8935 std::swap(LHS, RHS);
8936 } else if (!DAG.isKnownNeverNaN(RHS))
8939 Opcode = X86ISD::FMAX;
8942 // This can be a max if we can prove that at least one of the operands
8944 if (!FiniteOnlyFPMath()) {
8945 if (DAG.isKnownNeverNaN(RHS)) {
8946 // Put the potential NaN in the RHS so that SSE will preserve it.
8947 std::swap(LHS, RHS);
8948 } else if (!DAG.isKnownNeverNaN(LHS))
8951 Opcode = X86ISD::FMAX;
8954 // This can be a max, but if either operand is a NaN we need it to
8955 // preserve the original LHS.
8956 std::swap(LHS, RHS);
8960 Opcode = X86ISD::FMAX;
8966 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8969 // If this is a select between two integer constants, try to do some
8971 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8972 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8973 // Don't do this for crazy integer types.
8974 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8975 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8976 // so that TrueC (the true value) is larger than FalseC.
8977 bool NeedsCondInvert = false;
8979 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8980 // Efficiently invertible.
8981 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8982 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8983 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8984 NeedsCondInvert = true;
8985 std::swap(TrueC, FalseC);
8988 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8989 if (FalseC->getAPIntValue() == 0 &&
8990 TrueC->getAPIntValue().isPowerOf2()) {
8991 if (NeedsCondInvert) // Invert the condition if needed.
8992 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8993 DAG.getConstant(1, Cond.getValueType()));
8995 // Zero extend the condition if needed.
8996 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8998 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8999 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9000 DAG.getConstant(ShAmt, MVT::i8));
9003 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9004 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9005 if (NeedsCondInvert) // Invert the condition if needed.
9006 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9007 DAG.getConstant(1, Cond.getValueType()));
9009 // Zero extend the condition if needed.
9010 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9011 FalseC->getValueType(0), Cond);
9012 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9013 SDValue(FalseC, 0));
9016 // Optimize cases that will turn into an LEA instruction. This requires
9017 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9018 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9019 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9020 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9022 bool isFastMultiplier = false;
9024 switch ((unsigned char)Diff) {
9026 case 1: // result = add base, cond
9027 case 2: // result = lea base( , cond*2)
9028 case 3: // result = lea base(cond, cond*2)
9029 case 4: // result = lea base( , cond*4)
9030 case 5: // result = lea base(cond, cond*4)
9031 case 8: // result = lea base( , cond*8)
9032 case 9: // result = lea base(cond, cond*8)
9033 isFastMultiplier = true;
9038 if (isFastMultiplier) {
9039 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9040 if (NeedsCondInvert) // Invert the condition if needed.
9041 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9042 DAG.getConstant(1, Cond.getValueType()));
9044 // Zero extend the condition if needed.
9045 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9047 // Scale the condition by the difference.
9049 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9050 DAG.getConstant(Diff, Cond.getValueType()));
9052 // Add the base if non-zero.
9053 if (FalseC->getAPIntValue() != 0)
9054 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9055 SDValue(FalseC, 0));
9065 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9066 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9067 TargetLowering::DAGCombinerInfo &DCI) {
9068 DebugLoc DL = N->getDebugLoc();
9070 // If the flag operand isn't dead, don't touch this CMOV.
9071 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9074 // If this is a select between two integer constants, try to do some
9075 // optimizations. Note that the operands are ordered the opposite of SELECT
9077 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9078 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9079 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9080 // larger than FalseC (the false value).
9081 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9083 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9084 CC = X86::GetOppositeBranchCondition(CC);
9085 std::swap(TrueC, FalseC);
9088 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9089 // This is efficient for any integer data type (including i8/i16) and
9091 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9092 SDValue Cond = N->getOperand(3);
9093 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9094 DAG.getConstant(CC, MVT::i8), Cond);
9096 // Zero extend the condition if needed.
9097 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9099 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9100 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9101 DAG.getConstant(ShAmt, MVT::i8));
9102 if (N->getNumValues() == 2) // Dead flag value?
9103 return DCI.CombineTo(N, Cond, SDValue());
9107 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9108 // for any integer data type, including i8/i16.
9109 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9110 SDValue Cond = N->getOperand(3);
9111 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9112 DAG.getConstant(CC, MVT::i8), Cond);
9114 // Zero extend the condition if needed.
9115 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9116 FalseC->getValueType(0), Cond);
9117 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9118 SDValue(FalseC, 0));
9120 if (N->getNumValues() == 2) // Dead flag value?
9121 return DCI.CombineTo(N, Cond, SDValue());
9125 // Optimize cases that will turn into an LEA instruction. This requires
9126 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9127 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9128 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9129 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9131 bool isFastMultiplier = false;
9133 switch ((unsigned char)Diff) {
9135 case 1: // result = add base, cond
9136 case 2: // result = lea base( , cond*2)
9137 case 3: // result = lea base(cond, cond*2)
9138 case 4: // result = lea base( , cond*4)
9139 case 5: // result = lea base(cond, cond*4)
9140 case 8: // result = lea base( , cond*8)
9141 case 9: // result = lea base(cond, cond*8)
9142 isFastMultiplier = true;
9147 if (isFastMultiplier) {
9148 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9149 SDValue Cond = N->getOperand(3);
9150 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9151 DAG.getConstant(CC, MVT::i8), Cond);
9152 // Zero extend the condition if needed.
9153 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9155 // Scale the condition by the difference.
9157 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9158 DAG.getConstant(Diff, Cond.getValueType()));
9160 // Add the base if non-zero.
9161 if (FalseC->getAPIntValue() != 0)
9162 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9163 SDValue(FalseC, 0));
9164 if (N->getNumValues() == 2) // Dead flag value?
9165 return DCI.CombineTo(N, Cond, SDValue());
9175 /// PerformMulCombine - Optimize a single multiply with constant into two
9176 /// in order to implement it with two cheaper instructions, e.g.
9177 /// LEA + SHL, LEA + LEA.
9178 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9179 TargetLowering::DAGCombinerInfo &DCI) {
9180 if (DAG.getMachineFunction().
9181 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
9184 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9187 EVT VT = N->getValueType(0);
9191 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9194 uint64_t MulAmt = C->getZExtValue();
9195 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9198 uint64_t MulAmt1 = 0;
9199 uint64_t MulAmt2 = 0;
9200 if ((MulAmt % 9) == 0) {
9202 MulAmt2 = MulAmt / 9;
9203 } else if ((MulAmt % 5) == 0) {
9205 MulAmt2 = MulAmt / 5;
9206 } else if ((MulAmt % 3) == 0) {
9208 MulAmt2 = MulAmt / 3;
9211 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9212 DebugLoc DL = N->getDebugLoc();
9214 if (isPowerOf2_64(MulAmt2) &&
9215 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9216 // If second multiplifer is pow2, issue it first. We want the multiply by
9217 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9219 std::swap(MulAmt1, MulAmt2);
9222 if (isPowerOf2_64(MulAmt1))
9223 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9224 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9226 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9227 DAG.getConstant(MulAmt1, VT));
9229 if (isPowerOf2_64(MulAmt2))
9230 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9231 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9233 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9234 DAG.getConstant(MulAmt2, VT));
9236 // Do not add new nodes to DAG combiner worklist.
9237 DCI.CombineTo(N, NewMul, false);
9242 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9243 SDValue N0 = N->getOperand(0);
9244 SDValue N1 = N->getOperand(1);
9245 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9246 EVT VT = N0.getValueType();
9248 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9249 // since the result of setcc_c is all zero's or all ones.
9250 if (N1C && N0.getOpcode() == ISD::AND &&
9251 N0.getOperand(1).getOpcode() == ISD::Constant) {
9252 SDValue N00 = N0.getOperand(0);
9253 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9254 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9255 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9256 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9257 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9258 APInt ShAmt = N1C->getAPIntValue();
9259 Mask = Mask.shl(ShAmt);
9261 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9262 N00, DAG.getConstant(Mask, VT));
9269 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9271 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9272 const X86Subtarget *Subtarget) {
9273 EVT VT = N->getValueType(0);
9274 if (!VT.isVector() && VT.isInteger() &&
9275 N->getOpcode() == ISD::SHL)
9276 return PerformSHLCombine(N, DAG);
9278 // On X86 with SSE2 support, we can transform this to a vector shift if
9279 // all elements are shifted by the same amount. We can't do this in legalize
9280 // because the a constant vector is typically transformed to a constant pool
9281 // so we have no knowledge of the shift amount.
9282 if (!Subtarget->hasSSE2())
9285 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9288 SDValue ShAmtOp = N->getOperand(1);
9289 EVT EltVT = VT.getVectorElementType();
9290 DebugLoc DL = N->getDebugLoc();
9291 SDValue BaseShAmt = SDValue();
9292 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9293 unsigned NumElts = VT.getVectorNumElements();
9295 for (; i != NumElts; ++i) {
9296 SDValue Arg = ShAmtOp.getOperand(i);
9297 if (Arg.getOpcode() == ISD::UNDEF) continue;
9301 for (; i != NumElts; ++i) {
9302 SDValue Arg = ShAmtOp.getOperand(i);
9303 if (Arg.getOpcode() == ISD::UNDEF) continue;
9304 if (Arg != BaseShAmt) {
9308 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9309 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9310 SDValue InVec = ShAmtOp.getOperand(0);
9311 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9312 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9314 for (; i != NumElts; ++i) {
9315 SDValue Arg = InVec.getOperand(i);
9316 if (Arg.getOpcode() == ISD::UNDEF) continue;
9320 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9321 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9322 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9323 if (C->getZExtValue() == SplatIdx)
9324 BaseShAmt = InVec.getOperand(1);
9327 if (BaseShAmt.getNode() == 0)
9328 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9329 DAG.getIntPtrConstant(0));
9333 // The shift amount is an i32.
9334 if (EltVT.bitsGT(MVT::i32))
9335 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9336 else if (EltVT.bitsLT(MVT::i32))
9337 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9339 // The shift amount is identical so we can do a vector shift.
9340 SDValue ValOp = N->getOperand(0);
9341 switch (N->getOpcode()) {
9343 llvm_unreachable("Unknown shift opcode!");
9346 if (VT == MVT::v2i64)
9347 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9348 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9350 if (VT == MVT::v4i32)
9351 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9352 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9354 if (VT == MVT::v8i16)
9355 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9356 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9360 if (VT == MVT::v4i32)
9361 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9362 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9364 if (VT == MVT::v8i16)
9365 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9366 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9370 if (VT == MVT::v2i64)
9371 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9372 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9374 if (VT == MVT::v4i32)
9375 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9376 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9378 if (VT == MVT::v8i16)
9379 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9380 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9387 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9388 const X86Subtarget *Subtarget) {
9389 EVT VT = N->getValueType(0);
9390 if (VT != MVT::i64 || !Subtarget->is64Bit())
9393 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9394 SDValue N0 = N->getOperand(0);
9395 SDValue N1 = N->getOperand(1);
9396 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9398 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9401 SDValue ShAmt0 = N0.getOperand(1);
9402 if (ShAmt0.getValueType() != MVT::i8)
9404 SDValue ShAmt1 = N1.getOperand(1);
9405 if (ShAmt1.getValueType() != MVT::i8)
9407 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9408 ShAmt0 = ShAmt0.getOperand(0);
9409 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9410 ShAmt1 = ShAmt1.getOperand(0);
9412 DebugLoc DL = N->getDebugLoc();
9413 unsigned Opc = X86ISD::SHLD;
9414 SDValue Op0 = N0.getOperand(0);
9415 SDValue Op1 = N1.getOperand(0);
9416 if (ShAmt0.getOpcode() == ISD::SUB) {
9418 std::swap(Op0, Op1);
9419 std::swap(ShAmt0, ShAmt1);
9422 if (ShAmt1.getOpcode() == ISD::SUB) {
9423 SDValue Sum = ShAmt1.getOperand(0);
9424 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9425 if (SumC->getSExtValue() == 64 &&
9426 ShAmt1.getOperand(1) == ShAmt0)
9427 return DAG.getNode(Opc, DL, VT,
9429 DAG.getNode(ISD::TRUNCATE, DL,
9432 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9433 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9435 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9436 return DAG.getNode(Opc, DL, VT,
9437 N0.getOperand(0), N1.getOperand(0),
9438 DAG.getNode(ISD::TRUNCATE, DL,
9445 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9446 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9447 const X86Subtarget *Subtarget) {
9448 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9449 // the FP state in cases where an emms may be missing.
9450 // A preferable solution to the general problem is to figure out the right
9451 // places to insert EMMS. This qualifies as a quick hack.
9453 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9454 StoreSDNode *St = cast<StoreSDNode>(N);
9455 EVT VT = St->getValue().getValueType();
9456 if (VT.getSizeInBits() != 64)
9459 const Function *F = DAG.getMachineFunction().getFunction();
9460 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9461 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9462 && Subtarget->hasSSE2();
9463 if ((VT.isVector() ||
9464 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9465 isa<LoadSDNode>(St->getValue()) &&
9466 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9467 St->getChain().hasOneUse() && !St->isVolatile()) {
9468 SDNode* LdVal = St->getValue().getNode();
9470 int TokenFactorIndex = -1;
9471 SmallVector<SDValue, 8> Ops;
9472 SDNode* ChainVal = St->getChain().getNode();
9473 // Must be a store of a load. We currently handle two cases: the load
9474 // is a direct child, and it's under an intervening TokenFactor. It is
9475 // possible to dig deeper under nested TokenFactors.
9476 if (ChainVal == LdVal)
9477 Ld = cast<LoadSDNode>(St->getChain());
9478 else if (St->getValue().hasOneUse() &&
9479 ChainVal->getOpcode() == ISD::TokenFactor) {
9480 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9481 if (ChainVal->getOperand(i).getNode() == LdVal) {
9482 TokenFactorIndex = i;
9483 Ld = cast<LoadSDNode>(St->getValue());
9485 Ops.push_back(ChainVal->getOperand(i));
9489 if (!Ld || !ISD::isNormalLoad(Ld))
9492 // If this is not the MMX case, i.e. we are just turning i64 load/store
9493 // into f64 load/store, avoid the transformation if there are multiple
9494 // uses of the loaded value.
9495 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9498 DebugLoc LdDL = Ld->getDebugLoc();
9499 DebugLoc StDL = N->getDebugLoc();
9500 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9501 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9503 if (Subtarget->is64Bit() || F64IsLegal) {
9504 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9505 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9506 Ld->getBasePtr(), Ld->getSrcValue(),
9507 Ld->getSrcValueOffset(), Ld->isVolatile(),
9508 Ld->getAlignment());
9509 SDValue NewChain = NewLd.getValue(1);
9510 if (TokenFactorIndex != -1) {
9511 Ops.push_back(NewChain);
9512 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9515 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9516 St->getSrcValue(), St->getSrcValueOffset(),
9517 St->isVolatile(), St->getAlignment());
9520 // Otherwise, lower to two pairs of 32-bit loads / stores.
9521 SDValue LoAddr = Ld->getBasePtr();
9522 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9523 DAG.getConstant(4, MVT::i32));
9525 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9526 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9527 Ld->isVolatile(), Ld->getAlignment());
9528 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9529 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9531 MinAlign(Ld->getAlignment(), 4));
9533 SDValue NewChain = LoLd.getValue(1);
9534 if (TokenFactorIndex != -1) {
9535 Ops.push_back(LoLd);
9536 Ops.push_back(HiLd);
9537 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9541 LoAddr = St->getBasePtr();
9542 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9543 DAG.getConstant(4, MVT::i32));
9545 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9546 St->getSrcValue(), St->getSrcValueOffset(),
9547 St->isVolatile(), St->getAlignment());
9548 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9550 St->getSrcValueOffset() + 4,
9552 MinAlign(St->getAlignment(), 4));
9553 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9558 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9559 /// X86ISD::FXOR nodes.
9560 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9561 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9562 // F[X]OR(0.0, x) -> x
9563 // F[X]OR(x, 0.0) -> x
9564 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9565 if (C->getValueAPF().isPosZero())
9566 return N->getOperand(1);
9567 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9568 if (C->getValueAPF().isPosZero())
9569 return N->getOperand(0);
9573 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9574 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9575 // FAND(0.0, x) -> 0.0
9576 // FAND(x, 0.0) -> 0.0
9577 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9578 if (C->getValueAPF().isPosZero())
9579 return N->getOperand(0);
9580 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9581 if (C->getValueAPF().isPosZero())
9582 return N->getOperand(1);
9586 static SDValue PerformBTCombine(SDNode *N,
9588 TargetLowering::DAGCombinerInfo &DCI) {
9589 // BT ignores high bits in the bit index operand.
9590 SDValue Op1 = N->getOperand(1);
9591 if (Op1.hasOneUse()) {
9592 unsigned BitWidth = Op1.getValueSizeInBits();
9593 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9594 APInt KnownZero, KnownOne;
9595 TargetLowering::TargetLoweringOpt TLO(DAG);
9596 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9597 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9598 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9599 DCI.CommitTargetLoweringOpt(TLO);
9604 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9605 SDValue Op = N->getOperand(0);
9606 if (Op.getOpcode() == ISD::BIT_CONVERT)
9607 Op = Op.getOperand(0);
9608 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9609 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9610 VT.getVectorElementType().getSizeInBits() ==
9611 OpVT.getVectorElementType().getSizeInBits()) {
9612 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9617 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9618 // Locked instructions, in turn, have implicit fence semantics (all memory
9619 // operations are flushed before issuing the locked instruction, and the
9620 // are not buffered), so we can fold away the common pattern of
9621 // fence-atomic-fence.
9622 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9623 SDValue atomic = N->getOperand(0);
9624 switch (atomic.getOpcode()) {
9625 case ISD::ATOMIC_CMP_SWAP:
9626 case ISD::ATOMIC_SWAP:
9627 case ISD::ATOMIC_LOAD_ADD:
9628 case ISD::ATOMIC_LOAD_SUB:
9629 case ISD::ATOMIC_LOAD_AND:
9630 case ISD::ATOMIC_LOAD_OR:
9631 case ISD::ATOMIC_LOAD_XOR:
9632 case ISD::ATOMIC_LOAD_NAND:
9633 case ISD::ATOMIC_LOAD_MIN:
9634 case ISD::ATOMIC_LOAD_MAX:
9635 case ISD::ATOMIC_LOAD_UMIN:
9636 case ISD::ATOMIC_LOAD_UMAX:
9642 SDValue fence = atomic.getOperand(0);
9643 if (fence.getOpcode() != ISD::MEMBARRIER)
9646 switch (atomic.getOpcode()) {
9647 case ISD::ATOMIC_CMP_SWAP:
9648 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9649 atomic.getOperand(1), atomic.getOperand(2),
9650 atomic.getOperand(3));
9651 case ISD::ATOMIC_SWAP:
9652 case ISD::ATOMIC_LOAD_ADD:
9653 case ISD::ATOMIC_LOAD_SUB:
9654 case ISD::ATOMIC_LOAD_AND:
9655 case ISD::ATOMIC_LOAD_OR:
9656 case ISD::ATOMIC_LOAD_XOR:
9657 case ISD::ATOMIC_LOAD_NAND:
9658 case ISD::ATOMIC_LOAD_MIN:
9659 case ISD::ATOMIC_LOAD_MAX:
9660 case ISD::ATOMIC_LOAD_UMIN:
9661 case ISD::ATOMIC_LOAD_UMAX:
9662 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9663 atomic.getOperand(1), atomic.getOperand(2));
9669 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9670 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9671 // (and (i32 x86isd::setcc_carry), 1)
9672 // This eliminates the zext. This transformation is necessary because
9673 // ISD::SETCC is always legalized to i8.
9674 DebugLoc dl = N->getDebugLoc();
9675 SDValue N0 = N->getOperand(0);
9676 EVT VT = N->getValueType(0);
9677 if (N0.getOpcode() == ISD::AND &&
9679 N0.getOperand(0).hasOneUse()) {
9680 SDValue N00 = N0.getOperand(0);
9681 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9683 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9684 if (!C || C->getZExtValue() != 1)
9686 return DAG.getNode(ISD::AND, dl, VT,
9687 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9688 N00.getOperand(0), N00.getOperand(1)),
9689 DAG.getConstant(1, VT));
9695 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9696 DAGCombinerInfo &DCI) const {
9697 SelectionDAG &DAG = DCI.DAG;
9698 switch (N->getOpcode()) {
9700 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9701 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9702 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9703 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9706 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9707 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
9708 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9710 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9711 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9712 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9713 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9714 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9715 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9721 //===----------------------------------------------------------------------===//
9722 // X86 Inline Assembly Support
9723 //===----------------------------------------------------------------------===//
9725 static bool LowerToBSwap(CallInst *CI) {
9726 // FIXME: this should verify that we are targetting a 486 or better. If not,
9727 // we will turn this bswap into something that will be lowered to logical ops
9728 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9729 // so don't worry about this.
9731 // Verify this is a simple bswap.
9732 if (CI->getNumOperands() != 2 ||
9733 CI->getType() != CI->getOperand(1)->getType() ||
9734 !CI->getType()->isInteger())
9737 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9738 if (!Ty || Ty->getBitWidth() % 16 != 0)
9741 // Okay, we can do this xform, do so now.
9742 const Type *Tys[] = { Ty };
9743 Module *M = CI->getParent()->getParent()->getParent();
9744 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9746 Value *Op = CI->getOperand(1);
9747 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9749 CI->replaceAllUsesWith(Op);
9750 CI->eraseFromParent();
9754 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9755 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9756 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9758 std::string AsmStr = IA->getAsmString();
9760 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9761 SmallVector<StringRef, 4> AsmPieces;
9762 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9764 switch (AsmPieces.size()) {
9765 default: return false;
9767 AsmStr = AsmPieces[0];
9769 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9772 if (AsmPieces.size() == 2 &&
9773 (AsmPieces[0] == "bswap" ||
9774 AsmPieces[0] == "bswapq" ||
9775 AsmPieces[0] == "bswapl") &&
9776 (AsmPieces[1] == "$0" ||
9777 AsmPieces[1] == "${0:q}")) {
9778 // No need to check constraints, nothing other than the equivalent of
9779 // "=r,0" would be valid here.
9780 return LowerToBSwap(CI);
9782 // rorw $$8, ${0:w} --> llvm.bswap.i16
9783 if (CI->getType()->isInteger(16) &&
9784 AsmPieces.size() == 3 &&
9785 AsmPieces[0] == "rorw" &&
9786 AsmPieces[1] == "$$8," &&
9787 AsmPieces[2] == "${0:w}" &&
9788 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9789 return LowerToBSwap(CI);
9793 if (CI->getType()->isInteger(64) &&
9794 Constraints.size() >= 2 &&
9795 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9796 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9797 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9798 SmallVector<StringRef, 4> Words;
9799 SplitString(AsmPieces[0], Words, " \t");
9800 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9802 SplitString(AsmPieces[1], Words, " \t");
9803 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9805 SplitString(AsmPieces[2], Words, " \t,");
9806 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9807 Words[2] == "%edx") {
9808 return LowerToBSwap(CI);
9820 /// getConstraintType - Given a constraint letter, return the type of
9821 /// constraint it is for this target.
9822 X86TargetLowering::ConstraintType
9823 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9824 if (Constraint.size() == 1) {
9825 switch (Constraint[0]) {
9837 return C_RegisterClass;
9845 return TargetLowering::getConstraintType(Constraint);
9848 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9849 /// with another that has more specific requirements based on the type of the
9850 /// corresponding operand.
9851 const char *X86TargetLowering::
9852 LowerXConstraint(EVT ConstraintVT) const {
9853 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9854 // 'f' like normal targets.
9855 if (ConstraintVT.isFloatingPoint()) {
9856 if (Subtarget->hasSSE2())
9858 if (Subtarget->hasSSE1())
9862 return TargetLowering::LowerXConstraint(ConstraintVT);
9865 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9866 /// vector. If it is invalid, don't add anything to Ops.
9867 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9870 std::vector<SDValue>&Ops,
9871 SelectionDAG &DAG) const {
9872 SDValue Result(0, 0);
9874 switch (Constraint) {
9877 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9878 if (C->getZExtValue() <= 31) {
9879 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9885 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9886 if (C->getZExtValue() <= 63) {
9887 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9893 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9894 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9895 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9901 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9902 if (C->getZExtValue() <= 255) {
9903 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9909 // 32-bit signed value
9910 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9911 const ConstantInt *CI = C->getConstantIntValue();
9912 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9913 C->getSExtValue())) {
9914 // Widen to 64 bits here to get it sign extended.
9915 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9918 // FIXME gcc accepts some relocatable values here too, but only in certain
9919 // memory models; it's complicated.
9924 // 32-bit unsigned value
9925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9926 const ConstantInt *CI = C->getConstantIntValue();
9927 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9928 C->getZExtValue())) {
9929 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9933 // FIXME gcc accepts some relocatable values here too, but only in certain
9934 // memory models; it's complicated.
9938 // Literal immediates are always ok.
9939 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9940 // Widen to 64 bits here to get it sign extended.
9941 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9945 // If we are in non-pic codegen mode, we allow the address of a global (with
9946 // an optional displacement) to be used with 'i'.
9947 GlobalAddressSDNode *GA = 0;
9950 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9952 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9953 Offset += GA->getOffset();
9955 } else if (Op.getOpcode() == ISD::ADD) {
9956 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9957 Offset += C->getZExtValue();
9958 Op = Op.getOperand(0);
9961 } else if (Op.getOpcode() == ISD::SUB) {
9962 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9963 Offset += -C->getZExtValue();
9964 Op = Op.getOperand(0);
9969 // Otherwise, this isn't something we can handle, reject it.
9973 GlobalValue *GV = GA->getGlobal();
9974 // If we require an extra load to get this address, as in PIC mode, we
9976 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9977 getTargetMachine())))
9981 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9983 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9989 if (Result.getNode()) {
9990 Ops.push_back(Result);
9993 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9997 std::vector<unsigned> X86TargetLowering::
9998 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10000 if (Constraint.size() == 1) {
10001 // FIXME: not handling fp-stack yet!
10002 switch (Constraint[0]) { // GCC X86 Constraint Letters
10003 default: break; // Unknown constraint letter
10004 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10005 if (Subtarget->is64Bit()) {
10006 if (VT == MVT::i32)
10007 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10008 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10009 X86::R10D,X86::R11D,X86::R12D,
10010 X86::R13D,X86::R14D,X86::R15D,
10011 X86::EBP, X86::ESP, 0);
10012 else if (VT == MVT::i16)
10013 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10014 X86::SI, X86::DI, X86::R8W,X86::R9W,
10015 X86::R10W,X86::R11W,X86::R12W,
10016 X86::R13W,X86::R14W,X86::R15W,
10017 X86::BP, X86::SP, 0);
10018 else if (VT == MVT::i8)
10019 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10020 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10021 X86::R10B,X86::R11B,X86::R12B,
10022 X86::R13B,X86::R14B,X86::R15B,
10023 X86::BPL, X86::SPL, 0);
10025 else if (VT == MVT::i64)
10026 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10027 X86::RSI, X86::RDI, X86::R8, X86::R9,
10028 X86::R10, X86::R11, X86::R12,
10029 X86::R13, X86::R14, X86::R15,
10030 X86::RBP, X86::RSP, 0);
10034 // 32-bit fallthrough
10035 case 'Q': // Q_REGS
10036 if (VT == MVT::i32)
10037 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10038 else if (VT == MVT::i16)
10039 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10040 else if (VT == MVT::i8)
10041 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10042 else if (VT == MVT::i64)
10043 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10048 return std::vector<unsigned>();
10051 std::pair<unsigned, const TargetRegisterClass*>
10052 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10054 // First, see if this is a constraint that directly corresponds to an LLVM
10056 if (Constraint.size() == 1) {
10057 // GCC Constraint Letters
10058 switch (Constraint[0]) {
10060 case 'r': // GENERAL_REGS
10061 case 'l': // INDEX_REGS
10063 return std::make_pair(0U, X86::GR8RegisterClass);
10064 if (VT == MVT::i16)
10065 return std::make_pair(0U, X86::GR16RegisterClass);
10066 if (VT == MVT::i32 || !Subtarget->is64Bit())
10067 return std::make_pair(0U, X86::GR32RegisterClass);
10068 return std::make_pair(0U, X86::GR64RegisterClass);
10069 case 'R': // LEGACY_REGS
10071 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10072 if (VT == MVT::i16)
10073 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10074 if (VT == MVT::i32 || !Subtarget->is64Bit())
10075 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10076 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10077 case 'f': // FP Stack registers.
10078 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10079 // value to the correct fpstack register class.
10080 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10081 return std::make_pair(0U, X86::RFP32RegisterClass);
10082 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10083 return std::make_pair(0U, X86::RFP64RegisterClass);
10084 return std::make_pair(0U, X86::RFP80RegisterClass);
10085 case 'y': // MMX_REGS if MMX allowed.
10086 if (!Subtarget->hasMMX()) break;
10087 return std::make_pair(0U, X86::VR64RegisterClass);
10088 case 'Y': // SSE_REGS if SSE2 allowed
10089 if (!Subtarget->hasSSE2()) break;
10091 case 'x': // SSE_REGS if SSE1 allowed
10092 if (!Subtarget->hasSSE1()) break;
10094 switch (VT.getSimpleVT().SimpleTy) {
10096 // Scalar SSE types.
10099 return std::make_pair(0U, X86::FR32RegisterClass);
10102 return std::make_pair(0U, X86::FR64RegisterClass);
10110 return std::make_pair(0U, X86::VR128RegisterClass);
10116 // Use the default implementation in TargetLowering to convert the register
10117 // constraint into a member of a register class.
10118 std::pair<unsigned, const TargetRegisterClass*> Res;
10119 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10121 // Not found as a standard register?
10122 if (Res.second == 0) {
10123 // Map st(0) -> st(7) -> ST0
10124 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10125 tolower(Constraint[1]) == 's' &&
10126 tolower(Constraint[2]) == 't' &&
10127 Constraint[3] == '(' &&
10128 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10129 Constraint[5] == ')' &&
10130 Constraint[6] == '}') {
10132 Res.first = X86::ST0+Constraint[4]-'0';
10133 Res.second = X86::RFP80RegisterClass;
10137 // GCC allows "st(0)" to be called just plain "st".
10138 if (StringRef("{st}").equals_lower(Constraint)) {
10139 Res.first = X86::ST0;
10140 Res.second = X86::RFP80RegisterClass;
10145 if (StringRef("{flags}").equals_lower(Constraint)) {
10146 Res.first = X86::EFLAGS;
10147 Res.second = X86::CCRRegisterClass;
10151 // 'A' means EAX + EDX.
10152 if (Constraint == "A") {
10153 Res.first = X86::EAX;
10154 Res.second = X86::GR32_ADRegisterClass;
10160 // Otherwise, check to see if this is a register class of the wrong value
10161 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10162 // turn into {ax},{dx}.
10163 if (Res.second->hasType(VT))
10164 return Res; // Correct type already, nothing to do.
10166 // All of the single-register GCC register classes map their values onto
10167 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10168 // really want an 8-bit or 32-bit register, map to the appropriate register
10169 // class and return the appropriate register.
10170 if (Res.second == X86::GR16RegisterClass) {
10171 if (VT == MVT::i8) {
10172 unsigned DestReg = 0;
10173 switch (Res.first) {
10175 case X86::AX: DestReg = X86::AL; break;
10176 case X86::DX: DestReg = X86::DL; break;
10177 case X86::CX: DestReg = X86::CL; break;
10178 case X86::BX: DestReg = X86::BL; break;
10181 Res.first = DestReg;
10182 Res.second = X86::GR8RegisterClass;
10184 } else if (VT == MVT::i32) {
10185 unsigned DestReg = 0;
10186 switch (Res.first) {
10188 case X86::AX: DestReg = X86::EAX; break;
10189 case X86::DX: DestReg = X86::EDX; break;
10190 case X86::CX: DestReg = X86::ECX; break;
10191 case X86::BX: DestReg = X86::EBX; break;
10192 case X86::SI: DestReg = X86::ESI; break;
10193 case X86::DI: DestReg = X86::EDI; break;
10194 case X86::BP: DestReg = X86::EBP; break;
10195 case X86::SP: DestReg = X86::ESP; break;
10198 Res.first = DestReg;
10199 Res.second = X86::GR32RegisterClass;
10201 } else if (VT == MVT::i64) {
10202 unsigned DestReg = 0;
10203 switch (Res.first) {
10205 case X86::AX: DestReg = X86::RAX; break;
10206 case X86::DX: DestReg = X86::RDX; break;
10207 case X86::CX: DestReg = X86::RCX; break;
10208 case X86::BX: DestReg = X86::RBX; break;
10209 case X86::SI: DestReg = X86::RSI; break;
10210 case X86::DI: DestReg = X86::RDI; break;
10211 case X86::BP: DestReg = X86::RBP; break;
10212 case X86::SP: DestReg = X86::RSP; break;
10215 Res.first = DestReg;
10216 Res.second = X86::GR64RegisterClass;
10219 } else if (Res.second == X86::FR32RegisterClass ||
10220 Res.second == X86::FR64RegisterClass ||
10221 Res.second == X86::VR128RegisterClass) {
10222 // Handle references to XMM physical registers that got mapped into the
10223 // wrong class. This can happen with constraints like {xmm0} where the
10224 // target independent register mapper will just pick the first match it can
10225 // find, ignoring the required type.
10226 if (VT == MVT::f32)
10227 Res.second = X86::FR32RegisterClass;
10228 else if (VT == MVT::f64)
10229 Res.second = X86::FR64RegisterClass;
10230 else if (X86::VR128RegisterClass->hasType(VT))
10231 Res.second = X86::VR128RegisterClass;
10237 //===----------------------------------------------------------------------===//
10238 // X86 Widen vector type
10239 //===----------------------------------------------------------------------===//
10241 /// getWidenVectorType: given a vector type, returns the type to widen
10242 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
10243 /// If there is no vector type that we want to widen to, returns MVT::Other
10244 /// When and where to widen is target dependent based on the cost of
10245 /// scalarizing vs using the wider vector type.
10247 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
10248 assert(VT.isVector());
10249 if (isTypeLegal(VT))
10252 // TODO: In computeRegisterProperty, we can compute the list of legal vector
10253 // type based on element type. This would speed up our search (though
10254 // it may not be worth it since the size of the list is relatively
10256 EVT EltVT = VT.getVectorElementType();
10257 unsigned NElts = VT.getVectorNumElements();
10259 // On X86, it make sense to widen any vector wider than 1
10263 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
10264 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
10265 EVT SVT = (MVT::SimpleValueType)nVT;
10267 if (isTypeLegal(SVT) &&
10268 SVT.getVectorElementType() == EltVT &&
10269 SVT.getVectorNumElements() > NElts)