1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
57 using namespace dwarf;
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> UseRegMask("x86-use-regmask",
62 cl::desc("Use register masks for x86 calls"));
64 // Forward declarations.
65 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
68 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
69 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
70 /// simple subregister reference. Idx is an index in the 128 bits we
71 /// want. It need not be aligned to a 128-bit bounday. That makes
72 /// lowering EXTRACT_VECTOR_ELT operations easier.
73 static SDValue Extract128BitVector(SDValue Vec,
77 EVT VT = Vec.getValueType();
78 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
79 EVT ElVT = VT.getVectorElementType();
80 int Factor = VT.getSizeInBits()/128;
81 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
82 VT.getVectorNumElements()/Factor);
84 // Extract from UNDEF is UNDEF.
85 if (Vec.getOpcode() == ISD::UNDEF)
86 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
88 if (isa<ConstantSDNode>(Idx)) {
89 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
91 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
92 // we can match to VEXTRACTF128.
93 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
95 // This is the index of the first element of the 128-bit chunk
97 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
100 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
101 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
110 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
111 /// sets things up to match to an AVX VINSERTF128 instruction or a
112 /// simple superregister reference. Idx is an index in the 128 bits
113 /// we want. It need not be aligned to a 128-bit bounday. That makes
114 /// lowering INSERT_VECTOR_ELT operations easier.
115 static SDValue Insert128BitVector(SDValue Result,
120 if (isa<ConstantSDNode>(Idx)) {
121 EVT VT = Vec.getValueType();
122 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
124 EVT ElVT = VT.getVectorElementType();
125 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant 128 bits.
129 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
131 // This is the index of the first element of the 128-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
136 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
137 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
145 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
146 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
147 bool is64Bit = Subtarget->is64Bit();
149 if (Subtarget->isTargetEnvMacho()) {
151 return new X8664_MachoTargetObjectFile();
152 return new TargetLoweringObjectFileMachO();
155 if (Subtarget->isTargetELF())
156 return new TargetLoweringObjectFileELF();
157 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
158 return new TargetLoweringObjectFileCOFF();
159 llvm_unreachable("unknown subtarget type");
162 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
163 : TargetLowering(TM, createTLOF(TM)) {
164 Subtarget = &TM.getSubtarget<X86Subtarget>();
165 X86ScalarSSEf64 = Subtarget->hasSSE2();
166 X86ScalarSSEf32 = Subtarget->hasSSE1();
167 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
169 RegInfo = TM.getRegisterInfo();
170 TD = getTargetData();
172 // Set up the TargetLowering object.
173 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
175 // X86 is weird, it always uses i8 for shift amounts and setcc results.
176 setBooleanContents(ZeroOrOneBooleanContent);
177 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
178 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
180 // For 64-bit since we have so many registers use the ILP scheduler, for
181 // 32-bit code use the register pressure specific scheduling.
182 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
183 if (Subtarget->is64Bit())
184 setSchedulingPreference(Sched::ILP);
185 else if (Subtarget->isAtom())
186 setSchedulingPreference(Sched::Hybrid);
188 setSchedulingPreference(Sched::RegPressure);
189 setStackPointerRegisterToSaveRestore(X86StackPtr);
191 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
192 // Setup Windows compiler runtime calls.
193 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
194 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
195 setLibcallName(RTLIB::SREM_I64, "_allrem");
196 setLibcallName(RTLIB::UREM_I64, "_aullrem");
197 setLibcallName(RTLIB::MUL_I64, "_allmul");
198 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
199 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
200 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
201 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
209 if (Subtarget->isTargetDarwin()) {
210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
211 setUseUnderscoreSetJmp(false);
212 setUseUnderscoreLongJmp(false);
213 } else if (Subtarget->isTargetMingw()) {
214 // MS runtime is weird: it exports _setjmp, but longjmp!
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(false);
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(true);
222 // Set up the register classes.
223 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
224 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
225 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
226 if (Subtarget->is64Bit())
227 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 // We don't accept any truncstore of integer registers.
232 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
233 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
235 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
239 // SETOEQ and SETUNE require checking two conditions.
240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 } else if (!TM.Options.UseSoftFloat) {
257 // We have an algorithm for SSE2->double, and we turn this into a
258 // 64-bit FILD followed by conditional FADD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
260 // We have an algorithm for SSE2, and we turn this into a 64-bit
261 // FILD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
270 if (!TM.Options.UseSoftFloat) {
271 // SSE has no i16 to fp conversion, only i32
272 if (X86ScalarSSEf32) {
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 // f32 and f64 cases are Legal, f80 case is not
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
286 // are Legal, f80 is custom lowered.
287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
295 if (X86ScalarSSEf32) {
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
297 // f32 and f64 cases are Legal, f80 case is not
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 // Handle FP_TO_UINT by promoting the destination to a larger signed
306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
310 if (Subtarget->is64Bit()) {
311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
313 } else if (!TM.Options.UseSoftFloat) {
314 // Since AVX is a superset of SSE3, only check for SSE here.
315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 // Promote the i8 variants and force them on up to i32 which has a shorter
380 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
381 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
383 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
384 if (Subtarget->hasBMI()) {
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
387 if (Subtarget->is64Bit())
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
390 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
391 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
392 if (Subtarget->is64Bit())
393 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
396 if (Subtarget->hasLZCNT()) {
397 // When promoting the i8 variants, force them to i32 for a shorter
399 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
400 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
402 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
405 if (Subtarget->is64Bit())
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
408 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
414 if (Subtarget->is64Bit()) {
415 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
420 if (Subtarget->hasPOPCNT()) {
421 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
423 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
424 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
425 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
426 if (Subtarget->is64Bit())
427 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
430 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
431 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
433 // These should be promoted to a larger select which is supported.
434 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
435 // X86 wants to expand cmov itself.
436 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
437 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
438 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
439 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
440 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
442 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
443 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
445 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
446 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
448 if (Subtarget->is64Bit()) {
449 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
452 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
455 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
456 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
457 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
458 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
459 if (Subtarget->is64Bit())
460 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
461 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
462 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
463 if (Subtarget->is64Bit()) {
464 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
465 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
466 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
467 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
468 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
470 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
471 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
472 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
473 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
474 if (Subtarget->is64Bit()) {
475 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
476 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
477 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
480 if (Subtarget->hasSSE1())
481 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
483 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
484 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
486 // On X86 and X86-64, atomic operations are lowered to locked instructions.
487 // Locked instructions, in turn, have implicit fence semantics (all memory
488 // operations are flushed before issuing the locked instruction, and they
489 // are not buffered), so we can fold away the common pattern of
490 // fence-atomic-fence.
491 setShouldFoldAtomicFences(true);
493 // Expand certain atomics
494 for (unsigned i = 0, e = 4; i != e; ++i) {
496 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
497 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
498 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
501 if (!Subtarget->is64Bit()) {
502 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
512 if (Subtarget->hasCmpxchg16b()) {
513 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
516 // FIXME - use subtarget debug flags
517 if (!Subtarget->isTargetDarwin() &&
518 !Subtarget->isTargetELF() &&
519 !Subtarget->isTargetCygMing()) {
520 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
523 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
524 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
526 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
527 if (Subtarget->is64Bit()) {
528 setExceptionPointerRegister(X86::RAX);
529 setExceptionSelectorRegister(X86::RDX);
531 setExceptionPointerRegister(X86::EAX);
532 setExceptionSelectorRegister(X86::EDX);
534 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
537 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
538 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
540 setOperationAction(ISD::TRAP, MVT::Other, Legal);
542 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
543 setOperationAction(ISD::VASTART , MVT::Other, Custom);
544 setOperationAction(ISD::VAEND , MVT::Other, Expand);
545 if (Subtarget->is64Bit()) {
546 setOperationAction(ISD::VAARG , MVT::Other, Custom);
547 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
549 setOperationAction(ISD::VAARG , MVT::Other, Expand);
550 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
553 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
554 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
556 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
559 else if (TM.Options.EnableSegmentedStacks)
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Custom);
563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
564 MVT::i64 : MVT::i32, Expand);
566 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
567 // f32 and f64 use SSE.
568 // Set up the FP register classes.
569 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
570 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
572 // Use ANDPD to simulate FABS.
573 setOperationAction(ISD::FABS , MVT::f64, Custom);
574 setOperationAction(ISD::FABS , MVT::f32, Custom);
576 // Use XORP to simulate FNEG.
577 setOperationAction(ISD::FNEG , MVT::f64, Custom);
578 setOperationAction(ISD::FNEG , MVT::f32, Custom);
580 // Use ANDPD and ORPD to simulate FCOPYSIGN.
581 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
582 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
584 // Lower this to FGETSIGNx86 plus an AND.
585 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
586 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
588 // We don't support sin/cos/fmod
589 setOperationAction(ISD::FSIN , MVT::f64, Expand);
590 setOperationAction(ISD::FCOS , MVT::f64, Expand);
591 setOperationAction(ISD::FSIN , MVT::f32, Expand);
592 setOperationAction(ISD::FCOS , MVT::f32, Expand);
594 // Expand FP immediates into loads from the stack, except for the special
596 addLegalFPImmediate(APFloat(+0.0)); // xorpd
597 addLegalFPImmediate(APFloat(+0.0f)); // xorps
598 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
599 // Use SSE for f32, x87 for f64.
600 // Set up the FP register classes.
601 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
602 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
604 // Use ANDPS to simulate FABS.
605 setOperationAction(ISD::FABS , MVT::f32, Custom);
607 // Use XORP to simulate FNEG.
608 setOperationAction(ISD::FNEG , MVT::f32, Custom);
610 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
612 // Use ANDPS and ORPS to simulate FCOPYSIGN.
613 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
614 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
616 // We don't support sin/cos/fmod
617 setOperationAction(ISD::FSIN , MVT::f32, Expand);
618 setOperationAction(ISD::FCOS , MVT::f32, Expand);
620 // Special cases we handle for FP constants.
621 addLegalFPImmediate(APFloat(+0.0f)); // xorps
622 addLegalFPImmediate(APFloat(+0.0)); // FLD0
623 addLegalFPImmediate(APFloat(+1.0)); // FLD1
624 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
625 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
627 if (!TM.Options.UnsafeFPMath) {
628 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
629 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
631 } else if (!TM.Options.UseSoftFloat) {
632 // f32 and f64 in x87.
633 // Set up the FP register classes.
634 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
635 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
637 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
638 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
639 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
640 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
644 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
646 addLegalFPImmediate(APFloat(+0.0)); // FLD0
647 addLegalFPImmediate(APFloat(+1.0)); // FLD1
648 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
649 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
650 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
651 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
652 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
653 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
656 // We don't support FMA.
657 setOperationAction(ISD::FMA, MVT::f64, Expand);
658 setOperationAction(ISD::FMA, MVT::f32, Expand);
660 // Long double always uses X87.
661 if (!TM.Options.UseSoftFloat) {
662 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
663 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
664 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
666 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
667 addLegalFPImmediate(TmpFlt); // FLD0
669 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
672 APFloat TmpFlt2(+1.0);
673 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
675 addLegalFPImmediate(TmpFlt2); // FLD1
676 TmpFlt2.changeSign();
677 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
680 if (!TM.Options.UnsafeFPMath) {
681 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
682 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
685 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
686 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
687 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
688 setOperationAction(ISD::FRINT, MVT::f80, Expand);
689 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
690 setOperationAction(ISD::FMA, MVT::f80, Expand);
693 // Always use a library call for pow.
694 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
695 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
696 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
698 setOperationAction(ISD::FLOG, MVT::f80, Expand);
699 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
700 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
701 setOperationAction(ISD::FEXP, MVT::f80, Expand);
702 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
704 // First set operation action for all vector types to either promote
705 // (for widening) or expand (for scalarization). Then we will selectively
706 // turn on ones that can be effectively codegen'd.
707 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
708 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
709 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
761 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
766 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
767 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
768 setTruncStoreAction((MVT::SimpleValueType)VT,
769 (MVT::SimpleValueType)InnerVT, Expand);
770 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
771 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
775 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
776 // with -msoft-float, disable use of MMX as well.
777 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
778 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
779 // No operations on x86mmx supported, everything uses intrinsics.
782 // MMX-sized vectors (other than x86mmx) are expected to be expanded
783 // into smaller operations.
784 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
785 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
786 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
787 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
788 setOperationAction(ISD::AND, MVT::v8i8, Expand);
789 setOperationAction(ISD::AND, MVT::v4i16, Expand);
790 setOperationAction(ISD::AND, MVT::v2i32, Expand);
791 setOperationAction(ISD::AND, MVT::v1i64, Expand);
792 setOperationAction(ISD::OR, MVT::v8i8, Expand);
793 setOperationAction(ISD::OR, MVT::v4i16, Expand);
794 setOperationAction(ISD::OR, MVT::v2i32, Expand);
795 setOperationAction(ISD::OR, MVT::v1i64, Expand);
796 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
797 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
798 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
799 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
804 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
805 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
806 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
807 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
808 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
810 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
814 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
815 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
817 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
819 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
820 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
821 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
822 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
823 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
824 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
825 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
827 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
828 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
831 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
832 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
834 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
835 // registers cannot be used even for integer operations.
836 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
837 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
838 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
839 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
841 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
842 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
843 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
844 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
845 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
846 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
847 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
848 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
849 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
850 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
851 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
853 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
854 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
855 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
856 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
858 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
859 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
860 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
861 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
863 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
865 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
875 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
876 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
877 EVT VT = (MVT::SimpleValueType)i;
878 // Do not attempt to custom lower non-power-of-2 vectors
879 if (!isPowerOf2_32(VT.getVectorNumElements()))
881 // Do not attempt to custom lower non-128-bit vectors
882 if (!VT.is128BitVector())
884 setOperationAction(ISD::BUILD_VECTOR,
885 VT.getSimpleVT().SimpleTy, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE,
887 VT.getSimpleVT().SimpleTy, Custom);
888 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
889 VT.getSimpleVT().SimpleTy, Custom);
892 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
894 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
897 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
899 if (Subtarget->is64Bit()) {
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
904 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
905 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
906 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
909 // Do not attempt to promote non-128-bit vectors
910 if (!VT.is128BitVector())
913 setOperationAction(ISD::AND, SVT, Promote);
914 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
915 setOperationAction(ISD::OR, SVT, Promote);
916 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
917 setOperationAction(ISD::XOR, SVT, Promote);
918 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
919 setOperationAction(ISD::LOAD, SVT, Promote);
920 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
921 setOperationAction(ISD::SELECT, SVT, Promote);
922 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
925 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
927 // Custom lower v2i64 and v2f64 selects.
928 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
929 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
930 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
931 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
933 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
934 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 if (Subtarget->hasSSE41()) {
938 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
939 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
940 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
941 setOperationAction(ISD::FRINT, MVT::f32, Legal);
942 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
943 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
944 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
945 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
946 setOperationAction(ISD::FRINT, MVT::f64, Legal);
947 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
949 // FIXME: Do we need to handle scalar-to-vector here?
950 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
958 // i8 and i16 vectors are custom , because the source register and source
959 // source memory operand types are not the same width. f32 vectors are
960 // custom since the immediate controlling the insert encodes additional
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
972 // FIXME: these should be Legal but thats only for the case where
973 // the index is constant. For now custom expand to deal with that.
974 if (Subtarget->is64Bit()) {
975 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
976 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
980 if (Subtarget->hasSSE2()) {
981 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
985 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
987 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
988 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
990 if (Subtarget->hasAVX2()) {
991 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
995 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
997 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1003 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1005 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1009 if (Subtarget->hasSSE42())
1010 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1012 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1013 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1014 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1015 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1016 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1017 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1018 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1020 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1021 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1022 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1024 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1031 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1038 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1040 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1049 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1056 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1063 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1064 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1067 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1072 if (Subtarget->hasAVX2()) {
1073 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1074 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1075 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1076 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1078 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1079 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1080 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1081 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1083 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1084 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1085 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1086 // Don't lower v32i8 because there is no 128-bit byte mul
1088 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1090 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1094 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1098 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1099 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1100 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1101 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1103 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1104 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1105 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1106 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1108 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1109 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1110 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1111 // Don't lower v32i8 because there is no 128-bit byte mul
1113 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1117 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1122 // Custom lower several nodes for 256-bit types.
1123 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1124 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1125 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1128 // Extract subvector is special because the value type
1129 // (result) is 128-bit but the source is 256-bit wide.
1130 if (VT.is128BitVector())
1131 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1133 // Do not attempt to custom lower other non-256-bit vectors
1134 if (!VT.is256BitVector())
1137 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1138 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1141 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1142 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1145 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1146 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1147 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1150 // Do not attempt to promote non-256-bit vectors
1151 if (!VT.is256BitVector())
1154 setOperationAction(ISD::AND, SVT, Promote);
1155 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1156 setOperationAction(ISD::OR, SVT, Promote);
1157 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1158 setOperationAction(ISD::XOR, SVT, Promote);
1159 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1160 setOperationAction(ISD::LOAD, SVT, Promote);
1161 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1162 setOperationAction(ISD::SELECT, SVT, Promote);
1163 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1167 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1168 // of this type with custom code.
1169 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1170 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1171 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1175 // We want to custom lower some of our intrinsics.
1176 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1179 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1180 // handle type legalization for these operations here.
1182 // FIXME: We really should do custom legalization for addition and
1183 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1184 // than generic legalization for 64-bit multiplication-with-overflow, though.
1185 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1186 // Add/Sub/Mul with overflow operations are custom lowered.
1188 setOperationAction(ISD::SADDO, VT, Custom);
1189 setOperationAction(ISD::UADDO, VT, Custom);
1190 setOperationAction(ISD::SSUBO, VT, Custom);
1191 setOperationAction(ISD::USUBO, VT, Custom);
1192 setOperationAction(ISD::SMULO, VT, Custom);
1193 setOperationAction(ISD::UMULO, VT, Custom);
1196 // There are no 8-bit 3-address imul/mul instructions
1197 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1198 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1200 if (!Subtarget->is64Bit()) {
1201 // These libcalls are not available in 32-bit.
1202 setLibcallName(RTLIB::SHL_I128, 0);
1203 setLibcallName(RTLIB::SRL_I128, 0);
1204 setLibcallName(RTLIB::SRA_I128, 0);
1207 // We have target-specific dag combine patterns for the following nodes:
1208 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1209 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1210 setTargetDAGCombine(ISD::VSELECT);
1211 setTargetDAGCombine(ISD::SELECT);
1212 setTargetDAGCombine(ISD::SHL);
1213 setTargetDAGCombine(ISD::SRA);
1214 setTargetDAGCombine(ISD::SRL);
1215 setTargetDAGCombine(ISD::OR);
1216 setTargetDAGCombine(ISD::AND);
1217 setTargetDAGCombine(ISD::ADD);
1218 setTargetDAGCombine(ISD::FADD);
1219 setTargetDAGCombine(ISD::FSUB);
1220 setTargetDAGCombine(ISD::SUB);
1221 setTargetDAGCombine(ISD::LOAD);
1222 setTargetDAGCombine(ISD::STORE);
1223 setTargetDAGCombine(ISD::ZERO_EXTEND);
1224 setTargetDAGCombine(ISD::TRUNCATE);
1225 setTargetDAGCombine(ISD::SINT_TO_FP);
1226 if (Subtarget->is64Bit())
1227 setTargetDAGCombine(ISD::MUL);
1228 if (Subtarget->hasBMI())
1229 setTargetDAGCombine(ISD::XOR);
1231 computeRegisterProperties();
1233 // On Darwin, -Os means optimize for size without hurting performance,
1234 // do not reduce the limit.
1235 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1236 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1237 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1238 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1239 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1240 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 setPrefLoopAlignment(4); // 2^4 bytes.
1242 benefitFromCodePlacementOpt = true;
1244 setPrefFunctionAlignment(4); // 2^4 bytes.
1248 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1249 if (!VT.isVector()) return MVT::i8;
1250 return VT.changeVectorElementTypeToInteger();
1254 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1255 /// the desired ByVal argument alignment.
1256 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1259 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1260 if (VTy->getBitWidth() == 128)
1262 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1263 unsigned EltAlign = 0;
1264 getMaxByValAlign(ATy->getElementType(), EltAlign);
1265 if (EltAlign > MaxAlign)
1266 MaxAlign = EltAlign;
1267 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1268 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1269 unsigned EltAlign = 0;
1270 getMaxByValAlign(STy->getElementType(i), EltAlign);
1271 if (EltAlign > MaxAlign)
1272 MaxAlign = EltAlign;
1280 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1281 /// function arguments in the caller parameter area. For X86, aggregates
1282 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1283 /// are at 4-byte boundaries.
1284 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1285 if (Subtarget->is64Bit()) {
1286 // Max of 8 and alignment of type.
1287 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1294 if (Subtarget->hasSSE1())
1295 getMaxByValAlign(Ty, Align);
1299 /// getOptimalMemOpType - Returns the target specific optimal type for load
1300 /// and store operations as a result of memset, memcpy, and memmove
1301 /// lowering. If DstAlign is zero that means it's safe to destination
1302 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1303 /// means there isn't a need to check it against alignment requirement,
1304 /// probably because the source does not need to be loaded. If
1305 /// 'IsZeroVal' is true, that means it's safe to return a
1306 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1307 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1308 /// constant so it does not need to be loaded.
1309 /// It returns EVT::Other if the type should be determined using generic
1310 /// target-independent logic.
1312 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1313 unsigned DstAlign, unsigned SrcAlign,
1316 MachineFunction &MF) const {
1317 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1318 // linux. This is because the stack realignment code can't handle certain
1319 // cases like PR2962. This should be removed when PR2962 is fixed.
1320 const Function *F = MF.getFunction();
1322 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1324 (Subtarget->isUnalignedMemAccessFast() ||
1325 ((DstAlign == 0 || DstAlign >= 16) &&
1326 (SrcAlign == 0 || SrcAlign >= 16))) &&
1327 Subtarget->getStackAlignment() >= 16) {
1328 if (Subtarget->getStackAlignment() >= 32) {
1329 if (Subtarget->hasAVX2())
1331 if (Subtarget->hasAVX())
1334 if (Subtarget->hasSSE2())
1336 if (Subtarget->hasSSE1())
1338 } else if (!MemcpyStrSrc && Size >= 8 &&
1339 !Subtarget->is64Bit() &&
1340 Subtarget->getStackAlignment() >= 8 &&
1341 Subtarget->hasSSE2()) {
1342 // Do not use f64 to lower memcpy if source is string constant. It's
1343 // better to use i32 to avoid the loads.
1347 if (Subtarget->is64Bit() && Size >= 8)
1352 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1353 /// current function. The returned value is a member of the
1354 /// MachineJumpTableInfo::JTEntryKind enum.
1355 unsigned X86TargetLowering::getJumpTableEncoding() const {
1356 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1358 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1359 Subtarget->isPICStyleGOT())
1360 return MachineJumpTableInfo::EK_Custom32;
1362 // Otherwise, use the normal jump table encoding heuristics.
1363 return TargetLowering::getJumpTableEncoding();
1367 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1368 const MachineBasicBlock *MBB,
1369 unsigned uid,MCContext &Ctx) const{
1370 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1371 Subtarget->isPICStyleGOT());
1372 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1374 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1375 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1378 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1380 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1381 SelectionDAG &DAG) const {
1382 if (!Subtarget->is64Bit())
1383 // This doesn't have DebugLoc associated with it, but is not really the
1384 // same as a Register.
1385 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1389 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1390 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1392 const MCExpr *X86TargetLowering::
1393 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1394 MCContext &Ctx) const {
1395 // X86-64 uses RIP relative addressing based on the jump table label.
1396 if (Subtarget->isPICStyleRIPRel())
1397 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1399 // Otherwise, the reference is relative to the PIC base.
1400 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1403 // FIXME: Why this routine is here? Move to RegInfo!
1404 std::pair<const TargetRegisterClass*, uint8_t>
1405 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1406 const TargetRegisterClass *RRC = 0;
1408 switch (VT.getSimpleVT().SimpleTy) {
1410 return TargetLowering::findRepresentativeClass(VT);
1411 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1412 RRC = (Subtarget->is64Bit()
1413 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1416 RRC = X86::VR64RegisterClass;
1418 case MVT::f32: case MVT::f64:
1419 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1420 case MVT::v4f32: case MVT::v2f64:
1421 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1423 RRC = X86::VR128RegisterClass;
1426 return std::make_pair(RRC, Cost);
1429 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1430 unsigned &Offset) const {
1431 if (!Subtarget->isTargetLinux())
1434 if (Subtarget->is64Bit()) {
1435 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1437 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1450 //===----------------------------------------------------------------------===//
1451 // Return Value Calling Convention Implementation
1452 //===----------------------------------------------------------------------===//
1454 #include "X86GenCallingConv.inc"
1457 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1458 MachineFunction &MF, bool isVarArg,
1459 const SmallVectorImpl<ISD::OutputArg> &Outs,
1460 LLVMContext &Context) const {
1461 SmallVector<CCValAssign, 16> RVLocs;
1462 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1464 return CCInfo.CheckReturn(Outs, RetCC_X86);
1468 X86TargetLowering::LowerReturn(SDValue Chain,
1469 CallingConv::ID CallConv, bool isVarArg,
1470 const SmallVectorImpl<ISD::OutputArg> &Outs,
1471 const SmallVectorImpl<SDValue> &OutVals,
1472 DebugLoc dl, SelectionDAG &DAG) const {
1473 MachineFunction &MF = DAG.getMachineFunction();
1474 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1476 SmallVector<CCValAssign, 16> RVLocs;
1477 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1478 RVLocs, *DAG.getContext());
1479 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1481 // Add the regs to the liveout set for the function.
1482 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1483 for (unsigned i = 0; i != RVLocs.size(); ++i)
1484 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1485 MRI.addLiveOut(RVLocs[i].getLocReg());
1489 SmallVector<SDValue, 6> RetOps;
1490 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1491 // Operand #1 = Bytes To Pop
1492 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1495 // Copy the result values into the output registers.
1496 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1497 CCValAssign &VA = RVLocs[i];
1498 assert(VA.isRegLoc() && "Can only return in registers!");
1499 SDValue ValToCopy = OutVals[i];
1500 EVT ValVT = ValToCopy.getValueType();
1502 // If this is x86-64, and we disabled SSE, we can't return FP values,
1503 // or SSE or MMX vectors.
1504 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1505 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1506 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1507 report_fatal_error("SSE register return with SSE disabled");
1509 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1510 // llvm-gcc has never done it right and no one has noticed, so this
1511 // should be OK for now.
1512 if (ValVT == MVT::f64 &&
1513 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1514 report_fatal_error("SSE2 register return with SSE2 disabled");
1516 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1517 // the RET instruction and handled by the FP Stackifier.
1518 if (VA.getLocReg() == X86::ST0 ||
1519 VA.getLocReg() == X86::ST1) {
1520 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1521 // change the value to the FP stack register class.
1522 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1523 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1524 RetOps.push_back(ValToCopy);
1525 // Don't emit a copytoreg.
1529 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1530 // which is returned in RAX / RDX.
1531 if (Subtarget->is64Bit()) {
1532 if (ValVT == MVT::x86mmx) {
1533 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1534 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1535 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1537 // If we don't have SSE2 available, convert to v4f32 so the generated
1538 // register is legal.
1539 if (!Subtarget->hasSSE2())
1540 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1545 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1546 Flag = Chain.getValue(1);
1549 // The x86-64 ABI for returning structs by value requires that we copy
1550 // the sret argument into %rax for the return. We saved the argument into
1551 // a virtual register in the entry block, so now we copy the value out
1553 if (Subtarget->is64Bit() &&
1554 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1555 MachineFunction &MF = DAG.getMachineFunction();
1556 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1557 unsigned Reg = FuncInfo->getSRetReturnReg();
1559 "SRetReturnReg should have been set in LowerFormalArguments().");
1560 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1562 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1563 Flag = Chain.getValue(1);
1565 // RAX now acts like a return value.
1566 MRI.addLiveOut(X86::RAX);
1569 RetOps[0] = Chain; // Update chain.
1571 // Add the flag if we have it.
1573 RetOps.push_back(Flag);
1575 return DAG.getNode(X86ISD::RET_FLAG, dl,
1576 MVT::Other, &RetOps[0], RetOps.size());
1579 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1580 if (N->getNumValues() != 1)
1582 if (!N->hasNUsesOfValue(1, 0))
1585 SDNode *Copy = *N->use_begin();
1586 if (Copy->getOpcode() != ISD::CopyToReg &&
1587 Copy->getOpcode() != ISD::FP_EXTEND)
1590 bool HasRet = false;
1591 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1593 if (UI->getOpcode() != X86ISD::RET_FLAG)
1602 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1603 ISD::NodeType ExtendKind) const {
1605 // TODO: Is this also valid on 32-bit?
1606 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1607 ReturnMVT = MVT::i8;
1609 ReturnMVT = MVT::i32;
1611 EVT MinVT = getRegisterType(Context, ReturnMVT);
1612 return VT.bitsLT(MinVT) ? MinVT : VT;
1615 /// LowerCallResult - Lower the result values of a call into the
1616 /// appropriate copies out of appropriate physical registers.
1619 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1620 CallingConv::ID CallConv, bool isVarArg,
1621 const SmallVectorImpl<ISD::InputArg> &Ins,
1622 DebugLoc dl, SelectionDAG &DAG,
1623 SmallVectorImpl<SDValue> &InVals) const {
1625 // Assign locations to each value returned by this call.
1626 SmallVector<CCValAssign, 16> RVLocs;
1627 bool Is64Bit = Subtarget->is64Bit();
1628 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1629 getTargetMachine(), RVLocs, *DAG.getContext());
1630 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1632 // Copy all of the result registers out of their specified physreg.
1633 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1634 CCValAssign &VA = RVLocs[i];
1635 EVT CopyVT = VA.getValVT();
1637 // If this is x86-64, and we disabled SSE, we can't return FP values
1638 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1639 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1640 report_fatal_error("SSE register return with SSE disabled");
1645 // If this is a call to a function that returns an fp value on the floating
1646 // point stack, we must guarantee the the value is popped from the stack, so
1647 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1648 // if the return value is not used. We use the FpPOP_RETVAL instruction
1650 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1651 // If we prefer to use the value in xmm registers, copy it out as f80 and
1652 // use a truncate to move it from fp stack reg to xmm reg.
1653 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1654 SDValue Ops[] = { Chain, InFlag };
1655 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1656 MVT::Other, MVT::Glue, Ops, 2), 1);
1657 Val = Chain.getValue(0);
1659 // Round the f80 to the right size, which also moves it to the appropriate
1661 if (CopyVT != VA.getValVT())
1662 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1663 // This truncation won't change the value.
1664 DAG.getIntPtrConstant(1));
1666 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1667 CopyVT, InFlag).getValue(1);
1668 Val = Chain.getValue(0);
1670 InFlag = Chain.getValue(2);
1671 InVals.push_back(Val);
1678 //===----------------------------------------------------------------------===//
1679 // C & StdCall & Fast Calling Convention implementation
1680 //===----------------------------------------------------------------------===//
1681 // StdCall calling convention seems to be standard for many Windows' API
1682 // routines and around. It differs from C calling convention just a little:
1683 // callee should clean up the stack, not caller. Symbols should be also
1684 // decorated in some fancy way :) It doesn't support any vector arguments.
1685 // For info on fast calling convention see Fast Calling Convention (tail call)
1686 // implementation LowerX86_32FastCCCallTo.
1688 /// CallIsStructReturn - Determines whether a call uses struct return
1690 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1694 return Outs[0].Flags.isSRet();
1697 /// ArgsAreStructReturn - Determines whether a function uses struct
1698 /// return semantics.
1700 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1704 return Ins[0].Flags.isSRet();
1707 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1708 /// by "Src" to address "Dst" with size and alignment information specified by
1709 /// the specific parameter attribute. The copy will be passed as a byval
1710 /// function parameter.
1712 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1713 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1715 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1717 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1718 /*isVolatile*/false, /*AlwaysInline=*/true,
1719 MachinePointerInfo(), MachinePointerInfo());
1722 /// IsTailCallConvention - Return true if the calling convention is one that
1723 /// supports tail call optimization.
1724 static bool IsTailCallConvention(CallingConv::ID CC) {
1725 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1728 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1729 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1733 CallingConv::ID CalleeCC = CS.getCallingConv();
1734 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1740 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1741 /// a tailcall target by changing its ABI.
1742 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1743 bool GuaranteedTailCallOpt) {
1744 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1748 X86TargetLowering::LowerMemArgument(SDValue Chain,
1749 CallingConv::ID CallConv,
1750 const SmallVectorImpl<ISD::InputArg> &Ins,
1751 DebugLoc dl, SelectionDAG &DAG,
1752 const CCValAssign &VA,
1753 MachineFrameInfo *MFI,
1755 // Create the nodes corresponding to a load from this parameter slot.
1756 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1757 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1758 getTargetMachine().Options.GuaranteedTailCallOpt);
1759 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1762 // If value is passed by pointer we have address passed instead of the value
1764 if (VA.getLocInfo() == CCValAssign::Indirect)
1765 ValVT = VA.getLocVT();
1767 ValVT = VA.getValVT();
1769 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1770 // changed with more analysis.
1771 // In case of tail call optimization mark all arguments mutable. Since they
1772 // could be overwritten by lowering of arguments in case of a tail call.
1773 if (Flags.isByVal()) {
1774 unsigned Bytes = Flags.getByValSize();
1775 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1776 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1777 return DAG.getFrameIndex(FI, getPointerTy());
1779 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1780 VA.getLocMemOffset(), isImmutable);
1781 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1782 return DAG.getLoad(ValVT, dl, Chain, FIN,
1783 MachinePointerInfo::getFixedStack(FI),
1784 false, false, false, 0);
1789 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1790 CallingConv::ID CallConv,
1792 const SmallVectorImpl<ISD::InputArg> &Ins,
1795 SmallVectorImpl<SDValue> &InVals)
1797 MachineFunction &MF = DAG.getMachineFunction();
1798 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1800 const Function* Fn = MF.getFunction();
1801 if (Fn->hasExternalLinkage() &&
1802 Subtarget->isTargetCygMing() &&
1803 Fn->getName() == "main")
1804 FuncInfo->setForceFramePointer(true);
1806 MachineFrameInfo *MFI = MF.getFrameInfo();
1807 bool Is64Bit = Subtarget->is64Bit();
1808 bool IsWindows = Subtarget->isTargetWindows();
1809 bool IsWin64 = Subtarget->isTargetWin64();
1811 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1812 "Var args not supported with calling convention fastcc or ghc");
1814 // Assign locations to all of the incoming arguments.
1815 SmallVector<CCValAssign, 16> ArgLocs;
1816 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1817 ArgLocs, *DAG.getContext());
1819 // Allocate shadow area for Win64
1821 CCInfo.AllocateStack(32, 8);
1824 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1826 unsigned LastVal = ~0U;
1828 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1829 CCValAssign &VA = ArgLocs[i];
1830 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1832 assert(VA.getValNo() != LastVal &&
1833 "Don't support value assigned to multiple locs yet");
1835 LastVal = VA.getValNo();
1837 if (VA.isRegLoc()) {
1838 EVT RegVT = VA.getLocVT();
1839 TargetRegisterClass *RC = NULL;
1840 if (RegVT == MVT::i32)
1841 RC = X86::GR32RegisterClass;
1842 else if (Is64Bit && RegVT == MVT::i64)
1843 RC = X86::GR64RegisterClass;
1844 else if (RegVT == MVT::f32)
1845 RC = X86::FR32RegisterClass;
1846 else if (RegVT == MVT::f64)
1847 RC = X86::FR64RegisterClass;
1848 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1849 RC = X86::VR256RegisterClass;
1850 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1851 RC = X86::VR128RegisterClass;
1852 else if (RegVT == MVT::x86mmx)
1853 RC = X86::VR64RegisterClass;
1855 llvm_unreachable("Unknown argument type!");
1857 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1858 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1860 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1861 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1863 if (VA.getLocInfo() == CCValAssign::SExt)
1864 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1865 DAG.getValueType(VA.getValVT()));
1866 else if (VA.getLocInfo() == CCValAssign::ZExt)
1867 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1868 DAG.getValueType(VA.getValVT()));
1869 else if (VA.getLocInfo() == CCValAssign::BCvt)
1870 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1872 if (VA.isExtInLoc()) {
1873 // Handle MMX values passed in XMM regs.
1874 if (RegVT.isVector()) {
1875 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1878 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1881 assert(VA.isMemLoc());
1882 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1885 // If value is passed via pointer - do a load.
1886 if (VA.getLocInfo() == CCValAssign::Indirect)
1887 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1888 MachinePointerInfo(), false, false, false, 0);
1890 InVals.push_back(ArgValue);
1893 // The x86-64 ABI for returning structs by value requires that we copy
1894 // the sret argument into %rax for the return. Save the argument into
1895 // a virtual register so that we can access it from the return points.
1896 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1897 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1898 unsigned Reg = FuncInfo->getSRetReturnReg();
1900 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1901 FuncInfo->setSRetReturnReg(Reg);
1903 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1904 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1907 unsigned StackSize = CCInfo.getNextStackOffset();
1908 // Align stack specially for tail calls.
1909 if (FuncIsMadeTailCallSafe(CallConv,
1910 MF.getTarget().Options.GuaranteedTailCallOpt))
1911 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1913 // If the function takes variable number of arguments, make a frame index for
1914 // the start of the first vararg value... for expansion of llvm.va_start.
1916 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1917 CallConv != CallingConv::X86_ThisCall)) {
1918 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1921 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1923 // FIXME: We should really autogenerate these arrays
1924 static const unsigned GPR64ArgRegsWin64[] = {
1925 X86::RCX, X86::RDX, X86::R8, X86::R9
1927 static const unsigned GPR64ArgRegs64Bit[] = {
1928 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1930 static const unsigned XMMArgRegs64Bit[] = {
1931 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1932 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1934 const unsigned *GPR64ArgRegs;
1935 unsigned NumXMMRegs = 0;
1938 // The XMM registers which might contain var arg parameters are shadowed
1939 // in their paired GPR. So we only need to save the GPR to their home
1941 TotalNumIntRegs = 4;
1942 GPR64ArgRegs = GPR64ArgRegsWin64;
1944 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1945 GPR64ArgRegs = GPR64ArgRegs64Bit;
1947 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1950 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1953 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1954 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1955 "SSE register cannot be used when SSE is disabled!");
1956 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1957 NoImplicitFloatOps) &&
1958 "SSE register cannot be used when SSE is disabled!");
1959 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1960 !Subtarget->hasSSE1())
1961 // Kernel mode asks for SSE to be disabled, so don't push them
1963 TotalNumXMMRegs = 0;
1966 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1967 // Get to the caller-allocated home save location. Add 8 to account
1968 // for the return address.
1969 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1970 FuncInfo->setRegSaveFrameIndex(
1971 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1972 // Fixup to set vararg frame on shadow area (4 x i64).
1974 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1976 // For X86-64, if there are vararg parameters that are passed via
1977 // registers, then we must store them to their spots on the stack so
1978 // they may be loaded by deferencing the result of va_next.
1979 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1980 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1981 FuncInfo->setRegSaveFrameIndex(
1982 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1986 // Store the integer parameter registers.
1987 SmallVector<SDValue, 8> MemOps;
1988 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1990 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1991 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1992 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1993 DAG.getIntPtrConstant(Offset));
1994 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1995 X86::GR64RegisterClass);
1996 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1998 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1999 MachinePointerInfo::getFixedStack(
2000 FuncInfo->getRegSaveFrameIndex(), Offset),
2002 MemOps.push_back(Store);
2006 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2007 // Now store the XMM (fp + vector) parameter registers.
2008 SmallVector<SDValue, 11> SaveXMMOps;
2009 SaveXMMOps.push_back(Chain);
2011 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2012 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2013 SaveXMMOps.push_back(ALVal);
2015 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2016 FuncInfo->getRegSaveFrameIndex()));
2017 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2018 FuncInfo->getVarArgsFPOffset()));
2020 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2021 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2022 X86::VR128RegisterClass);
2023 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2024 SaveXMMOps.push_back(Val);
2026 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2028 &SaveXMMOps[0], SaveXMMOps.size()));
2031 if (!MemOps.empty())
2032 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2033 &MemOps[0], MemOps.size());
2037 // Some CCs need callee pop.
2038 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2039 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2040 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2042 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2043 // If this is an sret function, the return should pop the hidden pointer.
2044 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2045 ArgsAreStructReturn(Ins))
2046 FuncInfo->setBytesToPopOnReturn(4);
2050 // RegSaveFrameIndex is X86-64 only.
2051 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2052 if (CallConv == CallingConv::X86_FastCall ||
2053 CallConv == CallingConv::X86_ThisCall)
2054 // fastcc functions can't have varargs.
2055 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2058 FuncInfo->setArgumentStackSize(StackSize);
2064 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2065 SDValue StackPtr, SDValue Arg,
2066 DebugLoc dl, SelectionDAG &DAG,
2067 const CCValAssign &VA,
2068 ISD::ArgFlagsTy Flags) const {
2069 unsigned LocMemOffset = VA.getLocMemOffset();
2070 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2071 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2072 if (Flags.isByVal())
2073 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2075 return DAG.getStore(Chain, dl, Arg, PtrOff,
2076 MachinePointerInfo::getStack(LocMemOffset),
2080 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2081 /// optimization is performed and it is required.
2083 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2084 SDValue &OutRetAddr, SDValue Chain,
2085 bool IsTailCall, bool Is64Bit,
2086 int FPDiff, DebugLoc dl) const {
2087 // Adjust the Return address stack slot.
2088 EVT VT = getPointerTy();
2089 OutRetAddr = getReturnAddressFrameIndex(DAG);
2091 // Load the "old" Return address.
2092 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2093 false, false, false, 0);
2094 return SDValue(OutRetAddr.getNode(), 1);
2097 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2098 /// optimization is performed and it is required (FPDiff!=0).
2100 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2101 SDValue Chain, SDValue RetAddrFrIdx,
2102 bool Is64Bit, int FPDiff, DebugLoc dl) {
2103 // Store the return address to the appropriate stack slot.
2104 if (!FPDiff) return Chain;
2105 // Calculate the new stack slot for the return address.
2106 int SlotSize = Is64Bit ? 8 : 4;
2107 int NewReturnAddrFI =
2108 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2109 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2110 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2111 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2112 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2118 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2119 CallingConv::ID CallConv, bool isVarArg,
2121 const SmallVectorImpl<ISD::OutputArg> &Outs,
2122 const SmallVectorImpl<SDValue> &OutVals,
2123 const SmallVectorImpl<ISD::InputArg> &Ins,
2124 DebugLoc dl, SelectionDAG &DAG,
2125 SmallVectorImpl<SDValue> &InVals) const {
2126 MachineFunction &MF = DAG.getMachineFunction();
2127 bool Is64Bit = Subtarget->is64Bit();
2128 bool IsWin64 = Subtarget->isTargetWin64();
2129 bool IsWindows = Subtarget->isTargetWindows();
2130 bool IsStructRet = CallIsStructReturn(Outs);
2131 bool IsSibcall = false;
2133 if (MF.getTarget().Options.DisableTailCalls)
2137 // Check if it's really possible to do a tail call.
2138 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2139 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2140 Outs, OutVals, Ins, DAG);
2142 // Sibcalls are automatically detected tailcalls which do not require
2144 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2151 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2152 "Var args not supported with calling convention fastcc or ghc");
2154 // Analyze operands of the call, assigning locations to each operand.
2155 SmallVector<CCValAssign, 16> ArgLocs;
2156 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2157 ArgLocs, *DAG.getContext());
2159 // Allocate shadow area for Win64
2161 CCInfo.AllocateStack(32, 8);
2164 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2166 // Get a count of how many bytes are to be pushed on the stack.
2167 unsigned NumBytes = CCInfo.getNextStackOffset();
2169 // This is a sibcall. The memory operands are available in caller's
2170 // own caller's stack.
2172 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2173 IsTailCallConvention(CallConv))
2174 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2177 if (isTailCall && !IsSibcall) {
2178 // Lower arguments at fp - stackoffset + fpdiff.
2179 unsigned NumBytesCallerPushed =
2180 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2181 FPDiff = NumBytesCallerPushed - NumBytes;
2183 // Set the delta of movement of the returnaddr stackslot.
2184 // But only set if delta is greater than previous delta.
2185 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2186 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2190 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2192 SDValue RetAddrFrIdx;
2193 // Load return address for tail calls.
2194 if (isTailCall && FPDiff)
2195 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2196 Is64Bit, FPDiff, dl);
2198 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2199 SmallVector<SDValue, 8> MemOpChains;
2202 // Walk the register/memloc assignments, inserting copies/loads. In the case
2203 // of tail call optimization arguments are handle later.
2204 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2205 CCValAssign &VA = ArgLocs[i];
2206 EVT RegVT = VA.getLocVT();
2207 SDValue Arg = OutVals[i];
2208 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2209 bool isByVal = Flags.isByVal();
2211 // Promote the value if needed.
2212 switch (VA.getLocInfo()) {
2213 default: llvm_unreachable("Unknown loc info!");
2214 case CCValAssign::Full: break;
2215 case CCValAssign::SExt:
2216 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2218 case CCValAssign::ZExt:
2219 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2221 case CCValAssign::AExt:
2222 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2223 // Special case: passing MMX values in XMM registers.
2224 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2225 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2226 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2228 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2230 case CCValAssign::BCvt:
2231 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2233 case CCValAssign::Indirect: {
2234 // Store the argument.
2235 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2236 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2237 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2238 MachinePointerInfo::getFixedStack(FI),
2245 if (VA.isRegLoc()) {
2246 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2247 if (isVarArg && IsWin64) {
2248 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2249 // shadow reg if callee is a varargs function.
2250 unsigned ShadowReg = 0;
2251 switch (VA.getLocReg()) {
2252 case X86::XMM0: ShadowReg = X86::RCX; break;
2253 case X86::XMM1: ShadowReg = X86::RDX; break;
2254 case X86::XMM2: ShadowReg = X86::R8; break;
2255 case X86::XMM3: ShadowReg = X86::R9; break;
2258 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2260 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2261 assert(VA.isMemLoc());
2262 if (StackPtr.getNode() == 0)
2263 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2264 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2265 dl, DAG, VA, Flags));
2269 if (!MemOpChains.empty())
2270 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2271 &MemOpChains[0], MemOpChains.size());
2273 // Build a sequence of copy-to-reg nodes chained together with token chain
2274 // and flag operands which copy the outgoing args into registers.
2276 // Tail call byval lowering might overwrite argument registers so in case of
2277 // tail call optimization the copies to registers are lowered later.
2279 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2280 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2281 RegsToPass[i].second, InFlag);
2282 InFlag = Chain.getValue(1);
2285 if (Subtarget->isPICStyleGOT()) {
2286 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2289 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2290 DAG.getNode(X86ISD::GlobalBaseReg,
2291 DebugLoc(), getPointerTy()),
2293 InFlag = Chain.getValue(1);
2295 // If we are tail calling and generating PIC/GOT style code load the
2296 // address of the callee into ECX. The value in ecx is used as target of
2297 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2298 // for tail calls on PIC/GOT architectures. Normally we would just put the
2299 // address of GOT into ebx and then call target@PLT. But for tail calls
2300 // ebx would be restored (since ebx is callee saved) before jumping to the
2303 // Note: The actual moving to ECX is done further down.
2304 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2305 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2306 !G->getGlobal()->hasProtectedVisibility())
2307 Callee = LowerGlobalAddress(Callee, DAG);
2308 else if (isa<ExternalSymbolSDNode>(Callee))
2309 Callee = LowerExternalSymbol(Callee, DAG);
2313 if (Is64Bit && isVarArg && !IsWin64) {
2314 // From AMD64 ABI document:
2315 // For calls that may call functions that use varargs or stdargs
2316 // (prototype-less calls or calls to functions containing ellipsis (...) in
2317 // the declaration) %al is used as hidden argument to specify the number
2318 // of SSE registers used. The contents of %al do not need to match exactly
2319 // the number of registers, but must be an ubound on the number of SSE
2320 // registers used and is in the range 0 - 8 inclusive.
2322 // Count the number of XMM registers allocated.
2323 static const unsigned XMMArgRegs[] = {
2324 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2325 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2327 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2328 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2329 && "SSE registers cannot be used when SSE is disabled");
2331 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2332 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2333 InFlag = Chain.getValue(1);
2337 // For tail calls lower the arguments to the 'real' stack slot.
2339 // Force all the incoming stack arguments to be loaded from the stack
2340 // before any new outgoing arguments are stored to the stack, because the
2341 // outgoing stack slots may alias the incoming argument stack slots, and
2342 // the alias isn't otherwise explicit. This is slightly more conservative
2343 // than necessary, because it means that each store effectively depends
2344 // on every argument instead of just those arguments it would clobber.
2345 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2347 SmallVector<SDValue, 8> MemOpChains2;
2350 // Do not flag preceding copytoreg stuff together with the following stuff.
2352 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2353 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2354 CCValAssign &VA = ArgLocs[i];
2357 assert(VA.isMemLoc());
2358 SDValue Arg = OutVals[i];
2359 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2360 // Create frame index.
2361 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2362 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2363 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2364 FIN = DAG.getFrameIndex(FI, getPointerTy());
2366 if (Flags.isByVal()) {
2367 // Copy relative to framepointer.
2368 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2369 if (StackPtr.getNode() == 0)
2370 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2372 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2374 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2378 // Store relative to framepointer.
2379 MemOpChains2.push_back(
2380 DAG.getStore(ArgChain, dl, Arg, FIN,
2381 MachinePointerInfo::getFixedStack(FI),
2387 if (!MemOpChains2.empty())
2388 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2389 &MemOpChains2[0], MemOpChains2.size());
2391 // Copy arguments to their registers.
2392 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2393 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2394 RegsToPass[i].second, InFlag);
2395 InFlag = Chain.getValue(1);
2399 // Store the return address to the appropriate stack slot.
2400 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2404 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2405 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2406 // In the 64-bit large code model, we have to make all calls
2407 // through a register, since the call instruction's 32-bit
2408 // pc-relative offset may not be large enough to hold the whole
2410 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2411 // If the callee is a GlobalAddress node (quite common, every direct call
2412 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2415 // We should use extra load for direct calls to dllimported functions in
2417 const GlobalValue *GV = G->getGlobal();
2418 if (!GV->hasDLLImportLinkage()) {
2419 unsigned char OpFlags = 0;
2420 bool ExtraLoad = false;
2421 unsigned WrapperKind = ISD::DELETED_NODE;
2423 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2424 // external symbols most go through the PLT in PIC mode. If the symbol
2425 // has hidden or protected visibility, or if it is static or local, then
2426 // we don't need to use the PLT - we can directly call it.
2427 if (Subtarget->isTargetELF() &&
2428 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2429 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2430 OpFlags = X86II::MO_PLT;
2431 } else if (Subtarget->isPICStyleStubAny() &&
2432 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2433 (!Subtarget->getTargetTriple().isMacOSX() ||
2434 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2435 // PC-relative references to external symbols should go through $stub,
2436 // unless we're building with the leopard linker or later, which
2437 // automatically synthesizes these stubs.
2438 OpFlags = X86II::MO_DARWIN_STUB;
2439 } else if (Subtarget->isPICStyleRIPRel() &&
2440 isa<Function>(GV) &&
2441 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2442 // If the function is marked as non-lazy, generate an indirect call
2443 // which loads from the GOT directly. This avoids runtime overhead
2444 // at the cost of eager binding (and one extra byte of encoding).
2445 OpFlags = X86II::MO_GOTPCREL;
2446 WrapperKind = X86ISD::WrapperRIP;
2450 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2451 G->getOffset(), OpFlags);
2453 // Add a wrapper if needed.
2454 if (WrapperKind != ISD::DELETED_NODE)
2455 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2456 // Add extra indirection if needed.
2458 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2459 MachinePointerInfo::getGOT(),
2460 false, false, false, 0);
2462 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2463 unsigned char OpFlags = 0;
2465 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2466 // external symbols should go through the PLT.
2467 if (Subtarget->isTargetELF() &&
2468 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2469 OpFlags = X86II::MO_PLT;
2470 } else if (Subtarget->isPICStyleStubAny() &&
2471 (!Subtarget->getTargetTriple().isMacOSX() ||
2472 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2473 // PC-relative references to external symbols should go through $stub,
2474 // unless we're building with the leopard linker or later, which
2475 // automatically synthesizes these stubs.
2476 OpFlags = X86II::MO_DARWIN_STUB;
2479 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2483 // Returns a chain & a flag for retval copy to use.
2484 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2485 SmallVector<SDValue, 8> Ops;
2487 if (!IsSibcall && isTailCall) {
2488 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2489 DAG.getIntPtrConstant(0, true), InFlag);
2490 InFlag = Chain.getValue(1);
2493 Ops.push_back(Chain);
2494 Ops.push_back(Callee);
2497 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2499 // Add argument registers to the end of the list so that they are known live
2501 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2502 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2503 RegsToPass[i].second.getValueType()));
2505 // Add an implicit use GOT pointer in EBX.
2506 if (!isTailCall && Subtarget->isPICStyleGOT())
2507 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2509 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2510 if (Is64Bit && isVarArg && !IsWin64)
2511 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2513 // Experimental: Add a register mask operand representing the call-preserved
2516 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2517 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2518 Ops.push_back(DAG.getRegisterMask(Mask));
2521 if (InFlag.getNode())
2522 Ops.push_back(InFlag);
2526 //// If this is the first return lowered for this function, add the regs
2527 //// to the liveout set for the function.
2528 // This isn't right, although it's probably harmless on x86; liveouts
2529 // should be computed from returns not tail calls. Consider a void
2530 // function making a tail call to a function returning int.
2531 return DAG.getNode(X86ISD::TC_RETURN, dl,
2532 NodeTys, &Ops[0], Ops.size());
2535 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2536 InFlag = Chain.getValue(1);
2538 // Create the CALLSEQ_END node.
2539 unsigned NumBytesForCalleeToPush;
2540 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2541 getTargetMachine().Options.GuaranteedTailCallOpt))
2542 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2543 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2545 // If this is a call to a struct-return function, the callee
2546 // pops the hidden struct pointer, so we have to push it back.
2547 // This is common for Darwin/X86, Linux & Mingw32 targets.
2548 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2549 NumBytesForCalleeToPush = 4;
2551 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2553 // Returns a flag for retval copy to use.
2555 Chain = DAG.getCALLSEQ_END(Chain,
2556 DAG.getIntPtrConstant(NumBytes, true),
2557 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2560 InFlag = Chain.getValue(1);
2563 // Handle result values, copying them out of physregs into vregs that we
2565 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2566 Ins, dl, DAG, InVals);
2570 //===----------------------------------------------------------------------===//
2571 // Fast Calling Convention (tail call) implementation
2572 //===----------------------------------------------------------------------===//
2574 // Like std call, callee cleans arguments, convention except that ECX is
2575 // reserved for storing the tail called function address. Only 2 registers are
2576 // free for argument passing (inreg). Tail call optimization is performed
2578 // * tailcallopt is enabled
2579 // * caller/callee are fastcc
2580 // On X86_64 architecture with GOT-style position independent code only local
2581 // (within module) calls are supported at the moment.
2582 // To keep the stack aligned according to platform abi the function
2583 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2584 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2585 // If a tail called function callee has more arguments than the caller the
2586 // caller needs to make sure that there is room to move the RETADDR to. This is
2587 // achieved by reserving an area the size of the argument delta right after the
2588 // original REtADDR, but before the saved framepointer or the spilled registers
2589 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2601 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2602 /// for a 16 byte align requirement.
2604 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2605 SelectionDAG& DAG) const {
2606 MachineFunction &MF = DAG.getMachineFunction();
2607 const TargetMachine &TM = MF.getTarget();
2608 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2609 unsigned StackAlignment = TFI.getStackAlignment();
2610 uint64_t AlignMask = StackAlignment - 1;
2611 int64_t Offset = StackSize;
2612 uint64_t SlotSize = TD->getPointerSize();
2613 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2614 // Number smaller than 12 so just add the difference.
2615 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2617 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2618 Offset = ((~AlignMask) & Offset) + StackAlignment +
2619 (StackAlignment-SlotSize);
2624 /// MatchingStackOffset - Return true if the given stack call argument is
2625 /// already available in the same position (relatively) of the caller's
2626 /// incoming argument stack.
2628 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2629 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2630 const X86InstrInfo *TII) {
2631 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2633 if (Arg.getOpcode() == ISD::CopyFromReg) {
2634 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2635 if (!TargetRegisterInfo::isVirtualRegister(VR))
2637 MachineInstr *Def = MRI->getVRegDef(VR);
2640 if (!Flags.isByVal()) {
2641 if (!TII->isLoadFromStackSlot(Def, FI))
2644 unsigned Opcode = Def->getOpcode();
2645 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2646 Def->getOperand(1).isFI()) {
2647 FI = Def->getOperand(1).getIndex();
2648 Bytes = Flags.getByValSize();
2652 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2653 if (Flags.isByVal())
2654 // ByVal argument is passed in as a pointer but it's now being
2655 // dereferenced. e.g.
2656 // define @foo(%struct.X* %A) {
2657 // tail call @bar(%struct.X* byval %A)
2660 SDValue Ptr = Ld->getBasePtr();
2661 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2664 FI = FINode->getIndex();
2665 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2666 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2667 FI = FINode->getIndex();
2668 Bytes = Flags.getByValSize();
2672 assert(FI != INT_MAX);
2673 if (!MFI->isFixedObjectIndex(FI))
2675 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2678 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2679 /// for tail call optimization. Targets which want to do tail call
2680 /// optimization should implement this function.
2682 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2683 CallingConv::ID CalleeCC,
2685 bool isCalleeStructRet,
2686 bool isCallerStructRet,
2687 const SmallVectorImpl<ISD::OutputArg> &Outs,
2688 const SmallVectorImpl<SDValue> &OutVals,
2689 const SmallVectorImpl<ISD::InputArg> &Ins,
2690 SelectionDAG& DAG) const {
2691 if (!IsTailCallConvention(CalleeCC) &&
2692 CalleeCC != CallingConv::C)
2695 // If -tailcallopt is specified, make fastcc functions tail-callable.
2696 const MachineFunction &MF = DAG.getMachineFunction();
2697 const Function *CallerF = DAG.getMachineFunction().getFunction();
2698 CallingConv::ID CallerCC = CallerF->getCallingConv();
2699 bool CCMatch = CallerCC == CalleeCC;
2701 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2702 if (IsTailCallConvention(CalleeCC) && CCMatch)
2707 // Look for obvious safe cases to perform tail call optimization that do not
2708 // require ABI changes. This is what gcc calls sibcall.
2710 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2711 // emit a special epilogue.
2712 if (RegInfo->needsStackRealignment(MF))
2715 // Also avoid sibcall optimization if either caller or callee uses struct
2716 // return semantics.
2717 if (isCalleeStructRet || isCallerStructRet)
2720 // An stdcall caller is expected to clean up its arguments; the callee
2721 // isn't going to do that.
2722 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2725 // Do not sibcall optimize vararg calls unless all arguments are passed via
2727 if (isVarArg && !Outs.empty()) {
2729 // Optimizing for varargs on Win64 is unlikely to be safe without
2730 // additional testing.
2731 if (Subtarget->isTargetWin64())
2734 SmallVector<CCValAssign, 16> ArgLocs;
2735 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2736 getTargetMachine(), ArgLocs, *DAG.getContext());
2738 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2739 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2740 if (!ArgLocs[i].isRegLoc())
2744 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2745 // stack. Therefore, if it's not used by the call it is not safe to optimize
2746 // this into a sibcall.
2747 bool Unused = false;
2748 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2755 SmallVector<CCValAssign, 16> RVLocs;
2756 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2757 getTargetMachine(), RVLocs, *DAG.getContext());
2758 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2759 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2760 CCValAssign &VA = RVLocs[i];
2761 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2766 // If the calling conventions do not match, then we'd better make sure the
2767 // results are returned in the same way as what the caller expects.
2769 SmallVector<CCValAssign, 16> RVLocs1;
2770 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2771 getTargetMachine(), RVLocs1, *DAG.getContext());
2772 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2774 SmallVector<CCValAssign, 16> RVLocs2;
2775 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2776 getTargetMachine(), RVLocs2, *DAG.getContext());
2777 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2779 if (RVLocs1.size() != RVLocs2.size())
2781 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2782 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2784 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2786 if (RVLocs1[i].isRegLoc()) {
2787 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2790 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2796 // If the callee takes no arguments then go on to check the results of the
2798 if (!Outs.empty()) {
2799 // Check if stack adjustment is needed. For now, do not do this if any
2800 // argument is passed on the stack.
2801 SmallVector<CCValAssign, 16> ArgLocs;
2802 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2803 getTargetMachine(), ArgLocs, *DAG.getContext());
2805 // Allocate shadow area for Win64
2806 if (Subtarget->isTargetWin64()) {
2807 CCInfo.AllocateStack(32, 8);
2810 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2811 if (CCInfo.getNextStackOffset()) {
2812 MachineFunction &MF = DAG.getMachineFunction();
2813 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2816 // Check if the arguments are already laid out in the right way as
2817 // the caller's fixed stack objects.
2818 MachineFrameInfo *MFI = MF.getFrameInfo();
2819 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2820 const X86InstrInfo *TII =
2821 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2822 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2823 CCValAssign &VA = ArgLocs[i];
2824 SDValue Arg = OutVals[i];
2825 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2826 if (VA.getLocInfo() == CCValAssign::Indirect)
2828 if (!VA.isRegLoc()) {
2829 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2836 // If the tailcall address may be in a register, then make sure it's
2837 // possible to register allocate for it. In 32-bit, the call address can
2838 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2839 // callee-saved registers are restored. These happen to be the same
2840 // registers used to pass 'inreg' arguments so watch out for those.
2841 if (!Subtarget->is64Bit() &&
2842 !isa<GlobalAddressSDNode>(Callee) &&
2843 !isa<ExternalSymbolSDNode>(Callee)) {
2844 unsigned NumInRegs = 0;
2845 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2846 CCValAssign &VA = ArgLocs[i];
2849 unsigned Reg = VA.getLocReg();
2852 case X86::EAX: case X86::EDX: case X86::ECX:
2853 if (++NumInRegs == 3)
2865 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2866 return X86::createFastISel(funcInfo);
2870 //===----------------------------------------------------------------------===//
2871 // Other Lowering Hooks
2872 //===----------------------------------------------------------------------===//
2874 static bool MayFoldLoad(SDValue Op) {
2875 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2878 static bool MayFoldIntoStore(SDValue Op) {
2879 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2882 static bool isTargetShuffle(unsigned Opcode) {
2884 default: return false;
2885 case X86ISD::PSHUFD:
2886 case X86ISD::PSHUFHW:
2887 case X86ISD::PSHUFLW:
2889 case X86ISD::PALIGN:
2890 case X86ISD::MOVLHPS:
2891 case X86ISD::MOVLHPD:
2892 case X86ISD::MOVHLPS:
2893 case X86ISD::MOVLPS:
2894 case X86ISD::MOVLPD:
2895 case X86ISD::MOVSHDUP:
2896 case X86ISD::MOVSLDUP:
2897 case X86ISD::MOVDDUP:
2900 case X86ISD::UNPCKL:
2901 case X86ISD::UNPCKH:
2902 case X86ISD::VPERMILP:
2903 case X86ISD::VPERM2X128:
2908 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2909 SDValue V1, SelectionDAG &DAG) {
2911 default: llvm_unreachable("Unknown x86 shuffle node");
2912 case X86ISD::MOVSHDUP:
2913 case X86ISD::MOVSLDUP:
2914 case X86ISD::MOVDDUP:
2915 return DAG.getNode(Opc, dl, VT, V1);
2919 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2920 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2922 default: llvm_unreachable("Unknown x86 shuffle node");
2923 case X86ISD::PSHUFD:
2924 case X86ISD::PSHUFHW:
2925 case X86ISD::PSHUFLW:
2926 case X86ISD::VPERMILP:
2927 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2931 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2932 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2934 default: llvm_unreachable("Unknown x86 shuffle node");
2935 case X86ISD::PALIGN:
2937 case X86ISD::VPERM2X128:
2938 return DAG.getNode(Opc, dl, VT, V1, V2,
2939 DAG.getConstant(TargetMask, MVT::i8));
2943 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2944 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2946 default: llvm_unreachable("Unknown x86 shuffle node");
2947 case X86ISD::MOVLHPS:
2948 case X86ISD::MOVLHPD:
2949 case X86ISD::MOVHLPS:
2950 case X86ISD::MOVLPS:
2951 case X86ISD::MOVLPD:
2954 case X86ISD::UNPCKL:
2955 case X86ISD::UNPCKH:
2956 return DAG.getNode(Opc, dl, VT, V1, V2);
2960 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2961 MachineFunction &MF = DAG.getMachineFunction();
2962 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2963 int ReturnAddrIndex = FuncInfo->getRAIndex();
2965 if (ReturnAddrIndex == 0) {
2966 // Set up a frame object for the return address.
2967 uint64_t SlotSize = TD->getPointerSize();
2968 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2970 FuncInfo->setRAIndex(ReturnAddrIndex);
2973 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2977 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2978 bool hasSymbolicDisplacement) {
2979 // Offset should fit into 32 bit immediate field.
2980 if (!isInt<32>(Offset))
2983 // If we don't have a symbolic displacement - we don't have any extra
2985 if (!hasSymbolicDisplacement)
2988 // FIXME: Some tweaks might be needed for medium code model.
2989 if (M != CodeModel::Small && M != CodeModel::Kernel)
2992 // For small code model we assume that latest object is 16MB before end of 31
2993 // bits boundary. We may also accept pretty large negative constants knowing
2994 // that all objects are in the positive half of address space.
2995 if (M == CodeModel::Small && Offset < 16*1024*1024)
2998 // For kernel code model we know that all object resist in the negative half
2999 // of 32bits address space. We may not accept negative offsets, since they may
3000 // be just off and we may accept pretty large positive ones.
3001 if (M == CodeModel::Kernel && Offset > 0)
3007 /// isCalleePop - Determines whether the callee is required to pop its
3008 /// own arguments. Callee pop is necessary to support tail calls.
3009 bool X86::isCalleePop(CallingConv::ID CallingConv,
3010 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3014 switch (CallingConv) {
3017 case CallingConv::X86_StdCall:
3019 case CallingConv::X86_FastCall:
3021 case CallingConv::X86_ThisCall:
3023 case CallingConv::Fast:
3025 case CallingConv::GHC:
3030 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3031 /// specific condition code, returning the condition code and the LHS/RHS of the
3032 /// comparison to make.
3033 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3034 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3036 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3037 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3038 // X > -1 -> X == 0, jump !sign.
3039 RHS = DAG.getConstant(0, RHS.getValueType());
3040 return X86::COND_NS;
3041 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3042 // X < 0 -> X == 0, jump on sign.
3044 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3046 RHS = DAG.getConstant(0, RHS.getValueType());
3047 return X86::COND_LE;
3051 switch (SetCCOpcode) {
3052 default: llvm_unreachable("Invalid integer condition!");
3053 case ISD::SETEQ: return X86::COND_E;
3054 case ISD::SETGT: return X86::COND_G;
3055 case ISD::SETGE: return X86::COND_GE;
3056 case ISD::SETLT: return X86::COND_L;
3057 case ISD::SETLE: return X86::COND_LE;
3058 case ISD::SETNE: return X86::COND_NE;
3059 case ISD::SETULT: return X86::COND_B;
3060 case ISD::SETUGT: return X86::COND_A;
3061 case ISD::SETULE: return X86::COND_BE;
3062 case ISD::SETUGE: return X86::COND_AE;
3066 // First determine if it is required or is profitable to flip the operands.
3068 // If LHS is a foldable load, but RHS is not, flip the condition.
3069 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3070 !ISD::isNON_EXTLoad(RHS.getNode())) {
3071 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3072 std::swap(LHS, RHS);
3075 switch (SetCCOpcode) {
3081 std::swap(LHS, RHS);
3085 // On a floating point condition, the flags are set as follows:
3087 // 0 | 0 | 0 | X > Y
3088 // 0 | 0 | 1 | X < Y
3089 // 1 | 0 | 0 | X == Y
3090 // 1 | 1 | 1 | unordered
3091 switch (SetCCOpcode) {
3092 default: llvm_unreachable("Condcode should be pre-legalized away");
3094 case ISD::SETEQ: return X86::COND_E;
3095 case ISD::SETOLT: // flipped
3097 case ISD::SETGT: return X86::COND_A;
3098 case ISD::SETOLE: // flipped
3100 case ISD::SETGE: return X86::COND_AE;
3101 case ISD::SETUGT: // flipped
3103 case ISD::SETLT: return X86::COND_B;
3104 case ISD::SETUGE: // flipped
3106 case ISD::SETLE: return X86::COND_BE;
3108 case ISD::SETNE: return X86::COND_NE;
3109 case ISD::SETUO: return X86::COND_P;
3110 case ISD::SETO: return X86::COND_NP;
3112 case ISD::SETUNE: return X86::COND_INVALID;
3116 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3117 /// code. Current x86 isa includes the following FP cmov instructions:
3118 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3119 static bool hasFPCMov(unsigned X86CC) {
3135 /// isFPImmLegal - Returns true if the target can instruction select the
3136 /// specified FP immediate natively. If false, the legalizer will
3137 /// materialize the FP immediate as a load from a constant pool.
3138 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3139 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3140 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3146 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3147 /// the specified range (L, H].
3148 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3149 return (Val < 0) || (Val >= Low && Val < Hi);
3152 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3153 /// specified value.
3154 static bool isUndefOrEqual(int Val, int CmpVal) {
3155 if (Val < 0 || Val == CmpVal)
3160 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3161 /// from position Pos and ending in Pos+Size, falls within the specified
3162 /// sequential range (L, L+Pos]. or is undef.
3163 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3164 int Pos, int Size, int Low) {
3165 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3166 if (!isUndefOrEqual(Mask[i], Low))
3171 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3172 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3173 /// the second operand.
3174 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3175 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3176 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3177 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3178 return (Mask[0] < 2 && Mask[1] < 2);
3182 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3183 return ::isPSHUFDMask(N->getMask(), N->getValueType(0));
3186 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3187 /// is suitable for input to PSHUFHW.
3188 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3189 if (VT != MVT::v8i16)
3192 // Lower quadword copied in order or undef.
3193 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3196 // Upper quadword shuffled.
3197 for (unsigned i = 4; i != 8; ++i)
3198 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3204 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3205 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0));
3208 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3209 /// is suitable for input to PSHUFLW.
3210 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3211 if (VT != MVT::v8i16)
3214 // Upper quadword copied in order.
3215 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3218 // Lower quadword shuffled.
3219 for (unsigned i = 0; i != 4; ++i)
3226 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3227 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0));
3230 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3231 /// is suitable for input to PALIGNR.
3232 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3233 const X86Subtarget *Subtarget) {
3234 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3235 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3238 unsigned NumElts = VT.getVectorNumElements();
3239 unsigned NumLanes = VT.getSizeInBits()/128;
3240 unsigned NumLaneElts = NumElts/NumLanes;
3242 // Do not handle 64-bit element shuffles with palignr.
3243 if (NumLaneElts == 2)
3246 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3248 for (i = 0; i != NumLaneElts; ++i) {
3253 // Lane is all undef, go to next lane
3254 if (i == NumLaneElts)
3257 int Start = Mask[i+l];
3259 // Make sure its in this lane in one of the sources
3260 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3261 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3264 // If not lane 0, then we must match lane 0
3265 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3268 // Correct second source to be contiguous with first source
3269 if (Start >= (int)NumElts)
3270 Start -= NumElts - NumLaneElts;
3272 // Make sure we're shifting in the right direction.
3273 if (Start <= (int)(i+l))
3278 // Check the rest of the elements to see if they are consecutive.
3279 for (++i; i != NumLaneElts; ++i) {
3280 int Idx = Mask[i+l];
3282 // Make sure its in this lane
3283 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3284 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3287 // If not lane 0, then we must match lane 0
3288 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3291 if (Idx >= (int)NumElts)
3292 Idx -= NumElts - NumLaneElts;
3294 if (!isUndefOrEqual(Idx, Start+i))
3303 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3304 /// the two vector operands have swapped position.
3305 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3306 unsigned NumElems) {
3307 for (unsigned i = 0; i != NumElems; ++i) {
3311 else if (idx < (int)NumElems)
3312 Mask[i] = idx + NumElems;
3314 Mask[i] = idx - NumElems;
3318 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3319 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3320 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3321 /// reverse of what x86 shuffles want.
3322 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3323 bool Commuted = false) {
3324 if (!HasAVX && VT.getSizeInBits() == 256)
3327 unsigned NumElems = VT.getVectorNumElements();
3328 unsigned NumLanes = VT.getSizeInBits()/128;
3329 unsigned NumLaneElems = NumElems/NumLanes;
3331 if (NumLaneElems != 2 && NumLaneElems != 4)
3334 // VSHUFPSY divides the resulting vector into 4 chunks.
3335 // The sources are also splitted into 4 chunks, and each destination
3336 // chunk must come from a different source chunk.
3338 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3339 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3341 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3342 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3344 // VSHUFPDY divides the resulting vector into 4 chunks.
3345 // The sources are also splitted into 4 chunks, and each destination
3346 // chunk must come from a different source chunk.
3348 // SRC1 => X3 X2 X1 X0
3349 // SRC2 => Y3 Y2 Y1 Y0
3351 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3353 unsigned HalfLaneElems = NumLaneElems/2;
3354 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3355 for (unsigned i = 0; i != NumLaneElems; ++i) {
3356 int Idx = Mask[i+l];
3357 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3358 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3360 // For VSHUFPSY, the mask of the second half must be the same as the
3361 // first but with the appropriate offsets. This works in the same way as
3362 // VPERMILPS works with masks.
3363 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3365 if (!isUndefOrEqual(Idx, Mask[i]+l))
3373 bool X86::isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX) {
3374 return ::isSHUFPMask(N->getMask(), N->getValueType(0), HasAVX);
3377 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3378 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3379 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3380 EVT VT = N->getValueType(0);
3381 unsigned NumElems = VT.getVectorNumElements();
3383 if (VT.getSizeInBits() != 128)
3389 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3390 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3391 isUndefOrEqual(N->getMaskElt(1), 7) &&
3392 isUndefOrEqual(N->getMaskElt(2), 2) &&
3393 isUndefOrEqual(N->getMaskElt(3), 3);
3396 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3397 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3399 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3400 EVT VT = N->getValueType(0);
3401 unsigned NumElems = VT.getVectorNumElements();
3403 if (VT.getSizeInBits() != 128)
3409 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3410 isUndefOrEqual(N->getMaskElt(1), 3) &&
3411 isUndefOrEqual(N->getMaskElt(2), 2) &&
3412 isUndefOrEqual(N->getMaskElt(3), 3);
3415 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3416 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3417 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3418 EVT VT = N->getValueType(0);
3420 if (VT.getSizeInBits() != 128)
3423 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3425 if (NumElems != 2 && NumElems != 4)
3428 for (unsigned i = 0; i < NumElems/2; ++i)
3429 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3432 for (unsigned i = NumElems/2; i < NumElems; ++i)
3433 if (!isUndefOrEqual(N->getMaskElt(i), i))
3439 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3440 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3441 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3442 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3444 if ((NumElems != 2 && NumElems != 4)
3445 || N->getValueType(0).getSizeInBits() > 128)
3448 for (unsigned i = 0; i < NumElems/2; ++i)
3449 if (!isUndefOrEqual(N->getMaskElt(i), i))
3452 for (unsigned i = 0; i < NumElems/2; ++i)
3453 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3459 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3460 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3461 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3462 bool HasAVX2, bool V2IsSplat = false) {
3463 unsigned NumElts = VT.getVectorNumElements();
3465 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3466 "Unsupported vector type for unpckh");
3468 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3469 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3472 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3473 // independently on 128-bit lanes.
3474 unsigned NumLanes = VT.getSizeInBits()/128;
3475 unsigned NumLaneElts = NumElts/NumLanes;
3477 for (unsigned l = 0; l != NumLanes; ++l) {
3478 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3479 i != (l+1)*NumLaneElts;
3482 int BitI1 = Mask[i+1];
3483 if (!isUndefOrEqual(BitI, j))
3486 if (!isUndefOrEqual(BitI1, NumElts))
3489 if (!isUndefOrEqual(BitI1, j + NumElts))
3498 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3499 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3502 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3503 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3504 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3505 bool HasAVX2, bool V2IsSplat = false) {
3506 unsigned NumElts = VT.getVectorNumElements();
3508 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3509 "Unsupported vector type for unpckh");
3511 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3512 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3515 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3516 // independently on 128-bit lanes.
3517 unsigned NumLanes = VT.getSizeInBits()/128;
3518 unsigned NumLaneElts = NumElts/NumLanes;
3520 for (unsigned l = 0; l != NumLanes; ++l) {
3521 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3522 i != (l+1)*NumLaneElts; i += 2, ++j) {
3524 int BitI1 = Mask[i+1];
3525 if (!isUndefOrEqual(BitI, j))
3528 if (isUndefOrEqual(BitI1, NumElts))
3531 if (!isUndefOrEqual(BitI1, j+NumElts))
3539 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3540 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3543 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3544 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3546 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3548 unsigned NumElts = VT.getVectorNumElements();
3550 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3551 "Unsupported vector type for unpckh");
3553 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3554 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3557 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3558 // FIXME: Need a better way to get rid of this, there's no latency difference
3559 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3560 // the former later. We should also remove the "_undef" special mask.
3561 if (NumElts == 4 && VT.getSizeInBits() == 256)
3564 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3565 // independently on 128-bit lanes.
3566 unsigned NumLanes = VT.getSizeInBits()/128;
3567 unsigned NumLaneElts = NumElts/NumLanes;
3569 for (unsigned l = 0; l != NumLanes; ++l) {
3570 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3571 i != (l+1)*NumLaneElts;
3574 int BitI1 = Mask[i+1];
3576 if (!isUndefOrEqual(BitI, j))
3578 if (!isUndefOrEqual(BitI1, j))
3586 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3587 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3590 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3591 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3593 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3594 unsigned NumElts = VT.getVectorNumElements();
3596 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3597 "Unsupported vector type for unpckh");
3599 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3600 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3603 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3604 // independently on 128-bit lanes.
3605 unsigned NumLanes = VT.getSizeInBits()/128;
3606 unsigned NumLaneElts = NumElts/NumLanes;
3608 for (unsigned l = 0; l != NumLanes; ++l) {
3609 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3610 i != (l+1)*NumLaneElts; i += 2, ++j) {
3612 int BitI1 = Mask[i+1];
3613 if (!isUndefOrEqual(BitI, j))
3615 if (!isUndefOrEqual(BitI1, j))
3622 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3623 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3626 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3627 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3628 /// MOVSD, and MOVD, i.e. setting the lowest element.
3629 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3630 if (VT.getVectorElementType().getSizeInBits() < 32)
3632 if (VT.getSizeInBits() == 256)
3635 unsigned NumElts = VT.getVectorNumElements();
3637 if (!isUndefOrEqual(Mask[0], NumElts))
3640 for (unsigned i = 1; i != NumElts; ++i)
3641 if (!isUndefOrEqual(Mask[i], i))
3647 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3648 return ::isMOVLMask(N->getMask(), N->getValueType(0));
3651 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3652 /// as permutations between 128-bit chunks or halves. As an example: this
3654 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3655 /// The first half comes from the second half of V1 and the second half from the
3656 /// the second half of V2.
3657 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3658 if (!HasAVX || VT.getSizeInBits() != 256)
3661 // The shuffle result is divided into half A and half B. In total the two
3662 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3663 // B must come from C, D, E or F.
3664 unsigned HalfSize = VT.getVectorNumElements()/2;
3665 bool MatchA = false, MatchB = false;
3667 // Check if A comes from one of C, D, E, F.
3668 for (unsigned Half = 0; Half != 4; ++Half) {
3669 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3675 // Check if B comes from one of C, D, E, F.
3676 for (unsigned Half = 0; Half != 4; ++Half) {
3677 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3683 return MatchA && MatchB;
3686 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3687 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3688 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3689 EVT VT = SVOp->getValueType(0);
3691 unsigned HalfSize = VT.getVectorNumElements()/2;
3693 unsigned FstHalf = 0, SndHalf = 0;
3694 for (unsigned i = 0; i < HalfSize; ++i) {
3695 if (SVOp->getMaskElt(i) > 0) {
3696 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3700 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3701 if (SVOp->getMaskElt(i) > 0) {
3702 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3707 return (FstHalf | (SndHalf << 4));
3710 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3711 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3712 /// Note that VPERMIL mask matching is different depending whether theunderlying
3713 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3714 /// to the same elements of the low, but to the higher half of the source.
3715 /// In VPERMILPD the two lanes could be shuffled independently of each other
3716 /// with the same restriction that lanes can't be crossed.
3717 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3721 unsigned NumElts = VT.getVectorNumElements();
3722 // Only match 256-bit with 32/64-bit types
3723 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3726 unsigned NumLanes = VT.getSizeInBits()/128;
3727 unsigned LaneSize = NumElts/NumLanes;
3728 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3729 for (unsigned i = 0; i != LaneSize; ++i) {
3730 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3732 if (NumElts != 8 || l == 0)
3734 // VPERMILPS handling
3737 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3745 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3746 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3747 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3748 EVT VT = SVOp->getValueType(0);
3750 unsigned NumElts = VT.getVectorNumElements();
3751 unsigned NumLanes = VT.getSizeInBits()/128;
3752 unsigned LaneSize = NumElts/NumLanes;
3754 // Although the mask is equal for both lanes do it twice to get the cases
3755 // where a mask will match because the same mask element is undef on the
3756 // first half but valid on the second. This would get pathological cases
3757 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3758 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3760 for (unsigned i = 0; i != NumElts; ++i) {
3761 int MaskElt = SVOp->getMaskElt(i);
3764 MaskElt %= LaneSize;
3766 // VPERMILPSY, the mask of the first half must be equal to the second one
3767 if (NumElts == 8) Shamt %= LaneSize;
3768 Mask |= MaskElt << (Shamt*Shift);
3774 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3775 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3776 /// element of vector 2 and the other elements to come from vector 1 in order.
3777 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3778 bool V2IsSplat = false, bool V2IsUndef = false) {
3779 unsigned NumOps = VT.getVectorNumElements();
3780 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3783 if (!isUndefOrEqual(Mask[0], 0))
3786 for (unsigned i = 1; i != NumOps; ++i)
3787 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3788 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3789 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3795 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3796 bool V2IsUndef = false) {
3797 return isCommutedMOVLMask(N->getMask(), N->getValueType(0),
3798 V2IsSplat, V2IsUndef);
3801 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3802 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3803 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3804 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3805 const X86Subtarget *Subtarget) {
3806 if (!Subtarget->hasSSE3())
3809 // The second vector must be undef
3810 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3813 EVT VT = N->getValueType(0);
3814 unsigned NumElems = VT.getVectorNumElements();
3816 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3817 (VT.getSizeInBits() == 256 && NumElems != 8))
3820 // "i+1" is the value the indexed mask element must have
3821 for (unsigned i = 0; i < NumElems; i += 2)
3822 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3823 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3829 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3830 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3831 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3832 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3833 const X86Subtarget *Subtarget) {
3834 if (!Subtarget->hasSSE3())
3837 // The second vector must be undef
3838 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3841 EVT VT = N->getValueType(0);
3842 unsigned NumElems = VT.getVectorNumElements();
3844 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3845 (VT.getSizeInBits() == 256 && NumElems != 8))
3848 // "i" is the value the indexed mask element must have
3849 for (unsigned i = 0; i != NumElems; i += 2)
3850 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3851 !isUndefOrEqual(N->getMaskElt(i+1), i))
3857 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3858 /// specifies a shuffle of elements that is suitable for input to 256-bit
3859 /// version of MOVDDUP.
3860 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3861 unsigned NumElts = VT.getVectorNumElements();
3863 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3866 for (unsigned i = 0; i != NumElts/2; ++i)
3867 if (!isUndefOrEqual(Mask[i], 0))
3869 for (unsigned i = NumElts/2; i != NumElts; ++i)
3870 if (!isUndefOrEqual(Mask[i], NumElts/2))
3875 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3876 /// specifies a shuffle of elements that is suitable for input to 128-bit
3877 /// version of MOVDDUP.
3878 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3879 EVT VT = N->getValueType(0);
3881 if (VT.getSizeInBits() != 128)
3884 unsigned e = VT.getVectorNumElements() / 2;
3885 for (unsigned i = 0; i != e; ++i)
3886 if (!isUndefOrEqual(N->getMaskElt(i), i))
3888 for (unsigned i = 0; i != e; ++i)
3889 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3894 /// isVEXTRACTF128Index - Return true if the specified
3895 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3896 /// suitable for input to VEXTRACTF128.
3897 bool X86::isVEXTRACTF128Index(SDNode *N) {
3898 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3901 // The index should be aligned on a 128-bit boundary.
3903 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3905 unsigned VL = N->getValueType(0).getVectorNumElements();
3906 unsigned VBits = N->getValueType(0).getSizeInBits();
3907 unsigned ElSize = VBits / VL;
3908 bool Result = (Index * ElSize) % 128 == 0;
3913 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3914 /// operand specifies a subvector insert that is suitable for input to
3916 bool X86::isVINSERTF128Index(SDNode *N) {
3917 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3920 // The index should be aligned on a 128-bit boundary.
3922 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3924 unsigned VL = N->getValueType(0).getVectorNumElements();
3925 unsigned VBits = N->getValueType(0).getSizeInBits();
3926 unsigned ElSize = VBits / VL;
3927 bool Result = (Index * ElSize) % 128 == 0;
3932 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3933 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3934 /// Handles 128-bit and 256-bit.
3935 unsigned X86::getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3936 EVT VT = N->getValueType(0);
3938 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3939 "Unsupported vector type for PSHUF/SHUFP");
3941 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3942 // independently on 128-bit lanes.
3943 unsigned NumElts = VT.getVectorNumElements();
3944 unsigned NumLanes = VT.getSizeInBits()/128;
3945 unsigned NumLaneElts = NumElts/NumLanes;
3947 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3948 "Only supports 2 or 4 elements per lane");
3950 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3952 for (unsigned i = 0; i != NumElts; ++i) {
3953 int Elt = N->getMaskElt(i);
3954 if (Elt < 0) continue;
3956 unsigned ShAmt = i << Shift;
3957 if (ShAmt >= 8) ShAmt -= 8;
3958 Mask |= Elt << ShAmt;
3964 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3965 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3966 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3967 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3969 // 8 nodes, but we only care about the last 4.
3970 for (unsigned i = 7; i >= 4; --i) {
3971 int Val = SVOp->getMaskElt(i);
3980 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3981 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3982 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3983 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3985 // 8 nodes, but we only care about the first 4.
3986 for (int i = 3; i >= 0; --i) {
3987 int Val = SVOp->getMaskElt(i);
3996 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3997 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3998 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3999 EVT VT = SVOp->getValueType(0);
4000 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4002 unsigned NumElts = VT.getVectorNumElements();
4003 unsigned NumLanes = VT.getSizeInBits()/128;
4004 unsigned NumLaneElts = NumElts/NumLanes;
4008 for (i = 0; i != NumElts; ++i) {
4009 Val = SVOp->getMaskElt(i);
4013 if (Val >= (int)NumElts)
4014 Val -= NumElts - NumLaneElts;
4016 assert(Val - i > 0 && "PALIGNR imm should be positive");
4017 return (Val - i) * EltSize;
4020 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4021 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4023 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4024 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4025 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4028 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4030 EVT VecVT = N->getOperand(0).getValueType();
4031 EVT ElVT = VecVT.getVectorElementType();
4033 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4034 return Index / NumElemsPerChunk;
4037 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4038 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4040 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4041 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4042 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4045 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4047 EVT VecVT = N->getValueType(0);
4048 EVT ElVT = VecVT.getVectorElementType();
4050 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4051 return Index / NumElemsPerChunk;
4054 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4056 bool X86::isZeroNode(SDValue Elt) {
4057 return ((isa<ConstantSDNode>(Elt) &&
4058 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4059 (isa<ConstantFPSDNode>(Elt) &&
4060 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4063 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4064 /// their permute mask.
4065 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4066 SelectionDAG &DAG) {
4067 EVT VT = SVOp->getValueType(0);
4068 unsigned NumElems = VT.getVectorNumElements();
4069 SmallVector<int, 8> MaskVec;
4071 for (unsigned i = 0; i != NumElems; ++i) {
4072 int idx = SVOp->getMaskElt(i);
4074 MaskVec.push_back(idx);
4075 else if (idx < (int)NumElems)
4076 MaskVec.push_back(idx + NumElems);
4078 MaskVec.push_back(idx - NumElems);
4080 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4081 SVOp->getOperand(0), &MaskVec[0]);
4084 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4085 /// match movhlps. The lower half elements should come from upper half of
4086 /// V1 (and in order), and the upper half elements should come from the upper
4087 /// half of V2 (and in order).
4088 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4089 EVT VT = Op->getValueType(0);
4090 if (VT.getSizeInBits() != 128)
4092 if (VT.getVectorNumElements() != 4)
4094 for (unsigned i = 0, e = 2; i != e; ++i)
4095 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4097 for (unsigned i = 2; i != 4; ++i)
4098 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4103 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4104 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4106 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4107 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4109 N = N->getOperand(0).getNode();
4110 if (!ISD::isNON_EXTLoad(N))
4113 *LD = cast<LoadSDNode>(N);
4117 // Test whether the given value is a vector value which will be legalized
4119 static bool WillBeConstantPoolLoad(SDNode *N) {
4120 if (N->getOpcode() != ISD::BUILD_VECTOR)
4123 // Check for any non-constant elements.
4124 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4125 switch (N->getOperand(i).getNode()->getOpcode()) {
4127 case ISD::ConstantFP:
4134 // Vectors of all-zeros and all-ones are materialized with special
4135 // instructions rather than being loaded.
4136 return !ISD::isBuildVectorAllZeros(N) &&
4137 !ISD::isBuildVectorAllOnes(N);
4140 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4141 /// match movlp{s|d}. The lower half elements should come from lower half of
4142 /// V1 (and in order), and the upper half elements should come from the upper
4143 /// half of V2 (and in order). And since V1 will become the source of the
4144 /// MOVLP, it must be either a vector load or a scalar load to vector.
4145 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4146 ShuffleVectorSDNode *Op) {
4147 EVT VT = Op->getValueType(0);
4148 if (VT.getSizeInBits() != 128)
4151 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4153 // Is V2 is a vector load, don't do this transformation. We will try to use
4154 // load folding shufps op.
4155 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4158 unsigned NumElems = VT.getVectorNumElements();
4160 if (NumElems != 2 && NumElems != 4)
4162 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4163 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4165 for (unsigned i = NumElems/2; i != NumElems; ++i)
4166 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4171 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4173 static bool isSplatVector(SDNode *N) {
4174 if (N->getOpcode() != ISD::BUILD_VECTOR)
4177 SDValue SplatValue = N->getOperand(0);
4178 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4179 if (N->getOperand(i) != SplatValue)
4184 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4185 /// to an zero vector.
4186 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4187 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4188 SDValue V1 = N->getOperand(0);
4189 SDValue V2 = N->getOperand(1);
4190 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4191 for (unsigned i = 0; i != NumElems; ++i) {
4192 int Idx = N->getMaskElt(i);
4193 if (Idx >= (int)NumElems) {
4194 unsigned Opc = V2.getOpcode();
4195 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4197 if (Opc != ISD::BUILD_VECTOR ||
4198 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4200 } else if (Idx >= 0) {
4201 unsigned Opc = V1.getOpcode();
4202 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4204 if (Opc != ISD::BUILD_VECTOR ||
4205 !X86::isZeroNode(V1.getOperand(Idx)))
4212 /// getZeroVector - Returns a vector of specified type with all zero elements.
4214 static SDValue getZeroVector(EVT VT, bool HasSSE2, bool HasAVX2,
4215 SelectionDAG &DAG, DebugLoc dl) {
4216 assert(VT.isVector() && "Expected a vector type");
4218 // Always build SSE zero vectors as <4 x i32> bitcasted
4219 // to their dest type. This ensures they get CSE'd.
4221 if (VT.getSizeInBits() == 128) { // SSE
4222 if (HasSSE2) { // SSE2
4223 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4224 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4226 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4227 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4229 } else if (VT.getSizeInBits() == 256) { // AVX
4230 if (HasAVX2) { // AVX2
4231 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4232 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4233 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4235 // 256-bit logic and arithmetic instructions in AVX are all
4236 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4237 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4238 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4239 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4242 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4245 /// getOnesVector - Returns a vector of specified type with all bits set.
4246 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4247 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4248 /// Then bitcast to their original type, ensuring they get CSE'd.
4249 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4251 assert(VT.isVector() && "Expected a vector type");
4252 assert((VT.is128BitVector() || VT.is256BitVector())
4253 && "Expected a 128-bit or 256-bit vector type");
4255 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4257 if (VT.getSizeInBits() == 256) {
4258 if (HasAVX2) { // AVX2
4259 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4260 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4262 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4263 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4264 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4265 Vec = Insert128BitVector(InsV, Vec,
4266 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4272 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4275 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4276 /// that point to V2 points to its first element.
4277 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4278 EVT VT = SVOp->getValueType(0);
4279 unsigned NumElems = VT.getVectorNumElements();
4281 bool Changed = false;
4282 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end());
4284 for (unsigned i = 0; i != NumElems; ++i) {
4285 if (MaskVec[i] > (int)NumElems) {
4286 MaskVec[i] = NumElems;
4291 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4292 SVOp->getOperand(1), &MaskVec[0]);
4293 return SDValue(SVOp, 0);
4296 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4297 /// operation of specified width.
4298 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4300 unsigned NumElems = VT.getVectorNumElements();
4301 SmallVector<int, 8> Mask;
4302 Mask.push_back(NumElems);
4303 for (unsigned i = 1; i != NumElems; ++i)
4305 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4308 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4309 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4311 unsigned NumElems = VT.getVectorNumElements();
4312 SmallVector<int, 8> Mask;
4313 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4315 Mask.push_back(i + NumElems);
4317 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4320 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4321 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4323 unsigned NumElems = VT.getVectorNumElements();
4324 unsigned Half = NumElems/2;
4325 SmallVector<int, 8> Mask;
4326 for (unsigned i = 0; i != Half; ++i) {
4327 Mask.push_back(i + Half);
4328 Mask.push_back(i + NumElems + Half);
4330 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4333 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4334 // a generic shuffle instruction because the target has no such instructions.
4335 // Generate shuffles which repeat i16 and i8 several times until they can be
4336 // represented by v4f32 and then be manipulated by target suported shuffles.
4337 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4338 EVT VT = V.getValueType();
4339 int NumElems = VT.getVectorNumElements();
4340 DebugLoc dl = V.getDebugLoc();
4342 while (NumElems > 4) {
4343 if (EltNo < NumElems/2) {
4344 V = getUnpackl(DAG, dl, VT, V, V);
4346 V = getUnpackh(DAG, dl, VT, V, V);
4347 EltNo -= NumElems/2;
4354 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4355 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4356 EVT VT = V.getValueType();
4357 DebugLoc dl = V.getDebugLoc();
4358 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4359 && "Vector size not supported");
4361 if (VT.getSizeInBits() == 128) {
4362 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4363 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4364 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4367 // To use VPERMILPS to splat scalars, the second half of indicies must
4368 // refer to the higher part, which is a duplication of the lower one,
4369 // because VPERMILPS can only handle in-lane permutations.
4370 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4371 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4373 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4374 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4378 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4381 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4382 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4383 EVT SrcVT = SV->getValueType(0);
4384 SDValue V1 = SV->getOperand(0);
4385 DebugLoc dl = SV->getDebugLoc();
4387 int EltNo = SV->getSplatIndex();
4388 int NumElems = SrcVT.getVectorNumElements();
4389 unsigned Size = SrcVT.getSizeInBits();
4391 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4392 "Unknown how to promote splat for type");
4394 // Extract the 128-bit part containing the splat element and update
4395 // the splat element index when it refers to the higher register.
4397 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4398 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4400 EltNo -= NumElems/2;
4403 // All i16 and i8 vector types can't be used directly by a generic shuffle
4404 // instruction because the target has no such instruction. Generate shuffles
4405 // which repeat i16 and i8 several times until they fit in i32, and then can
4406 // be manipulated by target suported shuffles.
4407 EVT EltVT = SrcVT.getVectorElementType();
4408 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4409 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4411 // Recreate the 256-bit vector and place the same 128-bit vector
4412 // into the low and high part. This is necessary because we want
4413 // to use VPERM* to shuffle the vectors
4415 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4416 DAG.getConstant(0, MVT::i32), DAG, dl);
4417 V1 = Insert128BitVector(InsV, V1,
4418 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4421 return getLegalSplat(DAG, V1, EltNo);
4424 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4425 /// vector of zero or undef vector. This produces a shuffle where the low
4426 /// element of V2 is swizzled into the zero/undef vector, landing at element
4427 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4428 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4430 const X86Subtarget *Subtarget,
4431 SelectionDAG &DAG) {
4432 EVT VT = V2.getValueType();
4434 ? getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG,
4435 V2.getDebugLoc()) : DAG.getUNDEF(VT);
4436 unsigned NumElems = VT.getVectorNumElements();
4437 SmallVector<int, 16> MaskVec;
4438 for (unsigned i = 0; i != NumElems; ++i)
4439 // If this is the insertion idx, put the low elt of V2 here.
4440 MaskVec.push_back(i == Idx ? NumElems : i);
4441 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4444 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4445 /// element of the result of the vector shuffle.
4446 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4449 return SDValue(); // Limit search depth.
4451 SDValue V = SDValue(N, 0);
4452 EVT VT = V.getValueType();
4453 unsigned Opcode = V.getOpcode();
4455 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4456 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4457 Index = SV->getMaskElt(Index);
4460 return DAG.getUNDEF(VT.getVectorElementType());
4462 int NumElems = VT.getVectorNumElements();
4463 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4464 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4467 // Recurse into target specific vector shuffles to find scalars.
4468 if (isTargetShuffle(Opcode)) {
4469 int NumElems = VT.getVectorNumElements();
4470 SmallVector<unsigned, 16> ShuffleMask;
4475 ImmN = N->getOperand(N->getNumOperands()-1);
4476 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4479 case X86ISD::UNPCKH:
4480 DecodeUNPCKHMask(VT, ShuffleMask);
4482 case X86ISD::UNPCKL:
4483 DecodeUNPCKLMask(VT, ShuffleMask);
4485 case X86ISD::MOVHLPS:
4486 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4488 case X86ISD::MOVLHPS:
4489 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4491 case X86ISD::PSHUFD:
4492 ImmN = N->getOperand(N->getNumOperands()-1);
4493 DecodePSHUFMask(NumElems,
4494 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4497 case X86ISD::PSHUFHW:
4498 ImmN = N->getOperand(N->getNumOperands()-1);
4499 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4502 case X86ISD::PSHUFLW:
4503 ImmN = N->getOperand(N->getNumOperands()-1);
4504 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4508 case X86ISD::MOVSD: {
4509 // The index 0 always comes from the first element of the second source,
4510 // this is why MOVSS and MOVSD are used in the first place. The other
4511 // elements come from the other positions of the first source vector.
4512 unsigned OpNum = (Index == 0) ? 1 : 0;
4513 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4516 case X86ISD::VPERMILP:
4517 ImmN = N->getOperand(N->getNumOperands()-1);
4518 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4521 case X86ISD::VPERM2X128:
4522 ImmN = N->getOperand(N->getNumOperands()-1);
4523 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4526 case X86ISD::MOVDDUP:
4527 case X86ISD::MOVLHPD:
4528 case X86ISD::MOVLPD:
4529 case X86ISD::MOVLPS:
4530 case X86ISD::MOVSHDUP:
4531 case X86ISD::MOVSLDUP:
4532 case X86ISD::PALIGN:
4533 return SDValue(); // Not yet implemented.
4535 assert(0 && "unknown target shuffle node");
4539 Index = ShuffleMask[Index];
4541 return DAG.getUNDEF(VT.getVectorElementType());
4543 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4544 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4548 // Actual nodes that may contain scalar elements
4549 if (Opcode == ISD::BITCAST) {
4550 V = V.getOperand(0);
4551 EVT SrcVT = V.getValueType();
4552 unsigned NumElems = VT.getVectorNumElements();
4554 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4558 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4559 return (Index == 0) ? V.getOperand(0)
4560 : DAG.getUNDEF(VT.getVectorElementType());
4562 if (V.getOpcode() == ISD::BUILD_VECTOR)
4563 return V.getOperand(Index);
4568 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4569 /// shuffle operation which come from a consecutively from a zero. The
4570 /// search can start in two different directions, from left or right.
4572 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4573 bool ZerosFromLeft, SelectionDAG &DAG) {
4576 while (i < NumElems) {
4577 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4578 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4579 if (!(Elt.getNode() &&
4580 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4588 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4589 /// MaskE correspond consecutively to elements from one of the vector operands,
4590 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4592 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4593 int OpIdx, int NumElems, unsigned &OpNum) {
4594 bool SeenV1 = false;
4595 bool SeenV2 = false;
4597 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4598 int Idx = SVOp->getMaskElt(i);
4599 // Ignore undef indicies
4608 // Only accept consecutive elements from the same vector
4609 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4613 OpNum = SeenV1 ? 0 : 1;
4617 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4618 /// logical left shift of a vector.
4619 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4620 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4621 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4622 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4623 false /* check zeros from right */, DAG);
4629 // Considering the elements in the mask that are not consecutive zeros,
4630 // check if they consecutively come from only one of the source vectors.
4632 // V1 = {X, A, B, C} 0
4634 // vector_shuffle V1, V2 <1, 2, 3, X>
4636 if (!isShuffleMaskConsecutive(SVOp,
4637 0, // Mask Start Index
4638 NumElems-NumZeros-1, // Mask End Index
4639 NumZeros, // Where to start looking in the src vector
4640 NumElems, // Number of elements in vector
4641 OpSrc)) // Which source operand ?
4646 ShVal = SVOp->getOperand(OpSrc);
4650 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4651 /// logical left shift of a vector.
4652 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4653 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4654 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4655 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4656 true /* check zeros from left */, DAG);
4662 // Considering the elements in the mask that are not consecutive zeros,
4663 // check if they consecutively come from only one of the source vectors.
4665 // 0 { A, B, X, X } = V2
4667 // vector_shuffle V1, V2 <X, X, 4, 5>
4669 if (!isShuffleMaskConsecutive(SVOp,
4670 NumZeros, // Mask Start Index
4671 NumElems-1, // Mask End Index
4672 0, // Where to start looking in the src vector
4673 NumElems, // Number of elements in vector
4674 OpSrc)) // Which source operand ?
4679 ShVal = SVOp->getOperand(OpSrc);
4683 /// isVectorShift - Returns true if the shuffle can be implemented as a
4684 /// logical left or right shift of a vector.
4685 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4686 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4687 // Although the logic below support any bitwidth size, there are no
4688 // shift instructions which handle more than 128-bit vectors.
4689 if (SVOp->getValueType(0).getSizeInBits() > 128)
4692 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4693 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4699 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4701 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4702 unsigned NumNonZero, unsigned NumZero,
4704 const TargetLowering &TLI) {
4708 DebugLoc dl = Op.getDebugLoc();
4711 for (unsigned i = 0; i < 16; ++i) {
4712 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4713 if (ThisIsNonZero && First) {
4715 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4718 V = DAG.getUNDEF(MVT::v8i16);
4723 SDValue ThisElt(0, 0), LastElt(0, 0);
4724 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4725 if (LastIsNonZero) {
4726 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4727 MVT::i16, Op.getOperand(i-1));
4729 if (ThisIsNonZero) {
4730 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4731 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4732 ThisElt, DAG.getConstant(8, MVT::i8));
4734 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4738 if (ThisElt.getNode())
4739 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4740 DAG.getIntPtrConstant(i/2));
4744 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4747 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4749 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4750 unsigned NumNonZero, unsigned NumZero,
4752 const TargetLowering &TLI) {
4756 DebugLoc dl = Op.getDebugLoc();
4759 for (unsigned i = 0; i < 8; ++i) {
4760 bool isNonZero = (NonZeros & (1 << i)) != 0;
4764 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4767 V = DAG.getUNDEF(MVT::v8i16);
4770 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4771 MVT::v8i16, V, Op.getOperand(i),
4772 DAG.getIntPtrConstant(i));
4779 /// getVShift - Return a vector logical shift node.
4781 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4782 unsigned NumBits, SelectionDAG &DAG,
4783 const TargetLowering &TLI, DebugLoc dl) {
4784 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4785 EVT ShVT = MVT::v2i64;
4786 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4787 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4788 return DAG.getNode(ISD::BITCAST, dl, VT,
4789 DAG.getNode(Opc, dl, ShVT, SrcOp,
4790 DAG.getConstant(NumBits,
4791 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4795 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4796 SelectionDAG &DAG) const {
4798 // Check if the scalar load can be widened into a vector load. And if
4799 // the address is "base + cst" see if the cst can be "absorbed" into
4800 // the shuffle mask.
4801 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4802 SDValue Ptr = LD->getBasePtr();
4803 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4805 EVT PVT = LD->getValueType(0);
4806 if (PVT != MVT::i32 && PVT != MVT::f32)
4811 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4812 FI = FINode->getIndex();
4814 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4815 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4816 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4817 Offset = Ptr.getConstantOperandVal(1);
4818 Ptr = Ptr.getOperand(0);
4823 // FIXME: 256-bit vector instructions don't require a strict alignment,
4824 // improve this code to support it better.
4825 unsigned RequiredAlign = VT.getSizeInBits()/8;
4826 SDValue Chain = LD->getChain();
4827 // Make sure the stack object alignment is at least 16 or 32.
4828 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4829 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4830 if (MFI->isFixedObjectIndex(FI)) {
4831 // Can't change the alignment. FIXME: It's possible to compute
4832 // the exact stack offset and reference FI + adjust offset instead.
4833 // If someone *really* cares about this. That's the way to implement it.
4836 MFI->setObjectAlignment(FI, RequiredAlign);
4840 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4841 // Ptr + (Offset & ~15).
4844 if ((Offset % RequiredAlign) & 3)
4846 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4848 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4849 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4851 int EltNo = (Offset - StartOffset) >> 2;
4852 int NumElems = VT.getVectorNumElements();
4854 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4855 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4856 LD->getPointerInfo().getWithOffset(StartOffset),
4857 false, false, false, 0);
4859 SmallVector<int, 8> Mask;
4860 for (int i = 0; i < NumElems; ++i)
4861 Mask.push_back(EltNo);
4863 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4869 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4870 /// vector of type 'VT', see if the elements can be replaced by a single large
4871 /// load which has the same value as a build_vector whose operands are 'elts'.
4873 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4875 /// FIXME: we'd also like to handle the case where the last elements are zero
4876 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4877 /// There's even a handy isZeroNode for that purpose.
4878 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4879 DebugLoc &DL, SelectionDAG &DAG) {
4880 EVT EltVT = VT.getVectorElementType();
4881 unsigned NumElems = Elts.size();
4883 LoadSDNode *LDBase = NULL;
4884 unsigned LastLoadedElt = -1U;
4886 // For each element in the initializer, see if we've found a load or an undef.
4887 // If we don't find an initial load element, or later load elements are
4888 // non-consecutive, bail out.
4889 for (unsigned i = 0; i < NumElems; ++i) {
4890 SDValue Elt = Elts[i];
4892 if (!Elt.getNode() ||
4893 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4896 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4898 LDBase = cast<LoadSDNode>(Elt.getNode());
4902 if (Elt.getOpcode() == ISD::UNDEF)
4905 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4906 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4911 // If we have found an entire vector of loads and undefs, then return a large
4912 // load of the entire vector width starting at the base pointer. If we found
4913 // consecutive loads for the low half, generate a vzext_load node.
4914 if (LastLoadedElt == NumElems - 1) {
4915 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4916 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4917 LDBase->getPointerInfo(),
4918 LDBase->isVolatile(), LDBase->isNonTemporal(),
4919 LDBase->isInvariant(), 0);
4920 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4921 LDBase->getPointerInfo(),
4922 LDBase->isVolatile(), LDBase->isNonTemporal(),
4923 LDBase->isInvariant(), LDBase->getAlignment());
4924 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4925 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4926 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4927 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4929 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4930 LDBase->getPointerInfo(),
4931 LDBase->getAlignment(),
4932 false/*isVolatile*/, true/*ReadMem*/,
4934 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4939 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4940 /// a vbroadcast node. We support two patterns:
4941 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4942 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4944 /// The scalar load node is returned when a pattern is found,
4945 /// or SDValue() otherwise.
4946 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4947 if (!Subtarget->hasAVX())
4950 EVT VT = Op.getValueType();
4953 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4954 V = V.getOperand(0);
4956 //A suspected load to be broadcasted.
4959 switch (V.getOpcode()) {
4961 // Unknown pattern found.
4964 case ISD::BUILD_VECTOR: {
4965 // The BUILD_VECTOR node must be a splat.
4966 if (!isSplatVector(V.getNode()))
4969 Ld = V.getOperand(0);
4971 // The suspected load node has several users. Make sure that all
4972 // of its users are from the BUILD_VECTOR node.
4973 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4978 case ISD::VECTOR_SHUFFLE: {
4979 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4981 // Shuffles must have a splat mask where the first element is
4983 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4986 SDValue Sc = Op.getOperand(0);
4987 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4990 Ld = Sc.getOperand(0);
4992 // The scalar_to_vector node and the suspected
4993 // load node must have exactly one user.
4994 if (!Sc.hasOneUse() || !Ld.hasOneUse())
5000 // The scalar source must be a normal load.
5001 if (!ISD::isNormalLoad(Ld.getNode()))
5004 // Reject loads that have uses of the chain result
5005 if (Ld->hasAnyUseOfValue(1))
5008 bool Is256 = VT.getSizeInBits() == 256;
5009 bool Is128 = VT.getSizeInBits() == 128;
5010 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5012 // VBroadcast to YMM
5013 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5016 // VBroadcast to XMM
5017 if (Is128 && (ScalarSize == 32))
5020 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5021 // double since there is vbroadcastsd xmm
5022 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5023 // VBroadcast to YMM
5024 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5027 // VBroadcast to XMM
5028 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5032 // Unsupported broadcast.
5037 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5038 DebugLoc dl = Op.getDebugLoc();
5040 EVT VT = Op.getValueType();
5041 EVT ExtVT = VT.getVectorElementType();
5042 unsigned NumElems = Op.getNumOperands();
5044 // Vectors containing all zeros can be matched by pxor and xorps later
5045 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5046 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5047 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5048 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5051 return getZeroVector(VT, Subtarget->hasSSE2(),
5052 Subtarget->hasAVX2(), DAG, dl);
5055 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5056 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5057 // vpcmpeqd on 256-bit vectors.
5058 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5059 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5062 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5065 SDValue LD = isVectorBroadcast(Op, Subtarget);
5067 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5069 unsigned EVTBits = ExtVT.getSizeInBits();
5071 unsigned NumZero = 0;
5072 unsigned NumNonZero = 0;
5073 unsigned NonZeros = 0;
5074 bool IsAllConstants = true;
5075 SmallSet<SDValue, 8> Values;
5076 for (unsigned i = 0; i < NumElems; ++i) {
5077 SDValue Elt = Op.getOperand(i);
5078 if (Elt.getOpcode() == ISD::UNDEF)
5081 if (Elt.getOpcode() != ISD::Constant &&
5082 Elt.getOpcode() != ISD::ConstantFP)
5083 IsAllConstants = false;
5084 if (X86::isZeroNode(Elt))
5087 NonZeros |= (1 << i);
5092 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5093 if (NumNonZero == 0)
5094 return DAG.getUNDEF(VT);
5096 // Special case for single non-zero, non-undef, element.
5097 if (NumNonZero == 1) {
5098 unsigned Idx = CountTrailingZeros_32(NonZeros);
5099 SDValue Item = Op.getOperand(Idx);
5101 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5102 // the value are obviously zero, truncate the value to i32 and do the
5103 // insertion that way. Only do this if the value is non-constant or if the
5104 // value is a constant being inserted into element 0. It is cheaper to do
5105 // a constant pool load than it is to do a movd + shuffle.
5106 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5107 (!IsAllConstants || Idx == 0)) {
5108 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5110 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5111 EVT VecVT = MVT::v4i32;
5112 unsigned VecElts = 4;
5114 // Truncate the value (which may itself be a constant) to i32, and
5115 // convert it to a vector with movd (S2V+shuffle to zero extend).
5116 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5117 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5118 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5120 // Now we have our 32-bit value zero extended in the low element of
5121 // a vector. If Idx != 0, swizzle it into place.
5123 SmallVector<int, 4> Mask;
5124 Mask.push_back(Idx);
5125 for (unsigned i = 1; i != VecElts; ++i)
5127 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5128 DAG.getUNDEF(Item.getValueType()),
5131 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5135 // If we have a constant or non-constant insertion into the low element of
5136 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5137 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5138 // depending on what the source datatype is.
5141 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5143 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5144 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5145 if (VT.getSizeInBits() == 256) {
5146 SDValue ZeroVec = getZeroVector(VT, Subtarget->hasSSE2(),
5147 Subtarget->hasAVX2(), DAG, dl);
5148 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5149 Item, DAG.getIntPtrConstant(0));
5151 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5152 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5153 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5154 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5157 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5158 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5159 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5160 if (VT.getSizeInBits() == 256) {
5161 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget->hasSSE2(),
5162 Subtarget->hasAVX2(), DAG, dl);
5163 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5166 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5167 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5169 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5173 // Is it a vector logical left shift?
5174 if (NumElems == 2 && Idx == 1 &&
5175 X86::isZeroNode(Op.getOperand(0)) &&
5176 !X86::isZeroNode(Op.getOperand(1))) {
5177 unsigned NumBits = VT.getSizeInBits();
5178 return getVShift(true, VT,
5179 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5180 VT, Op.getOperand(1)),
5181 NumBits/2, DAG, *this, dl);
5184 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5187 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5188 // is a non-constant being inserted into an element other than the low one,
5189 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5190 // movd/movss) to move this into the low element, then shuffle it into
5192 if (EVTBits == 32) {
5193 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5195 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5196 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5197 SmallVector<int, 8> MaskVec;
5198 for (unsigned i = 0; i < NumElems; i++)
5199 MaskVec.push_back(i == Idx ? 0 : 1);
5200 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5204 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5205 if (Values.size() == 1) {
5206 if (EVTBits == 32) {
5207 // Instead of a shuffle like this:
5208 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5209 // Check if it's possible to issue this instead.
5210 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5211 unsigned Idx = CountTrailingZeros_32(NonZeros);
5212 SDValue Item = Op.getOperand(Idx);
5213 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5214 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5219 // A vector full of immediates; various special cases are already
5220 // handled, so this is best done with a single constant-pool load.
5224 // For AVX-length vectors, build the individual 128-bit pieces and use
5225 // shuffles to put them in place.
5226 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5227 SmallVector<SDValue, 32> V;
5228 for (unsigned i = 0; i < NumElems; ++i)
5229 V.push_back(Op.getOperand(i));
5231 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5233 // Build both the lower and upper subvector.
5234 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5235 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5238 // Recreate the wider vector with the lower and upper part.
5239 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5240 DAG.getConstant(0, MVT::i32), DAG, dl);
5241 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5245 // Let legalizer expand 2-wide build_vectors.
5246 if (EVTBits == 64) {
5247 if (NumNonZero == 1) {
5248 // One half is zero or undef.
5249 unsigned Idx = CountTrailingZeros_32(NonZeros);
5250 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5251 Op.getOperand(Idx));
5252 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5257 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5258 if (EVTBits == 8 && NumElems == 16) {
5259 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5261 if (V.getNode()) return V;
5264 if (EVTBits == 16 && NumElems == 8) {
5265 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5267 if (V.getNode()) return V;
5270 // If element VT is == 32 bits, turn it into a number of shuffles.
5271 SmallVector<SDValue, 8> V(NumElems);
5272 if (NumElems == 4 && NumZero > 0) {
5273 for (unsigned i = 0; i < 4; ++i) {
5274 bool isZero = !(NonZeros & (1 << i));
5276 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
5279 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5282 for (unsigned i = 0; i < 2; ++i) {
5283 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5286 V[i] = V[i*2]; // Must be a zero vector.
5289 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5292 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5295 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5300 bool Reverse1 = (NonZeros & 0x3) == 2;
5301 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5305 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5306 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5308 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5311 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5312 // Check for a build vector of consecutive loads.
5313 for (unsigned i = 0; i < NumElems; ++i)
5314 V[i] = Op.getOperand(i);
5316 // Check for elements which are consecutive loads.
5317 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5321 // For SSE 4.1, use insertps to put the high elements into the low element.
5322 if (getSubtarget()->hasSSE41()) {
5324 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5325 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5327 Result = DAG.getUNDEF(VT);
5329 for (unsigned i = 1; i < NumElems; ++i) {
5330 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5331 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5332 Op.getOperand(i), DAG.getIntPtrConstant(i));
5337 // Otherwise, expand into a number of unpckl*, start by extending each of
5338 // our (non-undef) elements to the full vector width with the element in the
5339 // bottom slot of the vector (which generates no code for SSE).
5340 for (unsigned i = 0; i < NumElems; ++i) {
5341 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5342 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5344 V[i] = DAG.getUNDEF(VT);
5347 // Next, we iteratively mix elements, e.g. for v4f32:
5348 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5349 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5350 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5351 unsigned EltStride = NumElems >> 1;
5352 while (EltStride != 0) {
5353 for (unsigned i = 0; i < EltStride; ++i) {
5354 // If V[i+EltStride] is undef and this is the first round of mixing,
5355 // then it is safe to just drop this shuffle: V[i] is already in the
5356 // right place, the one element (since it's the first round) being
5357 // inserted as undef can be dropped. This isn't safe for successive
5358 // rounds because they will permute elements within both vectors.
5359 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5360 EltStride == NumElems/2)
5363 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5372 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5373 // them in a MMX register. This is better than doing a stack convert.
5374 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5375 DebugLoc dl = Op.getDebugLoc();
5376 EVT ResVT = Op.getValueType();
5378 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5379 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5381 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5382 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5383 InVec = Op.getOperand(1);
5384 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5385 unsigned NumElts = ResVT.getVectorNumElements();
5386 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5387 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5388 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5390 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5391 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5392 Mask[0] = 0; Mask[1] = 2;
5393 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5395 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5398 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5399 // to create 256-bit vectors from two other 128-bit ones.
5400 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5401 DebugLoc dl = Op.getDebugLoc();
5402 EVT ResVT = Op.getValueType();
5404 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5406 SDValue V1 = Op.getOperand(0);
5407 SDValue V2 = Op.getOperand(1);
5408 unsigned NumElems = ResVT.getVectorNumElements();
5410 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5411 DAG.getConstant(0, MVT::i32), DAG, dl);
5412 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5417 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5418 EVT ResVT = Op.getValueType();
5420 assert(Op.getNumOperands() == 2);
5421 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5422 "Unsupported CONCAT_VECTORS for value type");
5424 // We support concatenate two MMX registers and place them in a MMX register.
5425 // This is better than doing a stack convert.
5426 if (ResVT.is128BitVector())
5427 return LowerMMXCONCAT_VECTORS(Op, DAG);
5429 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5430 // from two other 128-bit ones.
5431 return LowerAVXCONCAT_VECTORS(Op, DAG);
5434 // v8i16 shuffles - Prefer shuffles in the following order:
5435 // 1. [all] pshuflw, pshufhw, optional move
5436 // 2. [ssse3] 1 x pshufb
5437 // 3. [ssse3] 2 x pshufb + 1 x por
5438 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5440 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5441 SelectionDAG &DAG) const {
5442 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5443 SDValue V1 = SVOp->getOperand(0);
5444 SDValue V2 = SVOp->getOperand(1);
5445 DebugLoc dl = SVOp->getDebugLoc();
5446 SmallVector<int, 8> MaskVals;
5448 // Determine if more than 1 of the words in each of the low and high quadwords
5449 // of the result come from the same quadword of one of the two inputs. Undef
5450 // mask values count as coming from any quadword, for better codegen.
5451 unsigned LoQuad[] = { 0, 0, 0, 0 };
5452 unsigned HiQuad[] = { 0, 0, 0, 0 };
5453 BitVector InputQuads(4);
5454 for (unsigned i = 0; i < 8; ++i) {
5455 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5456 int EltIdx = SVOp->getMaskElt(i);
5457 MaskVals.push_back(EltIdx);
5466 InputQuads.set(EltIdx / 4);
5469 int BestLoQuad = -1;
5470 unsigned MaxQuad = 1;
5471 for (unsigned i = 0; i < 4; ++i) {
5472 if (LoQuad[i] > MaxQuad) {
5474 MaxQuad = LoQuad[i];
5478 int BestHiQuad = -1;
5480 for (unsigned i = 0; i < 4; ++i) {
5481 if (HiQuad[i] > MaxQuad) {
5483 MaxQuad = HiQuad[i];
5487 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5488 // of the two input vectors, shuffle them into one input vector so only a
5489 // single pshufb instruction is necessary. If There are more than 2 input
5490 // quads, disable the next transformation since it does not help SSSE3.
5491 bool V1Used = InputQuads[0] || InputQuads[1];
5492 bool V2Used = InputQuads[2] || InputQuads[3];
5493 if (Subtarget->hasSSSE3()) {
5494 if (InputQuads.count() == 2 && V1Used && V2Used) {
5495 BestLoQuad = InputQuads.find_first();
5496 BestHiQuad = InputQuads.find_next(BestLoQuad);
5498 if (InputQuads.count() > 2) {
5504 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5505 // the shuffle mask. If a quad is scored as -1, that means that it contains
5506 // words from all 4 input quadwords.
5508 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5510 BestLoQuad < 0 ? 0 : BestLoQuad,
5511 BestHiQuad < 0 ? 1 : BestHiQuad
5513 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5514 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5515 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5516 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5518 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5519 // source words for the shuffle, to aid later transformations.
5520 bool AllWordsInNewV = true;
5521 bool InOrder[2] = { true, true };
5522 for (unsigned i = 0; i != 8; ++i) {
5523 int idx = MaskVals[i];
5525 InOrder[i/4] = false;
5526 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5528 AllWordsInNewV = false;
5532 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5533 if (AllWordsInNewV) {
5534 for (int i = 0; i != 8; ++i) {
5535 int idx = MaskVals[i];
5538 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5539 if ((idx != i) && idx < 4)
5541 if ((idx != i) && idx > 3)
5550 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5551 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5552 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5553 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5554 unsigned TargetMask = 0;
5555 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5556 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5557 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5558 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5559 V1 = NewV.getOperand(0);
5560 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5564 // If we have SSSE3, and all words of the result are from 1 input vector,
5565 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5566 // is present, fall back to case 4.
5567 if (Subtarget->hasSSSE3()) {
5568 SmallVector<SDValue,16> pshufbMask;
5570 // If we have elements from both input vectors, set the high bit of the
5571 // shuffle mask element to zero out elements that come from V2 in the V1
5572 // mask, and elements that come from V1 in the V2 mask, so that the two
5573 // results can be OR'd together.
5574 bool TwoInputs = V1Used && V2Used;
5575 for (unsigned i = 0; i != 8; ++i) {
5576 int EltIdx = MaskVals[i] * 2;
5577 if (TwoInputs && (EltIdx >= 16)) {
5578 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5579 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5582 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5583 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5585 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5586 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5587 DAG.getNode(ISD::BUILD_VECTOR, dl,
5588 MVT::v16i8, &pshufbMask[0], 16));
5590 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5592 // Calculate the shuffle mask for the second input, shuffle it, and
5593 // OR it with the first shuffled input.
5595 for (unsigned i = 0; i != 8; ++i) {
5596 int EltIdx = MaskVals[i] * 2;
5598 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5599 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5602 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5603 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5605 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5606 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5607 DAG.getNode(ISD::BUILD_VECTOR, dl,
5608 MVT::v16i8, &pshufbMask[0], 16));
5609 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5610 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5613 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5614 // and update MaskVals with new element order.
5615 std::bitset<8> InOrder;
5616 if (BestLoQuad >= 0) {
5617 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5618 for (int i = 0; i != 4; ++i) {
5619 int idx = MaskVals[i];
5622 } else if ((idx / 4) == BestLoQuad) {
5627 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5630 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5631 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5633 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5637 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5638 // and update MaskVals with the new element order.
5639 if (BestHiQuad >= 0) {
5640 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5641 for (unsigned i = 4; i != 8; ++i) {
5642 int idx = MaskVals[i];
5645 } else if ((idx / 4) == BestHiQuad) {
5646 MaskV[i] = (idx & 3) + 4;
5650 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5653 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5654 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5656 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5660 // In case BestHi & BestLo were both -1, which means each quadword has a word
5661 // from each of the four input quadwords, calculate the InOrder bitvector now
5662 // before falling through to the insert/extract cleanup.
5663 if (BestLoQuad == -1 && BestHiQuad == -1) {
5665 for (int i = 0; i != 8; ++i)
5666 if (MaskVals[i] < 0 || MaskVals[i] == i)
5670 // The other elements are put in the right place using pextrw and pinsrw.
5671 for (unsigned i = 0; i != 8; ++i) {
5674 int EltIdx = MaskVals[i];
5677 SDValue ExtOp = (EltIdx < 8)
5678 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5679 DAG.getIntPtrConstant(EltIdx))
5680 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5681 DAG.getIntPtrConstant(EltIdx - 8));
5682 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5683 DAG.getIntPtrConstant(i));
5688 // v16i8 shuffles - Prefer shuffles in the following order:
5689 // 1. [ssse3] 1 x pshufb
5690 // 2. [ssse3] 2 x pshufb + 1 x por
5691 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5693 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5695 const X86TargetLowering &TLI) {
5696 SDValue V1 = SVOp->getOperand(0);
5697 SDValue V2 = SVOp->getOperand(1);
5698 DebugLoc dl = SVOp->getDebugLoc();
5699 ArrayRef<int> MaskVals = SVOp->getMask();
5701 // If we have SSSE3, case 1 is generated when all result bytes come from
5702 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5703 // present, fall back to case 3.
5704 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5707 for (unsigned i = 0; i < 16; ++i) {
5708 int EltIdx = MaskVals[i];
5717 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5718 if (TLI.getSubtarget()->hasSSSE3()) {
5719 SmallVector<SDValue,16> pshufbMask;
5721 // If all result elements are from one input vector, then only translate
5722 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5724 // Otherwise, we have elements from both input vectors, and must zero out
5725 // elements that come from V2 in the first mask, and V1 in the second mask
5726 // so that we can OR them together.
5727 bool TwoInputs = !(V1Only || V2Only);
5728 for (unsigned i = 0; i != 16; ++i) {
5729 int EltIdx = MaskVals[i];
5730 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5731 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5734 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5736 // If all the elements are from V2, assign it to V1 and return after
5737 // building the first pshufb.
5740 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5741 DAG.getNode(ISD::BUILD_VECTOR, dl,
5742 MVT::v16i8, &pshufbMask[0], 16));
5746 // Calculate the shuffle mask for the second input, shuffle it, and
5747 // OR it with the first shuffled input.
5749 for (unsigned i = 0; i != 16; ++i) {
5750 int EltIdx = MaskVals[i];
5752 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5755 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5757 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5758 DAG.getNode(ISD::BUILD_VECTOR, dl,
5759 MVT::v16i8, &pshufbMask[0], 16));
5760 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5763 // No SSSE3 - Calculate in place words and then fix all out of place words
5764 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5765 // the 16 different words that comprise the two doublequadword input vectors.
5766 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5767 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5768 SDValue NewV = V2Only ? V2 : V1;
5769 for (int i = 0; i != 8; ++i) {
5770 int Elt0 = MaskVals[i*2];
5771 int Elt1 = MaskVals[i*2+1];
5773 // This word of the result is all undef, skip it.
5774 if (Elt0 < 0 && Elt1 < 0)
5777 // This word of the result is already in the correct place, skip it.
5778 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5780 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5783 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5784 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5787 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5788 // using a single extract together, load it and store it.
5789 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5790 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5791 DAG.getIntPtrConstant(Elt1 / 2));
5792 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5793 DAG.getIntPtrConstant(i));
5797 // If Elt1 is defined, extract it from the appropriate source. If the
5798 // source byte is not also odd, shift the extracted word left 8 bits
5799 // otherwise clear the bottom 8 bits if we need to do an or.
5801 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5802 DAG.getIntPtrConstant(Elt1 / 2));
5803 if ((Elt1 & 1) == 0)
5804 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5806 TLI.getShiftAmountTy(InsElt.getValueType())));
5808 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5809 DAG.getConstant(0xFF00, MVT::i16));
5811 // If Elt0 is defined, extract it from the appropriate source. If the
5812 // source byte is not also even, shift the extracted word right 8 bits. If
5813 // Elt1 was also defined, OR the extracted values together before
5814 // inserting them in the result.
5816 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5817 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5818 if ((Elt0 & 1) != 0)
5819 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5821 TLI.getShiftAmountTy(InsElt0.getValueType())));
5823 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5824 DAG.getConstant(0x00FF, MVT::i16));
5825 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5828 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5829 DAG.getIntPtrConstant(i));
5831 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5834 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5835 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5836 /// done when every pair / quad of shuffle mask elements point to elements in
5837 /// the right sequence. e.g.
5838 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5840 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5841 SelectionDAG &DAG, DebugLoc dl) {
5842 EVT VT = SVOp->getValueType(0);
5843 SDValue V1 = SVOp->getOperand(0);
5844 SDValue V2 = SVOp->getOperand(1);
5845 unsigned NumElems = VT.getVectorNumElements();
5846 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5848 switch (VT.getSimpleVT().SimpleTy) {
5849 default: assert(false && "Unexpected!");
5850 case MVT::v4f32: NewVT = MVT::v2f64; break;
5851 case MVT::v4i32: NewVT = MVT::v2i64; break;
5852 case MVT::v8i16: NewVT = MVT::v4i32; break;
5853 case MVT::v16i8: NewVT = MVT::v4i32; break;
5856 int Scale = NumElems / NewWidth;
5857 SmallVector<int, 8> MaskVec;
5858 for (unsigned i = 0; i < NumElems; i += Scale) {
5860 for (int j = 0; j < Scale; ++j) {
5861 int EltIdx = SVOp->getMaskElt(i+j);
5865 StartIdx = EltIdx - (EltIdx % Scale);
5866 if (EltIdx != StartIdx + j)
5870 MaskVec.push_back(-1);
5872 MaskVec.push_back(StartIdx / Scale);
5875 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5876 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5877 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5880 /// getVZextMovL - Return a zero-extending vector move low node.
5882 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5883 SDValue SrcOp, SelectionDAG &DAG,
5884 const X86Subtarget *Subtarget, DebugLoc dl) {
5885 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5886 LoadSDNode *LD = NULL;
5887 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5888 LD = dyn_cast<LoadSDNode>(SrcOp);
5890 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5892 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5893 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5894 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5895 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5896 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5898 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5899 return DAG.getNode(ISD::BITCAST, dl, VT,
5900 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5901 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5909 return DAG.getNode(ISD::BITCAST, dl, VT,
5910 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5911 DAG.getNode(ISD::BITCAST, dl,
5915 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5916 /// which could not be matched by any known target speficic shuffle
5918 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5919 EVT VT = SVOp->getValueType(0);
5921 unsigned NumElems = VT.getVectorNumElements();
5922 unsigned NumLaneElems = NumElems / 2;
5924 int MinRange[2][2] = { { static_cast<int>(NumElems),
5925 static_cast<int>(NumElems) },
5926 { static_cast<int>(NumElems),
5927 static_cast<int>(NumElems) } };
5928 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5930 // Collect used ranges for each source in each lane
5931 for (unsigned l = 0; l < 2; ++l) {
5932 unsigned LaneStart = l*NumLaneElems;
5933 for (unsigned i = 0; i != NumLaneElems; ++i) {
5934 int Idx = SVOp->getMaskElt(i+LaneStart);
5939 if (Idx >= (int)NumElems) {
5944 if (Idx > MaxRange[l][Input])
5945 MaxRange[l][Input] = Idx;
5946 if (Idx < MinRange[l][Input])
5947 MinRange[l][Input] = Idx;
5951 // Make sure each range is 128-bits
5952 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5953 for (unsigned l = 0; l < 2; ++l) {
5954 for (unsigned Input = 0; Input < 2; ++Input) {
5955 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5958 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems)
5959 ExtractIdx[l][Input] = 0;
5960 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5961 MaxRange[l][Input] < (int)NumElems)
5962 ExtractIdx[l][Input] = NumLaneElems;
5968 DebugLoc dl = SVOp->getDebugLoc();
5969 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5970 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5973 for (unsigned l = 0; l < 2; ++l) {
5974 for (unsigned Input = 0; Input < 2; ++Input) {
5975 if (ExtractIdx[l][Input] >= 0)
5976 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
5977 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
5980 Ops[l][Input] = DAG.getUNDEF(NVT);
5984 // Generate 128-bit shuffles
5985 SmallVector<int, 16> Mask1, Mask2;
5986 for (unsigned i = 0; i != NumLaneElems; ++i) {
5987 int Elt = SVOp->getMaskElt(i);
5988 if (Elt >= (int)NumElems) {
5989 Elt %= NumLaneElems;
5990 Elt += NumLaneElems;
5991 } else if (Elt >= 0) {
5992 Elt %= NumLaneElems;
5994 Mask1.push_back(Elt);
5996 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
5997 int Elt = SVOp->getMaskElt(i);
5998 if (Elt >= (int)NumElems) {
5999 Elt %= NumLaneElems;
6000 Elt += NumLaneElems;
6001 } else if (Elt >= 0) {
6002 Elt %= NumLaneElems;
6004 Mask2.push_back(Elt);
6007 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
6008 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
6010 // Concatenate the result back
6011 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
6012 DAG.getConstant(0, MVT::i32), DAG, dl);
6013 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
6017 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6018 /// 4 elements, and match them with several different shuffle types.
6020 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6021 SDValue V1 = SVOp->getOperand(0);
6022 SDValue V2 = SVOp->getOperand(1);
6023 DebugLoc dl = SVOp->getDebugLoc();
6024 EVT VT = SVOp->getValueType(0);
6026 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6028 std::pair<int, int> Locs[4];
6029 int Mask1[] = { -1, -1, -1, -1 };
6030 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6034 for (unsigned i = 0; i != 4; ++i) {
6035 int Idx = PermMask[i];
6037 Locs[i] = std::make_pair(-1, -1);
6039 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6041 Locs[i] = std::make_pair(0, NumLo);
6045 Locs[i] = std::make_pair(1, NumHi);
6047 Mask1[2+NumHi] = Idx;
6053 if (NumLo <= 2 && NumHi <= 2) {
6054 // If no more than two elements come from either vector. This can be
6055 // implemented with two shuffles. First shuffle gather the elements.
6056 // The second shuffle, which takes the first shuffle as both of its
6057 // vector operands, put the elements into the right order.
6058 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6060 int Mask2[] = { -1, -1, -1, -1 };
6062 for (unsigned i = 0; i != 4; ++i)
6063 if (Locs[i].first != -1) {
6064 unsigned Idx = (i < 2) ? 0 : 4;
6065 Idx += Locs[i].first * 2 + Locs[i].second;
6069 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6070 } else if (NumLo == 3 || NumHi == 3) {
6071 // Otherwise, we must have three elements from one vector, call it X, and
6072 // one element from the other, call it Y. First, use a shufps to build an
6073 // intermediate vector with the one element from Y and the element from X
6074 // that will be in the same half in the final destination (the indexes don't
6075 // matter). Then, use a shufps to build the final vector, taking the half
6076 // containing the element from Y from the intermediate, and the other half
6079 // Normalize it so the 3 elements come from V1.
6080 CommuteVectorShuffleMask(PermMask, 4);
6084 // Find the element from V2.
6086 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6087 int Val = PermMask[HiIndex];
6094 Mask1[0] = PermMask[HiIndex];
6096 Mask1[2] = PermMask[HiIndex^1];
6098 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6101 Mask1[0] = PermMask[0];
6102 Mask1[1] = PermMask[1];
6103 Mask1[2] = HiIndex & 1 ? 6 : 4;
6104 Mask1[3] = HiIndex & 1 ? 4 : 6;
6105 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6107 Mask1[0] = HiIndex & 1 ? 2 : 0;
6108 Mask1[1] = HiIndex & 1 ? 0 : 2;
6109 Mask1[2] = PermMask[2];
6110 Mask1[3] = PermMask[3];
6115 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6119 // Break it into (shuffle shuffle_hi, shuffle_lo).
6120 int LoMask[] = { -1, -1, -1, -1 };
6121 int HiMask[] = { -1, -1, -1, -1 };
6123 int *MaskPtr = LoMask;
6124 unsigned MaskIdx = 0;
6127 for (unsigned i = 0; i != 4; ++i) {
6134 int Idx = PermMask[i];
6136 Locs[i] = std::make_pair(-1, -1);
6137 } else if (Idx < 4) {
6138 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6139 MaskPtr[LoIdx] = Idx;
6142 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6143 MaskPtr[HiIdx] = Idx;
6148 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6149 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6150 int MaskOps[] = { -1, -1, -1, -1 };
6151 for (unsigned i = 0; i != 4; ++i)
6152 if (Locs[i].first != -1)
6153 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6154 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6157 static bool MayFoldVectorLoad(SDValue V) {
6158 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6159 V = V.getOperand(0);
6160 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6161 V = V.getOperand(0);
6162 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6163 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6164 // BUILD_VECTOR (load), undef
6165 V = V.getOperand(0);
6171 // FIXME: the version above should always be used. Since there's
6172 // a bug where several vector shuffles can't be folded because the
6173 // DAG is not updated during lowering and a node claims to have two
6174 // uses while it only has one, use this version, and let isel match
6175 // another instruction if the load really happens to have more than
6176 // one use. Remove this version after this bug get fixed.
6177 // rdar://8434668, PR8156
6178 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6179 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6180 V = V.getOperand(0);
6181 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6182 V = V.getOperand(0);
6183 if (ISD::isNormalLoad(V.getNode()))
6188 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6189 /// a vector extract, and if both can be later optimized into a single load.
6190 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6191 /// here because otherwise a target specific shuffle node is going to be
6192 /// emitted for this shuffle, and the optimization not done.
6193 /// FIXME: This is probably not the best approach, but fix the problem
6194 /// until the right path is decided.
6196 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6197 const TargetLowering &TLI) {
6198 EVT VT = V.getValueType();
6199 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6201 // Be sure that the vector shuffle is present in a pattern like this:
6202 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6206 SDNode *N = *V.getNode()->use_begin();
6207 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6210 SDValue EltNo = N->getOperand(1);
6211 if (!isa<ConstantSDNode>(EltNo))
6214 // If the bit convert changed the number of elements, it is unsafe
6215 // to examine the mask.
6216 bool HasShuffleIntoBitcast = false;
6217 if (V.getOpcode() == ISD::BITCAST) {
6218 EVT SrcVT = V.getOperand(0).getValueType();
6219 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6221 V = V.getOperand(0);
6222 HasShuffleIntoBitcast = true;
6225 // Select the input vector, guarding against out of range extract vector.
6226 unsigned NumElems = VT.getVectorNumElements();
6227 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6228 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6229 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6231 // If we are accessing the upper part of a YMM register
6232 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6233 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6234 // because the legalization of N did not happen yet.
6235 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6238 // Skip one more bit_convert if necessary
6239 if (V.getOpcode() == ISD::BITCAST)
6240 V = V.getOperand(0);
6242 if (!ISD::isNormalLoad(V.getNode()))
6245 // Is the original load suitable?
6246 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6248 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6251 if (!HasShuffleIntoBitcast)
6254 // If there's a bitcast before the shuffle, check if the load type and
6255 // alignment is valid.
6256 unsigned Align = LN0->getAlignment();
6258 TLI.getTargetData()->getABITypeAlignment(
6259 VT.getTypeForEVT(*DAG.getContext()));
6261 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6268 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6269 EVT VT = Op.getValueType();
6271 // Canonizalize to v2f64.
6272 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6273 return DAG.getNode(ISD::BITCAST, dl, VT,
6274 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6279 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6281 SDValue V1 = Op.getOperand(0);
6282 SDValue V2 = Op.getOperand(1);
6283 EVT VT = Op.getValueType();
6285 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6287 if (HasSSE2 && VT == MVT::v2f64)
6288 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6290 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6291 return DAG.getNode(ISD::BITCAST, dl, VT,
6292 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6293 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6294 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6298 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6299 SDValue V1 = Op.getOperand(0);
6300 SDValue V2 = Op.getOperand(1);
6301 EVT VT = Op.getValueType();
6303 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6304 "unsupported shuffle type");
6306 if (V2.getOpcode() == ISD::UNDEF)
6310 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6314 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6315 SDValue V1 = Op.getOperand(0);
6316 SDValue V2 = Op.getOperand(1);
6317 EVT VT = Op.getValueType();
6318 unsigned NumElems = VT.getVectorNumElements();
6320 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6321 // operand of these instructions is only memory, so check if there's a
6322 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6324 bool CanFoldLoad = false;
6326 // Trivial case, when V2 comes from a load.
6327 if (MayFoldVectorLoad(V2))
6330 // When V1 is a load, it can be folded later into a store in isel, example:
6331 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6333 // (MOVLPSmr addr:$src1, VR128:$src2)
6334 // So, recognize this potential and also use MOVLPS or MOVLPD
6335 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6338 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6340 if (HasSSE2 && NumElems == 2)
6341 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6344 // If we don't care about the second element, procede to use movss.
6345 if (SVOp->getMaskElt(1) != -1)
6346 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6349 // movl and movlp will both match v2i64, but v2i64 is never matched by
6350 // movl earlier because we make it strict to avoid messing with the movlp load
6351 // folding logic (see the code above getMOVLP call). Match it here then,
6352 // this is horrible, but will stay like this until we move all shuffle
6353 // matching to x86 specific nodes. Note that for the 1st condition all
6354 // types are matched with movsd.
6356 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6357 // as to remove this logic from here, as much as possible
6358 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6359 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6360 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6363 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6365 // Invert the operand order and use SHUFPS to match it.
6366 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6367 X86::getShuffleSHUFImmediate(SVOp), DAG);
6371 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6372 const TargetLowering &TLI,
6373 const X86Subtarget *Subtarget) {
6374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6375 EVT VT = Op.getValueType();
6376 DebugLoc dl = Op.getDebugLoc();
6377 SDValue V1 = Op.getOperand(0);
6378 SDValue V2 = Op.getOperand(1);
6380 if (isZeroShuffle(SVOp))
6381 return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
6384 // Handle splat operations
6385 if (SVOp->isSplat()) {
6386 unsigned NumElem = VT.getVectorNumElements();
6387 int Size = VT.getSizeInBits();
6388 // Special case, this is the only place now where it's allowed to return
6389 // a vector_shuffle operation without using a target specific node, because
6390 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6391 // this be moved to DAGCombine instead?
6392 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6395 // Use vbroadcast whenever the splat comes from a foldable load
6396 SDValue LD = isVectorBroadcast(Op, Subtarget);
6398 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6400 // Handle splats by matching through known shuffle masks
6401 if ((Size == 128 && NumElem <= 4) ||
6402 (Size == 256 && NumElem < 8))
6405 // All remaning splats are promoted to target supported vector shuffles.
6406 return PromoteSplat(SVOp, DAG);
6409 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6411 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6412 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6413 if (NewOp.getNode())
6414 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6415 } else if ((VT == MVT::v4i32 ||
6416 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6417 // FIXME: Figure out a cleaner way to do this.
6418 // Try to make use of movq to zero out the top part.
6419 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6420 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6421 if (NewOp.getNode()) {
6422 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6423 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6424 DAG, Subtarget, dl);
6426 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6427 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6428 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6429 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6430 DAG, Subtarget, dl);
6437 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6438 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6439 SDValue V1 = Op.getOperand(0);
6440 SDValue V2 = Op.getOperand(1);
6441 EVT VT = Op.getValueType();
6442 DebugLoc dl = Op.getDebugLoc();
6443 unsigned NumElems = VT.getVectorNumElements();
6444 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6445 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6446 bool V1IsSplat = false;
6447 bool V2IsSplat = false;
6448 bool HasSSE2 = Subtarget->hasSSE2();
6449 bool HasAVX = Subtarget->hasAVX();
6450 bool HasAVX2 = Subtarget->hasAVX2();
6451 MachineFunction &MF = DAG.getMachineFunction();
6452 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6454 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6456 if (V1IsUndef && V2IsUndef)
6457 return DAG.getUNDEF(VT);
6459 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6461 // Vector shuffle lowering takes 3 steps:
6463 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6464 // narrowing and commutation of operands should be handled.
6465 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6467 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6468 // so the shuffle can be broken into other shuffles and the legalizer can
6469 // try the lowering again.
6471 // The general idea is that no vector_shuffle operation should be left to
6472 // be matched during isel, all of them must be converted to a target specific
6475 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6476 // narrowing and commutation of operands should be handled. The actual code
6477 // doesn't include all of those, work in progress...
6478 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6479 if (NewOp.getNode())
6482 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6483 // unpckh_undef). Only use pshufd if speed is more important than size.
6484 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6485 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6486 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6487 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6489 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() &&
6490 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6491 return getMOVDDup(Op, dl, V1, DAG);
6493 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6494 return getMOVHighToLow(Op, dl, DAG);
6496 // Use to match splats
6497 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6498 (VT == MVT::v2f64 || VT == MVT::v2i64))
6499 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6501 if (X86::isPSHUFDMask(SVOp)) {
6502 // The actual implementation will match the mask in the if above and then
6503 // during isel it can match several different instructions, not only pshufd
6504 // as its name says, sad but true, emulate the behavior for now...
6505 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6506 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6508 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6510 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6511 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6513 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6517 // Check if this can be converted into a logical shift.
6518 bool isLeft = false;
6521 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6522 if (isShift && ShVal.hasOneUse()) {
6523 // If the shifted value has multiple uses, it may be cheaper to use
6524 // v_set0 + movlhps or movhlps, etc.
6525 EVT EltVT = VT.getVectorElementType();
6526 ShAmt *= EltVT.getSizeInBits();
6527 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6530 if (X86::isMOVLMask(SVOp)) {
6531 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6532 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6533 if (!X86::isMOVLPMask(SVOp)) {
6534 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6535 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6537 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6538 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6542 // FIXME: fold these into legal mask.
6543 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6544 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6546 if (X86::isMOVHLPSMask(SVOp))
6547 return getMOVHighToLow(Op, dl, DAG);
6549 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6550 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6552 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6553 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6555 if (X86::isMOVLPMask(SVOp))
6556 return getMOVLP(Op, dl, DAG, HasSSE2);
6558 if (ShouldXformToMOVHLPS(SVOp) ||
6559 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6560 return CommuteVectorShuffle(SVOp, DAG);
6563 // No better options. Use a vshldq / vsrldq.
6564 EVT EltVT = VT.getVectorElementType();
6565 ShAmt *= EltVT.getSizeInBits();
6566 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6569 bool Commuted = false;
6570 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6571 // 1,1,1,1 -> v8i16 though.
6572 V1IsSplat = isSplatVector(V1.getNode());
6573 V2IsSplat = isSplatVector(V2.getNode());
6575 // Canonicalize the splat or undef, if present, to be on the RHS.
6576 if (V1IsSplat && !V2IsSplat) {
6577 Op = CommuteVectorShuffle(SVOp, DAG);
6578 SVOp = cast<ShuffleVectorSDNode>(Op);
6579 V1 = SVOp->getOperand(0);
6580 V2 = SVOp->getOperand(1);
6581 std::swap(V1IsSplat, V2IsSplat);
6585 ArrayRef<int> M = SVOp->getMask();
6587 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6588 // Shuffling low element of v1 into undef, just return v1.
6591 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6592 // the instruction selector will not match, so get a canonical MOVL with
6593 // swapped operands to undo the commute.
6594 return getMOVL(DAG, dl, VT, V2, V1);
6597 if (isUNPCKLMask(M, VT, HasAVX2))
6598 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6600 if (isUNPCKHMask(M, VT, HasAVX2))
6601 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6604 // Normalize mask so all entries that point to V2 points to its first
6605 // element then try to match unpck{h|l} again. If match, return a
6606 // new vector_shuffle with the corrected mask.
6607 SDValue NewMask = NormalizeMask(SVOp, DAG);
6608 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6609 if (NSVOp != SVOp) {
6610 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6612 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6619 // Commute is back and try unpck* again.
6620 // FIXME: this seems wrong.
6621 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6622 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6624 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6625 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6627 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6628 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6631 // Normalize the node to match x86 shuffle ops if needed
6632 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6633 return CommuteVectorShuffle(SVOp, DAG);
6635 // The checks below are all present in isShuffleMaskLegal, but they are
6636 // inlined here right now to enable us to directly emit target specific
6637 // nodes, and remove one by one until they don't return Op anymore.
6639 if (isPALIGNRMask(M, VT, Subtarget))
6640 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6641 getShufflePALIGNRImmediate(SVOp),
6644 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6645 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6646 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6647 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6650 if (isPSHUFHWMask(M, VT))
6651 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6652 X86::getShufflePSHUFHWImmediate(SVOp),
6655 if (isPSHUFLWMask(M, VT))
6656 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6657 X86::getShufflePSHUFLWImmediate(SVOp),
6660 if (isSHUFPMask(M, VT, HasAVX))
6661 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6662 X86::getShuffleSHUFImmediate(SVOp), DAG);
6664 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6665 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6666 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6667 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6669 //===--------------------------------------------------------------------===//
6670 // Generate target specific nodes for 128 or 256-bit shuffles only
6671 // supported in the AVX instruction set.
6674 // Handle VMOVDDUPY permutations
6675 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6676 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6678 // Handle VPERMILPS/D* permutations
6679 if (isVPERMILPMask(M, VT, HasAVX))
6680 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6681 getShuffleVPERMILPImmediate(SVOp), DAG);
6683 // Handle VPERM2F128/VPERM2I128 permutations
6684 if (isVPERM2X128Mask(M, VT, HasAVX))
6685 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6686 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6688 //===--------------------------------------------------------------------===//
6689 // Since no target specific shuffle was selected for this generic one,
6690 // lower it into other known shuffles. FIXME: this isn't true yet, but
6691 // this is the plan.
6694 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6695 if (VT == MVT::v8i16) {
6696 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6697 if (NewOp.getNode())
6701 if (VT == MVT::v16i8) {
6702 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6703 if (NewOp.getNode())
6707 // Handle all 128-bit wide vectors with 4 elements, and match them with
6708 // several different shuffle types.
6709 if (NumElems == 4 && VT.getSizeInBits() == 128)
6710 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6712 // Handle general 256-bit shuffles
6713 if (VT.is256BitVector())
6714 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6720 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6721 SelectionDAG &DAG) const {
6722 EVT VT = Op.getValueType();
6723 DebugLoc dl = Op.getDebugLoc();
6725 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6728 if (VT.getSizeInBits() == 8) {
6729 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6730 Op.getOperand(0), Op.getOperand(1));
6731 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6732 DAG.getValueType(VT));
6733 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6734 } else if (VT.getSizeInBits() == 16) {
6735 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6736 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6738 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6739 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6740 DAG.getNode(ISD::BITCAST, dl,
6744 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6745 Op.getOperand(0), Op.getOperand(1));
6746 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6747 DAG.getValueType(VT));
6748 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6749 } else if (VT == MVT::f32) {
6750 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6751 // the result back to FR32 register. It's only worth matching if the
6752 // result has a single use which is a store or a bitcast to i32. And in
6753 // the case of a store, it's not worth it if the index is a constant 0,
6754 // because a MOVSSmr can be used instead, which is smaller and faster.
6755 if (!Op.hasOneUse())
6757 SDNode *User = *Op.getNode()->use_begin();
6758 if ((User->getOpcode() != ISD::STORE ||
6759 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6760 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6761 (User->getOpcode() != ISD::BITCAST ||
6762 User->getValueType(0) != MVT::i32))
6764 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6765 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6768 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6769 } else if (VT == MVT::i32 || VT == MVT::i64) {
6770 // ExtractPS/pextrq works with constant index.
6771 if (isa<ConstantSDNode>(Op.getOperand(1)))
6779 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6780 SelectionDAG &DAG) const {
6781 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6784 SDValue Vec = Op.getOperand(0);
6785 EVT VecVT = Vec.getValueType();
6787 // If this is a 256-bit vector result, first extract the 128-bit vector and
6788 // then extract the element from the 128-bit vector.
6789 if (VecVT.getSizeInBits() == 256) {
6790 DebugLoc dl = Op.getNode()->getDebugLoc();
6791 unsigned NumElems = VecVT.getVectorNumElements();
6792 SDValue Idx = Op.getOperand(1);
6793 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6795 // Get the 128-bit vector.
6796 bool Upper = IdxVal >= NumElems/2;
6797 Vec = Extract128BitVector(Vec,
6798 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6800 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6801 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6804 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6806 if (Subtarget->hasSSE41()) {
6807 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6812 EVT VT = Op.getValueType();
6813 DebugLoc dl = Op.getDebugLoc();
6814 // TODO: handle v16i8.
6815 if (VT.getSizeInBits() == 16) {
6816 SDValue Vec = Op.getOperand(0);
6817 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6819 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6820 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6821 DAG.getNode(ISD::BITCAST, dl,
6824 // Transform it so it match pextrw which produces a 32-bit result.
6825 EVT EltVT = MVT::i32;
6826 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6827 Op.getOperand(0), Op.getOperand(1));
6828 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6829 DAG.getValueType(VT));
6830 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6831 } else if (VT.getSizeInBits() == 32) {
6832 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6836 // SHUFPS the element to the lowest double word, then movss.
6837 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6838 EVT VVT = Op.getOperand(0).getValueType();
6839 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6840 DAG.getUNDEF(VVT), Mask);
6841 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6842 DAG.getIntPtrConstant(0));
6843 } else if (VT.getSizeInBits() == 64) {
6844 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6845 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6846 // to match extract_elt for f64.
6847 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6851 // UNPCKHPD the element to the lowest double word, then movsd.
6852 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6853 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6854 int Mask[2] = { 1, -1 };
6855 EVT VVT = Op.getOperand(0).getValueType();
6856 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6857 DAG.getUNDEF(VVT), Mask);
6858 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6859 DAG.getIntPtrConstant(0));
6866 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6867 SelectionDAG &DAG) const {
6868 EVT VT = Op.getValueType();
6869 EVT EltVT = VT.getVectorElementType();
6870 DebugLoc dl = Op.getDebugLoc();
6872 SDValue N0 = Op.getOperand(0);
6873 SDValue N1 = Op.getOperand(1);
6874 SDValue N2 = Op.getOperand(2);
6876 if (VT.getSizeInBits() == 256)
6879 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6880 isa<ConstantSDNode>(N2)) {
6882 if (VT == MVT::v8i16)
6883 Opc = X86ISD::PINSRW;
6884 else if (VT == MVT::v16i8)
6885 Opc = X86ISD::PINSRB;
6887 Opc = X86ISD::PINSRB;
6889 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6891 if (N1.getValueType() != MVT::i32)
6892 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6893 if (N2.getValueType() != MVT::i32)
6894 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6895 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6896 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6897 // Bits [7:6] of the constant are the source select. This will always be
6898 // zero here. The DAG Combiner may combine an extract_elt index into these
6899 // bits. For example (insert (extract, 3), 2) could be matched by putting
6900 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6901 // Bits [5:4] of the constant are the destination select. This is the
6902 // value of the incoming immediate.
6903 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6904 // combine either bitwise AND or insert of float 0.0 to set these bits.
6905 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6906 // Create this as a scalar to vector..
6907 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6908 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6909 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6910 isa<ConstantSDNode>(N2)) {
6911 // PINSR* works with constant index.
6918 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6919 EVT VT = Op.getValueType();
6920 EVT EltVT = VT.getVectorElementType();
6922 DebugLoc dl = Op.getDebugLoc();
6923 SDValue N0 = Op.getOperand(0);
6924 SDValue N1 = Op.getOperand(1);
6925 SDValue N2 = Op.getOperand(2);
6927 // If this is a 256-bit vector result, first extract the 128-bit vector,
6928 // insert the element into the extracted half and then place it back.
6929 if (VT.getSizeInBits() == 256) {
6930 if (!isa<ConstantSDNode>(N2))
6933 // Get the desired 128-bit vector half.
6934 unsigned NumElems = VT.getVectorNumElements();
6935 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6936 bool Upper = IdxVal >= NumElems/2;
6937 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6938 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6940 // Insert the element into the desired half.
6941 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6942 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6944 // Insert the changed part back to the 256-bit vector
6945 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6948 if (Subtarget->hasSSE41())
6949 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6951 if (EltVT == MVT::i8)
6954 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6955 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6956 // as its second argument.
6957 if (N1.getValueType() != MVT::i32)
6958 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6959 if (N2.getValueType() != MVT::i32)
6960 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6961 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6967 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6968 LLVMContext *Context = DAG.getContext();
6969 DebugLoc dl = Op.getDebugLoc();
6970 EVT OpVT = Op.getValueType();
6972 // If this is a 256-bit vector result, first insert into a 128-bit
6973 // vector and then insert into the 256-bit vector.
6974 if (OpVT.getSizeInBits() > 128) {
6975 // Insert into a 128-bit vector.
6976 EVT VT128 = EVT::getVectorVT(*Context,
6977 OpVT.getVectorElementType(),
6978 OpVT.getVectorNumElements() / 2);
6980 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6982 // Insert the 128-bit vector.
6983 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6984 DAG.getConstant(0, MVT::i32),
6988 if (Op.getValueType() == MVT::v1i64 &&
6989 Op.getOperand(0).getValueType() == MVT::i64)
6990 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6992 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6993 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6994 "Expected an SSE type!");
6995 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6996 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6999 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7000 // a simple subregister reference or explicit instructions to grab
7001 // upper bits of a vector.
7003 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7004 if (Subtarget->hasAVX()) {
7005 DebugLoc dl = Op.getNode()->getDebugLoc();
7006 SDValue Vec = Op.getNode()->getOperand(0);
7007 SDValue Idx = Op.getNode()->getOperand(1);
7009 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7010 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7011 return Extract128BitVector(Vec, Idx, DAG, dl);
7017 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7018 // simple superregister reference or explicit instructions to insert
7019 // the upper bits of a vector.
7021 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7022 if (Subtarget->hasAVX()) {
7023 DebugLoc dl = Op.getNode()->getDebugLoc();
7024 SDValue Vec = Op.getNode()->getOperand(0);
7025 SDValue SubVec = Op.getNode()->getOperand(1);
7026 SDValue Idx = Op.getNode()->getOperand(2);
7028 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7029 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7030 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7036 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7037 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7038 // one of the above mentioned nodes. It has to be wrapped because otherwise
7039 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7040 // be used to form addressing mode. These wrapped nodes will be selected
7043 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7044 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7046 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7048 unsigned char OpFlag = 0;
7049 unsigned WrapperKind = X86ISD::Wrapper;
7050 CodeModel::Model M = getTargetMachine().getCodeModel();
7052 if (Subtarget->isPICStyleRIPRel() &&
7053 (M == CodeModel::Small || M == CodeModel::Kernel))
7054 WrapperKind = X86ISD::WrapperRIP;
7055 else if (Subtarget->isPICStyleGOT())
7056 OpFlag = X86II::MO_GOTOFF;
7057 else if (Subtarget->isPICStyleStubPIC())
7058 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7060 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7062 CP->getOffset(), OpFlag);
7063 DebugLoc DL = CP->getDebugLoc();
7064 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7065 // With PIC, the address is actually $g + Offset.
7067 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7068 DAG.getNode(X86ISD::GlobalBaseReg,
7069 DebugLoc(), getPointerTy()),
7076 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7077 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7079 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7081 unsigned char OpFlag = 0;
7082 unsigned WrapperKind = X86ISD::Wrapper;
7083 CodeModel::Model M = getTargetMachine().getCodeModel();
7085 if (Subtarget->isPICStyleRIPRel() &&
7086 (M == CodeModel::Small || M == CodeModel::Kernel))
7087 WrapperKind = X86ISD::WrapperRIP;
7088 else if (Subtarget->isPICStyleGOT())
7089 OpFlag = X86II::MO_GOTOFF;
7090 else if (Subtarget->isPICStyleStubPIC())
7091 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7093 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7095 DebugLoc DL = JT->getDebugLoc();
7096 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7098 // With PIC, the address is actually $g + Offset.
7100 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7101 DAG.getNode(X86ISD::GlobalBaseReg,
7102 DebugLoc(), getPointerTy()),
7109 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7110 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7112 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7114 unsigned char OpFlag = 0;
7115 unsigned WrapperKind = X86ISD::Wrapper;
7116 CodeModel::Model M = getTargetMachine().getCodeModel();
7118 if (Subtarget->isPICStyleRIPRel() &&
7119 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7120 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7121 OpFlag = X86II::MO_GOTPCREL;
7122 WrapperKind = X86ISD::WrapperRIP;
7123 } else if (Subtarget->isPICStyleGOT()) {
7124 OpFlag = X86II::MO_GOT;
7125 } else if (Subtarget->isPICStyleStubPIC()) {
7126 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7127 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7128 OpFlag = X86II::MO_DARWIN_NONLAZY;
7131 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7133 DebugLoc DL = Op.getDebugLoc();
7134 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7137 // With PIC, the address is actually $g + Offset.
7138 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7139 !Subtarget->is64Bit()) {
7140 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7141 DAG.getNode(X86ISD::GlobalBaseReg,
7142 DebugLoc(), getPointerTy()),
7146 // For symbols that require a load from a stub to get the address, emit the
7148 if (isGlobalStubReference(OpFlag))
7149 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7150 MachinePointerInfo::getGOT(), false, false, false, 0);
7156 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7157 // Create the TargetBlockAddressAddress node.
7158 unsigned char OpFlags =
7159 Subtarget->ClassifyBlockAddressReference();
7160 CodeModel::Model M = getTargetMachine().getCodeModel();
7161 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7162 DebugLoc dl = Op.getDebugLoc();
7163 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7164 /*isTarget=*/true, OpFlags);
7166 if (Subtarget->isPICStyleRIPRel() &&
7167 (M == CodeModel::Small || M == CodeModel::Kernel))
7168 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7170 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7172 // With PIC, the address is actually $g + Offset.
7173 if (isGlobalRelativeToPICBase(OpFlags)) {
7174 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7175 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7183 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7185 SelectionDAG &DAG) const {
7186 // Create the TargetGlobalAddress node, folding in the constant
7187 // offset if it is legal.
7188 unsigned char OpFlags =
7189 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7190 CodeModel::Model M = getTargetMachine().getCodeModel();
7192 if (OpFlags == X86II::MO_NO_FLAG &&
7193 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7194 // A direct static reference to a global.
7195 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7198 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7201 if (Subtarget->isPICStyleRIPRel() &&
7202 (M == CodeModel::Small || M == CodeModel::Kernel))
7203 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7205 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7207 // With PIC, the address is actually $g + Offset.
7208 if (isGlobalRelativeToPICBase(OpFlags)) {
7209 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7210 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7214 // For globals that require a load from a stub to get the address, emit the
7216 if (isGlobalStubReference(OpFlags))
7217 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7218 MachinePointerInfo::getGOT(), false, false, false, 0);
7220 // If there was a non-zero offset that we didn't fold, create an explicit
7223 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7224 DAG.getConstant(Offset, getPointerTy()));
7230 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7231 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7232 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7233 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7237 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7238 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7239 unsigned char OperandFlags) {
7240 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7241 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7242 DebugLoc dl = GA->getDebugLoc();
7243 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7244 GA->getValueType(0),
7248 SDValue Ops[] = { Chain, TGA, *InFlag };
7249 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7251 SDValue Ops[] = { Chain, TGA };
7252 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7255 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7256 MFI->setAdjustsStack(true);
7258 SDValue Flag = Chain.getValue(1);
7259 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7262 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7264 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7267 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7268 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7269 DAG.getNode(X86ISD::GlobalBaseReg,
7270 DebugLoc(), PtrVT), InFlag);
7271 InFlag = Chain.getValue(1);
7273 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7276 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7278 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7280 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7281 X86::RAX, X86II::MO_TLSGD);
7284 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7285 // "local exec" model.
7286 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7287 const EVT PtrVT, TLSModel::Model model,
7289 DebugLoc dl = GA->getDebugLoc();
7291 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7292 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7293 is64Bit ? 257 : 256));
7295 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7296 DAG.getIntPtrConstant(0),
7297 MachinePointerInfo(Ptr),
7298 false, false, false, 0);
7300 unsigned char OperandFlags = 0;
7301 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7303 unsigned WrapperKind = X86ISD::Wrapper;
7304 if (model == TLSModel::LocalExec) {
7305 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7306 } else if (is64Bit) {
7307 assert(model == TLSModel::InitialExec);
7308 OperandFlags = X86II::MO_GOTTPOFF;
7309 WrapperKind = X86ISD::WrapperRIP;
7311 assert(model == TLSModel::InitialExec);
7312 OperandFlags = X86II::MO_INDNTPOFF;
7315 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7317 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7318 GA->getValueType(0),
7319 GA->getOffset(), OperandFlags);
7320 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7322 if (model == TLSModel::InitialExec)
7323 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7324 MachinePointerInfo::getGOT(), false, false, false, 0);
7326 // The address of the thread local variable is the add of the thread
7327 // pointer with the offset of the variable.
7328 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7332 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7334 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7335 const GlobalValue *GV = GA->getGlobal();
7337 if (Subtarget->isTargetELF()) {
7338 // TODO: implement the "local dynamic" model
7339 // TODO: implement the "initial exec"model for pic executables
7341 // If GV is an alias then use the aliasee for determining
7342 // thread-localness.
7343 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7344 GV = GA->resolveAliasedGlobal(false);
7346 TLSModel::Model model
7347 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7350 case TLSModel::GeneralDynamic:
7351 case TLSModel::LocalDynamic: // not implemented
7352 if (Subtarget->is64Bit())
7353 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7354 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7356 case TLSModel::InitialExec:
7357 case TLSModel::LocalExec:
7358 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7359 Subtarget->is64Bit());
7361 } else if (Subtarget->isTargetDarwin()) {
7362 // Darwin only has one model of TLS. Lower to that.
7363 unsigned char OpFlag = 0;
7364 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7365 X86ISD::WrapperRIP : X86ISD::Wrapper;
7367 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7369 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7370 !Subtarget->is64Bit();
7372 OpFlag = X86II::MO_TLVP_PIC_BASE;
7374 OpFlag = X86II::MO_TLVP;
7375 DebugLoc DL = Op.getDebugLoc();
7376 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7377 GA->getValueType(0),
7378 GA->getOffset(), OpFlag);
7379 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7381 // With PIC32, the address is actually $g + Offset.
7383 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7384 DAG.getNode(X86ISD::GlobalBaseReg,
7385 DebugLoc(), getPointerTy()),
7388 // Lowering the machine isd will make sure everything is in the right
7390 SDValue Chain = DAG.getEntryNode();
7391 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7392 SDValue Args[] = { Chain, Offset };
7393 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7395 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7396 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7397 MFI->setAdjustsStack(true);
7399 // And our return value (tls address) is in the standard call return value
7401 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7402 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7406 llvm_unreachable("TLS not implemented for this target.");
7410 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7411 /// and take a 2 x i32 value to shift plus a shift amount.
7412 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7413 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7414 EVT VT = Op.getValueType();
7415 unsigned VTBits = VT.getSizeInBits();
7416 DebugLoc dl = Op.getDebugLoc();
7417 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7418 SDValue ShOpLo = Op.getOperand(0);
7419 SDValue ShOpHi = Op.getOperand(1);
7420 SDValue ShAmt = Op.getOperand(2);
7421 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7422 DAG.getConstant(VTBits - 1, MVT::i8))
7423 : DAG.getConstant(0, VT);
7426 if (Op.getOpcode() == ISD::SHL_PARTS) {
7427 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7428 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7430 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7431 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7434 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7435 DAG.getConstant(VTBits, MVT::i8));
7436 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7437 AndNode, DAG.getConstant(0, MVT::i8));
7440 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7441 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7442 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7444 if (Op.getOpcode() == ISD::SHL_PARTS) {
7445 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7446 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7448 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7449 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7452 SDValue Ops[2] = { Lo, Hi };
7453 return DAG.getMergeValues(Ops, 2, dl);
7456 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7457 SelectionDAG &DAG) const {
7458 EVT SrcVT = Op.getOperand(0).getValueType();
7460 if (SrcVT.isVector())
7463 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7464 "Unknown SINT_TO_FP to lower!");
7466 // These are really Legal; return the operand so the caller accepts it as
7468 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7470 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7471 Subtarget->is64Bit()) {
7475 DebugLoc dl = Op.getDebugLoc();
7476 unsigned Size = SrcVT.getSizeInBits()/8;
7477 MachineFunction &MF = DAG.getMachineFunction();
7478 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7479 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7480 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7482 MachinePointerInfo::getFixedStack(SSFI),
7484 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7487 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7489 SelectionDAG &DAG) const {
7491 DebugLoc DL = Op.getDebugLoc();
7493 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7495 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7497 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7499 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7501 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7502 MachineMemOperand *MMO;
7504 int SSFI = FI->getIndex();
7506 DAG.getMachineFunction()
7507 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7508 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7510 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7511 StackSlot = StackSlot.getOperand(1);
7513 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7514 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7516 Tys, Ops, array_lengthof(Ops),
7520 Chain = Result.getValue(1);
7521 SDValue InFlag = Result.getValue(2);
7523 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7524 // shouldn't be necessary except that RFP cannot be live across
7525 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7526 MachineFunction &MF = DAG.getMachineFunction();
7527 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7528 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7529 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7530 Tys = DAG.getVTList(MVT::Other);
7532 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7534 MachineMemOperand *MMO =
7535 DAG.getMachineFunction()
7536 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7537 MachineMemOperand::MOStore, SSFISize, SSFISize);
7539 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7540 Ops, array_lengthof(Ops),
7541 Op.getValueType(), MMO);
7542 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7543 MachinePointerInfo::getFixedStack(SSFI),
7544 false, false, false, 0);
7550 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7551 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7552 SelectionDAG &DAG) const {
7553 // This algorithm is not obvious. Here it is what we're trying to output:
7556 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7557 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7561 pshufd $0x4e, %xmm0, %xmm1
7566 DebugLoc dl = Op.getDebugLoc();
7567 LLVMContext *Context = DAG.getContext();
7569 // Build some magic constants.
7570 SmallVector<Constant*,4> CV0;
7571 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7572 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7573 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7574 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7575 Constant *C0 = ConstantVector::get(CV0);
7576 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7578 SmallVector<Constant*,2> CV1;
7580 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7582 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7583 Constant *C1 = ConstantVector::get(CV1);
7584 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7586 // Load the 64-bit value into an XMM register.
7587 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7589 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7590 MachinePointerInfo::getConstantPool(),
7591 false, false, false, 16);
7592 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7593 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7596 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7597 MachinePointerInfo::getConstantPool(),
7598 false, false, false, 16);
7599 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7600 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7603 if (Subtarget->hasSSE3()) {
7604 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7605 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7607 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7608 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7610 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7611 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7615 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7616 DAG.getIntPtrConstant(0));
7619 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7620 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7621 SelectionDAG &DAG) const {
7622 DebugLoc dl = Op.getDebugLoc();
7623 // FP constant to bias correct the final result.
7624 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7627 // Load the 32-bit value into an XMM register.
7628 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7631 // Zero out the upper parts of the register.
7632 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7634 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7635 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7636 DAG.getIntPtrConstant(0));
7638 // Or the load with the bias.
7639 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7640 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7641 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7643 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7644 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7645 MVT::v2f64, Bias)));
7646 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7647 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7648 DAG.getIntPtrConstant(0));
7650 // Subtract the bias.
7651 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7653 // Handle final rounding.
7654 EVT DestVT = Op.getValueType();
7656 if (DestVT.bitsLT(MVT::f64)) {
7657 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7658 DAG.getIntPtrConstant(0));
7659 } else if (DestVT.bitsGT(MVT::f64)) {
7660 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7663 // Handle final rounding.
7667 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7668 SelectionDAG &DAG) const {
7669 SDValue N0 = Op.getOperand(0);
7670 DebugLoc dl = Op.getDebugLoc();
7672 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7673 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7674 // the optimization here.
7675 if (DAG.SignBitIsZero(N0))
7676 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7678 EVT SrcVT = N0.getValueType();
7679 EVT DstVT = Op.getValueType();
7680 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7681 return LowerUINT_TO_FP_i64(Op, DAG);
7682 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7683 return LowerUINT_TO_FP_i32(Op, DAG);
7684 else if (Subtarget->is64Bit() &&
7685 SrcVT == MVT::i64 && DstVT == MVT::f32)
7688 // Make a 64-bit buffer, and use it to build an FILD.
7689 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7690 if (SrcVT == MVT::i32) {
7691 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7692 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7693 getPointerTy(), StackSlot, WordOff);
7694 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7695 StackSlot, MachinePointerInfo(),
7697 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7698 OffsetSlot, MachinePointerInfo(),
7700 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7704 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7705 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7706 StackSlot, MachinePointerInfo(),
7708 // For i64 source, we need to add the appropriate power of 2 if the input
7709 // was negative. This is the same as the optimization in
7710 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7711 // we must be careful to do the computation in x87 extended precision, not
7712 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7713 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7714 MachineMemOperand *MMO =
7715 DAG.getMachineFunction()
7716 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7717 MachineMemOperand::MOLoad, 8, 8);
7719 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7720 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7721 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7724 APInt FF(32, 0x5F800000ULL);
7726 // Check whether the sign bit is set.
7727 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7728 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7731 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7732 SDValue FudgePtr = DAG.getConstantPool(
7733 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7736 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7737 SDValue Zero = DAG.getIntPtrConstant(0);
7738 SDValue Four = DAG.getIntPtrConstant(4);
7739 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7741 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7743 // Load the value out, extending it from f32 to f80.
7744 // FIXME: Avoid the extend by constructing the right constant pool?
7745 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7746 FudgePtr, MachinePointerInfo::getConstantPool(),
7747 MVT::f32, false, false, 4);
7748 // Extend everything to 80 bits to force it to be done on x87.
7749 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7750 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7753 std::pair<SDValue,SDValue> X86TargetLowering::
7754 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7755 DebugLoc DL = Op.getDebugLoc();
7757 EVT DstTy = Op.getValueType();
7760 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7764 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7765 DstTy.getSimpleVT() >= MVT::i16 &&
7766 "Unknown FP_TO_SINT to lower!");
7768 // These are really Legal.
7769 if (DstTy == MVT::i32 &&
7770 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7771 return std::make_pair(SDValue(), SDValue());
7772 if (Subtarget->is64Bit() &&
7773 DstTy == MVT::i64 &&
7774 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7775 return std::make_pair(SDValue(), SDValue());
7777 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7779 MachineFunction &MF = DAG.getMachineFunction();
7780 unsigned MemSize = DstTy.getSizeInBits()/8;
7781 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7782 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7787 switch (DstTy.getSimpleVT().SimpleTy) {
7788 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7789 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7790 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7791 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7794 SDValue Chain = DAG.getEntryNode();
7795 SDValue Value = Op.getOperand(0);
7796 EVT TheVT = Op.getOperand(0).getValueType();
7797 if (isScalarFPTypeInSSEReg(TheVT)) {
7798 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7799 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7800 MachinePointerInfo::getFixedStack(SSFI),
7802 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7804 Chain, StackSlot, DAG.getValueType(TheVT)
7807 MachineMemOperand *MMO =
7808 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7809 MachineMemOperand::MOLoad, MemSize, MemSize);
7810 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7812 Chain = Value.getValue(1);
7813 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7814 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7817 MachineMemOperand *MMO =
7818 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7819 MachineMemOperand::MOStore, MemSize, MemSize);
7821 // Build the FP_TO_INT*_IN_MEM
7822 SDValue Ops[] = { Chain, Value, StackSlot };
7823 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7824 Ops, 3, DstTy, MMO);
7826 return std::make_pair(FIST, StackSlot);
7829 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7830 SelectionDAG &DAG) const {
7831 if (Op.getValueType().isVector())
7834 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7835 SDValue FIST = Vals.first, StackSlot = Vals.second;
7836 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7837 if (FIST.getNode() == 0) return Op;
7840 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7841 FIST, StackSlot, MachinePointerInfo(),
7842 false, false, false, 0);
7845 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7846 SelectionDAG &DAG) const {
7847 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7848 SDValue FIST = Vals.first, StackSlot = Vals.second;
7849 assert(FIST.getNode() && "Unexpected failure");
7852 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7853 FIST, StackSlot, MachinePointerInfo(),
7854 false, false, false, 0);
7857 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7858 SelectionDAG &DAG) const {
7859 LLVMContext *Context = DAG.getContext();
7860 DebugLoc dl = Op.getDebugLoc();
7861 EVT VT = Op.getValueType();
7864 EltVT = VT.getVectorElementType();
7866 if (EltVT == MVT::f64) {
7867 C = ConstantVector::getSplat(2,
7868 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7870 C = ConstantVector::getSplat(4,
7871 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7873 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7874 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7875 MachinePointerInfo::getConstantPool(),
7876 false, false, false, 16);
7877 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7880 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7881 LLVMContext *Context = DAG.getContext();
7882 DebugLoc dl = Op.getDebugLoc();
7883 EVT VT = Op.getValueType();
7885 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7886 if (VT.isVector()) {
7887 EltVT = VT.getVectorElementType();
7888 NumElts = VT.getVectorNumElements();
7891 if (EltVT == MVT::f64)
7892 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7894 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7895 C = ConstantVector::getSplat(NumElts, C);
7896 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7897 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7898 MachinePointerInfo::getConstantPool(),
7899 false, false, false, 16);
7900 if (VT.isVector()) {
7901 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7902 return DAG.getNode(ISD::BITCAST, dl, VT,
7903 DAG.getNode(ISD::XOR, dl, XORVT,
7904 DAG.getNode(ISD::BITCAST, dl, XORVT,
7906 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7908 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7912 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7913 LLVMContext *Context = DAG.getContext();
7914 SDValue Op0 = Op.getOperand(0);
7915 SDValue Op1 = Op.getOperand(1);
7916 DebugLoc dl = Op.getDebugLoc();
7917 EVT VT = Op.getValueType();
7918 EVT SrcVT = Op1.getValueType();
7920 // If second operand is smaller, extend it first.
7921 if (SrcVT.bitsLT(VT)) {
7922 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7925 // And if it is bigger, shrink it first.
7926 if (SrcVT.bitsGT(VT)) {
7927 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7931 // At this point the operands and the result should have the same
7932 // type, and that won't be f80 since that is not custom lowered.
7934 // First get the sign bit of second operand.
7935 SmallVector<Constant*,4> CV;
7936 if (SrcVT == MVT::f64) {
7937 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7938 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7940 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7941 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7942 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7943 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7945 Constant *C = ConstantVector::get(CV);
7946 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7947 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7948 MachinePointerInfo::getConstantPool(),
7949 false, false, false, 16);
7950 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7952 // Shift sign bit right or left if the two operands have different types.
7953 if (SrcVT.bitsGT(VT)) {
7954 // Op0 is MVT::f32, Op1 is MVT::f64.
7955 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7956 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7957 DAG.getConstant(32, MVT::i32));
7958 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7959 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7960 DAG.getIntPtrConstant(0));
7963 // Clear first operand sign bit.
7965 if (VT == MVT::f64) {
7966 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7967 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7969 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7970 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7971 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7972 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7974 C = ConstantVector::get(CV);
7975 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7976 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7977 MachinePointerInfo::getConstantPool(),
7978 false, false, false, 16);
7979 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7981 // Or the value with the sign bit.
7982 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7985 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7986 SDValue N0 = Op.getOperand(0);
7987 DebugLoc dl = Op.getDebugLoc();
7988 EVT VT = Op.getValueType();
7990 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7991 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7992 DAG.getConstant(1, VT));
7993 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7996 /// Emit nodes that will be selected as "test Op0,Op0", or something
7998 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7999 SelectionDAG &DAG) const {
8000 DebugLoc dl = Op.getDebugLoc();
8002 // CF and OF aren't always set the way we want. Determine which
8003 // of these we need.
8004 bool NeedCF = false;
8005 bool NeedOF = false;
8008 case X86::COND_A: case X86::COND_AE:
8009 case X86::COND_B: case X86::COND_BE:
8012 case X86::COND_G: case X86::COND_GE:
8013 case X86::COND_L: case X86::COND_LE:
8014 case X86::COND_O: case X86::COND_NO:
8019 // See if we can use the EFLAGS value from the operand instead of
8020 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8021 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8022 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8023 // Emit a CMP with 0, which is the TEST pattern.
8024 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8025 DAG.getConstant(0, Op.getValueType()));
8027 unsigned Opcode = 0;
8028 unsigned NumOperands = 0;
8029 switch (Op.getNode()->getOpcode()) {
8031 // Due to an isel shortcoming, be conservative if this add is likely to be
8032 // selected as part of a load-modify-store instruction. When the root node
8033 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8034 // uses of other nodes in the match, such as the ADD in this case. This
8035 // leads to the ADD being left around and reselected, with the result being
8036 // two adds in the output. Alas, even if none our users are stores, that
8037 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8038 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8039 // climbing the DAG back to the root, and it doesn't seem to be worth the
8041 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8042 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8043 if (UI->getOpcode() != ISD::CopyToReg &&
8044 UI->getOpcode() != ISD::SETCC &&
8045 UI->getOpcode() != ISD::STORE)
8048 if (ConstantSDNode *C =
8049 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8050 // An add of one will be selected as an INC.
8051 if (C->getAPIntValue() == 1) {
8052 Opcode = X86ISD::INC;
8057 // An add of negative one (subtract of one) will be selected as a DEC.
8058 if (C->getAPIntValue().isAllOnesValue()) {
8059 Opcode = X86ISD::DEC;
8065 // Otherwise use a regular EFLAGS-setting add.
8066 Opcode = X86ISD::ADD;
8070 // If the primary and result isn't used, don't bother using X86ISD::AND,
8071 // because a TEST instruction will be better.
8072 bool NonFlagUse = false;
8073 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8074 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8076 unsigned UOpNo = UI.getOperandNo();
8077 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8078 // Look pass truncate.
8079 UOpNo = User->use_begin().getOperandNo();
8080 User = *User->use_begin();
8083 if (User->getOpcode() != ISD::BRCOND &&
8084 User->getOpcode() != ISD::SETCC &&
8085 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8098 // Due to the ISEL shortcoming noted above, be conservative if this op is
8099 // likely to be selected as part of a load-modify-store instruction.
8100 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8101 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8102 if (UI->getOpcode() == ISD::STORE)
8105 // Otherwise use a regular EFLAGS-setting instruction.
8106 switch (Op.getNode()->getOpcode()) {
8107 default: llvm_unreachable("unexpected operator!");
8108 case ISD::SUB: Opcode = X86ISD::SUB; break;
8109 case ISD::OR: Opcode = X86ISD::OR; break;
8110 case ISD::XOR: Opcode = X86ISD::XOR; break;
8111 case ISD::AND: Opcode = X86ISD::AND; break;
8123 return SDValue(Op.getNode(), 1);
8130 // Emit a CMP with 0, which is the TEST pattern.
8131 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8132 DAG.getConstant(0, Op.getValueType()));
8134 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8135 SmallVector<SDValue, 4> Ops;
8136 for (unsigned i = 0; i != NumOperands; ++i)
8137 Ops.push_back(Op.getOperand(i));
8139 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8140 DAG.ReplaceAllUsesWith(Op, New);
8141 return SDValue(New.getNode(), 1);
8144 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8146 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8147 SelectionDAG &DAG) const {
8148 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8149 if (C->getAPIntValue() == 0)
8150 return EmitTest(Op0, X86CC, DAG);
8152 DebugLoc dl = Op0.getDebugLoc();
8153 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8156 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8157 /// if it's possible.
8158 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8159 DebugLoc dl, SelectionDAG &DAG) const {
8160 SDValue Op0 = And.getOperand(0);
8161 SDValue Op1 = And.getOperand(1);
8162 if (Op0.getOpcode() == ISD::TRUNCATE)
8163 Op0 = Op0.getOperand(0);
8164 if (Op1.getOpcode() == ISD::TRUNCATE)
8165 Op1 = Op1.getOperand(0);
8168 if (Op1.getOpcode() == ISD::SHL)
8169 std::swap(Op0, Op1);
8170 if (Op0.getOpcode() == ISD::SHL) {
8171 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8172 if (And00C->getZExtValue() == 1) {
8173 // If we looked past a truncate, check that it's only truncating away
8175 unsigned BitWidth = Op0.getValueSizeInBits();
8176 unsigned AndBitWidth = And.getValueSizeInBits();
8177 if (BitWidth > AndBitWidth) {
8178 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8179 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8180 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8184 RHS = Op0.getOperand(1);
8186 } else if (Op1.getOpcode() == ISD::Constant) {
8187 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8188 uint64_t AndRHSVal = AndRHS->getZExtValue();
8189 SDValue AndLHS = Op0;
8191 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8192 LHS = AndLHS.getOperand(0);
8193 RHS = AndLHS.getOperand(1);
8196 // Use BT if the immediate can't be encoded in a TEST instruction.
8197 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8199 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8203 if (LHS.getNode()) {
8204 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8205 // instruction. Since the shift amount is in-range-or-undefined, we know
8206 // that doing a bittest on the i32 value is ok. We extend to i32 because
8207 // the encoding for the i16 version is larger than the i32 version.
8208 // Also promote i16 to i32 for performance / code size reason.
8209 if (LHS.getValueType() == MVT::i8 ||
8210 LHS.getValueType() == MVT::i16)
8211 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8213 // If the operand types disagree, extend the shift amount to match. Since
8214 // BT ignores high bits (like shifts) we can use anyextend.
8215 if (LHS.getValueType() != RHS.getValueType())
8216 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8218 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8219 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8220 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8221 DAG.getConstant(Cond, MVT::i8), BT);
8227 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8229 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8231 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8232 SDValue Op0 = Op.getOperand(0);
8233 SDValue Op1 = Op.getOperand(1);
8234 DebugLoc dl = Op.getDebugLoc();
8235 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8237 // Optimize to BT if possible.
8238 // Lower (X & (1 << N)) == 0 to BT(X, N).
8239 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8240 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8241 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8242 Op1.getOpcode() == ISD::Constant &&
8243 cast<ConstantSDNode>(Op1)->isNullValue() &&
8244 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8245 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8246 if (NewSetCC.getNode())
8250 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8252 if (Op1.getOpcode() == ISD::Constant &&
8253 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8254 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8255 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8257 // If the input is a setcc, then reuse the input setcc or use a new one with
8258 // the inverted condition.
8259 if (Op0.getOpcode() == X86ISD::SETCC) {
8260 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8261 bool Invert = (CC == ISD::SETNE) ^
8262 cast<ConstantSDNode>(Op1)->isNullValue();
8263 if (!Invert) return Op0;
8265 CCode = X86::GetOppositeBranchCondition(CCode);
8266 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8267 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8271 bool isFP = Op1.getValueType().isFloatingPoint();
8272 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8273 if (X86CC == X86::COND_INVALID)
8276 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8277 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8278 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8281 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8282 // ones, and then concatenate the result back.
8283 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8284 EVT VT = Op.getValueType();
8286 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8287 "Unsupported value type for operation");
8289 int NumElems = VT.getVectorNumElements();
8290 DebugLoc dl = Op.getDebugLoc();
8291 SDValue CC = Op.getOperand(2);
8292 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8293 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8295 // Extract the LHS vectors
8296 SDValue LHS = Op.getOperand(0);
8297 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8298 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8300 // Extract the RHS vectors
8301 SDValue RHS = Op.getOperand(1);
8302 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8303 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8305 // Issue the operation on the smaller types and concatenate the result back
8306 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8307 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8308 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8309 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8310 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8314 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8316 SDValue Op0 = Op.getOperand(0);
8317 SDValue Op1 = Op.getOperand(1);
8318 SDValue CC = Op.getOperand(2);
8319 EVT VT = Op.getValueType();
8320 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8321 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8322 DebugLoc dl = Op.getDebugLoc();
8326 EVT EltVT = Op0.getValueType().getVectorElementType();
8327 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8331 // SSE Condition code mapping:
8340 switch (SetCCOpcode) {
8343 case ISD::SETEQ: SSECC = 0; break;
8345 case ISD::SETGT: Swap = true; // Fallthrough
8347 case ISD::SETOLT: SSECC = 1; break;
8349 case ISD::SETGE: Swap = true; // Fallthrough
8351 case ISD::SETOLE: SSECC = 2; break;
8352 case ISD::SETUO: SSECC = 3; break;
8354 case ISD::SETNE: SSECC = 4; break;
8355 case ISD::SETULE: Swap = true;
8356 case ISD::SETUGE: SSECC = 5; break;
8357 case ISD::SETULT: Swap = true;
8358 case ISD::SETUGT: SSECC = 6; break;
8359 case ISD::SETO: SSECC = 7; break;
8362 std::swap(Op0, Op1);
8364 // In the two special cases we can't handle, emit two comparisons.
8366 if (SetCCOpcode == ISD::SETUEQ) {
8368 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8369 DAG.getConstant(3, MVT::i8));
8370 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8371 DAG.getConstant(0, MVT::i8));
8372 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8373 } else if (SetCCOpcode == ISD::SETONE) {
8375 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8376 DAG.getConstant(7, MVT::i8));
8377 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8378 DAG.getConstant(4, MVT::i8));
8379 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8381 llvm_unreachable("Illegal FP comparison");
8383 // Handle all other FP comparisons here.
8384 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8385 DAG.getConstant(SSECC, MVT::i8));
8388 // Break 256-bit integer vector compare into smaller ones.
8389 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8390 return Lower256IntVSETCC(Op, DAG);
8392 // We are handling one of the integer comparisons here. Since SSE only has
8393 // GT and EQ comparisons for integer, swapping operands and multiple
8394 // operations may be required for some comparisons.
8396 bool Swap = false, Invert = false, FlipSigns = false;
8398 switch (SetCCOpcode) {
8400 case ISD::SETNE: Invert = true;
8401 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8402 case ISD::SETLT: Swap = true;
8403 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8404 case ISD::SETGE: Swap = true;
8405 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8406 case ISD::SETULT: Swap = true;
8407 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8408 case ISD::SETUGE: Swap = true;
8409 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8412 std::swap(Op0, Op1);
8414 // Check that the operation in question is available (most are plain SSE2,
8415 // but PCMPGTQ and PCMPEQQ have different requirements).
8416 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8418 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8421 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8422 // bits of the inputs before performing those operations.
8424 EVT EltVT = VT.getVectorElementType();
8425 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8427 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8428 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8430 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8431 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8434 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8436 // If the logical-not of the result is required, perform that now.
8438 Result = DAG.getNOT(dl, Result, VT);
8443 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8444 static bool isX86LogicalCmp(SDValue Op) {
8445 unsigned Opc = Op.getNode()->getOpcode();
8446 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8448 if (Op.getResNo() == 1 &&
8449 (Opc == X86ISD::ADD ||
8450 Opc == X86ISD::SUB ||
8451 Opc == X86ISD::ADC ||
8452 Opc == X86ISD::SBB ||
8453 Opc == X86ISD::SMUL ||
8454 Opc == X86ISD::UMUL ||
8455 Opc == X86ISD::INC ||
8456 Opc == X86ISD::DEC ||
8457 Opc == X86ISD::OR ||
8458 Opc == X86ISD::XOR ||
8459 Opc == X86ISD::AND))
8462 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8468 static bool isZero(SDValue V) {
8469 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8470 return C && C->isNullValue();
8473 static bool isAllOnes(SDValue V) {
8474 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8475 return C && C->isAllOnesValue();
8478 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8479 bool addTest = true;
8480 SDValue Cond = Op.getOperand(0);
8481 SDValue Op1 = Op.getOperand(1);
8482 SDValue Op2 = Op.getOperand(2);
8483 DebugLoc DL = Op.getDebugLoc();
8486 if (Cond.getOpcode() == ISD::SETCC) {
8487 SDValue NewCond = LowerSETCC(Cond, DAG);
8488 if (NewCond.getNode())
8492 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8493 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8494 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8495 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8496 if (Cond.getOpcode() == X86ISD::SETCC &&
8497 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8498 isZero(Cond.getOperand(1).getOperand(1))) {
8499 SDValue Cmp = Cond.getOperand(1);
8501 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8503 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8504 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8505 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8507 SDValue CmpOp0 = Cmp.getOperand(0);
8508 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8509 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8511 SDValue Res = // Res = 0 or -1.
8512 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8513 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8515 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8516 Res = DAG.getNOT(DL, Res, Res.getValueType());
8518 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8519 if (N2C == 0 || !N2C->isNullValue())
8520 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8525 // Look past (and (setcc_carry (cmp ...)), 1).
8526 if (Cond.getOpcode() == ISD::AND &&
8527 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8528 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8529 if (C && C->getAPIntValue() == 1)
8530 Cond = Cond.getOperand(0);
8533 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8534 // setting operand in place of the X86ISD::SETCC.
8535 unsigned CondOpcode = Cond.getOpcode();
8536 if (CondOpcode == X86ISD::SETCC ||
8537 CondOpcode == X86ISD::SETCC_CARRY) {
8538 CC = Cond.getOperand(0);
8540 SDValue Cmp = Cond.getOperand(1);
8541 unsigned Opc = Cmp.getOpcode();
8542 EVT VT = Op.getValueType();
8544 bool IllegalFPCMov = false;
8545 if (VT.isFloatingPoint() && !VT.isVector() &&
8546 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8547 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8549 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8550 Opc == X86ISD::BT) { // FIXME
8554 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8555 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8556 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8557 Cond.getOperand(0).getValueType() != MVT::i8)) {
8558 SDValue LHS = Cond.getOperand(0);
8559 SDValue RHS = Cond.getOperand(1);
8563 switch (CondOpcode) {
8564 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8565 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8566 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8567 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8568 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8569 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8570 default: llvm_unreachable("unexpected overflowing operator");
8572 if (CondOpcode == ISD::UMULO)
8573 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8576 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8578 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8580 if (CondOpcode == ISD::UMULO)
8581 Cond = X86Op.getValue(2);
8583 Cond = X86Op.getValue(1);
8585 CC = DAG.getConstant(X86Cond, MVT::i8);
8590 // Look pass the truncate.
8591 if (Cond.getOpcode() == ISD::TRUNCATE)
8592 Cond = Cond.getOperand(0);
8594 // We know the result of AND is compared against zero. Try to match
8596 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8597 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8598 if (NewSetCC.getNode()) {
8599 CC = NewSetCC.getOperand(0);
8600 Cond = NewSetCC.getOperand(1);
8607 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8608 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8611 // a < b ? -1 : 0 -> RES = ~setcc_carry
8612 // a < b ? 0 : -1 -> RES = setcc_carry
8613 // a >= b ? -1 : 0 -> RES = setcc_carry
8614 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8615 if (Cond.getOpcode() == X86ISD::CMP) {
8616 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8618 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8619 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8620 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8621 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8622 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8623 return DAG.getNOT(DL, Res, Res.getValueType());
8628 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8629 // condition is true.
8630 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8631 SDValue Ops[] = { Op2, Op1, CC, Cond };
8632 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8635 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8636 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8637 // from the AND / OR.
8638 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8639 Opc = Op.getOpcode();
8640 if (Opc != ISD::OR && Opc != ISD::AND)
8642 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8643 Op.getOperand(0).hasOneUse() &&
8644 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8645 Op.getOperand(1).hasOneUse());
8648 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8649 // 1 and that the SETCC node has a single use.
8650 static bool isXor1OfSetCC(SDValue Op) {
8651 if (Op.getOpcode() != ISD::XOR)
8653 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8654 if (N1C && N1C->getAPIntValue() == 1) {
8655 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8656 Op.getOperand(0).hasOneUse();
8661 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8662 bool addTest = true;
8663 SDValue Chain = Op.getOperand(0);
8664 SDValue Cond = Op.getOperand(1);
8665 SDValue Dest = Op.getOperand(2);
8666 DebugLoc dl = Op.getDebugLoc();
8668 bool Inverted = false;
8670 if (Cond.getOpcode() == ISD::SETCC) {
8671 // Check for setcc([su]{add,sub,mul}o == 0).
8672 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8673 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8674 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8675 Cond.getOperand(0).getResNo() == 1 &&
8676 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8677 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8678 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8679 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8680 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8681 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8683 Cond = Cond.getOperand(0);
8685 SDValue NewCond = LowerSETCC(Cond, DAG);
8686 if (NewCond.getNode())
8691 // FIXME: LowerXALUO doesn't handle these!!
8692 else if (Cond.getOpcode() == X86ISD::ADD ||
8693 Cond.getOpcode() == X86ISD::SUB ||
8694 Cond.getOpcode() == X86ISD::SMUL ||
8695 Cond.getOpcode() == X86ISD::UMUL)
8696 Cond = LowerXALUO(Cond, DAG);
8699 // Look pass (and (setcc_carry (cmp ...)), 1).
8700 if (Cond.getOpcode() == ISD::AND &&
8701 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8702 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8703 if (C && C->getAPIntValue() == 1)
8704 Cond = Cond.getOperand(0);
8707 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8708 // setting operand in place of the X86ISD::SETCC.
8709 unsigned CondOpcode = Cond.getOpcode();
8710 if (CondOpcode == X86ISD::SETCC ||
8711 CondOpcode == X86ISD::SETCC_CARRY) {
8712 CC = Cond.getOperand(0);
8714 SDValue Cmp = Cond.getOperand(1);
8715 unsigned Opc = Cmp.getOpcode();
8716 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8717 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8721 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8725 // These can only come from an arithmetic instruction with overflow,
8726 // e.g. SADDO, UADDO.
8727 Cond = Cond.getNode()->getOperand(1);
8733 CondOpcode = Cond.getOpcode();
8734 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8735 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8736 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8737 Cond.getOperand(0).getValueType() != MVT::i8)) {
8738 SDValue LHS = Cond.getOperand(0);
8739 SDValue RHS = Cond.getOperand(1);
8743 switch (CondOpcode) {
8744 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8745 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8746 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8747 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8748 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8749 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8750 default: llvm_unreachable("unexpected overflowing operator");
8753 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8754 if (CondOpcode == ISD::UMULO)
8755 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8758 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8760 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8762 if (CondOpcode == ISD::UMULO)
8763 Cond = X86Op.getValue(2);
8765 Cond = X86Op.getValue(1);
8767 CC = DAG.getConstant(X86Cond, MVT::i8);
8771 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8772 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8773 if (CondOpc == ISD::OR) {
8774 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8775 // two branches instead of an explicit OR instruction with a
8777 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8778 isX86LogicalCmp(Cmp)) {
8779 CC = Cond.getOperand(0).getOperand(0);
8780 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8781 Chain, Dest, CC, Cmp);
8782 CC = Cond.getOperand(1).getOperand(0);
8786 } else { // ISD::AND
8787 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8788 // two branches instead of an explicit AND instruction with a
8789 // separate test. However, we only do this if this block doesn't
8790 // have a fall-through edge, because this requires an explicit
8791 // jmp when the condition is false.
8792 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8793 isX86LogicalCmp(Cmp) &&
8794 Op.getNode()->hasOneUse()) {
8795 X86::CondCode CCode =
8796 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8797 CCode = X86::GetOppositeBranchCondition(CCode);
8798 CC = DAG.getConstant(CCode, MVT::i8);
8799 SDNode *User = *Op.getNode()->use_begin();
8800 // Look for an unconditional branch following this conditional branch.
8801 // We need this because we need to reverse the successors in order
8802 // to implement FCMP_OEQ.
8803 if (User->getOpcode() == ISD::BR) {
8804 SDValue FalseBB = User->getOperand(1);
8806 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8807 assert(NewBR == User);
8811 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8812 Chain, Dest, CC, Cmp);
8813 X86::CondCode CCode =
8814 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8815 CCode = X86::GetOppositeBranchCondition(CCode);
8816 CC = DAG.getConstant(CCode, MVT::i8);
8822 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8823 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8824 // It should be transformed during dag combiner except when the condition
8825 // is set by a arithmetics with overflow node.
8826 X86::CondCode CCode =
8827 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8828 CCode = X86::GetOppositeBranchCondition(CCode);
8829 CC = DAG.getConstant(CCode, MVT::i8);
8830 Cond = Cond.getOperand(0).getOperand(1);
8832 } else if (Cond.getOpcode() == ISD::SETCC &&
8833 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8834 // For FCMP_OEQ, we can emit
8835 // two branches instead of an explicit AND instruction with a
8836 // separate test. However, we only do this if this block doesn't
8837 // have a fall-through edge, because this requires an explicit
8838 // jmp when the condition is false.
8839 if (Op.getNode()->hasOneUse()) {
8840 SDNode *User = *Op.getNode()->use_begin();
8841 // Look for an unconditional branch following this conditional branch.
8842 // We need this because we need to reverse the successors in order
8843 // to implement FCMP_OEQ.
8844 if (User->getOpcode() == ISD::BR) {
8845 SDValue FalseBB = User->getOperand(1);
8847 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8848 assert(NewBR == User);
8852 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8853 Cond.getOperand(0), Cond.getOperand(1));
8854 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8855 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8856 Chain, Dest, CC, Cmp);
8857 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8862 } else if (Cond.getOpcode() == ISD::SETCC &&
8863 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8864 // For FCMP_UNE, we can emit
8865 // two branches instead of an explicit AND instruction with a
8866 // separate test. However, we only do this if this block doesn't
8867 // have a fall-through edge, because this requires an explicit
8868 // jmp when the condition is false.
8869 if (Op.getNode()->hasOneUse()) {
8870 SDNode *User = *Op.getNode()->use_begin();
8871 // Look for an unconditional branch following this conditional branch.
8872 // We need this because we need to reverse the successors in order
8873 // to implement FCMP_UNE.
8874 if (User->getOpcode() == ISD::BR) {
8875 SDValue FalseBB = User->getOperand(1);
8877 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8878 assert(NewBR == User);
8881 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8882 Cond.getOperand(0), Cond.getOperand(1));
8883 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8884 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8885 Chain, Dest, CC, Cmp);
8886 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8896 // Look pass the truncate.
8897 if (Cond.getOpcode() == ISD::TRUNCATE)
8898 Cond = Cond.getOperand(0);
8900 // We know the result of AND is compared against zero. Try to match
8902 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8903 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8904 if (NewSetCC.getNode()) {
8905 CC = NewSetCC.getOperand(0);
8906 Cond = NewSetCC.getOperand(1);
8913 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8914 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8916 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8917 Chain, Dest, CC, Cond);
8921 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8922 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8923 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8924 // that the guard pages used by the OS virtual memory manager are allocated in
8925 // correct sequence.
8927 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8928 SelectionDAG &DAG) const {
8929 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8930 getTargetMachine().Options.EnableSegmentedStacks) &&
8931 "This should be used only on Windows targets or when segmented stacks "
8933 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8934 DebugLoc dl = Op.getDebugLoc();
8937 SDValue Chain = Op.getOperand(0);
8938 SDValue Size = Op.getOperand(1);
8939 // FIXME: Ensure alignment here
8941 bool Is64Bit = Subtarget->is64Bit();
8942 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8944 if (getTargetMachine().Options.EnableSegmentedStacks) {
8945 MachineFunction &MF = DAG.getMachineFunction();
8946 MachineRegisterInfo &MRI = MF.getRegInfo();
8949 // The 64 bit implementation of segmented stacks needs to clobber both r10
8950 // r11. This makes it impossible to use it along with nested parameters.
8951 const Function *F = MF.getFunction();
8953 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8955 if (I->hasNestAttr())
8956 report_fatal_error("Cannot use segmented stacks with functions that "
8957 "have nested arguments.");
8960 const TargetRegisterClass *AddrRegClass =
8961 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8962 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8963 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8964 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8965 DAG.getRegister(Vreg, SPTy));
8966 SDValue Ops1[2] = { Value, Chain };
8967 return DAG.getMergeValues(Ops1, 2, dl);
8970 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8972 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8973 Flag = Chain.getValue(1);
8974 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8976 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8977 Flag = Chain.getValue(1);
8979 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8981 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8982 return DAG.getMergeValues(Ops1, 2, dl);
8986 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8987 MachineFunction &MF = DAG.getMachineFunction();
8988 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8990 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8991 DebugLoc DL = Op.getDebugLoc();
8993 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8994 // vastart just stores the address of the VarArgsFrameIndex slot into the
8995 // memory location argument.
8996 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8998 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8999 MachinePointerInfo(SV), false, false, 0);
9003 // gp_offset (0 - 6 * 8)
9004 // fp_offset (48 - 48 + 8 * 16)
9005 // overflow_arg_area (point to parameters coming in memory).
9007 SmallVector<SDValue, 8> MemOps;
9008 SDValue FIN = Op.getOperand(1);
9010 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9011 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9013 FIN, MachinePointerInfo(SV), false, false, 0);
9014 MemOps.push_back(Store);
9017 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9018 FIN, DAG.getIntPtrConstant(4));
9019 Store = DAG.getStore(Op.getOperand(0), DL,
9020 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9022 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9023 MemOps.push_back(Store);
9025 // Store ptr to overflow_arg_area
9026 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9027 FIN, DAG.getIntPtrConstant(4));
9028 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9030 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9031 MachinePointerInfo(SV, 8),
9033 MemOps.push_back(Store);
9035 // Store ptr to reg_save_area.
9036 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9037 FIN, DAG.getIntPtrConstant(8));
9038 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9040 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9041 MachinePointerInfo(SV, 16), false, false, 0);
9042 MemOps.push_back(Store);
9043 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9044 &MemOps[0], MemOps.size());
9047 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9048 assert(Subtarget->is64Bit() &&
9049 "LowerVAARG only handles 64-bit va_arg!");
9050 assert((Subtarget->isTargetLinux() ||
9051 Subtarget->isTargetDarwin()) &&
9052 "Unhandled target in LowerVAARG");
9053 assert(Op.getNode()->getNumOperands() == 4);
9054 SDValue Chain = Op.getOperand(0);
9055 SDValue SrcPtr = Op.getOperand(1);
9056 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9057 unsigned Align = Op.getConstantOperandVal(3);
9058 DebugLoc dl = Op.getDebugLoc();
9060 EVT ArgVT = Op.getNode()->getValueType(0);
9061 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9062 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9065 // Decide which area this value should be read from.
9066 // TODO: Implement the AMD64 ABI in its entirety. This simple
9067 // selection mechanism works only for the basic types.
9068 if (ArgVT == MVT::f80) {
9069 llvm_unreachable("va_arg for f80 not yet implemented");
9070 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9071 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9072 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9073 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9075 llvm_unreachable("Unhandled argument type in LowerVAARG");
9079 // Sanity Check: Make sure using fp_offset makes sense.
9080 assert(!getTargetMachine().Options.UseSoftFloat &&
9081 !(DAG.getMachineFunction()
9082 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9083 Subtarget->hasSSE1());
9086 // Insert VAARG_64 node into the DAG
9087 // VAARG_64 returns two values: Variable Argument Address, Chain
9088 SmallVector<SDValue, 11> InstOps;
9089 InstOps.push_back(Chain);
9090 InstOps.push_back(SrcPtr);
9091 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9092 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9093 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9094 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9095 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9096 VTs, &InstOps[0], InstOps.size(),
9098 MachinePointerInfo(SV),
9103 Chain = VAARG.getValue(1);
9105 // Load the next argument and return it
9106 return DAG.getLoad(ArgVT, dl,
9109 MachinePointerInfo(),
9110 false, false, false, 0);
9113 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9114 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9115 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9116 SDValue Chain = Op.getOperand(0);
9117 SDValue DstPtr = Op.getOperand(1);
9118 SDValue SrcPtr = Op.getOperand(2);
9119 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9120 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9121 DebugLoc DL = Op.getDebugLoc();
9123 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9124 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9126 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9129 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9130 // may or may not be a constant. Takes immediate version of shift as input.
9131 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9132 SDValue SrcOp, SDValue ShAmt,
9133 SelectionDAG &DAG) {
9134 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9136 if (isa<ConstantSDNode>(ShAmt)) {
9138 default: llvm_unreachable("Unknown target vector shift node");
9142 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9146 // Change opcode to non-immediate version
9148 default: llvm_unreachable("Unknown target vector shift node");
9149 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9150 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9151 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9154 // Need to build a vector containing shift amount
9155 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9158 ShOps[1] = DAG.getConstant(0, MVT::i32);
9159 ShOps[2] = DAG.getUNDEF(MVT::i32);
9160 ShOps[3] = DAG.getUNDEF(MVT::i32);
9161 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9162 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9163 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9167 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9168 DebugLoc dl = Op.getDebugLoc();
9169 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9171 default: return SDValue(); // Don't custom lower most intrinsics.
9172 // Comparison intrinsics.
9173 case Intrinsic::x86_sse_comieq_ss:
9174 case Intrinsic::x86_sse_comilt_ss:
9175 case Intrinsic::x86_sse_comile_ss:
9176 case Intrinsic::x86_sse_comigt_ss:
9177 case Intrinsic::x86_sse_comige_ss:
9178 case Intrinsic::x86_sse_comineq_ss:
9179 case Intrinsic::x86_sse_ucomieq_ss:
9180 case Intrinsic::x86_sse_ucomilt_ss:
9181 case Intrinsic::x86_sse_ucomile_ss:
9182 case Intrinsic::x86_sse_ucomigt_ss:
9183 case Intrinsic::x86_sse_ucomige_ss:
9184 case Intrinsic::x86_sse_ucomineq_ss:
9185 case Intrinsic::x86_sse2_comieq_sd:
9186 case Intrinsic::x86_sse2_comilt_sd:
9187 case Intrinsic::x86_sse2_comile_sd:
9188 case Intrinsic::x86_sse2_comigt_sd:
9189 case Intrinsic::x86_sse2_comige_sd:
9190 case Intrinsic::x86_sse2_comineq_sd:
9191 case Intrinsic::x86_sse2_ucomieq_sd:
9192 case Intrinsic::x86_sse2_ucomilt_sd:
9193 case Intrinsic::x86_sse2_ucomile_sd:
9194 case Intrinsic::x86_sse2_ucomigt_sd:
9195 case Intrinsic::x86_sse2_ucomige_sd:
9196 case Intrinsic::x86_sse2_ucomineq_sd: {
9198 ISD::CondCode CC = ISD::SETCC_INVALID;
9200 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9201 case Intrinsic::x86_sse_comieq_ss:
9202 case Intrinsic::x86_sse2_comieq_sd:
9206 case Intrinsic::x86_sse_comilt_ss:
9207 case Intrinsic::x86_sse2_comilt_sd:
9211 case Intrinsic::x86_sse_comile_ss:
9212 case Intrinsic::x86_sse2_comile_sd:
9216 case Intrinsic::x86_sse_comigt_ss:
9217 case Intrinsic::x86_sse2_comigt_sd:
9221 case Intrinsic::x86_sse_comige_ss:
9222 case Intrinsic::x86_sse2_comige_sd:
9226 case Intrinsic::x86_sse_comineq_ss:
9227 case Intrinsic::x86_sse2_comineq_sd:
9231 case Intrinsic::x86_sse_ucomieq_ss:
9232 case Intrinsic::x86_sse2_ucomieq_sd:
9233 Opc = X86ISD::UCOMI;
9236 case Intrinsic::x86_sse_ucomilt_ss:
9237 case Intrinsic::x86_sse2_ucomilt_sd:
9238 Opc = X86ISD::UCOMI;
9241 case Intrinsic::x86_sse_ucomile_ss:
9242 case Intrinsic::x86_sse2_ucomile_sd:
9243 Opc = X86ISD::UCOMI;
9246 case Intrinsic::x86_sse_ucomigt_ss:
9247 case Intrinsic::x86_sse2_ucomigt_sd:
9248 Opc = X86ISD::UCOMI;
9251 case Intrinsic::x86_sse_ucomige_ss:
9252 case Intrinsic::x86_sse2_ucomige_sd:
9253 Opc = X86ISD::UCOMI;
9256 case Intrinsic::x86_sse_ucomineq_ss:
9257 case Intrinsic::x86_sse2_ucomineq_sd:
9258 Opc = X86ISD::UCOMI;
9263 SDValue LHS = Op.getOperand(1);
9264 SDValue RHS = Op.getOperand(2);
9265 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9266 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9267 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9268 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9269 DAG.getConstant(X86CC, MVT::i8), Cond);
9270 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9272 // XOP comparison intrinsics
9273 case Intrinsic::x86_xop_vpcomltb:
9274 case Intrinsic::x86_xop_vpcomltw:
9275 case Intrinsic::x86_xop_vpcomltd:
9276 case Intrinsic::x86_xop_vpcomltq:
9277 case Intrinsic::x86_xop_vpcomltub:
9278 case Intrinsic::x86_xop_vpcomltuw:
9279 case Intrinsic::x86_xop_vpcomltud:
9280 case Intrinsic::x86_xop_vpcomltuq:
9281 case Intrinsic::x86_xop_vpcomleb:
9282 case Intrinsic::x86_xop_vpcomlew:
9283 case Intrinsic::x86_xop_vpcomled:
9284 case Intrinsic::x86_xop_vpcomleq:
9285 case Intrinsic::x86_xop_vpcomleub:
9286 case Intrinsic::x86_xop_vpcomleuw:
9287 case Intrinsic::x86_xop_vpcomleud:
9288 case Intrinsic::x86_xop_vpcomleuq:
9289 case Intrinsic::x86_xop_vpcomgtb:
9290 case Intrinsic::x86_xop_vpcomgtw:
9291 case Intrinsic::x86_xop_vpcomgtd:
9292 case Intrinsic::x86_xop_vpcomgtq:
9293 case Intrinsic::x86_xop_vpcomgtub:
9294 case Intrinsic::x86_xop_vpcomgtuw:
9295 case Intrinsic::x86_xop_vpcomgtud:
9296 case Intrinsic::x86_xop_vpcomgtuq:
9297 case Intrinsic::x86_xop_vpcomgeb:
9298 case Intrinsic::x86_xop_vpcomgew:
9299 case Intrinsic::x86_xop_vpcomged:
9300 case Intrinsic::x86_xop_vpcomgeq:
9301 case Intrinsic::x86_xop_vpcomgeub:
9302 case Intrinsic::x86_xop_vpcomgeuw:
9303 case Intrinsic::x86_xop_vpcomgeud:
9304 case Intrinsic::x86_xop_vpcomgeuq:
9305 case Intrinsic::x86_xop_vpcomeqb:
9306 case Intrinsic::x86_xop_vpcomeqw:
9307 case Intrinsic::x86_xop_vpcomeqd:
9308 case Intrinsic::x86_xop_vpcomeqq:
9309 case Intrinsic::x86_xop_vpcomequb:
9310 case Intrinsic::x86_xop_vpcomequw:
9311 case Intrinsic::x86_xop_vpcomequd:
9312 case Intrinsic::x86_xop_vpcomequq:
9313 case Intrinsic::x86_xop_vpcomneb:
9314 case Intrinsic::x86_xop_vpcomnew:
9315 case Intrinsic::x86_xop_vpcomned:
9316 case Intrinsic::x86_xop_vpcomneq:
9317 case Intrinsic::x86_xop_vpcomneub:
9318 case Intrinsic::x86_xop_vpcomneuw:
9319 case Intrinsic::x86_xop_vpcomneud:
9320 case Intrinsic::x86_xop_vpcomneuq:
9321 case Intrinsic::x86_xop_vpcomfalseb:
9322 case Intrinsic::x86_xop_vpcomfalsew:
9323 case Intrinsic::x86_xop_vpcomfalsed:
9324 case Intrinsic::x86_xop_vpcomfalseq:
9325 case Intrinsic::x86_xop_vpcomfalseub:
9326 case Intrinsic::x86_xop_vpcomfalseuw:
9327 case Intrinsic::x86_xop_vpcomfalseud:
9328 case Intrinsic::x86_xop_vpcomfalseuq:
9329 case Intrinsic::x86_xop_vpcomtrueb:
9330 case Intrinsic::x86_xop_vpcomtruew:
9331 case Intrinsic::x86_xop_vpcomtrued:
9332 case Intrinsic::x86_xop_vpcomtrueq:
9333 case Intrinsic::x86_xop_vpcomtrueub:
9334 case Intrinsic::x86_xop_vpcomtrueuw:
9335 case Intrinsic::x86_xop_vpcomtrueud:
9336 case Intrinsic::x86_xop_vpcomtrueuq: {
9341 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9342 case Intrinsic::x86_xop_vpcomltb:
9343 case Intrinsic::x86_xop_vpcomltw:
9344 case Intrinsic::x86_xop_vpcomltd:
9345 case Intrinsic::x86_xop_vpcomltq:
9347 Opc = X86ISD::VPCOM;
9349 case Intrinsic::x86_xop_vpcomltub:
9350 case Intrinsic::x86_xop_vpcomltuw:
9351 case Intrinsic::x86_xop_vpcomltud:
9352 case Intrinsic::x86_xop_vpcomltuq:
9354 Opc = X86ISD::VPCOMU;
9356 case Intrinsic::x86_xop_vpcomleb:
9357 case Intrinsic::x86_xop_vpcomlew:
9358 case Intrinsic::x86_xop_vpcomled:
9359 case Intrinsic::x86_xop_vpcomleq:
9361 Opc = X86ISD::VPCOM;
9363 case Intrinsic::x86_xop_vpcomleub:
9364 case Intrinsic::x86_xop_vpcomleuw:
9365 case Intrinsic::x86_xop_vpcomleud:
9366 case Intrinsic::x86_xop_vpcomleuq:
9368 Opc = X86ISD::VPCOMU;
9370 case Intrinsic::x86_xop_vpcomgtb:
9371 case Intrinsic::x86_xop_vpcomgtw:
9372 case Intrinsic::x86_xop_vpcomgtd:
9373 case Intrinsic::x86_xop_vpcomgtq:
9375 Opc = X86ISD::VPCOM;
9377 case Intrinsic::x86_xop_vpcomgtub:
9378 case Intrinsic::x86_xop_vpcomgtuw:
9379 case Intrinsic::x86_xop_vpcomgtud:
9380 case Intrinsic::x86_xop_vpcomgtuq:
9382 Opc = X86ISD::VPCOMU;
9384 case Intrinsic::x86_xop_vpcomgeb:
9385 case Intrinsic::x86_xop_vpcomgew:
9386 case Intrinsic::x86_xop_vpcomged:
9387 case Intrinsic::x86_xop_vpcomgeq:
9389 Opc = X86ISD::VPCOM;
9391 case Intrinsic::x86_xop_vpcomgeub:
9392 case Intrinsic::x86_xop_vpcomgeuw:
9393 case Intrinsic::x86_xop_vpcomgeud:
9394 case Intrinsic::x86_xop_vpcomgeuq:
9396 Opc = X86ISD::VPCOMU;
9398 case Intrinsic::x86_xop_vpcomeqb:
9399 case Intrinsic::x86_xop_vpcomeqw:
9400 case Intrinsic::x86_xop_vpcomeqd:
9401 case Intrinsic::x86_xop_vpcomeqq:
9403 Opc = X86ISD::VPCOM;
9405 case Intrinsic::x86_xop_vpcomequb:
9406 case Intrinsic::x86_xop_vpcomequw:
9407 case Intrinsic::x86_xop_vpcomequd:
9408 case Intrinsic::x86_xop_vpcomequq:
9410 Opc = X86ISD::VPCOMU;
9412 case Intrinsic::x86_xop_vpcomneb:
9413 case Intrinsic::x86_xop_vpcomnew:
9414 case Intrinsic::x86_xop_vpcomned:
9415 case Intrinsic::x86_xop_vpcomneq:
9417 Opc = X86ISD::VPCOM;
9419 case Intrinsic::x86_xop_vpcomneub:
9420 case Intrinsic::x86_xop_vpcomneuw:
9421 case Intrinsic::x86_xop_vpcomneud:
9422 case Intrinsic::x86_xop_vpcomneuq:
9424 Opc = X86ISD::VPCOMU;
9426 case Intrinsic::x86_xop_vpcomfalseb:
9427 case Intrinsic::x86_xop_vpcomfalsew:
9428 case Intrinsic::x86_xop_vpcomfalsed:
9429 case Intrinsic::x86_xop_vpcomfalseq:
9431 Opc = X86ISD::VPCOM;
9433 case Intrinsic::x86_xop_vpcomfalseub:
9434 case Intrinsic::x86_xop_vpcomfalseuw:
9435 case Intrinsic::x86_xop_vpcomfalseud:
9436 case Intrinsic::x86_xop_vpcomfalseuq:
9438 Opc = X86ISD::VPCOMU;
9440 case Intrinsic::x86_xop_vpcomtrueb:
9441 case Intrinsic::x86_xop_vpcomtruew:
9442 case Intrinsic::x86_xop_vpcomtrued:
9443 case Intrinsic::x86_xop_vpcomtrueq:
9445 Opc = X86ISD::VPCOM;
9447 case Intrinsic::x86_xop_vpcomtrueub:
9448 case Intrinsic::x86_xop_vpcomtrueuw:
9449 case Intrinsic::x86_xop_vpcomtrueud:
9450 case Intrinsic::x86_xop_vpcomtrueuq:
9452 Opc = X86ISD::VPCOMU;
9456 SDValue LHS = Op.getOperand(1);
9457 SDValue RHS = Op.getOperand(2);
9458 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9459 DAG.getConstant(CC, MVT::i8));
9462 // Arithmetic intrinsics.
9463 case Intrinsic::x86_sse3_hadd_ps:
9464 case Intrinsic::x86_sse3_hadd_pd:
9465 case Intrinsic::x86_avx_hadd_ps_256:
9466 case Intrinsic::x86_avx_hadd_pd_256:
9467 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9468 Op.getOperand(1), Op.getOperand(2));
9469 case Intrinsic::x86_sse3_hsub_ps:
9470 case Intrinsic::x86_sse3_hsub_pd:
9471 case Intrinsic::x86_avx_hsub_ps_256:
9472 case Intrinsic::x86_avx_hsub_pd_256:
9473 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9474 Op.getOperand(1), Op.getOperand(2));
9475 case Intrinsic::x86_ssse3_phadd_w_128:
9476 case Intrinsic::x86_ssse3_phadd_d_128:
9477 case Intrinsic::x86_avx2_phadd_w:
9478 case Intrinsic::x86_avx2_phadd_d:
9479 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9480 Op.getOperand(1), Op.getOperand(2));
9481 case Intrinsic::x86_ssse3_phsub_w_128:
9482 case Intrinsic::x86_ssse3_phsub_d_128:
9483 case Intrinsic::x86_avx2_phsub_w:
9484 case Intrinsic::x86_avx2_phsub_d:
9485 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9486 Op.getOperand(1), Op.getOperand(2));
9487 case Intrinsic::x86_avx2_psllv_d:
9488 case Intrinsic::x86_avx2_psllv_q:
9489 case Intrinsic::x86_avx2_psllv_d_256:
9490 case Intrinsic::x86_avx2_psllv_q_256:
9491 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9492 Op.getOperand(1), Op.getOperand(2));
9493 case Intrinsic::x86_avx2_psrlv_d:
9494 case Intrinsic::x86_avx2_psrlv_q:
9495 case Intrinsic::x86_avx2_psrlv_d_256:
9496 case Intrinsic::x86_avx2_psrlv_q_256:
9497 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9498 Op.getOperand(1), Op.getOperand(2));
9499 case Intrinsic::x86_avx2_psrav_d:
9500 case Intrinsic::x86_avx2_psrav_d_256:
9501 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9502 Op.getOperand(1), Op.getOperand(2));
9503 case Intrinsic::x86_ssse3_pshuf_b_128:
9504 case Intrinsic::x86_avx2_pshuf_b:
9505 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9506 Op.getOperand(1), Op.getOperand(2));
9507 case Intrinsic::x86_ssse3_psign_b_128:
9508 case Intrinsic::x86_ssse3_psign_w_128:
9509 case Intrinsic::x86_ssse3_psign_d_128:
9510 case Intrinsic::x86_avx2_psign_b:
9511 case Intrinsic::x86_avx2_psign_w:
9512 case Intrinsic::x86_avx2_psign_d:
9513 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9514 Op.getOperand(1), Op.getOperand(2));
9515 case Intrinsic::x86_sse41_insertps:
9516 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9517 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9518 case Intrinsic::x86_avx_vperm2f128_ps_256:
9519 case Intrinsic::x86_avx_vperm2f128_pd_256:
9520 case Intrinsic::x86_avx_vperm2f128_si_256:
9521 case Intrinsic::x86_avx2_vperm2i128:
9522 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9523 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9525 // ptest and testp intrinsics. The intrinsic these come from are designed to
9526 // return an integer value, not just an instruction so lower it to the ptest
9527 // or testp pattern and a setcc for the result.
9528 case Intrinsic::x86_sse41_ptestz:
9529 case Intrinsic::x86_sse41_ptestc:
9530 case Intrinsic::x86_sse41_ptestnzc:
9531 case Intrinsic::x86_avx_ptestz_256:
9532 case Intrinsic::x86_avx_ptestc_256:
9533 case Intrinsic::x86_avx_ptestnzc_256:
9534 case Intrinsic::x86_avx_vtestz_ps:
9535 case Intrinsic::x86_avx_vtestc_ps:
9536 case Intrinsic::x86_avx_vtestnzc_ps:
9537 case Intrinsic::x86_avx_vtestz_pd:
9538 case Intrinsic::x86_avx_vtestc_pd:
9539 case Intrinsic::x86_avx_vtestnzc_pd:
9540 case Intrinsic::x86_avx_vtestz_ps_256:
9541 case Intrinsic::x86_avx_vtestc_ps_256:
9542 case Intrinsic::x86_avx_vtestnzc_ps_256:
9543 case Intrinsic::x86_avx_vtestz_pd_256:
9544 case Intrinsic::x86_avx_vtestc_pd_256:
9545 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9546 bool IsTestPacked = false;
9549 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9550 case Intrinsic::x86_avx_vtestz_ps:
9551 case Intrinsic::x86_avx_vtestz_pd:
9552 case Intrinsic::x86_avx_vtestz_ps_256:
9553 case Intrinsic::x86_avx_vtestz_pd_256:
9554 IsTestPacked = true; // Fallthrough
9555 case Intrinsic::x86_sse41_ptestz:
9556 case Intrinsic::x86_avx_ptestz_256:
9558 X86CC = X86::COND_E;
9560 case Intrinsic::x86_avx_vtestc_ps:
9561 case Intrinsic::x86_avx_vtestc_pd:
9562 case Intrinsic::x86_avx_vtestc_ps_256:
9563 case Intrinsic::x86_avx_vtestc_pd_256:
9564 IsTestPacked = true; // Fallthrough
9565 case Intrinsic::x86_sse41_ptestc:
9566 case Intrinsic::x86_avx_ptestc_256:
9568 X86CC = X86::COND_B;
9570 case Intrinsic::x86_avx_vtestnzc_ps:
9571 case Intrinsic::x86_avx_vtestnzc_pd:
9572 case Intrinsic::x86_avx_vtestnzc_ps_256:
9573 case Intrinsic::x86_avx_vtestnzc_pd_256:
9574 IsTestPacked = true; // Fallthrough
9575 case Intrinsic::x86_sse41_ptestnzc:
9576 case Intrinsic::x86_avx_ptestnzc_256:
9578 X86CC = X86::COND_A;
9582 SDValue LHS = Op.getOperand(1);
9583 SDValue RHS = Op.getOperand(2);
9584 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9585 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9586 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9587 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9588 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9591 // SSE/AVX shift intrinsics
9592 case Intrinsic::x86_sse2_psll_w:
9593 case Intrinsic::x86_sse2_psll_d:
9594 case Intrinsic::x86_sse2_psll_q:
9595 case Intrinsic::x86_avx2_psll_w:
9596 case Intrinsic::x86_avx2_psll_d:
9597 case Intrinsic::x86_avx2_psll_q:
9598 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9599 Op.getOperand(1), Op.getOperand(2));
9600 case Intrinsic::x86_sse2_psrl_w:
9601 case Intrinsic::x86_sse2_psrl_d:
9602 case Intrinsic::x86_sse2_psrl_q:
9603 case Intrinsic::x86_avx2_psrl_w:
9604 case Intrinsic::x86_avx2_psrl_d:
9605 case Intrinsic::x86_avx2_psrl_q:
9606 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9607 Op.getOperand(1), Op.getOperand(2));
9608 case Intrinsic::x86_sse2_psra_w:
9609 case Intrinsic::x86_sse2_psra_d:
9610 case Intrinsic::x86_avx2_psra_w:
9611 case Intrinsic::x86_avx2_psra_d:
9612 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9613 Op.getOperand(1), Op.getOperand(2));
9614 case Intrinsic::x86_sse2_pslli_w:
9615 case Intrinsic::x86_sse2_pslli_d:
9616 case Intrinsic::x86_sse2_pslli_q:
9617 case Intrinsic::x86_avx2_pslli_w:
9618 case Intrinsic::x86_avx2_pslli_d:
9619 case Intrinsic::x86_avx2_pslli_q:
9620 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9621 Op.getOperand(1), Op.getOperand(2), DAG);
9622 case Intrinsic::x86_sse2_psrli_w:
9623 case Intrinsic::x86_sse2_psrli_d:
9624 case Intrinsic::x86_sse2_psrli_q:
9625 case Intrinsic::x86_avx2_psrli_w:
9626 case Intrinsic::x86_avx2_psrli_d:
9627 case Intrinsic::x86_avx2_psrli_q:
9628 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9629 Op.getOperand(1), Op.getOperand(2), DAG);
9630 case Intrinsic::x86_sse2_psrai_w:
9631 case Intrinsic::x86_sse2_psrai_d:
9632 case Intrinsic::x86_avx2_psrai_w:
9633 case Intrinsic::x86_avx2_psrai_d:
9634 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9635 Op.getOperand(1), Op.getOperand(2), DAG);
9636 // Fix vector shift instructions where the last operand is a non-immediate
9638 case Intrinsic::x86_mmx_pslli_w:
9639 case Intrinsic::x86_mmx_pslli_d:
9640 case Intrinsic::x86_mmx_pslli_q:
9641 case Intrinsic::x86_mmx_psrli_w:
9642 case Intrinsic::x86_mmx_psrli_d:
9643 case Intrinsic::x86_mmx_psrli_q:
9644 case Intrinsic::x86_mmx_psrai_w:
9645 case Intrinsic::x86_mmx_psrai_d: {
9646 SDValue ShAmt = Op.getOperand(2);
9647 if (isa<ConstantSDNode>(ShAmt))
9650 unsigned NewIntNo = 0;
9652 case Intrinsic::x86_mmx_pslli_w:
9653 NewIntNo = Intrinsic::x86_mmx_psll_w;
9655 case Intrinsic::x86_mmx_pslli_d:
9656 NewIntNo = Intrinsic::x86_mmx_psll_d;
9658 case Intrinsic::x86_mmx_pslli_q:
9659 NewIntNo = Intrinsic::x86_mmx_psll_q;
9661 case Intrinsic::x86_mmx_psrli_w:
9662 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9664 case Intrinsic::x86_mmx_psrli_d:
9665 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9667 case Intrinsic::x86_mmx_psrli_q:
9668 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9670 case Intrinsic::x86_mmx_psrai_w:
9671 NewIntNo = Intrinsic::x86_mmx_psra_w;
9673 case Intrinsic::x86_mmx_psrai_d:
9674 NewIntNo = Intrinsic::x86_mmx_psra_d;
9676 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9679 // The vector shift intrinsics with scalars uses 32b shift amounts but
9680 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9682 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9683 DAG.getConstant(0, MVT::i32));
9684 // FIXME this must be lowered to get rid of the invalid type.
9686 EVT VT = Op.getValueType();
9687 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9688 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9689 DAG.getConstant(NewIntNo, MVT::i32),
9690 Op.getOperand(1), ShAmt);
9695 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9696 SelectionDAG &DAG) const {
9697 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9698 MFI->setReturnAddressIsTaken(true);
9700 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9701 DebugLoc dl = Op.getDebugLoc();
9704 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9706 DAG.getConstant(TD->getPointerSize(),
9707 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9708 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9709 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9711 MachinePointerInfo(), false, false, false, 0);
9714 // Just load the return address.
9715 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9716 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9717 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9720 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9721 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9722 MFI->setFrameAddressIsTaken(true);
9724 EVT VT = Op.getValueType();
9725 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9726 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9727 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9728 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9730 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9731 MachinePointerInfo(),
9732 false, false, false, 0);
9736 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9737 SelectionDAG &DAG) const {
9738 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9741 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9742 MachineFunction &MF = DAG.getMachineFunction();
9743 SDValue Chain = Op.getOperand(0);
9744 SDValue Offset = Op.getOperand(1);
9745 SDValue Handler = Op.getOperand(2);
9746 DebugLoc dl = Op.getDebugLoc();
9748 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9749 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9751 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9753 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9754 DAG.getIntPtrConstant(TD->getPointerSize()));
9755 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9756 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9758 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9759 MF.getRegInfo().addLiveOut(StoreAddrReg);
9761 return DAG.getNode(X86ISD::EH_RETURN, dl,
9763 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9766 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9767 SelectionDAG &DAG) const {
9768 return Op.getOperand(0);
9771 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9772 SelectionDAG &DAG) const {
9773 SDValue Root = Op.getOperand(0);
9774 SDValue Trmp = Op.getOperand(1); // trampoline
9775 SDValue FPtr = Op.getOperand(2); // nested function
9776 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9777 DebugLoc dl = Op.getDebugLoc();
9779 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9781 if (Subtarget->is64Bit()) {
9782 SDValue OutChains[6];
9784 // Large code-model.
9785 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9786 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9788 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9789 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9791 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9793 // Load the pointer to the nested function into R11.
9794 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9795 SDValue Addr = Trmp;
9796 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9797 Addr, MachinePointerInfo(TrmpAddr),
9800 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9801 DAG.getConstant(2, MVT::i64));
9802 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9803 MachinePointerInfo(TrmpAddr, 2),
9806 // Load the 'nest' parameter value into R10.
9807 // R10 is specified in X86CallingConv.td
9808 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9809 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9810 DAG.getConstant(10, MVT::i64));
9811 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9812 Addr, MachinePointerInfo(TrmpAddr, 10),
9815 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9816 DAG.getConstant(12, MVT::i64));
9817 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9818 MachinePointerInfo(TrmpAddr, 12),
9821 // Jump to the nested function.
9822 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9823 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9824 DAG.getConstant(20, MVT::i64));
9825 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9826 Addr, MachinePointerInfo(TrmpAddr, 20),
9829 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9830 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9831 DAG.getConstant(22, MVT::i64));
9832 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9833 MachinePointerInfo(TrmpAddr, 22),
9836 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9838 const Function *Func =
9839 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9840 CallingConv::ID CC = Func->getCallingConv();
9845 llvm_unreachable("Unsupported calling convention");
9846 case CallingConv::C:
9847 case CallingConv::X86_StdCall: {
9848 // Pass 'nest' parameter in ECX.
9849 // Must be kept in sync with X86CallingConv.td
9852 // Check that ECX wasn't needed by an 'inreg' parameter.
9853 FunctionType *FTy = Func->getFunctionType();
9854 const AttrListPtr &Attrs = Func->getAttributes();
9856 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9857 unsigned InRegCount = 0;
9860 for (FunctionType::param_iterator I = FTy->param_begin(),
9861 E = FTy->param_end(); I != E; ++I, ++Idx)
9862 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9863 // FIXME: should only count parameters that are lowered to integers.
9864 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9866 if (InRegCount > 2) {
9867 report_fatal_error("Nest register in use - reduce number of inreg"
9873 case CallingConv::X86_FastCall:
9874 case CallingConv::X86_ThisCall:
9875 case CallingConv::Fast:
9876 // Pass 'nest' parameter in EAX.
9877 // Must be kept in sync with X86CallingConv.td
9882 SDValue OutChains[4];
9885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9886 DAG.getConstant(10, MVT::i32));
9887 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9889 // This is storing the opcode for MOV32ri.
9890 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9891 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9892 OutChains[0] = DAG.getStore(Root, dl,
9893 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9894 Trmp, MachinePointerInfo(TrmpAddr),
9897 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9898 DAG.getConstant(1, MVT::i32));
9899 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9900 MachinePointerInfo(TrmpAddr, 1),
9903 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9904 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9905 DAG.getConstant(5, MVT::i32));
9906 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9907 MachinePointerInfo(TrmpAddr, 5),
9910 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9911 DAG.getConstant(6, MVT::i32));
9912 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9913 MachinePointerInfo(TrmpAddr, 6),
9916 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9920 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9921 SelectionDAG &DAG) const {
9923 The rounding mode is in bits 11:10 of FPSR, and has the following
9930 FLT_ROUNDS, on the other hand, expects the following:
9937 To perform the conversion, we do:
9938 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9941 MachineFunction &MF = DAG.getMachineFunction();
9942 const TargetMachine &TM = MF.getTarget();
9943 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9944 unsigned StackAlignment = TFI.getStackAlignment();
9945 EVT VT = Op.getValueType();
9946 DebugLoc DL = Op.getDebugLoc();
9948 // Save FP Control Word to stack slot
9949 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9950 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9953 MachineMemOperand *MMO =
9954 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9955 MachineMemOperand::MOStore, 2, 2);
9957 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9958 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9959 DAG.getVTList(MVT::Other),
9960 Ops, 2, MVT::i16, MMO);
9962 // Load FP Control Word from stack slot
9963 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9964 MachinePointerInfo(), false, false, false, 0);
9966 // Transform as necessary
9968 DAG.getNode(ISD::SRL, DL, MVT::i16,
9969 DAG.getNode(ISD::AND, DL, MVT::i16,
9970 CWD, DAG.getConstant(0x800, MVT::i16)),
9971 DAG.getConstant(11, MVT::i8));
9973 DAG.getNode(ISD::SRL, DL, MVT::i16,
9974 DAG.getNode(ISD::AND, DL, MVT::i16,
9975 CWD, DAG.getConstant(0x400, MVT::i16)),
9976 DAG.getConstant(9, MVT::i8));
9979 DAG.getNode(ISD::AND, DL, MVT::i16,
9980 DAG.getNode(ISD::ADD, DL, MVT::i16,
9981 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9982 DAG.getConstant(1, MVT::i16)),
9983 DAG.getConstant(3, MVT::i16));
9986 return DAG.getNode((VT.getSizeInBits() < 16 ?
9987 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9990 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9991 EVT VT = Op.getValueType();
9993 unsigned NumBits = VT.getSizeInBits();
9994 DebugLoc dl = Op.getDebugLoc();
9996 Op = Op.getOperand(0);
9997 if (VT == MVT::i8) {
9998 // Zero extend to i32 since there is not an i8 bsr.
10000 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10003 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10004 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10005 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10007 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10010 DAG.getConstant(NumBits+NumBits-1, OpVT),
10011 DAG.getConstant(X86::COND_E, MVT::i8),
10014 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10016 // Finally xor with NumBits-1.
10017 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10020 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10024 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10025 SelectionDAG &DAG) const {
10026 EVT VT = Op.getValueType();
10028 unsigned NumBits = VT.getSizeInBits();
10029 DebugLoc dl = Op.getDebugLoc();
10031 Op = Op.getOperand(0);
10032 if (VT == MVT::i8) {
10033 // Zero extend to i32 since there is not an i8 bsr.
10035 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10038 // Issue a bsr (scan bits in reverse).
10039 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10040 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10042 // And xor with NumBits-1.
10043 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10046 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10050 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10051 EVT VT = Op.getValueType();
10052 unsigned NumBits = VT.getSizeInBits();
10053 DebugLoc dl = Op.getDebugLoc();
10054 Op = Op.getOperand(0);
10056 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10057 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10058 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10060 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10063 DAG.getConstant(NumBits, VT),
10064 DAG.getConstant(X86::COND_E, MVT::i8),
10067 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10070 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10071 // ones, and then concatenate the result back.
10072 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10073 EVT VT = Op.getValueType();
10075 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10076 "Unsupported value type for operation");
10078 int NumElems = VT.getVectorNumElements();
10079 DebugLoc dl = Op.getDebugLoc();
10080 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10081 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10083 // Extract the LHS vectors
10084 SDValue LHS = Op.getOperand(0);
10085 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10086 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10088 // Extract the RHS vectors
10089 SDValue RHS = Op.getOperand(1);
10090 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10091 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10093 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10094 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10096 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10097 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10098 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10101 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10102 assert(Op.getValueType().getSizeInBits() == 256 &&
10103 Op.getValueType().isInteger() &&
10104 "Only handle AVX 256-bit vector integer operation");
10105 return Lower256IntArith(Op, DAG);
10108 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10109 assert(Op.getValueType().getSizeInBits() == 256 &&
10110 Op.getValueType().isInteger() &&
10111 "Only handle AVX 256-bit vector integer operation");
10112 return Lower256IntArith(Op, DAG);
10115 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10116 EVT VT = Op.getValueType();
10118 // Decompose 256-bit ops into smaller 128-bit ops.
10119 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10120 return Lower256IntArith(Op, DAG);
10122 DebugLoc dl = Op.getDebugLoc();
10124 SDValue A = Op.getOperand(0);
10125 SDValue B = Op.getOperand(1);
10127 if (VT == MVT::v4i64) {
10128 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
10130 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
10131 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
10132 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
10133 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
10134 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
10136 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
10137 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
10138 // return AloBlo + AloBhi + AhiBlo;
10140 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
10141 DAG.getConstant(32, MVT::i32));
10142 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
10143 DAG.getConstant(32, MVT::i32));
10144 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10145 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10147 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10148 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10150 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10151 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
10153 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
10154 DAG.getConstant(32, MVT::i32));
10155 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
10156 DAG.getConstant(32, MVT::i32));
10157 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10158 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10162 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
10164 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
10165 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
10166 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
10167 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
10168 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
10170 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
10171 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
10172 // return AloBlo + AloBhi + AhiBlo;
10174 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
10175 DAG.getConstant(32, MVT::i32));
10176 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
10177 DAG.getConstant(32, MVT::i32));
10178 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10179 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10181 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10182 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10184 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10185 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10187 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
10188 DAG.getConstant(32, MVT::i32));
10189 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
10190 DAG.getConstant(32, MVT::i32));
10191 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10192 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10196 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10198 EVT VT = Op.getValueType();
10199 DebugLoc dl = Op.getDebugLoc();
10200 SDValue R = Op.getOperand(0);
10201 SDValue Amt = Op.getOperand(1);
10202 LLVMContext *Context = DAG.getContext();
10204 if (!Subtarget->hasSSE2())
10207 // Optimize shl/srl/sra with constant shift amount.
10208 if (isSplatVector(Amt.getNode())) {
10209 SDValue SclrAmt = Amt->getOperand(0);
10210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10211 uint64_t ShiftAmt = C->getZExtValue();
10213 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10214 (Subtarget->hasAVX2() &&
10215 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10216 if (Op.getOpcode() == ISD::SHL)
10217 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10218 DAG.getConstant(ShiftAmt, MVT::i32));
10219 if (Op.getOpcode() == ISD::SRL)
10220 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10221 DAG.getConstant(ShiftAmt, MVT::i32));
10222 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10223 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10224 DAG.getConstant(ShiftAmt, MVT::i32));
10227 if (VT == MVT::v16i8) {
10228 if (Op.getOpcode() == ISD::SHL) {
10229 // Make a large shift.
10230 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10231 DAG.getConstant(ShiftAmt, MVT::i32));
10232 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10233 // Zero out the rightmost bits.
10234 SmallVector<SDValue, 16> V(16,
10235 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10237 return DAG.getNode(ISD::AND, dl, VT, SHL,
10238 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10240 if (Op.getOpcode() == ISD::SRL) {
10241 // Make a large shift.
10242 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10243 DAG.getConstant(ShiftAmt, MVT::i32));
10244 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10245 // Zero out the leftmost bits.
10246 SmallVector<SDValue, 16> V(16,
10247 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10249 return DAG.getNode(ISD::AND, dl, VT, SRL,
10250 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10252 if (Op.getOpcode() == ISD::SRA) {
10253 if (ShiftAmt == 7) {
10254 // R s>> 7 === R s< 0
10255 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true,
10256 /* HasAVX2 */false, DAG, dl);
10257 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10260 // R s>> a === ((R u>> a) ^ m) - m
10261 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10262 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10264 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10265 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10266 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10271 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10272 if (Op.getOpcode() == ISD::SHL) {
10273 // Make a large shift.
10274 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10275 DAG.getConstant(ShiftAmt, MVT::i32));
10276 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10277 // Zero out the rightmost bits.
10278 SmallVector<SDValue, 32> V(32,
10279 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10281 return DAG.getNode(ISD::AND, dl, VT, SHL,
10282 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10284 if (Op.getOpcode() == ISD::SRL) {
10285 // Make a large shift.
10286 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10287 DAG.getConstant(ShiftAmt, MVT::i32));
10288 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10289 // Zero out the leftmost bits.
10290 SmallVector<SDValue, 32> V(32,
10291 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10293 return DAG.getNode(ISD::AND, dl, VT, SRL,
10294 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10296 if (Op.getOpcode() == ISD::SRA) {
10297 if (ShiftAmt == 7) {
10298 // R s>> 7 === R s< 0
10299 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */,
10300 true /* HasAVX2 */, DAG, dl);
10301 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10304 // R s>> a === ((R u>> a) ^ m) - m
10305 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10306 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10308 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10309 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10310 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10317 // Lower SHL with variable shift amount.
10318 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10319 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10320 DAG.getConstant(23, MVT::i32));
10322 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10323 Constant *C = ConstantVector::getSplat(4, CI);
10324 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10325 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10326 MachinePointerInfo::getConstantPool(),
10327 false, false, false, 16);
10329 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10330 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10331 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10332 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10334 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10335 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10338 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10339 DAG.getConstant(5, MVT::i32));
10340 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10342 // Turn 'a' into a mask suitable for VSELECT
10343 SDValue VSelM = DAG.getConstant(0x80, VT);
10344 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10345 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10347 SDValue CM1 = DAG.getConstant(0x0f, VT);
10348 SDValue CM2 = DAG.getConstant(0x3f, VT);
10350 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10351 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10352 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10353 DAG.getConstant(4, MVT::i32), DAG);
10354 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10355 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10358 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10359 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10360 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10362 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10363 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10364 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10365 DAG.getConstant(2, MVT::i32), DAG);
10366 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10367 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10370 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10371 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10372 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10374 // return VSELECT(r, r+r, a);
10375 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10376 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10380 // Decompose 256-bit shifts into smaller 128-bit shifts.
10381 if (VT.getSizeInBits() == 256) {
10382 unsigned NumElems = VT.getVectorNumElements();
10383 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10384 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10386 // Extract the two vectors
10387 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10388 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10391 // Recreate the shift amount vectors
10392 SDValue Amt1, Amt2;
10393 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10394 // Constant shift amount
10395 SmallVector<SDValue, 4> Amt1Csts;
10396 SmallVector<SDValue, 4> Amt2Csts;
10397 for (unsigned i = 0; i != NumElems/2; ++i)
10398 Amt1Csts.push_back(Amt->getOperand(i));
10399 for (unsigned i = NumElems/2; i != NumElems; ++i)
10400 Amt2Csts.push_back(Amt->getOperand(i));
10402 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10403 &Amt1Csts[0], NumElems/2);
10404 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10405 &Amt2Csts[0], NumElems/2);
10407 // Variable shift amount
10408 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10409 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10413 // Issue new vector shifts for the smaller types
10414 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10415 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10417 // Concatenate the result back
10418 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10424 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10425 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10426 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10427 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10428 // has only one use.
10429 SDNode *N = Op.getNode();
10430 SDValue LHS = N->getOperand(0);
10431 SDValue RHS = N->getOperand(1);
10432 unsigned BaseOp = 0;
10434 DebugLoc DL = Op.getDebugLoc();
10435 switch (Op.getOpcode()) {
10436 default: llvm_unreachable("Unknown ovf instruction!");
10438 // A subtract of one will be selected as a INC. Note that INC doesn't
10439 // set CF, so we can't do this for UADDO.
10440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10442 BaseOp = X86ISD::INC;
10443 Cond = X86::COND_O;
10446 BaseOp = X86ISD::ADD;
10447 Cond = X86::COND_O;
10450 BaseOp = X86ISD::ADD;
10451 Cond = X86::COND_B;
10454 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10455 // set CF, so we can't do this for USUBO.
10456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10458 BaseOp = X86ISD::DEC;
10459 Cond = X86::COND_O;
10462 BaseOp = X86ISD::SUB;
10463 Cond = X86::COND_O;
10466 BaseOp = X86ISD::SUB;
10467 Cond = X86::COND_B;
10470 BaseOp = X86ISD::SMUL;
10471 Cond = X86::COND_O;
10473 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10474 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10476 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10479 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10480 DAG.getConstant(X86::COND_O, MVT::i32),
10481 SDValue(Sum.getNode(), 2));
10483 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10487 // Also sets EFLAGS.
10488 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10489 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10492 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10493 DAG.getConstant(Cond, MVT::i32),
10494 SDValue(Sum.getNode(), 1));
10496 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10499 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10500 SelectionDAG &DAG) const {
10501 DebugLoc dl = Op.getDebugLoc();
10502 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10503 EVT VT = Op.getValueType();
10505 if (!Subtarget->hasSSE2() || !VT.isVector())
10508 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10509 ExtraVT.getScalarType().getSizeInBits();
10510 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10512 switch (VT.getSimpleVT().SimpleTy) {
10513 default: return SDValue();
10516 if (!Subtarget->hasAVX())
10518 if (!Subtarget->hasAVX2()) {
10519 // needs to be split
10520 int NumElems = VT.getVectorNumElements();
10521 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10522 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10524 // Extract the LHS vectors
10525 SDValue LHS = Op.getOperand(0);
10526 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10527 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10529 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10530 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10532 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10533 int ExtraNumElems = ExtraVT.getVectorNumElements();
10534 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10536 SDValue Extra = DAG.getValueType(ExtraVT);
10538 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10539 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10541 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10546 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10547 Op.getOperand(0), ShAmt, DAG);
10548 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10554 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10555 DebugLoc dl = Op.getDebugLoc();
10557 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10558 // There isn't any reason to disable it if the target processor supports it.
10559 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10560 SDValue Chain = Op.getOperand(0);
10561 SDValue Zero = DAG.getConstant(0, MVT::i32);
10563 DAG.getRegister(X86::ESP, MVT::i32), // Base
10564 DAG.getTargetConstant(1, MVT::i8), // Scale
10565 DAG.getRegister(0, MVT::i32), // Index
10566 DAG.getTargetConstant(0, MVT::i32), // Disp
10567 DAG.getRegister(0, MVT::i32), // Segment.
10572 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10573 array_lengthof(Ops));
10574 return SDValue(Res, 0);
10577 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10579 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10581 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10582 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10583 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10584 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10586 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10587 if (!Op1 && !Op2 && !Op3 && Op4)
10588 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10590 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10591 if (Op1 && !Op2 && !Op3 && !Op4)
10592 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10594 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10596 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10599 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10600 SelectionDAG &DAG) const {
10601 DebugLoc dl = Op.getDebugLoc();
10602 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10603 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10604 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10605 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10607 // The only fence that needs an instruction is a sequentially-consistent
10608 // cross-thread fence.
10609 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10610 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10611 // no-sse2). There isn't any reason to disable it if the target processor
10613 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10614 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10616 SDValue Chain = Op.getOperand(0);
10617 SDValue Zero = DAG.getConstant(0, MVT::i32);
10619 DAG.getRegister(X86::ESP, MVT::i32), // Base
10620 DAG.getTargetConstant(1, MVT::i8), // Scale
10621 DAG.getRegister(0, MVT::i32), // Index
10622 DAG.getTargetConstant(0, MVT::i32), // Disp
10623 DAG.getRegister(0, MVT::i32), // Segment.
10628 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10629 array_lengthof(Ops));
10630 return SDValue(Res, 0);
10633 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10634 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10638 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10639 EVT T = Op.getValueType();
10640 DebugLoc DL = Op.getDebugLoc();
10643 switch(T.getSimpleVT().SimpleTy) {
10645 assert(false && "Invalid value type!");
10646 case MVT::i8: Reg = X86::AL; size = 1; break;
10647 case MVT::i16: Reg = X86::AX; size = 2; break;
10648 case MVT::i32: Reg = X86::EAX; size = 4; break;
10650 assert(Subtarget->is64Bit() && "Node not type legal!");
10651 Reg = X86::RAX; size = 8;
10654 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10655 Op.getOperand(2), SDValue());
10656 SDValue Ops[] = { cpIn.getValue(0),
10659 DAG.getTargetConstant(size, MVT::i8),
10660 cpIn.getValue(1) };
10661 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10662 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10663 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10666 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10670 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10671 SelectionDAG &DAG) const {
10672 assert(Subtarget->is64Bit() && "Result not type legalized?");
10673 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10674 SDValue TheChain = Op.getOperand(0);
10675 DebugLoc dl = Op.getDebugLoc();
10676 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10677 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10678 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10680 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10681 DAG.getConstant(32, MVT::i8));
10683 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10686 return DAG.getMergeValues(Ops, 2, dl);
10689 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10690 SelectionDAG &DAG) const {
10691 EVT SrcVT = Op.getOperand(0).getValueType();
10692 EVT DstVT = Op.getValueType();
10693 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10694 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10695 assert((DstVT == MVT::i64 ||
10696 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10697 "Unexpected custom BITCAST");
10698 // i64 <=> MMX conversions are Legal.
10699 if (SrcVT==MVT::i64 && DstVT.isVector())
10701 if (DstVT==MVT::i64 && SrcVT.isVector())
10703 // MMX <=> MMX conversions are Legal.
10704 if (SrcVT.isVector() && DstVT.isVector())
10706 // All other conversions need to be expanded.
10710 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10711 SDNode *Node = Op.getNode();
10712 DebugLoc dl = Node->getDebugLoc();
10713 EVT T = Node->getValueType(0);
10714 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10715 DAG.getConstant(0, T), Node->getOperand(2));
10716 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10717 cast<AtomicSDNode>(Node)->getMemoryVT(),
10718 Node->getOperand(0),
10719 Node->getOperand(1), negOp,
10720 cast<AtomicSDNode>(Node)->getSrcValue(),
10721 cast<AtomicSDNode>(Node)->getAlignment(),
10722 cast<AtomicSDNode>(Node)->getOrdering(),
10723 cast<AtomicSDNode>(Node)->getSynchScope());
10726 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10727 SDNode *Node = Op.getNode();
10728 DebugLoc dl = Node->getDebugLoc();
10729 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10731 // Convert seq_cst store -> xchg
10732 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10733 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10734 // (The only way to get a 16-byte store is cmpxchg16b)
10735 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10736 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10737 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10738 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10739 cast<AtomicSDNode>(Node)->getMemoryVT(),
10740 Node->getOperand(0),
10741 Node->getOperand(1), Node->getOperand(2),
10742 cast<AtomicSDNode>(Node)->getMemOperand(),
10743 cast<AtomicSDNode>(Node)->getOrdering(),
10744 cast<AtomicSDNode>(Node)->getSynchScope());
10745 return Swap.getValue(1);
10747 // Other atomic stores have a simple pattern.
10751 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10752 EVT VT = Op.getNode()->getValueType(0);
10754 // Let legalize expand this if it isn't a legal type yet.
10755 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10758 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10761 bool ExtraOp = false;
10762 switch (Op.getOpcode()) {
10763 default: assert(0 && "Invalid code");
10764 case ISD::ADDC: Opc = X86ISD::ADD; break;
10765 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10766 case ISD::SUBC: Opc = X86ISD::SUB; break;
10767 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10771 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10773 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10774 Op.getOperand(1), Op.getOperand(2));
10777 /// LowerOperation - Provide custom lowering hooks for some operations.
10779 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10780 switch (Op.getOpcode()) {
10781 default: llvm_unreachable("Should not custom lower this!");
10782 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10783 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10784 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10785 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10786 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10787 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10788 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10789 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10790 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10791 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10792 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10793 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10794 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10795 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10796 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10797 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10798 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10799 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10800 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10801 case ISD::SHL_PARTS:
10802 case ISD::SRA_PARTS:
10803 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10804 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10805 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10806 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10807 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10808 case ISD::FABS: return LowerFABS(Op, DAG);
10809 case ISD::FNEG: return LowerFNEG(Op, DAG);
10810 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10811 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10812 case ISD::SETCC: return LowerSETCC(Op, DAG);
10813 case ISD::SELECT: return LowerSELECT(Op, DAG);
10814 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10815 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10816 case ISD::VASTART: return LowerVASTART(Op, DAG);
10817 case ISD::VAARG: return LowerVAARG(Op, DAG);
10818 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10819 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10820 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10821 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10822 case ISD::FRAME_TO_ARGS_OFFSET:
10823 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10824 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10825 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10826 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10827 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10828 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10829 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10830 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10831 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10832 case ISD::MUL: return LowerMUL(Op, DAG);
10835 case ISD::SHL: return LowerShift(Op, DAG);
10841 case ISD::UMULO: return LowerXALUO(Op, DAG);
10842 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10843 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10847 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10848 case ISD::ADD: return LowerADD(Op, DAG);
10849 case ISD::SUB: return LowerSUB(Op, DAG);
10853 static void ReplaceATOMIC_LOAD(SDNode *Node,
10854 SmallVectorImpl<SDValue> &Results,
10855 SelectionDAG &DAG) {
10856 DebugLoc dl = Node->getDebugLoc();
10857 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10859 // Convert wide load -> cmpxchg8b/cmpxchg16b
10860 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10861 // (The only way to get a 16-byte load is cmpxchg16b)
10862 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10863 SDValue Zero = DAG.getConstant(0, VT);
10864 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10865 Node->getOperand(0),
10866 Node->getOperand(1), Zero, Zero,
10867 cast<AtomicSDNode>(Node)->getMemOperand(),
10868 cast<AtomicSDNode>(Node)->getOrdering(),
10869 cast<AtomicSDNode>(Node)->getSynchScope());
10870 Results.push_back(Swap.getValue(0));
10871 Results.push_back(Swap.getValue(1));
10874 void X86TargetLowering::
10875 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10876 SelectionDAG &DAG, unsigned NewOp) const {
10877 DebugLoc dl = Node->getDebugLoc();
10878 assert (Node->getValueType(0) == MVT::i64 &&
10879 "Only know how to expand i64 atomics");
10881 SDValue Chain = Node->getOperand(0);
10882 SDValue In1 = Node->getOperand(1);
10883 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10884 Node->getOperand(2), DAG.getIntPtrConstant(0));
10885 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10886 Node->getOperand(2), DAG.getIntPtrConstant(1));
10887 SDValue Ops[] = { Chain, In1, In2L, In2H };
10888 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10890 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10891 cast<MemSDNode>(Node)->getMemOperand());
10892 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10893 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10894 Results.push_back(Result.getValue(2));
10897 /// ReplaceNodeResults - Replace a node with an illegal result type
10898 /// with a new node built out of custom code.
10899 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10900 SmallVectorImpl<SDValue>&Results,
10901 SelectionDAG &DAG) const {
10902 DebugLoc dl = N->getDebugLoc();
10903 switch (N->getOpcode()) {
10905 assert(false && "Do not know how to custom type legalize this operation!");
10907 case ISD::SIGN_EXTEND_INREG:
10912 // We don't want to expand or promote these.
10914 case ISD::FP_TO_SINT: {
10915 std::pair<SDValue,SDValue> Vals =
10916 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10917 SDValue FIST = Vals.first, StackSlot = Vals.second;
10918 if (FIST.getNode() != 0) {
10919 EVT VT = N->getValueType(0);
10920 // Return a load from the stack slot.
10921 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10922 MachinePointerInfo(),
10923 false, false, false, 0));
10927 case ISD::READCYCLECOUNTER: {
10928 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10929 SDValue TheChain = N->getOperand(0);
10930 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10931 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10933 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10935 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10936 SDValue Ops[] = { eax, edx };
10937 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10938 Results.push_back(edx.getValue(1));
10941 case ISD::ATOMIC_CMP_SWAP: {
10942 EVT T = N->getValueType(0);
10943 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10944 bool Regs64bit = T == MVT::i128;
10945 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10946 SDValue cpInL, cpInH;
10947 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10948 DAG.getConstant(0, HalfT));
10949 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10950 DAG.getConstant(1, HalfT));
10951 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10952 Regs64bit ? X86::RAX : X86::EAX,
10954 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10955 Regs64bit ? X86::RDX : X86::EDX,
10956 cpInH, cpInL.getValue(1));
10957 SDValue swapInL, swapInH;
10958 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10959 DAG.getConstant(0, HalfT));
10960 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10961 DAG.getConstant(1, HalfT));
10962 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10963 Regs64bit ? X86::RBX : X86::EBX,
10964 swapInL, cpInH.getValue(1));
10965 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10966 Regs64bit ? X86::RCX : X86::ECX,
10967 swapInH, swapInL.getValue(1));
10968 SDValue Ops[] = { swapInH.getValue(0),
10970 swapInH.getValue(1) };
10971 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10972 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10973 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10974 X86ISD::LCMPXCHG8_DAG;
10975 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10977 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10978 Regs64bit ? X86::RAX : X86::EAX,
10979 HalfT, Result.getValue(1));
10980 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10981 Regs64bit ? X86::RDX : X86::EDX,
10982 HalfT, cpOutL.getValue(2));
10983 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10984 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10985 Results.push_back(cpOutH.getValue(1));
10988 case ISD::ATOMIC_LOAD_ADD:
10989 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10991 case ISD::ATOMIC_LOAD_AND:
10992 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10994 case ISD::ATOMIC_LOAD_NAND:
10995 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10997 case ISD::ATOMIC_LOAD_OR:
10998 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11000 case ISD::ATOMIC_LOAD_SUB:
11001 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11003 case ISD::ATOMIC_LOAD_XOR:
11004 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11006 case ISD::ATOMIC_SWAP:
11007 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11009 case ISD::ATOMIC_LOAD:
11010 ReplaceATOMIC_LOAD(N, Results, DAG);
11014 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11016 default: return NULL;
11017 case X86ISD::BSF: return "X86ISD::BSF";
11018 case X86ISD::BSR: return "X86ISD::BSR";
11019 case X86ISD::SHLD: return "X86ISD::SHLD";
11020 case X86ISD::SHRD: return "X86ISD::SHRD";
11021 case X86ISD::FAND: return "X86ISD::FAND";
11022 case X86ISD::FOR: return "X86ISD::FOR";
11023 case X86ISD::FXOR: return "X86ISD::FXOR";
11024 case X86ISD::FSRL: return "X86ISD::FSRL";
11025 case X86ISD::FILD: return "X86ISD::FILD";
11026 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11027 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11028 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11029 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11030 case X86ISD::FLD: return "X86ISD::FLD";
11031 case X86ISD::FST: return "X86ISD::FST";
11032 case X86ISD::CALL: return "X86ISD::CALL";
11033 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11034 case X86ISD::BT: return "X86ISD::BT";
11035 case X86ISD::CMP: return "X86ISD::CMP";
11036 case X86ISD::COMI: return "X86ISD::COMI";
11037 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11038 case X86ISD::SETCC: return "X86ISD::SETCC";
11039 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11040 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11041 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11042 case X86ISD::CMOV: return "X86ISD::CMOV";
11043 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11044 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11045 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11046 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11047 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11048 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11049 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11050 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11051 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11052 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11053 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11054 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11055 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11056 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11057 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11058 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11059 case X86ISD::HADD: return "X86ISD::HADD";
11060 case X86ISD::HSUB: return "X86ISD::HSUB";
11061 case X86ISD::FHADD: return "X86ISD::FHADD";
11062 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11063 case X86ISD::FMAX: return "X86ISD::FMAX";
11064 case X86ISD::FMIN: return "X86ISD::FMIN";
11065 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11066 case X86ISD::FRCP: return "X86ISD::FRCP";
11067 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11068 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11069 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11070 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11071 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11072 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11073 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11074 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11075 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11076 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11077 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11078 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11079 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11080 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11081 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11082 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11083 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11084 case X86ISD::VSHL: return "X86ISD::VSHL";
11085 case X86ISD::VSRL: return "X86ISD::VSRL";
11086 case X86ISD::VSRA: return "X86ISD::VSRA";
11087 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11088 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11089 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11090 case X86ISD::CMPP: return "X86ISD::CMPP";
11091 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11092 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11093 case X86ISD::ADD: return "X86ISD::ADD";
11094 case X86ISD::SUB: return "X86ISD::SUB";
11095 case X86ISD::ADC: return "X86ISD::ADC";
11096 case X86ISD::SBB: return "X86ISD::SBB";
11097 case X86ISD::SMUL: return "X86ISD::SMUL";
11098 case X86ISD::UMUL: return "X86ISD::UMUL";
11099 case X86ISD::INC: return "X86ISD::INC";
11100 case X86ISD::DEC: return "X86ISD::DEC";
11101 case X86ISD::OR: return "X86ISD::OR";
11102 case X86ISD::XOR: return "X86ISD::XOR";
11103 case X86ISD::AND: return "X86ISD::AND";
11104 case X86ISD::ANDN: return "X86ISD::ANDN";
11105 case X86ISD::BLSI: return "X86ISD::BLSI";
11106 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11107 case X86ISD::BLSR: return "X86ISD::BLSR";
11108 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11109 case X86ISD::PTEST: return "X86ISD::PTEST";
11110 case X86ISD::TESTP: return "X86ISD::TESTP";
11111 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11112 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11113 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11114 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11115 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11116 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11117 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11118 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11119 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11120 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11121 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11122 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11123 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11124 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11125 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11126 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11127 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11128 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11129 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11130 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11131 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11132 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11133 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11134 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11135 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11139 // isLegalAddressingMode - Return true if the addressing mode represented
11140 // by AM is legal for this target, for a load/store of the specified type.
11141 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11143 // X86 supports extremely general addressing modes.
11144 CodeModel::Model M = getTargetMachine().getCodeModel();
11145 Reloc::Model R = getTargetMachine().getRelocationModel();
11147 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11148 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11153 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11155 // If a reference to this global requires an extra load, we can't fold it.
11156 if (isGlobalStubReference(GVFlags))
11159 // If BaseGV requires a register for the PIC base, we cannot also have a
11160 // BaseReg specified.
11161 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11164 // If lower 4G is not available, then we must use rip-relative addressing.
11165 if ((M != CodeModel::Small || R != Reloc::Static) &&
11166 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11170 switch (AM.Scale) {
11176 // These scales always work.
11181 // These scales are formed with basereg+scalereg. Only accept if there is
11186 default: // Other stuff never works.
11194 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11195 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11197 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11198 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11199 if (NumBits1 <= NumBits2)
11204 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11205 if (!VT1.isInteger() || !VT2.isInteger())
11207 unsigned NumBits1 = VT1.getSizeInBits();
11208 unsigned NumBits2 = VT2.getSizeInBits();
11209 if (NumBits1 <= NumBits2)
11214 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11215 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11216 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11219 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11220 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11221 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11224 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11225 // i16 instructions are longer (0x66 prefix) and potentially slower.
11226 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11229 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11230 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11231 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11232 /// are assumed to be legal.
11234 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11236 // Very little shuffling can be done for 64-bit vectors right now.
11237 if (VT.getSizeInBits() == 64)
11240 // FIXME: pshufb, blends, shifts.
11241 return (VT.getVectorNumElements() == 2 ||
11242 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11243 isMOVLMask(M, VT) ||
11244 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11245 isPSHUFDMask(M, VT) ||
11246 isPSHUFHWMask(M, VT) ||
11247 isPSHUFLWMask(M, VT) ||
11248 isPALIGNRMask(M, VT, Subtarget) ||
11249 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11250 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11251 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11252 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11256 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11258 unsigned NumElts = VT.getVectorNumElements();
11259 // FIXME: This collection of masks seems suspect.
11262 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11263 return (isMOVLMask(Mask, VT) ||
11264 isCommutedMOVLMask(Mask, VT, true) ||
11265 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11266 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11271 //===----------------------------------------------------------------------===//
11272 // X86 Scheduler Hooks
11273 //===----------------------------------------------------------------------===//
11275 // private utility function
11276 MachineBasicBlock *
11277 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11278 MachineBasicBlock *MBB,
11285 TargetRegisterClass *RC,
11286 bool invSrc) const {
11287 // For the atomic bitwise operator, we generate
11290 // ld t1 = [bitinstr.addr]
11291 // op t2 = t1, [bitinstr.val]
11293 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11295 // fallthrough -->nextMBB
11296 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11297 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11298 MachineFunction::iterator MBBIter = MBB;
11301 /// First build the CFG
11302 MachineFunction *F = MBB->getParent();
11303 MachineBasicBlock *thisMBB = MBB;
11304 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11305 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11306 F->insert(MBBIter, newMBB);
11307 F->insert(MBBIter, nextMBB);
11309 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11310 nextMBB->splice(nextMBB->begin(), thisMBB,
11311 llvm::next(MachineBasicBlock::iterator(bInstr)),
11313 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11315 // Update thisMBB to fall through to newMBB
11316 thisMBB->addSuccessor(newMBB);
11318 // newMBB jumps to itself and fall through to nextMBB
11319 newMBB->addSuccessor(nextMBB);
11320 newMBB->addSuccessor(newMBB);
11322 // Insert instructions into newMBB based on incoming instruction
11323 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11324 "unexpected number of operands");
11325 DebugLoc dl = bInstr->getDebugLoc();
11326 MachineOperand& destOper = bInstr->getOperand(0);
11327 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11328 int numArgs = bInstr->getNumOperands() - 1;
11329 for (int i=0; i < numArgs; ++i)
11330 argOpers[i] = &bInstr->getOperand(i+1);
11332 // x86 address has 4 operands: base, index, scale, and displacement
11333 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11334 int valArgIndx = lastAddrIndx + 1;
11336 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11337 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11338 for (int i=0; i <= lastAddrIndx; ++i)
11339 (*MIB).addOperand(*argOpers[i]);
11341 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11343 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11348 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11349 assert((argOpers[valArgIndx]->isReg() ||
11350 argOpers[valArgIndx]->isImm()) &&
11351 "invalid operand");
11352 if (argOpers[valArgIndx]->isReg())
11353 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11355 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11357 (*MIB).addOperand(*argOpers[valArgIndx]);
11359 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11362 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11363 for (int i=0; i <= lastAddrIndx; ++i)
11364 (*MIB).addOperand(*argOpers[i]);
11366 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11367 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11368 bInstr->memoperands_end());
11370 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11371 MIB.addReg(EAXreg);
11374 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11376 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11380 // private utility function: 64 bit atomics on 32 bit host.
11381 MachineBasicBlock *
11382 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11383 MachineBasicBlock *MBB,
11388 bool invSrc) const {
11389 // For the atomic bitwise operator, we generate
11390 // thisMBB (instructions are in pairs, except cmpxchg8b)
11391 // ld t1,t2 = [bitinstr.addr]
11393 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11394 // op t5, t6 <- out1, out2, [bitinstr.val]
11395 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11396 // mov ECX, EBX <- t5, t6
11397 // mov EAX, EDX <- t1, t2
11398 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11399 // mov t3, t4 <- EAX, EDX
11401 // result in out1, out2
11402 // fallthrough -->nextMBB
11404 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11405 const unsigned LoadOpc = X86::MOV32rm;
11406 const unsigned NotOpc = X86::NOT32r;
11407 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11408 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11409 MachineFunction::iterator MBBIter = MBB;
11412 /// First build the CFG
11413 MachineFunction *F = MBB->getParent();
11414 MachineBasicBlock *thisMBB = MBB;
11415 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11416 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11417 F->insert(MBBIter, newMBB);
11418 F->insert(MBBIter, nextMBB);
11420 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11421 nextMBB->splice(nextMBB->begin(), thisMBB,
11422 llvm::next(MachineBasicBlock::iterator(bInstr)),
11424 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11426 // Update thisMBB to fall through to newMBB
11427 thisMBB->addSuccessor(newMBB);
11429 // newMBB jumps to itself and fall through to nextMBB
11430 newMBB->addSuccessor(nextMBB);
11431 newMBB->addSuccessor(newMBB);
11433 DebugLoc dl = bInstr->getDebugLoc();
11434 // Insert instructions into newMBB based on incoming instruction
11435 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11436 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11437 "unexpected number of operands");
11438 MachineOperand& dest1Oper = bInstr->getOperand(0);
11439 MachineOperand& dest2Oper = bInstr->getOperand(1);
11440 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11441 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11442 argOpers[i] = &bInstr->getOperand(i+2);
11444 // We use some of the operands multiple times, so conservatively just
11445 // clear any kill flags that might be present.
11446 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11447 argOpers[i]->setIsKill(false);
11450 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11451 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11453 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11454 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11455 for (int i=0; i <= lastAddrIndx; ++i)
11456 (*MIB).addOperand(*argOpers[i]);
11457 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11458 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11459 // add 4 to displacement.
11460 for (int i=0; i <= lastAddrIndx-2; ++i)
11461 (*MIB).addOperand(*argOpers[i]);
11462 MachineOperand newOp3 = *(argOpers[3]);
11463 if (newOp3.isImm())
11464 newOp3.setImm(newOp3.getImm()+4);
11466 newOp3.setOffset(newOp3.getOffset()+4);
11467 (*MIB).addOperand(newOp3);
11468 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11470 // t3/4 are defined later, at the bottom of the loop
11471 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11472 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11473 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11474 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11475 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11476 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11478 // The subsequent operations should be using the destination registers of
11479 //the PHI instructions.
11481 t1 = F->getRegInfo().createVirtualRegister(RC);
11482 t2 = F->getRegInfo().createVirtualRegister(RC);
11483 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11484 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11486 t1 = dest1Oper.getReg();
11487 t2 = dest2Oper.getReg();
11490 int valArgIndx = lastAddrIndx + 1;
11491 assert((argOpers[valArgIndx]->isReg() ||
11492 argOpers[valArgIndx]->isImm()) &&
11493 "invalid operand");
11494 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11495 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11496 if (argOpers[valArgIndx]->isReg())
11497 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11499 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11500 if (regOpcL != X86::MOV32rr)
11502 (*MIB).addOperand(*argOpers[valArgIndx]);
11503 assert(argOpers[valArgIndx + 1]->isReg() ==
11504 argOpers[valArgIndx]->isReg());
11505 assert(argOpers[valArgIndx + 1]->isImm() ==
11506 argOpers[valArgIndx]->isImm());
11507 if (argOpers[valArgIndx + 1]->isReg())
11508 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11510 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11511 if (regOpcH != X86::MOV32rr)
11513 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11515 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11517 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11520 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11522 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11525 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11526 for (int i=0; i <= lastAddrIndx; ++i)
11527 (*MIB).addOperand(*argOpers[i]);
11529 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11530 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11531 bInstr->memoperands_end());
11533 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11534 MIB.addReg(X86::EAX);
11535 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11536 MIB.addReg(X86::EDX);
11539 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11541 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11545 // private utility function
11546 MachineBasicBlock *
11547 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11548 MachineBasicBlock *MBB,
11549 unsigned cmovOpc) const {
11550 // For the atomic min/max operator, we generate
11553 // ld t1 = [min/max.addr]
11554 // mov t2 = [min/max.val]
11556 // cmov[cond] t2 = t1
11558 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11560 // fallthrough -->nextMBB
11562 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11563 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11564 MachineFunction::iterator MBBIter = MBB;
11567 /// First build the CFG
11568 MachineFunction *F = MBB->getParent();
11569 MachineBasicBlock *thisMBB = MBB;
11570 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11571 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11572 F->insert(MBBIter, newMBB);
11573 F->insert(MBBIter, nextMBB);
11575 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11576 nextMBB->splice(nextMBB->begin(), thisMBB,
11577 llvm::next(MachineBasicBlock::iterator(mInstr)),
11579 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11581 // Update thisMBB to fall through to newMBB
11582 thisMBB->addSuccessor(newMBB);
11584 // newMBB jumps to newMBB and fall through to nextMBB
11585 newMBB->addSuccessor(nextMBB);
11586 newMBB->addSuccessor(newMBB);
11588 DebugLoc dl = mInstr->getDebugLoc();
11589 // Insert instructions into newMBB based on incoming instruction
11590 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11591 "unexpected number of operands");
11592 MachineOperand& destOper = mInstr->getOperand(0);
11593 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11594 int numArgs = mInstr->getNumOperands() - 1;
11595 for (int i=0; i < numArgs; ++i)
11596 argOpers[i] = &mInstr->getOperand(i+1);
11598 // x86 address has 4 operands: base, index, scale, and displacement
11599 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11600 int valArgIndx = lastAddrIndx + 1;
11602 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11603 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11604 for (int i=0; i <= lastAddrIndx; ++i)
11605 (*MIB).addOperand(*argOpers[i]);
11607 // We only support register and immediate values
11608 assert((argOpers[valArgIndx]->isReg() ||
11609 argOpers[valArgIndx]->isImm()) &&
11610 "invalid operand");
11612 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11613 if (argOpers[valArgIndx]->isReg())
11614 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11616 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11617 (*MIB).addOperand(*argOpers[valArgIndx]);
11619 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11622 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11627 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11628 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11632 // Cmp and exchange if none has modified the memory location
11633 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11634 for (int i=0; i <= lastAddrIndx; ++i)
11635 (*MIB).addOperand(*argOpers[i]);
11637 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11638 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11639 mInstr->memoperands_end());
11641 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11642 MIB.addReg(X86::EAX);
11645 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11647 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11651 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11652 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11653 // in the .td file.
11654 MachineBasicBlock *
11655 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11656 unsigned numArgs, bool memArg) const {
11657 assert(Subtarget->hasSSE42() &&
11658 "Target must have SSE4.2 or AVX features enabled");
11660 DebugLoc dl = MI->getDebugLoc();
11661 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11663 if (!Subtarget->hasAVX()) {
11665 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11667 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11670 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11672 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11675 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11676 for (unsigned i = 0; i < numArgs; ++i) {
11677 MachineOperand &Op = MI->getOperand(i+1);
11678 if (!(Op.isReg() && Op.isImplicit()))
11679 MIB.addOperand(Op);
11681 BuildMI(*BB, MI, dl,
11682 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11683 MI->getOperand(0).getReg())
11684 .addReg(X86::XMM0);
11686 MI->eraseFromParent();
11690 MachineBasicBlock *
11691 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11692 DebugLoc dl = MI->getDebugLoc();
11693 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11695 // Address into RAX/EAX, other two args into ECX, EDX.
11696 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11697 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11698 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11699 for (int i = 0; i < X86::AddrNumOperands; ++i)
11700 MIB.addOperand(MI->getOperand(i));
11702 unsigned ValOps = X86::AddrNumOperands;
11703 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11704 .addReg(MI->getOperand(ValOps).getReg());
11705 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11706 .addReg(MI->getOperand(ValOps+1).getReg());
11708 // The instruction doesn't actually take any operands though.
11709 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11711 MI->eraseFromParent(); // The pseudo is gone now.
11715 MachineBasicBlock *
11716 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11717 DebugLoc dl = MI->getDebugLoc();
11718 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11720 // First arg in ECX, the second in EAX.
11721 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11722 .addReg(MI->getOperand(0).getReg());
11723 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11724 .addReg(MI->getOperand(1).getReg());
11726 // The instruction doesn't actually take any operands though.
11727 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11729 MI->eraseFromParent(); // The pseudo is gone now.
11733 MachineBasicBlock *
11734 X86TargetLowering::EmitVAARG64WithCustomInserter(
11736 MachineBasicBlock *MBB) const {
11737 // Emit va_arg instruction on X86-64.
11739 // Operands to this pseudo-instruction:
11740 // 0 ) Output : destination address (reg)
11741 // 1-5) Input : va_list address (addr, i64mem)
11742 // 6 ) ArgSize : Size (in bytes) of vararg type
11743 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11744 // 8 ) Align : Alignment of type
11745 // 9 ) EFLAGS (implicit-def)
11747 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11748 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11750 unsigned DestReg = MI->getOperand(0).getReg();
11751 MachineOperand &Base = MI->getOperand(1);
11752 MachineOperand &Scale = MI->getOperand(2);
11753 MachineOperand &Index = MI->getOperand(3);
11754 MachineOperand &Disp = MI->getOperand(4);
11755 MachineOperand &Segment = MI->getOperand(5);
11756 unsigned ArgSize = MI->getOperand(6).getImm();
11757 unsigned ArgMode = MI->getOperand(7).getImm();
11758 unsigned Align = MI->getOperand(8).getImm();
11760 // Memory Reference
11761 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11762 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11763 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11765 // Machine Information
11766 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11767 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11768 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11769 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11770 DebugLoc DL = MI->getDebugLoc();
11772 // struct va_list {
11775 // i64 overflow_area (address)
11776 // i64 reg_save_area (address)
11778 // sizeof(va_list) = 24
11779 // alignment(va_list) = 8
11781 unsigned TotalNumIntRegs = 6;
11782 unsigned TotalNumXMMRegs = 8;
11783 bool UseGPOffset = (ArgMode == 1);
11784 bool UseFPOffset = (ArgMode == 2);
11785 unsigned MaxOffset = TotalNumIntRegs * 8 +
11786 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11788 /* Align ArgSize to a multiple of 8 */
11789 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11790 bool NeedsAlign = (Align > 8);
11792 MachineBasicBlock *thisMBB = MBB;
11793 MachineBasicBlock *overflowMBB;
11794 MachineBasicBlock *offsetMBB;
11795 MachineBasicBlock *endMBB;
11797 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11798 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11799 unsigned OffsetReg = 0;
11801 if (!UseGPOffset && !UseFPOffset) {
11802 // If we only pull from the overflow region, we don't create a branch.
11803 // We don't need to alter control flow.
11804 OffsetDestReg = 0; // unused
11805 OverflowDestReg = DestReg;
11808 overflowMBB = thisMBB;
11811 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11812 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11813 // If not, pull from overflow_area. (branch to overflowMBB)
11818 // offsetMBB overflowMBB
11823 // Registers for the PHI in endMBB
11824 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11825 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11827 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11828 MachineFunction *MF = MBB->getParent();
11829 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11830 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11831 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11833 MachineFunction::iterator MBBIter = MBB;
11836 // Insert the new basic blocks
11837 MF->insert(MBBIter, offsetMBB);
11838 MF->insert(MBBIter, overflowMBB);
11839 MF->insert(MBBIter, endMBB);
11841 // Transfer the remainder of MBB and its successor edges to endMBB.
11842 endMBB->splice(endMBB->begin(), thisMBB,
11843 llvm::next(MachineBasicBlock::iterator(MI)),
11845 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11847 // Make offsetMBB and overflowMBB successors of thisMBB
11848 thisMBB->addSuccessor(offsetMBB);
11849 thisMBB->addSuccessor(overflowMBB);
11851 // endMBB is a successor of both offsetMBB and overflowMBB
11852 offsetMBB->addSuccessor(endMBB);
11853 overflowMBB->addSuccessor(endMBB);
11855 // Load the offset value into a register
11856 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11857 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11861 .addDisp(Disp, UseFPOffset ? 4 : 0)
11862 .addOperand(Segment)
11863 .setMemRefs(MMOBegin, MMOEnd);
11865 // Check if there is enough room left to pull this argument.
11866 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11868 .addImm(MaxOffset + 8 - ArgSizeA8);
11870 // Branch to "overflowMBB" if offset >= max
11871 // Fall through to "offsetMBB" otherwise
11872 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11873 .addMBB(overflowMBB);
11876 // In offsetMBB, emit code to use the reg_save_area.
11878 assert(OffsetReg != 0);
11880 // Read the reg_save_area address.
11881 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11882 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11887 .addOperand(Segment)
11888 .setMemRefs(MMOBegin, MMOEnd);
11890 // Zero-extend the offset
11891 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11892 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11895 .addImm(X86::sub_32bit);
11897 // Add the offset to the reg_save_area to get the final address.
11898 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11899 .addReg(OffsetReg64)
11900 .addReg(RegSaveReg);
11902 // Compute the offset for the next argument
11903 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11904 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11906 .addImm(UseFPOffset ? 16 : 8);
11908 // Store it back into the va_list.
11909 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11913 .addDisp(Disp, UseFPOffset ? 4 : 0)
11914 .addOperand(Segment)
11915 .addReg(NextOffsetReg)
11916 .setMemRefs(MMOBegin, MMOEnd);
11919 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11924 // Emit code to use overflow area
11927 // Load the overflow_area address into a register.
11928 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11929 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11934 .addOperand(Segment)
11935 .setMemRefs(MMOBegin, MMOEnd);
11937 // If we need to align it, do so. Otherwise, just copy the address
11938 // to OverflowDestReg.
11940 // Align the overflow address
11941 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11942 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11944 // aligned_addr = (addr + (align-1)) & ~(align-1)
11945 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11946 .addReg(OverflowAddrReg)
11949 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11951 .addImm(~(uint64_t)(Align-1));
11953 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11954 .addReg(OverflowAddrReg);
11957 // Compute the next overflow address after this argument.
11958 // (the overflow address should be kept 8-byte aligned)
11959 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11960 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11961 .addReg(OverflowDestReg)
11962 .addImm(ArgSizeA8);
11964 // Store the new overflow address.
11965 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11970 .addOperand(Segment)
11971 .addReg(NextAddrReg)
11972 .setMemRefs(MMOBegin, MMOEnd);
11974 // If we branched, emit the PHI to the front of endMBB.
11976 BuildMI(*endMBB, endMBB->begin(), DL,
11977 TII->get(X86::PHI), DestReg)
11978 .addReg(OffsetDestReg).addMBB(offsetMBB)
11979 .addReg(OverflowDestReg).addMBB(overflowMBB);
11982 // Erase the pseudo instruction
11983 MI->eraseFromParent();
11988 MachineBasicBlock *
11989 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11991 MachineBasicBlock *MBB) const {
11992 // Emit code to save XMM registers to the stack. The ABI says that the
11993 // number of registers to save is given in %al, so it's theoretically
11994 // possible to do an indirect jump trick to avoid saving all of them,
11995 // however this code takes a simpler approach and just executes all
11996 // of the stores if %al is non-zero. It's less code, and it's probably
11997 // easier on the hardware branch predictor, and stores aren't all that
11998 // expensive anyway.
12000 // Create the new basic blocks. One block contains all the XMM stores,
12001 // and one block is the final destination regardless of whether any
12002 // stores were performed.
12003 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12004 MachineFunction *F = MBB->getParent();
12005 MachineFunction::iterator MBBIter = MBB;
12007 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12008 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12009 F->insert(MBBIter, XMMSaveMBB);
12010 F->insert(MBBIter, EndMBB);
12012 // Transfer the remainder of MBB and its successor edges to EndMBB.
12013 EndMBB->splice(EndMBB->begin(), MBB,
12014 llvm::next(MachineBasicBlock::iterator(MI)),
12016 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12018 // The original block will now fall through to the XMM save block.
12019 MBB->addSuccessor(XMMSaveMBB);
12020 // The XMMSaveMBB will fall through to the end block.
12021 XMMSaveMBB->addSuccessor(EndMBB);
12023 // Now add the instructions.
12024 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12025 DebugLoc DL = MI->getDebugLoc();
12027 unsigned CountReg = MI->getOperand(0).getReg();
12028 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12029 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12031 if (!Subtarget->isTargetWin64()) {
12032 // If %al is 0, branch around the XMM save block.
12033 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12034 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12035 MBB->addSuccessor(EndMBB);
12038 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12039 // In the XMM save block, save all the XMM argument registers.
12040 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12041 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12042 MachineMemOperand *MMO =
12043 F->getMachineMemOperand(
12044 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12045 MachineMemOperand::MOStore,
12046 /*Size=*/16, /*Align=*/16);
12047 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12048 .addFrameIndex(RegSaveFrameIndex)
12049 .addImm(/*Scale=*/1)
12050 .addReg(/*IndexReg=*/0)
12051 .addImm(/*Disp=*/Offset)
12052 .addReg(/*Segment=*/0)
12053 .addReg(MI->getOperand(i).getReg())
12054 .addMemOperand(MMO);
12057 MI->eraseFromParent(); // The pseudo instruction is gone now.
12062 MachineBasicBlock *
12063 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12064 MachineBasicBlock *BB) const {
12065 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12066 DebugLoc DL = MI->getDebugLoc();
12068 // To "insert" a SELECT_CC instruction, we actually have to insert the
12069 // diamond control-flow pattern. The incoming instruction knows the
12070 // destination vreg to set, the condition code register to branch on, the
12071 // true/false values to select between, and a branch opcode to use.
12072 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12073 MachineFunction::iterator It = BB;
12079 // cmpTY ccX, r1, r2
12081 // fallthrough --> copy0MBB
12082 MachineBasicBlock *thisMBB = BB;
12083 MachineFunction *F = BB->getParent();
12084 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12085 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12086 F->insert(It, copy0MBB);
12087 F->insert(It, sinkMBB);
12089 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12090 // live into the sink and copy blocks.
12091 if (!MI->killsRegister(X86::EFLAGS)) {
12092 copy0MBB->addLiveIn(X86::EFLAGS);
12093 sinkMBB->addLiveIn(X86::EFLAGS);
12096 // Transfer the remainder of BB and its successor edges to sinkMBB.
12097 sinkMBB->splice(sinkMBB->begin(), BB,
12098 llvm::next(MachineBasicBlock::iterator(MI)),
12100 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12102 // Add the true and fallthrough blocks as its successors.
12103 BB->addSuccessor(copy0MBB);
12104 BB->addSuccessor(sinkMBB);
12106 // Create the conditional branch instruction.
12108 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12109 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12112 // %FalseValue = ...
12113 // # fallthrough to sinkMBB
12114 copy0MBB->addSuccessor(sinkMBB);
12117 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12119 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12120 TII->get(X86::PHI), MI->getOperand(0).getReg())
12121 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12122 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12124 MI->eraseFromParent(); // The pseudo instruction is gone now.
12128 MachineBasicBlock *
12129 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12130 bool Is64Bit) const {
12131 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12132 DebugLoc DL = MI->getDebugLoc();
12133 MachineFunction *MF = BB->getParent();
12134 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12136 assert(getTargetMachine().Options.EnableSegmentedStacks);
12138 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12139 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12142 // ... [Till the alloca]
12143 // If stacklet is not large enough, jump to mallocMBB
12146 // Allocate by subtracting from RSP
12147 // Jump to continueMBB
12150 // Allocate by call to runtime
12154 // [rest of original BB]
12157 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12158 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12159 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12161 MachineRegisterInfo &MRI = MF->getRegInfo();
12162 const TargetRegisterClass *AddrRegClass =
12163 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12165 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12166 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12167 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12168 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12169 sizeVReg = MI->getOperand(1).getReg(),
12170 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12172 MachineFunction::iterator MBBIter = BB;
12175 MF->insert(MBBIter, bumpMBB);
12176 MF->insert(MBBIter, mallocMBB);
12177 MF->insert(MBBIter, continueMBB);
12179 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12180 (MachineBasicBlock::iterator(MI)), BB->end());
12181 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12183 // Add code to the main basic block to check if the stack limit has been hit,
12184 // and if so, jump to mallocMBB otherwise to bumpMBB.
12185 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12186 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12187 .addReg(tmpSPVReg).addReg(sizeVReg);
12188 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12189 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12190 .addReg(SPLimitVReg);
12191 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12193 // bumpMBB simply decreases the stack pointer, since we know the current
12194 // stacklet has enough space.
12195 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12196 .addReg(SPLimitVReg);
12197 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12198 .addReg(SPLimitVReg);
12199 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12201 // Calls into a routine in libgcc to allocate more space from the heap.
12203 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12205 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12206 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12208 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12210 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12211 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12212 .addExternalSymbol("__morestack_allocate_stack_space");
12216 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12219 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12220 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12221 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12223 // Set up the CFG correctly.
12224 BB->addSuccessor(bumpMBB);
12225 BB->addSuccessor(mallocMBB);
12226 mallocMBB->addSuccessor(continueMBB);
12227 bumpMBB->addSuccessor(continueMBB);
12229 // Take care of the PHI nodes.
12230 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12231 MI->getOperand(0).getReg())
12232 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12233 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12235 // Delete the original pseudo instruction.
12236 MI->eraseFromParent();
12239 return continueMBB;
12242 MachineBasicBlock *
12243 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12244 MachineBasicBlock *BB) const {
12245 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12246 DebugLoc DL = MI->getDebugLoc();
12248 assert(!Subtarget->isTargetEnvMacho());
12250 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12251 // non-trivial part is impdef of ESP.
12253 if (Subtarget->isTargetWin64()) {
12254 if (Subtarget->isTargetCygMing()) {
12255 // ___chkstk(Mingw64):
12256 // Clobbers R10, R11, RAX and EFLAGS.
12258 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12259 .addExternalSymbol("___chkstk")
12260 .addReg(X86::RAX, RegState::Implicit)
12261 .addReg(X86::RSP, RegState::Implicit)
12262 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12263 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12264 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12266 // __chkstk(MSVCRT): does not update stack pointer.
12267 // Clobbers R10, R11 and EFLAGS.
12268 // FIXME: RAX(allocated size) might be reused and not killed.
12269 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12270 .addExternalSymbol("__chkstk")
12271 .addReg(X86::RAX, RegState::Implicit)
12272 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12273 // RAX has the offset to subtracted from RSP.
12274 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12279 const char *StackProbeSymbol =
12280 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12282 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12283 .addExternalSymbol(StackProbeSymbol)
12284 .addReg(X86::EAX, RegState::Implicit)
12285 .addReg(X86::ESP, RegState::Implicit)
12286 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12287 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12288 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12291 MI->eraseFromParent(); // The pseudo instruction is gone now.
12295 MachineBasicBlock *
12296 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12297 MachineBasicBlock *BB) const {
12298 // This is pretty easy. We're taking the value that we received from
12299 // our load from the relocation, sticking it in either RDI (x86-64)
12300 // or EAX and doing an indirect call. The return value will then
12301 // be in the normal return register.
12302 const X86InstrInfo *TII
12303 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12304 DebugLoc DL = MI->getDebugLoc();
12305 MachineFunction *F = BB->getParent();
12307 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12308 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12310 if (Subtarget->is64Bit()) {
12311 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12312 TII->get(X86::MOV64rm), X86::RDI)
12314 .addImm(0).addReg(0)
12315 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12316 MI->getOperand(3).getTargetFlags())
12318 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12319 addDirectMem(MIB, X86::RDI);
12320 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12321 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12322 TII->get(X86::MOV32rm), X86::EAX)
12324 .addImm(0).addReg(0)
12325 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12326 MI->getOperand(3).getTargetFlags())
12328 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12329 addDirectMem(MIB, X86::EAX);
12331 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12332 TII->get(X86::MOV32rm), X86::EAX)
12333 .addReg(TII->getGlobalBaseReg(F))
12334 .addImm(0).addReg(0)
12335 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12336 MI->getOperand(3).getTargetFlags())
12338 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12339 addDirectMem(MIB, X86::EAX);
12342 MI->eraseFromParent(); // The pseudo instruction is gone now.
12346 MachineBasicBlock *
12347 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12348 MachineBasicBlock *BB) const {
12349 switch (MI->getOpcode()) {
12350 default: assert(0 && "Unexpected instr type to insert");
12351 case X86::TAILJMPd64:
12352 case X86::TAILJMPr64:
12353 case X86::TAILJMPm64:
12354 assert(0 && "TAILJMP64 would not be touched here.");
12355 case X86::TCRETURNdi64:
12356 case X86::TCRETURNri64:
12357 case X86::TCRETURNmi64:
12358 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12359 // On AMD64, additional defs should be added before register allocation.
12360 if (!Subtarget->isTargetWin64()) {
12361 MI->addRegisterDefined(X86::RSI);
12362 MI->addRegisterDefined(X86::RDI);
12363 MI->addRegisterDefined(X86::XMM6);
12364 MI->addRegisterDefined(X86::XMM7);
12365 MI->addRegisterDefined(X86::XMM8);
12366 MI->addRegisterDefined(X86::XMM9);
12367 MI->addRegisterDefined(X86::XMM10);
12368 MI->addRegisterDefined(X86::XMM11);
12369 MI->addRegisterDefined(X86::XMM12);
12370 MI->addRegisterDefined(X86::XMM13);
12371 MI->addRegisterDefined(X86::XMM14);
12372 MI->addRegisterDefined(X86::XMM15);
12375 case X86::WIN_ALLOCA:
12376 return EmitLoweredWinAlloca(MI, BB);
12377 case X86::SEG_ALLOCA_32:
12378 return EmitLoweredSegAlloca(MI, BB, false);
12379 case X86::SEG_ALLOCA_64:
12380 return EmitLoweredSegAlloca(MI, BB, true);
12381 case X86::TLSCall_32:
12382 case X86::TLSCall_64:
12383 return EmitLoweredTLSCall(MI, BB);
12384 case X86::CMOV_GR8:
12385 case X86::CMOV_FR32:
12386 case X86::CMOV_FR64:
12387 case X86::CMOV_V4F32:
12388 case X86::CMOV_V2F64:
12389 case X86::CMOV_V2I64:
12390 case X86::CMOV_V8F32:
12391 case X86::CMOV_V4F64:
12392 case X86::CMOV_V4I64:
12393 case X86::CMOV_GR16:
12394 case X86::CMOV_GR32:
12395 case X86::CMOV_RFP32:
12396 case X86::CMOV_RFP64:
12397 case X86::CMOV_RFP80:
12398 return EmitLoweredSelect(MI, BB);
12400 case X86::FP32_TO_INT16_IN_MEM:
12401 case X86::FP32_TO_INT32_IN_MEM:
12402 case X86::FP32_TO_INT64_IN_MEM:
12403 case X86::FP64_TO_INT16_IN_MEM:
12404 case X86::FP64_TO_INT32_IN_MEM:
12405 case X86::FP64_TO_INT64_IN_MEM:
12406 case X86::FP80_TO_INT16_IN_MEM:
12407 case X86::FP80_TO_INT32_IN_MEM:
12408 case X86::FP80_TO_INT64_IN_MEM: {
12409 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12410 DebugLoc DL = MI->getDebugLoc();
12412 // Change the floating point control register to use "round towards zero"
12413 // mode when truncating to an integer value.
12414 MachineFunction *F = BB->getParent();
12415 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12416 addFrameReference(BuildMI(*BB, MI, DL,
12417 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12419 // Load the old value of the high byte of the control word...
12421 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12422 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12425 // Set the high part to be round to zero...
12426 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12429 // Reload the modified control word now...
12430 addFrameReference(BuildMI(*BB, MI, DL,
12431 TII->get(X86::FLDCW16m)), CWFrameIdx);
12433 // Restore the memory image of control word to original value
12434 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12437 // Get the X86 opcode to use.
12439 switch (MI->getOpcode()) {
12440 default: llvm_unreachable("illegal opcode!");
12441 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12442 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12443 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12444 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12445 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12446 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12447 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12448 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12449 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12453 MachineOperand &Op = MI->getOperand(0);
12455 AM.BaseType = X86AddressMode::RegBase;
12456 AM.Base.Reg = Op.getReg();
12458 AM.BaseType = X86AddressMode::FrameIndexBase;
12459 AM.Base.FrameIndex = Op.getIndex();
12461 Op = MI->getOperand(1);
12463 AM.Scale = Op.getImm();
12464 Op = MI->getOperand(2);
12466 AM.IndexReg = Op.getImm();
12467 Op = MI->getOperand(3);
12468 if (Op.isGlobal()) {
12469 AM.GV = Op.getGlobal();
12471 AM.Disp = Op.getImm();
12473 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12474 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12476 // Reload the original control word now.
12477 addFrameReference(BuildMI(*BB, MI, DL,
12478 TII->get(X86::FLDCW16m)), CWFrameIdx);
12480 MI->eraseFromParent(); // The pseudo instruction is gone now.
12483 // String/text processing lowering.
12484 case X86::PCMPISTRM128REG:
12485 case X86::VPCMPISTRM128REG:
12486 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12487 case X86::PCMPISTRM128MEM:
12488 case X86::VPCMPISTRM128MEM:
12489 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12490 case X86::PCMPESTRM128REG:
12491 case X86::VPCMPESTRM128REG:
12492 return EmitPCMP(MI, BB, 5, false /* in mem */);
12493 case X86::PCMPESTRM128MEM:
12494 case X86::VPCMPESTRM128MEM:
12495 return EmitPCMP(MI, BB, 5, true /* in mem */);
12497 // Thread synchronization.
12499 return EmitMonitor(MI, BB);
12501 return EmitMwait(MI, BB);
12503 // Atomic Lowering.
12504 case X86::ATOMAND32:
12505 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12506 X86::AND32ri, X86::MOV32rm,
12508 X86::NOT32r, X86::EAX,
12509 X86::GR32RegisterClass);
12510 case X86::ATOMOR32:
12511 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12512 X86::OR32ri, X86::MOV32rm,
12514 X86::NOT32r, X86::EAX,
12515 X86::GR32RegisterClass);
12516 case X86::ATOMXOR32:
12517 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12518 X86::XOR32ri, X86::MOV32rm,
12520 X86::NOT32r, X86::EAX,
12521 X86::GR32RegisterClass);
12522 case X86::ATOMNAND32:
12523 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12524 X86::AND32ri, X86::MOV32rm,
12526 X86::NOT32r, X86::EAX,
12527 X86::GR32RegisterClass, true);
12528 case X86::ATOMMIN32:
12529 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12530 case X86::ATOMMAX32:
12531 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12532 case X86::ATOMUMIN32:
12533 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12534 case X86::ATOMUMAX32:
12535 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12537 case X86::ATOMAND16:
12538 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12539 X86::AND16ri, X86::MOV16rm,
12541 X86::NOT16r, X86::AX,
12542 X86::GR16RegisterClass);
12543 case X86::ATOMOR16:
12544 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12545 X86::OR16ri, X86::MOV16rm,
12547 X86::NOT16r, X86::AX,
12548 X86::GR16RegisterClass);
12549 case X86::ATOMXOR16:
12550 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12551 X86::XOR16ri, X86::MOV16rm,
12553 X86::NOT16r, X86::AX,
12554 X86::GR16RegisterClass);
12555 case X86::ATOMNAND16:
12556 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12557 X86::AND16ri, X86::MOV16rm,
12559 X86::NOT16r, X86::AX,
12560 X86::GR16RegisterClass, true);
12561 case X86::ATOMMIN16:
12562 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12563 case X86::ATOMMAX16:
12564 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12565 case X86::ATOMUMIN16:
12566 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12567 case X86::ATOMUMAX16:
12568 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12570 case X86::ATOMAND8:
12571 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12572 X86::AND8ri, X86::MOV8rm,
12574 X86::NOT8r, X86::AL,
12575 X86::GR8RegisterClass);
12577 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12578 X86::OR8ri, X86::MOV8rm,
12580 X86::NOT8r, X86::AL,
12581 X86::GR8RegisterClass);
12582 case X86::ATOMXOR8:
12583 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12584 X86::XOR8ri, X86::MOV8rm,
12586 X86::NOT8r, X86::AL,
12587 X86::GR8RegisterClass);
12588 case X86::ATOMNAND8:
12589 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12590 X86::AND8ri, X86::MOV8rm,
12592 X86::NOT8r, X86::AL,
12593 X86::GR8RegisterClass, true);
12594 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12595 // This group is for 64-bit host.
12596 case X86::ATOMAND64:
12597 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12598 X86::AND64ri32, X86::MOV64rm,
12600 X86::NOT64r, X86::RAX,
12601 X86::GR64RegisterClass);
12602 case X86::ATOMOR64:
12603 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12604 X86::OR64ri32, X86::MOV64rm,
12606 X86::NOT64r, X86::RAX,
12607 X86::GR64RegisterClass);
12608 case X86::ATOMXOR64:
12609 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12610 X86::XOR64ri32, X86::MOV64rm,
12612 X86::NOT64r, X86::RAX,
12613 X86::GR64RegisterClass);
12614 case X86::ATOMNAND64:
12615 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12616 X86::AND64ri32, X86::MOV64rm,
12618 X86::NOT64r, X86::RAX,
12619 X86::GR64RegisterClass, true);
12620 case X86::ATOMMIN64:
12621 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12622 case X86::ATOMMAX64:
12623 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12624 case X86::ATOMUMIN64:
12625 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12626 case X86::ATOMUMAX64:
12627 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12629 // This group does 64-bit operations on a 32-bit host.
12630 case X86::ATOMAND6432:
12631 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12632 X86::AND32rr, X86::AND32rr,
12633 X86::AND32ri, X86::AND32ri,
12635 case X86::ATOMOR6432:
12636 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12637 X86::OR32rr, X86::OR32rr,
12638 X86::OR32ri, X86::OR32ri,
12640 case X86::ATOMXOR6432:
12641 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12642 X86::XOR32rr, X86::XOR32rr,
12643 X86::XOR32ri, X86::XOR32ri,
12645 case X86::ATOMNAND6432:
12646 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12647 X86::AND32rr, X86::AND32rr,
12648 X86::AND32ri, X86::AND32ri,
12650 case X86::ATOMADD6432:
12651 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12652 X86::ADD32rr, X86::ADC32rr,
12653 X86::ADD32ri, X86::ADC32ri,
12655 case X86::ATOMSUB6432:
12656 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12657 X86::SUB32rr, X86::SBB32rr,
12658 X86::SUB32ri, X86::SBB32ri,
12660 case X86::ATOMSWAP6432:
12661 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12662 X86::MOV32rr, X86::MOV32rr,
12663 X86::MOV32ri, X86::MOV32ri,
12665 case X86::VASTART_SAVE_XMM_REGS:
12666 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12668 case X86::VAARG_64:
12669 return EmitVAARG64WithCustomInserter(MI, BB);
12673 //===----------------------------------------------------------------------===//
12674 // X86 Optimization Hooks
12675 //===----------------------------------------------------------------------===//
12677 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12681 const SelectionDAG &DAG,
12682 unsigned Depth) const {
12683 unsigned Opc = Op.getOpcode();
12684 assert((Opc >= ISD::BUILTIN_OP_END ||
12685 Opc == ISD::INTRINSIC_WO_CHAIN ||
12686 Opc == ISD::INTRINSIC_W_CHAIN ||
12687 Opc == ISD::INTRINSIC_VOID) &&
12688 "Should use MaskedValueIsZero if you don't know whether Op"
12689 " is a target node!");
12691 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12705 // These nodes' second result is a boolean.
12706 if (Op.getResNo() == 0)
12709 case X86ISD::SETCC:
12710 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12711 Mask.getBitWidth() - 1);
12713 case ISD::INTRINSIC_WO_CHAIN: {
12714 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12715 unsigned NumLoBits = 0;
12718 case Intrinsic::x86_sse_movmsk_ps:
12719 case Intrinsic::x86_avx_movmsk_ps_256:
12720 case Intrinsic::x86_sse2_movmsk_pd:
12721 case Intrinsic::x86_avx_movmsk_pd_256:
12722 case Intrinsic::x86_mmx_pmovmskb:
12723 case Intrinsic::x86_sse2_pmovmskb_128:
12724 case Intrinsic::x86_avx2_pmovmskb: {
12725 // High bits of movmskp{s|d}, pmovmskb are known zero.
12727 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12728 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12729 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12730 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12731 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12732 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12733 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12735 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12736 Mask.getBitWidth() - NumLoBits);
12745 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12746 unsigned Depth) const {
12747 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12748 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12749 return Op.getValueType().getScalarType().getSizeInBits();
12755 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12756 /// node is a GlobalAddress + offset.
12757 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12758 const GlobalValue* &GA,
12759 int64_t &Offset) const {
12760 if (N->getOpcode() == X86ISD::Wrapper) {
12761 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12762 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12763 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12767 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12770 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12771 /// same as extracting the high 128-bit part of 256-bit vector and then
12772 /// inserting the result into the low part of a new 256-bit vector
12773 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12774 EVT VT = SVOp->getValueType(0);
12775 int NumElems = VT.getVectorNumElements();
12777 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12778 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12779 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12780 SVOp->getMaskElt(j) >= 0)
12786 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12787 /// same as extracting the low 128-bit part of 256-bit vector and then
12788 /// inserting the result into the high part of a new 256-bit vector
12789 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12790 EVT VT = SVOp->getValueType(0);
12791 int NumElems = VT.getVectorNumElements();
12793 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12794 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12795 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12796 SVOp->getMaskElt(j) >= 0)
12802 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12803 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12804 TargetLowering::DAGCombinerInfo &DCI,
12806 DebugLoc dl = N->getDebugLoc();
12807 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12808 SDValue V1 = SVOp->getOperand(0);
12809 SDValue V2 = SVOp->getOperand(1);
12810 EVT VT = SVOp->getValueType(0);
12811 int NumElems = VT.getVectorNumElements();
12813 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12814 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12818 // V UNDEF BUILD_VECTOR UNDEF
12820 // CONCAT_VECTOR CONCAT_VECTOR
12823 // RESULT: V + zero extended
12825 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12826 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12827 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12830 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12833 // To match the shuffle mask, the first half of the mask should
12834 // be exactly the first vector, and all the rest a splat with the
12835 // first element of the second one.
12836 for (int i = 0; i < NumElems/2; ++i)
12837 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12838 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12841 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12842 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12843 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12844 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12846 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12848 Ld->getPointerInfo(),
12849 Ld->getAlignment(),
12850 false/*isVolatile*/, true/*ReadMem*/,
12851 false/*WriteMem*/);
12852 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12855 // Emit a zeroed vector and insert the desired subvector on its
12857 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, HasAVX2, DAG, dl);
12858 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12859 DAG.getConstant(0, MVT::i32), DAG, dl);
12860 return DCI.CombineTo(N, InsV);
12863 //===--------------------------------------------------------------------===//
12864 // Combine some shuffles into subvector extracts and inserts:
12867 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12868 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12869 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12871 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12872 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12873 return DCI.CombineTo(N, InsV);
12876 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12877 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12878 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12879 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12880 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12881 return DCI.CombineTo(N, InsV);
12887 /// PerformShuffleCombine - Performs several different shuffle combines.
12888 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12889 TargetLowering::DAGCombinerInfo &DCI,
12890 const X86Subtarget *Subtarget) {
12891 DebugLoc dl = N->getDebugLoc();
12892 EVT VT = N->getValueType(0);
12894 // Don't create instructions with illegal types after legalize types has run.
12895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12896 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12899 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12900 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12901 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12902 return PerformShuffleCombine256(N, DAG, DCI, Subtarget->hasAVX2());
12904 // Only handle 128 wide vector from here on.
12905 if (VT.getSizeInBits() != 128)
12908 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12909 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12910 // consecutive, non-overlapping, and in the right order.
12911 SmallVector<SDValue, 16> Elts;
12912 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12913 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12915 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12919 /// PerformTruncateCombine - Converts truncate operation to
12920 /// a sequence of vector shuffle operations.
12921 /// It is possible when we truncate 256-bit vector to 128-bit vector
12923 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12924 DAGCombinerInfo &DCI) const {
12925 if (!DCI.isBeforeLegalizeOps())
12928 if (!Subtarget->hasAVX()) return SDValue();
12930 EVT VT = N->getValueType(0);
12931 SDValue Op = N->getOperand(0);
12932 EVT OpVT = Op.getValueType();
12933 DebugLoc dl = N->getDebugLoc();
12935 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
12937 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12938 DAG.getIntPtrConstant(0));
12940 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12941 DAG.getIntPtrConstant(2));
12943 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12944 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12947 int ShufMask1[] = {0, 2, 0, 0};
12949 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
12951 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
12955 int ShufMask2[] = {0, 1, 4, 5};
12957 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
12959 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
12961 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12962 DAG.getIntPtrConstant(0));
12964 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12965 DAG.getIntPtrConstant(4));
12967 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
12968 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
12971 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12972 -1, -1, -1, -1, -1, -1, -1, -1};
12974 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
12975 DAG.getUNDEF(MVT::v16i8),
12977 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
12978 DAG.getUNDEF(MVT::v16i8),
12981 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12982 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12985 int ShufMask2[] = {0, 1, 4, 5};
12987 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
12988 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
12994 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12995 /// generation and convert it from being a bunch of shuffles and extracts
12996 /// to a simple store and scalar loads to extract the elements.
12997 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12998 const TargetLowering &TLI) {
12999 SDValue InputVector = N->getOperand(0);
13001 // Only operate on vectors of 4 elements, where the alternative shuffling
13002 // gets to be more expensive.
13003 if (InputVector.getValueType() != MVT::v4i32)
13006 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13007 // single use which is a sign-extend or zero-extend, and all elements are
13009 SmallVector<SDNode *, 4> Uses;
13010 unsigned ExtractedElements = 0;
13011 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13012 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13013 if (UI.getUse().getResNo() != InputVector.getResNo())
13016 SDNode *Extract = *UI;
13017 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13020 if (Extract->getValueType(0) != MVT::i32)
13022 if (!Extract->hasOneUse())
13024 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13025 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13027 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13030 // Record which element was extracted.
13031 ExtractedElements |=
13032 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13034 Uses.push_back(Extract);
13037 // If not all the elements were used, this may not be worthwhile.
13038 if (ExtractedElements != 15)
13041 // Ok, we've now decided to do the transformation.
13042 DebugLoc dl = InputVector.getDebugLoc();
13044 // Store the value to a temporary stack slot.
13045 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13046 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13047 MachinePointerInfo(), false, false, 0);
13049 // Replace each use (extract) with a load of the appropriate element.
13050 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13051 UE = Uses.end(); UI != UE; ++UI) {
13052 SDNode *Extract = *UI;
13054 // cOMpute the element's address.
13055 SDValue Idx = Extract->getOperand(1);
13057 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13058 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13059 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13061 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13062 StackPtr, OffsetVal);
13064 // Load the scalar.
13065 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13066 ScalarAddr, MachinePointerInfo(),
13067 false, false, false, 0);
13069 // Replace the exact with the load.
13070 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13073 // The replacement was made in place; don't return anything.
13077 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13079 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13080 TargetLowering::DAGCombinerInfo &DCI,
13081 const X86Subtarget *Subtarget) {
13082 DebugLoc DL = N->getDebugLoc();
13083 SDValue Cond = N->getOperand(0);
13084 // Get the LHS/RHS of the select.
13085 SDValue LHS = N->getOperand(1);
13086 SDValue RHS = N->getOperand(2);
13087 EVT VT = LHS.getValueType();
13089 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13090 // instructions match the semantics of the common C idiom x<y?x:y but not
13091 // x<=y?x:y, because of how they handle negative zero (which can be
13092 // ignored in unsafe-math mode).
13093 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13094 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13095 (Subtarget->hasSSE2() ||
13096 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13097 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13099 unsigned Opcode = 0;
13100 // Check for x CC y ? x : y.
13101 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13102 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13106 // Converting this to a min would handle NaNs incorrectly, and swapping
13107 // the operands would cause it to handle comparisons between positive
13108 // and negative zero incorrectly.
13109 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13110 if (!DAG.getTarget().Options.UnsafeFPMath &&
13111 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13113 std::swap(LHS, RHS);
13115 Opcode = X86ISD::FMIN;
13118 // Converting this to a min would handle comparisons between positive
13119 // and negative zero incorrectly.
13120 if (!DAG.getTarget().Options.UnsafeFPMath &&
13121 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13123 Opcode = X86ISD::FMIN;
13126 // Converting this to a min would handle both negative zeros and NaNs
13127 // incorrectly, but we can swap the operands to fix both.
13128 std::swap(LHS, RHS);
13132 Opcode = X86ISD::FMIN;
13136 // Converting this to a max would handle comparisons between positive
13137 // and negative zero incorrectly.
13138 if (!DAG.getTarget().Options.UnsafeFPMath &&
13139 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13141 Opcode = X86ISD::FMAX;
13144 // Converting this to a max would handle NaNs incorrectly, and swapping
13145 // the operands would cause it to handle comparisons between positive
13146 // and negative zero incorrectly.
13147 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13148 if (!DAG.getTarget().Options.UnsafeFPMath &&
13149 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13151 std::swap(LHS, RHS);
13153 Opcode = X86ISD::FMAX;
13156 // Converting this to a max would handle both negative zeros and NaNs
13157 // incorrectly, but we can swap the operands to fix both.
13158 std::swap(LHS, RHS);
13162 Opcode = X86ISD::FMAX;
13165 // Check for x CC y ? y : x -- a min/max with reversed arms.
13166 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13167 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13171 // Converting this to a min would handle comparisons between positive
13172 // and negative zero incorrectly, and swapping the operands would
13173 // cause it to handle NaNs incorrectly.
13174 if (!DAG.getTarget().Options.UnsafeFPMath &&
13175 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13176 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13178 std::swap(LHS, RHS);
13180 Opcode = X86ISD::FMIN;
13183 // Converting this to a min would handle NaNs incorrectly.
13184 if (!DAG.getTarget().Options.UnsafeFPMath &&
13185 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13187 Opcode = X86ISD::FMIN;
13190 // Converting this to a min would handle both negative zeros and NaNs
13191 // incorrectly, but we can swap the operands to fix both.
13192 std::swap(LHS, RHS);
13196 Opcode = X86ISD::FMIN;
13200 // Converting this to a max would handle NaNs incorrectly.
13201 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13203 Opcode = X86ISD::FMAX;
13206 // Converting this to a max would handle comparisons between positive
13207 // and negative zero incorrectly, and swapping the operands would
13208 // cause it to handle NaNs incorrectly.
13209 if (!DAG.getTarget().Options.UnsafeFPMath &&
13210 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13211 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13213 std::swap(LHS, RHS);
13215 Opcode = X86ISD::FMAX;
13218 // Converting this to a max would handle both negative zeros and NaNs
13219 // incorrectly, but we can swap the operands to fix both.
13220 std::swap(LHS, RHS);
13224 Opcode = X86ISD::FMAX;
13230 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13233 // If this is a select between two integer constants, try to do some
13235 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13236 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13237 // Don't do this for crazy integer types.
13238 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13239 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13240 // so that TrueC (the true value) is larger than FalseC.
13241 bool NeedsCondInvert = false;
13243 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13244 // Efficiently invertible.
13245 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13246 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13247 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13248 NeedsCondInvert = true;
13249 std::swap(TrueC, FalseC);
13252 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13253 if (FalseC->getAPIntValue() == 0 &&
13254 TrueC->getAPIntValue().isPowerOf2()) {
13255 if (NeedsCondInvert) // Invert the condition if needed.
13256 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13257 DAG.getConstant(1, Cond.getValueType()));
13259 // Zero extend the condition if needed.
13260 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13262 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13263 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13264 DAG.getConstant(ShAmt, MVT::i8));
13267 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13268 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13269 if (NeedsCondInvert) // Invert the condition if needed.
13270 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13271 DAG.getConstant(1, Cond.getValueType()));
13273 // Zero extend the condition if needed.
13274 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13275 FalseC->getValueType(0), Cond);
13276 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13277 SDValue(FalseC, 0));
13280 // Optimize cases that will turn into an LEA instruction. This requires
13281 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13282 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13283 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13284 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13286 bool isFastMultiplier = false;
13288 switch ((unsigned char)Diff) {
13290 case 1: // result = add base, cond
13291 case 2: // result = lea base( , cond*2)
13292 case 3: // result = lea base(cond, cond*2)
13293 case 4: // result = lea base( , cond*4)
13294 case 5: // result = lea base(cond, cond*4)
13295 case 8: // result = lea base( , cond*8)
13296 case 9: // result = lea base(cond, cond*8)
13297 isFastMultiplier = true;
13302 if (isFastMultiplier) {
13303 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13304 if (NeedsCondInvert) // Invert the condition if needed.
13305 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13306 DAG.getConstant(1, Cond.getValueType()));
13308 // Zero extend the condition if needed.
13309 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13311 // Scale the condition by the difference.
13313 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13314 DAG.getConstant(Diff, Cond.getValueType()));
13316 // Add the base if non-zero.
13317 if (FalseC->getAPIntValue() != 0)
13318 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13319 SDValue(FalseC, 0));
13326 // Canonicalize max and min:
13327 // (x > y) ? x : y -> (x >= y) ? x : y
13328 // (x < y) ? x : y -> (x <= y) ? x : y
13329 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13330 // the need for an extra compare
13331 // against zero. e.g.
13332 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13334 // testl %edi, %edi
13336 // cmovgl %edi, %eax
13340 // cmovsl %eax, %edi
13341 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13342 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13343 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13344 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13349 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13350 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13351 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13352 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13357 // If we know that this node is legal then we know that it is going to be
13358 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13359 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13360 // to simplify previous instructions.
13361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13362 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13363 !DCI.isBeforeLegalize() &&
13364 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13365 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13366 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13367 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13369 APInt KnownZero, KnownOne;
13370 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13371 DCI.isBeforeLegalizeOps());
13372 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13373 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13374 DCI.CommitTargetLoweringOpt(TLO);
13380 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13381 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13382 TargetLowering::DAGCombinerInfo &DCI) {
13383 DebugLoc DL = N->getDebugLoc();
13385 // If the flag operand isn't dead, don't touch this CMOV.
13386 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13389 SDValue FalseOp = N->getOperand(0);
13390 SDValue TrueOp = N->getOperand(1);
13391 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13392 SDValue Cond = N->getOperand(3);
13393 if (CC == X86::COND_E || CC == X86::COND_NE) {
13394 switch (Cond.getOpcode()) {
13398 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13399 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13400 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13404 // If this is a select between two integer constants, try to do some
13405 // optimizations. Note that the operands are ordered the opposite of SELECT
13407 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13408 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13409 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13410 // larger than FalseC (the false value).
13411 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13412 CC = X86::GetOppositeBranchCondition(CC);
13413 std::swap(TrueC, FalseC);
13416 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13417 // This is efficient for any integer data type (including i8/i16) and
13419 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13420 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13421 DAG.getConstant(CC, MVT::i8), Cond);
13423 // Zero extend the condition if needed.
13424 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13426 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13427 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13428 DAG.getConstant(ShAmt, MVT::i8));
13429 if (N->getNumValues() == 2) // Dead flag value?
13430 return DCI.CombineTo(N, Cond, SDValue());
13434 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13435 // for any integer data type, including i8/i16.
13436 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13437 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13438 DAG.getConstant(CC, MVT::i8), Cond);
13440 // Zero extend the condition if needed.
13441 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13442 FalseC->getValueType(0), Cond);
13443 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13444 SDValue(FalseC, 0));
13446 if (N->getNumValues() == 2) // Dead flag value?
13447 return DCI.CombineTo(N, Cond, SDValue());
13451 // Optimize cases that will turn into an LEA instruction. This requires
13452 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13453 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13454 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13455 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13457 bool isFastMultiplier = false;
13459 switch ((unsigned char)Diff) {
13461 case 1: // result = add base, cond
13462 case 2: // result = lea base( , cond*2)
13463 case 3: // result = lea base(cond, cond*2)
13464 case 4: // result = lea base( , cond*4)
13465 case 5: // result = lea base(cond, cond*4)
13466 case 8: // result = lea base( , cond*8)
13467 case 9: // result = lea base(cond, cond*8)
13468 isFastMultiplier = true;
13473 if (isFastMultiplier) {
13474 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13475 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13476 DAG.getConstant(CC, MVT::i8), Cond);
13477 // Zero extend the condition if needed.
13478 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13480 // Scale the condition by the difference.
13482 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13483 DAG.getConstant(Diff, Cond.getValueType()));
13485 // Add the base if non-zero.
13486 if (FalseC->getAPIntValue() != 0)
13487 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13488 SDValue(FalseC, 0));
13489 if (N->getNumValues() == 2) // Dead flag value?
13490 return DCI.CombineTo(N, Cond, SDValue());
13500 /// PerformMulCombine - Optimize a single multiply with constant into two
13501 /// in order to implement it with two cheaper instructions, e.g.
13502 /// LEA + SHL, LEA + LEA.
13503 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13504 TargetLowering::DAGCombinerInfo &DCI) {
13505 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13508 EVT VT = N->getValueType(0);
13509 if (VT != MVT::i64)
13512 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13515 uint64_t MulAmt = C->getZExtValue();
13516 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13519 uint64_t MulAmt1 = 0;
13520 uint64_t MulAmt2 = 0;
13521 if ((MulAmt % 9) == 0) {
13523 MulAmt2 = MulAmt / 9;
13524 } else if ((MulAmt % 5) == 0) {
13526 MulAmt2 = MulAmt / 5;
13527 } else if ((MulAmt % 3) == 0) {
13529 MulAmt2 = MulAmt / 3;
13532 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13533 DebugLoc DL = N->getDebugLoc();
13535 if (isPowerOf2_64(MulAmt2) &&
13536 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13537 // If second multiplifer is pow2, issue it first. We want the multiply by
13538 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13540 std::swap(MulAmt1, MulAmt2);
13543 if (isPowerOf2_64(MulAmt1))
13544 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13545 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13547 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13548 DAG.getConstant(MulAmt1, VT));
13550 if (isPowerOf2_64(MulAmt2))
13551 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13552 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13554 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13555 DAG.getConstant(MulAmt2, VT));
13557 // Do not add new nodes to DAG combiner worklist.
13558 DCI.CombineTo(N, NewMul, false);
13563 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13564 SDValue N0 = N->getOperand(0);
13565 SDValue N1 = N->getOperand(1);
13566 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13567 EVT VT = N0.getValueType();
13569 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13570 // since the result of setcc_c is all zero's or all ones.
13571 if (VT.isInteger() && !VT.isVector() &&
13572 N1C && N0.getOpcode() == ISD::AND &&
13573 N0.getOperand(1).getOpcode() == ISD::Constant) {
13574 SDValue N00 = N0.getOperand(0);
13575 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13576 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13577 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13578 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13579 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13580 APInt ShAmt = N1C->getAPIntValue();
13581 Mask = Mask.shl(ShAmt);
13583 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13584 N00, DAG.getConstant(Mask, VT));
13589 // Hardware support for vector shifts is sparse which makes us scalarize the
13590 // vector operations in many cases. Also, on sandybridge ADD is faster than
13592 // (shl V, 1) -> add V,V
13593 if (isSplatVector(N1.getNode())) {
13594 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13595 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13596 // We shift all of the values by one. In many cases we do not have
13597 // hardware support for this operation. This is better expressed as an ADD
13599 if (N1C && (1 == N1C->getZExtValue())) {
13600 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13607 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13609 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13610 TargetLowering::DAGCombinerInfo &DCI,
13611 const X86Subtarget *Subtarget) {
13612 EVT VT = N->getValueType(0);
13613 if (N->getOpcode() == ISD::SHL) {
13614 SDValue V = PerformSHLCombine(N, DAG);
13615 if (V.getNode()) return V;
13618 // On X86 with SSE2 support, we can transform this to a vector shift if
13619 // all elements are shifted by the same amount. We can't do this in legalize
13620 // because the a constant vector is typically transformed to a constant pool
13621 // so we have no knowledge of the shift amount.
13622 if (!Subtarget->hasSSE2())
13625 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13626 (!Subtarget->hasAVX2() ||
13627 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13630 SDValue ShAmtOp = N->getOperand(1);
13631 EVT EltVT = VT.getVectorElementType();
13632 DebugLoc DL = N->getDebugLoc();
13633 SDValue BaseShAmt = SDValue();
13634 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13635 unsigned NumElts = VT.getVectorNumElements();
13637 for (; i != NumElts; ++i) {
13638 SDValue Arg = ShAmtOp.getOperand(i);
13639 if (Arg.getOpcode() == ISD::UNDEF) continue;
13643 // Handle the case where the build_vector is all undef
13644 // FIXME: Should DAG allow this?
13648 for (; i != NumElts; ++i) {
13649 SDValue Arg = ShAmtOp.getOperand(i);
13650 if (Arg.getOpcode() == ISD::UNDEF) continue;
13651 if (Arg != BaseShAmt) {
13655 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13656 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13657 SDValue InVec = ShAmtOp.getOperand(0);
13658 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13659 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13661 for (; i != NumElts; ++i) {
13662 SDValue Arg = InVec.getOperand(i);
13663 if (Arg.getOpcode() == ISD::UNDEF) continue;
13667 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13668 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13669 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13670 if (C->getZExtValue() == SplatIdx)
13671 BaseShAmt = InVec.getOperand(1);
13674 if (BaseShAmt.getNode() == 0) {
13675 // Don't create instructions with illegal types after legalize
13677 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13678 !DCI.isBeforeLegalize())
13681 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13682 DAG.getIntPtrConstant(0));
13687 // The shift amount is an i32.
13688 if (EltVT.bitsGT(MVT::i32))
13689 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13690 else if (EltVT.bitsLT(MVT::i32))
13691 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13693 // The shift amount is identical so we can do a vector shift.
13694 SDValue ValOp = N->getOperand(0);
13695 switch (N->getOpcode()) {
13697 llvm_unreachable("Unknown shift opcode!");
13699 switch (VT.getSimpleVT().SimpleTy) {
13700 default: return SDValue();
13707 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13710 switch (VT.getSimpleVT().SimpleTy) {
13711 default: return SDValue();
13716 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13719 switch (VT.getSimpleVT().SimpleTy) {
13720 default: return SDValue();
13727 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13733 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13734 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13735 // and friends. Likewise for OR -> CMPNEQSS.
13736 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13737 TargetLowering::DAGCombinerInfo &DCI,
13738 const X86Subtarget *Subtarget) {
13741 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13742 // we're requiring SSE2 for both.
13743 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13744 SDValue N0 = N->getOperand(0);
13745 SDValue N1 = N->getOperand(1);
13746 SDValue CMP0 = N0->getOperand(1);
13747 SDValue CMP1 = N1->getOperand(1);
13748 DebugLoc DL = N->getDebugLoc();
13750 // The SETCCs should both refer to the same CMP.
13751 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13754 SDValue CMP00 = CMP0->getOperand(0);
13755 SDValue CMP01 = CMP0->getOperand(1);
13756 EVT VT = CMP00.getValueType();
13758 if (VT == MVT::f32 || VT == MVT::f64) {
13759 bool ExpectingFlags = false;
13760 // Check for any users that want flags:
13761 for (SDNode::use_iterator UI = N->use_begin(),
13763 !ExpectingFlags && UI != UE; ++UI)
13764 switch (UI->getOpcode()) {
13769 ExpectingFlags = true;
13771 case ISD::CopyToReg:
13772 case ISD::SIGN_EXTEND:
13773 case ISD::ZERO_EXTEND:
13774 case ISD::ANY_EXTEND:
13778 if (!ExpectingFlags) {
13779 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13780 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13782 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13783 X86::CondCode tmp = cc0;
13788 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13789 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13790 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13791 X86ISD::NodeType NTOperator = is64BitFP ?
13792 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13793 // FIXME: need symbolic constants for these magic numbers.
13794 // See X86ATTInstPrinter.cpp:printSSECC().
13795 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13796 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13797 DAG.getConstant(x86cc, MVT::i8));
13798 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13800 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13801 DAG.getConstant(1, MVT::i32));
13802 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13803 return OneBitOfTruth;
13811 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13812 /// so it can be folded inside ANDNP.
13813 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13814 EVT VT = N->getValueType(0);
13816 // Match direct AllOnes for 128 and 256-bit vectors
13817 if (ISD::isBuildVectorAllOnes(N))
13820 // Look through a bit convert.
13821 if (N->getOpcode() == ISD::BITCAST)
13822 N = N->getOperand(0).getNode();
13824 // Sometimes the operand may come from a insert_subvector building a 256-bit
13826 if (VT.getSizeInBits() == 256 &&
13827 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13828 SDValue V1 = N->getOperand(0);
13829 SDValue V2 = N->getOperand(1);
13831 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13832 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13833 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13834 ISD::isBuildVectorAllOnes(V2.getNode()))
13841 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13842 TargetLowering::DAGCombinerInfo &DCI,
13843 const X86Subtarget *Subtarget) {
13844 if (DCI.isBeforeLegalizeOps())
13847 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13851 EVT VT = N->getValueType(0);
13853 // Create ANDN, BLSI, and BLSR instructions
13854 // BLSI is X & (-X)
13855 // BLSR is X & (X-1)
13856 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13857 SDValue N0 = N->getOperand(0);
13858 SDValue N1 = N->getOperand(1);
13859 DebugLoc DL = N->getDebugLoc();
13861 // Check LHS for not
13862 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13863 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13864 // Check RHS for not
13865 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13866 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13868 // Check LHS for neg
13869 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13870 isZero(N0.getOperand(0)))
13871 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13873 // Check RHS for neg
13874 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13875 isZero(N1.getOperand(0)))
13876 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13878 // Check LHS for X-1
13879 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13880 isAllOnes(N0.getOperand(1)))
13881 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13883 // Check RHS for X-1
13884 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13885 isAllOnes(N1.getOperand(1)))
13886 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13891 // Want to form ANDNP nodes:
13892 // 1) In the hopes of then easily combining them with OR and AND nodes
13893 // to form PBLEND/PSIGN.
13894 // 2) To match ANDN packed intrinsics
13895 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13898 SDValue N0 = N->getOperand(0);
13899 SDValue N1 = N->getOperand(1);
13900 DebugLoc DL = N->getDebugLoc();
13902 // Check LHS for vnot
13903 if (N0.getOpcode() == ISD::XOR &&
13904 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13905 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13906 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13908 // Check RHS for vnot
13909 if (N1.getOpcode() == ISD::XOR &&
13910 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13911 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13912 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13917 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13918 TargetLowering::DAGCombinerInfo &DCI,
13919 const X86Subtarget *Subtarget) {
13920 if (DCI.isBeforeLegalizeOps())
13923 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13927 EVT VT = N->getValueType(0);
13929 SDValue N0 = N->getOperand(0);
13930 SDValue N1 = N->getOperand(1);
13932 // look for psign/blend
13933 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13934 if (!Subtarget->hasSSSE3() ||
13935 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13938 // Canonicalize pandn to RHS
13939 if (N0.getOpcode() == X86ISD::ANDNP)
13941 // or (and (m, y), (pandn m, x))
13942 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13943 SDValue Mask = N1.getOperand(0);
13944 SDValue X = N1.getOperand(1);
13946 if (N0.getOperand(0) == Mask)
13947 Y = N0.getOperand(1);
13948 if (N0.getOperand(1) == Mask)
13949 Y = N0.getOperand(0);
13951 // Check to see if the mask appeared in both the AND and ANDNP and
13955 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13956 if (Mask.getOpcode() != ISD::BITCAST ||
13957 X.getOpcode() != ISD::BITCAST ||
13958 Y.getOpcode() != ISD::BITCAST)
13961 // Look through mask bitcast.
13962 Mask = Mask.getOperand(0);
13963 EVT MaskVT = Mask.getValueType();
13965 // Validate that the Mask operand is a vector sra node.
13966 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13967 // there is no psrai.b
13968 if (Mask.getOpcode() != X86ISD::VSRAI)
13971 // Check that the SRA is all signbits.
13972 SDValue SraC = Mask.getOperand(1);
13973 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13974 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13975 if ((SraAmt + 1) != EltBits)
13978 DebugLoc DL = N->getDebugLoc();
13980 // Now we know we at least have a plendvb with the mask val. See if
13981 // we can form a psignb/w/d.
13982 // psign = x.type == y.type == mask.type && y = sub(0, x);
13983 X = X.getOperand(0);
13984 Y = Y.getOperand(0);
13985 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13986 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13987 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
13988 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
13989 "Unsupported VT for PSIGN");
13990 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
13991 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13993 // PBLENDVB only available on SSE 4.1
13994 if (!Subtarget->hasSSE41())
13997 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13999 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14000 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14001 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14002 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14003 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14007 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14010 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14011 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14013 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14015 if (!N0.hasOneUse() || !N1.hasOneUse())
14018 SDValue ShAmt0 = N0.getOperand(1);
14019 if (ShAmt0.getValueType() != MVT::i8)
14021 SDValue ShAmt1 = N1.getOperand(1);
14022 if (ShAmt1.getValueType() != MVT::i8)
14024 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14025 ShAmt0 = ShAmt0.getOperand(0);
14026 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14027 ShAmt1 = ShAmt1.getOperand(0);
14029 DebugLoc DL = N->getDebugLoc();
14030 unsigned Opc = X86ISD::SHLD;
14031 SDValue Op0 = N0.getOperand(0);
14032 SDValue Op1 = N1.getOperand(0);
14033 if (ShAmt0.getOpcode() == ISD::SUB) {
14034 Opc = X86ISD::SHRD;
14035 std::swap(Op0, Op1);
14036 std::swap(ShAmt0, ShAmt1);
14039 unsigned Bits = VT.getSizeInBits();
14040 if (ShAmt1.getOpcode() == ISD::SUB) {
14041 SDValue Sum = ShAmt1.getOperand(0);
14042 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14043 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14044 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14045 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14046 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14047 return DAG.getNode(Opc, DL, VT,
14049 DAG.getNode(ISD::TRUNCATE, DL,
14052 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14053 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14055 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14056 return DAG.getNode(Opc, DL, VT,
14057 N0.getOperand(0), N1.getOperand(0),
14058 DAG.getNode(ISD::TRUNCATE, DL,
14065 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14066 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14067 TargetLowering::DAGCombinerInfo &DCI,
14068 const X86Subtarget *Subtarget) {
14069 if (DCI.isBeforeLegalizeOps())
14072 EVT VT = N->getValueType(0);
14074 if (VT != MVT::i32 && VT != MVT::i64)
14077 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14079 // Create BLSMSK instructions by finding X ^ (X-1)
14080 SDValue N0 = N->getOperand(0);
14081 SDValue N1 = N->getOperand(1);
14082 DebugLoc DL = N->getDebugLoc();
14084 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14085 isAllOnes(N0.getOperand(1)))
14086 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14088 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14089 isAllOnes(N1.getOperand(1)))
14090 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14095 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14096 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14097 const X86Subtarget *Subtarget) {
14098 LoadSDNode *Ld = cast<LoadSDNode>(N);
14099 EVT RegVT = Ld->getValueType(0);
14100 EVT MemVT = Ld->getMemoryVT();
14101 DebugLoc dl = Ld->getDebugLoc();
14102 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14104 ISD::LoadExtType Ext = Ld->getExtensionType();
14106 // If this is a vector EXT Load then attempt to optimize it using a
14107 // shuffle. We need SSE4 for the shuffles.
14108 // TODO: It is possible to support ZExt by zeroing the undef values
14109 // during the shuffle phase or after the shuffle.
14110 if (RegVT.isVector() && RegVT.isInteger() &&
14111 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14112 assert(MemVT != RegVT && "Cannot extend to the same type");
14113 assert(MemVT.isVector() && "Must load a vector from memory");
14115 unsigned NumElems = RegVT.getVectorNumElements();
14116 unsigned RegSz = RegVT.getSizeInBits();
14117 unsigned MemSz = MemVT.getSizeInBits();
14118 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14119 // All sizes must be a power of two
14120 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14122 // Attempt to load the original value using a single load op.
14123 // Find a scalar type which is equal to the loaded word size.
14124 MVT SclrLoadTy = MVT::i8;
14125 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14126 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14127 MVT Tp = (MVT::SimpleValueType)tp;
14128 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14134 // Proceed if a load word is found.
14135 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14137 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14138 RegSz/SclrLoadTy.getSizeInBits());
14140 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14141 RegSz/MemVT.getScalarType().getSizeInBits());
14142 // Can't shuffle using an illegal type.
14143 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14145 // Perform a single load.
14146 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14148 Ld->getPointerInfo(), Ld->isVolatile(),
14149 Ld->isNonTemporal(), Ld->isInvariant(),
14150 Ld->getAlignment());
14152 // Insert the word loaded into a vector.
14153 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14154 LoadUnitVecVT, ScalarLoad);
14156 // Bitcast the loaded value to a vector of the original element type, in
14157 // the size of the target vector type.
14158 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14160 unsigned SizeRatio = RegSz/MemSz;
14162 // Redistribute the loaded elements into the different locations.
14163 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14164 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14166 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14167 DAG.getUNDEF(SlicedVec.getValueType()),
14168 ShuffleVec.data());
14170 // Bitcast to the requested type.
14171 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14172 // Replace the original load with the new sequence
14173 // and return the new chain.
14174 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14175 return SDValue(ScalarLoad.getNode(), 1);
14181 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14182 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14183 const X86Subtarget *Subtarget) {
14184 StoreSDNode *St = cast<StoreSDNode>(N);
14185 EVT VT = St->getValue().getValueType();
14186 EVT StVT = St->getMemoryVT();
14187 DebugLoc dl = St->getDebugLoc();
14188 SDValue StoredVal = St->getOperand(1);
14189 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14191 // If we are saving a concatenation of two XMM registers, perform two stores.
14192 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14193 // 128-bit ones. If in the future the cost becomes only one memory access the
14194 // first version would be better.
14195 if (VT.getSizeInBits() == 256 &&
14196 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14197 StoredVal.getNumOperands() == 2) {
14199 SDValue Value0 = StoredVal.getOperand(0);
14200 SDValue Value1 = StoredVal.getOperand(1);
14202 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14203 SDValue Ptr0 = St->getBasePtr();
14204 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14206 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14207 St->getPointerInfo(), St->isVolatile(),
14208 St->isNonTemporal(), St->getAlignment());
14209 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14210 St->getPointerInfo(), St->isVolatile(),
14211 St->isNonTemporal(), St->getAlignment());
14212 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14215 // Optimize trunc store (of multiple scalars) to shuffle and store.
14216 // First, pack all of the elements in one place. Next, store to memory
14217 // in fewer chunks.
14218 if (St->isTruncatingStore() && VT.isVector()) {
14219 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14220 unsigned NumElems = VT.getVectorNumElements();
14221 assert(StVT != VT && "Cannot truncate to the same type");
14222 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14223 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14225 // From, To sizes and ElemCount must be pow of two
14226 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14227 // We are going to use the original vector elt for storing.
14228 // Accumulated smaller vector elements must be a multiple of the store size.
14229 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14231 unsigned SizeRatio = FromSz / ToSz;
14233 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14235 // Create a type on which we perform the shuffle
14236 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14237 StVT.getScalarType(), NumElems*SizeRatio);
14239 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14241 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14242 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14243 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14245 // Can't shuffle using an illegal type
14246 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14248 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14249 DAG.getUNDEF(WideVec.getValueType()),
14250 ShuffleVec.data());
14251 // At this point all of the data is stored at the bottom of the
14252 // register. We now need to save it to mem.
14254 // Find the largest store unit
14255 MVT StoreType = MVT::i8;
14256 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14257 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14258 MVT Tp = (MVT::SimpleValueType)tp;
14259 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14263 // Bitcast the original vector into a vector of store-size units
14264 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14265 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14266 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14267 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14268 SmallVector<SDValue, 8> Chains;
14269 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14270 TLI.getPointerTy());
14271 SDValue Ptr = St->getBasePtr();
14273 // Perform one or more big stores into memory.
14274 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14275 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14276 StoreType, ShuffWide,
14277 DAG.getIntPtrConstant(i));
14278 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14279 St->getPointerInfo(), St->isVolatile(),
14280 St->isNonTemporal(), St->getAlignment());
14281 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14282 Chains.push_back(Ch);
14285 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14290 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14291 // the FP state in cases where an emms may be missing.
14292 // A preferable solution to the general problem is to figure out the right
14293 // places to insert EMMS. This qualifies as a quick hack.
14295 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14296 if (VT.getSizeInBits() != 64)
14299 const Function *F = DAG.getMachineFunction().getFunction();
14300 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14301 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14302 && Subtarget->hasSSE2();
14303 if ((VT.isVector() ||
14304 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14305 isa<LoadSDNode>(St->getValue()) &&
14306 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14307 St->getChain().hasOneUse() && !St->isVolatile()) {
14308 SDNode* LdVal = St->getValue().getNode();
14309 LoadSDNode *Ld = 0;
14310 int TokenFactorIndex = -1;
14311 SmallVector<SDValue, 8> Ops;
14312 SDNode* ChainVal = St->getChain().getNode();
14313 // Must be a store of a load. We currently handle two cases: the load
14314 // is a direct child, and it's under an intervening TokenFactor. It is
14315 // possible to dig deeper under nested TokenFactors.
14316 if (ChainVal == LdVal)
14317 Ld = cast<LoadSDNode>(St->getChain());
14318 else if (St->getValue().hasOneUse() &&
14319 ChainVal->getOpcode() == ISD::TokenFactor) {
14320 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14321 if (ChainVal->getOperand(i).getNode() == LdVal) {
14322 TokenFactorIndex = i;
14323 Ld = cast<LoadSDNode>(St->getValue());
14325 Ops.push_back(ChainVal->getOperand(i));
14329 if (!Ld || !ISD::isNormalLoad(Ld))
14332 // If this is not the MMX case, i.e. we are just turning i64 load/store
14333 // into f64 load/store, avoid the transformation if there are multiple
14334 // uses of the loaded value.
14335 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14338 DebugLoc LdDL = Ld->getDebugLoc();
14339 DebugLoc StDL = N->getDebugLoc();
14340 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14341 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14343 if (Subtarget->is64Bit() || F64IsLegal) {
14344 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14345 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14346 Ld->getPointerInfo(), Ld->isVolatile(),
14347 Ld->isNonTemporal(), Ld->isInvariant(),
14348 Ld->getAlignment());
14349 SDValue NewChain = NewLd.getValue(1);
14350 if (TokenFactorIndex != -1) {
14351 Ops.push_back(NewChain);
14352 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14355 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14356 St->getPointerInfo(),
14357 St->isVolatile(), St->isNonTemporal(),
14358 St->getAlignment());
14361 // Otherwise, lower to two pairs of 32-bit loads / stores.
14362 SDValue LoAddr = Ld->getBasePtr();
14363 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14364 DAG.getConstant(4, MVT::i32));
14366 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14367 Ld->getPointerInfo(),
14368 Ld->isVolatile(), Ld->isNonTemporal(),
14369 Ld->isInvariant(), Ld->getAlignment());
14370 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14371 Ld->getPointerInfo().getWithOffset(4),
14372 Ld->isVolatile(), Ld->isNonTemporal(),
14374 MinAlign(Ld->getAlignment(), 4));
14376 SDValue NewChain = LoLd.getValue(1);
14377 if (TokenFactorIndex != -1) {
14378 Ops.push_back(LoLd);
14379 Ops.push_back(HiLd);
14380 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14384 LoAddr = St->getBasePtr();
14385 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14386 DAG.getConstant(4, MVT::i32));
14388 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14389 St->getPointerInfo(),
14390 St->isVolatile(), St->isNonTemporal(),
14391 St->getAlignment());
14392 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14393 St->getPointerInfo().getWithOffset(4),
14395 St->isNonTemporal(),
14396 MinAlign(St->getAlignment(), 4));
14397 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14402 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14403 /// and return the operands for the horizontal operation in LHS and RHS. A
14404 /// horizontal operation performs the binary operation on successive elements
14405 /// of its first operand, then on successive elements of its second operand,
14406 /// returning the resulting values in a vector. For example, if
14407 /// A = < float a0, float a1, float a2, float a3 >
14409 /// B = < float b0, float b1, float b2, float b3 >
14410 /// then the result of doing a horizontal operation on A and B is
14411 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14412 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14413 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14414 /// set to A, RHS to B, and the routine returns 'true'.
14415 /// Note that the binary operation should have the property that if one of the
14416 /// operands is UNDEF then the result is UNDEF.
14417 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14418 // Look for the following pattern: if
14419 // A = < float a0, float a1, float a2, float a3 >
14420 // B = < float b0, float b1, float b2, float b3 >
14422 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14423 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14424 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14425 // which is A horizontal-op B.
14427 // At least one of the operands should be a vector shuffle.
14428 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14429 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14432 EVT VT = LHS.getValueType();
14434 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14435 "Unsupported vector type for horizontal add/sub");
14437 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14438 // operate independently on 128-bit lanes.
14439 unsigned NumElts = VT.getVectorNumElements();
14440 unsigned NumLanes = VT.getSizeInBits()/128;
14441 unsigned NumLaneElts = NumElts / NumLanes;
14442 assert((NumLaneElts % 2 == 0) &&
14443 "Vector type should have an even number of elements in each lane");
14444 unsigned HalfLaneElts = NumLaneElts/2;
14446 // View LHS in the form
14447 // LHS = VECTOR_SHUFFLE A, B, LMask
14448 // If LHS is not a shuffle then pretend it is the shuffle
14449 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14450 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14453 SmallVector<int, 16> LMask(NumElts);
14454 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14455 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14456 A = LHS.getOperand(0);
14457 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14458 B = LHS.getOperand(1);
14459 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14460 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14462 if (LHS.getOpcode() != ISD::UNDEF)
14464 for (unsigned i = 0; i != NumElts; ++i)
14468 // Likewise, view RHS in the form
14469 // RHS = VECTOR_SHUFFLE C, D, RMask
14471 SmallVector<int, 16> RMask(NumElts);
14472 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14473 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14474 C = RHS.getOperand(0);
14475 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14476 D = RHS.getOperand(1);
14477 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14478 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14480 if (RHS.getOpcode() != ISD::UNDEF)
14482 for (unsigned i = 0; i != NumElts; ++i)
14486 // Check that the shuffles are both shuffling the same vectors.
14487 if (!(A == C && B == D) && !(A == D && B == C))
14490 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14491 if (!A.getNode() && !B.getNode())
14494 // If A and B occur in reverse order in RHS, then "swap" them (which means
14495 // rewriting the mask).
14497 CommuteVectorShuffleMask(RMask, NumElts);
14499 // At this point LHS and RHS are equivalent to
14500 // LHS = VECTOR_SHUFFLE A, B, LMask
14501 // RHS = VECTOR_SHUFFLE A, B, RMask
14502 // Check that the masks correspond to performing a horizontal operation.
14503 for (unsigned i = 0; i != NumElts; ++i) {
14504 int LIdx = LMask[i], RIdx = RMask[i];
14506 // Ignore any UNDEF components.
14507 if (LIdx < 0 || RIdx < 0 ||
14508 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14509 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14512 // Check that successive elements are being operated on. If not, this is
14513 // not a horizontal operation.
14514 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14515 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14516 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14517 if (!(LIdx == Index && RIdx == Index + 1) &&
14518 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14522 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14523 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14527 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14528 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14529 const X86Subtarget *Subtarget) {
14530 EVT VT = N->getValueType(0);
14531 SDValue LHS = N->getOperand(0);
14532 SDValue RHS = N->getOperand(1);
14534 // Try to synthesize horizontal adds from adds of shuffles.
14535 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14536 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14537 isHorizontalBinOp(LHS, RHS, true))
14538 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14542 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14543 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14544 const X86Subtarget *Subtarget) {
14545 EVT VT = N->getValueType(0);
14546 SDValue LHS = N->getOperand(0);
14547 SDValue RHS = N->getOperand(1);
14549 // Try to synthesize horizontal subs from subs of shuffles.
14550 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14551 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14552 isHorizontalBinOp(LHS, RHS, false))
14553 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14557 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14558 /// X86ISD::FXOR nodes.
14559 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14560 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14561 // F[X]OR(0.0, x) -> x
14562 // F[X]OR(x, 0.0) -> x
14563 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14564 if (C->getValueAPF().isPosZero())
14565 return N->getOperand(1);
14566 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14567 if (C->getValueAPF().isPosZero())
14568 return N->getOperand(0);
14572 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14573 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14574 // FAND(0.0, x) -> 0.0
14575 // FAND(x, 0.0) -> 0.0
14576 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14577 if (C->getValueAPF().isPosZero())
14578 return N->getOperand(0);
14579 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14580 if (C->getValueAPF().isPosZero())
14581 return N->getOperand(1);
14585 static SDValue PerformBTCombine(SDNode *N,
14587 TargetLowering::DAGCombinerInfo &DCI) {
14588 // BT ignores high bits in the bit index operand.
14589 SDValue Op1 = N->getOperand(1);
14590 if (Op1.hasOneUse()) {
14591 unsigned BitWidth = Op1.getValueSizeInBits();
14592 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14593 APInt KnownZero, KnownOne;
14594 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14595 !DCI.isBeforeLegalizeOps());
14596 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14597 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14598 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14599 DCI.CommitTargetLoweringOpt(TLO);
14604 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14605 SDValue Op = N->getOperand(0);
14606 if (Op.getOpcode() == ISD::BITCAST)
14607 Op = Op.getOperand(0);
14608 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14609 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14610 VT.getVectorElementType().getSizeInBits() ==
14611 OpVT.getVectorElementType().getSizeInBits()) {
14612 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14617 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14618 const X86Subtarget *Subtarget) {
14619 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14620 // (and (i32 x86isd::setcc_carry), 1)
14621 // This eliminates the zext. This transformation is necessary because
14622 // ISD::SETCC is always legalized to i8.
14623 DebugLoc dl = N->getDebugLoc();
14624 SDValue N0 = N->getOperand(0);
14625 EVT VT = N->getValueType(0);
14626 EVT OpVT = N0.getValueType();
14628 if (N0.getOpcode() == ISD::AND &&
14630 N0.getOperand(0).hasOneUse()) {
14631 SDValue N00 = N0.getOperand(0);
14632 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14634 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14635 if (!C || C->getZExtValue() != 1)
14637 return DAG.getNode(ISD::AND, dl, VT,
14638 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14639 N00.getOperand(0), N00.getOperand(1)),
14640 DAG.getConstant(1, VT));
14642 // Optimize vectors in AVX mode:
14645 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14646 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14647 // Concat upper and lower parts.
14650 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14651 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14652 // Concat upper and lower parts.
14654 if (Subtarget->hasAVX()) {
14656 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14657 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14659 SDValue ZeroVec = getZeroVector(OpVT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
14661 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14662 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14664 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14665 VT.getVectorNumElements()/2);
14667 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14668 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14670 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14678 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14679 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14680 unsigned X86CC = N->getConstantOperandVal(0);
14681 SDValue EFLAG = N->getOperand(1);
14682 DebugLoc DL = N->getDebugLoc();
14684 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14685 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14687 if (X86CC == X86::COND_B)
14688 return DAG.getNode(ISD::AND, DL, MVT::i8,
14689 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14690 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14691 DAG.getConstant(1, MVT::i8));
14696 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14697 const X86TargetLowering *XTLI) {
14698 SDValue Op0 = N->getOperand(0);
14699 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14700 // a 32-bit target where SSE doesn't support i64->FP operations.
14701 if (Op0.getOpcode() == ISD::LOAD) {
14702 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14703 EVT VT = Ld->getValueType(0);
14704 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14705 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14706 !XTLI->getSubtarget()->is64Bit() &&
14707 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14708 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14709 Ld->getChain(), Op0, DAG);
14710 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14717 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14718 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14719 X86TargetLowering::DAGCombinerInfo &DCI) {
14720 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14721 // the result is either zero or one (depending on the input carry bit).
14722 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14723 if (X86::isZeroNode(N->getOperand(0)) &&
14724 X86::isZeroNode(N->getOperand(1)) &&
14725 // We don't have a good way to replace an EFLAGS use, so only do this when
14727 SDValue(N, 1).use_empty()) {
14728 DebugLoc DL = N->getDebugLoc();
14729 EVT VT = N->getValueType(0);
14730 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14731 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14732 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14733 DAG.getConstant(X86::COND_B,MVT::i8),
14735 DAG.getConstant(1, VT));
14736 return DCI.CombineTo(N, Res1, CarryOut);
14742 // fold (add Y, (sete X, 0)) -> adc 0, Y
14743 // (add Y, (setne X, 0)) -> sbb -1, Y
14744 // (sub (sete X, 0), Y) -> sbb 0, Y
14745 // (sub (setne X, 0), Y) -> adc -1, Y
14746 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14747 DebugLoc DL = N->getDebugLoc();
14749 // Look through ZExts.
14750 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14751 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14754 SDValue SetCC = Ext.getOperand(0);
14755 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14758 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14759 if (CC != X86::COND_E && CC != X86::COND_NE)
14762 SDValue Cmp = SetCC.getOperand(1);
14763 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14764 !X86::isZeroNode(Cmp.getOperand(1)) ||
14765 !Cmp.getOperand(0).getValueType().isInteger())
14768 SDValue CmpOp0 = Cmp.getOperand(0);
14769 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14770 DAG.getConstant(1, CmpOp0.getValueType()));
14772 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14773 if (CC == X86::COND_NE)
14774 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14775 DL, OtherVal.getValueType(), OtherVal,
14776 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14777 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14778 DL, OtherVal.getValueType(), OtherVal,
14779 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14782 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14783 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14784 const X86Subtarget *Subtarget) {
14785 EVT VT = N->getValueType(0);
14786 SDValue Op0 = N->getOperand(0);
14787 SDValue Op1 = N->getOperand(1);
14789 // Try to synthesize horizontal adds from adds of shuffles.
14790 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14791 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14792 isHorizontalBinOp(Op0, Op1, true))
14793 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14795 return OptimizeConditionalInDecrement(N, DAG);
14798 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14799 const X86Subtarget *Subtarget) {
14800 SDValue Op0 = N->getOperand(0);
14801 SDValue Op1 = N->getOperand(1);
14803 // X86 can't encode an immediate LHS of a sub. See if we can push the
14804 // negation into a preceding instruction.
14805 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14806 // If the RHS of the sub is a XOR with one use and a constant, invert the
14807 // immediate. Then add one to the LHS of the sub so we can turn
14808 // X-Y -> X+~Y+1, saving one register.
14809 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14810 isa<ConstantSDNode>(Op1.getOperand(1))) {
14811 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14812 EVT VT = Op0.getValueType();
14813 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14815 DAG.getConstant(~XorC, VT));
14816 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14817 DAG.getConstant(C->getAPIntValue()+1, VT));
14821 // Try to synthesize horizontal adds from adds of shuffles.
14822 EVT VT = N->getValueType(0);
14823 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14824 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14825 isHorizontalBinOp(Op0, Op1, true))
14826 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14828 return OptimizeConditionalInDecrement(N, DAG);
14831 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14832 DAGCombinerInfo &DCI) const {
14833 SelectionDAG &DAG = DCI.DAG;
14834 switch (N->getOpcode()) {
14836 case ISD::EXTRACT_VECTOR_ELT:
14837 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14839 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14840 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14841 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14842 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14843 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14844 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14847 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
14848 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14849 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14850 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14851 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14852 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14853 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14854 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14855 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14857 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14858 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14859 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14860 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14861 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
14862 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
14863 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14864 case X86ISD::SHUFP: // Handle all target specific shuffles
14865 case X86ISD::PALIGN:
14866 case X86ISD::UNPCKH:
14867 case X86ISD::UNPCKL:
14868 case X86ISD::MOVHLPS:
14869 case X86ISD::MOVLHPS:
14870 case X86ISD::PSHUFD:
14871 case X86ISD::PSHUFHW:
14872 case X86ISD::PSHUFLW:
14873 case X86ISD::MOVSS:
14874 case X86ISD::MOVSD:
14875 case X86ISD::VPERMILP:
14876 case X86ISD::VPERM2X128:
14877 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14883 /// isTypeDesirableForOp - Return true if the target has native support for
14884 /// the specified value type and it is 'desirable' to use the type for the
14885 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14886 /// instruction encodings are longer and some i16 instructions are slow.
14887 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14888 if (!isTypeLegal(VT))
14890 if (VT != MVT::i16)
14897 case ISD::SIGN_EXTEND:
14898 case ISD::ZERO_EXTEND:
14899 case ISD::ANY_EXTEND:
14912 /// IsDesirableToPromoteOp - This method query the target whether it is
14913 /// beneficial for dag combiner to promote the specified node. If true, it
14914 /// should return the desired promotion type by reference.
14915 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14916 EVT VT = Op.getValueType();
14917 if (VT != MVT::i16)
14920 bool Promote = false;
14921 bool Commute = false;
14922 switch (Op.getOpcode()) {
14925 LoadSDNode *LD = cast<LoadSDNode>(Op);
14926 // If the non-extending load has a single use and it's not live out, then it
14927 // might be folded.
14928 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14929 Op.hasOneUse()*/) {
14930 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14931 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14932 // The only case where we'd want to promote LOAD (rather then it being
14933 // promoted as an operand is when it's only use is liveout.
14934 if (UI->getOpcode() != ISD::CopyToReg)
14941 case ISD::SIGN_EXTEND:
14942 case ISD::ZERO_EXTEND:
14943 case ISD::ANY_EXTEND:
14948 SDValue N0 = Op.getOperand(0);
14949 // Look out for (store (shl (load), x)).
14950 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14963 SDValue N0 = Op.getOperand(0);
14964 SDValue N1 = Op.getOperand(1);
14965 if (!Commute && MayFoldLoad(N1))
14967 // Avoid disabling potential load folding opportunities.
14968 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14970 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14980 //===----------------------------------------------------------------------===//
14981 // X86 Inline Assembly Support
14982 //===----------------------------------------------------------------------===//
14985 // Helper to match a string separated by whitespace.
14986 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
14987 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
14989 for (unsigned i = 0, e = args.size(); i != e; ++i) {
14990 StringRef piece(*args[i]);
14991 if (!s.startswith(piece)) // Check if the piece matches.
14994 s = s.substr(piece.size());
14995 StringRef::size_type pos = s.find_first_not_of(" \t");
14996 if (pos == 0) // We matched a prefix.
15004 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15007 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15008 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15010 std::string AsmStr = IA->getAsmString();
15012 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15013 if (!Ty || Ty->getBitWidth() % 16 != 0)
15016 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15017 SmallVector<StringRef, 4> AsmPieces;
15018 SplitString(AsmStr, AsmPieces, ";\n");
15020 switch (AsmPieces.size()) {
15021 default: return false;
15023 // FIXME: this should verify that we are targeting a 486 or better. If not,
15024 // we will turn this bswap into something that will be lowered to logical
15025 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15026 // lower so don't worry about this.
15028 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15029 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15030 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15031 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15032 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15033 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15034 // No need to check constraints, nothing other than the equivalent of
15035 // "=r,0" would be valid here.
15036 return IntrinsicLowering::LowerToByteSwap(CI);
15039 // rorw $$8, ${0:w} --> llvm.bswap.i16
15040 if (CI->getType()->isIntegerTy(16) &&
15041 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15042 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15043 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15045 const std::string &ConstraintsStr = IA->getConstraintString();
15046 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15047 std::sort(AsmPieces.begin(), AsmPieces.end());
15048 if (AsmPieces.size() == 4 &&
15049 AsmPieces[0] == "~{cc}" &&
15050 AsmPieces[1] == "~{dirflag}" &&
15051 AsmPieces[2] == "~{flags}" &&
15052 AsmPieces[3] == "~{fpsr}")
15053 return IntrinsicLowering::LowerToByteSwap(CI);
15057 if (CI->getType()->isIntegerTy(32) &&
15058 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15059 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15060 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15061 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15063 const std::string &ConstraintsStr = IA->getConstraintString();
15064 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15065 std::sort(AsmPieces.begin(), AsmPieces.end());
15066 if (AsmPieces.size() == 4 &&
15067 AsmPieces[0] == "~{cc}" &&
15068 AsmPieces[1] == "~{dirflag}" &&
15069 AsmPieces[2] == "~{flags}" &&
15070 AsmPieces[3] == "~{fpsr}")
15071 return IntrinsicLowering::LowerToByteSwap(CI);
15074 if (CI->getType()->isIntegerTy(64)) {
15075 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15076 if (Constraints.size() >= 2 &&
15077 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15078 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15079 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15080 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15081 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15082 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15083 return IntrinsicLowering::LowerToByteSwap(CI);
15093 /// getConstraintType - Given a constraint letter, return the type of
15094 /// constraint it is for this target.
15095 X86TargetLowering::ConstraintType
15096 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15097 if (Constraint.size() == 1) {
15098 switch (Constraint[0]) {
15109 return C_RegisterClass;
15133 return TargetLowering::getConstraintType(Constraint);
15136 /// Examine constraint type and operand type and determine a weight value.
15137 /// This object must already have been set up with the operand type
15138 /// and the current alternative constraint selected.
15139 TargetLowering::ConstraintWeight
15140 X86TargetLowering::getSingleConstraintMatchWeight(
15141 AsmOperandInfo &info, const char *constraint) const {
15142 ConstraintWeight weight = CW_Invalid;
15143 Value *CallOperandVal = info.CallOperandVal;
15144 // If we don't have a value, we can't do a match,
15145 // but allow it at the lowest weight.
15146 if (CallOperandVal == NULL)
15148 Type *type = CallOperandVal->getType();
15149 // Look at the constraint type.
15150 switch (*constraint) {
15152 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15163 if (CallOperandVal->getType()->isIntegerTy())
15164 weight = CW_SpecificReg;
15169 if (type->isFloatingPointTy())
15170 weight = CW_SpecificReg;
15173 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15174 weight = CW_SpecificReg;
15178 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15179 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15180 weight = CW_Register;
15183 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15184 if (C->getZExtValue() <= 31)
15185 weight = CW_Constant;
15189 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15190 if (C->getZExtValue() <= 63)
15191 weight = CW_Constant;
15195 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15196 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15197 weight = CW_Constant;
15201 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15202 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15203 weight = CW_Constant;
15207 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15208 if (C->getZExtValue() <= 3)
15209 weight = CW_Constant;
15213 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15214 if (C->getZExtValue() <= 0xff)
15215 weight = CW_Constant;
15220 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15221 weight = CW_Constant;
15225 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15226 if ((C->getSExtValue() >= -0x80000000LL) &&
15227 (C->getSExtValue() <= 0x7fffffffLL))
15228 weight = CW_Constant;
15232 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15233 if (C->getZExtValue() <= 0xffffffff)
15234 weight = CW_Constant;
15241 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15242 /// with another that has more specific requirements based on the type of the
15243 /// corresponding operand.
15244 const char *X86TargetLowering::
15245 LowerXConstraint(EVT ConstraintVT) const {
15246 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15247 // 'f' like normal targets.
15248 if (ConstraintVT.isFloatingPoint()) {
15249 if (Subtarget->hasSSE2())
15251 if (Subtarget->hasSSE1())
15255 return TargetLowering::LowerXConstraint(ConstraintVT);
15258 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15259 /// vector. If it is invalid, don't add anything to Ops.
15260 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15261 std::string &Constraint,
15262 std::vector<SDValue>&Ops,
15263 SelectionDAG &DAG) const {
15264 SDValue Result(0, 0);
15266 // Only support length 1 constraints for now.
15267 if (Constraint.length() > 1) return;
15269 char ConstraintLetter = Constraint[0];
15270 switch (ConstraintLetter) {
15273 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15274 if (C->getZExtValue() <= 31) {
15275 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15281 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15282 if (C->getZExtValue() <= 63) {
15283 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15289 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15290 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15291 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15298 if (C->getZExtValue() <= 255) {
15299 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15305 // 32-bit signed value
15306 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15307 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15308 C->getSExtValue())) {
15309 // Widen to 64 bits here to get it sign extended.
15310 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15313 // FIXME gcc accepts some relocatable values here too, but only in certain
15314 // memory models; it's complicated.
15319 // 32-bit unsigned value
15320 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15321 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15322 C->getZExtValue())) {
15323 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15327 // FIXME gcc accepts some relocatable values here too, but only in certain
15328 // memory models; it's complicated.
15332 // Literal immediates are always ok.
15333 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15334 // Widen to 64 bits here to get it sign extended.
15335 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15339 // In any sort of PIC mode addresses need to be computed at runtime by
15340 // adding in a register or some sort of table lookup. These can't
15341 // be used as immediates.
15342 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15345 // If we are in non-pic codegen mode, we allow the address of a global (with
15346 // an optional displacement) to be used with 'i'.
15347 GlobalAddressSDNode *GA = 0;
15348 int64_t Offset = 0;
15350 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15352 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15353 Offset += GA->getOffset();
15355 } else if (Op.getOpcode() == ISD::ADD) {
15356 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15357 Offset += C->getZExtValue();
15358 Op = Op.getOperand(0);
15361 } else if (Op.getOpcode() == ISD::SUB) {
15362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15363 Offset += -C->getZExtValue();
15364 Op = Op.getOperand(0);
15369 // Otherwise, this isn't something we can handle, reject it.
15373 const GlobalValue *GV = GA->getGlobal();
15374 // If we require an extra load to get this address, as in PIC mode, we
15375 // can't accept it.
15376 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15377 getTargetMachine())))
15380 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15381 GA->getValueType(0), Offset);
15386 if (Result.getNode()) {
15387 Ops.push_back(Result);
15390 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15393 std::pair<unsigned, const TargetRegisterClass*>
15394 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15396 // First, see if this is a constraint that directly corresponds to an LLVM
15398 if (Constraint.size() == 1) {
15399 // GCC Constraint Letters
15400 switch (Constraint[0]) {
15402 // TODO: Slight differences here in allocation order and leaving
15403 // RIP in the class. Do they matter any more here than they do
15404 // in the normal allocation?
15405 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15406 if (Subtarget->is64Bit()) {
15407 if (VT == MVT::i32 || VT == MVT::f32)
15408 return std::make_pair(0U, X86::GR32RegisterClass);
15409 else if (VT == MVT::i16)
15410 return std::make_pair(0U, X86::GR16RegisterClass);
15411 else if (VT == MVT::i8 || VT == MVT::i1)
15412 return std::make_pair(0U, X86::GR8RegisterClass);
15413 else if (VT == MVT::i64 || VT == MVT::f64)
15414 return std::make_pair(0U, X86::GR64RegisterClass);
15417 // 32-bit fallthrough
15418 case 'Q': // Q_REGS
15419 if (VT == MVT::i32 || VT == MVT::f32)
15420 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15421 else if (VT == MVT::i16)
15422 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15423 else if (VT == MVT::i8 || VT == MVT::i1)
15424 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15425 else if (VT == MVT::i64)
15426 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15428 case 'r': // GENERAL_REGS
15429 case 'l': // INDEX_REGS
15430 if (VT == MVT::i8 || VT == MVT::i1)
15431 return std::make_pair(0U, X86::GR8RegisterClass);
15432 if (VT == MVT::i16)
15433 return std::make_pair(0U, X86::GR16RegisterClass);
15434 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15435 return std::make_pair(0U, X86::GR32RegisterClass);
15436 return std::make_pair(0U, X86::GR64RegisterClass);
15437 case 'R': // LEGACY_REGS
15438 if (VT == MVT::i8 || VT == MVT::i1)
15439 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15440 if (VT == MVT::i16)
15441 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15442 if (VT == MVT::i32 || !Subtarget->is64Bit())
15443 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15444 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15445 case 'f': // FP Stack registers.
15446 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15447 // value to the correct fpstack register class.
15448 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15449 return std::make_pair(0U, X86::RFP32RegisterClass);
15450 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15451 return std::make_pair(0U, X86::RFP64RegisterClass);
15452 return std::make_pair(0U, X86::RFP80RegisterClass);
15453 case 'y': // MMX_REGS if MMX allowed.
15454 if (!Subtarget->hasMMX()) break;
15455 return std::make_pair(0U, X86::VR64RegisterClass);
15456 case 'Y': // SSE_REGS if SSE2 allowed
15457 if (!Subtarget->hasSSE2()) break;
15459 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15460 if (!Subtarget->hasSSE1()) break;
15462 switch (VT.getSimpleVT().SimpleTy) {
15464 // Scalar SSE types.
15467 return std::make_pair(0U, X86::FR32RegisterClass);
15470 return std::make_pair(0U, X86::FR64RegisterClass);
15478 return std::make_pair(0U, X86::VR128RegisterClass);
15486 return std::make_pair(0U, X86::VR256RegisterClass);
15493 // Use the default implementation in TargetLowering to convert the register
15494 // constraint into a member of a register class.
15495 std::pair<unsigned, const TargetRegisterClass*> Res;
15496 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15498 // Not found as a standard register?
15499 if (Res.second == 0) {
15500 // Map st(0) -> st(7) -> ST0
15501 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15502 tolower(Constraint[1]) == 's' &&
15503 tolower(Constraint[2]) == 't' &&
15504 Constraint[3] == '(' &&
15505 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15506 Constraint[5] == ')' &&
15507 Constraint[6] == '}') {
15509 Res.first = X86::ST0+Constraint[4]-'0';
15510 Res.second = X86::RFP80RegisterClass;
15514 // GCC allows "st(0)" to be called just plain "st".
15515 if (StringRef("{st}").equals_lower(Constraint)) {
15516 Res.first = X86::ST0;
15517 Res.second = X86::RFP80RegisterClass;
15522 if (StringRef("{flags}").equals_lower(Constraint)) {
15523 Res.first = X86::EFLAGS;
15524 Res.second = X86::CCRRegisterClass;
15528 // 'A' means EAX + EDX.
15529 if (Constraint == "A") {
15530 Res.first = X86::EAX;
15531 Res.second = X86::GR32_ADRegisterClass;
15537 // Otherwise, check to see if this is a register class of the wrong value
15538 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15539 // turn into {ax},{dx}.
15540 if (Res.second->hasType(VT))
15541 return Res; // Correct type already, nothing to do.
15543 // All of the single-register GCC register classes map their values onto
15544 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15545 // really want an 8-bit or 32-bit register, map to the appropriate register
15546 // class and return the appropriate register.
15547 if (Res.second == X86::GR16RegisterClass) {
15548 if (VT == MVT::i8) {
15549 unsigned DestReg = 0;
15550 switch (Res.first) {
15552 case X86::AX: DestReg = X86::AL; break;
15553 case X86::DX: DestReg = X86::DL; break;
15554 case X86::CX: DestReg = X86::CL; break;
15555 case X86::BX: DestReg = X86::BL; break;
15558 Res.first = DestReg;
15559 Res.second = X86::GR8RegisterClass;
15561 } else if (VT == MVT::i32) {
15562 unsigned DestReg = 0;
15563 switch (Res.first) {
15565 case X86::AX: DestReg = X86::EAX; break;
15566 case X86::DX: DestReg = X86::EDX; break;
15567 case X86::CX: DestReg = X86::ECX; break;
15568 case X86::BX: DestReg = X86::EBX; break;
15569 case X86::SI: DestReg = X86::ESI; break;
15570 case X86::DI: DestReg = X86::EDI; break;
15571 case X86::BP: DestReg = X86::EBP; break;
15572 case X86::SP: DestReg = X86::ESP; break;
15575 Res.first = DestReg;
15576 Res.second = X86::GR32RegisterClass;
15578 } else if (VT == MVT::i64) {
15579 unsigned DestReg = 0;
15580 switch (Res.first) {
15582 case X86::AX: DestReg = X86::RAX; break;
15583 case X86::DX: DestReg = X86::RDX; break;
15584 case X86::CX: DestReg = X86::RCX; break;
15585 case X86::BX: DestReg = X86::RBX; break;
15586 case X86::SI: DestReg = X86::RSI; break;
15587 case X86::DI: DestReg = X86::RDI; break;
15588 case X86::BP: DestReg = X86::RBP; break;
15589 case X86::SP: DestReg = X86::RSP; break;
15592 Res.first = DestReg;
15593 Res.second = X86::GR64RegisterClass;
15596 } else if (Res.second == X86::FR32RegisterClass ||
15597 Res.second == X86::FR64RegisterClass ||
15598 Res.second == X86::VR128RegisterClass) {
15599 // Handle references to XMM physical registers that got mapped into the
15600 // wrong class. This can happen with constraints like {xmm0} where the
15601 // target independent register mapper will just pick the first match it can
15602 // find, ignoring the required type.
15603 if (VT == MVT::f32)
15604 Res.second = X86::FR32RegisterClass;
15605 else if (VT == MVT::f64)
15606 Res.second = X86::FR64RegisterClass;
15607 else if (X86::VR128RegisterClass->hasType(VT))
15608 Res.second = X86::VR128RegisterClass;