1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCExpr.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
66 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
68 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
69 if (is64Bit) return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
71 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
72 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
73 return new X8632_ELFTargetObjectFile(TM);
74 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
75 return new TargetLoweringObjectFileCOFF();
77 llvm_unreachable("unknown subtarget type");
80 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
81 : TargetLowering(TM, createTLOF(TM)) {
82 Subtarget = &TM.getSubtarget<X86Subtarget>();
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
85 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
87 RegInfo = TM.getRegisterInfo();
90 // Set up the TargetLowering object.
92 // X86 is weird, it always uses i8 for shift amounts and setcc results.
93 setShiftAmountType(MVT::i8);
94 setBooleanContents(ZeroOrOneBooleanContent);
95 setSchedulingPreference(Sched::RegPressure);
96 setStackPointerRegisterToSaveRestore(X86StackPtr);
98 if (Subtarget->isTargetDarwin()) {
99 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
100 setUseUnderscoreSetJmp(false);
101 setUseUnderscoreLongJmp(false);
102 } else if (Subtarget->isTargetMingw()) {
103 // MS runtime is weird: it exports _setjmp, but longjmp!
104 setUseUnderscoreSetJmp(true);
105 setUseUnderscoreLongJmp(false);
107 setUseUnderscoreSetJmp(true);
108 setUseUnderscoreLongJmp(true);
111 // Set up the register classes.
112 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
122 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
124 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
128 // SETOEQ and SETUNE require checking two conditions.
129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
145 } else if (!UseSoftFloat) {
146 // We have an algorithm for SSE2->double, and we turn this into a
147 // 64-bit FILD followed by conditional FADD for other targets.
148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
149 // We have an algorithm for SSE2, and we turn this into a 64-bit
150 // FILD for other targets.
151 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
154 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
156 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
157 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
160 // SSE has no i16 to fp conversion, only i32
161 if (X86ScalarSSEf32) {
162 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
163 // f32 and f64 cases are Legal, f80 case is not
164 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
166 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
174 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
175 // are Legal, f80 is custom lowered.
176 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
177 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
179 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
181 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
182 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
184 if (X86ScalarSSEf32) {
185 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
186 // f32 and f64 cases are Legal, f80 case is not
187 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
189 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
193 // Handle FP_TO_UINT by promoting the destination to a larger signed
195 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
196 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
199 if (Subtarget->is64Bit()) {
200 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
202 } else if (!UseSoftFloat) {
203 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
204 // Expand FP_TO_UINT into a select.
205 // FIXME: We would like to use a Custom expander here eventually to do
206 // the optimal thing for SSE vs. the default expansion in the legalizer.
207 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
209 // With SSE3 we can use fisttpll to convert to a signed i64; without
210 // SSE, we're stuck with a fistpll.
211 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
214 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
215 if (!X86ScalarSSEf64) {
216 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
217 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
218 if (Subtarget->is64Bit()) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
220 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
221 if (Subtarget->hasMMX() && !DisableMMX)
222 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
228 // Scalar integer divide and remainder are lowered to use operations that
229 // produce two results, to match the available instructions. This exposes
230 // the two-result form to trivial CSE, which is able to combine x/y and x%y
231 // into a single instruction.
233 // Scalar integer multiply-high is also lowered to use two-result
234 // operations, to match the available instructions. However, plain multiply
235 // (low) operations are left as Legal, as there are single-result
236 // instructions for this in x86. Using the two-result multiply instructions
237 // when both high and low results are needed must be arranged by dagcombine.
238 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
240 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
241 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
242 setOperationAction(ISD::SREM , MVT::i8 , Expand);
243 setOperationAction(ISD::UREM , MVT::i8 , Expand);
244 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
246 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
247 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
248 setOperationAction(ISD::SREM , MVT::i16 , Expand);
249 setOperationAction(ISD::UREM , MVT::i16 , Expand);
250 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
252 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
253 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
254 setOperationAction(ISD::SREM , MVT::i32 , Expand);
255 setOperationAction(ISD::UREM , MVT::i32 , Expand);
256 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
257 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
258 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
259 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
260 setOperationAction(ISD::SREM , MVT::i64 , Expand);
261 setOperationAction(ISD::UREM , MVT::i64 , Expand);
263 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
264 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
265 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
266 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
267 if (Subtarget->is64Bit())
268 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
272 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
273 setOperationAction(ISD::FREM , MVT::f32 , Expand);
274 setOperationAction(ISD::FREM , MVT::f64 , Expand);
275 setOperationAction(ISD::FREM , MVT::f80 , Expand);
276 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
278 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
279 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
280 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
281 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
282 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
300 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
302 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
305 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
308 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
309 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
315 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
318 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
319 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
320 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
321 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
322 if (Subtarget->is64Bit())
323 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
324 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
325 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
328 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
329 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
330 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
333 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
334 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
335 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
336 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
339 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
340 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
343 if (Subtarget->hasSSE1())
344 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
346 // We may not have a libcall for MEMBARRIER so we should lower this.
347 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
349 // On X86 and X86-64, atomic operations are lowered to locked instructions.
350 // Locked instructions, in turn, have implicit fence semantics (all memory
351 // operations are flushed before issuing the locked instruction, and they
352 // are not buffered), so we can fold away the common pattern of
353 // fence-atomic-fence.
354 setShouldFoldAtomicFences(true);
356 // Expand certain atomics
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
367 if (!Subtarget->is64Bit()) {
368 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
377 // FIXME - use subtarget debug flags
378 if (!Subtarget->isTargetDarwin() &&
379 !Subtarget->isTargetELF() &&
380 !Subtarget->isTargetCygMing()) {
381 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
385 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
387 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
388 if (Subtarget->is64Bit()) {
389 setExceptionPointerRegister(X86::RAX);
390 setExceptionSelectorRegister(X86::RDX);
392 setExceptionPointerRegister(X86::EAX);
393 setExceptionSelectorRegister(X86::EDX);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
398 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
400 setOperationAction(ISD::TRAP, MVT::Other, Legal);
402 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
403 setOperationAction(ISD::VASTART , MVT::Other, Custom);
404 setOperationAction(ISD::VAEND , MVT::Other, Expand);
405 if (Subtarget->is64Bit()) {
406 setOperationAction(ISD::VAARG , MVT::Other, Custom);
407 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
409 setOperationAction(ISD::VAARG , MVT::Other, Expand);
410 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
413 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
414 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
415 if (Subtarget->is64Bit())
416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
417 if (Subtarget->isTargetCygMing())
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
422 if (!UseSoftFloat && X86ScalarSSEf64) {
423 // f32 and f64 use SSE.
424 // Set up the FP register classes.
425 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
426 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
428 // Use ANDPD to simulate FABS.
429 setOperationAction(ISD::FABS , MVT::f64, Custom);
430 setOperationAction(ISD::FABS , MVT::f32, Custom);
432 // Use XORP to simulate FNEG.
433 setOperationAction(ISD::FNEG , MVT::f64, Custom);
434 setOperationAction(ISD::FNEG , MVT::f32, Custom);
436 // Use ANDPD and ORPD to simulate FCOPYSIGN.
437 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
438 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
440 // We don't support sin/cos/fmod
441 setOperationAction(ISD::FSIN , MVT::f64, Expand);
442 setOperationAction(ISD::FCOS , MVT::f64, Expand);
443 setOperationAction(ISD::FSIN , MVT::f32, Expand);
444 setOperationAction(ISD::FCOS , MVT::f32, Expand);
446 // Expand FP immediates into loads from the stack, except for the special
448 addLegalFPImmediate(APFloat(+0.0)); // xorpd
449 addLegalFPImmediate(APFloat(+0.0f)); // xorps
450 } else if (!UseSoftFloat && X86ScalarSSEf32) {
451 // Use SSE for f32, x87 for f64.
452 // Set up the FP register classes.
453 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
454 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
456 // Use ANDPS to simulate FABS.
457 setOperationAction(ISD::FABS , MVT::f32, Custom);
459 // Use XORP to simulate FNEG.
460 setOperationAction(ISD::FNEG , MVT::f32, Custom);
462 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
464 // Use ANDPS and ORPS to simulate FCOPYSIGN.
465 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
466 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
468 // We don't support sin/cos/fmod
469 setOperationAction(ISD::FSIN , MVT::f32, Expand);
470 setOperationAction(ISD::FCOS , MVT::f32, Expand);
472 // Special cases we handle for FP constants.
473 addLegalFPImmediate(APFloat(+0.0f)); // xorps
474 addLegalFPImmediate(APFloat(+0.0)); // FLD0
475 addLegalFPImmediate(APFloat(+1.0)); // FLD1
476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
480 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
481 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
483 } else if (!UseSoftFloat) {
484 // f32 and f64 in x87.
485 // Set up the FP register classes.
486 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
487 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
489 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
490 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
492 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
495 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
496 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
498 addLegalFPImmediate(APFloat(+0.0)); // FLD0
499 addLegalFPImmediate(APFloat(+1.0)); // FLD1
500 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
501 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
502 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
503 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
504 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
505 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
508 // Long double always uses X87.
510 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
511 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
512 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
515 APFloat TmpFlt(+0.0);
516 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
518 addLegalFPImmediate(TmpFlt); // FLD0
520 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
521 APFloat TmpFlt2(+1.0);
522 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
524 addLegalFPImmediate(TmpFlt2); // FLD1
525 TmpFlt2.changeSign();
526 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
530 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
531 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
535 // Always use a library call for pow.
536 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
538 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
540 setOperationAction(ISD::FLOG, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
542 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP, MVT::f80, Expand);
544 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
546 // First set operation action for all vector types to either promote
547 // (for widening) or expand (for scalarization). Then we will selectively
548 // turn on ones that can be effectively codegen'd.
549 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
550 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
551 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
567 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
600 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
604 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
605 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
606 setTruncStoreAction((MVT::SimpleValueType)VT,
607 (MVT::SimpleValueType)InnerVT, Expand);
608 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
610 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
613 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
614 // with -msoft-float, disable use of MMX as well.
615 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
616 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
617 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
618 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
620 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
622 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
623 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
624 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
625 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
627 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
628 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
629 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
630 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
632 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
633 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
635 setOperationAction(ISD::AND, MVT::v8i8, Promote);
636 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
637 setOperationAction(ISD::AND, MVT::v4i16, Promote);
638 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
639 setOperationAction(ISD::AND, MVT::v2i32, Promote);
640 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
641 setOperationAction(ISD::AND, MVT::v1i64, Legal);
643 setOperationAction(ISD::OR, MVT::v8i8, Promote);
644 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
645 setOperationAction(ISD::OR, MVT::v4i16, Promote);
646 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
647 setOperationAction(ISD::OR, MVT::v2i32, Promote);
648 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
649 setOperationAction(ISD::OR, MVT::v1i64, Legal);
651 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
652 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
653 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
654 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
655 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
656 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
657 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
659 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
660 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
661 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
662 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
663 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
664 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
665 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
681 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
683 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
684 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
685 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
686 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
687 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
689 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
691 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
692 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
693 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
694 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
695 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
699 if (!UseSoftFloat && Subtarget->hasSSE1()) {
700 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
702 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
703 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
704 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
705 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
706 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
707 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
708 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
709 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
712 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
713 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
716 if (!UseSoftFloat && Subtarget->hasSSE2()) {
717 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
719 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
720 // registers cannot be used even for integer operations.
721 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
722 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
723 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
724 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
726 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
727 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
728 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
729 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
730 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
731 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
732 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
733 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
734 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
735 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
736 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
737 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
738 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
739 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
740 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
741 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
743 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
744 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
745 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
746 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
752 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
760 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
761 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
762 EVT VT = (MVT::SimpleValueType)i;
763 // Do not attempt to custom lower non-power-of-2 vectors
764 if (!isPowerOf2_32(VT.getVectorNumElements()))
766 // Do not attempt to custom lower non-128-bit vectors
767 if (!VT.is128BitVector())
769 setOperationAction(ISD::BUILD_VECTOR,
770 VT.getSimpleVT().SimpleTy, Custom);
771 setOperationAction(ISD::VECTOR_SHUFFLE,
772 VT.getSimpleVT().SimpleTy, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
774 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
778 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
781 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
782 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
784 if (Subtarget->is64Bit()) {
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
789 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
790 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
791 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
794 // Do not attempt to promote non-128-bit vectors
795 if (!VT.is128BitVector())
798 setOperationAction(ISD::AND, SVT, Promote);
799 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
800 setOperationAction(ISD::OR, SVT, Promote);
801 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
802 setOperationAction(ISD::XOR, SVT, Promote);
803 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
804 setOperationAction(ISD::LOAD, SVT, Promote);
805 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
806 setOperationAction(ISD::SELECT, SVT, Promote);
807 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
810 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
812 // Custom lower v2i64 and v2f64 selects.
813 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
814 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
815 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
816 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
818 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
819 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
820 if (!DisableMMX && Subtarget->hasMMX()) {
821 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
822 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
826 if (Subtarget->hasSSE41()) {
827 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
828 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
829 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
830 setOperationAction(ISD::FRINT, MVT::f32, Legal);
831 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
832 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
833 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
834 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
835 setOperationAction(ISD::FRINT, MVT::f64, Legal);
836 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
838 // FIXME: Do we need to handle scalar-to-vector here?
839 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
841 // i8 and i16 vectors are custom , because the source register and source
842 // source memory operand types are not the same width. f32 vectors are
843 // custom since the immediate controlling the insert encodes additional
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
855 if (Subtarget->is64Bit()) {
856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
861 if (Subtarget->hasSSE42()) {
862 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
865 if (!UseSoftFloat && Subtarget->hasAVX()) {
866 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
867 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
868 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
869 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
871 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
872 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
873 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
874 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
875 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
876 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
877 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
878 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
879 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
880 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
881 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
882 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
883 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
884 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
885 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
887 // Operations to consider commented out -v16i16 v32i8
888 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
889 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
890 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
891 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
892 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
893 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
894 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
895 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
896 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
897 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
898 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
899 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
900 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
901 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
903 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
904 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
905 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
906 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
908 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
909 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
910 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
914 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
915 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
917 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
922 // Not sure we want to do this since there are no 256-bit integer
925 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
926 // This includes 256-bit vectors
927 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
928 EVT VT = (MVT::SimpleValueType)i;
930 // Do not attempt to custom lower non-power-of-2 vectors
931 if (!isPowerOf2_32(VT.getVectorNumElements()))
934 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
935 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
939 if (Subtarget->is64Bit()) {
940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
946 // Not sure we want to do this since there are no 256-bit integer
949 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
950 // Including 256-bit vectors
951 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
952 EVT VT = (MVT::SimpleValueType)i;
954 if (!VT.is256BitVector()) {
957 setOperationAction(ISD::AND, VT, Promote);
958 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
959 setOperationAction(ISD::OR, VT, Promote);
960 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
961 setOperationAction(ISD::XOR, VT, Promote);
962 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
963 setOperationAction(ISD::LOAD, VT, Promote);
964 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
965 setOperationAction(ISD::SELECT, VT, Promote);
966 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
969 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
973 // We want to custom lower some of our intrinsics.
974 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
976 // Add/Sub/Mul with overflow operations are custom lowered.
977 setOperationAction(ISD::SADDO, MVT::i32, Custom);
978 setOperationAction(ISD::UADDO, MVT::i32, Custom);
979 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
980 setOperationAction(ISD::USUBO, MVT::i32, Custom);
981 setOperationAction(ISD::SMULO, MVT::i32, Custom);
983 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
984 // handle type legalization for these operations here.
986 // FIXME: We really should do custom legalization for addition and
987 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
988 // than generic legalization for 64-bit multiplication-with-overflow, though.
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::SADDO, MVT::i64, Custom);
991 setOperationAction(ISD::UADDO, MVT::i64, Custom);
992 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
993 setOperationAction(ISD::USUBO, MVT::i64, Custom);
994 setOperationAction(ISD::SMULO, MVT::i64, Custom);
997 if (!Subtarget->is64Bit()) {
998 // These libcalls are not available in 32-bit.
999 setLibcallName(RTLIB::SHL_I128, 0);
1000 setLibcallName(RTLIB::SRL_I128, 0);
1001 setLibcallName(RTLIB::SRA_I128, 0);
1004 // We have target-specific dag combine patterns for the following nodes:
1005 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1006 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1007 setTargetDAGCombine(ISD::BUILD_VECTOR);
1008 setTargetDAGCombine(ISD::SELECT);
1009 setTargetDAGCombine(ISD::SHL);
1010 setTargetDAGCombine(ISD::SRA);
1011 setTargetDAGCombine(ISD::SRL);
1012 setTargetDAGCombine(ISD::OR);
1013 setTargetDAGCombine(ISD::STORE);
1014 setTargetDAGCombine(ISD::ZERO_EXTEND);
1015 if (Subtarget->is64Bit())
1016 setTargetDAGCombine(ISD::MUL);
1018 computeRegisterProperties();
1020 // FIXME: These should be based on subtarget info. Plus, the values should
1021 // be smaller when we are in optimizing for size mode.
1022 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1023 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1024 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1025 setPrefLoopAlignment(16);
1026 benefitFromCodePlacementOpt = true;
1030 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1035 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1036 /// the desired ByVal argument alignment.
1037 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1040 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1041 if (VTy->getBitWidth() == 128)
1043 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1044 unsigned EltAlign = 0;
1045 getMaxByValAlign(ATy->getElementType(), EltAlign);
1046 if (EltAlign > MaxAlign)
1047 MaxAlign = EltAlign;
1048 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1049 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1050 unsigned EltAlign = 0;
1051 getMaxByValAlign(STy->getElementType(i), EltAlign);
1052 if (EltAlign > MaxAlign)
1053 MaxAlign = EltAlign;
1061 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1062 /// function arguments in the caller parameter area. For X86, aggregates
1063 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1064 /// are at 4-byte boundaries.
1065 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1066 if (Subtarget->is64Bit()) {
1067 // Max of 8 and alignment of type.
1068 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1075 if (Subtarget->hasSSE1())
1076 getMaxByValAlign(Ty, Align);
1080 /// getOptimalMemOpType - Returns the target specific optimal type for load
1081 /// and store operations as a result of memset, memcpy, and memmove
1082 /// lowering. If DstAlign is zero that means it's safe to destination
1083 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1084 /// means there isn't a need to check it against alignment requirement,
1085 /// probably because the source does not need to be loaded. If
1086 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1087 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1088 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1089 /// constant so it does not need to be loaded.
1090 /// It returns EVT::Other if the type should be determined using generic
1091 /// target-independent logic.
1093 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1094 unsigned DstAlign, unsigned SrcAlign,
1095 bool NonScalarIntSafe,
1097 MachineFunction &MF) const {
1098 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1099 // linux. This is because the stack realignment code can't handle certain
1100 // cases like PR2962. This should be removed when PR2962 is fixed.
1101 const Function *F = MF.getFunction();
1102 if (NonScalarIntSafe &&
1103 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1105 (Subtarget->isUnalignedMemAccessFast() ||
1106 ((DstAlign == 0 || DstAlign >= 16) &&
1107 (SrcAlign == 0 || SrcAlign >= 16))) &&
1108 Subtarget->getStackAlignment() >= 16) {
1109 if (Subtarget->hasSSE2())
1111 if (Subtarget->hasSSE1())
1113 } else if (!MemcpyStrSrc && Size >= 8 &&
1114 !Subtarget->is64Bit() &&
1115 Subtarget->getStackAlignment() >= 8 &&
1116 Subtarget->hasSSE2()) {
1117 // Do not use f64 to lower memcpy if source is string constant. It's
1118 // better to use i32 to avoid the loads.
1122 if (Subtarget->is64Bit() && Size >= 8)
1127 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1128 /// current function. The returned value is a member of the
1129 /// MachineJumpTableInfo::JTEntryKind enum.
1130 unsigned X86TargetLowering::getJumpTableEncoding() const {
1131 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1133 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1134 Subtarget->isPICStyleGOT())
1135 return MachineJumpTableInfo::EK_Custom32;
1137 // Otherwise, use the normal jump table encoding heuristics.
1138 return TargetLowering::getJumpTableEncoding();
1141 /// getPICBaseSymbol - Return the X86-32 PIC base.
1143 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1144 MCContext &Ctx) const {
1145 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1146 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1147 Twine(MF->getFunctionNumber())+"$pb");
1152 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1153 const MachineBasicBlock *MBB,
1154 unsigned uid,MCContext &Ctx) const{
1155 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1156 Subtarget->isPICStyleGOT());
1157 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1159 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1160 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1163 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1165 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1166 SelectionDAG &DAG) const {
1167 if (!Subtarget->is64Bit())
1168 // This doesn't have DebugLoc associated with it, but is not really the
1169 // same as a Register.
1170 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1174 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1175 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1177 const MCExpr *X86TargetLowering::
1178 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1179 MCContext &Ctx) const {
1180 // X86-64 uses RIP relative addressing based on the jump table label.
1181 if (Subtarget->isPICStyleRIPRel())
1182 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1184 // Otherwise, the reference is relative to the PIC base.
1185 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1188 /// getFunctionAlignment - Return the Log2 alignment of this function.
1189 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1190 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1193 std::pair<const TargetRegisterClass*, uint8_t>
1194 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1195 const TargetRegisterClass *RRC = 0;
1197 switch (VT.getSimpleVT().SimpleTy) {
1199 return TargetLowering::findRepresentativeClass(VT);
1200 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1201 RRC = (Subtarget->is64Bit()
1202 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1204 case MVT::v8i8: case MVT::v4i16:
1205 case MVT::v2i32: case MVT::v1i64:
1206 RRC = X86::VR64RegisterClass;
1208 case MVT::f32: case MVT::f64:
1209 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1210 case MVT::v4f32: case MVT::v2f64:
1211 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1213 RRC = X86::VR128RegisterClass;
1216 return std::make_pair(RRC, Cost);
1220 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1221 MachineFunction &MF) const {
1222 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
1223 switch (RC->getID()) {
1226 case X86::GR32RegClassID:
1228 case X86::GR64RegClassID:
1230 case X86::VR128RegClassID:
1231 return Subtarget->is64Bit() ? 10 : 4;
1232 case X86::VR64RegClassID:
1237 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1238 unsigned &Offset) const {
1239 if (!Subtarget->isTargetLinux())
1242 if (Subtarget->is64Bit()) {
1243 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1245 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1258 //===----------------------------------------------------------------------===//
1259 // Return Value Calling Convention Implementation
1260 //===----------------------------------------------------------------------===//
1262 #include "X86GenCallingConv.inc"
1265 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1266 const SmallVectorImpl<ISD::OutputArg> &Outs,
1267 LLVMContext &Context) const {
1268 SmallVector<CCValAssign, 16> RVLocs;
1269 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1271 return CCInfo.CheckReturn(Outs, RetCC_X86);
1275 X86TargetLowering::LowerReturn(SDValue Chain,
1276 CallingConv::ID CallConv, bool isVarArg,
1277 const SmallVectorImpl<ISD::OutputArg> &Outs,
1278 const SmallVectorImpl<SDValue> &OutVals,
1279 DebugLoc dl, SelectionDAG &DAG) const {
1280 MachineFunction &MF = DAG.getMachineFunction();
1281 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1283 SmallVector<CCValAssign, 16> RVLocs;
1284 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1285 RVLocs, *DAG.getContext());
1286 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1288 // Add the regs to the liveout set for the function.
1289 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1290 for (unsigned i = 0; i != RVLocs.size(); ++i)
1291 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1292 MRI.addLiveOut(RVLocs[i].getLocReg());
1296 SmallVector<SDValue, 6> RetOps;
1297 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1298 // Operand #1 = Bytes To Pop
1299 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1302 // Copy the result values into the output registers.
1303 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1304 CCValAssign &VA = RVLocs[i];
1305 assert(VA.isRegLoc() && "Can only return in registers!");
1306 SDValue ValToCopy = OutVals[i];
1307 EVT ValVT = ValToCopy.getValueType();
1309 // If this is x86-64, and we disabled SSE, we can't return FP values
1310 if ((ValVT == MVT::f32 || ValVT == MVT::f64) &&
1311 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1312 report_fatal_error("SSE register return with SSE disabled");
1314 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1315 // llvm-gcc has never done it right and no one has noticed, so this
1316 // should be OK for now.
1317 if (ValVT == MVT::f64 &&
1318 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) {
1319 report_fatal_error("SSE2 register return with SSE2 disabled");
1322 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1323 // the RET instruction and handled by the FP Stackifier.
1324 if (VA.getLocReg() == X86::ST0 ||
1325 VA.getLocReg() == X86::ST1) {
1326 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1327 // change the value to the FP stack register class.
1328 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1329 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1330 RetOps.push_back(ValToCopy);
1331 // Don't emit a copytoreg.
1335 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1336 // which is returned in RAX / RDX.
1337 if (Subtarget->is64Bit()) {
1338 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1339 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1340 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1341 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1346 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1347 Flag = Chain.getValue(1);
1350 // The x86-64 ABI for returning structs by value requires that we copy
1351 // the sret argument into %rax for the return. We saved the argument into
1352 // a virtual register in the entry block, so now we copy the value out
1354 if (Subtarget->is64Bit() &&
1355 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1356 MachineFunction &MF = DAG.getMachineFunction();
1357 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1358 unsigned Reg = FuncInfo->getSRetReturnReg();
1360 "SRetReturnReg should have been set in LowerFormalArguments().");
1361 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1363 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1364 Flag = Chain.getValue(1);
1366 // RAX now acts like a return value.
1367 MRI.addLiveOut(X86::RAX);
1370 RetOps[0] = Chain; // Update chain.
1372 // Add the flag if we have it.
1374 RetOps.push_back(Flag);
1376 return DAG.getNode(X86ISD::RET_FLAG, dl,
1377 MVT::Other, &RetOps[0], RetOps.size());
1380 /// LowerCallResult - Lower the result values of a call into the
1381 /// appropriate copies out of appropriate physical registers.
1384 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1385 CallingConv::ID CallConv, bool isVarArg,
1386 const SmallVectorImpl<ISD::InputArg> &Ins,
1387 DebugLoc dl, SelectionDAG &DAG,
1388 SmallVectorImpl<SDValue> &InVals) const {
1390 // Assign locations to each value returned by this call.
1391 SmallVector<CCValAssign, 16> RVLocs;
1392 bool Is64Bit = Subtarget->is64Bit();
1393 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1394 RVLocs, *DAG.getContext());
1395 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1397 // Copy all of the result registers out of their specified physreg.
1398 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1399 CCValAssign &VA = RVLocs[i];
1400 EVT CopyVT = VA.getValVT();
1402 // If this is x86-64, and we disabled SSE, we can't return FP values
1403 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1404 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1405 report_fatal_error("SSE register return with SSE disabled");
1410 // If this is a call to a function that returns an fp value on the floating
1411 // point stack, we must guarantee the the value is popped from the stack, so
1412 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1413 // if the return value is not used. We use the FpGET_ST0 instructions
1415 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1416 // If we prefer to use the value in xmm registers, copy it out as f80 and
1417 // use a truncate to move it from fp stack reg to xmm reg.
1418 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1419 bool isST0 = VA.getLocReg() == X86::ST0;
1421 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1422 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1423 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1424 SDValue Ops[] = { Chain, InFlag };
1425 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1427 Val = Chain.getValue(0);
1429 // Round the f80 to the right size, which also moves it to the appropriate
1431 if (CopyVT != VA.getValVT())
1432 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1433 // This truncation won't change the value.
1434 DAG.getIntPtrConstant(1));
1435 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1436 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1437 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1438 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1439 MVT::v2i64, InFlag).getValue(1);
1440 Val = Chain.getValue(0);
1441 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1442 Val, DAG.getConstant(0, MVT::i64));
1444 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1445 MVT::i64, InFlag).getValue(1);
1446 Val = Chain.getValue(0);
1448 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1450 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1451 CopyVT, InFlag).getValue(1);
1452 Val = Chain.getValue(0);
1454 InFlag = Chain.getValue(2);
1455 InVals.push_back(Val);
1462 //===----------------------------------------------------------------------===//
1463 // C & StdCall & Fast Calling Convention implementation
1464 //===----------------------------------------------------------------------===//
1465 // StdCall calling convention seems to be standard for many Windows' API
1466 // routines and around. It differs from C calling convention just a little:
1467 // callee should clean up the stack, not caller. Symbols should be also
1468 // decorated in some fancy way :) It doesn't support any vector arguments.
1469 // For info on fast calling convention see Fast Calling Convention (tail call)
1470 // implementation LowerX86_32FastCCCallTo.
1472 /// CallIsStructReturn - Determines whether a call uses struct return
1474 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1478 return Outs[0].Flags.isSRet();
1481 /// ArgsAreStructReturn - Determines whether a function uses struct
1482 /// return semantics.
1484 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1488 return Ins[0].Flags.isSRet();
1491 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1492 /// given CallingConvention value.
1493 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1494 if (Subtarget->is64Bit()) {
1495 if (CC == CallingConv::GHC)
1496 return CC_X86_64_GHC;
1497 else if (Subtarget->isTargetWin64())
1498 return CC_X86_Win64_C;
1503 if (CC == CallingConv::X86_FastCall)
1504 return CC_X86_32_FastCall;
1505 else if (CC == CallingConv::X86_ThisCall)
1506 return CC_X86_32_ThisCall;
1507 else if (CC == CallingConv::Fast)
1508 return CC_X86_32_FastCC;
1509 else if (CC == CallingConv::GHC)
1510 return CC_X86_32_GHC;
1515 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1516 /// by "Src" to address "Dst" with size and alignment information specified by
1517 /// the specific parameter attribute. The copy will be passed as a byval
1518 /// function parameter.
1520 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1521 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1523 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1524 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1525 /*isVolatile*/false, /*AlwaysInline=*/true,
1529 /// IsTailCallConvention - Return true if the calling convention is one that
1530 /// supports tail call optimization.
1531 static bool IsTailCallConvention(CallingConv::ID CC) {
1532 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1535 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1536 /// a tailcall target by changing its ABI.
1537 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1538 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1542 X86TargetLowering::LowerMemArgument(SDValue Chain,
1543 CallingConv::ID CallConv,
1544 const SmallVectorImpl<ISD::InputArg> &Ins,
1545 DebugLoc dl, SelectionDAG &DAG,
1546 const CCValAssign &VA,
1547 MachineFrameInfo *MFI,
1549 // Create the nodes corresponding to a load from this parameter slot.
1550 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1551 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1552 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1555 // If value is passed by pointer we have address passed instead of the value
1557 if (VA.getLocInfo() == CCValAssign::Indirect)
1558 ValVT = VA.getLocVT();
1560 ValVT = VA.getValVT();
1562 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1563 // changed with more analysis.
1564 // In case of tail call optimization mark all arguments mutable. Since they
1565 // could be overwritten by lowering of arguments in case of a tail call.
1566 if (Flags.isByVal()) {
1567 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1568 VA.getLocMemOffset(), isImmutable);
1569 return DAG.getFrameIndex(FI, getPointerTy());
1571 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1572 VA.getLocMemOffset(), isImmutable);
1573 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1574 return DAG.getLoad(ValVT, dl, Chain, FIN,
1575 PseudoSourceValue::getFixedStack(FI), 0,
1581 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1582 CallingConv::ID CallConv,
1584 const SmallVectorImpl<ISD::InputArg> &Ins,
1587 SmallVectorImpl<SDValue> &InVals)
1589 MachineFunction &MF = DAG.getMachineFunction();
1590 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1592 const Function* Fn = MF.getFunction();
1593 if (Fn->hasExternalLinkage() &&
1594 Subtarget->isTargetCygMing() &&
1595 Fn->getName() == "main")
1596 FuncInfo->setForceFramePointer(true);
1598 MachineFrameInfo *MFI = MF.getFrameInfo();
1599 bool Is64Bit = Subtarget->is64Bit();
1600 bool IsWin64 = Subtarget->isTargetWin64();
1602 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1603 "Var args not supported with calling convention fastcc or ghc");
1605 // Assign locations to all of the incoming arguments.
1606 SmallVector<CCValAssign, 16> ArgLocs;
1607 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1608 ArgLocs, *DAG.getContext());
1609 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1611 unsigned LastVal = ~0U;
1613 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1614 CCValAssign &VA = ArgLocs[i];
1615 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1617 assert(VA.getValNo() != LastVal &&
1618 "Don't support value assigned to multiple locs yet");
1619 LastVal = VA.getValNo();
1621 if (VA.isRegLoc()) {
1622 EVT RegVT = VA.getLocVT();
1623 TargetRegisterClass *RC = NULL;
1624 if (RegVT == MVT::i32)
1625 RC = X86::GR32RegisterClass;
1626 else if (Is64Bit && RegVT == MVT::i64)
1627 RC = X86::GR64RegisterClass;
1628 else if (RegVT == MVT::f32)
1629 RC = X86::FR32RegisterClass;
1630 else if (RegVT == MVT::f64)
1631 RC = X86::FR64RegisterClass;
1632 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1633 RC = X86::VR128RegisterClass;
1634 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1635 RC = X86::VR64RegisterClass;
1637 llvm_unreachable("Unknown argument type!");
1639 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1640 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1642 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1643 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1645 if (VA.getLocInfo() == CCValAssign::SExt)
1646 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1647 DAG.getValueType(VA.getValVT()));
1648 else if (VA.getLocInfo() == CCValAssign::ZExt)
1649 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1650 DAG.getValueType(VA.getValVT()));
1651 else if (VA.getLocInfo() == CCValAssign::BCvt)
1652 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1654 if (VA.isExtInLoc()) {
1655 // Handle MMX values passed in XMM regs.
1656 if (RegVT.isVector()) {
1657 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1658 ArgValue, DAG.getConstant(0, MVT::i64));
1659 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1661 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1664 assert(VA.isMemLoc());
1665 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1668 // If value is passed via pointer - do a load.
1669 if (VA.getLocInfo() == CCValAssign::Indirect)
1670 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1673 InVals.push_back(ArgValue);
1676 // The x86-64 ABI for returning structs by value requires that we copy
1677 // the sret argument into %rax for the return. Save the argument into
1678 // a virtual register so that we can access it from the return points.
1679 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1680 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1681 unsigned Reg = FuncInfo->getSRetReturnReg();
1683 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1684 FuncInfo->setSRetReturnReg(Reg);
1686 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1687 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1690 unsigned StackSize = CCInfo.getNextStackOffset();
1691 // Align stack specially for tail calls.
1692 if (FuncIsMadeTailCallSafe(CallConv))
1693 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1695 // If the function takes variable number of arguments, make a frame index for
1696 // the start of the first vararg value... for expansion of llvm.va_start.
1698 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1699 CallConv != CallingConv::X86_ThisCall)) {
1700 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1703 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1705 // FIXME: We should really autogenerate these arrays
1706 static const unsigned GPR64ArgRegsWin64[] = {
1707 X86::RCX, X86::RDX, X86::R8, X86::R9
1709 static const unsigned XMMArgRegsWin64[] = {
1710 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1712 static const unsigned GPR64ArgRegs64Bit[] = {
1713 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1715 static const unsigned XMMArgRegs64Bit[] = {
1716 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1717 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1719 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1722 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1723 GPR64ArgRegs = GPR64ArgRegsWin64;
1724 XMMArgRegs = XMMArgRegsWin64;
1726 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1727 GPR64ArgRegs = GPR64ArgRegs64Bit;
1728 XMMArgRegs = XMMArgRegs64Bit;
1730 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1732 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1735 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1736 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1737 "SSE register cannot be used when SSE is disabled!");
1738 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1739 "SSE register cannot be used when SSE is disabled!");
1740 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1741 // Kernel mode asks for SSE to be disabled, so don't push them
1743 TotalNumXMMRegs = 0;
1745 // For X86-64, if there are vararg parameters that are passed via
1746 // registers, then we must store them to their spots on the stack so they
1747 // may be loaded by deferencing the result of va_next.
1748 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1749 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1750 FuncInfo->setRegSaveFrameIndex(
1751 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1754 // Store the integer parameter registers.
1755 SmallVector<SDValue, 8> MemOps;
1756 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1758 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1759 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1760 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1761 DAG.getIntPtrConstant(Offset));
1762 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1763 X86::GR64RegisterClass);
1764 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1766 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1767 PseudoSourceValue::getFixedStack(
1768 FuncInfo->getRegSaveFrameIndex()),
1769 Offset, false, false, 0);
1770 MemOps.push_back(Store);
1774 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1775 // Now store the XMM (fp + vector) parameter registers.
1776 SmallVector<SDValue, 11> SaveXMMOps;
1777 SaveXMMOps.push_back(Chain);
1779 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1780 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1781 SaveXMMOps.push_back(ALVal);
1783 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1784 FuncInfo->getRegSaveFrameIndex()));
1785 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1786 FuncInfo->getVarArgsFPOffset()));
1788 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1789 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1790 X86::VR128RegisterClass);
1791 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1792 SaveXMMOps.push_back(Val);
1794 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1796 &SaveXMMOps[0], SaveXMMOps.size()));
1799 if (!MemOps.empty())
1800 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1801 &MemOps[0], MemOps.size());
1805 // Some CCs need callee pop.
1806 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1807 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1809 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1810 // If this is an sret function, the return should pop the hidden pointer.
1811 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1812 FuncInfo->setBytesToPopOnReturn(4);
1816 // RegSaveFrameIndex is X86-64 only.
1817 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1818 if (CallConv == CallingConv::X86_FastCall ||
1819 CallConv == CallingConv::X86_ThisCall)
1820 // fastcc functions can't have varargs.
1821 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1828 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1829 SDValue StackPtr, SDValue Arg,
1830 DebugLoc dl, SelectionDAG &DAG,
1831 const CCValAssign &VA,
1832 ISD::ArgFlagsTy Flags) const {
1833 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1834 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1835 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1836 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1837 if (Flags.isByVal()) {
1838 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1840 return DAG.getStore(Chain, dl, Arg, PtrOff,
1841 PseudoSourceValue::getStack(), LocMemOffset,
1845 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1846 /// optimization is performed and it is required.
1848 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1849 SDValue &OutRetAddr, SDValue Chain,
1850 bool IsTailCall, bool Is64Bit,
1851 int FPDiff, DebugLoc dl) const {
1852 // Adjust the Return address stack slot.
1853 EVT VT = getPointerTy();
1854 OutRetAddr = getReturnAddressFrameIndex(DAG);
1856 // Load the "old" Return address.
1857 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1858 return SDValue(OutRetAddr.getNode(), 1);
1861 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1862 /// optimization is performed and it is required (FPDiff!=0).
1864 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1865 SDValue Chain, SDValue RetAddrFrIdx,
1866 bool Is64Bit, int FPDiff, DebugLoc dl) {
1867 // Store the return address to the appropriate stack slot.
1868 if (!FPDiff) return Chain;
1869 // Calculate the new stack slot for the return address.
1870 int SlotSize = Is64Bit ? 8 : 4;
1871 int NewReturnAddrFI =
1872 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1873 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1874 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1875 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1876 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1882 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1883 CallingConv::ID CallConv, bool isVarArg,
1885 const SmallVectorImpl<ISD::OutputArg> &Outs,
1886 const SmallVectorImpl<SDValue> &OutVals,
1887 const SmallVectorImpl<ISD::InputArg> &Ins,
1888 DebugLoc dl, SelectionDAG &DAG,
1889 SmallVectorImpl<SDValue> &InVals) const {
1890 MachineFunction &MF = DAG.getMachineFunction();
1891 bool Is64Bit = Subtarget->is64Bit();
1892 bool IsStructRet = CallIsStructReturn(Outs);
1893 bool IsSibcall = false;
1896 // Check if it's really possible to do a tail call.
1897 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1898 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1899 Outs, OutVals, Ins, DAG);
1901 // Sibcalls are automatically detected tailcalls which do not require
1903 if (!GuaranteedTailCallOpt && isTailCall)
1910 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1911 "Var args not supported with calling convention fastcc or ghc");
1913 // Analyze operands of the call, assigning locations to each operand.
1914 SmallVector<CCValAssign, 16> ArgLocs;
1915 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1916 ArgLocs, *DAG.getContext());
1917 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1919 // Get a count of how many bytes are to be pushed on the stack.
1920 unsigned NumBytes = CCInfo.getNextStackOffset();
1922 // This is a sibcall. The memory operands are available in caller's
1923 // own caller's stack.
1925 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1926 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1929 if (isTailCall && !IsSibcall) {
1930 // Lower arguments at fp - stackoffset + fpdiff.
1931 unsigned NumBytesCallerPushed =
1932 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1933 FPDiff = NumBytesCallerPushed - NumBytes;
1935 // Set the delta of movement of the returnaddr stackslot.
1936 // But only set if delta is greater than previous delta.
1937 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1938 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1942 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1944 SDValue RetAddrFrIdx;
1945 // Load return adress for tail calls.
1946 if (isTailCall && FPDiff)
1947 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1948 Is64Bit, FPDiff, dl);
1950 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1951 SmallVector<SDValue, 8> MemOpChains;
1954 // Walk the register/memloc assignments, inserting copies/loads. In the case
1955 // of tail call optimization arguments are handle later.
1956 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1957 CCValAssign &VA = ArgLocs[i];
1958 EVT RegVT = VA.getLocVT();
1959 SDValue Arg = OutVals[i];
1960 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1961 bool isByVal = Flags.isByVal();
1963 // Promote the value if needed.
1964 switch (VA.getLocInfo()) {
1965 default: llvm_unreachable("Unknown loc info!");
1966 case CCValAssign::Full: break;
1967 case CCValAssign::SExt:
1968 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1970 case CCValAssign::ZExt:
1971 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1973 case CCValAssign::AExt:
1974 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1975 // Special case: passing MMX values in XMM registers.
1976 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1977 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1978 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1980 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1982 case CCValAssign::BCvt:
1983 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1985 case CCValAssign::Indirect: {
1986 // Store the argument.
1987 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1988 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1989 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1990 PseudoSourceValue::getFixedStack(FI), 0,
1997 if (VA.isRegLoc()) {
1998 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1999 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2000 assert(VA.isMemLoc());
2001 if (StackPtr.getNode() == 0)
2002 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2003 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2004 dl, DAG, VA, Flags));
2008 if (!MemOpChains.empty())
2009 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2010 &MemOpChains[0], MemOpChains.size());
2012 // Build a sequence of copy-to-reg nodes chained together with token chain
2013 // and flag operands which copy the outgoing args into registers.
2015 // Tail call byval lowering might overwrite argument registers so in case of
2016 // tail call optimization the copies to registers are lowered later.
2018 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2019 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2020 RegsToPass[i].second, InFlag);
2021 InFlag = Chain.getValue(1);
2024 if (Subtarget->isPICStyleGOT()) {
2025 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2028 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2029 DAG.getNode(X86ISD::GlobalBaseReg,
2030 DebugLoc(), getPointerTy()),
2032 InFlag = Chain.getValue(1);
2034 // If we are tail calling and generating PIC/GOT style code load the
2035 // address of the callee into ECX. The value in ecx is used as target of
2036 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2037 // for tail calls on PIC/GOT architectures. Normally we would just put the
2038 // address of GOT into ebx and then call target@PLT. But for tail calls
2039 // ebx would be restored (since ebx is callee saved) before jumping to the
2042 // Note: The actual moving to ECX is done further down.
2043 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2044 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2045 !G->getGlobal()->hasProtectedVisibility())
2046 Callee = LowerGlobalAddress(Callee, DAG);
2047 else if (isa<ExternalSymbolSDNode>(Callee))
2048 Callee = LowerExternalSymbol(Callee, DAG);
2052 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2053 // From AMD64 ABI document:
2054 // For calls that may call functions that use varargs or stdargs
2055 // (prototype-less calls or calls to functions containing ellipsis (...) in
2056 // the declaration) %al is used as hidden argument to specify the number
2057 // of SSE registers used. The contents of %al do not need to match exactly
2058 // the number of registers, but must be an ubound on the number of SSE
2059 // registers used and is in the range 0 - 8 inclusive.
2061 // Count the number of XMM registers allocated.
2062 static const unsigned XMMArgRegs[] = {
2063 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2064 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2066 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2067 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2068 && "SSE registers cannot be used when SSE is disabled");
2070 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2071 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2072 InFlag = Chain.getValue(1);
2076 // For tail calls lower the arguments to the 'real' stack slot.
2078 // Force all the incoming stack arguments to be loaded from the stack
2079 // before any new outgoing arguments are stored to the stack, because the
2080 // outgoing stack slots may alias the incoming argument stack slots, and
2081 // the alias isn't otherwise explicit. This is slightly more conservative
2082 // than necessary, because it means that each store effectively depends
2083 // on every argument instead of just those arguments it would clobber.
2084 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2086 SmallVector<SDValue, 8> MemOpChains2;
2089 // Do not flag preceeding copytoreg stuff together with the following stuff.
2091 if (GuaranteedTailCallOpt) {
2092 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2093 CCValAssign &VA = ArgLocs[i];
2096 assert(VA.isMemLoc());
2097 SDValue Arg = OutVals[i];
2098 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2099 // Create frame index.
2100 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2101 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2102 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2103 FIN = DAG.getFrameIndex(FI, getPointerTy());
2105 if (Flags.isByVal()) {
2106 // Copy relative to framepointer.
2107 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2108 if (StackPtr.getNode() == 0)
2109 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2111 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2113 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2117 // Store relative to framepointer.
2118 MemOpChains2.push_back(
2119 DAG.getStore(ArgChain, dl, Arg, FIN,
2120 PseudoSourceValue::getFixedStack(FI), 0,
2126 if (!MemOpChains2.empty())
2127 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2128 &MemOpChains2[0], MemOpChains2.size());
2130 // Copy arguments to their registers.
2131 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2132 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2133 RegsToPass[i].second, InFlag);
2134 InFlag = Chain.getValue(1);
2138 // Store the return address to the appropriate stack slot.
2139 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2143 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2144 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2145 // In the 64-bit large code model, we have to make all calls
2146 // through a register, since the call instruction's 32-bit
2147 // pc-relative offset may not be large enough to hold the whole
2149 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2150 // If the callee is a GlobalAddress node (quite common, every direct call
2151 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2154 // We should use extra load for direct calls to dllimported functions in
2156 const GlobalValue *GV = G->getGlobal();
2157 if (!GV->hasDLLImportLinkage()) {
2158 unsigned char OpFlags = 0;
2160 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2161 // external symbols most go through the PLT in PIC mode. If the symbol
2162 // has hidden or protected visibility, or if it is static or local, then
2163 // we don't need to use the PLT - we can directly call it.
2164 if (Subtarget->isTargetELF() &&
2165 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2166 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2167 OpFlags = X86II::MO_PLT;
2168 } else if (Subtarget->isPICStyleStubAny() &&
2169 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2170 Subtarget->getDarwinVers() < 9) {
2171 // PC-relative references to external symbols should go through $stub,
2172 // unless we're building with the leopard linker or later, which
2173 // automatically synthesizes these stubs.
2174 OpFlags = X86II::MO_DARWIN_STUB;
2177 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2178 G->getOffset(), OpFlags);
2180 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2181 unsigned char OpFlags = 0;
2183 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2184 // symbols should go through the PLT.
2185 if (Subtarget->isTargetELF() &&
2186 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2187 OpFlags = X86II::MO_PLT;
2188 } else if (Subtarget->isPICStyleStubAny() &&
2189 Subtarget->getDarwinVers() < 9) {
2190 // PC-relative references to external symbols should go through $stub,
2191 // unless we're building with the leopard linker or later, which
2192 // automatically synthesizes these stubs.
2193 OpFlags = X86II::MO_DARWIN_STUB;
2196 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2200 // Returns a chain & a flag for retval copy to use.
2201 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2202 SmallVector<SDValue, 8> Ops;
2204 if (!IsSibcall && isTailCall) {
2205 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2206 DAG.getIntPtrConstant(0, true), InFlag);
2207 InFlag = Chain.getValue(1);
2210 Ops.push_back(Chain);
2211 Ops.push_back(Callee);
2214 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2216 // Add argument registers to the end of the list so that they are known live
2218 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2219 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2220 RegsToPass[i].second.getValueType()));
2222 // Add an implicit use GOT pointer in EBX.
2223 if (!isTailCall && Subtarget->isPICStyleGOT())
2224 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2226 // Add an implicit use of AL for x86 vararg functions.
2227 if (Is64Bit && isVarArg)
2228 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2230 if (InFlag.getNode())
2231 Ops.push_back(InFlag);
2235 //// If this is the first return lowered for this function, add the regs
2236 //// to the liveout set for the function.
2237 // This isn't right, although it's probably harmless on x86; liveouts
2238 // should be computed from returns not tail calls. Consider a void
2239 // function making a tail call to a function returning int.
2240 return DAG.getNode(X86ISD::TC_RETURN, dl,
2241 NodeTys, &Ops[0], Ops.size());
2244 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2245 InFlag = Chain.getValue(1);
2247 // Create the CALLSEQ_END node.
2248 unsigned NumBytesForCalleeToPush;
2249 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2250 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2251 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2252 // If this is a call to a struct-return function, the callee
2253 // pops the hidden struct pointer, so we have to push it back.
2254 // This is common for Darwin/X86, Linux & Mingw32 targets.
2255 NumBytesForCalleeToPush = 4;
2257 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2259 // Returns a flag for retval copy to use.
2261 Chain = DAG.getCALLSEQ_END(Chain,
2262 DAG.getIntPtrConstant(NumBytes, true),
2263 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2266 InFlag = Chain.getValue(1);
2269 // Handle result values, copying them out of physregs into vregs that we
2271 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2272 Ins, dl, DAG, InVals);
2276 //===----------------------------------------------------------------------===//
2277 // Fast Calling Convention (tail call) implementation
2278 //===----------------------------------------------------------------------===//
2280 // Like std call, callee cleans arguments, convention except that ECX is
2281 // reserved for storing the tail called function address. Only 2 registers are
2282 // free for argument passing (inreg). Tail call optimization is performed
2284 // * tailcallopt is enabled
2285 // * caller/callee are fastcc
2286 // On X86_64 architecture with GOT-style position independent code only local
2287 // (within module) calls are supported at the moment.
2288 // To keep the stack aligned according to platform abi the function
2289 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2290 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2291 // If a tail called function callee has more arguments than the caller the
2292 // caller needs to make sure that there is room to move the RETADDR to. This is
2293 // achieved by reserving an area the size of the argument delta right after the
2294 // original REtADDR, but before the saved framepointer or the spilled registers
2295 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2307 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2308 /// for a 16 byte align requirement.
2310 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2311 SelectionDAG& DAG) const {
2312 MachineFunction &MF = DAG.getMachineFunction();
2313 const TargetMachine &TM = MF.getTarget();
2314 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2315 unsigned StackAlignment = TFI.getStackAlignment();
2316 uint64_t AlignMask = StackAlignment - 1;
2317 int64_t Offset = StackSize;
2318 uint64_t SlotSize = TD->getPointerSize();
2319 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2320 // Number smaller than 12 so just add the difference.
2321 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2323 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2324 Offset = ((~AlignMask) & Offset) + StackAlignment +
2325 (StackAlignment-SlotSize);
2330 /// MatchingStackOffset - Return true if the given stack call argument is
2331 /// already available in the same position (relatively) of the caller's
2332 /// incoming argument stack.
2334 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2335 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2336 const X86InstrInfo *TII) {
2337 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2339 if (Arg.getOpcode() == ISD::CopyFromReg) {
2340 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2341 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2343 MachineInstr *Def = MRI->getVRegDef(VR);
2346 if (!Flags.isByVal()) {
2347 if (!TII->isLoadFromStackSlot(Def, FI))
2350 unsigned Opcode = Def->getOpcode();
2351 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2352 Def->getOperand(1).isFI()) {
2353 FI = Def->getOperand(1).getIndex();
2354 Bytes = Flags.getByValSize();
2358 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2359 if (Flags.isByVal())
2360 // ByVal argument is passed in as a pointer but it's now being
2361 // dereferenced. e.g.
2362 // define @foo(%struct.X* %A) {
2363 // tail call @bar(%struct.X* byval %A)
2366 SDValue Ptr = Ld->getBasePtr();
2367 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2370 FI = FINode->getIndex();
2374 assert(FI != INT_MAX);
2375 if (!MFI->isFixedObjectIndex(FI))
2377 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2380 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2381 /// for tail call optimization. Targets which want to do tail call
2382 /// optimization should implement this function.
2384 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2385 CallingConv::ID CalleeCC,
2387 bool isCalleeStructRet,
2388 bool isCallerStructRet,
2389 const SmallVectorImpl<ISD::OutputArg> &Outs,
2390 const SmallVectorImpl<SDValue> &OutVals,
2391 const SmallVectorImpl<ISD::InputArg> &Ins,
2392 SelectionDAG& DAG) const {
2393 if (!IsTailCallConvention(CalleeCC) &&
2394 CalleeCC != CallingConv::C)
2397 // If -tailcallopt is specified, make fastcc functions tail-callable.
2398 const MachineFunction &MF = DAG.getMachineFunction();
2399 const Function *CallerF = DAG.getMachineFunction().getFunction();
2400 CallingConv::ID CallerCC = CallerF->getCallingConv();
2401 bool CCMatch = CallerCC == CalleeCC;
2403 if (GuaranteedTailCallOpt) {
2404 if (IsTailCallConvention(CalleeCC) && CCMatch)
2409 // Look for obvious safe cases to perform tail call optimization that do not
2410 // require ABI changes. This is what gcc calls sibcall.
2412 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2413 // emit a special epilogue.
2414 if (RegInfo->needsStackRealignment(MF))
2417 // Do not sibcall optimize vararg calls unless the call site is not passing
2419 if (isVarArg && !Outs.empty())
2422 // Also avoid sibcall optimization if either caller or callee uses struct
2423 // return semantics.
2424 if (isCalleeStructRet || isCallerStructRet)
2427 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2428 // Therefore if it's not used by the call it is not safe to optimize this into
2430 bool Unused = false;
2431 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2438 SmallVector<CCValAssign, 16> RVLocs;
2439 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2440 RVLocs, *DAG.getContext());
2441 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2442 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2443 CCValAssign &VA = RVLocs[i];
2444 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2449 // If the calling conventions do not match, then we'd better make sure the
2450 // results are returned in the same way as what the caller expects.
2452 SmallVector<CCValAssign, 16> RVLocs1;
2453 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2454 RVLocs1, *DAG.getContext());
2455 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2457 SmallVector<CCValAssign, 16> RVLocs2;
2458 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2459 RVLocs2, *DAG.getContext());
2460 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2462 if (RVLocs1.size() != RVLocs2.size())
2464 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2465 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2467 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2469 if (RVLocs1[i].isRegLoc()) {
2470 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2473 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2479 // If the callee takes no arguments then go on to check the results of the
2481 if (!Outs.empty()) {
2482 // Check if stack adjustment is needed. For now, do not do this if any
2483 // argument is passed on the stack.
2484 SmallVector<CCValAssign, 16> ArgLocs;
2485 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2486 ArgLocs, *DAG.getContext());
2487 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2488 if (CCInfo.getNextStackOffset()) {
2489 MachineFunction &MF = DAG.getMachineFunction();
2490 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2492 if (Subtarget->isTargetWin64())
2493 // Win64 ABI has additional complications.
2496 // Check if the arguments are already laid out in the right way as
2497 // the caller's fixed stack objects.
2498 MachineFrameInfo *MFI = MF.getFrameInfo();
2499 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2500 const X86InstrInfo *TII =
2501 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2503 CCValAssign &VA = ArgLocs[i];
2504 SDValue Arg = OutVals[i];
2505 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2506 if (VA.getLocInfo() == CCValAssign::Indirect)
2508 if (!VA.isRegLoc()) {
2509 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2516 // If the tailcall address may be in a register, then make sure it's
2517 // possible to register allocate for it. In 32-bit, the call address can
2518 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2519 // callee-saved registers are restored. These happen to be the same
2520 // registers used to pass 'inreg' arguments so watch out for those.
2521 if (!Subtarget->is64Bit() &&
2522 !isa<GlobalAddressSDNode>(Callee) &&
2523 !isa<ExternalSymbolSDNode>(Callee)) {
2524 unsigned NumInRegs = 0;
2525 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2526 CCValAssign &VA = ArgLocs[i];
2529 unsigned Reg = VA.getLocReg();
2532 case X86::EAX: case X86::EDX: case X86::ECX:
2533 if (++NumInRegs == 3)
2545 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2546 return X86::createFastISel(funcInfo);
2550 //===----------------------------------------------------------------------===//
2551 // Other Lowering Hooks
2552 //===----------------------------------------------------------------------===//
2555 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2556 MachineFunction &MF = DAG.getMachineFunction();
2557 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2558 int ReturnAddrIndex = FuncInfo->getRAIndex();
2560 if (ReturnAddrIndex == 0) {
2561 // Set up a frame object for the return address.
2562 uint64_t SlotSize = TD->getPointerSize();
2563 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2565 FuncInfo->setRAIndex(ReturnAddrIndex);
2568 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2572 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2573 bool hasSymbolicDisplacement) {
2574 // Offset should fit into 32 bit immediate field.
2575 if (!isInt<32>(Offset))
2578 // If we don't have a symbolic displacement - we don't have any extra
2580 if (!hasSymbolicDisplacement)
2583 // FIXME: Some tweaks might be needed for medium code model.
2584 if (M != CodeModel::Small && M != CodeModel::Kernel)
2587 // For small code model we assume that latest object is 16MB before end of 31
2588 // bits boundary. We may also accept pretty large negative constants knowing
2589 // that all objects are in the positive half of address space.
2590 if (M == CodeModel::Small && Offset < 16*1024*1024)
2593 // For kernel code model we know that all object resist in the negative half
2594 // of 32bits address space. We may not accept negative offsets, since they may
2595 // be just off and we may accept pretty large positive ones.
2596 if (M == CodeModel::Kernel && Offset > 0)
2602 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2603 /// specific condition code, returning the condition code and the LHS/RHS of the
2604 /// comparison to make.
2605 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2606 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2608 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2609 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2610 // X > -1 -> X == 0, jump !sign.
2611 RHS = DAG.getConstant(0, RHS.getValueType());
2612 return X86::COND_NS;
2613 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2614 // X < 0 -> X == 0, jump on sign.
2616 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2618 RHS = DAG.getConstant(0, RHS.getValueType());
2619 return X86::COND_LE;
2623 switch (SetCCOpcode) {
2624 default: llvm_unreachable("Invalid integer condition!");
2625 case ISD::SETEQ: return X86::COND_E;
2626 case ISD::SETGT: return X86::COND_G;
2627 case ISD::SETGE: return X86::COND_GE;
2628 case ISD::SETLT: return X86::COND_L;
2629 case ISD::SETLE: return X86::COND_LE;
2630 case ISD::SETNE: return X86::COND_NE;
2631 case ISD::SETULT: return X86::COND_B;
2632 case ISD::SETUGT: return X86::COND_A;
2633 case ISD::SETULE: return X86::COND_BE;
2634 case ISD::SETUGE: return X86::COND_AE;
2638 // First determine if it is required or is profitable to flip the operands.
2640 // If LHS is a foldable load, but RHS is not, flip the condition.
2641 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2642 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2643 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2644 std::swap(LHS, RHS);
2647 switch (SetCCOpcode) {
2653 std::swap(LHS, RHS);
2657 // On a floating point condition, the flags are set as follows:
2659 // 0 | 0 | 0 | X > Y
2660 // 0 | 0 | 1 | X < Y
2661 // 1 | 0 | 0 | X == Y
2662 // 1 | 1 | 1 | unordered
2663 switch (SetCCOpcode) {
2664 default: llvm_unreachable("Condcode should be pre-legalized away");
2666 case ISD::SETEQ: return X86::COND_E;
2667 case ISD::SETOLT: // flipped
2669 case ISD::SETGT: return X86::COND_A;
2670 case ISD::SETOLE: // flipped
2672 case ISD::SETGE: return X86::COND_AE;
2673 case ISD::SETUGT: // flipped
2675 case ISD::SETLT: return X86::COND_B;
2676 case ISD::SETUGE: // flipped
2678 case ISD::SETLE: return X86::COND_BE;
2680 case ISD::SETNE: return X86::COND_NE;
2681 case ISD::SETUO: return X86::COND_P;
2682 case ISD::SETO: return X86::COND_NP;
2684 case ISD::SETUNE: return X86::COND_INVALID;
2688 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2689 /// code. Current x86 isa includes the following FP cmov instructions:
2690 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2691 static bool hasFPCMov(unsigned X86CC) {
2707 /// isFPImmLegal - Returns true if the target can instruction select the
2708 /// specified FP immediate natively. If false, the legalizer will
2709 /// materialize the FP immediate as a load from a constant pool.
2710 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2711 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2712 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2718 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2719 /// the specified range (L, H].
2720 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2721 return (Val < 0) || (Val >= Low && Val < Hi);
2724 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2725 /// specified value.
2726 static bool isUndefOrEqual(int Val, int CmpVal) {
2727 if (Val < 0 || Val == CmpVal)
2732 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2733 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2734 /// the second operand.
2735 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2736 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2737 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2738 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2739 return (Mask[0] < 2 && Mask[1] < 2);
2743 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2744 SmallVector<int, 8> M;
2746 return ::isPSHUFDMask(M, N->getValueType(0));
2749 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2750 /// is suitable for input to PSHUFHW.
2751 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2752 if (VT != MVT::v8i16)
2755 // Lower quadword copied in order or undef.
2756 for (int i = 0; i != 4; ++i)
2757 if (Mask[i] >= 0 && Mask[i] != i)
2760 // Upper quadword shuffled.
2761 for (int i = 4; i != 8; ++i)
2762 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2768 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2769 SmallVector<int, 8> M;
2771 return ::isPSHUFHWMask(M, N->getValueType(0));
2774 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2775 /// is suitable for input to PSHUFLW.
2776 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2777 if (VT != MVT::v8i16)
2780 // Upper quadword copied in order.
2781 for (int i = 4; i != 8; ++i)
2782 if (Mask[i] >= 0 && Mask[i] != i)
2785 // Lower quadword shuffled.
2786 for (int i = 0; i != 4; ++i)
2793 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2794 SmallVector<int, 8> M;
2796 return ::isPSHUFLWMask(M, N->getValueType(0));
2799 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2800 /// is suitable for input to PALIGNR.
2801 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2803 int i, e = VT.getVectorNumElements();
2805 // Do not handle v2i64 / v2f64 shuffles with palignr.
2806 if (e < 4 || !hasSSSE3)
2809 for (i = 0; i != e; ++i)
2813 // All undef, not a palignr.
2817 // Determine if it's ok to perform a palignr with only the LHS, since we
2818 // don't have access to the actual shuffle elements to see if RHS is undef.
2819 bool Unary = Mask[i] < (int)e;
2820 bool NeedsUnary = false;
2822 int s = Mask[i] - i;
2824 // Check the rest of the elements to see if they are consecutive.
2825 for (++i; i != e; ++i) {
2830 Unary = Unary && (m < (int)e);
2831 NeedsUnary = NeedsUnary || (m < s);
2833 if (NeedsUnary && !Unary)
2835 if (Unary && m != ((s+i) & (e-1)))
2837 if (!Unary && m != (s+i))
2843 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2844 SmallVector<int, 8> M;
2846 return ::isPALIGNRMask(M, N->getValueType(0), true);
2849 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2850 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2851 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2852 int NumElems = VT.getVectorNumElements();
2853 if (NumElems != 2 && NumElems != 4)
2856 int Half = NumElems / 2;
2857 for (int i = 0; i < Half; ++i)
2858 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2860 for (int i = Half; i < NumElems; ++i)
2861 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2867 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2868 SmallVector<int, 8> M;
2870 return ::isSHUFPMask(M, N->getValueType(0));
2873 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2874 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2875 /// half elements to come from vector 1 (which would equal the dest.) and
2876 /// the upper half to come from vector 2.
2877 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2878 int NumElems = VT.getVectorNumElements();
2880 if (NumElems != 2 && NumElems != 4)
2883 int Half = NumElems / 2;
2884 for (int i = 0; i < Half; ++i)
2885 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2887 for (int i = Half; i < NumElems; ++i)
2888 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2893 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2894 SmallVector<int, 8> M;
2896 return isCommutedSHUFPMask(M, N->getValueType(0));
2899 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2900 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2901 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2902 if (N->getValueType(0).getVectorNumElements() != 4)
2905 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2906 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2907 isUndefOrEqual(N->getMaskElt(1), 7) &&
2908 isUndefOrEqual(N->getMaskElt(2), 2) &&
2909 isUndefOrEqual(N->getMaskElt(3), 3);
2912 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2913 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2915 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2916 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2921 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2922 isUndefOrEqual(N->getMaskElt(1), 3) &&
2923 isUndefOrEqual(N->getMaskElt(2), 2) &&
2924 isUndefOrEqual(N->getMaskElt(3), 3);
2927 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2928 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2929 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2930 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2932 if (NumElems != 2 && NumElems != 4)
2935 for (unsigned i = 0; i < NumElems/2; ++i)
2936 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2939 for (unsigned i = NumElems/2; i < NumElems; ++i)
2940 if (!isUndefOrEqual(N->getMaskElt(i), i))
2946 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2947 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2948 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2949 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2951 if (NumElems != 2 && NumElems != 4)
2954 for (unsigned i = 0; i < NumElems/2; ++i)
2955 if (!isUndefOrEqual(N->getMaskElt(i), i))
2958 for (unsigned i = 0; i < NumElems/2; ++i)
2959 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2965 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2966 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2967 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2968 bool V2IsSplat = false) {
2969 int NumElts = VT.getVectorNumElements();
2970 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2973 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2975 int BitI1 = Mask[i+1];
2976 if (!isUndefOrEqual(BitI, j))
2979 if (!isUndefOrEqual(BitI1, NumElts))
2982 if (!isUndefOrEqual(BitI1, j + NumElts))
2989 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2990 SmallVector<int, 8> M;
2992 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2995 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2996 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2997 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2998 bool V2IsSplat = false) {
2999 int NumElts = VT.getVectorNumElements();
3000 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3003 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3005 int BitI1 = Mask[i+1];
3006 if (!isUndefOrEqual(BitI, j + NumElts/2))
3009 if (isUndefOrEqual(BitI1, NumElts))
3012 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3019 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3020 SmallVector<int, 8> M;
3022 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3025 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3026 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3028 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3029 int NumElems = VT.getVectorNumElements();
3030 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3033 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3035 int BitI1 = Mask[i+1];
3036 if (!isUndefOrEqual(BitI, j))
3038 if (!isUndefOrEqual(BitI1, j))
3044 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3045 SmallVector<int, 8> M;
3047 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3050 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3051 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3053 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3054 int NumElems = VT.getVectorNumElements();
3055 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3058 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3060 int BitI1 = Mask[i+1];
3061 if (!isUndefOrEqual(BitI, j))
3063 if (!isUndefOrEqual(BitI1, j))
3069 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3070 SmallVector<int, 8> M;
3072 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3075 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3076 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3077 /// MOVSD, and MOVD, i.e. setting the lowest element.
3078 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3079 if (VT.getVectorElementType().getSizeInBits() < 32)
3082 int NumElts = VT.getVectorNumElements();
3084 if (!isUndefOrEqual(Mask[0], NumElts))
3087 for (int i = 1; i < NumElts; ++i)
3088 if (!isUndefOrEqual(Mask[i], i))
3094 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3095 SmallVector<int, 8> M;
3097 return ::isMOVLMask(M, N->getValueType(0));
3100 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3101 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3102 /// element of vector 2 and the other elements to come from vector 1 in order.
3103 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3104 bool V2IsSplat = false, bool V2IsUndef = false) {
3105 int NumOps = VT.getVectorNumElements();
3106 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3109 if (!isUndefOrEqual(Mask[0], 0))
3112 for (int i = 1; i < NumOps; ++i)
3113 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3114 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3115 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3121 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3122 bool V2IsUndef = false) {
3123 SmallVector<int, 8> M;
3125 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3128 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3129 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3130 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3131 if (N->getValueType(0).getVectorNumElements() != 4)
3134 // Expect 1, 1, 3, 3
3135 for (unsigned i = 0; i < 2; ++i) {
3136 int Elt = N->getMaskElt(i);
3137 if (Elt >= 0 && Elt != 1)
3142 for (unsigned i = 2; i < 4; ++i) {
3143 int Elt = N->getMaskElt(i);
3144 if (Elt >= 0 && Elt != 3)
3149 // Don't use movshdup if it can be done with a shufps.
3150 // FIXME: verify that matching u, u, 3, 3 is what we want.
3154 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3155 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3156 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3157 if (N->getValueType(0).getVectorNumElements() != 4)
3160 // Expect 0, 0, 2, 2
3161 for (unsigned i = 0; i < 2; ++i)
3162 if (N->getMaskElt(i) > 0)
3166 for (unsigned i = 2; i < 4; ++i) {
3167 int Elt = N->getMaskElt(i);
3168 if (Elt >= 0 && Elt != 2)
3173 // Don't use movsldup if it can be done with a shufps.
3177 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3178 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3179 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3180 int e = N->getValueType(0).getVectorNumElements() / 2;
3182 for (int i = 0; i < e; ++i)
3183 if (!isUndefOrEqual(N->getMaskElt(i), i))
3185 for (int i = 0; i < e; ++i)
3186 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3191 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3192 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3193 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3194 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3195 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3197 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3199 for (int i = 0; i < NumOperands; ++i) {
3200 int Val = SVOp->getMaskElt(NumOperands-i-1);
3201 if (Val < 0) Val = 0;
3202 if (Val >= NumOperands) Val -= NumOperands;
3204 if (i != NumOperands - 1)
3210 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3211 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3212 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3213 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3215 // 8 nodes, but we only care about the last 4.
3216 for (unsigned i = 7; i >= 4; --i) {
3217 int Val = SVOp->getMaskElt(i);
3226 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3227 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3228 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3229 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3231 // 8 nodes, but we only care about the first 4.
3232 for (int i = 3; i >= 0; --i) {
3233 int Val = SVOp->getMaskElt(i);
3242 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3243 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3244 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3245 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3246 EVT VVT = N->getValueType(0);
3247 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3251 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3252 Val = SVOp->getMaskElt(i);
3256 return (Val - i) * EltSize;
3259 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3261 bool X86::isZeroNode(SDValue Elt) {
3262 return ((isa<ConstantSDNode>(Elt) &&
3263 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3264 (isa<ConstantFPSDNode>(Elt) &&
3265 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3268 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3269 /// their permute mask.
3270 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3271 SelectionDAG &DAG) {
3272 EVT VT = SVOp->getValueType(0);
3273 unsigned NumElems = VT.getVectorNumElements();
3274 SmallVector<int, 8> MaskVec;
3276 for (unsigned i = 0; i != NumElems; ++i) {
3277 int idx = SVOp->getMaskElt(i);
3279 MaskVec.push_back(idx);
3280 else if (idx < (int)NumElems)
3281 MaskVec.push_back(idx + NumElems);
3283 MaskVec.push_back(idx - NumElems);
3285 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3286 SVOp->getOperand(0), &MaskVec[0]);
3289 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3290 /// the two vector operands have swapped position.
3291 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3292 unsigned NumElems = VT.getVectorNumElements();
3293 for (unsigned i = 0; i != NumElems; ++i) {
3297 else if (idx < (int)NumElems)
3298 Mask[i] = idx + NumElems;
3300 Mask[i] = idx - NumElems;
3304 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3305 /// match movhlps. The lower half elements should come from upper half of
3306 /// V1 (and in order), and the upper half elements should come from the upper
3307 /// half of V2 (and in order).
3308 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3309 if (Op->getValueType(0).getVectorNumElements() != 4)
3311 for (unsigned i = 0, e = 2; i != e; ++i)
3312 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3314 for (unsigned i = 2; i != 4; ++i)
3315 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3320 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3321 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3323 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3324 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3326 N = N->getOperand(0).getNode();
3327 if (!ISD::isNON_EXTLoad(N))
3330 *LD = cast<LoadSDNode>(N);
3334 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3335 /// match movlp{s|d}. The lower half elements should come from lower half of
3336 /// V1 (and in order), and the upper half elements should come from the upper
3337 /// half of V2 (and in order). And since V1 will become the source of the
3338 /// MOVLP, it must be either a vector load or a scalar load to vector.
3339 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3340 ShuffleVectorSDNode *Op) {
3341 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3343 // Is V2 is a vector load, don't do this transformation. We will try to use
3344 // load folding shufps op.
3345 if (ISD::isNON_EXTLoad(V2))
3348 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3350 if (NumElems != 2 && NumElems != 4)
3352 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3353 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3355 for (unsigned i = NumElems/2; i != NumElems; ++i)
3356 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3361 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3363 static bool isSplatVector(SDNode *N) {
3364 if (N->getOpcode() != ISD::BUILD_VECTOR)
3367 SDValue SplatValue = N->getOperand(0);
3368 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3369 if (N->getOperand(i) != SplatValue)
3374 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3375 /// to an zero vector.
3376 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3377 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3378 SDValue V1 = N->getOperand(0);
3379 SDValue V2 = N->getOperand(1);
3380 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3381 for (unsigned i = 0; i != NumElems; ++i) {
3382 int Idx = N->getMaskElt(i);
3383 if (Idx >= (int)NumElems) {
3384 unsigned Opc = V2.getOpcode();
3385 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3387 if (Opc != ISD::BUILD_VECTOR ||
3388 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3390 } else if (Idx >= 0) {
3391 unsigned Opc = V1.getOpcode();
3392 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3394 if (Opc != ISD::BUILD_VECTOR ||
3395 !X86::isZeroNode(V1.getOperand(Idx)))
3402 /// getZeroVector - Returns a vector of specified type with all zero elements.
3404 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3406 assert(VT.isVector() && "Expected a vector type");
3408 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3409 // type. This ensures they get CSE'd.
3411 if (VT.getSizeInBits() == 64) { // MMX
3412 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3413 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3414 } else if (HasSSE2) { // SSE2
3415 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3416 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3418 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3419 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3421 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3424 /// getOnesVector - Returns a vector of specified type with all bits set.
3426 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3427 assert(VT.isVector() && "Expected a vector type");
3429 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3430 // type. This ensures they get CSE'd.
3431 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3433 if (VT.getSizeInBits() == 64) // MMX
3434 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3436 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3437 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3441 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3442 /// that point to V2 points to its first element.
3443 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3444 EVT VT = SVOp->getValueType(0);
3445 unsigned NumElems = VT.getVectorNumElements();
3447 bool Changed = false;
3448 SmallVector<int, 8> MaskVec;
3449 SVOp->getMask(MaskVec);
3451 for (unsigned i = 0; i != NumElems; ++i) {
3452 if (MaskVec[i] > (int)NumElems) {
3453 MaskVec[i] = NumElems;
3458 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3459 SVOp->getOperand(1), &MaskVec[0]);
3460 return SDValue(SVOp, 0);
3463 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3464 /// operation of specified width.
3465 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3467 unsigned NumElems = VT.getVectorNumElements();
3468 SmallVector<int, 8> Mask;
3469 Mask.push_back(NumElems);
3470 for (unsigned i = 1; i != NumElems; ++i)
3472 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3475 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3476 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3478 unsigned NumElems = VT.getVectorNumElements();
3479 SmallVector<int, 8> Mask;
3480 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3482 Mask.push_back(i + NumElems);
3484 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3487 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3488 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3490 unsigned NumElems = VT.getVectorNumElements();
3491 unsigned Half = NumElems/2;
3492 SmallVector<int, 8> Mask;
3493 for (unsigned i = 0; i != Half; ++i) {
3494 Mask.push_back(i + Half);
3495 Mask.push_back(i + NumElems + Half);
3497 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3500 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3501 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3503 if (SV->getValueType(0).getVectorNumElements() <= 4)
3504 return SDValue(SV, 0);
3506 EVT PVT = MVT::v4f32;
3507 EVT VT = SV->getValueType(0);
3508 DebugLoc dl = SV->getDebugLoc();
3509 SDValue V1 = SV->getOperand(0);
3510 int NumElems = VT.getVectorNumElements();
3511 int EltNo = SV->getSplatIndex();
3513 // unpack elements to the correct location
3514 while (NumElems > 4) {
3515 if (EltNo < NumElems/2) {
3516 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3518 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3519 EltNo -= NumElems/2;
3524 // Perform the splat.
3525 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3526 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3527 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3528 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3531 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3532 /// vector of zero or undef vector. This produces a shuffle where the low
3533 /// element of V2 is swizzled into the zero/undef vector, landing at element
3534 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3535 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3536 bool isZero, bool HasSSE2,
3537 SelectionDAG &DAG) {
3538 EVT VT = V2.getValueType();
3540 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3541 unsigned NumElems = VT.getVectorNumElements();
3542 SmallVector<int, 16> MaskVec;
3543 for (unsigned i = 0; i != NumElems; ++i)
3544 // If this is the insertion idx, put the low elt of V2 here.
3545 MaskVec.push_back(i == Idx ? NumElems : i);
3546 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3549 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3550 /// a shuffle that is zero.
3552 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3553 bool Low, SelectionDAG &DAG) {
3554 unsigned NumZeros = 0;
3555 for (int i = 0; i < NumElems; ++i) {
3556 unsigned Index = Low ? i : NumElems-i-1;
3557 int Idx = SVOp->getMaskElt(Index);
3562 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3563 if (Elt.getNode() && X86::isZeroNode(Elt))
3571 /// isVectorShift - Returns true if the shuffle can be implemented as a
3572 /// logical left or right shift of a vector.
3573 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3574 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3575 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3576 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3579 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3582 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3586 bool SeenV1 = false;
3587 bool SeenV2 = false;
3588 for (unsigned i = NumZeros; i < NumElems; ++i) {
3589 unsigned Val = isLeft ? (i - NumZeros) : i;
3590 int Idx_ = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3593 unsigned Idx = (unsigned) Idx_;
3603 if (SeenV1 && SeenV2)
3606 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3612 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3614 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3615 unsigned NumNonZero, unsigned NumZero,
3617 const TargetLowering &TLI) {
3621 DebugLoc dl = Op.getDebugLoc();
3624 for (unsigned i = 0; i < 16; ++i) {
3625 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3626 if (ThisIsNonZero && First) {
3628 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3630 V = DAG.getUNDEF(MVT::v8i16);
3635 SDValue ThisElt(0, 0), LastElt(0, 0);
3636 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3637 if (LastIsNonZero) {
3638 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3639 MVT::i16, Op.getOperand(i-1));
3641 if (ThisIsNonZero) {
3642 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3643 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3644 ThisElt, DAG.getConstant(8, MVT::i8));
3646 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3650 if (ThisElt.getNode())
3651 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3652 DAG.getIntPtrConstant(i/2));
3656 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3659 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3661 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3662 unsigned NumNonZero, unsigned NumZero,
3664 const TargetLowering &TLI) {
3668 DebugLoc dl = Op.getDebugLoc();
3671 for (unsigned i = 0; i < 8; ++i) {
3672 bool isNonZero = (NonZeros & (1 << i)) != 0;
3676 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3678 V = DAG.getUNDEF(MVT::v8i16);
3681 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3682 MVT::v8i16, V, Op.getOperand(i),
3683 DAG.getIntPtrConstant(i));
3690 /// getVShift - Return a vector logical shift node.
3692 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3693 unsigned NumBits, SelectionDAG &DAG,
3694 const TargetLowering &TLI, DebugLoc dl) {
3695 bool isMMX = VT.getSizeInBits() == 64;
3696 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3697 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3698 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3699 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3700 DAG.getNode(Opc, dl, ShVT, SrcOp,
3701 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3705 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3706 SelectionDAG &DAG) const {
3708 // Check if the scalar load can be widened into a vector load. And if
3709 // the address is "base + cst" see if the cst can be "absorbed" into
3710 // the shuffle mask.
3711 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3712 SDValue Ptr = LD->getBasePtr();
3713 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3715 EVT PVT = LD->getValueType(0);
3716 if (PVT != MVT::i32 && PVT != MVT::f32)
3721 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3722 FI = FINode->getIndex();
3724 } else if (Ptr.getOpcode() == ISD::ADD &&
3725 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3726 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3727 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3728 Offset = Ptr.getConstantOperandVal(1);
3729 Ptr = Ptr.getOperand(0);
3734 SDValue Chain = LD->getChain();
3735 // Make sure the stack object alignment is at least 16.
3736 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3737 if (DAG.InferPtrAlignment(Ptr) < 16) {
3738 if (MFI->isFixedObjectIndex(FI)) {
3739 // Can't change the alignment. FIXME: It's possible to compute
3740 // the exact stack offset and reference FI + adjust offset instead.
3741 // If someone *really* cares about this. That's the way to implement it.
3744 MFI->setObjectAlignment(FI, 16);
3748 // (Offset % 16) must be multiple of 4. Then address is then
3749 // Ptr + (Offset & ~15).
3752 if ((Offset % 16) & 3)
3754 int64_t StartOffset = Offset & ~15;
3756 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3757 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3759 int EltNo = (Offset - StartOffset) >> 2;
3760 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3761 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3762 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3764 // Canonicalize it to a v4i32 shuffle.
3765 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3766 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3767 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3768 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3774 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
3775 /// vector of type 'VT', see if the elements can be replaced by a single large
3776 /// load which has the same value as a build_vector whose operands are 'elts'.
3778 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
3780 /// FIXME: we'd also like to handle the case where the last elements are zero
3781 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
3782 /// There's even a handy isZeroNode for that purpose.
3783 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
3784 DebugLoc &dl, SelectionDAG &DAG) {
3785 EVT EltVT = VT.getVectorElementType();
3786 unsigned NumElems = Elts.size();
3788 LoadSDNode *LDBase = NULL;
3789 unsigned LastLoadedElt = -1U;
3791 // For each element in the initializer, see if we've found a load or an undef.
3792 // If we don't find an initial load element, or later load elements are
3793 // non-consecutive, bail out.
3794 for (unsigned i = 0; i < NumElems; ++i) {
3795 SDValue Elt = Elts[i];
3797 if (!Elt.getNode() ||
3798 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
3801 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
3803 LDBase = cast<LoadSDNode>(Elt.getNode());
3807 if (Elt.getOpcode() == ISD::UNDEF)
3810 LoadSDNode *LD = cast<LoadSDNode>(Elt);
3811 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
3816 // If we have found an entire vector of loads and undefs, then return a large
3817 // load of the entire vector width starting at the base pointer. If we found
3818 // consecutive loads for the low half, generate a vzext_load node.
3819 if (LastLoadedElt == NumElems - 1) {
3820 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
3821 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3822 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3823 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
3824 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3825 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3826 LDBase->isVolatile(), LDBase->isNonTemporal(),
3827 LDBase->getAlignment());
3828 } else if (NumElems == 4 && LastLoadedElt == 1) {
3829 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
3830 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
3831 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
3832 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
3838 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
3839 DebugLoc dl = Op.getDebugLoc();
3840 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3841 if (ISD::isBuildVectorAllZeros(Op.getNode())
3842 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3843 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3844 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3845 // eliminated on x86-32 hosts.
3846 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3849 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3850 return getOnesVector(Op.getValueType(), DAG, dl);
3851 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3854 EVT VT = Op.getValueType();
3855 EVT ExtVT = VT.getVectorElementType();
3856 unsigned EVTBits = ExtVT.getSizeInBits();
3858 unsigned NumElems = Op.getNumOperands();
3859 unsigned NumZero = 0;
3860 unsigned NumNonZero = 0;
3861 unsigned NonZeros = 0;
3862 bool IsAllConstants = true;
3863 SmallSet<SDValue, 8> Values;
3864 for (unsigned i = 0; i < NumElems; ++i) {
3865 SDValue Elt = Op.getOperand(i);
3866 if (Elt.getOpcode() == ISD::UNDEF)
3869 if (Elt.getOpcode() != ISD::Constant &&
3870 Elt.getOpcode() != ISD::ConstantFP)
3871 IsAllConstants = false;
3872 if (X86::isZeroNode(Elt))
3875 NonZeros |= (1 << i);
3880 if (NumNonZero == 0) {
3881 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3882 return DAG.getUNDEF(VT);
3885 // Special case for single non-zero, non-undef, element.
3886 if (NumNonZero == 1) {
3887 unsigned Idx = CountTrailingZeros_32(NonZeros);
3888 SDValue Item = Op.getOperand(Idx);
3890 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3891 // the value are obviously zero, truncate the value to i32 and do the
3892 // insertion that way. Only do this if the value is non-constant or if the
3893 // value is a constant being inserted into element 0. It is cheaper to do
3894 // a constant pool load than it is to do a movd + shuffle.
3895 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3896 (!IsAllConstants || Idx == 0)) {
3897 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3898 // Handle MMX and SSE both.
3899 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3900 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3902 // Truncate the value (which may itself be a constant) to i32, and
3903 // convert it to a vector with movd (S2V+shuffle to zero extend).
3904 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3905 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3906 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3907 Subtarget->hasSSE2(), DAG);
3909 // Now we have our 32-bit value zero extended in the low element of
3910 // a vector. If Idx != 0, swizzle it into place.
3912 SmallVector<int, 4> Mask;
3913 Mask.push_back(Idx);
3914 for (unsigned i = 1; i != VecElts; ++i)
3916 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3917 DAG.getUNDEF(Item.getValueType()),
3920 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3924 // If we have a constant or non-constant insertion into the low element of
3925 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3926 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3927 // depending on what the source datatype is.
3930 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3931 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3932 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3933 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3934 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3935 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3937 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3938 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3939 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3940 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3941 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3942 Subtarget->hasSSE2(), DAG);
3943 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3947 // Is it a vector logical left shift?
3948 if (NumElems == 2 && Idx == 1 &&
3949 X86::isZeroNode(Op.getOperand(0)) &&
3950 !X86::isZeroNode(Op.getOperand(1))) {
3951 unsigned NumBits = VT.getSizeInBits();
3952 return getVShift(true, VT,
3953 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3954 VT, Op.getOperand(1)),
3955 NumBits/2, DAG, *this, dl);
3958 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3961 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3962 // is a non-constant being inserted into an element other than the low one,
3963 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3964 // movd/movss) to move this into the low element, then shuffle it into
3966 if (EVTBits == 32) {
3967 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3969 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3970 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3971 Subtarget->hasSSE2(), DAG);
3972 SmallVector<int, 8> MaskVec;
3973 for (unsigned i = 0; i < NumElems; i++)
3974 MaskVec.push_back(i == Idx ? 0 : 1);
3975 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3979 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3980 if (Values.size() == 1) {
3981 if (EVTBits == 32) {
3982 // Instead of a shuffle like this:
3983 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3984 // Check if it's possible to issue this instead.
3985 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3986 unsigned Idx = CountTrailingZeros_32(NonZeros);
3987 SDValue Item = Op.getOperand(Idx);
3988 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3989 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3994 // A vector full of immediates; various special cases are already
3995 // handled, so this is best done with a single constant-pool load.
3999 // Let legalizer expand 2-wide build_vectors.
4000 if (EVTBits == 64) {
4001 if (NumNonZero == 1) {
4002 // One half is zero or undef.
4003 unsigned Idx = CountTrailingZeros_32(NonZeros);
4004 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4005 Op.getOperand(Idx));
4006 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4007 Subtarget->hasSSE2(), DAG);
4012 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4013 if (EVTBits == 8 && NumElems == 16) {
4014 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4016 if (V.getNode()) return V;
4019 if (EVTBits == 16 && NumElems == 8) {
4020 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4022 if (V.getNode()) return V;
4025 // If element VT is == 32 bits, turn it into a number of shuffles.
4026 SmallVector<SDValue, 8> V;
4028 if (NumElems == 4 && NumZero > 0) {
4029 for (unsigned i = 0; i < 4; ++i) {
4030 bool isZero = !(NonZeros & (1 << i));
4032 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4034 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4037 for (unsigned i = 0; i < 2; ++i) {
4038 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4041 V[i] = V[i*2]; // Must be a zero vector.
4044 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4047 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4050 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4055 SmallVector<int, 8> MaskVec;
4056 bool Reverse = (NonZeros & 0x3) == 2;
4057 for (unsigned i = 0; i < 2; ++i)
4058 MaskVec.push_back(Reverse ? 1-i : i);
4059 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4060 for (unsigned i = 0; i < 2; ++i)
4061 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4062 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4065 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4066 // Check for a build vector of consecutive loads.
4067 for (unsigned i = 0; i < NumElems; ++i)
4068 V[i] = Op.getOperand(i);
4070 // Check for elements which are consecutive loads.
4071 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4075 // For SSE 4.1, use inserts into undef.
4076 if (getSubtarget()->hasSSE41()) {
4077 V[0] = DAG.getUNDEF(VT);
4078 for (unsigned i = 0; i < NumElems; ++i)
4079 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4080 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
4081 Op.getOperand(i), DAG.getIntPtrConstant(i));
4085 // Otherwise, expand into a number of unpckl*
4087 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4088 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4089 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4090 for (unsigned i = 0; i < NumElems; ++i)
4091 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4093 while (NumElems != 0) {
4094 for (unsigned i = 0; i < NumElems; ++i)
4095 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
4104 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4105 // We support concatenate two MMX registers and place them in a MMX
4106 // register. This is better than doing a stack convert.
4107 DebugLoc dl = Op.getDebugLoc();
4108 EVT ResVT = Op.getValueType();
4109 assert(Op.getNumOperands() == 2);
4110 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4111 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4113 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4114 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4115 InVec = Op.getOperand(1);
4116 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4117 unsigned NumElts = ResVT.getVectorNumElements();
4118 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4119 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4120 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4122 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4123 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4124 Mask[0] = 0; Mask[1] = 2;
4125 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4127 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4130 // v8i16 shuffles - Prefer shuffles in the following order:
4131 // 1. [all] pshuflw, pshufhw, optional move
4132 // 2. [ssse3] 1 x pshufb
4133 // 3. [ssse3] 2 x pshufb + 1 x por
4134 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4136 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
4138 const X86TargetLowering &TLI) {
4139 SDValue V1 = SVOp->getOperand(0);
4140 SDValue V2 = SVOp->getOperand(1);
4141 DebugLoc dl = SVOp->getDebugLoc();
4142 SmallVector<int, 8> MaskVals;
4144 // Determine if more than 1 of the words in each of the low and high quadwords
4145 // of the result come from the same quadword of one of the two inputs. Undef
4146 // mask values count as coming from any quadword, for better codegen.
4147 SmallVector<unsigned, 4> LoQuad(4);
4148 SmallVector<unsigned, 4> HiQuad(4);
4149 BitVector InputQuads(4);
4150 for (unsigned i = 0; i < 8; ++i) {
4151 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4152 int EltIdx = SVOp->getMaskElt(i);
4153 MaskVals.push_back(EltIdx);
4162 InputQuads.set(EltIdx / 4);
4165 int BestLoQuad = -1;
4166 unsigned MaxQuad = 1;
4167 for (unsigned i = 0; i < 4; ++i) {
4168 if (LoQuad[i] > MaxQuad) {
4170 MaxQuad = LoQuad[i];
4174 int BestHiQuad = -1;
4176 for (unsigned i = 0; i < 4; ++i) {
4177 if (HiQuad[i] > MaxQuad) {
4179 MaxQuad = HiQuad[i];
4183 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4184 // of the two input vectors, shuffle them into one input vector so only a
4185 // single pshufb instruction is necessary. If There are more than 2 input
4186 // quads, disable the next transformation since it does not help SSSE3.
4187 bool V1Used = InputQuads[0] || InputQuads[1];
4188 bool V2Used = InputQuads[2] || InputQuads[3];
4189 if (TLI.getSubtarget()->hasSSSE3()) {
4190 if (InputQuads.count() == 2 && V1Used && V2Used) {
4191 BestLoQuad = InputQuads.find_first();
4192 BestHiQuad = InputQuads.find_next(BestLoQuad);
4194 if (InputQuads.count() > 2) {
4200 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4201 // the shuffle mask. If a quad is scored as -1, that means that it contains
4202 // words from all 4 input quadwords.
4204 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4205 SmallVector<int, 8> MaskV;
4206 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4207 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4208 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4209 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4210 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4211 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4213 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4214 // source words for the shuffle, to aid later transformations.
4215 bool AllWordsInNewV = true;
4216 bool InOrder[2] = { true, true };
4217 for (unsigned i = 0; i != 8; ++i) {
4218 int idx = MaskVals[i];
4220 InOrder[i/4] = false;
4221 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4223 AllWordsInNewV = false;
4227 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4228 if (AllWordsInNewV) {
4229 for (int i = 0; i != 8; ++i) {
4230 int idx = MaskVals[i];
4233 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4234 if ((idx != i) && idx < 4)
4236 if ((idx != i) && idx > 3)
4245 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4246 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4247 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4248 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4249 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4253 // If we have SSSE3, and all words of the result are from 1 input vector,
4254 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4255 // is present, fall back to case 4.
4256 if (TLI.getSubtarget()->hasSSSE3()) {
4257 SmallVector<SDValue,16> pshufbMask;
4259 // If we have elements from both input vectors, set the high bit of the
4260 // shuffle mask element to zero out elements that come from V2 in the V1
4261 // mask, and elements that come from V1 in the V2 mask, so that the two
4262 // results can be OR'd together.
4263 bool TwoInputs = V1Used && V2Used;
4264 for (unsigned i = 0; i != 8; ++i) {
4265 int EltIdx = MaskVals[i] * 2;
4266 if (TwoInputs && (EltIdx >= 16)) {
4267 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4268 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4271 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4272 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4274 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4275 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4276 DAG.getNode(ISD::BUILD_VECTOR, dl,
4277 MVT::v16i8, &pshufbMask[0], 16));
4279 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4281 // Calculate the shuffle mask for the second input, shuffle it, and
4282 // OR it with the first shuffled input.
4284 for (unsigned i = 0; i != 8; ++i) {
4285 int EltIdx = MaskVals[i] * 2;
4287 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4288 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4291 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4292 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4294 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4295 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4296 DAG.getNode(ISD::BUILD_VECTOR, dl,
4297 MVT::v16i8, &pshufbMask[0], 16));
4298 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4299 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4302 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4303 // and update MaskVals with new element order.
4304 BitVector InOrder(8);
4305 if (BestLoQuad >= 0) {
4306 SmallVector<int, 8> MaskV;
4307 for (int i = 0; i != 4; ++i) {
4308 int idx = MaskVals[i];
4310 MaskV.push_back(-1);
4312 } else if ((idx / 4) == BestLoQuad) {
4313 MaskV.push_back(idx & 3);
4316 MaskV.push_back(-1);
4319 for (unsigned i = 4; i != 8; ++i)
4321 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4325 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4326 // and update MaskVals with the new element order.
4327 if (BestHiQuad >= 0) {
4328 SmallVector<int, 8> MaskV;
4329 for (unsigned i = 0; i != 4; ++i)
4331 for (unsigned i = 4; i != 8; ++i) {
4332 int idx = MaskVals[i];
4334 MaskV.push_back(-1);
4336 } else if ((idx / 4) == BestHiQuad) {
4337 MaskV.push_back((idx & 3) + 4);
4340 MaskV.push_back(-1);
4343 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4347 // In case BestHi & BestLo were both -1, which means each quadword has a word
4348 // from each of the four input quadwords, calculate the InOrder bitvector now
4349 // before falling through to the insert/extract cleanup.
4350 if (BestLoQuad == -1 && BestHiQuad == -1) {
4352 for (int i = 0; i != 8; ++i)
4353 if (MaskVals[i] < 0 || MaskVals[i] == i)
4357 // The other elements are put in the right place using pextrw and pinsrw.
4358 for (unsigned i = 0; i != 8; ++i) {
4361 int EltIdx = MaskVals[i];
4364 SDValue ExtOp = (EltIdx < 8)
4365 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4366 DAG.getIntPtrConstant(EltIdx))
4367 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4368 DAG.getIntPtrConstant(EltIdx - 8));
4369 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4370 DAG.getIntPtrConstant(i));
4375 // v16i8 shuffles - Prefer shuffles in the following order:
4376 // 1. [ssse3] 1 x pshufb
4377 // 2. [ssse3] 2 x pshufb + 1 x por
4378 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4380 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4382 const X86TargetLowering &TLI) {
4383 SDValue V1 = SVOp->getOperand(0);
4384 SDValue V2 = SVOp->getOperand(1);
4385 DebugLoc dl = SVOp->getDebugLoc();
4386 SmallVector<int, 16> MaskVals;
4387 SVOp->getMask(MaskVals);
4389 // If we have SSSE3, case 1 is generated when all result bytes come from
4390 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4391 // present, fall back to case 3.
4392 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4395 for (unsigned i = 0; i < 16; ++i) {
4396 int EltIdx = MaskVals[i];
4405 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4406 if (TLI.getSubtarget()->hasSSSE3()) {
4407 SmallVector<SDValue,16> pshufbMask;
4409 // If all result elements are from one input vector, then only translate
4410 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4412 // Otherwise, we have elements from both input vectors, and must zero out
4413 // elements that come from V2 in the first mask, and V1 in the second mask
4414 // so that we can OR them together.
4415 bool TwoInputs = !(V1Only || V2Only);
4416 for (unsigned i = 0; i != 16; ++i) {
4417 int EltIdx = MaskVals[i];
4418 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4419 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4422 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4424 // If all the elements are from V2, assign it to V1 and return after
4425 // building the first pshufb.
4428 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4429 DAG.getNode(ISD::BUILD_VECTOR, dl,
4430 MVT::v16i8, &pshufbMask[0], 16));
4434 // Calculate the shuffle mask for the second input, shuffle it, and
4435 // OR it with the first shuffled input.
4437 for (unsigned i = 0; i != 16; ++i) {
4438 int EltIdx = MaskVals[i];
4440 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4443 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4445 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4446 DAG.getNode(ISD::BUILD_VECTOR, dl,
4447 MVT::v16i8, &pshufbMask[0], 16));
4448 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4451 // No SSSE3 - Calculate in place words and then fix all out of place words
4452 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4453 // the 16 different words that comprise the two doublequadword input vectors.
4454 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4455 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4456 SDValue NewV = V2Only ? V2 : V1;
4457 for (int i = 0; i != 8; ++i) {
4458 int Elt0 = MaskVals[i*2];
4459 int Elt1 = MaskVals[i*2+1];
4461 // This word of the result is all undef, skip it.
4462 if (Elt0 < 0 && Elt1 < 0)
4465 // This word of the result is already in the correct place, skip it.
4466 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4468 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4471 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4472 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4475 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4476 // using a single extract together, load it and store it.
4477 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4478 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4479 DAG.getIntPtrConstant(Elt1 / 2));
4480 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4481 DAG.getIntPtrConstant(i));
4485 // If Elt1 is defined, extract it from the appropriate source. If the
4486 // source byte is not also odd, shift the extracted word left 8 bits
4487 // otherwise clear the bottom 8 bits if we need to do an or.
4489 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4490 DAG.getIntPtrConstant(Elt1 / 2));
4491 if ((Elt1 & 1) == 0)
4492 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4493 DAG.getConstant(8, TLI.getShiftAmountTy()));
4495 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4496 DAG.getConstant(0xFF00, MVT::i16));
4498 // If Elt0 is defined, extract it from the appropriate source. If the
4499 // source byte is not also even, shift the extracted word right 8 bits. If
4500 // Elt1 was also defined, OR the extracted values together before
4501 // inserting them in the result.
4503 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4504 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4505 if ((Elt0 & 1) != 0)
4506 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4507 DAG.getConstant(8, TLI.getShiftAmountTy()));
4509 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4510 DAG.getConstant(0x00FF, MVT::i16));
4511 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4514 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4515 DAG.getIntPtrConstant(i));
4517 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4520 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4521 /// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be
4522 /// done when every pair / quad of shuffle mask elements point to elements in
4523 /// the right sequence. e.g.
4524 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4526 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4528 const TargetLowering &TLI, DebugLoc dl) {
4529 EVT VT = SVOp->getValueType(0);
4530 SDValue V1 = SVOp->getOperand(0);
4531 SDValue V2 = SVOp->getOperand(1);
4532 unsigned NumElems = VT.getVectorNumElements();
4533 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4534 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4536 switch (VT.getSimpleVT().SimpleTy) {
4537 default: assert(false && "Unexpected!");
4538 case MVT::v4f32: NewVT = MVT::v2f64; break;
4539 case MVT::v4i32: NewVT = MVT::v2i64; break;
4540 case MVT::v8i16: NewVT = MVT::v4i32; break;
4541 case MVT::v16i8: NewVT = MVT::v4i32; break;
4544 if (NewWidth == 2) {
4550 int Scale = NumElems / NewWidth;
4551 SmallVector<int, 8> MaskVec;
4552 for (unsigned i = 0; i < NumElems; i += Scale) {
4554 for (int j = 0; j < Scale; ++j) {
4555 int EltIdx = SVOp->getMaskElt(i+j);
4559 StartIdx = EltIdx - (EltIdx % Scale);
4560 if (EltIdx != StartIdx + j)
4564 MaskVec.push_back(-1);
4566 MaskVec.push_back(StartIdx / Scale);
4569 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4570 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4571 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4574 /// getVZextMovL - Return a zero-extending vector move low node.
4576 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4577 SDValue SrcOp, SelectionDAG &DAG,
4578 const X86Subtarget *Subtarget, DebugLoc dl) {
4579 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4580 LoadSDNode *LD = NULL;
4581 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4582 LD = dyn_cast<LoadSDNode>(SrcOp);
4584 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4586 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4587 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4588 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4589 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4590 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4592 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4593 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4594 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4595 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4603 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4604 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4605 DAG.getNode(ISD::BIT_CONVERT, dl,
4609 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4612 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4613 SDValue V1 = SVOp->getOperand(0);
4614 SDValue V2 = SVOp->getOperand(1);
4615 DebugLoc dl = SVOp->getDebugLoc();
4616 EVT VT = SVOp->getValueType(0);
4618 SmallVector<std::pair<int, int>, 8> Locs;
4620 SmallVector<int, 8> Mask1(4U, -1);
4621 SmallVector<int, 8> PermMask;
4622 SVOp->getMask(PermMask);
4626 for (unsigned i = 0; i != 4; ++i) {
4627 int Idx = PermMask[i];
4629 Locs[i] = std::make_pair(-1, -1);
4631 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4633 Locs[i] = std::make_pair(0, NumLo);
4637 Locs[i] = std::make_pair(1, NumHi);
4639 Mask1[2+NumHi] = Idx;
4645 if (NumLo <= 2 && NumHi <= 2) {
4646 // If no more than two elements come from either vector. This can be
4647 // implemented with two shuffles. First shuffle gather the elements.
4648 // The second shuffle, which takes the first shuffle as both of its
4649 // vector operands, put the elements into the right order.
4650 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4652 SmallVector<int, 8> Mask2(4U, -1);
4654 for (unsigned i = 0; i != 4; ++i) {
4655 if (Locs[i].first == -1)
4658 unsigned Idx = (i < 2) ? 0 : 4;
4659 Idx += Locs[i].first * 2 + Locs[i].second;
4664 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4665 } else if (NumLo == 3 || NumHi == 3) {
4666 // Otherwise, we must have three elements from one vector, call it X, and
4667 // one element from the other, call it Y. First, use a shufps to build an
4668 // intermediate vector with the one element from Y and the element from X
4669 // that will be in the same half in the final destination (the indexes don't
4670 // matter). Then, use a shufps to build the final vector, taking the half
4671 // containing the element from Y from the intermediate, and the other half
4674 // Normalize it so the 3 elements come from V1.
4675 CommuteVectorShuffleMask(PermMask, VT);
4679 // Find the element from V2.
4681 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4682 int Val = PermMask[HiIndex];
4689 Mask1[0] = PermMask[HiIndex];
4691 Mask1[2] = PermMask[HiIndex^1];
4693 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4696 Mask1[0] = PermMask[0];
4697 Mask1[1] = PermMask[1];
4698 Mask1[2] = HiIndex & 1 ? 6 : 4;
4699 Mask1[3] = HiIndex & 1 ? 4 : 6;
4700 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4702 Mask1[0] = HiIndex & 1 ? 2 : 0;
4703 Mask1[1] = HiIndex & 1 ? 0 : 2;
4704 Mask1[2] = PermMask[2];
4705 Mask1[3] = PermMask[3];
4710 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4714 // Break it into (shuffle shuffle_hi, shuffle_lo).
4716 SmallVector<int,8> LoMask(4U, -1);
4717 SmallVector<int,8> HiMask(4U, -1);
4719 SmallVector<int,8> *MaskPtr = &LoMask;
4720 unsigned MaskIdx = 0;
4723 for (unsigned i = 0; i != 4; ++i) {
4730 int Idx = PermMask[i];
4732 Locs[i] = std::make_pair(-1, -1);
4733 } else if (Idx < 4) {
4734 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4735 (*MaskPtr)[LoIdx] = Idx;
4738 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4739 (*MaskPtr)[HiIdx] = Idx;
4744 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4745 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4746 SmallVector<int, 8> MaskOps;
4747 for (unsigned i = 0; i != 4; ++i) {
4748 if (Locs[i].first == -1) {
4749 MaskOps.push_back(-1);
4751 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4752 MaskOps.push_back(Idx);
4755 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4759 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
4760 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4761 SDValue V1 = Op.getOperand(0);
4762 SDValue V2 = Op.getOperand(1);
4763 EVT VT = Op.getValueType();
4764 DebugLoc dl = Op.getDebugLoc();
4765 unsigned NumElems = VT.getVectorNumElements();
4766 bool isMMX = VT.getSizeInBits() == 64;
4767 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4768 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4769 bool V1IsSplat = false;
4770 bool V2IsSplat = false;
4772 if (isZeroShuffle(SVOp))
4773 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4775 // Promote splats to v4f32.
4776 if (SVOp->isSplat()) {
4777 if (isMMX || NumElems < 4)
4779 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4782 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4784 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4785 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4786 if (NewOp.getNode())
4787 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4788 LowerVECTOR_SHUFFLE(NewOp, DAG));
4789 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4790 // FIXME: Figure out a cleaner way to do this.
4791 // Try to make use of movq to zero out the top part.
4792 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4793 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4794 if (NewOp.getNode()) {
4795 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4796 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4797 DAG, Subtarget, dl);
4799 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4800 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4801 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4802 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4803 DAG, Subtarget, dl);
4807 if (X86::isPSHUFDMask(SVOp))
4810 // Check if this can be converted into a logical shift.
4811 bool isLeft = false;
4814 bool isShift = getSubtarget()->hasSSE2() &&
4815 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4816 if (isShift && ShVal.hasOneUse()) {
4817 // If the shifted value has multiple uses, it may be cheaper to use
4818 // v_set0 + movlhps or movhlps, etc.
4819 EVT EltVT = VT.getVectorElementType();
4820 ShAmt *= EltVT.getSizeInBits();
4821 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4824 if (X86::isMOVLMask(SVOp)) {
4827 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4828 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4833 // FIXME: fold these into legal mask.
4834 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4835 X86::isMOVSLDUPMask(SVOp) ||
4836 X86::isMOVHLPSMask(SVOp) ||
4837 X86::isMOVLHPSMask(SVOp) ||
4838 X86::isMOVLPMask(SVOp)))
4841 if (ShouldXformToMOVHLPS(SVOp) ||
4842 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4843 return CommuteVectorShuffle(SVOp, DAG);
4846 // No better options. Use a vshl / vsrl.
4847 EVT EltVT = VT.getVectorElementType();
4848 ShAmt *= EltVT.getSizeInBits();
4849 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4852 bool Commuted = false;
4853 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4854 // 1,1,1,1 -> v8i16 though.
4855 V1IsSplat = isSplatVector(V1.getNode());
4856 V2IsSplat = isSplatVector(V2.getNode());
4858 // Canonicalize the splat or undef, if present, to be on the RHS.
4859 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4860 Op = CommuteVectorShuffle(SVOp, DAG);
4861 SVOp = cast<ShuffleVectorSDNode>(Op);
4862 V1 = SVOp->getOperand(0);
4863 V2 = SVOp->getOperand(1);
4864 std::swap(V1IsSplat, V2IsSplat);
4865 std::swap(V1IsUndef, V2IsUndef);
4869 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4870 // Shuffling low element of v1 into undef, just return v1.
4873 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4874 // the instruction selector will not match, so get a canonical MOVL with
4875 // swapped operands to undo the commute.
4876 return getMOVL(DAG, dl, VT, V2, V1);
4879 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4880 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4881 X86::isUNPCKLMask(SVOp) ||
4882 X86::isUNPCKHMask(SVOp))
4886 // Normalize mask so all entries that point to V2 points to its first
4887 // element then try to match unpck{h|l} again. If match, return a
4888 // new vector_shuffle with the corrected mask.
4889 SDValue NewMask = NormalizeMask(SVOp, DAG);
4890 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4891 if (NSVOp != SVOp) {
4892 if (X86::isUNPCKLMask(NSVOp, true)) {
4894 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4901 // Commute is back and try unpck* again.
4902 // FIXME: this seems wrong.
4903 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4904 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4905 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4906 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4907 X86::isUNPCKLMask(NewSVOp) ||
4908 X86::isUNPCKHMask(NewSVOp))
4912 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4914 // Normalize the node to match x86 shuffle ops if needed
4915 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4916 return CommuteVectorShuffle(SVOp, DAG);
4918 // Check for legal shuffle and return?
4919 SmallVector<int, 16> PermMask;
4920 SVOp->getMask(PermMask);
4921 if (isShuffleMaskLegal(PermMask, VT))
4924 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4925 if (VT == MVT::v8i16) {
4926 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4927 if (NewOp.getNode())
4931 if (VT == MVT::v16i8) {
4932 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4933 if (NewOp.getNode())
4937 // Handle all 4 wide cases with a number of shuffles except for MMX.
4938 if (NumElems == 4 && !isMMX)
4939 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4945 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4946 SelectionDAG &DAG) const {
4947 EVT VT = Op.getValueType();
4948 DebugLoc dl = Op.getDebugLoc();
4949 if (VT.getSizeInBits() == 8) {
4950 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4951 Op.getOperand(0), Op.getOperand(1));
4952 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4953 DAG.getValueType(VT));
4954 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4955 } else if (VT.getSizeInBits() == 16) {
4956 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4957 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4959 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4960 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4961 DAG.getNode(ISD::BIT_CONVERT, dl,
4965 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4966 Op.getOperand(0), Op.getOperand(1));
4967 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4968 DAG.getValueType(VT));
4969 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4970 } else if (VT == MVT::f32) {
4971 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4972 // the result back to FR32 register. It's only worth matching if the
4973 // result has a single use which is a store or a bitcast to i32. And in
4974 // the case of a store, it's not worth it if the index is a constant 0,
4975 // because a MOVSSmr can be used instead, which is smaller and faster.
4976 if (!Op.hasOneUse())
4978 SDNode *User = *Op.getNode()->use_begin();
4979 if ((User->getOpcode() != ISD::STORE ||
4980 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4981 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4982 (User->getOpcode() != ISD::BIT_CONVERT ||
4983 User->getValueType(0) != MVT::i32))
4985 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4986 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4989 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4990 } else if (VT == MVT::i32) {
4991 // ExtractPS works with constant index.
4992 if (isa<ConstantSDNode>(Op.getOperand(1)))
5000 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5001 SelectionDAG &DAG) const {
5002 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5005 if (Subtarget->hasSSE41()) {
5006 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5011 EVT VT = Op.getValueType();
5012 DebugLoc dl = Op.getDebugLoc();
5013 // TODO: handle v16i8.
5014 if (VT.getSizeInBits() == 16) {
5015 SDValue Vec = Op.getOperand(0);
5016 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5018 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5019 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5020 DAG.getNode(ISD::BIT_CONVERT, dl,
5023 // Transform it so it match pextrw which produces a 32-bit result.
5024 EVT EltVT = MVT::i32;
5025 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5026 Op.getOperand(0), Op.getOperand(1));
5027 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5028 DAG.getValueType(VT));
5029 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5030 } else if (VT.getSizeInBits() == 32) {
5031 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5035 // SHUFPS the element to the lowest double word, then movss.
5036 int Mask[4] = { Idx, -1, -1, -1 };
5037 EVT VVT = Op.getOperand(0).getValueType();
5038 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5039 DAG.getUNDEF(VVT), Mask);
5040 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5041 DAG.getIntPtrConstant(0));
5042 } else if (VT.getSizeInBits() == 64) {
5043 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5044 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5045 // to match extract_elt for f64.
5046 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5050 // UNPCKHPD the element to the lowest double word, then movsd.
5051 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5052 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5053 int Mask[2] = { 1, -1 };
5054 EVT VVT = Op.getOperand(0).getValueType();
5055 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5056 DAG.getUNDEF(VVT), Mask);
5057 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5058 DAG.getIntPtrConstant(0));
5065 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5066 SelectionDAG &DAG) const {
5067 EVT VT = Op.getValueType();
5068 EVT EltVT = VT.getVectorElementType();
5069 DebugLoc dl = Op.getDebugLoc();
5071 SDValue N0 = Op.getOperand(0);
5072 SDValue N1 = Op.getOperand(1);
5073 SDValue N2 = Op.getOperand(2);
5075 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5076 isa<ConstantSDNode>(N2)) {
5078 if (VT == MVT::v8i16)
5079 Opc = X86ISD::PINSRW;
5080 else if (VT == MVT::v4i16)
5081 Opc = X86ISD::MMX_PINSRW;
5082 else if (VT == MVT::v16i8)
5083 Opc = X86ISD::PINSRB;
5085 Opc = X86ISD::PINSRB;
5087 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5089 if (N1.getValueType() != MVT::i32)
5090 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5091 if (N2.getValueType() != MVT::i32)
5092 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5093 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5094 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5095 // Bits [7:6] of the constant are the source select. This will always be
5096 // zero here. The DAG Combiner may combine an extract_elt index into these
5097 // bits. For example (insert (extract, 3), 2) could be matched by putting
5098 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5099 // Bits [5:4] of the constant are the destination select. This is the
5100 // value of the incoming immediate.
5101 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5102 // combine either bitwise AND or insert of float 0.0 to set these bits.
5103 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5104 // Create this as a scalar to vector..
5105 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5106 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5107 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5108 // PINSR* works with constant index.
5115 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5116 EVT VT = Op.getValueType();
5117 EVT EltVT = VT.getVectorElementType();
5119 if (Subtarget->hasSSE41())
5120 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5122 if (EltVT == MVT::i8)
5125 DebugLoc dl = Op.getDebugLoc();
5126 SDValue N0 = Op.getOperand(0);
5127 SDValue N1 = Op.getOperand(1);
5128 SDValue N2 = Op.getOperand(2);
5130 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5131 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5132 // as its second argument.
5133 if (N1.getValueType() != MVT::i32)
5134 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5135 if (N2.getValueType() != MVT::i32)
5136 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5137 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5138 dl, VT, N0, N1, N2);
5144 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5145 DebugLoc dl = Op.getDebugLoc();
5147 if (Op.getValueType() == MVT::v1i64 &&
5148 Op.getOperand(0).getValueType() == MVT::i64)
5149 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5151 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5152 EVT VT = MVT::v2i32;
5153 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5160 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5161 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5164 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5165 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5166 // one of the above mentioned nodes. It has to be wrapped because otherwise
5167 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5168 // be used to form addressing mode. These wrapped nodes will be selected
5171 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5172 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5174 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5176 unsigned char OpFlag = 0;
5177 unsigned WrapperKind = X86ISD::Wrapper;
5178 CodeModel::Model M = getTargetMachine().getCodeModel();
5180 if (Subtarget->isPICStyleRIPRel() &&
5181 (M == CodeModel::Small || M == CodeModel::Kernel))
5182 WrapperKind = X86ISD::WrapperRIP;
5183 else if (Subtarget->isPICStyleGOT())
5184 OpFlag = X86II::MO_GOTOFF;
5185 else if (Subtarget->isPICStyleStubPIC())
5186 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5188 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5190 CP->getOffset(), OpFlag);
5191 DebugLoc DL = CP->getDebugLoc();
5192 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5193 // With PIC, the address is actually $g + Offset.
5195 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5196 DAG.getNode(X86ISD::GlobalBaseReg,
5197 DebugLoc(), getPointerTy()),
5204 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5205 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5207 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5209 unsigned char OpFlag = 0;
5210 unsigned WrapperKind = X86ISD::Wrapper;
5211 CodeModel::Model M = getTargetMachine().getCodeModel();
5213 if (Subtarget->isPICStyleRIPRel() &&
5214 (M == CodeModel::Small || M == CodeModel::Kernel))
5215 WrapperKind = X86ISD::WrapperRIP;
5216 else if (Subtarget->isPICStyleGOT())
5217 OpFlag = X86II::MO_GOTOFF;
5218 else if (Subtarget->isPICStyleStubPIC())
5219 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5221 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5223 DebugLoc DL = JT->getDebugLoc();
5224 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5226 // With PIC, the address is actually $g + Offset.
5228 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5229 DAG.getNode(X86ISD::GlobalBaseReg,
5230 DebugLoc(), getPointerTy()),
5238 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5239 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5241 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5243 unsigned char OpFlag = 0;
5244 unsigned WrapperKind = X86ISD::Wrapper;
5245 CodeModel::Model M = getTargetMachine().getCodeModel();
5247 if (Subtarget->isPICStyleRIPRel() &&
5248 (M == CodeModel::Small || M == CodeModel::Kernel))
5249 WrapperKind = X86ISD::WrapperRIP;
5250 else if (Subtarget->isPICStyleGOT())
5251 OpFlag = X86II::MO_GOTOFF;
5252 else if (Subtarget->isPICStyleStubPIC())
5253 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5255 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5257 DebugLoc DL = Op.getDebugLoc();
5258 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5261 // With PIC, the address is actually $g + Offset.
5262 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5263 !Subtarget->is64Bit()) {
5264 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5265 DAG.getNode(X86ISD::GlobalBaseReg,
5266 DebugLoc(), getPointerTy()),
5274 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5275 // Create the TargetBlockAddressAddress node.
5276 unsigned char OpFlags =
5277 Subtarget->ClassifyBlockAddressReference();
5278 CodeModel::Model M = getTargetMachine().getCodeModel();
5279 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5280 DebugLoc dl = Op.getDebugLoc();
5281 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5282 /*isTarget=*/true, OpFlags);
5284 if (Subtarget->isPICStyleRIPRel() &&
5285 (M == CodeModel::Small || M == CodeModel::Kernel))
5286 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5288 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5290 // With PIC, the address is actually $g + Offset.
5291 if (isGlobalRelativeToPICBase(OpFlags)) {
5292 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5293 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5301 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5303 SelectionDAG &DAG) const {
5304 // Create the TargetGlobalAddress node, folding in the constant
5305 // offset if it is legal.
5306 unsigned char OpFlags =
5307 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5308 CodeModel::Model M = getTargetMachine().getCodeModel();
5310 if (OpFlags == X86II::MO_NO_FLAG &&
5311 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5312 // A direct static reference to a global.
5313 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5316 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5319 if (Subtarget->isPICStyleRIPRel() &&
5320 (M == CodeModel::Small || M == CodeModel::Kernel))
5321 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5323 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5325 // With PIC, the address is actually $g + Offset.
5326 if (isGlobalRelativeToPICBase(OpFlags)) {
5327 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5328 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5332 // For globals that require a load from a stub to get the address, emit the
5334 if (isGlobalStubReference(OpFlags))
5335 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5336 PseudoSourceValue::getGOT(), 0, false, false, 0);
5338 // If there was a non-zero offset that we didn't fold, create an explicit
5341 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5342 DAG.getConstant(Offset, getPointerTy()));
5348 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5349 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5350 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5351 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5355 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5356 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5357 unsigned char OperandFlags) {
5358 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5359 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5360 DebugLoc dl = GA->getDebugLoc();
5361 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5362 GA->getValueType(0),
5366 SDValue Ops[] = { Chain, TGA, *InFlag };
5367 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5369 SDValue Ops[] = { Chain, TGA };
5370 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5373 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5374 MFI->setAdjustsStack(true);
5376 SDValue Flag = Chain.getValue(1);
5377 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5380 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5382 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5385 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5386 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5387 DAG.getNode(X86ISD::GlobalBaseReg,
5388 DebugLoc(), PtrVT), InFlag);
5389 InFlag = Chain.getValue(1);
5391 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5394 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5396 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5398 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5399 X86::RAX, X86II::MO_TLSGD);
5402 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5403 // "local exec" model.
5404 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5405 const EVT PtrVT, TLSModel::Model model,
5407 DebugLoc dl = GA->getDebugLoc();
5408 // Get the Thread Pointer
5409 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5411 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5414 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5415 NULL, 0, false, false, 0);
5417 unsigned char OperandFlags = 0;
5418 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5420 unsigned WrapperKind = X86ISD::Wrapper;
5421 if (model == TLSModel::LocalExec) {
5422 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5423 } else if (is64Bit) {
5424 assert(model == TLSModel::InitialExec);
5425 OperandFlags = X86II::MO_GOTTPOFF;
5426 WrapperKind = X86ISD::WrapperRIP;
5428 assert(model == TLSModel::InitialExec);
5429 OperandFlags = X86II::MO_INDNTPOFF;
5432 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5434 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5435 GA->getValueType(0),
5436 GA->getOffset(), OperandFlags);
5437 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5439 if (model == TLSModel::InitialExec)
5440 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5441 PseudoSourceValue::getGOT(), 0, false, false, 0);
5443 // The address of the thread local variable is the add of the thread
5444 // pointer with the offset of the variable.
5445 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5449 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
5451 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5452 const GlobalValue *GV = GA->getGlobal();
5454 if (Subtarget->isTargetELF()) {
5455 // TODO: implement the "local dynamic" model
5456 // TODO: implement the "initial exec"model for pic executables
5458 // If GV is an alias then use the aliasee for determining
5459 // thread-localness.
5460 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5461 GV = GA->resolveAliasedGlobal(false);
5463 TLSModel::Model model
5464 = getTLSModel(GV, getTargetMachine().getRelocationModel());
5467 case TLSModel::GeneralDynamic:
5468 case TLSModel::LocalDynamic: // not implemented
5469 if (Subtarget->is64Bit())
5470 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5471 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5473 case TLSModel::InitialExec:
5474 case TLSModel::LocalExec:
5475 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5476 Subtarget->is64Bit());
5478 } else if (Subtarget->isTargetDarwin()) {
5479 // Darwin only has one model of TLS. Lower to that.
5480 unsigned char OpFlag = 0;
5481 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
5482 X86ISD::WrapperRIP : X86ISD::Wrapper;
5484 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5486 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
5487 !Subtarget->is64Bit();
5489 OpFlag = X86II::MO_TLVP_PIC_BASE;
5491 OpFlag = X86II::MO_TLVP;
5492 DebugLoc DL = Op.getDebugLoc();
5493 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
5495 GA->getOffset(), OpFlag);
5496 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5498 // With PIC32, the address is actually $g + Offset.
5500 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5501 DAG.getNode(X86ISD::GlobalBaseReg,
5502 DebugLoc(), getPointerTy()),
5505 // Lowering the machine isd will make sure everything is in the right
5507 SDValue Args[] = { Offset };
5508 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
5510 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
5511 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5512 MFI->setAdjustsStack(true);
5514 // And our return value (tls address) is in the standard call return value
5516 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
5517 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
5521 "TLS not implemented for this target.");
5523 llvm_unreachable("Unreachable");
5528 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5529 /// take a 2 x i32 value to shift plus a shift amount.
5530 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
5531 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5532 EVT VT = Op.getValueType();
5533 unsigned VTBits = VT.getSizeInBits();
5534 DebugLoc dl = Op.getDebugLoc();
5535 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5536 SDValue ShOpLo = Op.getOperand(0);
5537 SDValue ShOpHi = Op.getOperand(1);
5538 SDValue ShAmt = Op.getOperand(2);
5539 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5540 DAG.getConstant(VTBits - 1, MVT::i8))
5541 : DAG.getConstant(0, VT);
5544 if (Op.getOpcode() == ISD::SHL_PARTS) {
5545 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5546 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5548 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5549 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5552 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5553 DAG.getConstant(VTBits, MVT::i8));
5554 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5555 AndNode, DAG.getConstant(0, MVT::i8));
5558 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5559 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5560 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5562 if (Op.getOpcode() == ISD::SHL_PARTS) {
5563 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5564 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5566 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5567 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5570 SDValue Ops[2] = { Lo, Hi };
5571 return DAG.getMergeValues(Ops, 2, dl);
5574 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
5575 SelectionDAG &DAG) const {
5576 EVT SrcVT = Op.getOperand(0).getValueType();
5578 if (SrcVT.isVector()) {
5579 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5585 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5586 "Unknown SINT_TO_FP to lower!");
5588 // These are really Legal; return the operand so the caller accepts it as
5590 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5592 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5593 Subtarget->is64Bit()) {
5597 DebugLoc dl = Op.getDebugLoc();
5598 unsigned Size = SrcVT.getSizeInBits()/8;
5599 MachineFunction &MF = DAG.getMachineFunction();
5600 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5601 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5602 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5604 PseudoSourceValue::getFixedStack(SSFI), 0,
5606 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5609 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5611 SelectionDAG &DAG) const {
5613 DebugLoc dl = Op.getDebugLoc();
5615 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5617 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5619 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5620 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5621 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5622 Tys, Ops, array_lengthof(Ops));
5625 Chain = Result.getValue(1);
5626 SDValue InFlag = Result.getValue(2);
5628 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5629 // shouldn't be necessary except that RFP cannot be live across
5630 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5631 MachineFunction &MF = DAG.getMachineFunction();
5632 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5633 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5634 Tys = DAG.getVTList(MVT::Other);
5636 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5638 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5639 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5640 PseudoSourceValue::getFixedStack(SSFI), 0,
5647 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5648 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
5649 SelectionDAG &DAG) const {
5650 // This algorithm is not obvious. Here it is in C code, more or less:
5652 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5653 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5654 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5656 // Copy ints to xmm registers.
5657 __m128i xh = _mm_cvtsi32_si128( hi );
5658 __m128i xl = _mm_cvtsi32_si128( lo );
5660 // Combine into low half of a single xmm register.
5661 __m128i x = _mm_unpacklo_epi32( xh, xl );
5665 // Merge in appropriate exponents to give the integer bits the right
5667 x = _mm_unpacklo_epi32( x, exp );
5669 // Subtract away the biases to deal with the IEEE-754 double precision
5671 d = _mm_sub_pd( (__m128d) x, bias );
5673 // All conversions up to here are exact. The correctly rounded result is
5674 // calculated using the current rounding mode using the following
5676 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5677 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5678 // store doesn't really need to be here (except
5679 // maybe to zero the other double)
5684 DebugLoc dl = Op.getDebugLoc();
5685 LLVMContext *Context = DAG.getContext();
5687 // Build some magic constants.
5688 std::vector<Constant*> CV0;
5689 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5690 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5691 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5692 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5693 Constant *C0 = ConstantVector::get(CV0);
5694 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5696 std::vector<Constant*> CV1;
5698 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5700 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5701 Constant *C1 = ConstantVector::get(CV1);
5702 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5704 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5705 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5707 DAG.getIntPtrConstant(1)));
5708 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5709 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5711 DAG.getIntPtrConstant(0)));
5712 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5713 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5714 PseudoSourceValue::getConstantPool(), 0,
5716 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5717 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5718 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5719 PseudoSourceValue::getConstantPool(), 0,
5721 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5723 // Add the halves; easiest way is to swap them into another reg first.
5724 int ShufMask[2] = { 1, -1 };
5725 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5726 DAG.getUNDEF(MVT::v2f64), ShufMask);
5727 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5728 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5729 DAG.getIntPtrConstant(0));
5732 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5733 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
5734 SelectionDAG &DAG) const {
5735 DebugLoc dl = Op.getDebugLoc();
5736 // FP constant to bias correct the final result.
5737 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5740 // Load the 32-bit value into an XMM register.
5741 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5742 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5744 DAG.getIntPtrConstant(0)));
5746 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5747 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5748 DAG.getIntPtrConstant(0));
5750 // Or the load with the bias.
5751 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5752 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5753 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5755 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5756 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5757 MVT::v2f64, Bias)));
5758 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5759 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5760 DAG.getIntPtrConstant(0));
5762 // Subtract the bias.
5763 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5765 // Handle final rounding.
5766 EVT DestVT = Op.getValueType();
5768 if (DestVT.bitsLT(MVT::f64)) {
5769 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5770 DAG.getIntPtrConstant(0));
5771 } else if (DestVT.bitsGT(MVT::f64)) {
5772 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5775 // Handle final rounding.
5779 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
5780 SelectionDAG &DAG) const {
5781 SDValue N0 = Op.getOperand(0);
5782 DebugLoc dl = Op.getDebugLoc();
5784 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
5785 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5786 // the optimization here.
5787 if (DAG.SignBitIsZero(N0))
5788 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5790 EVT SrcVT = N0.getValueType();
5791 EVT DstVT = Op.getValueType();
5792 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
5793 return LowerUINT_TO_FP_i64(Op, DAG);
5794 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
5795 return LowerUINT_TO_FP_i32(Op, DAG);
5797 // Make a 64-bit buffer, and use it to build an FILD.
5798 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5799 if (SrcVT == MVT::i32) {
5800 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5801 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5802 getPointerTy(), StackSlot, WordOff);
5803 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5804 StackSlot, NULL, 0, false, false, 0);
5805 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5806 OffsetSlot, NULL, 0, false, false, 0);
5807 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5811 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
5812 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5813 StackSlot, NULL, 0, false, false, 0);
5814 // For i64 source, we need to add the appropriate power of 2 if the input
5815 // was negative. This is the same as the optimization in
5816 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
5817 // we must be careful to do the computation in x87 extended precision, not
5818 // in SSE. (The generic code can't know it's OK to do this, or how to.)
5819 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
5820 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
5821 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
5823 APInt FF(32, 0x5F800000ULL);
5825 // Check whether the sign bit is set.
5826 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
5827 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
5830 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
5831 SDValue FudgePtr = DAG.getConstantPool(
5832 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
5835 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
5836 SDValue Zero = DAG.getIntPtrConstant(0);
5837 SDValue Four = DAG.getIntPtrConstant(4);
5838 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
5840 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
5842 // Load the value out, extending it from f32 to f80.
5843 // FIXME: Avoid the extend by constructing the right constant pool?
5844 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
5845 FudgePtr, PseudoSourceValue::getConstantPool(),
5846 0, MVT::f32, false, false, 4);
5847 // Extend everything to 80 bits to force it to be done on x87.
5848 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
5849 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
5852 std::pair<SDValue,SDValue> X86TargetLowering::
5853 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
5854 DebugLoc dl = Op.getDebugLoc();
5856 EVT DstTy = Op.getValueType();
5859 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5863 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5864 DstTy.getSimpleVT() >= MVT::i16 &&
5865 "Unknown FP_TO_SINT to lower!");
5867 // These are really Legal.
5868 if (DstTy == MVT::i32 &&
5869 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5870 return std::make_pair(SDValue(), SDValue());
5871 if (Subtarget->is64Bit() &&
5872 DstTy == MVT::i64 &&
5873 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5874 return std::make_pair(SDValue(), SDValue());
5876 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5878 MachineFunction &MF = DAG.getMachineFunction();
5879 unsigned MemSize = DstTy.getSizeInBits()/8;
5880 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5881 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5884 switch (DstTy.getSimpleVT().SimpleTy) {
5885 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5886 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5887 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5888 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5891 SDValue Chain = DAG.getEntryNode();
5892 SDValue Value = Op.getOperand(0);
5893 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5894 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5895 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5896 PseudoSourceValue::getFixedStack(SSFI), 0,
5898 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5900 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5902 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5903 Chain = Value.getValue(1);
5904 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5905 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5908 // Build the FP_TO_INT*_IN_MEM
5909 SDValue Ops[] = { Chain, Value, StackSlot };
5910 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5912 return std::make_pair(FIST, StackSlot);
5915 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
5916 SelectionDAG &DAG) const {
5917 if (Op.getValueType().isVector()) {
5918 if (Op.getValueType() == MVT::v2i32 &&
5919 Op.getOperand(0).getValueType() == MVT::v2f64) {
5925 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5926 SDValue FIST = Vals.first, StackSlot = Vals.second;
5927 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5928 if (FIST.getNode() == 0) return Op;
5931 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5932 FIST, StackSlot, NULL, 0, false, false, 0);
5935 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
5936 SelectionDAG &DAG) const {
5937 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5938 SDValue FIST = Vals.first, StackSlot = Vals.second;
5939 assert(FIST.getNode() && "Unexpected failure");
5942 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5943 FIST, StackSlot, NULL, 0, false, false, 0);
5946 SDValue X86TargetLowering::LowerFABS(SDValue Op,
5947 SelectionDAG &DAG) const {
5948 LLVMContext *Context = DAG.getContext();
5949 DebugLoc dl = Op.getDebugLoc();
5950 EVT VT = Op.getValueType();
5953 EltVT = VT.getVectorElementType();
5954 std::vector<Constant*> CV;
5955 if (EltVT == MVT::f64) {
5956 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5960 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5966 Constant *C = ConstantVector::get(CV);
5967 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5968 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5969 PseudoSourceValue::getConstantPool(), 0,
5971 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5974 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
5975 LLVMContext *Context = DAG.getContext();
5976 DebugLoc dl = Op.getDebugLoc();
5977 EVT VT = Op.getValueType();
5980 EltVT = VT.getVectorElementType();
5981 std::vector<Constant*> CV;
5982 if (EltVT == MVT::f64) {
5983 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5987 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5993 Constant *C = ConstantVector::get(CV);
5994 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5995 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5996 PseudoSourceValue::getConstantPool(), 0,
5998 if (VT.isVector()) {
5999 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6000 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6001 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6003 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
6005 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6009 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6010 LLVMContext *Context = DAG.getContext();
6011 SDValue Op0 = Op.getOperand(0);
6012 SDValue Op1 = Op.getOperand(1);
6013 DebugLoc dl = Op.getDebugLoc();
6014 EVT VT = Op.getValueType();
6015 EVT SrcVT = Op1.getValueType();
6017 // If second operand is smaller, extend it first.
6018 if (SrcVT.bitsLT(VT)) {
6019 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6022 // And if it is bigger, shrink it first.
6023 if (SrcVT.bitsGT(VT)) {
6024 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6028 // At this point the operands and the result should have the same
6029 // type, and that won't be f80 since that is not custom lowered.
6031 // First get the sign bit of second operand.
6032 std::vector<Constant*> CV;
6033 if (SrcVT == MVT::f64) {
6034 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6035 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6037 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6038 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6039 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6040 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6042 Constant *C = ConstantVector::get(CV);
6043 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6044 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6045 PseudoSourceValue::getConstantPool(), 0,
6047 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6049 // Shift sign bit right or left if the two operands have different types.
6050 if (SrcVT.bitsGT(VT)) {
6051 // Op0 is MVT::f32, Op1 is MVT::f64.
6052 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6053 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6054 DAG.getConstant(32, MVT::i32));
6055 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
6056 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6057 DAG.getIntPtrConstant(0));
6060 // Clear first operand sign bit.
6062 if (VT == MVT::f64) {
6063 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6064 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6066 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6067 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6068 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6069 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6071 C = ConstantVector::get(CV);
6072 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6073 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6074 PseudoSourceValue::getConstantPool(), 0,
6076 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6078 // Or the value with the sign bit.
6079 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6082 /// Emit nodes that will be selected as "test Op0,Op0", or something
6084 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6085 SelectionDAG &DAG) const {
6086 DebugLoc dl = Op.getDebugLoc();
6088 // CF and OF aren't always set the way we want. Determine which
6089 // of these we need.
6090 bool NeedCF = false;
6091 bool NeedOF = false;
6094 case X86::COND_A: case X86::COND_AE:
6095 case X86::COND_B: case X86::COND_BE:
6098 case X86::COND_G: case X86::COND_GE:
6099 case X86::COND_L: case X86::COND_LE:
6100 case X86::COND_O: case X86::COND_NO:
6105 // See if we can use the EFLAGS value from the operand instead of
6106 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6107 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6108 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6109 // Emit a CMP with 0, which is the TEST pattern.
6110 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6111 DAG.getConstant(0, Op.getValueType()));
6113 unsigned Opcode = 0;
6114 unsigned NumOperands = 0;
6115 switch (Op.getNode()->getOpcode()) {
6117 // Due to an isel shortcoming, be conservative if this add is likely to be
6118 // selected as part of a load-modify-store instruction. When the root node
6119 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6120 // uses of other nodes in the match, such as the ADD in this case. This
6121 // leads to the ADD being left around and reselected, with the result being
6122 // two adds in the output. Alas, even if none our users are stores, that
6123 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6124 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6125 // climbing the DAG back to the root, and it doesn't seem to be worth the
6127 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6128 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6129 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6132 if (ConstantSDNode *C =
6133 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6134 // An add of one will be selected as an INC.
6135 if (C->getAPIntValue() == 1) {
6136 Opcode = X86ISD::INC;
6141 // An add of negative one (subtract of one) will be selected as a DEC.
6142 if (C->getAPIntValue().isAllOnesValue()) {
6143 Opcode = X86ISD::DEC;
6149 // Otherwise use a regular EFLAGS-setting add.
6150 Opcode = X86ISD::ADD;
6154 // If the primary and result isn't used, don't bother using X86ISD::AND,
6155 // because a TEST instruction will be better.
6156 bool NonFlagUse = false;
6157 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6158 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6160 unsigned UOpNo = UI.getOperandNo();
6161 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6162 // Look pass truncate.
6163 UOpNo = User->use_begin().getOperandNo();
6164 User = *User->use_begin();
6167 if (User->getOpcode() != ISD::BRCOND &&
6168 User->getOpcode() != ISD::SETCC &&
6169 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6182 // Due to the ISEL shortcoming noted above, be conservative if this op is
6183 // likely to be selected as part of a load-modify-store instruction.
6184 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6185 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6186 if (UI->getOpcode() == ISD::STORE)
6189 // Otherwise use a regular EFLAGS-setting instruction.
6190 switch (Op.getNode()->getOpcode()) {
6191 default: llvm_unreachable("unexpected operator!");
6192 case ISD::SUB: Opcode = X86ISD::SUB; break;
6193 case ISD::OR: Opcode = X86ISD::OR; break;
6194 case ISD::XOR: Opcode = X86ISD::XOR; break;
6195 case ISD::AND: Opcode = X86ISD::AND; break;
6207 return SDValue(Op.getNode(), 1);
6214 // Emit a CMP with 0, which is the TEST pattern.
6215 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6216 DAG.getConstant(0, Op.getValueType()));
6218 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6219 SmallVector<SDValue, 4> Ops;
6220 for (unsigned i = 0; i != NumOperands; ++i)
6221 Ops.push_back(Op.getOperand(i));
6223 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6224 DAG.ReplaceAllUsesWith(Op, New);
6225 return SDValue(New.getNode(), 1);
6228 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6230 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6231 SelectionDAG &DAG) const {
6232 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6233 if (C->getAPIntValue() == 0)
6234 return EmitTest(Op0, X86CC, DAG);
6236 DebugLoc dl = Op0.getDebugLoc();
6237 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6240 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6241 /// if it's possible.
6242 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6243 DebugLoc dl, SelectionDAG &DAG) const {
6244 SDValue Op0 = And.getOperand(0);
6245 SDValue Op1 = And.getOperand(1);
6246 if (Op0.getOpcode() == ISD::TRUNCATE)
6247 Op0 = Op0.getOperand(0);
6248 if (Op1.getOpcode() == ISD::TRUNCATE)
6249 Op1 = Op1.getOperand(0);
6252 if (Op1.getOpcode() == ISD::SHL)
6253 std::swap(Op0, Op1);
6254 if (Op0.getOpcode() == ISD::SHL) {
6255 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6256 if (And00C->getZExtValue() == 1) {
6257 // If we looked past a truncate, check that it's only truncating away
6259 unsigned BitWidth = Op0.getValueSizeInBits();
6260 unsigned AndBitWidth = And.getValueSizeInBits();
6261 if (BitWidth > AndBitWidth) {
6262 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6263 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6264 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6268 RHS = Op0.getOperand(1);
6270 } else if (Op1.getOpcode() == ISD::Constant) {
6271 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6272 SDValue AndLHS = Op0;
6273 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6274 LHS = AndLHS.getOperand(0);
6275 RHS = AndLHS.getOperand(1);
6279 if (LHS.getNode()) {
6280 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6281 // instruction. Since the shift amount is in-range-or-undefined, we know
6282 // that doing a bittest on the i32 value is ok. We extend to i32 because
6283 // the encoding for the i16 version is larger than the i32 version.
6284 // Also promote i16 to i32 for performance / code size reason.
6285 if (LHS.getValueType() == MVT::i8 ||
6286 LHS.getValueType() == MVT::i16)
6287 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6289 // If the operand types disagree, extend the shift amount to match. Since
6290 // BT ignores high bits (like shifts) we can use anyextend.
6291 if (LHS.getValueType() != RHS.getValueType())
6292 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6294 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6295 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6296 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6297 DAG.getConstant(Cond, MVT::i8), BT);
6303 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6304 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6305 SDValue Op0 = Op.getOperand(0);
6306 SDValue Op1 = Op.getOperand(1);
6307 DebugLoc dl = Op.getDebugLoc();
6308 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6310 // Optimize to BT if possible.
6311 // Lower (X & (1 << N)) == 0 to BT(X, N).
6312 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6313 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6314 if (Op0.getOpcode() == ISD::AND &&
6316 Op1.getOpcode() == ISD::Constant &&
6317 cast<ConstantSDNode>(Op1)->isNullValue() &&
6318 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6319 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6320 if (NewSetCC.getNode())
6324 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6325 if (Op0.getOpcode() == X86ISD::SETCC &&
6326 Op1.getOpcode() == ISD::Constant &&
6327 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6328 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6329 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6330 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6331 bool Invert = (CC == ISD::SETNE) ^
6332 cast<ConstantSDNode>(Op1)->isNullValue();
6334 CCode = X86::GetOppositeBranchCondition(CCode);
6335 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6336 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6339 bool isFP = Op1.getValueType().isFloatingPoint();
6340 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6341 if (X86CC == X86::COND_INVALID)
6344 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6346 // Use sbb x, x to materialize carry bit into a GPR.
6347 if (X86CC == X86::COND_B)
6348 return DAG.getNode(ISD::AND, dl, MVT::i8,
6349 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6350 DAG.getConstant(X86CC, MVT::i8), Cond),
6351 DAG.getConstant(1, MVT::i8));
6353 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6354 DAG.getConstant(X86CC, MVT::i8), Cond);
6357 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6359 SDValue Op0 = Op.getOperand(0);
6360 SDValue Op1 = Op.getOperand(1);
6361 SDValue CC = Op.getOperand(2);
6362 EVT VT = Op.getValueType();
6363 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6364 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6365 DebugLoc dl = Op.getDebugLoc();
6369 EVT VT0 = Op0.getValueType();
6370 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6371 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6374 switch (SetCCOpcode) {
6377 case ISD::SETEQ: SSECC = 0; break;
6379 case ISD::SETGT: Swap = true; // Fallthrough
6381 case ISD::SETOLT: SSECC = 1; break;
6383 case ISD::SETGE: Swap = true; // Fallthrough
6385 case ISD::SETOLE: SSECC = 2; break;
6386 case ISD::SETUO: SSECC = 3; break;
6388 case ISD::SETNE: SSECC = 4; break;
6389 case ISD::SETULE: Swap = true;
6390 case ISD::SETUGE: SSECC = 5; break;
6391 case ISD::SETULT: Swap = true;
6392 case ISD::SETUGT: SSECC = 6; break;
6393 case ISD::SETO: SSECC = 7; break;
6396 std::swap(Op0, Op1);
6398 // In the two special cases we can't handle, emit two comparisons.
6400 if (SetCCOpcode == ISD::SETUEQ) {
6402 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6403 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6404 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6406 else if (SetCCOpcode == ISD::SETONE) {
6408 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6409 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6410 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6412 llvm_unreachable("Illegal FP comparison");
6414 // Handle all other FP comparisons here.
6415 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6418 // We are handling one of the integer comparisons here. Since SSE only has
6419 // GT and EQ comparisons for integer, swapping operands and multiple
6420 // operations may be required for some comparisons.
6421 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6422 bool Swap = false, Invert = false, FlipSigns = false;
6424 switch (VT.getSimpleVT().SimpleTy) {
6427 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6429 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6431 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6432 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6435 switch (SetCCOpcode) {
6437 case ISD::SETNE: Invert = true;
6438 case ISD::SETEQ: Opc = EQOpc; break;
6439 case ISD::SETLT: Swap = true;
6440 case ISD::SETGT: Opc = GTOpc; break;
6441 case ISD::SETGE: Swap = true;
6442 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6443 case ISD::SETULT: Swap = true;
6444 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6445 case ISD::SETUGE: Swap = true;
6446 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6449 std::swap(Op0, Op1);
6451 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6452 // bits of the inputs before performing those operations.
6454 EVT EltVT = VT.getVectorElementType();
6455 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6457 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6458 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6460 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6461 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6464 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6466 // If the logical-not of the result is required, perform that now.
6468 Result = DAG.getNOT(dl, Result, VT);
6473 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6474 static bool isX86LogicalCmp(SDValue Op) {
6475 unsigned Opc = Op.getNode()->getOpcode();
6476 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6478 if (Op.getResNo() == 1 &&
6479 (Opc == X86ISD::ADD ||
6480 Opc == X86ISD::SUB ||
6481 Opc == X86ISD::SMUL ||
6482 Opc == X86ISD::UMUL ||
6483 Opc == X86ISD::INC ||
6484 Opc == X86ISD::DEC ||
6485 Opc == X86ISD::OR ||
6486 Opc == X86ISD::XOR ||
6487 Opc == X86ISD::AND))
6493 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
6494 bool addTest = true;
6495 SDValue Cond = Op.getOperand(0);
6496 DebugLoc dl = Op.getDebugLoc();
6499 if (Cond.getOpcode() == ISD::SETCC) {
6500 SDValue NewCond = LowerSETCC(Cond, DAG);
6501 if (NewCond.getNode())
6505 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6506 SDValue Op1 = Op.getOperand(1);
6507 SDValue Op2 = Op.getOperand(2);
6508 if (Cond.getOpcode() == X86ISD::SETCC &&
6509 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6510 SDValue Cmp = Cond.getOperand(1);
6511 if (Cmp.getOpcode() == X86ISD::CMP) {
6512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6513 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6514 ConstantSDNode *RHSC =
6515 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6516 if (N1C && N1C->isAllOnesValue() &&
6517 N2C && N2C->isNullValue() &&
6518 RHSC && RHSC->isNullValue()) {
6519 SDValue CmpOp0 = Cmp.getOperand(0);
6520 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6521 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6522 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6523 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6528 // Look pass (and (setcc_carry (cmp ...)), 1).
6529 if (Cond.getOpcode() == ISD::AND &&
6530 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6531 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6532 if (C && C->getAPIntValue() == 1)
6533 Cond = Cond.getOperand(0);
6536 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6537 // setting operand in place of the X86ISD::SETCC.
6538 if (Cond.getOpcode() == X86ISD::SETCC ||
6539 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6540 CC = Cond.getOperand(0);
6542 SDValue Cmp = Cond.getOperand(1);
6543 unsigned Opc = Cmp.getOpcode();
6544 EVT VT = Op.getValueType();
6546 bool IllegalFPCMov = false;
6547 if (VT.isFloatingPoint() && !VT.isVector() &&
6548 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6549 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6551 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6552 Opc == X86ISD::BT) { // FIXME
6559 // Look pass the truncate.
6560 if (Cond.getOpcode() == ISD::TRUNCATE)
6561 Cond = Cond.getOperand(0);
6563 // We know the result of AND is compared against zero. Try to match
6565 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6566 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6567 if (NewSetCC.getNode()) {
6568 CC = NewSetCC.getOperand(0);
6569 Cond = NewSetCC.getOperand(1);
6576 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6577 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6580 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6581 // condition is true.
6582 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6583 SDValue Ops[] = { Op2, Op1, CC, Cond };
6584 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6587 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6588 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6589 // from the AND / OR.
6590 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6591 Opc = Op.getOpcode();
6592 if (Opc != ISD::OR && Opc != ISD::AND)
6594 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6595 Op.getOperand(0).hasOneUse() &&
6596 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6597 Op.getOperand(1).hasOneUse());
6600 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6601 // 1 and that the SETCC node has a single use.
6602 static bool isXor1OfSetCC(SDValue Op) {
6603 if (Op.getOpcode() != ISD::XOR)
6605 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6606 if (N1C && N1C->getAPIntValue() == 1) {
6607 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6608 Op.getOperand(0).hasOneUse();
6613 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
6614 bool addTest = true;
6615 SDValue Chain = Op.getOperand(0);
6616 SDValue Cond = Op.getOperand(1);
6617 SDValue Dest = Op.getOperand(2);
6618 DebugLoc dl = Op.getDebugLoc();
6621 if (Cond.getOpcode() == ISD::SETCC) {
6622 SDValue NewCond = LowerSETCC(Cond, DAG);
6623 if (NewCond.getNode())
6627 // FIXME: LowerXALUO doesn't handle these!!
6628 else if (Cond.getOpcode() == X86ISD::ADD ||
6629 Cond.getOpcode() == X86ISD::SUB ||
6630 Cond.getOpcode() == X86ISD::SMUL ||
6631 Cond.getOpcode() == X86ISD::UMUL)
6632 Cond = LowerXALUO(Cond, DAG);
6635 // Look pass (and (setcc_carry (cmp ...)), 1).
6636 if (Cond.getOpcode() == ISD::AND &&
6637 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6638 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6639 if (C && C->getAPIntValue() == 1)
6640 Cond = Cond.getOperand(0);
6643 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6644 // setting operand in place of the X86ISD::SETCC.
6645 if (Cond.getOpcode() == X86ISD::SETCC ||
6646 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6647 CC = Cond.getOperand(0);
6649 SDValue Cmp = Cond.getOperand(1);
6650 unsigned Opc = Cmp.getOpcode();
6651 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6652 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6656 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6660 // These can only come from an arithmetic instruction with overflow,
6661 // e.g. SADDO, UADDO.
6662 Cond = Cond.getNode()->getOperand(1);
6669 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6670 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6671 if (CondOpc == ISD::OR) {
6672 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6673 // two branches instead of an explicit OR instruction with a
6675 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6676 isX86LogicalCmp(Cmp)) {
6677 CC = Cond.getOperand(0).getOperand(0);
6678 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6679 Chain, Dest, CC, Cmp);
6680 CC = Cond.getOperand(1).getOperand(0);
6684 } else { // ISD::AND
6685 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6686 // two branches instead of an explicit AND instruction with a
6687 // separate test. However, we only do this if this block doesn't
6688 // have a fall-through edge, because this requires an explicit
6689 // jmp when the condition is false.
6690 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6691 isX86LogicalCmp(Cmp) &&
6692 Op.getNode()->hasOneUse()) {
6693 X86::CondCode CCode =
6694 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6695 CCode = X86::GetOppositeBranchCondition(CCode);
6696 CC = DAG.getConstant(CCode, MVT::i8);
6697 SDNode *User = *Op.getNode()->use_begin();
6698 // Look for an unconditional branch following this conditional branch.
6699 // We need this because we need to reverse the successors in order
6700 // to implement FCMP_OEQ.
6701 if (User->getOpcode() == ISD::BR) {
6702 SDValue FalseBB = User->getOperand(1);
6704 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
6705 assert(NewBR == User);
6709 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6710 Chain, Dest, CC, Cmp);
6711 X86::CondCode CCode =
6712 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6713 CCode = X86::GetOppositeBranchCondition(CCode);
6714 CC = DAG.getConstant(CCode, MVT::i8);
6720 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6721 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6722 // It should be transformed during dag combiner except when the condition
6723 // is set by a arithmetics with overflow node.
6724 X86::CondCode CCode =
6725 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6726 CCode = X86::GetOppositeBranchCondition(CCode);
6727 CC = DAG.getConstant(CCode, MVT::i8);
6728 Cond = Cond.getOperand(0).getOperand(1);
6734 // Look pass the truncate.
6735 if (Cond.getOpcode() == ISD::TRUNCATE)
6736 Cond = Cond.getOperand(0);
6738 // We know the result of AND is compared against zero. Try to match
6740 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6741 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6742 if (NewSetCC.getNode()) {
6743 CC = NewSetCC.getOperand(0);
6744 Cond = NewSetCC.getOperand(1);
6751 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6752 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6754 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6755 Chain, Dest, CC, Cond);
6759 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6760 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6761 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6762 // that the guard pages used by the OS virtual memory manager are allocated in
6763 // correct sequence.
6765 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6766 SelectionDAG &DAG) const {
6767 assert(Subtarget->isTargetCygMing() &&
6768 "This should be used only on Cygwin/Mingw targets");
6769 DebugLoc dl = Op.getDebugLoc();
6772 SDValue Chain = Op.getOperand(0);
6773 SDValue Size = Op.getOperand(1);
6774 // FIXME: Ensure alignment here
6778 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6780 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6781 Flag = Chain.getValue(1);
6783 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6785 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6786 Flag = Chain.getValue(1);
6788 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6790 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6791 return DAG.getMergeValues(Ops1, 2, dl);
6794 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
6795 MachineFunction &MF = DAG.getMachineFunction();
6796 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
6798 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6799 DebugLoc dl = Op.getDebugLoc();
6801 if (!Subtarget->is64Bit()) {
6802 // vastart just stores the address of the VarArgsFrameIndex slot into the
6803 // memory location argument.
6804 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6806 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6811 // gp_offset (0 - 6 * 8)
6812 // fp_offset (48 - 48 + 8 * 16)
6813 // overflow_arg_area (point to parameters coming in memory).
6815 SmallVector<SDValue, 8> MemOps;
6816 SDValue FIN = Op.getOperand(1);
6818 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6819 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
6821 FIN, SV, 0, false, false, 0);
6822 MemOps.push_back(Store);
6825 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6826 FIN, DAG.getIntPtrConstant(4));
6827 Store = DAG.getStore(Op.getOperand(0), dl,
6828 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
6830 FIN, SV, 4, false, false, 0);
6831 MemOps.push_back(Store);
6833 // Store ptr to overflow_arg_area
6834 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6835 FIN, DAG.getIntPtrConstant(4));
6836 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6838 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8,
6840 MemOps.push_back(Store);
6842 // Store ptr to reg_save_area.
6843 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6844 FIN, DAG.getIntPtrConstant(8));
6845 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
6847 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16,
6849 MemOps.push_back(Store);
6850 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6851 &MemOps[0], MemOps.size());
6854 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
6855 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6856 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6858 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
6862 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
6863 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6864 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6865 SDValue Chain = Op.getOperand(0);
6866 SDValue DstPtr = Op.getOperand(1);
6867 SDValue SrcPtr = Op.getOperand(2);
6868 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6869 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6870 DebugLoc dl = Op.getDebugLoc();
6872 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6873 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
6874 false, DstSV, 0, SrcSV, 0);
6878 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
6879 DebugLoc dl = Op.getDebugLoc();
6880 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6882 default: return SDValue(); // Don't custom lower most intrinsics.
6883 // Comparison intrinsics.
6884 case Intrinsic::x86_sse_comieq_ss:
6885 case Intrinsic::x86_sse_comilt_ss:
6886 case Intrinsic::x86_sse_comile_ss:
6887 case Intrinsic::x86_sse_comigt_ss:
6888 case Intrinsic::x86_sse_comige_ss:
6889 case Intrinsic::x86_sse_comineq_ss:
6890 case Intrinsic::x86_sse_ucomieq_ss:
6891 case Intrinsic::x86_sse_ucomilt_ss:
6892 case Intrinsic::x86_sse_ucomile_ss:
6893 case Intrinsic::x86_sse_ucomigt_ss:
6894 case Intrinsic::x86_sse_ucomige_ss:
6895 case Intrinsic::x86_sse_ucomineq_ss:
6896 case Intrinsic::x86_sse2_comieq_sd:
6897 case Intrinsic::x86_sse2_comilt_sd:
6898 case Intrinsic::x86_sse2_comile_sd:
6899 case Intrinsic::x86_sse2_comigt_sd:
6900 case Intrinsic::x86_sse2_comige_sd:
6901 case Intrinsic::x86_sse2_comineq_sd:
6902 case Intrinsic::x86_sse2_ucomieq_sd:
6903 case Intrinsic::x86_sse2_ucomilt_sd:
6904 case Intrinsic::x86_sse2_ucomile_sd:
6905 case Intrinsic::x86_sse2_ucomigt_sd:
6906 case Intrinsic::x86_sse2_ucomige_sd:
6907 case Intrinsic::x86_sse2_ucomineq_sd: {
6909 ISD::CondCode CC = ISD::SETCC_INVALID;
6912 case Intrinsic::x86_sse_comieq_ss:
6913 case Intrinsic::x86_sse2_comieq_sd:
6917 case Intrinsic::x86_sse_comilt_ss:
6918 case Intrinsic::x86_sse2_comilt_sd:
6922 case Intrinsic::x86_sse_comile_ss:
6923 case Intrinsic::x86_sse2_comile_sd:
6927 case Intrinsic::x86_sse_comigt_ss:
6928 case Intrinsic::x86_sse2_comigt_sd:
6932 case Intrinsic::x86_sse_comige_ss:
6933 case Intrinsic::x86_sse2_comige_sd:
6937 case Intrinsic::x86_sse_comineq_ss:
6938 case Intrinsic::x86_sse2_comineq_sd:
6942 case Intrinsic::x86_sse_ucomieq_ss:
6943 case Intrinsic::x86_sse2_ucomieq_sd:
6944 Opc = X86ISD::UCOMI;
6947 case Intrinsic::x86_sse_ucomilt_ss:
6948 case Intrinsic::x86_sse2_ucomilt_sd:
6949 Opc = X86ISD::UCOMI;
6952 case Intrinsic::x86_sse_ucomile_ss:
6953 case Intrinsic::x86_sse2_ucomile_sd:
6954 Opc = X86ISD::UCOMI;
6957 case Intrinsic::x86_sse_ucomigt_ss:
6958 case Intrinsic::x86_sse2_ucomigt_sd:
6959 Opc = X86ISD::UCOMI;
6962 case Intrinsic::x86_sse_ucomige_ss:
6963 case Intrinsic::x86_sse2_ucomige_sd:
6964 Opc = X86ISD::UCOMI;
6967 case Intrinsic::x86_sse_ucomineq_ss:
6968 case Intrinsic::x86_sse2_ucomineq_sd:
6969 Opc = X86ISD::UCOMI;
6974 SDValue LHS = Op.getOperand(1);
6975 SDValue RHS = Op.getOperand(2);
6976 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6977 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6978 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6979 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6980 DAG.getConstant(X86CC, MVT::i8), Cond);
6981 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6983 // ptest intrinsics. The intrinsic these come from are designed to return
6984 // an integer value, not just an instruction so lower it to the ptest
6985 // pattern and a setcc for the result.
6986 case Intrinsic::x86_sse41_ptestz:
6987 case Intrinsic::x86_sse41_ptestc:
6988 case Intrinsic::x86_sse41_ptestnzc:{
6991 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6992 case Intrinsic::x86_sse41_ptestz:
6994 X86CC = X86::COND_E;
6996 case Intrinsic::x86_sse41_ptestc:
6998 X86CC = X86::COND_B;
7000 case Intrinsic::x86_sse41_ptestnzc:
7002 X86CC = X86::COND_A;
7006 SDValue LHS = Op.getOperand(1);
7007 SDValue RHS = Op.getOperand(2);
7008 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
7009 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7010 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7011 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7014 // Fix vector shift instructions where the last operand is a non-immediate
7016 case Intrinsic::x86_sse2_pslli_w:
7017 case Intrinsic::x86_sse2_pslli_d:
7018 case Intrinsic::x86_sse2_pslli_q:
7019 case Intrinsic::x86_sse2_psrli_w:
7020 case Intrinsic::x86_sse2_psrli_d:
7021 case Intrinsic::x86_sse2_psrli_q:
7022 case Intrinsic::x86_sse2_psrai_w:
7023 case Intrinsic::x86_sse2_psrai_d:
7024 case Intrinsic::x86_mmx_pslli_w:
7025 case Intrinsic::x86_mmx_pslli_d:
7026 case Intrinsic::x86_mmx_pslli_q:
7027 case Intrinsic::x86_mmx_psrli_w:
7028 case Intrinsic::x86_mmx_psrli_d:
7029 case Intrinsic::x86_mmx_psrli_q:
7030 case Intrinsic::x86_mmx_psrai_w:
7031 case Intrinsic::x86_mmx_psrai_d: {
7032 SDValue ShAmt = Op.getOperand(2);
7033 if (isa<ConstantSDNode>(ShAmt))
7036 unsigned NewIntNo = 0;
7037 EVT ShAmtVT = MVT::v4i32;
7039 case Intrinsic::x86_sse2_pslli_w:
7040 NewIntNo = Intrinsic::x86_sse2_psll_w;
7042 case Intrinsic::x86_sse2_pslli_d:
7043 NewIntNo = Intrinsic::x86_sse2_psll_d;
7045 case Intrinsic::x86_sse2_pslli_q:
7046 NewIntNo = Intrinsic::x86_sse2_psll_q;
7048 case Intrinsic::x86_sse2_psrli_w:
7049 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7051 case Intrinsic::x86_sse2_psrli_d:
7052 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7054 case Intrinsic::x86_sse2_psrli_q:
7055 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7057 case Intrinsic::x86_sse2_psrai_w:
7058 NewIntNo = Intrinsic::x86_sse2_psra_w;
7060 case Intrinsic::x86_sse2_psrai_d:
7061 NewIntNo = Intrinsic::x86_sse2_psra_d;
7064 ShAmtVT = MVT::v2i32;
7066 case Intrinsic::x86_mmx_pslli_w:
7067 NewIntNo = Intrinsic::x86_mmx_psll_w;
7069 case Intrinsic::x86_mmx_pslli_d:
7070 NewIntNo = Intrinsic::x86_mmx_psll_d;
7072 case Intrinsic::x86_mmx_pslli_q:
7073 NewIntNo = Intrinsic::x86_mmx_psll_q;
7075 case Intrinsic::x86_mmx_psrli_w:
7076 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7078 case Intrinsic::x86_mmx_psrli_d:
7079 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7081 case Intrinsic::x86_mmx_psrli_q:
7082 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7084 case Intrinsic::x86_mmx_psrai_w:
7085 NewIntNo = Intrinsic::x86_mmx_psra_w;
7087 case Intrinsic::x86_mmx_psrai_d:
7088 NewIntNo = Intrinsic::x86_mmx_psra_d;
7090 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7096 // The vector shift intrinsics with scalars uses 32b shift amounts but
7097 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7101 ShOps[1] = DAG.getConstant(0, MVT::i32);
7102 if (ShAmtVT == MVT::v4i32) {
7103 ShOps[2] = DAG.getUNDEF(MVT::i32);
7104 ShOps[3] = DAG.getUNDEF(MVT::i32);
7105 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7107 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7110 EVT VT = Op.getValueType();
7111 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7112 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7113 DAG.getConstant(NewIntNo, MVT::i32),
7114 Op.getOperand(1), ShAmt);
7119 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7120 SelectionDAG &DAG) const {
7121 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7122 MFI->setReturnAddressIsTaken(true);
7124 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7125 DebugLoc dl = Op.getDebugLoc();
7128 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7130 DAG.getConstant(TD->getPointerSize(),
7131 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7132 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7133 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7135 NULL, 0, false, false, 0);
7138 // Just load the return address.
7139 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7140 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7141 RetAddrFI, NULL, 0, false, false, 0);
7144 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7145 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7146 MFI->setFrameAddressIsTaken(true);
7148 EVT VT = Op.getValueType();
7149 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7150 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7151 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7152 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7154 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7159 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7160 SelectionDAG &DAG) const {
7161 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7164 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7165 MachineFunction &MF = DAG.getMachineFunction();
7166 SDValue Chain = Op.getOperand(0);
7167 SDValue Offset = Op.getOperand(1);
7168 SDValue Handler = Op.getOperand(2);
7169 DebugLoc dl = Op.getDebugLoc();
7171 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7173 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7175 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7176 DAG.getIntPtrConstant(-TD->getPointerSize()));
7177 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7178 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7179 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7180 MF.getRegInfo().addLiveOut(StoreAddrReg);
7182 return DAG.getNode(X86ISD::EH_RETURN, dl,
7184 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7187 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7188 SelectionDAG &DAG) const {
7189 SDValue Root = Op.getOperand(0);
7190 SDValue Trmp = Op.getOperand(1); // trampoline
7191 SDValue FPtr = Op.getOperand(2); // nested function
7192 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7193 DebugLoc dl = Op.getDebugLoc();
7195 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7197 if (Subtarget->is64Bit()) {
7198 SDValue OutChains[6];
7200 // Large code-model.
7201 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7202 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7204 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7205 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7207 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7209 // Load the pointer to the nested function into R11.
7210 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7211 SDValue Addr = Trmp;
7212 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7213 Addr, TrmpAddr, 0, false, false, 0);
7215 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7216 DAG.getConstant(2, MVT::i64));
7217 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7220 // Load the 'nest' parameter value into R10.
7221 // R10 is specified in X86CallingConv.td
7222 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7223 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7224 DAG.getConstant(10, MVT::i64));
7225 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7226 Addr, TrmpAddr, 10, false, false, 0);
7228 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7229 DAG.getConstant(12, MVT::i64));
7230 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7233 // Jump to the nested function.
7234 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7235 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7236 DAG.getConstant(20, MVT::i64));
7237 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7238 Addr, TrmpAddr, 20, false, false, 0);
7240 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7241 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7242 DAG.getConstant(22, MVT::i64));
7243 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7244 TrmpAddr, 22, false, false, 0);
7247 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7248 return DAG.getMergeValues(Ops, 2, dl);
7250 const Function *Func =
7251 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7252 CallingConv::ID CC = Func->getCallingConv();
7257 llvm_unreachable("Unsupported calling convention");
7258 case CallingConv::C:
7259 case CallingConv::X86_StdCall: {
7260 // Pass 'nest' parameter in ECX.
7261 // Must be kept in sync with X86CallingConv.td
7264 // Check that ECX wasn't needed by an 'inreg' parameter.
7265 const FunctionType *FTy = Func->getFunctionType();
7266 const AttrListPtr &Attrs = Func->getAttributes();
7268 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7269 unsigned InRegCount = 0;
7272 for (FunctionType::param_iterator I = FTy->param_begin(),
7273 E = FTy->param_end(); I != E; ++I, ++Idx)
7274 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7275 // FIXME: should only count parameters that are lowered to integers.
7276 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7278 if (InRegCount > 2) {
7279 report_fatal_error("Nest register in use - reduce number of inreg"
7285 case CallingConv::X86_FastCall:
7286 case CallingConv::X86_ThisCall:
7287 case CallingConv::Fast:
7288 // Pass 'nest' parameter in EAX.
7289 // Must be kept in sync with X86CallingConv.td
7294 SDValue OutChains[4];
7297 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7298 DAG.getConstant(10, MVT::i32));
7299 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7301 // This is storing the opcode for MOV32ri.
7302 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7303 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7304 OutChains[0] = DAG.getStore(Root, dl,
7305 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7306 Trmp, TrmpAddr, 0, false, false, 0);
7308 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7309 DAG.getConstant(1, MVT::i32));
7310 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7313 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7314 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7315 DAG.getConstant(5, MVT::i32));
7316 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7317 TrmpAddr, 5, false, false, 1);
7319 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7320 DAG.getConstant(6, MVT::i32));
7321 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7325 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7326 return DAG.getMergeValues(Ops, 2, dl);
7330 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7331 SelectionDAG &DAG) const {
7333 The rounding mode is in bits 11:10 of FPSR, and has the following
7340 FLT_ROUNDS, on the other hand, expects the following:
7347 To perform the conversion, we do:
7348 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7351 MachineFunction &MF = DAG.getMachineFunction();
7352 const TargetMachine &TM = MF.getTarget();
7353 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7354 unsigned StackAlignment = TFI.getStackAlignment();
7355 EVT VT = Op.getValueType();
7356 DebugLoc dl = Op.getDebugLoc();
7358 // Save FP Control Word to stack slot
7359 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7360 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7362 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7363 DAG.getEntryNode(), StackSlot);
7365 // Load FP Control Word from stack slot
7366 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7369 // Transform as necessary
7371 DAG.getNode(ISD::SRL, dl, MVT::i16,
7372 DAG.getNode(ISD::AND, dl, MVT::i16,
7373 CWD, DAG.getConstant(0x800, MVT::i16)),
7374 DAG.getConstant(11, MVT::i8));
7376 DAG.getNode(ISD::SRL, dl, MVT::i16,
7377 DAG.getNode(ISD::AND, dl, MVT::i16,
7378 CWD, DAG.getConstant(0x400, MVT::i16)),
7379 DAG.getConstant(9, MVT::i8));
7382 DAG.getNode(ISD::AND, dl, MVT::i16,
7383 DAG.getNode(ISD::ADD, dl, MVT::i16,
7384 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7385 DAG.getConstant(1, MVT::i16)),
7386 DAG.getConstant(3, MVT::i16));
7389 return DAG.getNode((VT.getSizeInBits() < 16 ?
7390 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7393 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
7394 EVT VT = Op.getValueType();
7396 unsigned NumBits = VT.getSizeInBits();
7397 DebugLoc dl = Op.getDebugLoc();
7399 Op = Op.getOperand(0);
7400 if (VT == MVT::i8) {
7401 // Zero extend to i32 since there is not an i8 bsr.
7403 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7406 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7407 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7408 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7410 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7413 DAG.getConstant(NumBits+NumBits-1, OpVT),
7414 DAG.getConstant(X86::COND_E, MVT::i8),
7417 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7419 // Finally xor with NumBits-1.
7420 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7423 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7427 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
7428 EVT VT = Op.getValueType();
7430 unsigned NumBits = VT.getSizeInBits();
7431 DebugLoc dl = Op.getDebugLoc();
7433 Op = Op.getOperand(0);
7434 if (VT == MVT::i8) {
7436 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7439 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7440 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7441 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7443 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7446 DAG.getConstant(NumBits, OpVT),
7447 DAG.getConstant(X86::COND_E, MVT::i8),
7450 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7453 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7457 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
7458 EVT VT = Op.getValueType();
7459 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7460 DebugLoc dl = Op.getDebugLoc();
7462 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7463 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7464 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7465 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7466 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7468 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7469 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7470 // return AloBlo + AloBhi + AhiBlo;
7472 SDValue A = Op.getOperand(0);
7473 SDValue B = Op.getOperand(1);
7475 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7476 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7477 A, DAG.getConstant(32, MVT::i32));
7478 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7479 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7480 B, DAG.getConstant(32, MVT::i32));
7481 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7482 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7484 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7485 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7487 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7488 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7490 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7491 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7492 AloBhi, DAG.getConstant(32, MVT::i32));
7493 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7494 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7495 AhiBlo, DAG.getConstant(32, MVT::i32));
7496 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7497 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7502 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
7503 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7504 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7505 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7506 // has only one use.
7507 SDNode *N = Op.getNode();
7508 SDValue LHS = N->getOperand(0);
7509 SDValue RHS = N->getOperand(1);
7510 unsigned BaseOp = 0;
7512 DebugLoc dl = Op.getDebugLoc();
7514 switch (Op.getOpcode()) {
7515 default: llvm_unreachable("Unknown ovf instruction!");
7517 // A subtract of one will be selected as a INC. Note that INC doesn't
7518 // set CF, so we can't do this for UADDO.
7519 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7520 if (C->getAPIntValue() == 1) {
7521 BaseOp = X86ISD::INC;
7525 BaseOp = X86ISD::ADD;
7529 BaseOp = X86ISD::ADD;
7533 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7534 // set CF, so we can't do this for USUBO.
7535 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7536 if (C->getAPIntValue() == 1) {
7537 BaseOp = X86ISD::DEC;
7541 BaseOp = X86ISD::SUB;
7545 BaseOp = X86ISD::SUB;
7549 BaseOp = X86ISD::SMUL;
7553 BaseOp = X86ISD::UMUL;
7558 // Also sets EFLAGS.
7559 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7560 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7563 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7564 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7566 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7570 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
7571 DebugLoc dl = Op.getDebugLoc();
7573 if (!Subtarget->hasSSE2())
7574 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
7575 DAG.getConstant(0, MVT::i32));
7577 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
7579 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
7581 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7582 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
7583 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
7584 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
7586 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
7587 if (!Op1 && !Op2 && !Op3 && Op4)
7588 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
7590 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
7591 if (Op1 && !Op2 && !Op3 && !Op4)
7592 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
7594 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
7596 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
7600 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
7601 EVT T = Op.getValueType();
7602 DebugLoc dl = Op.getDebugLoc();
7605 switch(T.getSimpleVT().SimpleTy) {
7607 assert(false && "Invalid value type!");
7608 case MVT::i8: Reg = X86::AL; size = 1; break;
7609 case MVT::i16: Reg = X86::AX; size = 2; break;
7610 case MVT::i32: Reg = X86::EAX; size = 4; break;
7612 assert(Subtarget->is64Bit() && "Node not type legal!");
7613 Reg = X86::RAX; size = 8;
7616 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7617 Op.getOperand(2), SDValue());
7618 SDValue Ops[] = { cpIn.getValue(0),
7621 DAG.getTargetConstant(size, MVT::i8),
7623 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7624 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7626 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7630 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7631 SelectionDAG &DAG) const {
7632 assert(Subtarget->is64Bit() && "Result not type legalized?");
7633 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7634 SDValue TheChain = Op.getOperand(0);
7635 DebugLoc dl = Op.getDebugLoc();
7636 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7637 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7638 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7640 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7641 DAG.getConstant(32, MVT::i8));
7643 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7646 return DAG.getMergeValues(Ops, 2, dl);
7649 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
7650 SelectionDAG &DAG) const {
7651 EVT SrcVT = Op.getOperand(0).getValueType();
7652 EVT DstVT = Op.getValueType();
7653 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
7654 Subtarget->hasMMX() && !DisableMMX) &&
7655 "Unexpected custom BIT_CONVERT");
7656 assert((DstVT == MVT::i64 ||
7657 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
7658 "Unexpected custom BIT_CONVERT");
7659 // i64 <=> MMX conversions are Legal.
7660 if (SrcVT==MVT::i64 && DstVT.isVector())
7662 if (DstVT==MVT::i64 && SrcVT.isVector())
7664 // MMX <=> MMX conversions are Legal.
7665 if (SrcVT.isVector() && DstVT.isVector())
7667 // All other conversions need to be expanded.
7670 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
7671 SDNode *Node = Op.getNode();
7672 DebugLoc dl = Node->getDebugLoc();
7673 EVT T = Node->getValueType(0);
7674 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7675 DAG.getConstant(0, T), Node->getOperand(2));
7676 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7677 cast<AtomicSDNode>(Node)->getMemoryVT(),
7678 Node->getOperand(0),
7679 Node->getOperand(1), negOp,
7680 cast<AtomicSDNode>(Node)->getSrcValue(),
7681 cast<AtomicSDNode>(Node)->getAlignment());
7684 /// LowerOperation - Provide custom lowering hooks for some operations.
7686 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7687 switch (Op.getOpcode()) {
7688 default: llvm_unreachable("Should not custom lower this!");
7689 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
7690 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7691 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7692 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7693 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7694 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7695 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7696 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7697 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7698 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7699 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7700 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7701 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7702 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7703 case ISD::SHL_PARTS:
7704 case ISD::SRA_PARTS:
7705 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7706 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7707 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7708 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7709 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7710 case ISD::FABS: return LowerFABS(Op, DAG);
7711 case ISD::FNEG: return LowerFNEG(Op, DAG);
7712 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7713 case ISD::SETCC: return LowerSETCC(Op, DAG);
7714 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7715 case ISD::SELECT: return LowerSELECT(Op, DAG);
7716 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7717 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7718 case ISD::VASTART: return LowerVASTART(Op, DAG);
7719 case ISD::VAARG: return LowerVAARG(Op, DAG);
7720 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7721 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7722 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7723 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7724 case ISD::FRAME_TO_ARGS_OFFSET:
7725 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7726 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7727 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7728 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7729 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7730 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7731 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7732 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7738 case ISD::UMULO: return LowerXALUO(Op, DAG);
7739 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7740 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
7744 void X86TargetLowering::
7745 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7746 SelectionDAG &DAG, unsigned NewOp) const {
7747 EVT T = Node->getValueType(0);
7748 DebugLoc dl = Node->getDebugLoc();
7749 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7751 SDValue Chain = Node->getOperand(0);
7752 SDValue In1 = Node->getOperand(1);
7753 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7754 Node->getOperand(2), DAG.getIntPtrConstant(0));
7755 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7756 Node->getOperand(2), DAG.getIntPtrConstant(1));
7757 SDValue Ops[] = { Chain, In1, In2L, In2H };
7758 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7760 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7761 cast<MemSDNode>(Node)->getMemOperand());
7762 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7763 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7764 Results.push_back(Result.getValue(2));
7767 /// ReplaceNodeResults - Replace a node with an illegal result type
7768 /// with a new node built out of custom code.
7769 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7770 SmallVectorImpl<SDValue>&Results,
7771 SelectionDAG &DAG) const {
7772 DebugLoc dl = N->getDebugLoc();
7773 switch (N->getOpcode()) {
7775 assert(false && "Do not know how to custom type legalize this operation!");
7777 case ISD::FP_TO_SINT: {
7778 std::pair<SDValue,SDValue> Vals =
7779 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7780 SDValue FIST = Vals.first, StackSlot = Vals.second;
7781 if (FIST.getNode() != 0) {
7782 EVT VT = N->getValueType(0);
7783 // Return a load from the stack slot.
7784 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7789 case ISD::READCYCLECOUNTER: {
7790 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7791 SDValue TheChain = N->getOperand(0);
7792 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7793 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7795 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7797 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7798 SDValue Ops[] = { eax, edx };
7799 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7800 Results.push_back(edx.getValue(1));
7803 case ISD::ATOMIC_CMP_SWAP: {
7804 EVT T = N->getValueType(0);
7805 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7806 SDValue cpInL, cpInH;
7807 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7808 DAG.getConstant(0, MVT::i32));
7809 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7810 DAG.getConstant(1, MVT::i32));
7811 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7812 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7814 SDValue swapInL, swapInH;
7815 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7816 DAG.getConstant(0, MVT::i32));
7817 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7818 DAG.getConstant(1, MVT::i32));
7819 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7821 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7822 swapInL.getValue(1));
7823 SDValue Ops[] = { swapInH.getValue(0),
7825 swapInH.getValue(1) };
7826 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7827 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7828 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7829 MVT::i32, Result.getValue(1));
7830 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7831 MVT::i32, cpOutL.getValue(2));
7832 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7833 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7834 Results.push_back(cpOutH.getValue(1));
7837 case ISD::ATOMIC_LOAD_ADD:
7838 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7840 case ISD::ATOMIC_LOAD_AND:
7841 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7843 case ISD::ATOMIC_LOAD_NAND:
7844 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7846 case ISD::ATOMIC_LOAD_OR:
7847 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7849 case ISD::ATOMIC_LOAD_SUB:
7850 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7852 case ISD::ATOMIC_LOAD_XOR:
7853 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7855 case ISD::ATOMIC_SWAP:
7856 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7861 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7863 default: return NULL;
7864 case X86ISD::BSF: return "X86ISD::BSF";
7865 case X86ISD::BSR: return "X86ISD::BSR";
7866 case X86ISD::SHLD: return "X86ISD::SHLD";
7867 case X86ISD::SHRD: return "X86ISD::SHRD";
7868 case X86ISD::FAND: return "X86ISD::FAND";
7869 case X86ISD::FOR: return "X86ISD::FOR";
7870 case X86ISD::FXOR: return "X86ISD::FXOR";
7871 case X86ISD::FSRL: return "X86ISD::FSRL";
7872 case X86ISD::FILD: return "X86ISD::FILD";
7873 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7874 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7875 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7876 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7877 case X86ISD::FLD: return "X86ISD::FLD";
7878 case X86ISD::FST: return "X86ISD::FST";
7879 case X86ISD::CALL: return "X86ISD::CALL";
7880 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7881 case X86ISD::BT: return "X86ISD::BT";
7882 case X86ISD::CMP: return "X86ISD::CMP";
7883 case X86ISD::COMI: return "X86ISD::COMI";
7884 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7885 case X86ISD::SETCC: return "X86ISD::SETCC";
7886 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7887 case X86ISD::CMOV: return "X86ISD::CMOV";
7888 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7889 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7890 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7891 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7892 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7893 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7894 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7895 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7896 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7897 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7898 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7899 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7900 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7901 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7902 case X86ISD::FMAX: return "X86ISD::FMAX";
7903 case X86ISD::FMIN: return "X86ISD::FMIN";
7904 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7905 case X86ISD::FRCP: return "X86ISD::FRCP";
7906 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7907 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
7908 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7909 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7910 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7911 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7912 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7913 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7914 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7915 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7916 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7917 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7918 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7919 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7920 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7921 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7922 case X86ISD::VSHL: return "X86ISD::VSHL";
7923 case X86ISD::VSRL: return "X86ISD::VSRL";
7924 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7925 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7926 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7927 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7928 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7929 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7930 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7931 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7932 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7933 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7934 case X86ISD::ADD: return "X86ISD::ADD";
7935 case X86ISD::SUB: return "X86ISD::SUB";
7936 case X86ISD::SMUL: return "X86ISD::SMUL";
7937 case X86ISD::UMUL: return "X86ISD::UMUL";
7938 case X86ISD::INC: return "X86ISD::INC";
7939 case X86ISD::DEC: return "X86ISD::DEC";
7940 case X86ISD::OR: return "X86ISD::OR";
7941 case X86ISD::XOR: return "X86ISD::XOR";
7942 case X86ISD::AND: return "X86ISD::AND";
7943 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7944 case X86ISD::PTEST: return "X86ISD::PTEST";
7945 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7946 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7950 // isLegalAddressingMode - Return true if the addressing mode represented
7951 // by AM is legal for this target, for a load/store of the specified type.
7952 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7953 const Type *Ty) const {
7954 // X86 supports extremely general addressing modes.
7955 CodeModel::Model M = getTargetMachine().getCodeModel();
7957 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7958 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7963 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7965 // If a reference to this global requires an extra load, we can't fold it.
7966 if (isGlobalStubReference(GVFlags))
7969 // If BaseGV requires a register for the PIC base, we cannot also have a
7970 // BaseReg specified.
7971 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7974 // If lower 4G is not available, then we must use rip-relative addressing.
7975 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7985 // These scales always work.
7990 // These scales are formed with basereg+scalereg. Only accept if there is
7995 default: // Other stuff never works.
8003 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
8004 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8006 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8007 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8008 if (NumBits1 <= NumBits2)
8013 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8014 if (!VT1.isInteger() || !VT2.isInteger())
8016 unsigned NumBits1 = VT1.getSizeInBits();
8017 unsigned NumBits2 = VT2.getSizeInBits();
8018 if (NumBits1 <= NumBits2)
8023 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
8024 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8025 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
8028 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
8029 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8030 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
8033 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
8034 // i16 instructions are longer (0x66 prefix) and potentially slower.
8035 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
8038 /// isShuffleMaskLegal - Targets can use this to indicate that they only
8039 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
8040 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
8041 /// are assumed to be legal.
8043 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
8045 // Very little shuffling can be done for 64-bit vectors right now.
8046 if (VT.getSizeInBits() == 64)
8047 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
8049 // FIXME: pshufb, blends, shifts.
8050 return (VT.getVectorNumElements() == 2 ||
8051 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
8052 isMOVLMask(M, VT) ||
8053 isSHUFPMask(M, VT) ||
8054 isPSHUFDMask(M, VT) ||
8055 isPSHUFHWMask(M, VT) ||
8056 isPSHUFLWMask(M, VT) ||
8057 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
8058 isUNPCKLMask(M, VT) ||
8059 isUNPCKHMask(M, VT) ||
8060 isUNPCKL_v_undef_Mask(M, VT) ||
8061 isUNPCKH_v_undef_Mask(M, VT));
8065 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
8067 unsigned NumElts = VT.getVectorNumElements();
8068 // FIXME: This collection of masks seems suspect.
8071 if (NumElts == 4 && VT.getSizeInBits() == 128) {
8072 return (isMOVLMask(Mask, VT) ||
8073 isCommutedMOVLMask(Mask, VT, true) ||
8074 isSHUFPMask(Mask, VT) ||
8075 isCommutedSHUFPMask(Mask, VT));
8080 //===----------------------------------------------------------------------===//
8081 // X86 Scheduler Hooks
8082 //===----------------------------------------------------------------------===//
8084 // private utility function
8086 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
8087 MachineBasicBlock *MBB,
8094 TargetRegisterClass *RC,
8095 bool invSrc) const {
8096 // For the atomic bitwise operator, we generate
8099 // ld t1 = [bitinstr.addr]
8100 // op t2 = t1, [bitinstr.val]
8102 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8104 // fallthrough -->nextMBB
8105 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8106 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8107 MachineFunction::iterator MBBIter = MBB;
8110 /// First build the CFG
8111 MachineFunction *F = MBB->getParent();
8112 MachineBasicBlock *thisMBB = MBB;
8113 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8114 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8115 F->insert(MBBIter, newMBB);
8116 F->insert(MBBIter, nextMBB);
8118 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8119 nextMBB->splice(nextMBB->begin(), thisMBB,
8120 llvm::next(MachineBasicBlock::iterator(bInstr)),
8122 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8124 // Update thisMBB to fall through to newMBB
8125 thisMBB->addSuccessor(newMBB);
8127 // newMBB jumps to itself and fall through to nextMBB
8128 newMBB->addSuccessor(nextMBB);
8129 newMBB->addSuccessor(newMBB);
8131 // Insert instructions into newMBB based on incoming instruction
8132 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8133 "unexpected number of operands");
8134 DebugLoc dl = bInstr->getDebugLoc();
8135 MachineOperand& destOper = bInstr->getOperand(0);
8136 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8137 int numArgs = bInstr->getNumOperands() - 1;
8138 for (int i=0; i < numArgs; ++i)
8139 argOpers[i] = &bInstr->getOperand(i+1);
8141 // x86 address has 4 operands: base, index, scale, and displacement
8142 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8143 int valArgIndx = lastAddrIndx + 1;
8145 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8146 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
8147 for (int i=0; i <= lastAddrIndx; ++i)
8148 (*MIB).addOperand(*argOpers[i]);
8150 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
8152 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
8157 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8158 assert((argOpers[valArgIndx]->isReg() ||
8159 argOpers[valArgIndx]->isImm()) &&
8161 if (argOpers[valArgIndx]->isReg())
8162 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
8164 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
8166 (*MIB).addOperand(*argOpers[valArgIndx]);
8168 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
8171 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
8172 for (int i=0; i <= lastAddrIndx; ++i)
8173 (*MIB).addOperand(*argOpers[i]);
8175 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8176 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8177 bInstr->memoperands_end());
8179 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
8183 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8185 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8189 // private utility function: 64 bit atomics on 32 bit host.
8191 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8192 MachineBasicBlock *MBB,
8197 bool invSrc) const {
8198 // For the atomic bitwise operator, we generate
8199 // thisMBB (instructions are in pairs, except cmpxchg8b)
8200 // ld t1,t2 = [bitinstr.addr]
8202 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8203 // op t5, t6 <- out1, out2, [bitinstr.val]
8204 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8205 // mov ECX, EBX <- t5, t6
8206 // mov EAX, EDX <- t1, t2
8207 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8208 // mov t3, t4 <- EAX, EDX
8210 // result in out1, out2
8211 // fallthrough -->nextMBB
8213 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8214 const unsigned LoadOpc = X86::MOV32rm;
8215 const unsigned NotOpc = X86::NOT32r;
8216 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8217 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8218 MachineFunction::iterator MBBIter = MBB;
8221 /// First build the CFG
8222 MachineFunction *F = MBB->getParent();
8223 MachineBasicBlock *thisMBB = MBB;
8224 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8225 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8226 F->insert(MBBIter, newMBB);
8227 F->insert(MBBIter, nextMBB);
8229 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8230 nextMBB->splice(nextMBB->begin(), thisMBB,
8231 llvm::next(MachineBasicBlock::iterator(bInstr)),
8233 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8235 // Update thisMBB to fall through to newMBB
8236 thisMBB->addSuccessor(newMBB);
8238 // newMBB jumps to itself and fall through to nextMBB
8239 newMBB->addSuccessor(nextMBB);
8240 newMBB->addSuccessor(newMBB);
8242 DebugLoc dl = bInstr->getDebugLoc();
8243 // Insert instructions into newMBB based on incoming instruction
8244 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8245 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
8246 "unexpected number of operands");
8247 MachineOperand& dest1Oper = bInstr->getOperand(0);
8248 MachineOperand& dest2Oper = bInstr->getOperand(1);
8249 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8250 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
8251 argOpers[i] = &bInstr->getOperand(i+2);
8253 // We use some of the operands multiple times, so conservatively just
8254 // clear any kill flags that might be present.
8255 if (argOpers[i]->isReg() && argOpers[i]->isUse())
8256 argOpers[i]->setIsKill(false);
8259 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8260 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8262 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8263 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8264 for (int i=0; i <= lastAddrIndx; ++i)
8265 (*MIB).addOperand(*argOpers[i]);
8266 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8267 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8268 // add 4 to displacement.
8269 for (int i=0; i <= lastAddrIndx-2; ++i)
8270 (*MIB).addOperand(*argOpers[i]);
8271 MachineOperand newOp3 = *(argOpers[3]);
8273 newOp3.setImm(newOp3.getImm()+4);
8275 newOp3.setOffset(newOp3.getOffset()+4);
8276 (*MIB).addOperand(newOp3);
8277 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8279 // t3/4 are defined later, at the bottom of the loop
8280 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8281 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8282 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8283 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8284 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8285 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8287 // The subsequent operations should be using the destination registers of
8288 //the PHI instructions.
8290 t1 = F->getRegInfo().createVirtualRegister(RC);
8291 t2 = F->getRegInfo().createVirtualRegister(RC);
8292 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8293 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8295 t1 = dest1Oper.getReg();
8296 t2 = dest2Oper.getReg();
8299 int valArgIndx = lastAddrIndx + 1;
8300 assert((argOpers[valArgIndx]->isReg() ||
8301 argOpers[valArgIndx]->isImm()) &&
8303 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8304 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8305 if (argOpers[valArgIndx]->isReg())
8306 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8308 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8309 if (regOpcL != X86::MOV32rr)
8311 (*MIB).addOperand(*argOpers[valArgIndx]);
8312 assert(argOpers[valArgIndx + 1]->isReg() ==
8313 argOpers[valArgIndx]->isReg());
8314 assert(argOpers[valArgIndx + 1]->isImm() ==
8315 argOpers[valArgIndx]->isImm());
8316 if (argOpers[valArgIndx + 1]->isReg())
8317 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8319 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8320 if (regOpcH != X86::MOV32rr)
8322 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8324 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
8326 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
8329 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
8331 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
8334 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8335 for (int i=0; i <= lastAddrIndx; ++i)
8336 (*MIB).addOperand(*argOpers[i]);
8338 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8339 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8340 bInstr->memoperands_end());
8342 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
8343 MIB.addReg(X86::EAX);
8344 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
8345 MIB.addReg(X86::EDX);
8348 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8350 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8354 // private utility function
8356 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8357 MachineBasicBlock *MBB,
8358 unsigned cmovOpc) const {
8359 // For the atomic min/max operator, we generate
8362 // ld t1 = [min/max.addr]
8363 // mov t2 = [min/max.val]
8365 // cmov[cond] t2 = t1
8367 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8369 // fallthrough -->nextMBB
8371 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8372 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8373 MachineFunction::iterator MBBIter = MBB;
8376 /// First build the CFG
8377 MachineFunction *F = MBB->getParent();
8378 MachineBasicBlock *thisMBB = MBB;
8379 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8380 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8381 F->insert(MBBIter, newMBB);
8382 F->insert(MBBIter, nextMBB);
8384 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8385 nextMBB->splice(nextMBB->begin(), thisMBB,
8386 llvm::next(MachineBasicBlock::iterator(mInstr)),
8388 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8390 // Update thisMBB to fall through to newMBB
8391 thisMBB->addSuccessor(newMBB);
8393 // newMBB jumps to newMBB and fall through to nextMBB
8394 newMBB->addSuccessor(nextMBB);
8395 newMBB->addSuccessor(newMBB);
8397 DebugLoc dl = mInstr->getDebugLoc();
8398 // Insert instructions into newMBB based on incoming instruction
8399 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8400 "unexpected number of operands");
8401 MachineOperand& destOper = mInstr->getOperand(0);
8402 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8403 int numArgs = mInstr->getNumOperands() - 1;
8404 for (int i=0; i < numArgs; ++i)
8405 argOpers[i] = &mInstr->getOperand(i+1);
8407 // x86 address has 4 operands: base, index, scale, and displacement
8408 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8409 int valArgIndx = lastAddrIndx + 1;
8411 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8412 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8413 for (int i=0; i <= lastAddrIndx; ++i)
8414 (*MIB).addOperand(*argOpers[i]);
8416 // We only support register and immediate values
8417 assert((argOpers[valArgIndx]->isReg() ||
8418 argOpers[valArgIndx]->isImm()) &&
8421 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8422 if (argOpers[valArgIndx]->isReg())
8423 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
8425 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8426 (*MIB).addOperand(*argOpers[valArgIndx]);
8428 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
8431 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8436 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8437 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8441 // Cmp and exchange if none has modified the memory location
8442 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8443 for (int i=0; i <= lastAddrIndx; ++i)
8444 (*MIB).addOperand(*argOpers[i]);
8446 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8447 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8448 mInstr->memoperands_end());
8450 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
8451 MIB.addReg(X86::EAX);
8454 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8456 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
8460 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8461 // all of this code can be replaced with that in the .td file.
8463 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8464 unsigned numArgs, bool memArg) const {
8466 DebugLoc dl = MI->getDebugLoc();
8467 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8471 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8473 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8475 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8477 for (unsigned i = 0; i < numArgs; ++i) {
8478 MachineOperand &Op = MI->getOperand(i+1);
8480 if (!(Op.isReg() && Op.isImplicit()))
8484 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8487 MI->eraseFromParent();
8493 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8495 MachineBasicBlock *MBB) const {
8496 // Emit code to save XMM registers to the stack. The ABI says that the
8497 // number of registers to save is given in %al, so it's theoretically
8498 // possible to do an indirect jump trick to avoid saving all of them,
8499 // however this code takes a simpler approach and just executes all
8500 // of the stores if %al is non-zero. It's less code, and it's probably
8501 // easier on the hardware branch predictor, and stores aren't all that
8502 // expensive anyway.
8504 // Create the new basic blocks. One block contains all the XMM stores,
8505 // and one block is the final destination regardless of whether any
8506 // stores were performed.
8507 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8508 MachineFunction *F = MBB->getParent();
8509 MachineFunction::iterator MBBIter = MBB;
8511 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8512 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8513 F->insert(MBBIter, XMMSaveMBB);
8514 F->insert(MBBIter, EndMBB);
8516 // Transfer the remainder of MBB and its successor edges to EndMBB.
8517 EndMBB->splice(EndMBB->begin(), MBB,
8518 llvm::next(MachineBasicBlock::iterator(MI)),
8520 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
8522 // The original block will now fall through to the XMM save block.
8523 MBB->addSuccessor(XMMSaveMBB);
8524 // The XMMSaveMBB will fall through to the end block.
8525 XMMSaveMBB->addSuccessor(EndMBB);
8527 // Now add the instructions.
8528 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8529 DebugLoc DL = MI->getDebugLoc();
8531 unsigned CountReg = MI->getOperand(0).getReg();
8532 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8533 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8535 if (!Subtarget->isTargetWin64()) {
8536 // If %al is 0, branch around the XMM save block.
8537 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8538 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8539 MBB->addSuccessor(EndMBB);
8542 // In the XMM save block, save all the XMM argument registers.
8543 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8544 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8545 MachineMemOperand *MMO =
8546 F->getMachineMemOperand(
8547 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8548 MachineMemOperand::MOStore, Offset,
8549 /*Size=*/16, /*Align=*/16);
8550 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8551 .addFrameIndex(RegSaveFrameIndex)
8552 .addImm(/*Scale=*/1)
8553 .addReg(/*IndexReg=*/0)
8554 .addImm(/*Disp=*/Offset)
8555 .addReg(/*Segment=*/0)
8556 .addReg(MI->getOperand(i).getReg())
8557 .addMemOperand(MMO);
8560 MI->eraseFromParent(); // The pseudo instruction is gone now.
8566 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8567 MachineBasicBlock *BB) const {
8568 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8569 DebugLoc DL = MI->getDebugLoc();
8571 // To "insert" a SELECT_CC instruction, we actually have to insert the
8572 // diamond control-flow pattern. The incoming instruction knows the
8573 // destination vreg to set, the condition code register to branch on, the
8574 // true/false values to select between, and a branch opcode to use.
8575 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8576 MachineFunction::iterator It = BB;
8582 // cmpTY ccX, r1, r2
8584 // fallthrough --> copy0MBB
8585 MachineBasicBlock *thisMBB = BB;
8586 MachineFunction *F = BB->getParent();
8587 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8588 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8589 F->insert(It, copy0MBB);
8590 F->insert(It, sinkMBB);
8592 // If the EFLAGS register isn't dead in the terminator, then claim that it's
8593 // live into the sink and copy blocks.
8594 const MachineFunction *MF = BB->getParent();
8595 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
8596 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
8598 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
8599 const MachineOperand &MO = MI->getOperand(I);
8600 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
8601 unsigned Reg = MO.getReg();
8602 if (Reg != X86::EFLAGS) continue;
8603 copy0MBB->addLiveIn(Reg);
8604 sinkMBB->addLiveIn(Reg);
8607 // Transfer the remainder of BB and its successor edges to sinkMBB.
8608 sinkMBB->splice(sinkMBB->begin(), BB,
8609 llvm::next(MachineBasicBlock::iterator(MI)),
8611 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8613 // Add the true and fallthrough blocks as its successors.
8614 BB->addSuccessor(copy0MBB);
8615 BB->addSuccessor(sinkMBB);
8617 // Create the conditional branch instruction.
8619 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8620 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8623 // %FalseValue = ...
8624 // # fallthrough to sinkMBB
8625 copy0MBB->addSuccessor(sinkMBB);
8628 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8630 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8631 TII->get(X86::PHI), MI->getOperand(0).getReg())
8632 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8633 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8635 MI->eraseFromParent(); // The pseudo instruction is gone now.
8640 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8641 MachineBasicBlock *BB) const {
8642 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8643 DebugLoc DL = MI->getDebugLoc();
8645 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8646 // non-trivial part is impdef of ESP.
8647 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8650 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
8651 .addExternalSymbol("_alloca")
8652 .addReg(X86::EAX, RegState::Implicit)
8653 .addReg(X86::ESP, RegState::Implicit)
8654 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8655 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8657 MI->eraseFromParent(); // The pseudo instruction is gone now.
8662 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
8663 MachineBasicBlock *BB) const {
8664 // This is pretty easy. We're taking the value that we received from
8665 // our load from the relocation, sticking it in either RDI (x86-64)
8666 // or EAX and doing an indirect call. The return value will then
8667 // be in the normal return register.
8668 const X86InstrInfo *TII
8669 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
8670 DebugLoc DL = MI->getDebugLoc();
8671 MachineFunction *F = BB->getParent();
8673 assert(MI->getOperand(3).isGlobal() && "This should be a global");
8675 if (Subtarget->is64Bit()) {
8676 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8677 TII->get(X86::MOV64rm), X86::RDI)
8679 .addImm(0).addReg(0)
8680 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8681 MI->getOperand(3).getTargetFlags())
8683 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
8684 addDirectMem(MIB, X86::RDI);
8685 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
8686 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8687 TII->get(X86::MOV32rm), X86::EAX)
8689 .addImm(0).addReg(0)
8690 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8691 MI->getOperand(3).getTargetFlags())
8693 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8694 addDirectMem(MIB, X86::EAX);
8696 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8697 TII->get(X86::MOV32rm), X86::EAX)
8698 .addReg(TII->getGlobalBaseReg(F))
8699 .addImm(0).addReg(0)
8700 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8701 MI->getOperand(3).getTargetFlags())
8703 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8704 addDirectMem(MIB, X86::EAX);
8707 MI->eraseFromParent(); // The pseudo instruction is gone now.
8712 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8713 MachineBasicBlock *BB) const {
8714 switch (MI->getOpcode()) {
8715 default: assert(false && "Unexpected instr type to insert");
8716 case X86::MINGW_ALLOCA:
8717 return EmitLoweredMingwAlloca(MI, BB);
8718 case X86::TLSCall_32:
8719 case X86::TLSCall_64:
8720 return EmitLoweredTLSCall(MI, BB);
8722 case X86::CMOV_V1I64:
8723 case X86::CMOV_FR32:
8724 case X86::CMOV_FR64:
8725 case X86::CMOV_V4F32:
8726 case X86::CMOV_V2F64:
8727 case X86::CMOV_V2I64:
8728 case X86::CMOV_GR16:
8729 case X86::CMOV_GR32:
8730 case X86::CMOV_RFP32:
8731 case X86::CMOV_RFP64:
8732 case X86::CMOV_RFP80:
8733 return EmitLoweredSelect(MI, BB);
8735 case X86::FP32_TO_INT16_IN_MEM:
8736 case X86::FP32_TO_INT32_IN_MEM:
8737 case X86::FP32_TO_INT64_IN_MEM:
8738 case X86::FP64_TO_INT16_IN_MEM:
8739 case X86::FP64_TO_INT32_IN_MEM:
8740 case X86::FP64_TO_INT64_IN_MEM:
8741 case X86::FP80_TO_INT16_IN_MEM:
8742 case X86::FP80_TO_INT32_IN_MEM:
8743 case X86::FP80_TO_INT64_IN_MEM: {
8744 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8745 DebugLoc DL = MI->getDebugLoc();
8747 // Change the floating point control register to use "round towards zero"
8748 // mode when truncating to an integer value.
8749 MachineFunction *F = BB->getParent();
8750 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8751 addFrameReference(BuildMI(*BB, MI, DL,
8752 TII->get(X86::FNSTCW16m)), CWFrameIdx);
8754 // Load the old value of the high byte of the control word...
8756 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8757 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
8760 // Set the high part to be round to zero...
8761 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8764 // Reload the modified control word now...
8765 addFrameReference(BuildMI(*BB, MI, DL,
8766 TII->get(X86::FLDCW16m)), CWFrameIdx);
8768 // Restore the memory image of control word to original value
8769 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8772 // Get the X86 opcode to use.
8774 switch (MI->getOpcode()) {
8775 default: llvm_unreachable("illegal opcode!");
8776 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8777 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8778 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8779 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8780 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8781 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8782 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8783 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8784 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8788 MachineOperand &Op = MI->getOperand(0);
8790 AM.BaseType = X86AddressMode::RegBase;
8791 AM.Base.Reg = Op.getReg();
8793 AM.BaseType = X86AddressMode::FrameIndexBase;
8794 AM.Base.FrameIndex = Op.getIndex();
8796 Op = MI->getOperand(1);
8798 AM.Scale = Op.getImm();
8799 Op = MI->getOperand(2);
8801 AM.IndexReg = Op.getImm();
8802 Op = MI->getOperand(3);
8803 if (Op.isGlobal()) {
8804 AM.GV = Op.getGlobal();
8806 AM.Disp = Op.getImm();
8808 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
8809 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
8811 // Reload the original control word now.
8812 addFrameReference(BuildMI(*BB, MI, DL,
8813 TII->get(X86::FLDCW16m)), CWFrameIdx);
8815 MI->eraseFromParent(); // The pseudo instruction is gone now.
8818 // String/text processing lowering.
8819 case X86::PCMPISTRM128REG:
8820 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8821 case X86::PCMPISTRM128MEM:
8822 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8823 case X86::PCMPESTRM128REG:
8824 return EmitPCMP(MI, BB, 5, false /* in mem */);
8825 case X86::PCMPESTRM128MEM:
8826 return EmitPCMP(MI, BB, 5, true /* in mem */);
8829 case X86::ATOMAND32:
8830 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8831 X86::AND32ri, X86::MOV32rm,
8833 X86::NOT32r, X86::EAX,
8834 X86::GR32RegisterClass);
8836 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8837 X86::OR32ri, X86::MOV32rm,
8839 X86::NOT32r, X86::EAX,
8840 X86::GR32RegisterClass);
8841 case X86::ATOMXOR32:
8842 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8843 X86::XOR32ri, X86::MOV32rm,
8845 X86::NOT32r, X86::EAX,
8846 X86::GR32RegisterClass);
8847 case X86::ATOMNAND32:
8848 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8849 X86::AND32ri, X86::MOV32rm,
8851 X86::NOT32r, X86::EAX,
8852 X86::GR32RegisterClass, true);
8853 case X86::ATOMMIN32:
8854 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8855 case X86::ATOMMAX32:
8856 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8857 case X86::ATOMUMIN32:
8858 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8859 case X86::ATOMUMAX32:
8860 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8862 case X86::ATOMAND16:
8863 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8864 X86::AND16ri, X86::MOV16rm,
8866 X86::NOT16r, X86::AX,
8867 X86::GR16RegisterClass);
8869 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8870 X86::OR16ri, X86::MOV16rm,
8872 X86::NOT16r, X86::AX,
8873 X86::GR16RegisterClass);
8874 case X86::ATOMXOR16:
8875 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8876 X86::XOR16ri, X86::MOV16rm,
8878 X86::NOT16r, X86::AX,
8879 X86::GR16RegisterClass);
8880 case X86::ATOMNAND16:
8881 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8882 X86::AND16ri, X86::MOV16rm,
8884 X86::NOT16r, X86::AX,
8885 X86::GR16RegisterClass, true);
8886 case X86::ATOMMIN16:
8887 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8888 case X86::ATOMMAX16:
8889 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8890 case X86::ATOMUMIN16:
8891 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8892 case X86::ATOMUMAX16:
8893 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8896 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8897 X86::AND8ri, X86::MOV8rm,
8899 X86::NOT8r, X86::AL,
8900 X86::GR8RegisterClass);
8902 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8903 X86::OR8ri, X86::MOV8rm,
8905 X86::NOT8r, X86::AL,
8906 X86::GR8RegisterClass);
8908 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8909 X86::XOR8ri, X86::MOV8rm,
8911 X86::NOT8r, X86::AL,
8912 X86::GR8RegisterClass);
8913 case X86::ATOMNAND8:
8914 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8915 X86::AND8ri, X86::MOV8rm,
8917 X86::NOT8r, X86::AL,
8918 X86::GR8RegisterClass, true);
8919 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8920 // This group is for 64-bit host.
8921 case X86::ATOMAND64:
8922 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8923 X86::AND64ri32, X86::MOV64rm,
8925 X86::NOT64r, X86::RAX,
8926 X86::GR64RegisterClass);
8928 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8929 X86::OR64ri32, X86::MOV64rm,
8931 X86::NOT64r, X86::RAX,
8932 X86::GR64RegisterClass);
8933 case X86::ATOMXOR64:
8934 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8935 X86::XOR64ri32, X86::MOV64rm,
8937 X86::NOT64r, X86::RAX,
8938 X86::GR64RegisterClass);
8939 case X86::ATOMNAND64:
8940 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8941 X86::AND64ri32, X86::MOV64rm,
8943 X86::NOT64r, X86::RAX,
8944 X86::GR64RegisterClass, true);
8945 case X86::ATOMMIN64:
8946 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8947 case X86::ATOMMAX64:
8948 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8949 case X86::ATOMUMIN64:
8950 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8951 case X86::ATOMUMAX64:
8952 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8954 // This group does 64-bit operations on a 32-bit host.
8955 case X86::ATOMAND6432:
8956 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8957 X86::AND32rr, X86::AND32rr,
8958 X86::AND32ri, X86::AND32ri,
8960 case X86::ATOMOR6432:
8961 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8962 X86::OR32rr, X86::OR32rr,
8963 X86::OR32ri, X86::OR32ri,
8965 case X86::ATOMXOR6432:
8966 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8967 X86::XOR32rr, X86::XOR32rr,
8968 X86::XOR32ri, X86::XOR32ri,
8970 case X86::ATOMNAND6432:
8971 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8972 X86::AND32rr, X86::AND32rr,
8973 X86::AND32ri, X86::AND32ri,
8975 case X86::ATOMADD6432:
8976 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8977 X86::ADD32rr, X86::ADC32rr,
8978 X86::ADD32ri, X86::ADC32ri,
8980 case X86::ATOMSUB6432:
8981 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8982 X86::SUB32rr, X86::SBB32rr,
8983 X86::SUB32ri, X86::SBB32ri,
8985 case X86::ATOMSWAP6432:
8986 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8987 X86::MOV32rr, X86::MOV32rr,
8988 X86::MOV32ri, X86::MOV32ri,
8990 case X86::VASTART_SAVE_XMM_REGS:
8991 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8995 //===----------------------------------------------------------------------===//
8996 // X86 Optimization Hooks
8997 //===----------------------------------------------------------------------===//
8999 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9003 const SelectionDAG &DAG,
9004 unsigned Depth) const {
9005 unsigned Opc = Op.getOpcode();
9006 assert((Opc >= ISD::BUILTIN_OP_END ||
9007 Opc == ISD::INTRINSIC_WO_CHAIN ||
9008 Opc == ISD::INTRINSIC_W_CHAIN ||
9009 Opc == ISD::INTRINSIC_VOID) &&
9010 "Should use MaskedValueIsZero if you don't know whether Op"
9011 " is a target node!");
9013 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
9025 // These nodes' second result is a boolean.
9026 if (Op.getResNo() == 0)
9030 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
9031 Mask.getBitWidth() - 1);
9036 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
9037 /// node is a GlobalAddress + offset.
9038 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
9039 const GlobalValue* &GA,
9040 int64_t &Offset) const {
9041 if (N->getOpcode() == X86ISD::Wrapper) {
9042 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
9043 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
9044 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
9048 return TargetLowering::isGAPlusOffset(N, GA, Offset);
9051 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
9052 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
9053 /// if the load addresses are consecutive, non-overlapping, and in the right
9055 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
9056 const TargetLowering &TLI) {
9057 DebugLoc dl = N->getDebugLoc();
9058 EVT VT = N->getValueType(0);
9059 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9061 if (VT.getSizeInBits() != 128)
9064 SmallVector<SDValue, 16> Elts;
9065 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
9066 Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
9068 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
9071 /// PerformShuffleCombine - Detect vector gather/scatter index generation
9072 /// and convert it from being a bunch of shuffles and extracts to a simple
9073 /// store and scalar loads to extract the elements.
9074 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
9075 const TargetLowering &TLI) {
9076 SDValue InputVector = N->getOperand(0);
9078 // Only operate on vectors of 4 elements, where the alternative shuffling
9079 // gets to be more expensive.
9080 if (InputVector.getValueType() != MVT::v4i32)
9083 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
9084 // single use which is a sign-extend or zero-extend, and all elements are
9086 SmallVector<SDNode *, 4> Uses;
9087 unsigned ExtractedElements = 0;
9088 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
9089 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
9090 if (UI.getUse().getResNo() != InputVector.getResNo())
9093 SDNode *Extract = *UI;
9094 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9097 if (Extract->getValueType(0) != MVT::i32)
9099 if (!Extract->hasOneUse())
9101 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
9102 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
9104 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
9107 // Record which element was extracted.
9108 ExtractedElements |=
9109 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
9111 Uses.push_back(Extract);
9114 // If not all the elements were used, this may not be worthwhile.
9115 if (ExtractedElements != 15)
9118 // Ok, we've now decided to do the transformation.
9119 DebugLoc dl = InputVector.getDebugLoc();
9121 // Store the value to a temporary stack slot.
9122 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
9123 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL,
9124 0, false, false, 0);
9126 // Replace each use (extract) with a load of the appropriate element.
9127 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
9128 UE = Uses.end(); UI != UE; ++UI) {
9129 SDNode *Extract = *UI;
9131 // Compute the element's address.
9132 SDValue Idx = Extract->getOperand(1);
9134 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
9135 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
9136 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
9138 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
9139 OffsetVal, StackPtr);
9142 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
9143 ScalarAddr, NULL, 0, false, false, 0);
9145 // Replace the exact with the load.
9146 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
9149 // The replacement was made in place; don't return anything.
9153 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
9154 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
9155 const X86Subtarget *Subtarget) {
9156 DebugLoc DL = N->getDebugLoc();
9157 SDValue Cond = N->getOperand(0);
9158 // Get the LHS/RHS of the select.
9159 SDValue LHS = N->getOperand(1);
9160 SDValue RHS = N->getOperand(2);
9162 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
9163 // instructions match the semantics of the common C idiom x<y?x:y but not
9164 // x<=y?x:y, because of how they handle negative zero (which can be
9165 // ignored in unsafe-math mode).
9166 if (Subtarget->hasSSE2() &&
9167 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
9168 Cond.getOpcode() == ISD::SETCC) {
9169 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
9171 unsigned Opcode = 0;
9172 // Check for x CC y ? x : y.
9173 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
9174 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
9178 // Converting this to a min would handle NaNs incorrectly, and swapping
9179 // the operands would cause it to handle comparisons between positive
9180 // and negative zero incorrectly.
9181 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9182 if (!UnsafeFPMath &&
9183 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9185 std::swap(LHS, RHS);
9187 Opcode = X86ISD::FMIN;
9190 // Converting this to a min would handle comparisons between positive
9191 // and negative zero incorrectly.
9192 if (!UnsafeFPMath &&
9193 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
9195 Opcode = X86ISD::FMIN;
9198 // Converting this to a min would handle both negative zeros and NaNs
9199 // incorrectly, but we can swap the operands to fix both.
9200 std::swap(LHS, RHS);
9204 Opcode = X86ISD::FMIN;
9208 // Converting this to a max would handle comparisons between positive
9209 // and negative zero incorrectly.
9210 if (!UnsafeFPMath &&
9211 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
9213 Opcode = X86ISD::FMAX;
9216 // Converting this to a max would handle NaNs incorrectly, and swapping
9217 // the operands would cause it to handle comparisons between positive
9218 // and negative zero incorrectly.
9219 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9220 if (!UnsafeFPMath &&
9221 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9223 std::swap(LHS, RHS);
9225 Opcode = X86ISD::FMAX;
9228 // Converting this to a max would handle both negative zeros and NaNs
9229 // incorrectly, but we can swap the operands to fix both.
9230 std::swap(LHS, RHS);
9234 Opcode = X86ISD::FMAX;
9237 // Check for x CC y ? y : x -- a min/max with reversed arms.
9238 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
9239 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
9243 // Converting this to a min would handle comparisons between positive
9244 // and negative zero incorrectly, and swapping the operands would
9245 // cause it to handle NaNs incorrectly.
9246 if (!UnsafeFPMath &&
9247 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
9248 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9250 std::swap(LHS, RHS);
9252 Opcode = X86ISD::FMIN;
9255 // Converting this to a min would handle NaNs incorrectly.
9256 if (!UnsafeFPMath &&
9257 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9259 Opcode = X86ISD::FMIN;
9262 // Converting this to a min would handle both negative zeros and NaNs
9263 // incorrectly, but we can swap the operands to fix both.
9264 std::swap(LHS, RHS);
9268 Opcode = X86ISD::FMIN;
9272 // Converting this to a max would handle NaNs incorrectly.
9273 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9275 Opcode = X86ISD::FMAX;
9278 // Converting this to a max would handle comparisons between positive
9279 // and negative zero incorrectly, and swapping the operands would
9280 // cause it to handle NaNs incorrectly.
9281 if (!UnsafeFPMath &&
9282 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
9283 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9285 std::swap(LHS, RHS);
9287 Opcode = X86ISD::FMAX;
9290 // Converting this to a max would handle both negative zeros and NaNs
9291 // incorrectly, but we can swap the operands to fix both.
9292 std::swap(LHS, RHS);
9296 Opcode = X86ISD::FMAX;
9302 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9305 // If this is a select between two integer constants, try to do some
9307 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9308 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9309 // Don't do this for crazy integer types.
9310 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9311 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9312 // so that TrueC (the true value) is larger than FalseC.
9313 bool NeedsCondInvert = false;
9315 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9316 // Efficiently invertible.
9317 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9318 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9319 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9320 NeedsCondInvert = true;
9321 std::swap(TrueC, FalseC);
9324 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9325 if (FalseC->getAPIntValue() == 0 &&
9326 TrueC->getAPIntValue().isPowerOf2()) {
9327 if (NeedsCondInvert) // Invert the condition if needed.
9328 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9329 DAG.getConstant(1, Cond.getValueType()));
9331 // Zero extend the condition if needed.
9332 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9334 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9335 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9336 DAG.getConstant(ShAmt, MVT::i8));
9339 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9340 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9341 if (NeedsCondInvert) // Invert the condition if needed.
9342 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9343 DAG.getConstant(1, Cond.getValueType()));
9345 // Zero extend the condition if needed.
9346 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9347 FalseC->getValueType(0), Cond);
9348 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9349 SDValue(FalseC, 0));
9352 // Optimize cases that will turn into an LEA instruction. This requires
9353 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9354 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9355 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9356 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9358 bool isFastMultiplier = false;
9360 switch ((unsigned char)Diff) {
9362 case 1: // result = add base, cond
9363 case 2: // result = lea base( , cond*2)
9364 case 3: // result = lea base(cond, cond*2)
9365 case 4: // result = lea base( , cond*4)
9366 case 5: // result = lea base(cond, cond*4)
9367 case 8: // result = lea base( , cond*8)
9368 case 9: // result = lea base(cond, cond*8)
9369 isFastMultiplier = true;
9374 if (isFastMultiplier) {
9375 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9376 if (NeedsCondInvert) // Invert the condition if needed.
9377 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9378 DAG.getConstant(1, Cond.getValueType()));
9380 // Zero extend the condition if needed.
9381 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9383 // Scale the condition by the difference.
9385 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9386 DAG.getConstant(Diff, Cond.getValueType()));
9388 // Add the base if non-zero.
9389 if (FalseC->getAPIntValue() != 0)
9390 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9391 SDValue(FalseC, 0));
9401 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9402 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9403 TargetLowering::DAGCombinerInfo &DCI) {
9404 DebugLoc DL = N->getDebugLoc();
9406 // If the flag operand isn't dead, don't touch this CMOV.
9407 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9410 // If this is a select between two integer constants, try to do some
9411 // optimizations. Note that the operands are ordered the opposite of SELECT
9413 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9414 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9415 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9416 // larger than FalseC (the false value).
9417 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9419 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9420 CC = X86::GetOppositeBranchCondition(CC);
9421 std::swap(TrueC, FalseC);
9424 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9425 // This is efficient for any integer data type (including i8/i16) and
9427 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9428 SDValue Cond = N->getOperand(3);
9429 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9430 DAG.getConstant(CC, MVT::i8), Cond);
9432 // Zero extend the condition if needed.
9433 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9435 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9436 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9437 DAG.getConstant(ShAmt, MVT::i8));
9438 if (N->getNumValues() == 2) // Dead flag value?
9439 return DCI.CombineTo(N, Cond, SDValue());
9443 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9444 // for any integer data type, including i8/i16.
9445 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9446 SDValue Cond = N->getOperand(3);
9447 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9448 DAG.getConstant(CC, MVT::i8), Cond);
9450 // Zero extend the condition if needed.
9451 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9452 FalseC->getValueType(0), Cond);
9453 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9454 SDValue(FalseC, 0));
9456 if (N->getNumValues() == 2) // Dead flag value?
9457 return DCI.CombineTo(N, Cond, SDValue());
9461 // Optimize cases that will turn into an LEA instruction. This requires
9462 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9463 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9464 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9465 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9467 bool isFastMultiplier = false;
9469 switch ((unsigned char)Diff) {
9471 case 1: // result = add base, cond
9472 case 2: // result = lea base( , cond*2)
9473 case 3: // result = lea base(cond, cond*2)
9474 case 4: // result = lea base( , cond*4)
9475 case 5: // result = lea base(cond, cond*4)
9476 case 8: // result = lea base( , cond*8)
9477 case 9: // result = lea base(cond, cond*8)
9478 isFastMultiplier = true;
9483 if (isFastMultiplier) {
9484 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9485 SDValue Cond = N->getOperand(3);
9486 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9487 DAG.getConstant(CC, MVT::i8), Cond);
9488 // Zero extend the condition if needed.
9489 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9491 // Scale the condition by the difference.
9493 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9494 DAG.getConstant(Diff, Cond.getValueType()));
9496 // Add the base if non-zero.
9497 if (FalseC->getAPIntValue() != 0)
9498 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9499 SDValue(FalseC, 0));
9500 if (N->getNumValues() == 2) // Dead flag value?
9501 return DCI.CombineTo(N, Cond, SDValue());
9511 /// PerformMulCombine - Optimize a single multiply with constant into two
9512 /// in order to implement it with two cheaper instructions, e.g.
9513 /// LEA + SHL, LEA + LEA.
9514 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9515 TargetLowering::DAGCombinerInfo &DCI) {
9516 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9519 EVT VT = N->getValueType(0);
9523 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9526 uint64_t MulAmt = C->getZExtValue();
9527 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9530 uint64_t MulAmt1 = 0;
9531 uint64_t MulAmt2 = 0;
9532 if ((MulAmt % 9) == 0) {
9534 MulAmt2 = MulAmt / 9;
9535 } else if ((MulAmt % 5) == 0) {
9537 MulAmt2 = MulAmt / 5;
9538 } else if ((MulAmt % 3) == 0) {
9540 MulAmt2 = MulAmt / 3;
9543 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9544 DebugLoc DL = N->getDebugLoc();
9546 if (isPowerOf2_64(MulAmt2) &&
9547 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9548 // If second multiplifer is pow2, issue it first. We want the multiply by
9549 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9551 std::swap(MulAmt1, MulAmt2);
9554 if (isPowerOf2_64(MulAmt1))
9555 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9556 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9558 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9559 DAG.getConstant(MulAmt1, VT));
9561 if (isPowerOf2_64(MulAmt2))
9562 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9563 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9565 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9566 DAG.getConstant(MulAmt2, VT));
9568 // Do not add new nodes to DAG combiner worklist.
9569 DCI.CombineTo(N, NewMul, false);
9574 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9575 SDValue N0 = N->getOperand(0);
9576 SDValue N1 = N->getOperand(1);
9577 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9578 EVT VT = N0.getValueType();
9580 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9581 // since the result of setcc_c is all zero's or all ones.
9582 if (N1C && N0.getOpcode() == ISD::AND &&
9583 N0.getOperand(1).getOpcode() == ISD::Constant) {
9584 SDValue N00 = N0.getOperand(0);
9585 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9586 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9587 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9588 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9589 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9590 APInt ShAmt = N1C->getAPIntValue();
9591 Mask = Mask.shl(ShAmt);
9593 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9594 N00, DAG.getConstant(Mask, VT));
9601 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9603 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9604 const X86Subtarget *Subtarget) {
9605 EVT VT = N->getValueType(0);
9606 if (!VT.isVector() && VT.isInteger() &&
9607 N->getOpcode() == ISD::SHL)
9608 return PerformSHLCombine(N, DAG);
9610 // On X86 with SSE2 support, we can transform this to a vector shift if
9611 // all elements are shifted by the same amount. We can't do this in legalize
9612 // because the a constant vector is typically transformed to a constant pool
9613 // so we have no knowledge of the shift amount.
9614 if (!Subtarget->hasSSE2())
9617 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9620 SDValue ShAmtOp = N->getOperand(1);
9621 EVT EltVT = VT.getVectorElementType();
9622 DebugLoc DL = N->getDebugLoc();
9623 SDValue BaseShAmt = SDValue();
9624 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9625 unsigned NumElts = VT.getVectorNumElements();
9627 for (; i != NumElts; ++i) {
9628 SDValue Arg = ShAmtOp.getOperand(i);
9629 if (Arg.getOpcode() == ISD::UNDEF) continue;
9633 for (; i != NumElts; ++i) {
9634 SDValue Arg = ShAmtOp.getOperand(i);
9635 if (Arg.getOpcode() == ISD::UNDEF) continue;
9636 if (Arg != BaseShAmt) {
9640 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9641 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9642 SDValue InVec = ShAmtOp.getOperand(0);
9643 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9644 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9646 for (; i != NumElts; ++i) {
9647 SDValue Arg = InVec.getOperand(i);
9648 if (Arg.getOpcode() == ISD::UNDEF) continue;
9652 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9653 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9654 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9655 if (C->getZExtValue() == SplatIdx)
9656 BaseShAmt = InVec.getOperand(1);
9659 if (BaseShAmt.getNode() == 0)
9660 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9661 DAG.getIntPtrConstant(0));
9665 // The shift amount is an i32.
9666 if (EltVT.bitsGT(MVT::i32))
9667 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9668 else if (EltVT.bitsLT(MVT::i32))
9669 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9671 // The shift amount is identical so we can do a vector shift.
9672 SDValue ValOp = N->getOperand(0);
9673 switch (N->getOpcode()) {
9675 llvm_unreachable("Unknown shift opcode!");
9678 if (VT == MVT::v2i64)
9679 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9680 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9682 if (VT == MVT::v4i32)
9683 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9684 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9686 if (VT == MVT::v8i16)
9687 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9688 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9692 if (VT == MVT::v4i32)
9693 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9694 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9696 if (VT == MVT::v8i16)
9697 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9698 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9702 if (VT == MVT::v2i64)
9703 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9704 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9706 if (VT == MVT::v4i32)
9707 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9708 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9710 if (VT == MVT::v8i16)
9711 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9712 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9719 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9720 TargetLowering::DAGCombinerInfo &DCI,
9721 const X86Subtarget *Subtarget) {
9722 if (DCI.isBeforeLegalizeOps())
9725 EVT VT = N->getValueType(0);
9726 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
9729 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9730 SDValue N0 = N->getOperand(0);
9731 SDValue N1 = N->getOperand(1);
9732 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9734 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9736 if (!N0.hasOneUse() || !N1.hasOneUse())
9739 SDValue ShAmt0 = N0.getOperand(1);
9740 if (ShAmt0.getValueType() != MVT::i8)
9742 SDValue ShAmt1 = N1.getOperand(1);
9743 if (ShAmt1.getValueType() != MVT::i8)
9745 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9746 ShAmt0 = ShAmt0.getOperand(0);
9747 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9748 ShAmt1 = ShAmt1.getOperand(0);
9750 DebugLoc DL = N->getDebugLoc();
9751 unsigned Opc = X86ISD::SHLD;
9752 SDValue Op0 = N0.getOperand(0);
9753 SDValue Op1 = N1.getOperand(0);
9754 if (ShAmt0.getOpcode() == ISD::SUB) {
9756 std::swap(Op0, Op1);
9757 std::swap(ShAmt0, ShAmt1);
9760 unsigned Bits = VT.getSizeInBits();
9761 if (ShAmt1.getOpcode() == ISD::SUB) {
9762 SDValue Sum = ShAmt1.getOperand(0);
9763 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9764 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
9765 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
9766 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
9767 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
9768 return DAG.getNode(Opc, DL, VT,
9770 DAG.getNode(ISD::TRUNCATE, DL,
9773 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9774 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9776 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
9777 return DAG.getNode(Opc, DL, VT,
9778 N0.getOperand(0), N1.getOperand(0),
9779 DAG.getNode(ISD::TRUNCATE, DL,
9786 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9787 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9788 const X86Subtarget *Subtarget) {
9789 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9790 // the FP state in cases where an emms may be missing.
9791 // A preferable solution to the general problem is to figure out the right
9792 // places to insert EMMS. This qualifies as a quick hack.
9794 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9795 StoreSDNode *St = cast<StoreSDNode>(N);
9796 EVT VT = St->getValue().getValueType();
9797 if (VT.getSizeInBits() != 64)
9800 const Function *F = DAG.getMachineFunction().getFunction();
9801 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9802 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9803 && Subtarget->hasSSE2();
9804 if ((VT.isVector() ||
9805 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9806 isa<LoadSDNode>(St->getValue()) &&
9807 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9808 St->getChain().hasOneUse() && !St->isVolatile()) {
9809 SDNode* LdVal = St->getValue().getNode();
9811 int TokenFactorIndex = -1;
9812 SmallVector<SDValue, 8> Ops;
9813 SDNode* ChainVal = St->getChain().getNode();
9814 // Must be a store of a load. We currently handle two cases: the load
9815 // is a direct child, and it's under an intervening TokenFactor. It is
9816 // possible to dig deeper under nested TokenFactors.
9817 if (ChainVal == LdVal)
9818 Ld = cast<LoadSDNode>(St->getChain());
9819 else if (St->getValue().hasOneUse() &&
9820 ChainVal->getOpcode() == ISD::TokenFactor) {
9821 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9822 if (ChainVal->getOperand(i).getNode() == LdVal) {
9823 TokenFactorIndex = i;
9824 Ld = cast<LoadSDNode>(St->getValue());
9826 Ops.push_back(ChainVal->getOperand(i));
9830 if (!Ld || !ISD::isNormalLoad(Ld))
9833 // If this is not the MMX case, i.e. we are just turning i64 load/store
9834 // into f64 load/store, avoid the transformation if there are multiple
9835 // uses of the loaded value.
9836 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9839 DebugLoc LdDL = Ld->getDebugLoc();
9840 DebugLoc StDL = N->getDebugLoc();
9841 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9842 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9844 if (Subtarget->is64Bit() || F64IsLegal) {
9845 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9846 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9847 Ld->getBasePtr(), Ld->getSrcValue(),
9848 Ld->getSrcValueOffset(), Ld->isVolatile(),
9849 Ld->isNonTemporal(), Ld->getAlignment());
9850 SDValue NewChain = NewLd.getValue(1);
9851 if (TokenFactorIndex != -1) {
9852 Ops.push_back(NewChain);
9853 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9856 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9857 St->getSrcValue(), St->getSrcValueOffset(),
9858 St->isVolatile(), St->isNonTemporal(),
9859 St->getAlignment());
9862 // Otherwise, lower to two pairs of 32-bit loads / stores.
9863 SDValue LoAddr = Ld->getBasePtr();
9864 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9865 DAG.getConstant(4, MVT::i32));
9867 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9868 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9869 Ld->isVolatile(), Ld->isNonTemporal(),
9870 Ld->getAlignment());
9871 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9872 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9873 Ld->isVolatile(), Ld->isNonTemporal(),
9874 MinAlign(Ld->getAlignment(), 4));
9876 SDValue NewChain = LoLd.getValue(1);
9877 if (TokenFactorIndex != -1) {
9878 Ops.push_back(LoLd);
9879 Ops.push_back(HiLd);
9880 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9884 LoAddr = St->getBasePtr();
9885 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9886 DAG.getConstant(4, MVT::i32));
9888 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9889 St->getSrcValue(), St->getSrcValueOffset(),
9890 St->isVolatile(), St->isNonTemporal(),
9891 St->getAlignment());
9892 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9894 St->getSrcValueOffset() + 4,
9896 St->isNonTemporal(),
9897 MinAlign(St->getAlignment(), 4));
9898 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9903 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9904 /// X86ISD::FXOR nodes.
9905 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9906 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9907 // F[X]OR(0.0, x) -> x
9908 // F[X]OR(x, 0.0) -> x
9909 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9910 if (C->getValueAPF().isPosZero())
9911 return N->getOperand(1);
9912 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9913 if (C->getValueAPF().isPosZero())
9914 return N->getOperand(0);
9918 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9919 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9920 // FAND(0.0, x) -> 0.0
9921 // FAND(x, 0.0) -> 0.0
9922 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9923 if (C->getValueAPF().isPosZero())
9924 return N->getOperand(0);
9925 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9926 if (C->getValueAPF().isPosZero())
9927 return N->getOperand(1);
9931 static SDValue PerformBTCombine(SDNode *N,
9933 TargetLowering::DAGCombinerInfo &DCI) {
9934 // BT ignores high bits in the bit index operand.
9935 SDValue Op1 = N->getOperand(1);
9936 if (Op1.hasOneUse()) {
9937 unsigned BitWidth = Op1.getValueSizeInBits();
9938 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9939 APInt KnownZero, KnownOne;
9940 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
9941 !DCI.isBeforeLegalizeOps());
9942 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9943 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9944 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9945 DCI.CommitTargetLoweringOpt(TLO);
9950 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9951 SDValue Op = N->getOperand(0);
9952 if (Op.getOpcode() == ISD::BIT_CONVERT)
9953 Op = Op.getOperand(0);
9954 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9955 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9956 VT.getVectorElementType().getSizeInBits() ==
9957 OpVT.getVectorElementType().getSizeInBits()) {
9958 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9963 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9964 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9965 // (and (i32 x86isd::setcc_carry), 1)
9966 // This eliminates the zext. This transformation is necessary because
9967 // ISD::SETCC is always legalized to i8.
9968 DebugLoc dl = N->getDebugLoc();
9969 SDValue N0 = N->getOperand(0);
9970 EVT VT = N->getValueType(0);
9971 if (N0.getOpcode() == ISD::AND &&
9973 N0.getOperand(0).hasOneUse()) {
9974 SDValue N00 = N0.getOperand(0);
9975 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9977 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9978 if (!C || C->getZExtValue() != 1)
9980 return DAG.getNode(ISD::AND, dl, VT,
9981 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9982 N00.getOperand(0), N00.getOperand(1)),
9983 DAG.getConstant(1, VT));
9989 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9990 DAGCombinerInfo &DCI) const {
9991 SelectionDAG &DAG = DCI.DAG;
9992 switch (N->getOpcode()) {
9994 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9995 case ISD::EXTRACT_VECTOR_ELT:
9996 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
9997 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9998 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9999 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
10002 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
10003 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
10004 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
10006 case X86ISD::FOR: return PerformFORCombine(N, DAG);
10007 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
10008 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
10009 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
10010 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
10016 /// isTypeDesirableForOp - Return true if the target has native support for
10017 /// the specified value type and it is 'desirable' to use the type for the
10018 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
10019 /// instruction encodings are longer and some i16 instructions are slow.
10020 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
10021 if (!isTypeLegal(VT))
10023 if (VT != MVT::i16)
10030 case ISD::SIGN_EXTEND:
10031 case ISD::ZERO_EXTEND:
10032 case ISD::ANY_EXTEND:
10045 static bool MayFoldLoad(SDValue Op) {
10046 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
10049 static bool MayFoldIntoStore(SDValue Op) {
10050 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
10053 /// IsDesirableToPromoteOp - This method query the target whether it is
10054 /// beneficial for dag combiner to promote the specified node. If true, it
10055 /// should return the desired promotion type by reference.
10056 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
10057 EVT VT = Op.getValueType();
10058 if (VT != MVT::i16)
10061 bool Promote = false;
10062 bool Commute = false;
10063 switch (Op.getOpcode()) {
10066 LoadSDNode *LD = cast<LoadSDNode>(Op);
10067 // If the non-extending load has a single use and it's not live out, then it
10068 // might be folded.
10069 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
10070 Op.hasOneUse()*/) {
10071 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10072 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
10073 // The only case where we'd want to promote LOAD (rather then it being
10074 // promoted as an operand is when it's only use is liveout.
10075 if (UI->getOpcode() != ISD::CopyToReg)
10082 case ISD::SIGN_EXTEND:
10083 case ISD::ZERO_EXTEND:
10084 case ISD::ANY_EXTEND:
10089 SDValue N0 = Op.getOperand(0);
10090 // Look out for (store (shl (load), x)).
10091 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
10104 SDValue N0 = Op.getOperand(0);
10105 SDValue N1 = Op.getOperand(1);
10106 if (!Commute && MayFoldLoad(N1))
10108 // Avoid disabling potential load folding opportunities.
10109 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
10111 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
10121 //===----------------------------------------------------------------------===//
10122 // X86 Inline Assembly Support
10123 //===----------------------------------------------------------------------===//
10125 static bool LowerToBSwap(CallInst *CI) {
10126 // FIXME: this should verify that we are targetting a 486 or better. If not,
10127 // we will turn this bswap into something that will be lowered to logical ops
10128 // instead of emitting the bswap asm. For now, we don't support 486 or lower
10129 // so don't worry about this.
10131 // Verify this is a simple bswap.
10132 if (CI->getNumArgOperands() != 1 ||
10133 CI->getType() != CI->getArgOperand(0)->getType() ||
10134 !CI->getType()->isIntegerTy())
10137 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10138 if (!Ty || Ty->getBitWidth() % 16 != 0)
10141 // Okay, we can do this xform, do so now.
10142 const Type *Tys[] = { Ty };
10143 Module *M = CI->getParent()->getParent()->getParent();
10144 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
10146 Value *Op = CI->getArgOperand(0);
10147 Op = CallInst::Create(Int, Op, CI->getName(), CI);
10149 CI->replaceAllUsesWith(Op);
10150 CI->eraseFromParent();
10154 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
10155 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10156 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
10158 std::string AsmStr = IA->getAsmString();
10160 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
10161 SmallVector<StringRef, 4> AsmPieces;
10162 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
10164 switch (AsmPieces.size()) {
10165 default: return false;
10167 AsmStr = AsmPieces[0];
10169 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
10172 if (AsmPieces.size() == 2 &&
10173 (AsmPieces[0] == "bswap" ||
10174 AsmPieces[0] == "bswapq" ||
10175 AsmPieces[0] == "bswapl") &&
10176 (AsmPieces[1] == "$0" ||
10177 AsmPieces[1] == "${0:q}")) {
10178 // No need to check constraints, nothing other than the equivalent of
10179 // "=r,0" would be valid here.
10180 return LowerToBSwap(CI);
10182 // rorw $$8, ${0:w} --> llvm.bswap.i16
10183 if (CI->getType()->isIntegerTy(16) &&
10184 AsmPieces.size() == 3 &&
10185 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
10186 AsmPieces[1] == "$$8," &&
10187 AsmPieces[2] == "${0:w}" &&
10188 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
10190 const std::string &Constraints = IA->getConstraintString();
10191 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
10192 std::sort(AsmPieces.begin(), AsmPieces.end());
10193 if (AsmPieces.size() == 4 &&
10194 AsmPieces[0] == "~{cc}" &&
10195 AsmPieces[1] == "~{dirflag}" &&
10196 AsmPieces[2] == "~{flags}" &&
10197 AsmPieces[3] == "~{fpsr}") {
10198 return LowerToBSwap(CI);
10203 if (CI->getType()->isIntegerTy(64) &&
10204 Constraints.size() >= 2 &&
10205 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
10206 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
10207 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
10208 SmallVector<StringRef, 4> Words;
10209 SplitString(AsmPieces[0], Words, " \t");
10210 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
10212 SplitString(AsmPieces[1], Words, " \t");
10213 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
10215 SplitString(AsmPieces[2], Words, " \t,");
10216 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
10217 Words[2] == "%edx") {
10218 return LowerToBSwap(CI);
10230 /// getConstraintType - Given a constraint letter, return the type of
10231 /// constraint it is for this target.
10232 X86TargetLowering::ConstraintType
10233 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
10234 if (Constraint.size() == 1) {
10235 switch (Constraint[0]) {
10247 return C_RegisterClass;
10255 return TargetLowering::getConstraintType(Constraint);
10258 /// LowerXConstraint - try to replace an X constraint, which matches anything,
10259 /// with another that has more specific requirements based on the type of the
10260 /// corresponding operand.
10261 const char *X86TargetLowering::
10262 LowerXConstraint(EVT ConstraintVT) const {
10263 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
10264 // 'f' like normal targets.
10265 if (ConstraintVT.isFloatingPoint()) {
10266 if (Subtarget->hasSSE2())
10268 if (Subtarget->hasSSE1())
10272 return TargetLowering::LowerXConstraint(ConstraintVT);
10275 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10276 /// vector. If it is invalid, don't add anything to Ops.
10277 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10279 std::vector<SDValue>&Ops,
10280 SelectionDAG &DAG) const {
10281 SDValue Result(0, 0);
10283 switch (Constraint) {
10286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10287 if (C->getZExtValue() <= 31) {
10288 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10295 if (C->getZExtValue() <= 63) {
10296 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10303 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
10304 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10311 if (C->getZExtValue() <= 255) {
10312 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10318 // 32-bit signed value
10319 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10320 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10321 C->getSExtValue())) {
10322 // Widen to 64 bits here to get it sign extended.
10323 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
10326 // FIXME gcc accepts some relocatable values here too, but only in certain
10327 // memory models; it's complicated.
10332 // 32-bit unsigned value
10333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10334 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10335 C->getZExtValue())) {
10336 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10340 // FIXME gcc accepts some relocatable values here too, but only in certain
10341 // memory models; it's complicated.
10345 // Literal immediates are always ok.
10346 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
10347 // Widen to 64 bits here to get it sign extended.
10348 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10352 // In any sort of PIC mode addresses need to be computed at runtime by
10353 // adding in a register or some sort of table lookup. These can't
10354 // be used as immediates.
10355 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
10358 // If we are in non-pic codegen mode, we allow the address of a global (with
10359 // an optional displacement) to be used with 'i'.
10360 GlobalAddressSDNode *GA = 0;
10361 int64_t Offset = 0;
10363 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10365 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10366 Offset += GA->getOffset();
10368 } else if (Op.getOpcode() == ISD::ADD) {
10369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10370 Offset += C->getZExtValue();
10371 Op = Op.getOperand(0);
10374 } else if (Op.getOpcode() == ISD::SUB) {
10375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10376 Offset += -C->getZExtValue();
10377 Op = Op.getOperand(0);
10382 // Otherwise, this isn't something we can handle, reject it.
10386 const GlobalValue *GV = GA->getGlobal();
10387 // If we require an extra load to get this address, as in PIC mode, we
10388 // can't accept it.
10389 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10390 getTargetMachine())))
10393 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
10394 GA->getValueType(0), Offset);
10399 if (Result.getNode()) {
10400 Ops.push_back(Result);
10403 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10406 std::vector<unsigned> X86TargetLowering::
10407 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10409 if (Constraint.size() == 1) {
10410 // FIXME: not handling fp-stack yet!
10411 switch (Constraint[0]) { // GCC X86 Constraint Letters
10412 default: break; // Unknown constraint letter
10413 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10414 if (Subtarget->is64Bit()) {
10415 if (VT == MVT::i32)
10416 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10417 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10418 X86::R10D,X86::R11D,X86::R12D,
10419 X86::R13D,X86::R14D,X86::R15D,
10420 X86::EBP, X86::ESP, 0);
10421 else if (VT == MVT::i16)
10422 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10423 X86::SI, X86::DI, X86::R8W,X86::R9W,
10424 X86::R10W,X86::R11W,X86::R12W,
10425 X86::R13W,X86::R14W,X86::R15W,
10426 X86::BP, X86::SP, 0);
10427 else if (VT == MVT::i8)
10428 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10429 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10430 X86::R10B,X86::R11B,X86::R12B,
10431 X86::R13B,X86::R14B,X86::R15B,
10432 X86::BPL, X86::SPL, 0);
10434 else if (VT == MVT::i64)
10435 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10436 X86::RSI, X86::RDI, X86::R8, X86::R9,
10437 X86::R10, X86::R11, X86::R12,
10438 X86::R13, X86::R14, X86::R15,
10439 X86::RBP, X86::RSP, 0);
10443 // 32-bit fallthrough
10444 case 'Q': // Q_REGS
10445 if (VT == MVT::i32)
10446 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10447 else if (VT == MVT::i16)
10448 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10449 else if (VT == MVT::i8)
10450 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10451 else if (VT == MVT::i64)
10452 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10457 return std::vector<unsigned>();
10460 std::pair<unsigned, const TargetRegisterClass*>
10461 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10463 // First, see if this is a constraint that directly corresponds to an LLVM
10465 if (Constraint.size() == 1) {
10466 // GCC Constraint Letters
10467 switch (Constraint[0]) {
10469 case 'r': // GENERAL_REGS
10470 case 'l': // INDEX_REGS
10472 return std::make_pair(0U, X86::GR8RegisterClass);
10473 if (VT == MVT::i16)
10474 return std::make_pair(0U, X86::GR16RegisterClass);
10475 if (VT == MVT::i32 || !Subtarget->is64Bit())
10476 return std::make_pair(0U, X86::GR32RegisterClass);
10477 return std::make_pair(0U, X86::GR64RegisterClass);
10478 case 'R': // LEGACY_REGS
10480 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10481 if (VT == MVT::i16)
10482 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10483 if (VT == MVT::i32 || !Subtarget->is64Bit())
10484 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10485 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10486 case 'f': // FP Stack registers.
10487 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10488 // value to the correct fpstack register class.
10489 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10490 return std::make_pair(0U, X86::RFP32RegisterClass);
10491 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10492 return std::make_pair(0U, X86::RFP64RegisterClass);
10493 return std::make_pair(0U, X86::RFP80RegisterClass);
10494 case 'y': // MMX_REGS if MMX allowed.
10495 if (!Subtarget->hasMMX()) break;
10496 return std::make_pair(0U, X86::VR64RegisterClass);
10497 case 'Y': // SSE_REGS if SSE2 allowed
10498 if (!Subtarget->hasSSE2()) break;
10500 case 'x': // SSE_REGS if SSE1 allowed
10501 if (!Subtarget->hasSSE1()) break;
10503 switch (VT.getSimpleVT().SimpleTy) {
10505 // Scalar SSE types.
10508 return std::make_pair(0U, X86::FR32RegisterClass);
10511 return std::make_pair(0U, X86::FR64RegisterClass);
10519 return std::make_pair(0U, X86::VR128RegisterClass);
10525 // Use the default implementation in TargetLowering to convert the register
10526 // constraint into a member of a register class.
10527 std::pair<unsigned, const TargetRegisterClass*> Res;
10528 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10530 // Not found as a standard register?
10531 if (Res.second == 0) {
10532 // Map st(0) -> st(7) -> ST0
10533 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10534 tolower(Constraint[1]) == 's' &&
10535 tolower(Constraint[2]) == 't' &&
10536 Constraint[3] == '(' &&
10537 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10538 Constraint[5] == ')' &&
10539 Constraint[6] == '}') {
10541 Res.first = X86::ST0+Constraint[4]-'0';
10542 Res.second = X86::RFP80RegisterClass;
10546 // GCC allows "st(0)" to be called just plain "st".
10547 if (StringRef("{st}").equals_lower(Constraint)) {
10548 Res.first = X86::ST0;
10549 Res.second = X86::RFP80RegisterClass;
10554 if (StringRef("{flags}").equals_lower(Constraint)) {
10555 Res.first = X86::EFLAGS;
10556 Res.second = X86::CCRRegisterClass;
10560 // 'A' means EAX + EDX.
10561 if (Constraint == "A") {
10562 Res.first = X86::EAX;
10563 Res.second = X86::GR32_ADRegisterClass;
10569 // Otherwise, check to see if this is a register class of the wrong value
10570 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10571 // turn into {ax},{dx}.
10572 if (Res.second->hasType(VT))
10573 return Res; // Correct type already, nothing to do.
10575 // All of the single-register GCC register classes map their values onto
10576 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10577 // really want an 8-bit or 32-bit register, map to the appropriate register
10578 // class and return the appropriate register.
10579 if (Res.second == X86::GR16RegisterClass) {
10580 if (VT == MVT::i8) {
10581 unsigned DestReg = 0;
10582 switch (Res.first) {
10584 case X86::AX: DestReg = X86::AL; break;
10585 case X86::DX: DestReg = X86::DL; break;
10586 case X86::CX: DestReg = X86::CL; break;
10587 case X86::BX: DestReg = X86::BL; break;
10590 Res.first = DestReg;
10591 Res.second = X86::GR8RegisterClass;
10593 } else if (VT == MVT::i32) {
10594 unsigned DestReg = 0;
10595 switch (Res.first) {
10597 case X86::AX: DestReg = X86::EAX; break;
10598 case X86::DX: DestReg = X86::EDX; break;
10599 case X86::CX: DestReg = X86::ECX; break;
10600 case X86::BX: DestReg = X86::EBX; break;
10601 case X86::SI: DestReg = X86::ESI; break;
10602 case X86::DI: DestReg = X86::EDI; break;
10603 case X86::BP: DestReg = X86::EBP; break;
10604 case X86::SP: DestReg = X86::ESP; break;
10607 Res.first = DestReg;
10608 Res.second = X86::GR32RegisterClass;
10610 } else if (VT == MVT::i64) {
10611 unsigned DestReg = 0;
10612 switch (Res.first) {
10614 case X86::AX: DestReg = X86::RAX; break;
10615 case X86::DX: DestReg = X86::RDX; break;
10616 case X86::CX: DestReg = X86::RCX; break;
10617 case X86::BX: DestReg = X86::RBX; break;
10618 case X86::SI: DestReg = X86::RSI; break;
10619 case X86::DI: DestReg = X86::RDI; break;
10620 case X86::BP: DestReg = X86::RBP; break;
10621 case X86::SP: DestReg = X86::RSP; break;
10624 Res.first = DestReg;
10625 Res.second = X86::GR64RegisterClass;
10628 } else if (Res.second == X86::FR32RegisterClass ||
10629 Res.second == X86::FR64RegisterClass ||
10630 Res.second == X86::VR128RegisterClass) {
10631 // Handle references to XMM physical registers that got mapped into the
10632 // wrong class. This can happen with constraints like {xmm0} where the
10633 // target independent register mapper will just pick the first match it can
10634 // find, ignoring the required type.
10635 if (VT == MVT::f32)
10636 Res.second = X86::FR32RegisterClass;
10637 else if (VT == MVT::f64)
10638 Res.second = X86::FR64RegisterClass;
10639 else if (X86::VR128RegisterClass->hasType(VT))
10640 Res.second = X86::VR128RegisterClass;