1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1518 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1520 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1521 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1524 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1535 if (Subtarget->hasDQI()) {
1536 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1537 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1538 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1540 // Custom lower several nodes.
1541 for (MVT VT : MVT::vector_valuetypes()) {
1542 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 setOperationAction(ISD::AND, VT, Legal);
1545 setOperationAction(ISD::OR, VT, Legal);
1546 setOperationAction(ISD::XOR, VT, Legal);
1548 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1549 setOperationAction(ISD::MGATHER, VT, Custom);
1550 setOperationAction(ISD::MSCATTER, VT, Custom);
1552 // Extract subvector is special because the value type
1553 // (result) is 256/128-bit but the source is 512-bit wide.
1554 if (VT.is128BitVector() || VT.is256BitVector()) {
1555 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1557 if (VT.getVectorElementType() == MVT::i1)
1558 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1560 // Do not attempt to custom lower other non-512-bit vectors
1561 if (!VT.is512BitVector())
1564 if (EltSize >= 32) {
1565 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1566 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1567 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1568 setOperationAction(ISD::VSELECT, VT, Legal);
1569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1570 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1572 setOperationAction(ISD::MLOAD, VT, Legal);
1573 setOperationAction(ISD::MSTORE, VT, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 MVT VT = (MVT::SimpleValueType)i;
1579 // Do not attempt to promote non-512-bit vectors.
1580 if (!VT.is512BitVector())
1583 setOperationAction(ISD::SELECT, VT, Promote);
1584 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1588 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1589 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1592 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1593 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1595 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1596 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1597 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1598 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1599 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1602 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1603 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1604 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1605 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1606 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1607 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1608 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1609 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1610 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1611 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1612 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1613 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1614 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1615 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1616 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1617 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1618 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1619 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1620 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1621 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1622 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1623 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1624 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1625 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1629 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1630 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1631 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1632 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1633 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1634 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1635 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1636 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1638 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1639 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1640 if (Subtarget->hasVLX())
1641 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1643 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1644 const MVT VT = (MVT::SimpleValueType)i;
1646 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1648 // Do not attempt to promote non-512-bit vectors.
1649 if (!VT.is512BitVector())
1653 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1654 setOperationAction(ISD::VSELECT, VT, Legal);
1659 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1660 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1661 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1663 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1664 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1665 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1666 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1667 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1668 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1669 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1670 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1671 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1672 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1676 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1677 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1678 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1679 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1680 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1681 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1682 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1683 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1685 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1686 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1687 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1688 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1689 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1690 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1691 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1692 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1695 // We want to custom lower some of our intrinsics.
1696 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1697 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1698 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1699 if (!Subtarget->is64Bit())
1700 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1702 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1703 // handle type legalization for these operations here.
1705 // FIXME: We really should do custom legalization for addition and
1706 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1707 // than generic legalization for 64-bit multiplication-with-overflow, though.
1708 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1709 // Add/Sub/Mul with overflow operations are custom lowered.
1711 setOperationAction(ISD::SADDO, VT, Custom);
1712 setOperationAction(ISD::UADDO, VT, Custom);
1713 setOperationAction(ISD::SSUBO, VT, Custom);
1714 setOperationAction(ISD::USUBO, VT, Custom);
1715 setOperationAction(ISD::SMULO, VT, Custom);
1716 setOperationAction(ISD::UMULO, VT, Custom);
1719 if (!Subtarget->is64Bit()) {
1720 // These libcalls are not available in 32-bit.
1721 setLibcallName(RTLIB::SHL_I128, nullptr);
1722 setLibcallName(RTLIB::SRL_I128, nullptr);
1723 setLibcallName(RTLIB::SRA_I128, nullptr);
1726 // Combine sin / cos into one node or libcall if possible.
1727 if (Subtarget->hasSinCos()) {
1728 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1729 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1730 if (Subtarget->isTargetDarwin()) {
1731 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1732 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1733 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1734 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1738 if (Subtarget->isTargetWin64()) {
1739 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1740 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1741 setOperationAction(ISD::SREM, MVT::i128, Custom);
1742 setOperationAction(ISD::UREM, MVT::i128, Custom);
1743 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1744 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1747 // We have target-specific dag combine patterns for the following nodes:
1748 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1749 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1750 setTargetDAGCombine(ISD::BITCAST);
1751 setTargetDAGCombine(ISD::VSELECT);
1752 setTargetDAGCombine(ISD::SELECT);
1753 setTargetDAGCombine(ISD::SHL);
1754 setTargetDAGCombine(ISD::SRA);
1755 setTargetDAGCombine(ISD::SRL);
1756 setTargetDAGCombine(ISD::OR);
1757 setTargetDAGCombine(ISD::AND);
1758 setTargetDAGCombine(ISD::ADD);
1759 setTargetDAGCombine(ISD::FADD);
1760 setTargetDAGCombine(ISD::FSUB);
1761 setTargetDAGCombine(ISD::FMA);
1762 setTargetDAGCombine(ISD::SUB);
1763 setTargetDAGCombine(ISD::LOAD);
1764 setTargetDAGCombine(ISD::MLOAD);
1765 setTargetDAGCombine(ISD::STORE);
1766 setTargetDAGCombine(ISD::MSTORE);
1767 setTargetDAGCombine(ISD::ZERO_EXTEND);
1768 setTargetDAGCombine(ISD::ANY_EXTEND);
1769 setTargetDAGCombine(ISD::SIGN_EXTEND);
1770 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1771 setTargetDAGCombine(ISD::SINT_TO_FP);
1772 setTargetDAGCombine(ISD::UINT_TO_FP);
1773 setTargetDAGCombine(ISD::SETCC);
1774 setTargetDAGCombine(ISD::BUILD_VECTOR);
1775 setTargetDAGCombine(ISD::MUL);
1776 setTargetDAGCombine(ISD::XOR);
1778 computeRegisterProperties(Subtarget->getRegisterInfo());
1780 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1781 MaxStoresPerMemsetOptSize = 8;
1782 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1783 MaxStoresPerMemcpyOptSize = 4;
1784 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1785 MaxStoresPerMemmoveOptSize = 4;
1786 setPrefLoopAlignment(4); // 2^4 bytes.
1788 // A predictable cmov does not hurt on an in-order CPU.
1789 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1790 PredictableSelectIsExpensive = !Subtarget->isAtom();
1791 EnableExtLdPromotion = true;
1792 setPrefFunctionAlignment(4); // 2^4 bytes.
1794 verifyIntrinsicTables();
1797 // This has so far only been implemented for 64-bit MachO.
1798 bool X86TargetLowering::useLoadStackGuardNode() const {
1799 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1802 TargetLoweringBase::LegalizeTypeAction
1803 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1804 if (ExperimentalVectorWideningLegalization &&
1805 VT.getVectorNumElements() != 1 &&
1806 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1807 return TypeWidenVector;
1809 return TargetLoweringBase::getPreferredVectorAction(VT);
1812 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1815 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1817 const unsigned NumElts = VT.getVectorNumElements();
1818 const EVT EltVT = VT.getVectorElementType();
1819 if (VT.is512BitVector()) {
1820 if (Subtarget->hasAVX512())
1821 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1822 EltVT == MVT::f32 || EltVT == MVT::f64)
1824 case 8: return MVT::v8i1;
1825 case 16: return MVT::v16i1;
1827 if (Subtarget->hasBWI())
1828 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1830 case 32: return MVT::v32i1;
1831 case 64: return MVT::v64i1;
1835 if (VT.is256BitVector() || VT.is128BitVector()) {
1836 if (Subtarget->hasVLX())
1837 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1838 EltVT == MVT::f32 || EltVT == MVT::f64)
1840 case 2: return MVT::v2i1;
1841 case 4: return MVT::v4i1;
1842 case 8: return MVT::v8i1;
1844 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1845 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1847 case 8: return MVT::v8i1;
1848 case 16: return MVT::v16i1;
1849 case 32: return MVT::v32i1;
1853 return VT.changeVectorElementTypeToInteger();
1856 /// Helper for getByValTypeAlignment to determine
1857 /// the desired ByVal argument alignment.
1858 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1861 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1862 if (VTy->getBitWidth() == 128)
1864 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1865 unsigned EltAlign = 0;
1866 getMaxByValAlign(ATy->getElementType(), EltAlign);
1867 if (EltAlign > MaxAlign)
1868 MaxAlign = EltAlign;
1869 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1870 for (auto *EltTy : STy->elements()) {
1871 unsigned EltAlign = 0;
1872 getMaxByValAlign(EltTy, EltAlign);
1873 if (EltAlign > MaxAlign)
1874 MaxAlign = EltAlign;
1881 /// Return the desired alignment for ByVal aggregate
1882 /// function arguments in the caller parameter area. For X86, aggregates
1883 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1884 /// are at 4-byte boundaries.
1885 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1886 const DataLayout &DL) const {
1887 if (Subtarget->is64Bit()) {
1888 // Max of 8 and alignment of type.
1889 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1896 if (Subtarget->hasSSE1())
1897 getMaxByValAlign(Ty, Align);
1901 /// Returns the target specific optimal type for load
1902 /// and store operations as a result of memset, memcpy, and memmove
1903 /// lowering. If DstAlign is zero that means it's safe to destination
1904 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1905 /// means there isn't a need to check it against alignment requirement,
1906 /// probably because the source does not need to be loaded. If 'IsMemset' is
1907 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1908 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1909 /// source is constant so it does not need to be loaded.
1910 /// It returns EVT::Other if the type should be determined using generic
1911 /// target-independent logic.
1913 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1914 unsigned DstAlign, unsigned SrcAlign,
1915 bool IsMemset, bool ZeroMemset,
1917 MachineFunction &MF) const {
1918 const Function *F = MF.getFunction();
1919 if ((!IsMemset || ZeroMemset) &&
1920 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1922 (!Subtarget->isUnalignedMem16Slow() ||
1923 ((DstAlign == 0 || DstAlign >= 16) &&
1924 (SrcAlign == 0 || SrcAlign >= 16)))) {
1926 // FIXME: Check if unaligned 32-byte accesses are slow.
1927 if (Subtarget->hasInt256())
1929 if (Subtarget->hasFp256())
1932 if (Subtarget->hasSSE2())
1934 if (Subtarget->hasSSE1())
1936 } else if (!MemcpyStrSrc && Size >= 8 &&
1937 !Subtarget->is64Bit() &&
1938 Subtarget->hasSSE2()) {
1939 // Do not use f64 to lower memcpy if source is string constant. It's
1940 // better to use i32 to avoid the loads.
1944 // This is a compromise. If we reach here, unaligned accesses may be slow on
1945 // this target. However, creating smaller, aligned accesses could be even
1946 // slower and would certainly be a lot more code.
1947 if (Subtarget->is64Bit() && Size >= 8)
1952 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1954 return X86ScalarSSEf32;
1955 else if (VT == MVT::f64)
1956 return X86ScalarSSEf64;
1961 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1966 switch (VT.getSizeInBits()) {
1968 // 8-byte and under are always assumed to be fast.
1972 *Fast = !Subtarget->isUnalignedMem16Slow();
1975 *Fast = !Subtarget->isUnalignedMem32Slow();
1977 // TODO: What about AVX-512 (512-bit) accesses?
1980 // Misaligned accesses of any size are always allowed.
1984 /// Return the entry encoding for a jump table in the
1985 /// current function. The returned value is a member of the
1986 /// MachineJumpTableInfo::JTEntryKind enum.
1987 unsigned X86TargetLowering::getJumpTableEncoding() const {
1988 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1990 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1991 Subtarget->isPICStyleGOT())
1992 return MachineJumpTableInfo::EK_Custom32;
1994 // Otherwise, use the normal jump table encoding heuristics.
1995 return TargetLowering::getJumpTableEncoding();
1998 bool X86TargetLowering::useSoftFloat() const {
1999 return Subtarget->useSoftFloat();
2003 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2004 const MachineBasicBlock *MBB,
2005 unsigned uid,MCContext &Ctx) const{
2006 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2007 Subtarget->isPICStyleGOT());
2008 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2010 return MCSymbolRefExpr::create(MBB->getSymbol(),
2011 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2014 /// Returns relocation base for the given PIC jumptable.
2015 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2016 SelectionDAG &DAG) const {
2017 if (!Subtarget->is64Bit())
2018 // This doesn't have SDLoc associated with it, but is not really the
2019 // same as a Register.
2020 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2021 getPointerTy(DAG.getDataLayout()));
2025 /// This returns the relocation base for the given PIC jumptable,
2026 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2027 const MCExpr *X86TargetLowering::
2028 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2029 MCContext &Ctx) const {
2030 // X86-64 uses RIP relative addressing based on the jump table label.
2031 if (Subtarget->isPICStyleRIPRel())
2032 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2034 // Otherwise, the reference is relative to the PIC base.
2035 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2038 std::pair<const TargetRegisterClass *, uint8_t>
2039 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2041 const TargetRegisterClass *RRC = nullptr;
2043 switch (VT.SimpleTy) {
2045 return TargetLowering::findRepresentativeClass(TRI, VT);
2046 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2047 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2050 RRC = &X86::VR64RegClass;
2052 case MVT::f32: case MVT::f64:
2053 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2054 case MVT::v4f32: case MVT::v2f64:
2055 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2057 RRC = &X86::VR128RegClass;
2060 return std::make_pair(RRC, Cost);
2063 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2064 unsigned &Offset) const {
2065 if (!Subtarget->isTargetLinux())
2068 if (Subtarget->is64Bit()) {
2069 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2071 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2083 /// Android provides a fixed TLS slot for the SafeStack pointer.
2084 /// See the definition of TLS_SLOT_SAFESTACK in
2085 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2086 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2087 unsigned &Offset) const {
2088 if (!Subtarget->isTargetAndroid())
2091 if (Subtarget->is64Bit()) {
2092 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2094 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2106 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2107 unsigned DestAS) const {
2108 assert(SrcAS != DestAS && "Expected different address spaces!");
2110 return SrcAS < 256 && DestAS < 256;
2113 //===----------------------------------------------------------------------===//
2114 // Return Value Calling Convention Implementation
2115 //===----------------------------------------------------------------------===//
2117 #include "X86GenCallingConv.inc"
2119 bool X86TargetLowering::CanLowerReturn(
2120 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2121 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2122 SmallVector<CCValAssign, 16> RVLocs;
2123 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2124 return CCInfo.CheckReturn(Outs, RetCC_X86);
2127 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2128 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2133 X86TargetLowering::LowerReturn(SDValue Chain,
2134 CallingConv::ID CallConv, bool isVarArg,
2135 const SmallVectorImpl<ISD::OutputArg> &Outs,
2136 const SmallVectorImpl<SDValue> &OutVals,
2137 SDLoc dl, SelectionDAG &DAG) const {
2138 MachineFunction &MF = DAG.getMachineFunction();
2139 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2141 SmallVector<CCValAssign, 16> RVLocs;
2142 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2143 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2146 SmallVector<SDValue, 6> RetOps;
2147 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2148 // Operand #1 = Bytes To Pop
2149 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2152 // Copy the result values into the output registers.
2153 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2154 CCValAssign &VA = RVLocs[i];
2155 assert(VA.isRegLoc() && "Can only return in registers!");
2156 SDValue ValToCopy = OutVals[i];
2157 EVT ValVT = ValToCopy.getValueType();
2159 // Promote values to the appropriate types.
2160 if (VA.getLocInfo() == CCValAssign::SExt)
2161 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2162 else if (VA.getLocInfo() == CCValAssign::ZExt)
2163 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2164 else if (VA.getLocInfo() == CCValAssign::AExt) {
2165 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2166 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2168 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2170 else if (VA.getLocInfo() == CCValAssign::BCvt)
2171 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2173 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2174 "Unexpected FP-extend for return value.");
2176 // If this is x86-64, and we disabled SSE, we can't return FP values,
2177 // or SSE or MMX vectors.
2178 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2179 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2180 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2181 report_fatal_error("SSE register return with SSE disabled");
2183 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2184 // llvm-gcc has never done it right and no one has noticed, so this
2185 // should be OK for now.
2186 if (ValVT == MVT::f64 &&
2187 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2188 report_fatal_error("SSE2 register return with SSE2 disabled");
2190 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2191 // the RET instruction and handled by the FP Stackifier.
2192 if (VA.getLocReg() == X86::FP0 ||
2193 VA.getLocReg() == X86::FP1) {
2194 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2195 // change the value to the FP stack register class.
2196 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2197 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2198 RetOps.push_back(ValToCopy);
2199 // Don't emit a copytoreg.
2203 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2204 // which is returned in RAX / RDX.
2205 if (Subtarget->is64Bit()) {
2206 if (ValVT == MVT::x86mmx) {
2207 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2208 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2209 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2211 // If we don't have SSE2 available, convert to v4f32 so the generated
2212 // register is legal.
2213 if (!Subtarget->hasSSE2())
2214 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2219 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2220 Flag = Chain.getValue(1);
2221 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2224 // All x86 ABIs require that for returning structs by value we copy
2225 // the sret argument into %rax/%eax (depending on ABI) for the return.
2226 // We saved the argument into a virtual register in the entry block,
2227 // so now we copy the value out and into %rax/%eax.
2229 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2230 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2231 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2232 // either case FuncInfo->setSRetReturnReg() will have been called.
2233 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2234 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2235 getPointerTy(MF.getDataLayout()));
2238 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2239 X86::RAX : X86::EAX;
2240 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2241 Flag = Chain.getValue(1);
2243 // RAX/EAX now acts like a return value.
2245 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2248 RetOps[0] = Chain; // Update chain.
2250 // Add the flag if we have it.
2252 RetOps.push_back(Flag);
2254 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2257 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2258 if (N->getNumValues() != 1)
2260 if (!N->hasNUsesOfValue(1, 0))
2263 SDValue TCChain = Chain;
2264 SDNode *Copy = *N->use_begin();
2265 if (Copy->getOpcode() == ISD::CopyToReg) {
2266 // If the copy has a glue operand, we conservatively assume it isn't safe to
2267 // perform a tail call.
2268 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2270 TCChain = Copy->getOperand(0);
2271 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2274 bool HasRet = false;
2275 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2277 if (UI->getOpcode() != X86ISD::RET_FLAG)
2279 // If we are returning more than one value, we can definitely
2280 // not make a tail call see PR19530
2281 if (UI->getNumOperands() > 4)
2283 if (UI->getNumOperands() == 4 &&
2284 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2297 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2298 ISD::NodeType ExtendKind) const {
2300 // TODO: Is this also valid on 32-bit?
2301 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2302 ReturnMVT = MVT::i8;
2304 ReturnMVT = MVT::i32;
2306 EVT MinVT = getRegisterType(Context, ReturnMVT);
2307 return VT.bitsLT(MinVT) ? MinVT : VT;
2310 /// Lower the result values of a call into the
2311 /// appropriate copies out of appropriate physical registers.
2314 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2315 CallingConv::ID CallConv, bool isVarArg,
2316 const SmallVectorImpl<ISD::InputArg> &Ins,
2317 SDLoc dl, SelectionDAG &DAG,
2318 SmallVectorImpl<SDValue> &InVals) const {
2320 // Assign locations to each value returned by this call.
2321 SmallVector<CCValAssign, 16> RVLocs;
2322 bool Is64Bit = Subtarget->is64Bit();
2323 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2325 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2327 // Copy all of the result registers out of their specified physreg.
2328 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2329 CCValAssign &VA = RVLocs[i];
2330 EVT CopyVT = VA.getLocVT();
2332 // If this is x86-64, and we disabled SSE, we can't return FP values
2333 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2334 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2335 report_fatal_error("SSE register return with SSE disabled");
2338 // If we prefer to use the value in xmm registers, copy it out as f80 and
2339 // use a truncate to move it from fp stack reg to xmm reg.
2340 bool RoundAfterCopy = false;
2341 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2342 isScalarFPTypeInSSEReg(VA.getValVT())) {
2344 RoundAfterCopy = (CopyVT != VA.getLocVT());
2347 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2348 CopyVT, InFlag).getValue(1);
2349 SDValue Val = Chain.getValue(0);
2352 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2353 // This truncation won't change the value.
2354 DAG.getIntPtrConstant(1, dl));
2356 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2357 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2359 InFlag = Chain.getValue(2);
2360 InVals.push_back(Val);
2366 //===----------------------------------------------------------------------===//
2367 // C & StdCall & Fast Calling Convention implementation
2368 //===----------------------------------------------------------------------===//
2369 // StdCall calling convention seems to be standard for many Windows' API
2370 // routines and around. It differs from C calling convention just a little:
2371 // callee should clean up the stack, not caller. Symbols should be also
2372 // decorated in some fancy way :) It doesn't support any vector arguments.
2373 // For info on fast calling convention see Fast Calling Convention (tail call)
2374 // implementation LowerX86_32FastCCCallTo.
2376 /// CallIsStructReturn - Determines whether a call uses struct return
2378 enum StructReturnType {
2383 static StructReturnType
2384 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2386 return NotStructReturn;
2388 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2389 if (!Flags.isSRet())
2390 return NotStructReturn;
2391 if (Flags.isInReg())
2392 return RegStructReturn;
2393 return StackStructReturn;
2396 /// Determines whether a function uses struct return semantics.
2397 static StructReturnType
2398 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2400 return NotStructReturn;
2402 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2403 if (!Flags.isSRet())
2404 return NotStructReturn;
2405 if (Flags.isInReg())
2406 return RegStructReturn;
2407 return StackStructReturn;
2410 /// Make a copy of an aggregate at address specified by "Src" to address
2411 /// "Dst" with size and alignment information specified by the specific
2412 /// parameter attribute. The copy will be passed as a byval function parameter.
2414 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2415 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2417 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2419 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2420 /*isVolatile*/false, /*AlwaysInline=*/true,
2421 /*isTailCall*/false,
2422 MachinePointerInfo(), MachinePointerInfo());
2425 /// Return true if the calling convention is one that
2426 /// supports tail call optimization.
2427 static bool IsTailCallConvention(CallingConv::ID CC) {
2428 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2429 CC == CallingConv::HiPE);
2432 /// \brief Return true if the calling convention is a C calling convention.
2433 static bool IsCCallConvention(CallingConv::ID CC) {
2434 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2435 CC == CallingConv::X86_64_SysV);
2438 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2440 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2441 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2445 CallingConv::ID CalleeCC = CS.getCallingConv();
2446 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2452 /// Return true if the function is being made into
2453 /// a tailcall target by changing its ABI.
2454 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2455 bool GuaranteedTailCallOpt) {
2456 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2460 X86TargetLowering::LowerMemArgument(SDValue Chain,
2461 CallingConv::ID CallConv,
2462 const SmallVectorImpl<ISD::InputArg> &Ins,
2463 SDLoc dl, SelectionDAG &DAG,
2464 const CCValAssign &VA,
2465 MachineFrameInfo *MFI,
2467 // Create the nodes corresponding to a load from this parameter slot.
2468 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2469 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2470 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2471 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2474 // If value is passed by pointer we have address passed instead of the value
2476 bool ExtendedInMem = VA.isExtInLoc() &&
2477 VA.getValVT().getScalarType() == MVT::i1;
2479 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2480 ValVT = VA.getLocVT();
2482 ValVT = VA.getValVT();
2484 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2485 // changed with more analysis.
2486 // In case of tail call optimization mark all arguments mutable. Since they
2487 // could be overwritten by lowering of arguments in case of a tail call.
2488 if (Flags.isByVal()) {
2489 unsigned Bytes = Flags.getByValSize();
2490 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2491 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2492 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2494 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2495 VA.getLocMemOffset(), isImmutable);
2496 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2497 SDValue Val = DAG.getLoad(
2498 ValVT, dl, Chain, FIN,
2499 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2501 return ExtendedInMem ?
2502 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2506 // FIXME: Get this from tablegen.
2507 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2508 const X86Subtarget *Subtarget) {
2509 assert(Subtarget->is64Bit());
2511 if (Subtarget->isCallingConvWin64(CallConv)) {
2512 static const MCPhysReg GPR64ArgRegsWin64[] = {
2513 X86::RCX, X86::RDX, X86::R8, X86::R9
2515 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2518 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2519 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2521 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2524 // FIXME: Get this from tablegen.
2525 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2526 CallingConv::ID CallConv,
2527 const X86Subtarget *Subtarget) {
2528 assert(Subtarget->is64Bit());
2529 if (Subtarget->isCallingConvWin64(CallConv)) {
2530 // The XMM registers which might contain var arg parameters are shadowed
2531 // in their paired GPR. So we only need to save the GPR to their home
2533 // TODO: __vectorcall will change this.
2537 const Function *Fn = MF.getFunction();
2538 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2539 bool isSoftFloat = Subtarget->useSoftFloat();
2540 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2541 "SSE register cannot be used when SSE is disabled!");
2542 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2543 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2547 static const MCPhysReg XMMArgRegs64Bit[] = {
2548 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2549 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2551 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2554 SDValue X86TargetLowering::LowerFormalArguments(
2555 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2556 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2557 SmallVectorImpl<SDValue> &InVals) const {
2558 MachineFunction &MF = DAG.getMachineFunction();
2559 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2560 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2562 const Function* Fn = MF.getFunction();
2563 if (Fn->hasExternalLinkage() &&
2564 Subtarget->isTargetCygMing() &&
2565 Fn->getName() == "main")
2566 FuncInfo->setForceFramePointer(true);
2568 MachineFrameInfo *MFI = MF.getFrameInfo();
2569 bool Is64Bit = Subtarget->is64Bit();
2570 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2572 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2573 "Var args not supported with calling convention fastcc, ghc or hipe");
2575 // Assign locations to all of the incoming arguments.
2576 SmallVector<CCValAssign, 16> ArgLocs;
2577 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2579 // Allocate shadow area for Win64
2581 CCInfo.AllocateStack(32, 8);
2583 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2585 unsigned LastVal = ~0U;
2587 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2588 CCValAssign &VA = ArgLocs[i];
2589 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2591 assert(VA.getValNo() != LastVal &&
2592 "Don't support value assigned to multiple locs yet");
2594 LastVal = VA.getValNo();
2596 if (VA.isRegLoc()) {
2597 EVT RegVT = VA.getLocVT();
2598 const TargetRegisterClass *RC;
2599 if (RegVT == MVT::i32)
2600 RC = &X86::GR32RegClass;
2601 else if (Is64Bit && RegVT == MVT::i64)
2602 RC = &X86::GR64RegClass;
2603 else if (RegVT == MVT::f32)
2604 RC = &X86::FR32RegClass;
2605 else if (RegVT == MVT::f64)
2606 RC = &X86::FR64RegClass;
2607 else if (RegVT.is512BitVector())
2608 RC = &X86::VR512RegClass;
2609 else if (RegVT.is256BitVector())
2610 RC = &X86::VR256RegClass;
2611 else if (RegVT.is128BitVector())
2612 RC = &X86::VR128RegClass;
2613 else if (RegVT == MVT::x86mmx)
2614 RC = &X86::VR64RegClass;
2615 else if (RegVT == MVT::i1)
2616 RC = &X86::VK1RegClass;
2617 else if (RegVT == MVT::v8i1)
2618 RC = &X86::VK8RegClass;
2619 else if (RegVT == MVT::v16i1)
2620 RC = &X86::VK16RegClass;
2621 else if (RegVT == MVT::v32i1)
2622 RC = &X86::VK32RegClass;
2623 else if (RegVT == MVT::v64i1)
2624 RC = &X86::VK64RegClass;
2626 llvm_unreachable("Unknown argument type!");
2628 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2629 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2631 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2632 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2634 if (VA.getLocInfo() == CCValAssign::SExt)
2635 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2636 DAG.getValueType(VA.getValVT()));
2637 else if (VA.getLocInfo() == CCValAssign::ZExt)
2638 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2639 DAG.getValueType(VA.getValVT()));
2640 else if (VA.getLocInfo() == CCValAssign::BCvt)
2641 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2643 if (VA.isExtInLoc()) {
2644 // Handle MMX values passed in XMM regs.
2645 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2646 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2648 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2651 assert(VA.isMemLoc());
2652 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2655 // If value is passed via pointer - do a load.
2656 if (VA.getLocInfo() == CCValAssign::Indirect)
2657 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2658 MachinePointerInfo(), false, false, false, 0);
2660 InVals.push_back(ArgValue);
2663 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2664 // All x86 ABIs require that for returning structs by value we copy the
2665 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2666 // the argument into a virtual register so that we can access it from the
2668 if (Ins[i].Flags.isSRet()) {
2669 unsigned Reg = FuncInfo->getSRetReturnReg();
2671 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2672 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2673 FuncInfo->setSRetReturnReg(Reg);
2675 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2676 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2681 unsigned StackSize = CCInfo.getNextStackOffset();
2682 // Align stack specially for tail calls.
2683 if (FuncIsMadeTailCallSafe(CallConv,
2684 MF.getTarget().Options.GuaranteedTailCallOpt))
2685 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2687 // If the function takes variable number of arguments, make a frame index for
2688 // the start of the first vararg value... for expansion of llvm.va_start. We
2689 // can skip this if there are no va_start calls.
2690 if (MFI->hasVAStart() &&
2691 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2692 CallConv != CallingConv::X86_ThisCall))) {
2693 FuncInfo->setVarArgsFrameIndex(
2694 MFI->CreateFixedObject(1, StackSize, true));
2697 MachineModuleInfo &MMI = MF.getMMI();
2698 const Function *WinEHParent = nullptr;
2699 if (MMI.hasWinEHFuncInfo(Fn))
2700 WinEHParent = MMI.getWinEHParent(Fn);
2701 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2703 // Figure out if XMM registers are in use.
2704 assert(!(Subtarget->useSoftFloat() &&
2705 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2706 "SSE register cannot be used when SSE is disabled!");
2708 // 64-bit calling conventions support varargs and register parameters, so we
2709 // have to do extra work to spill them in the prologue.
2710 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2711 // Find the first unallocated argument registers.
2712 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2713 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2714 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2715 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2716 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2717 "SSE register cannot be used when SSE is disabled!");
2719 // Gather all the live in physical registers.
2720 SmallVector<SDValue, 6> LiveGPRs;
2721 SmallVector<SDValue, 8> LiveXMMRegs;
2723 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2724 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2726 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2728 if (!ArgXMMs.empty()) {
2729 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2730 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2731 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2732 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2733 LiveXMMRegs.push_back(
2734 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2739 // Get to the caller-allocated home save location. Add 8 to account
2740 // for the return address.
2741 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2742 FuncInfo->setRegSaveFrameIndex(
2743 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2744 // Fixup to set vararg frame on shadow area (4 x i64).
2746 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2748 // For X86-64, if there are vararg parameters that are passed via
2749 // registers, then we must store them to their spots on the stack so
2750 // they may be loaded by deferencing the result of va_next.
2751 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2752 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2753 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2754 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2757 // Store the integer parameter registers.
2758 SmallVector<SDValue, 8> MemOps;
2759 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2760 getPointerTy(DAG.getDataLayout()));
2761 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2762 for (SDValue Val : LiveGPRs) {
2763 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2764 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2766 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2767 MachinePointerInfo::getFixedStack(
2768 DAG.getMachineFunction(),
2769 FuncInfo->getRegSaveFrameIndex(), Offset),
2771 MemOps.push_back(Store);
2775 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2776 // Now store the XMM (fp + vector) parameter registers.
2777 SmallVector<SDValue, 12> SaveXMMOps;
2778 SaveXMMOps.push_back(Chain);
2779 SaveXMMOps.push_back(ALVal);
2780 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2781 FuncInfo->getRegSaveFrameIndex(), dl));
2782 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2783 FuncInfo->getVarArgsFPOffset(), dl));
2784 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2786 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2787 MVT::Other, SaveXMMOps));
2790 if (!MemOps.empty())
2791 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2794 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2795 // Find the largest legal vector type.
2796 MVT VecVT = MVT::Other;
2797 // FIXME: Only some x86_32 calling conventions support AVX512.
2798 if (Subtarget->hasAVX512() &&
2799 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2800 CallConv == CallingConv::Intel_OCL_BI)))
2801 VecVT = MVT::v16f32;
2802 else if (Subtarget->hasAVX())
2804 else if (Subtarget->hasSSE2())
2807 // We forward some GPRs and some vector types.
2808 SmallVector<MVT, 2> RegParmTypes;
2809 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2810 RegParmTypes.push_back(IntVT);
2811 if (VecVT != MVT::Other)
2812 RegParmTypes.push_back(VecVT);
2814 // Compute the set of forwarded registers. The rest are scratch.
2815 SmallVectorImpl<ForwardedRegister> &Forwards =
2816 FuncInfo->getForwardedMustTailRegParms();
2817 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2819 // Conservatively forward AL on x86_64, since it might be used for varargs.
2820 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2821 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2822 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2825 // Copy all forwards from physical to virtual registers.
2826 for (ForwardedRegister &F : Forwards) {
2827 // FIXME: Can we use a less constrained schedule?
2828 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2829 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2830 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2834 // Some CCs need callee pop.
2835 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2836 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2837 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2839 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2840 // If this is an sret function, the return should pop the hidden pointer.
2841 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2842 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2843 argsAreStructReturn(Ins) == StackStructReturn)
2844 FuncInfo->setBytesToPopOnReturn(4);
2848 // RegSaveFrameIndex is X86-64 only.
2849 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2850 if (CallConv == CallingConv::X86_FastCall ||
2851 CallConv == CallingConv::X86_ThisCall)
2852 // fastcc functions can't have varargs.
2853 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2856 FuncInfo->setArgumentStackSize(StackSize);
2858 if (IsWinEHParent) {
2860 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2861 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2862 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2863 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2864 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2865 MachinePointerInfo::getFixedStack(
2866 DAG.getMachineFunction(), UnwindHelpFI),
2867 /*isVolatile=*/true,
2868 /*isNonTemporal=*/false, /*Alignment=*/0);
2870 // Functions using Win32 EH are considered to have opaque SP adjustments
2871 // to force local variables to be addressed from the frame or base
2873 MFI->setHasOpaqueSPAdjustment(true);
2881 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2882 SDValue StackPtr, SDValue Arg,
2883 SDLoc dl, SelectionDAG &DAG,
2884 const CCValAssign &VA,
2885 ISD::ArgFlagsTy Flags) const {
2886 unsigned LocMemOffset = VA.getLocMemOffset();
2887 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2888 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2890 if (Flags.isByVal())
2891 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2893 return DAG.getStore(
2894 Chain, dl, Arg, PtrOff,
2895 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2899 /// Emit a load of return address if tail call
2900 /// optimization is performed and it is required.
2902 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2903 SDValue &OutRetAddr, SDValue Chain,
2904 bool IsTailCall, bool Is64Bit,
2905 int FPDiff, SDLoc dl) const {
2906 // Adjust the Return address stack slot.
2907 EVT VT = getPointerTy(DAG.getDataLayout());
2908 OutRetAddr = getReturnAddressFrameIndex(DAG);
2910 // Load the "old" Return address.
2911 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2912 false, false, false, 0);
2913 return SDValue(OutRetAddr.getNode(), 1);
2916 /// Emit a store of the return address if tail call
2917 /// optimization is performed and it is required (FPDiff!=0).
2918 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2919 SDValue Chain, SDValue RetAddrFrIdx,
2920 EVT PtrVT, unsigned SlotSize,
2921 int FPDiff, SDLoc dl) {
2922 // Store the return address to the appropriate stack slot.
2923 if (!FPDiff) return Chain;
2924 // Calculate the new stack slot for the return address.
2925 int NewReturnAddrFI =
2926 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2928 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2929 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2930 MachinePointerInfo::getFixedStack(
2931 DAG.getMachineFunction(), NewReturnAddrFI),
2936 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2937 /// operation of specified width.
2938 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2940 unsigned NumElems = VT.getVectorNumElements();
2941 SmallVector<int, 8> Mask;
2942 Mask.push_back(NumElems);
2943 for (unsigned i = 1; i != NumElems; ++i)
2945 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2949 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2950 SmallVectorImpl<SDValue> &InVals) const {
2951 SelectionDAG &DAG = CLI.DAG;
2953 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2954 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2955 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2956 SDValue Chain = CLI.Chain;
2957 SDValue Callee = CLI.Callee;
2958 CallingConv::ID CallConv = CLI.CallConv;
2959 bool &isTailCall = CLI.IsTailCall;
2960 bool isVarArg = CLI.IsVarArg;
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 bool Is64Bit = Subtarget->is64Bit();
2964 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2965 StructReturnType SR = callIsStructReturn(Outs);
2966 bool IsSibcall = false;
2967 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2968 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2970 if (Attr.getValueAsString() == "true")
2973 if (Subtarget->isPICStyleGOT() &&
2974 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2975 // If we are using a GOT, disable tail calls to external symbols with
2976 // default visibility. Tail calling such a symbol requires using a GOT
2977 // relocation, which forces early binding of the symbol. This breaks code
2978 // that require lazy function symbol resolution. Using musttail or
2979 // GuaranteedTailCallOpt will override this.
2980 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2981 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2982 G->getGlobal()->hasDefaultVisibility()))
2986 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2988 // Force this to be a tail call. The verifier rules are enough to ensure
2989 // that we can lower this successfully without moving the return address
2992 } else if (isTailCall) {
2993 // Check if it's really possible to do a tail call.
2994 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2995 isVarArg, SR != NotStructReturn,
2996 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2997 Outs, OutVals, Ins, DAG);
2999 // Sibcalls are automatically detected tailcalls which do not require
3001 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3008 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3009 "Var args not supported with calling convention fastcc, ghc or hipe");
3011 // Analyze operands of the call, assigning locations to each operand.
3012 SmallVector<CCValAssign, 16> ArgLocs;
3013 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3015 // Allocate shadow area for Win64
3017 CCInfo.AllocateStack(32, 8);
3019 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3021 // Get a count of how many bytes are to be pushed on the stack.
3022 unsigned NumBytes = CCInfo.getNextStackOffset();
3024 // This is a sibcall. The memory operands are available in caller's
3025 // own caller's stack.
3027 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3028 IsTailCallConvention(CallConv))
3029 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3032 if (isTailCall && !IsSibcall && !IsMustTail) {
3033 // Lower arguments at fp - stackoffset + fpdiff.
3034 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3036 FPDiff = NumBytesCallerPushed - NumBytes;
3038 // Set the delta of movement of the returnaddr stackslot.
3039 // But only set if delta is greater than previous delta.
3040 if (FPDiff < X86Info->getTCReturnAddrDelta())
3041 X86Info->setTCReturnAddrDelta(FPDiff);
3044 unsigned NumBytesToPush = NumBytes;
3045 unsigned NumBytesToPop = NumBytes;
3047 // If we have an inalloca argument, all stack space has already been allocated
3048 // for us and be right at the top of the stack. We don't support multiple
3049 // arguments passed in memory when using inalloca.
3050 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3052 if (!ArgLocs.back().isMemLoc())
3053 report_fatal_error("cannot use inalloca attribute on a register "
3055 if (ArgLocs.back().getLocMemOffset() != 0)
3056 report_fatal_error("any parameter with the inalloca attribute must be "
3057 "the only memory argument");
3061 Chain = DAG.getCALLSEQ_START(
3062 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3064 SDValue RetAddrFrIdx;
3065 // Load return address for tail calls.
3066 if (isTailCall && FPDiff)
3067 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3068 Is64Bit, FPDiff, dl);
3070 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3071 SmallVector<SDValue, 8> MemOpChains;
3074 // Walk the register/memloc assignments, inserting copies/loads. In the case
3075 // of tail call optimization arguments are handle later.
3076 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3077 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3078 // Skip inalloca arguments, they have already been written.
3079 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3080 if (Flags.isInAlloca())
3083 CCValAssign &VA = ArgLocs[i];
3084 EVT RegVT = VA.getLocVT();
3085 SDValue Arg = OutVals[i];
3086 bool isByVal = Flags.isByVal();
3088 // Promote the value if needed.
3089 switch (VA.getLocInfo()) {
3090 default: llvm_unreachable("Unknown loc info!");
3091 case CCValAssign::Full: break;
3092 case CCValAssign::SExt:
3093 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3095 case CCValAssign::ZExt:
3096 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3098 case CCValAssign::AExt:
3099 if (Arg.getValueType().isVector() &&
3100 Arg.getValueType().getScalarType() == MVT::i1)
3101 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3102 else if (RegVT.is128BitVector()) {
3103 // Special case: passing MMX values in XMM registers.
3104 Arg = DAG.getBitcast(MVT::i64, Arg);
3105 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3106 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3108 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3110 case CCValAssign::BCvt:
3111 Arg = DAG.getBitcast(RegVT, Arg);
3113 case CCValAssign::Indirect: {
3114 // Store the argument.
3115 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3116 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3117 Chain = DAG.getStore(
3118 Chain, dl, Arg, SpillSlot,
3119 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3126 if (VA.isRegLoc()) {
3127 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3128 if (isVarArg && IsWin64) {
3129 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3130 // shadow reg if callee is a varargs function.
3131 unsigned ShadowReg = 0;
3132 switch (VA.getLocReg()) {
3133 case X86::XMM0: ShadowReg = X86::RCX; break;
3134 case X86::XMM1: ShadowReg = X86::RDX; break;
3135 case X86::XMM2: ShadowReg = X86::R8; break;
3136 case X86::XMM3: ShadowReg = X86::R9; break;
3139 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3141 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3142 assert(VA.isMemLoc());
3143 if (!StackPtr.getNode())
3144 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3145 getPointerTy(DAG.getDataLayout()));
3146 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3147 dl, DAG, VA, Flags));
3151 if (!MemOpChains.empty())
3152 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3154 if (Subtarget->isPICStyleGOT()) {
3155 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3158 RegsToPass.push_back(std::make_pair(
3159 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3160 getPointerTy(DAG.getDataLayout()))));
3162 // If we are tail calling and generating PIC/GOT style code load the
3163 // address of the callee into ECX. The value in ecx is used as target of
3164 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3165 // for tail calls on PIC/GOT architectures. Normally we would just put the
3166 // address of GOT into ebx and then call target@PLT. But for tail calls
3167 // ebx would be restored (since ebx is callee saved) before jumping to the
3170 // Note: The actual moving to ECX is done further down.
3171 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3172 if (G && !G->getGlobal()->hasLocalLinkage() &&
3173 G->getGlobal()->hasDefaultVisibility())
3174 Callee = LowerGlobalAddress(Callee, DAG);
3175 else if (isa<ExternalSymbolSDNode>(Callee))
3176 Callee = LowerExternalSymbol(Callee, DAG);
3180 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3181 // From AMD64 ABI document:
3182 // For calls that may call functions that use varargs or stdargs
3183 // (prototype-less calls or calls to functions containing ellipsis (...) in
3184 // the declaration) %al is used as hidden argument to specify the number
3185 // of SSE registers used. The contents of %al do not need to match exactly
3186 // the number of registers, but must be an ubound on the number of SSE
3187 // registers used and is in the range 0 - 8 inclusive.
3189 // Count the number of XMM registers allocated.
3190 static const MCPhysReg XMMArgRegs[] = {
3191 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3192 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3194 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3195 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3196 && "SSE registers cannot be used when SSE is disabled");
3198 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3199 DAG.getConstant(NumXMMRegs, dl,
3203 if (isVarArg && IsMustTail) {
3204 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3205 for (const auto &F : Forwards) {
3206 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3207 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3211 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3212 // don't need this because the eligibility check rejects calls that require
3213 // shuffling arguments passed in memory.
3214 if (!IsSibcall && isTailCall) {
3215 // Force all the incoming stack arguments to be loaded from the stack
3216 // before any new outgoing arguments are stored to the stack, because the
3217 // outgoing stack slots may alias the incoming argument stack slots, and
3218 // the alias isn't otherwise explicit. This is slightly more conservative
3219 // than necessary, because it means that each store effectively depends
3220 // on every argument instead of just those arguments it would clobber.
3221 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3223 SmallVector<SDValue, 8> MemOpChains2;
3226 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3227 CCValAssign &VA = ArgLocs[i];
3230 assert(VA.isMemLoc());
3231 SDValue Arg = OutVals[i];
3232 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3233 // Skip inalloca arguments. They don't require any work.
3234 if (Flags.isInAlloca())
3236 // Create frame index.
3237 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3238 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3239 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3240 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3242 if (Flags.isByVal()) {
3243 // Copy relative to framepointer.
3244 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3245 if (!StackPtr.getNode())
3246 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3247 getPointerTy(DAG.getDataLayout()));
3248 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3251 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3255 // Store relative to framepointer.
3256 MemOpChains2.push_back(DAG.getStore(
3257 ArgChain, dl, Arg, FIN,
3258 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3263 if (!MemOpChains2.empty())
3264 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3266 // Store the return address to the appropriate stack slot.
3267 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3268 getPointerTy(DAG.getDataLayout()),
3269 RegInfo->getSlotSize(), FPDiff, dl);
3272 // Build a sequence of copy-to-reg nodes chained together with token chain
3273 // and flag operands which copy the outgoing args into registers.
3275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3276 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3277 RegsToPass[i].second, InFlag);
3278 InFlag = Chain.getValue(1);
3281 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3282 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3283 // In the 64-bit large code model, we have to make all calls
3284 // through a register, since the call instruction's 32-bit
3285 // pc-relative offset may not be large enough to hold the whole
3287 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3288 // If the callee is a GlobalAddress node (quite common, every direct call
3289 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3291 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3293 // We should use extra load for direct calls to dllimported functions in
3295 const GlobalValue *GV = G->getGlobal();
3296 if (!GV->hasDLLImportStorageClass()) {
3297 unsigned char OpFlags = 0;
3298 bool ExtraLoad = false;
3299 unsigned WrapperKind = ISD::DELETED_NODE;
3301 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3302 // external symbols most go through the PLT in PIC mode. If the symbol
3303 // has hidden or protected visibility, or if it is static or local, then
3304 // we don't need to use the PLT - we can directly call it.
3305 if (Subtarget->isTargetELF() &&
3306 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3307 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3308 OpFlags = X86II::MO_PLT;
3309 } else if (Subtarget->isPICStyleStubAny() &&
3310 !GV->isStrongDefinitionForLinker() &&
3311 (!Subtarget->getTargetTriple().isMacOSX() ||
3312 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3313 // PC-relative references to external symbols should go through $stub,
3314 // unless we're building with the leopard linker or later, which
3315 // automatically synthesizes these stubs.
3316 OpFlags = X86II::MO_DARWIN_STUB;
3317 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3318 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3319 // If the function is marked as non-lazy, generate an indirect call
3320 // which loads from the GOT directly. This avoids runtime overhead
3321 // at the cost of eager binding (and one extra byte of encoding).
3322 OpFlags = X86II::MO_GOTPCREL;
3323 WrapperKind = X86ISD::WrapperRIP;
3327 Callee = DAG.getTargetGlobalAddress(
3328 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3330 // Add a wrapper if needed.
3331 if (WrapperKind != ISD::DELETED_NODE)
3332 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3333 getPointerTy(DAG.getDataLayout()), Callee);
3334 // Add extra indirection if needed.
3336 Callee = DAG.getLoad(
3337 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3338 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3341 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3342 unsigned char OpFlags = 0;
3344 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3345 // external symbols should go through the PLT.
3346 if (Subtarget->isTargetELF() &&
3347 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3348 OpFlags = X86II::MO_PLT;
3349 } else if (Subtarget->isPICStyleStubAny() &&
3350 (!Subtarget->getTargetTriple().isMacOSX() ||
3351 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3352 // PC-relative references to external symbols should go through $stub,
3353 // unless we're building with the leopard linker or later, which
3354 // automatically synthesizes these stubs.
3355 OpFlags = X86II::MO_DARWIN_STUB;
3358 Callee = DAG.getTargetExternalSymbol(
3359 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3360 } else if (Subtarget->isTarget64BitILP32() &&
3361 Callee->getValueType(0) == MVT::i32) {
3362 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3363 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3366 // Returns a chain & a flag for retval copy to use.
3367 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3368 SmallVector<SDValue, 8> Ops;
3370 if (!IsSibcall && isTailCall) {
3371 Chain = DAG.getCALLSEQ_END(Chain,
3372 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3373 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3374 InFlag = Chain.getValue(1);
3377 Ops.push_back(Chain);
3378 Ops.push_back(Callee);
3381 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3383 // Add argument registers to the end of the list so that they are known live
3385 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3386 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3387 RegsToPass[i].second.getValueType()));
3389 // Add a register mask operand representing the call-preserved registers.
3390 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3391 assert(Mask && "Missing call preserved mask for calling convention");
3393 // If this is an invoke in a 32-bit function using an MSVC personality, assume
3394 // the function clobbers all registers. If an exception is thrown, the runtime
3395 // will not restore CSRs.
3396 // FIXME: Model this more precisely so that we can register allocate across
3397 // the normal edge and spill and fill across the exceptional edge.
3398 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3399 const Function *CallerFn = MF.getFunction();
3400 EHPersonality Pers =
3401 CallerFn->hasPersonalityFn()
3402 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3403 : EHPersonality::Unknown;
3404 if (isMSVCEHPersonality(Pers))
3405 Mask = RegInfo->getNoPreservedMask();
3408 Ops.push_back(DAG.getRegisterMask(Mask));
3410 if (InFlag.getNode())
3411 Ops.push_back(InFlag);
3415 //// If this is the first return lowered for this function, add the regs
3416 //// to the liveout set for the function.
3417 // This isn't right, although it's probably harmless on x86; liveouts
3418 // should be computed from returns not tail calls. Consider a void
3419 // function making a tail call to a function returning int.
3420 MF.getFrameInfo()->setHasTailCall();
3421 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3424 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3425 InFlag = Chain.getValue(1);
3427 // Create the CALLSEQ_END node.
3428 unsigned NumBytesForCalleeToPop;
3429 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3430 DAG.getTarget().Options.GuaranteedTailCallOpt))
3431 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3432 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3433 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3434 SR == StackStructReturn)
3435 // If this is a call to a struct-return function, the callee
3436 // pops the hidden struct pointer, so we have to push it back.
3437 // This is common for Darwin/X86, Linux & Mingw32 targets.
3438 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3439 NumBytesForCalleeToPop = 4;
3441 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3443 // Returns a flag for retval copy to use.
3445 Chain = DAG.getCALLSEQ_END(Chain,
3446 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3447 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3450 InFlag = Chain.getValue(1);
3453 // Handle result values, copying them out of physregs into vregs that we
3455 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3456 Ins, dl, DAG, InVals);
3459 //===----------------------------------------------------------------------===//
3460 // Fast Calling Convention (tail call) implementation
3461 //===----------------------------------------------------------------------===//
3463 // Like std call, callee cleans arguments, convention except that ECX is
3464 // reserved for storing the tail called function address. Only 2 registers are
3465 // free for argument passing (inreg). Tail call optimization is performed
3467 // * tailcallopt is enabled
3468 // * caller/callee are fastcc
3469 // On X86_64 architecture with GOT-style position independent code only local
3470 // (within module) calls are supported at the moment.
3471 // To keep the stack aligned according to platform abi the function
3472 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3473 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3474 // If a tail called function callee has more arguments than the caller the
3475 // caller needs to make sure that there is room to move the RETADDR to. This is
3476 // achieved by reserving an area the size of the argument delta right after the
3477 // original RETADDR, but before the saved framepointer or the spilled registers
3478 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3490 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3493 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3494 SelectionDAG& DAG) const {
3495 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3496 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3497 unsigned StackAlignment = TFI.getStackAlignment();
3498 uint64_t AlignMask = StackAlignment - 1;
3499 int64_t Offset = StackSize;
3500 unsigned SlotSize = RegInfo->getSlotSize();
3501 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3502 // Number smaller than 12 so just add the difference.
3503 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3505 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3506 Offset = ((~AlignMask) & Offset) + StackAlignment +
3507 (StackAlignment-SlotSize);
3512 /// Return true if the given stack call argument is already available in the
3513 /// same position (relatively) of the caller's incoming argument stack.
3515 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3516 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3517 const X86InstrInfo *TII) {
3518 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3520 if (Arg.getOpcode() == ISD::CopyFromReg) {
3521 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3522 if (!TargetRegisterInfo::isVirtualRegister(VR))
3524 MachineInstr *Def = MRI->getVRegDef(VR);
3527 if (!Flags.isByVal()) {
3528 if (!TII->isLoadFromStackSlot(Def, FI))
3531 unsigned Opcode = Def->getOpcode();
3532 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3533 Opcode == X86::LEA64_32r) &&
3534 Def->getOperand(1).isFI()) {
3535 FI = Def->getOperand(1).getIndex();
3536 Bytes = Flags.getByValSize();
3540 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3541 if (Flags.isByVal())
3542 // ByVal argument is passed in as a pointer but it's now being
3543 // dereferenced. e.g.
3544 // define @foo(%struct.X* %A) {
3545 // tail call @bar(%struct.X* byval %A)
3548 SDValue Ptr = Ld->getBasePtr();
3549 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3552 FI = FINode->getIndex();
3553 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3554 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3555 FI = FINode->getIndex();
3556 Bytes = Flags.getByValSize();
3560 assert(FI != INT_MAX);
3561 if (!MFI->isFixedObjectIndex(FI))
3563 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3566 /// Check whether the call is eligible for tail call optimization. Targets
3567 /// that want to do tail call optimization should implement this function.
3568 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3569 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3570 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3571 const SmallVectorImpl<ISD::OutputArg> &Outs,
3572 const SmallVectorImpl<SDValue> &OutVals,
3573 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3574 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3577 // If -tailcallopt is specified, make fastcc functions tail-callable.
3578 const MachineFunction &MF = DAG.getMachineFunction();
3579 const Function *CallerF = MF.getFunction();
3581 // If the function return type is x86_fp80 and the callee return type is not,
3582 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3583 // perform a tailcall optimization here.
3584 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3587 CallingConv::ID CallerCC = CallerF->getCallingConv();
3588 bool CCMatch = CallerCC == CalleeCC;
3589 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3590 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3592 // Win64 functions have extra shadow space for argument homing. Don't do the
3593 // sibcall if the caller and callee have mismatched expectations for this
3595 if (IsCalleeWin64 != IsCallerWin64)
3598 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3599 if (IsTailCallConvention(CalleeCC) && CCMatch)
3604 // Look for obvious safe cases to perform tail call optimization that do not
3605 // require ABI changes. This is what gcc calls sibcall.
3607 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3608 // emit a special epilogue.
3609 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3610 if (RegInfo->needsStackRealignment(MF))
3613 // Also avoid sibcall optimization if either caller or callee uses struct
3614 // return semantics.
3615 if (isCalleeStructRet || isCallerStructRet)
3618 // An stdcall/thiscall caller is expected to clean up its arguments; the
3619 // callee isn't going to do that.
3620 // FIXME: this is more restrictive than needed. We could produce a tailcall
3621 // when the stack adjustment matches. For example, with a thiscall that takes
3622 // only one argument.
3623 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3624 CallerCC == CallingConv::X86_ThisCall))
3627 // Do not sibcall optimize vararg calls unless all arguments are passed via
3629 if (isVarArg && !Outs.empty()) {
3631 // Optimizing for varargs on Win64 is unlikely to be safe without
3632 // additional testing.
3633 if (IsCalleeWin64 || IsCallerWin64)
3636 SmallVector<CCValAssign, 16> ArgLocs;
3637 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3640 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3641 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3642 if (!ArgLocs[i].isRegLoc())
3646 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3647 // stack. Therefore, if it's not used by the call it is not safe to optimize
3648 // this into a sibcall.
3649 bool Unused = false;
3650 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3657 SmallVector<CCValAssign, 16> RVLocs;
3658 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3660 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3661 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3662 CCValAssign &VA = RVLocs[i];
3663 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3668 // If the calling conventions do not match, then we'd better make sure the
3669 // results are returned in the same way as what the caller expects.
3671 SmallVector<CCValAssign, 16> RVLocs1;
3672 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3674 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3676 SmallVector<CCValAssign, 16> RVLocs2;
3677 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3679 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3681 if (RVLocs1.size() != RVLocs2.size())
3683 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3684 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3686 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3688 if (RVLocs1[i].isRegLoc()) {
3689 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3692 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3698 // If the callee takes no arguments then go on to check the results of the
3700 if (!Outs.empty()) {
3701 // Check if stack adjustment is needed. For now, do not do this if any
3702 // argument is passed on the stack.
3703 SmallVector<CCValAssign, 16> ArgLocs;
3704 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3707 // Allocate shadow area for Win64
3709 CCInfo.AllocateStack(32, 8);
3711 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3712 if (CCInfo.getNextStackOffset()) {
3713 MachineFunction &MF = DAG.getMachineFunction();
3714 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3717 // Check if the arguments are already laid out in the right way as
3718 // the caller's fixed stack objects.
3719 MachineFrameInfo *MFI = MF.getFrameInfo();
3720 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3721 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3723 CCValAssign &VA = ArgLocs[i];
3724 SDValue Arg = OutVals[i];
3725 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3726 if (VA.getLocInfo() == CCValAssign::Indirect)
3728 if (!VA.isRegLoc()) {
3729 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3736 // If the tailcall address may be in a register, then make sure it's
3737 // possible to register allocate for it. In 32-bit, the call address can
3738 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3739 // callee-saved registers are restored. These happen to be the same
3740 // registers used to pass 'inreg' arguments so watch out for those.
3741 if (!Subtarget->is64Bit() &&
3742 ((!isa<GlobalAddressSDNode>(Callee) &&
3743 !isa<ExternalSymbolSDNode>(Callee)) ||
3744 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3745 unsigned NumInRegs = 0;
3746 // In PIC we need an extra register to formulate the address computation
3748 unsigned MaxInRegs =
3749 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3751 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3752 CCValAssign &VA = ArgLocs[i];
3755 unsigned Reg = VA.getLocReg();
3758 case X86::EAX: case X86::EDX: case X86::ECX:
3759 if (++NumInRegs == MaxInRegs)
3771 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3772 const TargetLibraryInfo *libInfo) const {
3773 return X86::createFastISel(funcInfo, libInfo);
3776 //===----------------------------------------------------------------------===//
3777 // Other Lowering Hooks
3778 //===----------------------------------------------------------------------===//
3780 static bool MayFoldLoad(SDValue Op) {
3781 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3784 static bool MayFoldIntoStore(SDValue Op) {
3785 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3788 static bool isTargetShuffle(unsigned Opcode) {
3790 default: return false;
3791 case X86ISD::BLENDI:
3792 case X86ISD::PSHUFB:
3793 case X86ISD::PSHUFD:
3794 case X86ISD::PSHUFHW:
3795 case X86ISD::PSHUFLW:
3797 case X86ISD::PALIGNR:
3798 case X86ISD::MOVLHPS:
3799 case X86ISD::MOVLHPD:
3800 case X86ISD::MOVHLPS:
3801 case X86ISD::MOVLPS:
3802 case X86ISD::MOVLPD:
3803 case X86ISD::MOVSHDUP:
3804 case X86ISD::MOVSLDUP:
3805 case X86ISD::MOVDDUP:
3808 case X86ISD::UNPCKL:
3809 case X86ISD::UNPCKH:
3810 case X86ISD::VPERMILPI:
3811 case X86ISD::VPERM2X128:
3812 case X86ISD::VPERMI:
3813 case X86ISD::VPERMV:
3814 case X86ISD::VPERMV3:
3819 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3820 SDValue V1, unsigned TargetMask,
3821 SelectionDAG &DAG) {
3823 default: llvm_unreachable("Unknown x86 shuffle node");
3824 case X86ISD::PSHUFD:
3825 case X86ISD::PSHUFHW:
3826 case X86ISD::PSHUFLW:
3827 case X86ISD::VPERMILPI:
3828 case X86ISD::VPERMI:
3829 return DAG.getNode(Opc, dl, VT, V1,
3830 DAG.getConstant(TargetMask, dl, MVT::i8));
3834 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3835 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3837 default: llvm_unreachable("Unknown x86 shuffle node");
3838 case X86ISD::MOVLHPS:
3839 case X86ISD::MOVLHPD:
3840 case X86ISD::MOVHLPS:
3841 case X86ISD::MOVLPS:
3842 case X86ISD::MOVLPD:
3845 case X86ISD::UNPCKL:
3846 case X86ISD::UNPCKH:
3847 return DAG.getNode(Opc, dl, VT, V1, V2);
3851 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3852 MachineFunction &MF = DAG.getMachineFunction();
3853 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3854 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3855 int ReturnAddrIndex = FuncInfo->getRAIndex();
3857 if (ReturnAddrIndex == 0) {
3858 // Set up a frame object for the return address.
3859 unsigned SlotSize = RegInfo->getSlotSize();
3860 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3863 FuncInfo->setRAIndex(ReturnAddrIndex);
3866 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3869 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3870 bool hasSymbolicDisplacement) {
3871 // Offset should fit into 32 bit immediate field.
3872 if (!isInt<32>(Offset))
3875 // If we don't have a symbolic displacement - we don't have any extra
3877 if (!hasSymbolicDisplacement)
3880 // FIXME: Some tweaks might be needed for medium code model.
3881 if (M != CodeModel::Small && M != CodeModel::Kernel)
3884 // For small code model we assume that latest object is 16MB before end of 31
3885 // bits boundary. We may also accept pretty large negative constants knowing
3886 // that all objects are in the positive half of address space.
3887 if (M == CodeModel::Small && Offset < 16*1024*1024)
3890 // For kernel code model we know that all object resist in the negative half
3891 // of 32bits address space. We may not accept negative offsets, since they may
3892 // be just off and we may accept pretty large positive ones.
3893 if (M == CodeModel::Kernel && Offset >= 0)
3899 /// Determines whether the callee is required to pop its own arguments.
3900 /// Callee pop is necessary to support tail calls.
3901 bool X86::isCalleePop(CallingConv::ID CallingConv,
3902 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3903 switch (CallingConv) {
3906 case CallingConv::X86_StdCall:
3907 case CallingConv::X86_FastCall:
3908 case CallingConv::X86_ThisCall:
3910 case CallingConv::Fast:
3911 case CallingConv::GHC:
3912 case CallingConv::HiPE:
3919 /// \brief Return true if the condition is an unsigned comparison operation.
3920 static bool isX86CCUnsigned(unsigned X86CC) {
3922 default: llvm_unreachable("Invalid integer condition!");
3923 case X86::COND_E: return true;
3924 case X86::COND_G: return false;
3925 case X86::COND_GE: return false;
3926 case X86::COND_L: return false;
3927 case X86::COND_LE: return false;
3928 case X86::COND_NE: return true;
3929 case X86::COND_B: return true;
3930 case X86::COND_A: return true;
3931 case X86::COND_BE: return true;
3932 case X86::COND_AE: return true;
3934 llvm_unreachable("covered switch fell through?!");
3937 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3938 /// condition code, returning the condition code and the LHS/RHS of the
3939 /// comparison to make.
3940 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3941 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3943 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3944 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3945 // X > -1 -> X == 0, jump !sign.
3946 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3947 return X86::COND_NS;
3949 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3950 // X < 0 -> X == 0, jump on sign.
3953 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3955 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3956 return X86::COND_LE;
3960 switch (SetCCOpcode) {
3961 default: llvm_unreachable("Invalid integer condition!");
3962 case ISD::SETEQ: return X86::COND_E;
3963 case ISD::SETGT: return X86::COND_G;
3964 case ISD::SETGE: return X86::COND_GE;
3965 case ISD::SETLT: return X86::COND_L;
3966 case ISD::SETLE: return X86::COND_LE;
3967 case ISD::SETNE: return X86::COND_NE;
3968 case ISD::SETULT: return X86::COND_B;
3969 case ISD::SETUGT: return X86::COND_A;
3970 case ISD::SETULE: return X86::COND_BE;
3971 case ISD::SETUGE: return X86::COND_AE;
3975 // First determine if it is required or is profitable to flip the operands.
3977 // If LHS is a foldable load, but RHS is not, flip the condition.
3978 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3979 !ISD::isNON_EXTLoad(RHS.getNode())) {
3980 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3981 std::swap(LHS, RHS);
3984 switch (SetCCOpcode) {
3990 std::swap(LHS, RHS);
3994 // On a floating point condition, the flags are set as follows:
3996 // 0 | 0 | 0 | X > Y
3997 // 0 | 0 | 1 | X < Y
3998 // 1 | 0 | 0 | X == Y
3999 // 1 | 1 | 1 | unordered
4000 switch (SetCCOpcode) {
4001 default: llvm_unreachable("Condcode should be pre-legalized away");
4003 case ISD::SETEQ: return X86::COND_E;
4004 case ISD::SETOLT: // flipped
4006 case ISD::SETGT: return X86::COND_A;
4007 case ISD::SETOLE: // flipped
4009 case ISD::SETGE: return X86::COND_AE;
4010 case ISD::SETUGT: // flipped
4012 case ISD::SETLT: return X86::COND_B;
4013 case ISD::SETUGE: // flipped
4015 case ISD::SETLE: return X86::COND_BE;
4017 case ISD::SETNE: return X86::COND_NE;
4018 case ISD::SETUO: return X86::COND_P;
4019 case ISD::SETO: return X86::COND_NP;
4021 case ISD::SETUNE: return X86::COND_INVALID;
4025 /// Is there a floating point cmov for the specific X86 condition code?
4026 /// Current x86 isa includes the following FP cmov instructions:
4027 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4028 static bool hasFPCMov(unsigned X86CC) {
4044 /// Returns true if the target can instruction select the
4045 /// specified FP immediate natively. If false, the legalizer will
4046 /// materialize the FP immediate as a load from a constant pool.
4047 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4048 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4049 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4055 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4056 ISD::LoadExtType ExtTy,
4058 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4059 // relocation target a movq or addq instruction: don't let the load shrink.
4060 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4061 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4062 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4063 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4067 /// \brief Returns true if it is beneficial to convert a load of a constant
4068 /// to just the constant itself.
4069 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4071 assert(Ty->isIntegerTy());
4073 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4074 if (BitSize == 0 || BitSize > 64)
4079 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4080 unsigned Index) const {
4081 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4084 return (Index == 0 || Index == ResVT.getVectorNumElements());
4087 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4088 // Speculate cttz only if we can directly use TZCNT.
4089 return Subtarget->hasBMI();
4092 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4093 // Speculate ctlz only if we can directly use LZCNT.
4094 return Subtarget->hasLZCNT();
4097 /// Return true if every element in Mask, beginning
4098 /// from position Pos and ending in Pos+Size is undef.
4099 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4100 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4106 /// Return true if Val is undef or if its value falls within the
4107 /// specified range (L, H].
4108 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4109 return (Val < 0) || (Val >= Low && Val < Hi);
4112 /// Val is either less than zero (undef) or equal to the specified value.
4113 static bool isUndefOrEqual(int Val, int CmpVal) {
4114 return (Val < 0 || Val == CmpVal);
4117 /// Return true if every element in Mask, beginning
4118 /// from position Pos and ending in Pos+Size, falls within the specified
4119 /// sequential range (Low, Low+Size]. or is undef.
4120 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4121 unsigned Pos, unsigned Size, int Low) {
4122 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4123 if (!isUndefOrEqual(Mask[i], Low))
4128 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4129 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4130 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4131 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4132 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4135 // The index should be aligned on a vecWidth-bit boundary.
4137 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4139 MVT VT = N->getSimpleValueType(0);
4140 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4141 bool Result = (Index * ElSize) % vecWidth == 0;
4146 /// Return true if the specified INSERT_SUBVECTOR
4147 /// operand specifies a subvector insert that is suitable for input to
4148 /// insertion of 128 or 256-bit subvectors
4149 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4150 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4151 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4153 // The index should be aligned on a vecWidth-bit boundary.
4155 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4157 MVT VT = N->getSimpleValueType(0);
4158 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4159 bool Result = (Index * ElSize) % vecWidth == 0;
4164 bool X86::isVINSERT128Index(SDNode *N) {
4165 return isVINSERTIndex(N, 128);
4168 bool X86::isVINSERT256Index(SDNode *N) {
4169 return isVINSERTIndex(N, 256);
4172 bool X86::isVEXTRACT128Index(SDNode *N) {
4173 return isVEXTRACTIndex(N, 128);
4176 bool X86::isVEXTRACT256Index(SDNode *N) {
4177 return isVEXTRACTIndex(N, 256);
4180 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4181 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4182 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4183 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4186 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4188 MVT VecVT = N->getOperand(0).getSimpleValueType();
4189 MVT ElVT = VecVT.getVectorElementType();
4191 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4192 return Index / NumElemsPerChunk;
4195 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4196 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4197 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4198 llvm_unreachable("Illegal insert subvector for VINSERT");
4201 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4203 MVT VecVT = N->getSimpleValueType(0);
4204 MVT ElVT = VecVT.getVectorElementType();
4206 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4207 return Index / NumElemsPerChunk;
4210 /// Return the appropriate immediate to extract the specified
4211 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4212 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4213 return getExtractVEXTRACTImmediate(N, 128);
4216 /// Return the appropriate immediate to extract the specified
4217 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4218 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4219 return getExtractVEXTRACTImmediate(N, 256);
4222 /// Return the appropriate immediate to insert at the specified
4223 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4224 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4225 return getInsertVINSERTImmediate(N, 128);
4228 /// Return the appropriate immediate to insert at the specified
4229 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4230 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4231 return getInsertVINSERTImmediate(N, 256);
4234 /// Returns true if Elt is a constant integer zero
4235 static bool isZero(SDValue V) {
4236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4237 return C && C->isNullValue();
4240 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4241 bool X86::isZeroNode(SDValue Elt) {
4244 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4245 return CFP->getValueAPF().isPosZero();
4249 /// Returns a vector of specified type with all zero elements.
4250 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4251 SelectionDAG &DAG, SDLoc dl) {
4252 assert(VT.isVector() && "Expected a vector type");
4254 // Always build SSE zero vectors as <4 x i32> bitcasted
4255 // to their dest type. This ensures they get CSE'd.
4257 if (VT.is128BitVector()) { // SSE
4258 if (Subtarget->hasSSE2()) { // SSE2
4259 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4260 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4262 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4263 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4265 } else if (VT.is256BitVector()) { // AVX
4266 if (Subtarget->hasInt256()) { // AVX2
4267 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4268 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4271 // 256-bit logic and arithmetic instructions in AVX are all
4272 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4273 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4274 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4275 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4277 } else if (VT.is512BitVector()) { // AVX-512
4278 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4279 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4280 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4281 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4282 } else if (VT.getScalarType() == MVT::i1) {
4284 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4285 && "Unexpected vector type");
4286 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4287 && "Unexpected vector type");
4288 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4289 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4290 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4292 llvm_unreachable("Unexpected vector type");
4294 return DAG.getBitcast(VT, Vec);
4297 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4298 SelectionDAG &DAG, SDLoc dl,
4299 unsigned vectorWidth) {
4300 assert((vectorWidth == 128 || vectorWidth == 256) &&
4301 "Unsupported vector width");
4302 EVT VT = Vec.getValueType();
4303 EVT ElVT = VT.getVectorElementType();
4304 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4305 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4306 VT.getVectorNumElements()/Factor);
4308 // Extract from UNDEF is UNDEF.
4309 if (Vec.getOpcode() == ISD::UNDEF)
4310 return DAG.getUNDEF(ResultVT);
4312 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4313 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4315 // This is the index of the first element of the vectorWidth-bit chunk
4317 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4320 // If the input is a buildvector just emit a smaller one.
4321 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4322 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4323 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4326 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4327 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4330 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4331 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4332 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4333 /// instructions or a simple subregister reference. Idx is an index in the
4334 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4335 /// lowering EXTRACT_VECTOR_ELT operations easier.
4336 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4337 SelectionDAG &DAG, SDLoc dl) {
4338 assert((Vec.getValueType().is256BitVector() ||
4339 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4340 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4343 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4344 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4345 SelectionDAG &DAG, SDLoc dl) {
4346 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4347 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4350 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4351 unsigned IdxVal, SelectionDAG &DAG,
4352 SDLoc dl, unsigned vectorWidth) {
4353 assert((vectorWidth == 128 || vectorWidth == 256) &&
4354 "Unsupported vector width");
4355 // Inserting UNDEF is Result
4356 if (Vec.getOpcode() == ISD::UNDEF)
4358 EVT VT = Vec.getValueType();
4359 EVT ElVT = VT.getVectorElementType();
4360 EVT ResultVT = Result.getValueType();
4362 // Insert the relevant vectorWidth bits.
4363 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4365 // This is the index of the first element of the vectorWidth-bit chunk
4367 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4370 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4371 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4374 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4375 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4376 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4377 /// simple superregister reference. Idx is an index in the 128 bits
4378 /// we want. It need not be aligned to a 128-bit boundary. That makes
4379 /// lowering INSERT_VECTOR_ELT operations easier.
4380 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4381 SelectionDAG &DAG, SDLoc dl) {
4382 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4384 // For insertion into the zero index (low half) of a 256-bit vector, it is
4385 // more efficient to generate a blend with immediate instead of an insert*128.
4386 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4387 // extend the subvector to the size of the result vector. Make sure that
4388 // we are not recursing on that node by checking for undef here.
4389 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4390 Result.getOpcode() != ISD::UNDEF) {
4391 EVT ResultVT = Result.getValueType();
4392 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4393 SDValue Undef = DAG.getUNDEF(ResultVT);
4394 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4397 // The blend instruction, and therefore its mask, depend on the data type.
4398 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4399 if (ScalarType.isFloatingPoint()) {
4400 // Choose either vblendps (float) or vblendpd (double).
4401 unsigned ScalarSize = ScalarType.getSizeInBits();
4402 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4403 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4404 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4405 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4408 const X86Subtarget &Subtarget =
4409 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4411 // AVX2 is needed for 256-bit integer blend support.
4412 // Integers must be cast to 32-bit because there is only vpblendd;
4413 // vpblendw can't be used for this because it has a handicapped mask.
4415 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4416 // is still more efficient than using the wrong domain vinsertf128 that
4417 // will be created by InsertSubVector().
4418 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4420 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4421 Vec256 = DAG.getBitcast(CastVT, Vec256);
4422 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4423 return DAG.getBitcast(ResultVT, Vec256);
4426 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4429 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4430 SelectionDAG &DAG, SDLoc dl) {
4431 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4432 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4435 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4436 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4437 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4438 /// large BUILD_VECTORS.
4439 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4440 unsigned NumElems, SelectionDAG &DAG,
4442 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4443 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4446 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4447 unsigned NumElems, SelectionDAG &DAG,
4449 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4450 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4453 /// Returns a vector of specified type with all bits set.
4454 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4455 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4456 /// Then bitcast to their original type, ensuring they get CSE'd.
4457 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4458 SelectionDAG &DAG, SDLoc dl) {
4459 assert(VT.isVector() && "Expected a vector type");
4461 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4463 if (VT.is512BitVector()) {
4464 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4465 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4466 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4467 } else if (VT.is256BitVector()) {
4468 if (Subtarget->hasInt256()) { // AVX2
4469 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4470 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4472 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4473 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4475 } else if (VT.is128BitVector()) {
4476 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4478 llvm_unreachable("Unexpected vector type");
4480 return DAG.getBitcast(VT, Vec);
4483 /// Returns a vector_shuffle node for an unpackl operation.
4484 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4486 unsigned NumElems = VT.getVectorNumElements();
4487 SmallVector<int, 8> Mask;
4488 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4490 Mask.push_back(i + NumElems);
4492 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4495 /// Returns a vector_shuffle node for an unpackh operation.
4496 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4498 unsigned NumElems = VT.getVectorNumElements();
4499 SmallVector<int, 8> Mask;
4500 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4501 Mask.push_back(i + Half);
4502 Mask.push_back(i + NumElems + Half);
4504 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4507 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4508 /// This produces a shuffle where the low element of V2 is swizzled into the
4509 /// zero/undef vector, landing at element Idx.
4510 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4511 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4513 const X86Subtarget *Subtarget,
4514 SelectionDAG &DAG) {
4515 MVT VT = V2.getSimpleValueType();
4517 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4518 unsigned NumElems = VT.getVectorNumElements();
4519 SmallVector<int, 16> MaskVec;
4520 for (unsigned i = 0; i != NumElems; ++i)
4521 // If this is the insertion idx, put the low elt of V2 here.
4522 MaskVec.push_back(i == Idx ? NumElems : i);
4523 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4526 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4527 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4528 /// uses one source. Note that this will set IsUnary for shuffles which use a
4529 /// single input multiple times, and in those cases it will
4530 /// adjust the mask to only have indices within that single input.
4531 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4532 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4533 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4534 unsigned NumElems = VT.getVectorNumElements();
4538 bool IsFakeUnary = false;
4539 switch(N->getOpcode()) {
4540 case X86ISD::BLENDI:
4541 ImmN = N->getOperand(N->getNumOperands()-1);
4542 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4545 ImmN = N->getOperand(N->getNumOperands()-1);
4546 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4547 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4549 case X86ISD::UNPCKH:
4550 DecodeUNPCKHMask(VT, Mask);
4551 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4553 case X86ISD::UNPCKL:
4554 DecodeUNPCKLMask(VT, Mask);
4555 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4557 case X86ISD::MOVHLPS:
4558 DecodeMOVHLPSMask(NumElems, Mask);
4559 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4561 case X86ISD::MOVLHPS:
4562 DecodeMOVLHPSMask(NumElems, Mask);
4563 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4565 case X86ISD::PALIGNR:
4566 ImmN = N->getOperand(N->getNumOperands()-1);
4567 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4569 case X86ISD::PSHUFD:
4570 case X86ISD::VPERMILPI:
4571 ImmN = N->getOperand(N->getNumOperands()-1);
4572 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4575 case X86ISD::PSHUFHW:
4576 ImmN = N->getOperand(N->getNumOperands()-1);
4577 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4580 case X86ISD::PSHUFLW:
4581 ImmN = N->getOperand(N->getNumOperands()-1);
4582 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4585 case X86ISD::PSHUFB: {
4587 SDValue MaskNode = N->getOperand(1);
4588 while (MaskNode->getOpcode() == ISD::BITCAST)
4589 MaskNode = MaskNode->getOperand(0);
4591 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4592 // If we have a build-vector, then things are easy.
4593 EVT VT = MaskNode.getValueType();
4594 assert(VT.isVector() &&
4595 "Can't produce a non-vector with a build_vector!");
4596 if (!VT.isInteger())
4599 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4601 SmallVector<uint64_t, 32> RawMask;
4602 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4603 SDValue Op = MaskNode->getOperand(i);
4604 if (Op->getOpcode() == ISD::UNDEF) {
4605 RawMask.push_back((uint64_t)SM_SentinelUndef);
4608 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4611 APInt MaskElement = CN->getAPIntValue();
4613 // We now have to decode the element which could be any integer size and
4614 // extract each byte of it.
4615 for (int j = 0; j < NumBytesPerElement; ++j) {
4616 // Note that this is x86 and so always little endian: the low byte is
4617 // the first byte of the mask.
4618 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4619 MaskElement = MaskElement.lshr(8);
4622 DecodePSHUFBMask(RawMask, Mask);
4626 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4630 SDValue Ptr = MaskLoad->getBasePtr();
4631 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4632 Ptr->getOpcode() == X86ISD::WrapperRIP)
4633 Ptr = Ptr->getOperand(0);
4635 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4636 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4639 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4640 DecodePSHUFBMask(C, Mask);
4648 case X86ISD::VPERMI:
4649 ImmN = N->getOperand(N->getNumOperands()-1);
4650 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4655 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4657 case X86ISD::VPERM2X128:
4658 ImmN = N->getOperand(N->getNumOperands()-1);
4659 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4660 if (Mask.empty()) return false;
4661 // Mask only contains negative index if an element is zero.
4662 if (std::any_of(Mask.begin(), Mask.end(),
4663 [](int M){ return M == SM_SentinelZero; }))
4666 case X86ISD::MOVSLDUP:
4667 DecodeMOVSLDUPMask(VT, Mask);
4670 case X86ISD::MOVSHDUP:
4671 DecodeMOVSHDUPMask(VT, Mask);
4674 case X86ISD::MOVDDUP:
4675 DecodeMOVDDUPMask(VT, Mask);
4678 case X86ISD::MOVLHPD:
4679 case X86ISD::MOVLPD:
4680 case X86ISD::MOVLPS:
4681 // Not yet implemented
4683 case X86ISD::VPERMV: {
4685 SDValue MaskNode = N->getOperand(0);
4686 while (MaskNode->getOpcode() == ISD::BITCAST)
4687 MaskNode = MaskNode->getOperand(0);
4689 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4690 SmallVector<uint64_t, 32> RawMask;
4691 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4692 // If we have a build-vector, then things are easy.
4693 assert(MaskNode.getValueType().isInteger() &&
4694 MaskNode.getValueType().getVectorNumElements() ==
4695 VT.getVectorNumElements());
4697 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4698 SDValue Op = MaskNode->getOperand(i);
4699 if (Op->getOpcode() == ISD::UNDEF)
4700 RawMask.push_back((uint64_t)SM_SentinelUndef);
4701 else if (isa<ConstantSDNode>(Op)) {
4702 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4703 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4707 DecodeVPERMVMask(RawMask, Mask);
4710 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4711 unsigned NumEltsInMask = MaskNode->getNumOperands();
4712 MaskNode = MaskNode->getOperand(0);
4713 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4715 APInt MaskEltValue = CN->getAPIntValue();
4716 for (unsigned i = 0; i < NumEltsInMask; ++i)
4717 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4718 DecodeVPERMVMask(RawMask, Mask);
4721 // It may be a scalar load
4724 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4728 SDValue Ptr = MaskLoad->getBasePtr();
4729 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4730 Ptr->getOpcode() == X86ISD::WrapperRIP)
4731 Ptr = Ptr->getOperand(0);
4733 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4734 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4737 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4739 DecodeVPERMVMask(C, VT, Mask);
4746 case X86ISD::VPERMV3: {
4748 SDValue MaskNode = N->getOperand(1);
4749 while (MaskNode->getOpcode() == ISD::BITCAST)
4750 MaskNode = MaskNode->getOperand(1);
4752 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4753 // If we have a build-vector, then things are easy.
4754 assert(MaskNode.getValueType().isInteger() &&
4755 MaskNode.getValueType().getVectorNumElements() ==
4756 VT.getVectorNumElements());
4758 SmallVector<uint64_t, 32> RawMask;
4759 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4761 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4762 SDValue Op = MaskNode->getOperand(i);
4763 if (Op->getOpcode() == ISD::UNDEF)
4764 RawMask.push_back((uint64_t)SM_SentinelUndef);
4766 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4769 APInt MaskElement = CN->getAPIntValue();
4770 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4773 DecodeVPERMV3Mask(RawMask, Mask);
4777 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4781 SDValue Ptr = MaskLoad->getBasePtr();
4782 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4783 Ptr->getOpcode() == X86ISD::WrapperRIP)
4784 Ptr = Ptr->getOperand(0);
4786 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4787 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4790 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4792 DecodeVPERMV3Mask(C, VT, Mask);
4799 default: llvm_unreachable("unknown target shuffle node");
4802 // If we have a fake unary shuffle, the shuffle mask is spread across two
4803 // inputs that are actually the same node. Re-map the mask to always point
4804 // into the first input.
4807 if (M >= (int)Mask.size())
4813 /// Returns the scalar element that will make up the ith
4814 /// element of the result of the vector shuffle.
4815 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4818 return SDValue(); // Limit search depth.
4820 SDValue V = SDValue(N, 0);
4821 EVT VT = V.getValueType();
4822 unsigned Opcode = V.getOpcode();
4824 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4825 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4826 int Elt = SV->getMaskElt(Index);
4829 return DAG.getUNDEF(VT.getVectorElementType());
4831 unsigned NumElems = VT.getVectorNumElements();
4832 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4833 : SV->getOperand(1);
4834 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4837 // Recurse into target specific vector shuffles to find scalars.
4838 if (isTargetShuffle(Opcode)) {
4839 MVT ShufVT = V.getSimpleValueType();
4840 unsigned NumElems = ShufVT.getVectorNumElements();
4841 SmallVector<int, 16> ShuffleMask;
4844 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4847 int Elt = ShuffleMask[Index];
4849 return DAG.getUNDEF(ShufVT.getVectorElementType());
4851 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4853 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4857 // Actual nodes that may contain scalar elements
4858 if (Opcode == ISD::BITCAST) {
4859 V = V.getOperand(0);
4860 EVT SrcVT = V.getValueType();
4861 unsigned NumElems = VT.getVectorNumElements();
4863 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4867 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4868 return (Index == 0) ? V.getOperand(0)
4869 : DAG.getUNDEF(VT.getVectorElementType());
4871 if (V.getOpcode() == ISD::BUILD_VECTOR)
4872 return V.getOperand(Index);
4877 /// Custom lower build_vector of v16i8.
4878 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4879 unsigned NumNonZero, unsigned NumZero,
4881 const X86Subtarget* Subtarget,
4882 const TargetLowering &TLI) {
4890 // SSE4.1 - use PINSRB to insert each byte directly.
4891 if (Subtarget->hasSSE41()) {
4892 for (unsigned i = 0; i < 16; ++i) {
4893 bool isNonZero = (NonZeros & (1 << i)) != 0;
4897 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4899 V = DAG.getUNDEF(MVT::v16i8);
4902 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4903 MVT::v16i8, V, Op.getOperand(i),
4904 DAG.getIntPtrConstant(i, dl));
4911 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4912 for (unsigned i = 0; i < 16; ++i) {
4913 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4914 if (ThisIsNonZero && First) {
4916 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4918 V = DAG.getUNDEF(MVT::v8i16);
4923 SDValue ThisElt, LastElt;
4924 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4925 if (LastIsNonZero) {
4926 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4927 MVT::i16, Op.getOperand(i-1));
4929 if (ThisIsNonZero) {
4930 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4931 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4932 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4934 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4938 if (ThisElt.getNode())
4939 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4940 DAG.getIntPtrConstant(i/2, dl));
4944 return DAG.getBitcast(MVT::v16i8, V);
4947 /// Custom lower build_vector of v8i16.
4948 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4949 unsigned NumNonZero, unsigned NumZero,
4951 const X86Subtarget* Subtarget,
4952 const TargetLowering &TLI) {
4959 for (unsigned i = 0; i < 8; ++i) {
4960 bool isNonZero = (NonZeros & (1 << i)) != 0;
4964 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4966 V = DAG.getUNDEF(MVT::v8i16);
4969 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4970 MVT::v8i16, V, Op.getOperand(i),
4971 DAG.getIntPtrConstant(i, dl));
4978 /// Custom lower build_vector of v4i32 or v4f32.
4979 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4980 const X86Subtarget *Subtarget,
4981 const TargetLowering &TLI) {
4982 // Find all zeroable elements.
4983 std::bitset<4> Zeroable;
4984 for (int i=0; i < 4; ++i) {
4985 SDValue Elt = Op->getOperand(i);
4986 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4988 assert(Zeroable.size() - Zeroable.count() > 1 &&
4989 "We expect at least two non-zero elements!");
4991 // We only know how to deal with build_vector nodes where elements are either
4992 // zeroable or extract_vector_elt with constant index.
4993 SDValue FirstNonZero;
4994 unsigned FirstNonZeroIdx;
4995 for (unsigned i=0; i < 4; ++i) {
4998 SDValue Elt = Op->getOperand(i);
4999 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5000 !isa<ConstantSDNode>(Elt.getOperand(1)))
5002 // Make sure that this node is extracting from a 128-bit vector.
5003 MVT VT = Elt.getOperand(0).getSimpleValueType();
5004 if (!VT.is128BitVector())
5006 if (!FirstNonZero.getNode()) {
5008 FirstNonZeroIdx = i;
5012 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5013 SDValue V1 = FirstNonZero.getOperand(0);
5014 MVT VT = V1.getSimpleValueType();
5016 // See if this build_vector can be lowered as a blend with zero.
5018 unsigned EltMaskIdx, EltIdx;
5020 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5021 if (Zeroable[EltIdx]) {
5022 // The zero vector will be on the right hand side.
5023 Mask[EltIdx] = EltIdx+4;
5027 Elt = Op->getOperand(EltIdx);
5028 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5029 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5030 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5032 Mask[EltIdx] = EltIdx;
5036 // Let the shuffle legalizer deal with blend operations.
5037 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5038 if (V1.getSimpleValueType() != VT)
5039 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5040 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5043 // See if we can lower this build_vector to a INSERTPS.
5044 if (!Subtarget->hasSSE41())
5047 SDValue V2 = Elt.getOperand(0);
5048 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5051 bool CanFold = true;
5052 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5056 SDValue Current = Op->getOperand(i);
5057 SDValue SrcVector = Current->getOperand(0);
5060 CanFold = SrcVector == V1 &&
5061 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5067 assert(V1.getNode() && "Expected at least two non-zero elements!");
5068 if (V1.getSimpleValueType() != MVT::v4f32)
5069 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5070 if (V2.getSimpleValueType() != MVT::v4f32)
5071 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5073 // Ok, we can emit an INSERTPS instruction.
5074 unsigned ZMask = Zeroable.to_ulong();
5076 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5077 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5079 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5080 DAG.getIntPtrConstant(InsertPSMask, DL));
5081 return DAG.getBitcast(VT, Result);
5084 /// Return a vector logical shift node.
5085 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5086 unsigned NumBits, SelectionDAG &DAG,
5087 const TargetLowering &TLI, SDLoc dl) {
5088 assert(VT.is128BitVector() && "Unknown type for VShift");
5089 MVT ShVT = MVT::v2i64;
5090 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5091 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5092 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5093 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5094 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5095 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5099 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5101 // Check if the scalar load can be widened into a vector load. And if
5102 // the address is "base + cst" see if the cst can be "absorbed" into
5103 // the shuffle mask.
5104 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5105 SDValue Ptr = LD->getBasePtr();
5106 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5108 EVT PVT = LD->getValueType(0);
5109 if (PVT != MVT::i32 && PVT != MVT::f32)
5114 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5115 FI = FINode->getIndex();
5117 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5118 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5119 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5120 Offset = Ptr.getConstantOperandVal(1);
5121 Ptr = Ptr.getOperand(0);
5126 // FIXME: 256-bit vector instructions don't require a strict alignment,
5127 // improve this code to support it better.
5128 unsigned RequiredAlign = VT.getSizeInBits()/8;
5129 SDValue Chain = LD->getChain();
5130 // Make sure the stack object alignment is at least 16 or 32.
5131 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5132 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5133 if (MFI->isFixedObjectIndex(FI)) {
5134 // Can't change the alignment. FIXME: It's possible to compute
5135 // the exact stack offset and reference FI + adjust offset instead.
5136 // If someone *really* cares about this. That's the way to implement it.
5139 MFI->setObjectAlignment(FI, RequiredAlign);
5143 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5144 // Ptr + (Offset & ~15).
5147 if ((Offset % RequiredAlign) & 3)
5149 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5152 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5153 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5156 int EltNo = (Offset - StartOffset) >> 2;
5157 unsigned NumElems = VT.getVectorNumElements();
5159 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5160 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5161 LD->getPointerInfo().getWithOffset(StartOffset),
5162 false, false, false, 0);
5164 SmallVector<int, 8> Mask(NumElems, EltNo);
5166 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5172 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5173 /// elements can be replaced by a single large load which has the same value as
5174 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5176 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5178 /// FIXME: we'd also like to handle the case where the last elements are zero
5179 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5180 /// There's even a handy isZeroNode for that purpose.
5181 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5182 SDLoc &DL, SelectionDAG &DAG,
5183 bool isAfterLegalize) {
5184 unsigned NumElems = Elts.size();
5186 LoadSDNode *LDBase = nullptr;
5187 unsigned LastLoadedElt = -1U;
5189 // For each element in the initializer, see if we've found a load or an undef.
5190 // If we don't find an initial load element, or later load elements are
5191 // non-consecutive, bail out.
5192 for (unsigned i = 0; i < NumElems; ++i) {
5193 SDValue Elt = Elts[i];
5194 // Look through a bitcast.
5195 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5196 Elt = Elt.getOperand(0);
5197 if (!Elt.getNode() ||
5198 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5201 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5203 LDBase = cast<LoadSDNode>(Elt.getNode());
5207 if (Elt.getOpcode() == ISD::UNDEF)
5210 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5211 EVT LdVT = Elt.getValueType();
5212 // Each loaded element must be the correct fractional portion of the
5213 // requested vector load.
5214 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5216 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5221 // If we have found an entire vector of loads and undefs, then return a large
5222 // load of the entire vector width starting at the base pointer. If we found
5223 // consecutive loads for the low half, generate a vzext_load node.
5224 if (LastLoadedElt == NumElems - 1) {
5225 assert(LDBase && "Did not find base load for merging consecutive loads");
5226 EVT EltVT = LDBase->getValueType(0);
5227 // Ensure that the input vector size for the merged loads matches the
5228 // cumulative size of the input elements.
5229 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5232 if (isAfterLegalize &&
5233 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5236 SDValue NewLd = SDValue();
5238 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5239 LDBase->getPointerInfo(), LDBase->isVolatile(),
5240 LDBase->isNonTemporal(), LDBase->isInvariant(),
5241 LDBase->getAlignment());
5243 if (LDBase->hasAnyUseOfValue(1)) {
5244 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5246 SDValue(NewLd.getNode(), 1));
5247 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5248 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5249 SDValue(NewLd.getNode(), 1));
5255 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5256 //of a v4i32 / v4f32. It's probably worth generalizing.
5257 EVT EltVT = VT.getVectorElementType();
5258 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5259 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5260 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5261 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5263 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5264 LDBase->getPointerInfo(),
5265 LDBase->getAlignment(),
5266 false/*isVolatile*/, true/*ReadMem*/,
5269 // Make sure the newly-created LOAD is in the same position as LDBase in
5270 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5271 // update uses of LDBase's output chain to use the TokenFactor.
5272 if (LDBase->hasAnyUseOfValue(1)) {
5273 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5274 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5275 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5276 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5277 SDValue(ResNode.getNode(), 1));
5280 return DAG.getBitcast(VT, ResNode);
5285 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5286 /// to generate a splat value for the following cases:
5287 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5288 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5289 /// a scalar load, or a constant.
5290 /// The VBROADCAST node is returned when a pattern is found,
5291 /// or SDValue() otherwise.
5292 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5293 SelectionDAG &DAG) {
5294 // VBROADCAST requires AVX.
5295 // TODO: Splats could be generated for non-AVX CPUs using SSE
5296 // instructions, but there's less potential gain for only 128-bit vectors.
5297 if (!Subtarget->hasAVX())
5300 MVT VT = Op.getSimpleValueType();
5303 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5304 "Unsupported vector type for broadcast.");
5309 switch (Op.getOpcode()) {
5311 // Unknown pattern found.
5314 case ISD::BUILD_VECTOR: {
5315 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5316 BitVector UndefElements;
5317 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5319 // We need a splat of a single value to use broadcast, and it doesn't
5320 // make any sense if the value is only in one element of the vector.
5321 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5325 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5326 Ld.getOpcode() == ISD::ConstantFP);
5328 // Make sure that all of the users of a non-constant load are from the
5329 // BUILD_VECTOR node.
5330 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5335 case ISD::VECTOR_SHUFFLE: {
5336 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5338 // Shuffles must have a splat mask where the first element is
5340 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5343 SDValue Sc = Op.getOperand(0);
5344 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5345 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5347 if (!Subtarget->hasInt256())
5350 // Use the register form of the broadcast instruction available on AVX2.
5351 if (VT.getSizeInBits() >= 256)
5352 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5353 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5356 Ld = Sc.getOperand(0);
5357 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5358 Ld.getOpcode() == ISD::ConstantFP);
5360 // The scalar_to_vector node and the suspected
5361 // load node must have exactly one user.
5362 // Constants may have multiple users.
5364 // AVX-512 has register version of the broadcast
5365 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5366 Ld.getValueType().getSizeInBits() >= 32;
5367 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5374 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5375 bool IsGE256 = (VT.getSizeInBits() >= 256);
5377 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5378 // instruction to save 8 or more bytes of constant pool data.
5379 // TODO: If multiple splats are generated to load the same constant,
5380 // it may be detrimental to overall size. There needs to be a way to detect
5381 // that condition to know if this is truly a size win.
5382 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5384 // Handle broadcasting a single constant scalar from the constant pool
5386 // On Sandybridge (no AVX2), it is still better to load a constant vector
5387 // from the constant pool and not to broadcast it from a scalar.
5388 // But override that restriction when optimizing for size.
5389 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5390 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5391 EVT CVT = Ld.getValueType();
5392 assert(!CVT.isVector() && "Must not broadcast a vector type");
5394 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5395 // For size optimization, also splat v2f64 and v2i64, and for size opt
5396 // with AVX2, also splat i8 and i16.
5397 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5398 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5399 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5400 const Constant *C = nullptr;
5401 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5402 C = CI->getConstantIntValue();
5403 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5404 C = CF->getConstantFPValue();
5406 assert(C && "Invalid constant type");
5408 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5410 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5411 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5413 CVT, dl, DAG.getEntryNode(), CP,
5414 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5415 false, false, Alignment);
5417 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5421 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5423 // Handle AVX2 in-register broadcasts.
5424 if (!IsLoad && Subtarget->hasInt256() &&
5425 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5426 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5428 // The scalar source must be a normal load.
5432 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5433 (Subtarget->hasVLX() && ScalarSize == 64))
5434 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5436 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5437 // double since there is no vbroadcastsd xmm
5438 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5439 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5440 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5443 // Unsupported broadcast.
5447 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5448 /// underlying vector and index.
5450 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5452 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5454 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5455 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5458 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5460 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5462 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5463 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5466 // In this case the vector is the extract_subvector expression and the index
5467 // is 2, as specified by the shuffle.
5468 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5469 SDValue ShuffleVec = SVOp->getOperand(0);
5470 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5471 assert(ShuffleVecVT.getVectorElementType() ==
5472 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5474 int ShuffleIdx = SVOp->getMaskElt(Idx);
5475 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5476 ExtractedFromVec = ShuffleVec;
5482 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5483 MVT VT = Op.getSimpleValueType();
5485 // Skip if insert_vec_elt is not supported.
5486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5487 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5491 unsigned NumElems = Op.getNumOperands();
5495 SmallVector<unsigned, 4> InsertIndices;
5496 SmallVector<int, 8> Mask(NumElems, -1);
5498 for (unsigned i = 0; i != NumElems; ++i) {
5499 unsigned Opc = Op.getOperand(i).getOpcode();
5501 if (Opc == ISD::UNDEF)
5504 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5505 // Quit if more than 1 elements need inserting.
5506 if (InsertIndices.size() > 1)
5509 InsertIndices.push_back(i);
5513 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5514 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5515 // Quit if non-constant index.
5516 if (!isa<ConstantSDNode>(ExtIdx))
5518 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5520 // Quit if extracted from vector of different type.
5521 if (ExtractedFromVec.getValueType() != VT)
5524 if (!VecIn1.getNode())
5525 VecIn1 = ExtractedFromVec;
5526 else if (VecIn1 != ExtractedFromVec) {
5527 if (!VecIn2.getNode())
5528 VecIn2 = ExtractedFromVec;
5529 else if (VecIn2 != ExtractedFromVec)
5530 // Quit if more than 2 vectors to shuffle
5534 if (ExtractedFromVec == VecIn1)
5536 else if (ExtractedFromVec == VecIn2)
5537 Mask[i] = Idx + NumElems;
5540 if (!VecIn1.getNode())
5543 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5544 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5545 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5546 unsigned Idx = InsertIndices[i];
5547 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5548 DAG.getIntPtrConstant(Idx, DL));
5554 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5555 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5556 Op.getScalarValueSizeInBits() == 1 &&
5557 "Can not convert non-constant vector");
5558 uint64_t Immediate = 0;
5559 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5560 SDValue In = Op.getOperand(idx);
5561 if (In.getOpcode() != ISD::UNDEF)
5562 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5566 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5567 return DAG.getConstant(Immediate, dl, VT);
5569 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5571 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5573 MVT VT = Op.getSimpleValueType();
5574 assert((VT.getVectorElementType() == MVT::i1) &&
5575 "Unexpected type in LowerBUILD_VECTORvXi1!");
5578 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5579 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5580 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5581 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5584 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5585 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5586 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5587 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5590 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5591 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5592 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5593 return DAG.getBitcast(VT, Imm);
5594 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5595 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5596 DAG.getIntPtrConstant(0, dl));
5599 // Vector has one or more non-const elements
5600 uint64_t Immediate = 0;
5601 SmallVector<unsigned, 16> NonConstIdx;
5602 bool IsSplat = true;
5603 bool HasConstElts = false;
5605 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5606 SDValue In = Op.getOperand(idx);
5607 if (In.getOpcode() == ISD::UNDEF)
5609 if (!isa<ConstantSDNode>(In))
5610 NonConstIdx.push_back(idx);
5612 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5613 HasConstElts = true;
5617 else if (In != Op.getOperand(SplatIdx))
5621 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5623 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5624 DAG.getConstant(1, dl, VT),
5625 DAG.getConstant(0, dl, VT));
5627 // insert elements one by one
5631 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5632 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5634 else if (HasConstElts)
5635 Imm = DAG.getConstant(0, dl, VT);
5637 Imm = DAG.getUNDEF(VT);
5638 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5639 DstVec = DAG.getBitcast(VT, Imm);
5641 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5642 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5643 DAG.getIntPtrConstant(0, dl));
5646 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5647 unsigned InsertIdx = NonConstIdx[i];
5648 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5649 Op.getOperand(InsertIdx),
5650 DAG.getIntPtrConstant(InsertIdx, dl));
5655 /// \brief Return true if \p N implements a horizontal binop and return the
5656 /// operands for the horizontal binop into V0 and V1.
5658 /// This is a helper function of LowerToHorizontalOp().
5659 /// This function checks that the build_vector \p N in input implements a
5660 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5661 /// operation to match.
5662 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5663 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5664 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5667 /// This function only analyzes elements of \p N whose indices are
5668 /// in range [BaseIdx, LastIdx).
5669 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5671 unsigned BaseIdx, unsigned LastIdx,
5672 SDValue &V0, SDValue &V1) {
5673 EVT VT = N->getValueType(0);
5675 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5676 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5677 "Invalid Vector in input!");
5679 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5680 bool CanFold = true;
5681 unsigned ExpectedVExtractIdx = BaseIdx;
5682 unsigned NumElts = LastIdx - BaseIdx;
5683 V0 = DAG.getUNDEF(VT);
5684 V1 = DAG.getUNDEF(VT);
5686 // Check if N implements a horizontal binop.
5687 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5688 SDValue Op = N->getOperand(i + BaseIdx);
5691 if (Op->getOpcode() == ISD::UNDEF) {
5692 // Update the expected vector extract index.
5693 if (i * 2 == NumElts)
5694 ExpectedVExtractIdx = BaseIdx;
5695 ExpectedVExtractIdx += 2;
5699 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5704 SDValue Op0 = Op.getOperand(0);
5705 SDValue Op1 = Op.getOperand(1);
5707 // Try to match the following pattern:
5708 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5709 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5710 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5711 Op0.getOperand(0) == Op1.getOperand(0) &&
5712 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5713 isa<ConstantSDNode>(Op1.getOperand(1)));
5717 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5718 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5720 if (i * 2 < NumElts) {
5721 if (V0.getOpcode() == ISD::UNDEF) {
5722 V0 = Op0.getOperand(0);
5723 if (V0.getValueType() != VT)
5727 if (V1.getOpcode() == ISD::UNDEF) {
5728 V1 = Op0.getOperand(0);
5729 if (V1.getValueType() != VT)
5732 if (i * 2 == NumElts)
5733 ExpectedVExtractIdx = BaseIdx;
5736 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5737 if (I0 == ExpectedVExtractIdx)
5738 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5739 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5740 // Try to match the following dag sequence:
5741 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5742 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5746 ExpectedVExtractIdx += 2;
5752 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5753 /// a concat_vector.
5755 /// This is a helper function of LowerToHorizontalOp().
5756 /// This function expects two 256-bit vectors called V0 and V1.
5757 /// At first, each vector is split into two separate 128-bit vectors.
5758 /// Then, the resulting 128-bit vectors are used to implement two
5759 /// horizontal binary operations.
5761 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5763 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5764 /// the two new horizontal binop.
5765 /// When Mode is set, the first horizontal binop dag node would take as input
5766 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5767 /// horizontal binop dag node would take as input the lower 128-bit of V1
5768 /// and the upper 128-bit of V1.
5770 /// HADD V0_LO, V0_HI
5771 /// HADD V1_LO, V1_HI
5773 /// Otherwise, the first horizontal binop dag node takes as input the lower
5774 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5775 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5777 /// HADD V0_LO, V1_LO
5778 /// HADD V0_HI, V1_HI
5780 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5781 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5782 /// the upper 128-bits of the result.
5783 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5784 SDLoc DL, SelectionDAG &DAG,
5785 unsigned X86Opcode, bool Mode,
5786 bool isUndefLO, bool isUndefHI) {
5787 EVT VT = V0.getValueType();
5788 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5789 "Invalid nodes in input!");
5791 unsigned NumElts = VT.getVectorNumElements();
5792 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5793 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5794 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5795 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5796 EVT NewVT = V0_LO.getValueType();
5798 SDValue LO = DAG.getUNDEF(NewVT);
5799 SDValue HI = DAG.getUNDEF(NewVT);
5802 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5803 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5804 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5805 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5806 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5808 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5809 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5810 V1_LO->getOpcode() != ISD::UNDEF))
5811 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5813 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5814 V1_HI->getOpcode() != ISD::UNDEF))
5815 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5818 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5821 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5823 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5824 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5825 EVT VT = BV->getValueType(0);
5826 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5827 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5831 unsigned NumElts = VT.getVectorNumElements();
5832 SDValue InVec0 = DAG.getUNDEF(VT);
5833 SDValue InVec1 = DAG.getUNDEF(VT);
5835 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5836 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5838 // Odd-numbered elements in the input build vector are obtained from
5839 // adding two integer/float elements.
5840 // Even-numbered elements in the input build vector are obtained from
5841 // subtracting two integer/float elements.
5842 unsigned ExpectedOpcode = ISD::FSUB;
5843 unsigned NextExpectedOpcode = ISD::FADD;
5844 bool AddFound = false;
5845 bool SubFound = false;
5847 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5848 SDValue Op = BV->getOperand(i);
5850 // Skip 'undef' values.
5851 unsigned Opcode = Op.getOpcode();
5852 if (Opcode == ISD::UNDEF) {
5853 std::swap(ExpectedOpcode, NextExpectedOpcode);
5857 // Early exit if we found an unexpected opcode.
5858 if (Opcode != ExpectedOpcode)
5861 SDValue Op0 = Op.getOperand(0);
5862 SDValue Op1 = Op.getOperand(1);
5864 // Try to match the following pattern:
5865 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5866 // Early exit if we cannot match that sequence.
5867 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5868 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5869 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5870 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5871 Op0.getOperand(1) != Op1.getOperand(1))
5874 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5878 // We found a valid add/sub node. Update the information accordingly.
5884 // Update InVec0 and InVec1.
5885 if (InVec0.getOpcode() == ISD::UNDEF) {
5886 InVec0 = Op0.getOperand(0);
5887 if (InVec0.getValueType() != VT)
5890 if (InVec1.getOpcode() == ISD::UNDEF) {
5891 InVec1 = Op1.getOperand(0);
5892 if (InVec1.getValueType() != VT)
5896 // Make sure that operands in input to each add/sub node always
5897 // come from a same pair of vectors.
5898 if (InVec0 != Op0.getOperand(0)) {
5899 if (ExpectedOpcode == ISD::FSUB)
5902 // FADD is commutable. Try to commute the operands
5903 // and then test again.
5904 std::swap(Op0, Op1);
5905 if (InVec0 != Op0.getOperand(0))
5909 if (InVec1 != Op1.getOperand(0))
5912 // Update the pair of expected opcodes.
5913 std::swap(ExpectedOpcode, NextExpectedOpcode);
5916 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5917 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5918 InVec1.getOpcode() != ISD::UNDEF)
5919 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5924 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5925 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5926 const X86Subtarget *Subtarget,
5927 SelectionDAG &DAG) {
5928 EVT VT = BV->getValueType(0);
5929 unsigned NumElts = VT.getVectorNumElements();
5930 unsigned NumUndefsLO = 0;
5931 unsigned NumUndefsHI = 0;
5932 unsigned Half = NumElts/2;
5934 // Count the number of UNDEF operands in the build_vector in input.
5935 for (unsigned i = 0, e = Half; i != e; ++i)
5936 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5939 for (unsigned i = Half, e = NumElts; i != e; ++i)
5940 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5943 // Early exit if this is either a build_vector of all UNDEFs or all the
5944 // operands but one are UNDEF.
5945 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5949 SDValue InVec0, InVec1;
5950 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5951 // Try to match an SSE3 float HADD/HSUB.
5952 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5953 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5955 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5956 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5957 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5958 // Try to match an SSSE3 integer HADD/HSUB.
5959 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5960 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5962 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5963 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5966 if (!Subtarget->hasAVX())
5969 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5970 // Try to match an AVX horizontal add/sub of packed single/double
5971 // precision floating point values from 256-bit vectors.
5972 SDValue InVec2, InVec3;
5973 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5974 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5975 ((InVec0.getOpcode() == ISD::UNDEF ||
5976 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5977 ((InVec1.getOpcode() == ISD::UNDEF ||
5978 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5979 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5981 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5982 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5983 ((InVec0.getOpcode() == ISD::UNDEF ||
5984 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5985 ((InVec1.getOpcode() == ISD::UNDEF ||
5986 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5987 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5988 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5989 // Try to match an AVX2 horizontal add/sub of signed integers.
5990 SDValue InVec2, InVec3;
5992 bool CanFold = true;
5994 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5995 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5996 ((InVec0.getOpcode() == ISD::UNDEF ||
5997 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5998 ((InVec1.getOpcode() == ISD::UNDEF ||
5999 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6000 X86Opcode = X86ISD::HADD;
6001 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6002 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6003 ((InVec0.getOpcode() == ISD::UNDEF ||
6004 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6005 ((InVec1.getOpcode() == ISD::UNDEF ||
6006 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6007 X86Opcode = X86ISD::HSUB;
6012 // Fold this build_vector into a single horizontal add/sub.
6013 // Do this only if the target has AVX2.
6014 if (Subtarget->hasAVX2())
6015 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6017 // Do not try to expand this build_vector into a pair of horizontal
6018 // add/sub if we can emit a pair of scalar add/sub.
6019 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6022 // Convert this build_vector into a pair of horizontal binop followed by
6024 bool isUndefLO = NumUndefsLO == Half;
6025 bool isUndefHI = NumUndefsHI == Half;
6026 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6027 isUndefLO, isUndefHI);
6031 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6032 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6034 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6035 X86Opcode = X86ISD::HADD;
6036 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6037 X86Opcode = X86ISD::HSUB;
6038 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6039 X86Opcode = X86ISD::FHADD;
6040 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6041 X86Opcode = X86ISD::FHSUB;
6045 // Don't try to expand this build_vector into a pair of horizontal add/sub
6046 // if we can simply emit a pair of scalar add/sub.
6047 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6050 // Convert this build_vector into two horizontal add/sub followed by
6052 bool isUndefLO = NumUndefsLO == Half;
6053 bool isUndefHI = NumUndefsHI == Half;
6054 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6055 isUndefLO, isUndefHI);
6062 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6065 MVT VT = Op.getSimpleValueType();
6066 MVT ExtVT = VT.getVectorElementType();
6067 unsigned NumElems = Op.getNumOperands();
6069 // Generate vectors for predicate vectors.
6070 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6071 return LowerBUILD_VECTORvXi1(Op, DAG);
6073 // Vectors containing all zeros can be matched by pxor and xorps later
6074 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6075 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6076 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6077 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6080 return getZeroVector(VT, Subtarget, DAG, dl);
6083 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6084 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6085 // vpcmpeqd on 256-bit vectors.
6086 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6087 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6090 if (!VT.is512BitVector())
6091 return getOnesVector(VT, Subtarget, DAG, dl);
6094 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6095 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6097 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6098 return HorizontalOp;
6099 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6102 unsigned EVTBits = ExtVT.getSizeInBits();
6104 unsigned NumZero = 0;
6105 unsigned NumNonZero = 0;
6106 unsigned NonZeros = 0;
6107 bool IsAllConstants = true;
6108 SmallSet<SDValue, 8> Values;
6109 for (unsigned i = 0; i < NumElems; ++i) {
6110 SDValue Elt = Op.getOperand(i);
6111 if (Elt.getOpcode() == ISD::UNDEF)
6114 if (Elt.getOpcode() != ISD::Constant &&
6115 Elt.getOpcode() != ISD::ConstantFP)
6116 IsAllConstants = false;
6117 if (X86::isZeroNode(Elt))
6120 NonZeros |= (1 << i);
6125 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6126 if (NumNonZero == 0)
6127 return DAG.getUNDEF(VT);
6129 // Special case for single non-zero, non-undef, element.
6130 if (NumNonZero == 1) {
6131 unsigned Idx = countTrailingZeros(NonZeros);
6132 SDValue Item = Op.getOperand(Idx);
6134 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6135 // the value are obviously zero, truncate the value to i32 and do the
6136 // insertion that way. Only do this if the value is non-constant or if the
6137 // value is a constant being inserted into element 0. It is cheaper to do
6138 // a constant pool load than it is to do a movd + shuffle.
6139 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6140 (!IsAllConstants || Idx == 0)) {
6141 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6143 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6144 EVT VecVT = MVT::v4i32;
6146 // Truncate the value (which may itself be a constant) to i32, and
6147 // convert it to a vector with movd (S2V+shuffle to zero extend).
6148 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6149 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6150 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6151 Item, Idx * 2, true, Subtarget, DAG));
6155 // If we have a constant or non-constant insertion into the low element of
6156 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6157 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6158 // depending on what the source datatype is.
6161 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6163 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6164 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6165 if (VT.is512BitVector()) {
6166 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6167 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6168 Item, DAG.getIntPtrConstant(0, dl));
6170 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6171 "Expected an SSE value type!");
6172 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6173 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6174 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6177 // We can't directly insert an i8 or i16 into a vector, so zero extend
6179 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6180 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6181 if (VT.is256BitVector()) {
6182 if (Subtarget->hasAVX()) {
6183 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6184 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6186 // Without AVX, we need to extend to a 128-bit vector and then
6187 // insert into the 256-bit vector.
6188 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6189 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6190 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6193 assert(VT.is128BitVector() && "Expected an SSE value type!");
6194 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6195 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6197 return DAG.getBitcast(VT, Item);
6201 // Is it a vector logical left shift?
6202 if (NumElems == 2 && Idx == 1 &&
6203 X86::isZeroNode(Op.getOperand(0)) &&
6204 !X86::isZeroNode(Op.getOperand(1))) {
6205 unsigned NumBits = VT.getSizeInBits();
6206 return getVShift(true, VT,
6207 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6208 VT, Op.getOperand(1)),
6209 NumBits/2, DAG, *this, dl);
6212 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6215 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6216 // is a non-constant being inserted into an element other than the low one,
6217 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6218 // movd/movss) to move this into the low element, then shuffle it into
6220 if (EVTBits == 32) {
6221 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6222 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6226 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6227 if (Values.size() == 1) {
6228 if (EVTBits == 32) {
6229 // Instead of a shuffle like this:
6230 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6231 // Check if it's possible to issue this instead.
6232 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6233 unsigned Idx = countTrailingZeros(NonZeros);
6234 SDValue Item = Op.getOperand(Idx);
6235 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6236 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6241 // A vector full of immediates; various special cases are already
6242 // handled, so this is best done with a single constant-pool load.
6246 // For AVX-length vectors, see if we can use a vector load to get all of the
6247 // elements, otherwise build the individual 128-bit pieces and use
6248 // shuffles to put them in place.
6249 if (VT.is256BitVector() || VT.is512BitVector()) {
6250 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6252 // Check for a build vector of consecutive loads.
6253 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6256 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6258 // Build both the lower and upper subvector.
6259 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6260 makeArrayRef(&V[0], NumElems/2));
6261 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6262 makeArrayRef(&V[NumElems / 2], NumElems/2));
6264 // Recreate the wider vector with the lower and upper part.
6265 if (VT.is256BitVector())
6266 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6267 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6270 // Let legalizer expand 2-wide build_vectors.
6271 if (EVTBits == 64) {
6272 if (NumNonZero == 1) {
6273 // One half is zero or undef.
6274 unsigned Idx = countTrailingZeros(NonZeros);
6275 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6276 Op.getOperand(Idx));
6277 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6282 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6283 if (EVTBits == 8 && NumElems == 16)
6284 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6288 if (EVTBits == 16 && NumElems == 8)
6289 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6293 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6294 if (EVTBits == 32 && NumElems == 4)
6295 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6298 // If element VT is == 32 bits, turn it into a number of shuffles.
6299 SmallVector<SDValue, 8> V(NumElems);
6300 if (NumElems == 4 && NumZero > 0) {
6301 for (unsigned i = 0; i < 4; ++i) {
6302 bool isZero = !(NonZeros & (1 << i));
6304 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6306 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6309 for (unsigned i = 0; i < 2; ++i) {
6310 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6313 V[i] = V[i*2]; // Must be a zero vector.
6316 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6319 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6322 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6327 bool Reverse1 = (NonZeros & 0x3) == 2;
6328 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6332 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6333 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6335 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6338 if (Values.size() > 1 && VT.is128BitVector()) {
6339 // Check for a build vector of consecutive loads.
6340 for (unsigned i = 0; i < NumElems; ++i)
6341 V[i] = Op.getOperand(i);
6343 // Check for elements which are consecutive loads.
6344 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6347 // Check for a build vector from mostly shuffle plus few inserting.
6348 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6351 // For SSE 4.1, use insertps to put the high elements into the low element.
6352 if (Subtarget->hasSSE41()) {
6354 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6355 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6357 Result = DAG.getUNDEF(VT);
6359 for (unsigned i = 1; i < NumElems; ++i) {
6360 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6361 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6362 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6367 // Otherwise, expand into a number of unpckl*, start by extending each of
6368 // our (non-undef) elements to the full vector width with the element in the
6369 // bottom slot of the vector (which generates no code for SSE).
6370 for (unsigned i = 0; i < NumElems; ++i) {
6371 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6372 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6374 V[i] = DAG.getUNDEF(VT);
6377 // Next, we iteratively mix elements, e.g. for v4f32:
6378 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6379 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6380 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6381 unsigned EltStride = NumElems >> 1;
6382 while (EltStride != 0) {
6383 for (unsigned i = 0; i < EltStride; ++i) {
6384 // If V[i+EltStride] is undef and this is the first round of mixing,
6385 // then it is safe to just drop this shuffle: V[i] is already in the
6386 // right place, the one element (since it's the first round) being
6387 // inserted as undef can be dropped. This isn't safe for successive
6388 // rounds because they will permute elements within both vectors.
6389 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6390 EltStride == NumElems/2)
6393 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6402 // 256-bit AVX can use the vinsertf128 instruction
6403 // to create 256-bit vectors from two other 128-bit ones.
6404 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6406 MVT ResVT = Op.getSimpleValueType();
6408 assert((ResVT.is256BitVector() ||
6409 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6411 SDValue V1 = Op.getOperand(0);
6412 SDValue V2 = Op.getOperand(1);
6413 unsigned NumElems = ResVT.getVectorNumElements();
6414 if (ResVT.is256BitVector())
6415 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6417 if (Op.getNumOperands() == 4) {
6418 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6419 ResVT.getVectorNumElements()/2);
6420 SDValue V3 = Op.getOperand(2);
6421 SDValue V4 = Op.getOperand(3);
6422 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6423 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6425 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6428 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6429 const X86Subtarget *Subtarget,
6430 SelectionDAG & DAG) {
6432 MVT ResVT = Op.getSimpleValueType();
6433 unsigned NumOfOperands = Op.getNumOperands();
6435 assert(isPowerOf2_32(NumOfOperands) &&
6436 "Unexpected number of operands in CONCAT_VECTORS");
6438 if (NumOfOperands > 2) {
6439 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6440 ResVT.getVectorNumElements()/2);
6441 SmallVector<SDValue, 2> Ops;
6442 for (unsigned i = 0; i < NumOfOperands/2; i++)
6443 Ops.push_back(Op.getOperand(i));
6444 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6446 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6447 Ops.push_back(Op.getOperand(i));
6448 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6449 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6452 SDValue V1 = Op.getOperand(0);
6453 SDValue V2 = Op.getOperand(1);
6454 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6455 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6457 if (IsZeroV1 && IsZeroV2)
6458 return getZeroVector(ResVT, Subtarget, DAG, dl);
6460 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6461 SDValue Undef = DAG.getUNDEF(ResVT);
6462 unsigned NumElems = ResVT.getVectorNumElements();
6463 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6465 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6466 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6470 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6471 // Zero the upper bits of V1
6472 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6473 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6476 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6479 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6480 const X86Subtarget *Subtarget,
6481 SelectionDAG &DAG) {
6482 MVT VT = Op.getSimpleValueType();
6483 if (VT.getVectorElementType() == MVT::i1)
6484 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6486 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6487 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6488 Op.getNumOperands() == 4)));
6490 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6491 // from two other 128-bit ones.
6493 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6494 return LowerAVXCONCAT_VECTORS(Op, DAG);
6497 //===----------------------------------------------------------------------===//
6498 // Vector shuffle lowering
6500 // This is an experimental code path for lowering vector shuffles on x86. It is
6501 // designed to handle arbitrary vector shuffles and blends, gracefully
6502 // degrading performance as necessary. It works hard to recognize idiomatic
6503 // shuffles and lower them to optimal instruction patterns without leaving
6504 // a framework that allows reasonably efficient handling of all vector shuffle
6506 //===----------------------------------------------------------------------===//
6508 /// \brief Tiny helper function to identify a no-op mask.
6510 /// This is a somewhat boring predicate function. It checks whether the mask
6511 /// array input, which is assumed to be a single-input shuffle mask of the kind
6512 /// used by the X86 shuffle instructions (not a fully general
6513 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6514 /// in-place shuffle are 'no-op's.
6515 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6516 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6517 if (Mask[i] != -1 && Mask[i] != i)
6522 /// \brief Helper function to classify a mask as a single-input mask.
6524 /// This isn't a generic single-input test because in the vector shuffle
6525 /// lowering we canonicalize single inputs to be the first input operand. This
6526 /// means we can more quickly test for a single input by only checking whether
6527 /// an input from the second operand exists. We also assume that the size of
6528 /// mask corresponds to the size of the input vectors which isn't true in the
6529 /// fully general case.
6530 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6532 if (M >= (int)Mask.size())
6537 /// \brief Test whether there are elements crossing 128-bit lanes in this
6540 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6541 /// and we routinely test for these.
6542 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6543 int LaneSize = 128 / VT.getScalarSizeInBits();
6544 int Size = Mask.size();
6545 for (int i = 0; i < Size; ++i)
6546 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6551 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6553 /// This checks a shuffle mask to see if it is performing the same
6554 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6555 /// that it is also not lane-crossing. It may however involve a blend from the
6556 /// same lane of a second vector.
6558 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6559 /// non-trivial to compute in the face of undef lanes. The representation is
6560 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6561 /// entries from both V1 and V2 inputs to the wider mask.
6563 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6564 SmallVectorImpl<int> &RepeatedMask) {
6565 int LaneSize = 128 / VT.getScalarSizeInBits();
6566 RepeatedMask.resize(LaneSize, -1);
6567 int Size = Mask.size();
6568 for (int i = 0; i < Size; ++i) {
6571 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6572 // This entry crosses lanes, so there is no way to model this shuffle.
6575 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6576 if (RepeatedMask[i % LaneSize] == -1)
6577 // This is the first non-undef entry in this slot of a 128-bit lane.
6578 RepeatedMask[i % LaneSize] =
6579 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6580 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6581 // Found a mismatch with the repeated mask.
6587 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6590 /// This is a fast way to test a shuffle mask against a fixed pattern:
6592 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6594 /// It returns true if the mask is exactly as wide as the argument list, and
6595 /// each element of the mask is either -1 (signifying undef) or the value given
6596 /// in the argument.
6597 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6598 ArrayRef<int> ExpectedMask) {
6599 if (Mask.size() != ExpectedMask.size())
6602 int Size = Mask.size();
6604 // If the values are build vectors, we can look through them to find
6605 // equivalent inputs that make the shuffles equivalent.
6606 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6607 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6609 for (int i = 0; i < Size; ++i)
6610 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6611 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6612 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6613 if (!MaskBV || !ExpectedBV ||
6614 MaskBV->getOperand(Mask[i] % Size) !=
6615 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6622 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6624 /// This helper function produces an 8-bit shuffle immediate corresponding to
6625 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6626 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6629 /// NB: We rely heavily on "undef" masks preserving the input lane.
6630 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6631 SelectionDAG &DAG) {
6632 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6633 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6634 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6635 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6636 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6639 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6640 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6641 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6642 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6643 return DAG.getConstant(Imm, DL, MVT::i8);
6646 /// \brief Compute whether each element of a shuffle is zeroable.
6648 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6649 /// Either it is an undef element in the shuffle mask, the element of the input
6650 /// referenced is undef, or the element of the input referenced is known to be
6651 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6652 /// as many lanes with this technique as possible to simplify the remaining
6654 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6655 SDValue V1, SDValue V2) {
6656 SmallBitVector Zeroable(Mask.size(), false);
6658 while (V1.getOpcode() == ISD::BITCAST)
6659 V1 = V1->getOperand(0);
6660 while (V2.getOpcode() == ISD::BITCAST)
6661 V2 = V2->getOperand(0);
6663 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6664 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6666 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6668 // Handle the easy cases.
6669 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6674 // If this is an index into a build_vector node (which has the same number
6675 // of elements), dig out the input value and use it.
6676 SDValue V = M < Size ? V1 : V2;
6677 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6680 SDValue Input = V.getOperand(M % Size);
6681 // The UNDEF opcode check really should be dead code here, but not quite
6682 // worth asserting on (it isn't invalid, just unexpected).
6683 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6690 // X86 has dedicated unpack instructions that can handle specific blend
6691 // operations: UNPCKH and UNPCKL.
6692 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6693 SDValue V1, SDValue V2,
6694 SelectionDAG &DAG) {
6695 int NumElts = VT.getVectorNumElements();
6698 bool UnpcklSwapped = true;
6699 bool UnpckhSwapped = true;
6700 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6702 for (int i = 0; i < NumElts; ++i) {
6703 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6705 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6706 int HiPos = LoPos + NumEltsInLane / 2;
6707 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6708 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6712 if (Mask[i] != LoPos)
6714 if (Mask[i] != HiPos)
6716 if (Mask[i] != LoPosSwapped)
6717 UnpcklSwapped = false;
6718 if (Mask[i] != HiPosSwapped)
6719 UnpckhSwapped = false;
6720 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6724 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6726 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6728 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6730 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6732 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6736 /// \brief Try to emit a bitmask instruction for a shuffle.
6738 /// This handles cases where we can model a blend exactly as a bitmask due to
6739 /// one of the inputs being zeroable.
6740 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6741 SDValue V2, ArrayRef<int> Mask,
6742 SelectionDAG &DAG) {
6743 MVT EltVT = VT.getScalarType();
6744 int NumEltBits = EltVT.getSizeInBits();
6745 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6746 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6747 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6749 if (EltVT.isFloatingPoint()) {
6750 Zero = DAG.getBitcast(EltVT, Zero);
6751 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6753 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6754 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6756 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6759 if (Mask[i] % Size != i)
6760 return SDValue(); // Not a blend.
6762 V = Mask[i] < Size ? V1 : V2;
6763 else if (V != (Mask[i] < Size ? V1 : V2))
6764 return SDValue(); // Can only let one input through the mask.
6766 VMaskOps[i] = AllOnes;
6769 return SDValue(); // No non-zeroable elements!
6771 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6772 V = DAG.getNode(VT.isFloatingPoint()
6773 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6778 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6780 /// This is used as a fallback approach when first class blend instructions are
6781 /// unavailable. Currently it is only suitable for integer vectors, but could
6782 /// be generalized for floating point vectors if desirable.
6783 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6784 SDValue V2, ArrayRef<int> Mask,
6785 SelectionDAG &DAG) {
6786 assert(VT.isInteger() && "Only supports integer vector types!");
6787 MVT EltVT = VT.getScalarType();
6788 int NumEltBits = EltVT.getSizeInBits();
6789 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6790 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6792 SmallVector<SDValue, 16> MaskOps;
6793 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6794 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6795 return SDValue(); // Shuffled input!
6796 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6799 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6800 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6801 // We have to cast V2 around.
6802 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6803 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6804 DAG.getBitcast(MaskVT, V1Mask),
6805 DAG.getBitcast(MaskVT, V2)));
6806 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6809 /// \brief Try to emit a blend instruction for a shuffle.
6811 /// This doesn't do any checks for the availability of instructions for blending
6812 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6813 /// be matched in the backend with the type given. What it does check for is
6814 /// that the shuffle mask is in fact a blend.
6815 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6816 SDValue V2, ArrayRef<int> Mask,
6817 const X86Subtarget *Subtarget,
6818 SelectionDAG &DAG) {
6819 unsigned BlendMask = 0;
6820 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6821 if (Mask[i] >= Size) {
6822 if (Mask[i] != i + Size)
6823 return SDValue(); // Shuffled V2 input!
6824 BlendMask |= 1u << i;
6827 if (Mask[i] >= 0 && Mask[i] != i)
6828 return SDValue(); // Shuffled V1 input!
6830 switch (VT.SimpleTy) {
6835 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6836 DAG.getConstant(BlendMask, DL, MVT::i8));
6840 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6844 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6845 // that instruction.
6846 if (Subtarget->hasAVX2()) {
6847 // Scale the blend by the number of 32-bit dwords per element.
6848 int Scale = VT.getScalarSizeInBits() / 32;
6850 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6851 if (Mask[i] >= Size)
6852 for (int j = 0; j < Scale; ++j)
6853 BlendMask |= 1u << (i * Scale + j);
6855 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6856 V1 = DAG.getBitcast(BlendVT, V1);
6857 V2 = DAG.getBitcast(BlendVT, V2);
6858 return DAG.getBitcast(
6859 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6860 DAG.getConstant(BlendMask, DL, MVT::i8)));
6864 // For integer shuffles we need to expand the mask and cast the inputs to
6865 // v8i16s prior to blending.
6866 int Scale = 8 / VT.getVectorNumElements();
6868 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6869 if (Mask[i] >= Size)
6870 for (int j = 0; j < Scale; ++j)
6871 BlendMask |= 1u << (i * Scale + j);
6873 V1 = DAG.getBitcast(MVT::v8i16, V1);
6874 V2 = DAG.getBitcast(MVT::v8i16, V2);
6875 return DAG.getBitcast(VT,
6876 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6877 DAG.getConstant(BlendMask, DL, MVT::i8)));
6881 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6882 SmallVector<int, 8> RepeatedMask;
6883 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6884 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6885 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6887 for (int i = 0; i < 8; ++i)
6888 if (RepeatedMask[i] >= 16)
6889 BlendMask |= 1u << i;
6890 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6891 DAG.getConstant(BlendMask, DL, MVT::i8));
6897 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6898 "256-bit byte-blends require AVX2 support!");
6900 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6901 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6904 // Scale the blend by the number of bytes per element.
6905 int Scale = VT.getScalarSizeInBits() / 8;
6907 // This form of blend is always done on bytes. Compute the byte vector
6909 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6911 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6912 // mix of LLVM's code generator and the x86 backend. We tell the code
6913 // generator that boolean values in the elements of an x86 vector register
6914 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6915 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6916 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6917 // of the element (the remaining are ignored) and 0 in that high bit would
6918 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6919 // the LLVM model for boolean values in vector elements gets the relevant
6920 // bit set, it is set backwards and over constrained relative to x86's
6922 SmallVector<SDValue, 32> VSELECTMask;
6923 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6924 for (int j = 0; j < Scale; ++j)
6925 VSELECTMask.push_back(
6926 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6927 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6930 V1 = DAG.getBitcast(BlendVT, V1);
6931 V2 = DAG.getBitcast(BlendVT, V2);
6932 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6933 DAG.getNode(ISD::BUILD_VECTOR, DL,
6934 BlendVT, VSELECTMask),
6939 llvm_unreachable("Not a supported integer vector type!");
6943 /// \brief Try to lower as a blend of elements from two inputs followed by
6944 /// a single-input permutation.
6946 /// This matches the pattern where we can blend elements from two inputs and
6947 /// then reduce the shuffle to a single-input permutation.
6948 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6951 SelectionDAG &DAG) {
6952 // We build up the blend mask while checking whether a blend is a viable way
6953 // to reduce the shuffle.
6954 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6955 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6957 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6961 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6963 if (BlendMask[Mask[i] % Size] == -1)
6964 BlendMask[Mask[i] % Size] = Mask[i];
6965 else if (BlendMask[Mask[i] % Size] != Mask[i])
6966 return SDValue(); // Can't blend in the needed input!
6968 PermuteMask[i] = Mask[i] % Size;
6971 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6972 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6975 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6976 /// blends and permutes.
6978 /// This matches the extremely common pattern for handling combined
6979 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6980 /// operations. It will try to pick the best arrangement of shuffles and
6982 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6986 SelectionDAG &DAG) {
6987 // Shuffle the input elements into the desired positions in V1 and V2 and
6988 // blend them together.
6989 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6990 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6991 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6992 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6993 if (Mask[i] >= 0 && Mask[i] < Size) {
6994 V1Mask[i] = Mask[i];
6996 } else if (Mask[i] >= Size) {
6997 V2Mask[i] = Mask[i] - Size;
6998 BlendMask[i] = i + Size;
7001 // Try to lower with the simpler initial blend strategy unless one of the
7002 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7003 // shuffle may be able to fold with a load or other benefit. However, when
7004 // we'll have to do 2x as many shuffles in order to achieve this, blending
7005 // first is a better strategy.
7006 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7007 if (SDValue BlendPerm =
7008 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7011 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7012 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7013 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7016 /// \brief Try to lower a vector shuffle as a byte rotation.
7018 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7019 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7020 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7021 /// try to generically lower a vector shuffle through such an pattern. It
7022 /// does not check for the profitability of lowering either as PALIGNR or
7023 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7024 /// This matches shuffle vectors that look like:
7026 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7028 /// Essentially it concatenates V1 and V2, shifts right by some number of
7029 /// elements, and takes the low elements as the result. Note that while this is
7030 /// specified as a *right shift* because x86 is little-endian, it is a *left
7031 /// rotate* of the vector lanes.
7032 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7035 const X86Subtarget *Subtarget,
7036 SelectionDAG &DAG) {
7037 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7039 int NumElts = Mask.size();
7040 int NumLanes = VT.getSizeInBits() / 128;
7041 int NumLaneElts = NumElts / NumLanes;
7043 // We need to detect various ways of spelling a rotation:
7044 // [11, 12, 13, 14, 15, 0, 1, 2]
7045 // [-1, 12, 13, 14, -1, -1, 1, -1]
7046 // [-1, -1, -1, -1, -1, -1, 1, 2]
7047 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7048 // [-1, 4, 5, 6, -1, -1, 9, -1]
7049 // [-1, 4, 5, 6, -1, -1, -1, -1]
7052 for (int l = 0; l < NumElts; l += NumLaneElts) {
7053 for (int i = 0; i < NumLaneElts; ++i) {
7054 if (Mask[l + i] == -1)
7056 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7058 // Get the mod-Size index and lane correct it.
7059 int LaneIdx = (Mask[l + i] % NumElts) - l;
7060 // Make sure it was in this lane.
7061 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7064 // Determine where a rotated vector would have started.
7065 int StartIdx = i - LaneIdx;
7067 // The identity rotation isn't interesting, stop.
7070 // If we found the tail of a vector the rotation must be the missing
7071 // front. If we found the head of a vector, it must be how much of the
7073 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7076 Rotation = CandidateRotation;
7077 else if (Rotation != CandidateRotation)
7078 // The rotations don't match, so we can't match this mask.
7081 // Compute which value this mask is pointing at.
7082 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7084 // Compute which of the two target values this index should be assigned
7085 // to. This reflects whether the high elements are remaining or the low
7086 // elements are remaining.
7087 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7089 // Either set up this value if we've not encountered it before, or check
7090 // that it remains consistent.
7093 else if (TargetV != MaskV)
7094 // This may be a rotation, but it pulls from the inputs in some
7095 // unsupported interleaving.
7100 // Check that we successfully analyzed the mask, and normalize the results.
7101 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7102 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7108 // The actual rotate instruction rotates bytes, so we need to scale the
7109 // rotation based on how many bytes are in the vector lane.
7110 int Scale = 16 / NumLaneElts;
7112 // SSSE3 targets can use the palignr instruction.
7113 if (Subtarget->hasSSSE3()) {
7114 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7115 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7116 Lo = DAG.getBitcast(AlignVT, Lo);
7117 Hi = DAG.getBitcast(AlignVT, Hi);
7119 return DAG.getBitcast(
7120 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7121 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7124 assert(VT.getSizeInBits() == 128 &&
7125 "Rotate-based lowering only supports 128-bit lowering!");
7126 assert(Mask.size() <= 16 &&
7127 "Can shuffle at most 16 bytes in a 128-bit vector!");
7129 // Default SSE2 implementation
7130 int LoByteShift = 16 - Rotation * Scale;
7131 int HiByteShift = Rotation * Scale;
7133 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7134 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7135 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7137 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7138 DAG.getConstant(LoByteShift, DL, MVT::i8));
7139 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7140 DAG.getConstant(HiByteShift, DL, MVT::i8));
7141 return DAG.getBitcast(VT,
7142 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7145 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7147 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7148 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7149 /// matches elements from one of the input vectors shuffled to the left or
7150 /// right with zeroable elements 'shifted in'. It handles both the strictly
7151 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7154 /// PSHL : (little-endian) left bit shift.
7155 /// [ zz, 0, zz, 2 ]
7156 /// [ -1, 4, zz, -1 ]
7157 /// PSRL : (little-endian) right bit shift.
7159 /// [ -1, -1, 7, zz]
7160 /// PSLLDQ : (little-endian) left byte shift
7161 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7162 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7163 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7164 /// PSRLDQ : (little-endian) right byte shift
7165 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7166 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7167 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7168 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7169 SDValue V2, ArrayRef<int> Mask,
7170 SelectionDAG &DAG) {
7171 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7173 int Size = Mask.size();
7174 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7176 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7177 for (int i = 0; i < Size; i += Scale)
7178 for (int j = 0; j < Shift; ++j)
7179 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7185 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7186 for (int i = 0; i != Size; i += Scale) {
7187 unsigned Pos = Left ? i + Shift : i;
7188 unsigned Low = Left ? i : i + Shift;
7189 unsigned Len = Scale - Shift;
7190 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7191 Low + (V == V1 ? 0 : Size)))
7195 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7196 bool ByteShift = ShiftEltBits > 64;
7197 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7198 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7199 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7201 // Normalize the scale for byte shifts to still produce an i64 element
7203 Scale = ByteShift ? Scale / 2 : Scale;
7205 // We need to round trip through the appropriate type for the shift.
7206 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7207 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7208 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7209 "Illegal integer vector type");
7210 V = DAG.getBitcast(ShiftVT, V);
7212 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7213 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7214 return DAG.getBitcast(VT, V);
7217 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7218 // keep doubling the size of the integer elements up to that. We can
7219 // then shift the elements of the integer vector by whole multiples of
7220 // their width within the elements of the larger integer vector. Test each
7221 // multiple to see if we can find a match with the moved element indices
7222 // and that the shifted in elements are all zeroable.
7223 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7224 for (int Shift = 1; Shift != Scale; ++Shift)
7225 for (bool Left : {true, false})
7226 if (CheckZeros(Shift, Scale, Left))
7227 for (SDValue V : {V1, V2})
7228 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7235 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7236 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7237 SDValue V2, ArrayRef<int> Mask,
7238 SelectionDAG &DAG) {
7239 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7240 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7242 int Size = Mask.size();
7243 int HalfSize = Size / 2;
7244 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7246 // Upper half must be undefined.
7247 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7250 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7251 // Remainder of lower half result is zero and upper half is all undef.
7252 auto LowerAsEXTRQ = [&]() {
7253 // Determine the extraction length from the part of the
7254 // lower half that isn't zeroable.
7256 for (; Len >= 0; --Len)
7257 if (!Zeroable[Len - 1])
7259 assert(Len > 0 && "Zeroable shuffle mask");
7261 // Attempt to match first Len sequential elements from the lower half.
7264 for (int i = 0; i != Len; ++i) {
7268 SDValue &V = (M < Size ? V1 : V2);
7271 // All mask elements must be in the lower half.
7275 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7286 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7287 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7288 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7289 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7290 DAG.getConstant(BitLen, DL, MVT::i8),
7291 DAG.getConstant(BitIdx, DL, MVT::i8));
7294 if (SDValue ExtrQ = LowerAsEXTRQ())
7297 // INSERTQ: Extract lowest Len elements from lower half of second source and
7298 // insert over first source, starting at Idx.
7299 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7300 auto LowerAsInsertQ = [&]() {
7301 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7304 // Attempt to match first source from mask before insertion point.
7305 if (isUndefInRange(Mask, 0, Idx)) {
7307 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7309 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7315 // Extend the extraction length looking to match both the insertion of
7316 // the second source and the remaining elements of the first.
7317 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7322 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7324 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7330 // Match the remaining elements of the lower half.
7331 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7333 } else if ((!Base || (Base == V1)) &&
7334 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7336 } else if ((!Base || (Base == V2)) &&
7337 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7344 // We may not have a base (first source) - this can safely be undefined.
7346 Base = DAG.getUNDEF(VT);
7348 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7349 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7350 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7351 DAG.getConstant(BitLen, DL, MVT::i8),
7352 DAG.getConstant(BitIdx, DL, MVT::i8));
7359 if (SDValue InsertQ = LowerAsInsertQ())
7365 /// \brief Lower a vector shuffle as a zero or any extension.
7367 /// Given a specific number of elements, element bit width, and extension
7368 /// stride, produce either a zero or any extension based on the available
7369 /// features of the subtarget. The extended elements are consecutive and
7370 /// begin and can start from an offseted element index in the input; to
7371 /// avoid excess shuffling the offset must either being in the bottom lane
7372 /// or at the start of a higher lane. All extended elements must be from
7374 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7375 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7376 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7377 assert(Scale > 1 && "Need a scale to extend.");
7378 int EltBits = VT.getScalarSizeInBits();
7379 int NumElements = VT.getVectorNumElements();
7380 int NumEltsPerLane = 128 / EltBits;
7381 int OffsetLane = Offset / NumEltsPerLane;
7382 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7383 "Only 8, 16, and 32 bit elements can be extended.");
7384 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7385 assert(0 <= Offset && "Extension offset must be positive.");
7386 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7387 "Extension offset must be in the first lane or start an upper lane.");
7389 // Check that an index is in same lane as the base offset.
7390 auto SafeOffset = [&](int Idx) {
7391 return OffsetLane == (Idx / NumEltsPerLane);
7394 // Shift along an input so that the offset base moves to the first element.
7395 auto ShuffleOffset = [&](SDValue V) {
7399 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7400 for (int i = 0; i * Scale < NumElements; ++i) {
7401 int SrcIdx = i + Offset;
7402 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7404 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7407 // Found a valid zext mask! Try various lowering strategies based on the
7408 // input type and available ISA extensions.
7409 if (Subtarget->hasSSE41()) {
7410 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7411 // PUNPCK will catch this in a later shuffle match.
7412 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7414 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7415 NumElements / Scale);
7416 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7417 return DAG.getBitcast(VT, InputV);
7420 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7422 // For any extends we can cheat for larger element sizes and use shuffle
7423 // instructions that can fold with a load and/or copy.
7424 if (AnyExt && EltBits == 32) {
7425 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7427 return DAG.getBitcast(
7428 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7429 DAG.getBitcast(MVT::v4i32, InputV),
7430 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7432 if (AnyExt && EltBits == 16 && Scale > 2) {
7433 int PSHUFDMask[4] = {Offset / 2, -1,
7434 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7435 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7436 DAG.getBitcast(MVT::v4i32, InputV),
7437 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7438 int PSHUFWMask[4] = {1, -1, -1, -1};
7439 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7440 return DAG.getBitcast(
7441 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7442 DAG.getBitcast(MVT::v8i16, InputV),
7443 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7446 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7448 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7449 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7450 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7452 int LoIdx = Offset * EltBits;
7453 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7454 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7455 DAG.getConstant(EltBits, DL, MVT::i8),
7456 DAG.getConstant(LoIdx, DL, MVT::i8)));
7458 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7459 !SafeOffset(Offset + 1))
7460 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7462 int HiIdx = (Offset + 1) * EltBits;
7463 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7464 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7465 DAG.getConstant(EltBits, DL, MVT::i8),
7466 DAG.getConstant(HiIdx, DL, MVT::i8)));
7467 return DAG.getNode(ISD::BITCAST, DL, VT,
7468 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7471 // If this would require more than 2 unpack instructions to expand, use
7472 // pshufb when available. We can only use more than 2 unpack instructions
7473 // when zero extending i8 elements which also makes it easier to use pshufb.
7474 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7475 assert(NumElements == 16 && "Unexpected byte vector width!");
7476 SDValue PSHUFBMask[16];
7477 for (int i = 0; i < 16; ++i) {
7478 int Idx = Offset + (i / Scale);
7479 PSHUFBMask[i] = DAG.getConstant(
7480 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7482 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7483 return DAG.getBitcast(VT,
7484 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7485 DAG.getNode(ISD::BUILD_VECTOR, DL,
7486 MVT::v16i8, PSHUFBMask)));
7489 // If we are extending from an offset, ensure we start on a boundary that
7490 // we can unpack from.
7491 int AlignToUnpack = Offset % (NumElements / Scale);
7492 if (AlignToUnpack) {
7493 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7494 for (int i = AlignToUnpack; i < NumElements; ++i)
7495 ShMask[i - AlignToUnpack] = i;
7496 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7497 Offset -= AlignToUnpack;
7500 // Otherwise emit a sequence of unpacks.
7502 unsigned UnpackLoHi = X86ISD::UNPCKL;
7503 if (Offset >= (NumElements / 2)) {
7504 UnpackLoHi = X86ISD::UNPCKH;
7505 Offset -= (NumElements / 2);
7508 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7509 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7510 : getZeroVector(InputVT, Subtarget, DAG, DL);
7511 InputV = DAG.getBitcast(InputVT, InputV);
7512 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7516 } while (Scale > 1);
7517 return DAG.getBitcast(VT, InputV);
7520 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7522 /// This routine will try to do everything in its power to cleverly lower
7523 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7524 /// check for the profitability of this lowering, it tries to aggressively
7525 /// match this pattern. It will use all of the micro-architectural details it
7526 /// can to emit an efficient lowering. It handles both blends with all-zero
7527 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7528 /// masking out later).
7530 /// The reason we have dedicated lowering for zext-style shuffles is that they
7531 /// are both incredibly common and often quite performance sensitive.
7532 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7533 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7534 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7535 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7537 int Bits = VT.getSizeInBits();
7538 int NumLanes = Bits / 128;
7539 int NumElements = VT.getVectorNumElements();
7540 int NumEltsPerLane = NumElements / NumLanes;
7541 assert(VT.getScalarSizeInBits() <= 32 &&
7542 "Exceeds 32-bit integer zero extension limit");
7543 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7545 // Define a helper function to check a particular ext-scale and lower to it if
7547 auto Lower = [&](int Scale) -> SDValue {
7552 for (int i = 0; i < NumElements; ++i) {
7555 continue; // Valid anywhere but doesn't tell us anything.
7556 if (i % Scale != 0) {
7557 // Each of the extended elements need to be zeroable.
7561 // We no longer are in the anyext case.
7566 // Each of the base elements needs to be consecutive indices into the
7567 // same input vector.
7568 SDValue V = M < NumElements ? V1 : V2;
7569 M = M % NumElements;
7572 Offset = M - (i / Scale);
7573 } else if (InputV != V)
7574 return SDValue(); // Flip-flopping inputs.
7576 // Offset must start in the lowest 128-bit lane or at the start of an
7578 // FIXME: Is it ever worth allowing a negative base offset?
7579 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7580 (Offset % NumEltsPerLane) == 0))
7583 // If we are offsetting, all referenced entries must come from the same
7585 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7588 if ((M % NumElements) != (Offset + (i / Scale)))
7589 return SDValue(); // Non-consecutive strided elements.
7593 // If we fail to find an input, we have a zero-shuffle which should always
7594 // have already been handled.
7595 // FIXME: Maybe handle this here in case during blending we end up with one?
7599 // If we are offsetting, don't extend if we only match a single input, we
7600 // can always do better by using a basic PSHUF or PUNPCK.
7601 if (Offset != 0 && Matches < 2)
7604 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7605 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7608 // The widest scale possible for extending is to a 64-bit integer.
7609 assert(Bits % 64 == 0 &&
7610 "The number of bits in a vector must be divisible by 64 on x86!");
7611 int NumExtElements = Bits / 64;
7613 // Each iteration, try extending the elements half as much, but into twice as
7615 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7616 assert(NumElements % NumExtElements == 0 &&
7617 "The input vector size must be divisible by the extended size.");
7618 if (SDValue V = Lower(NumElements / NumExtElements))
7622 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7626 // Returns one of the source operands if the shuffle can be reduced to a
7627 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7628 auto CanZExtLowHalf = [&]() {
7629 for (int i = NumElements / 2; i != NumElements; ++i)
7632 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7634 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7639 if (SDValue V = CanZExtLowHalf()) {
7640 V = DAG.getBitcast(MVT::v2i64, V);
7641 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7642 return DAG.getBitcast(VT, V);
7645 // No viable ext lowering found.
7649 /// \brief Try to get a scalar value for a specific element of a vector.
7651 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7652 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7653 SelectionDAG &DAG) {
7654 MVT VT = V.getSimpleValueType();
7655 MVT EltVT = VT.getVectorElementType();
7656 while (V.getOpcode() == ISD::BITCAST)
7657 V = V.getOperand(0);
7658 // If the bitcasts shift the element size, we can't extract an equivalent
7660 MVT NewVT = V.getSimpleValueType();
7661 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7664 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7665 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7666 // Ensure the scalar operand is the same size as the destination.
7667 // FIXME: Add support for scalar truncation where possible.
7668 SDValue S = V.getOperand(Idx);
7669 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7670 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7676 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7678 /// This is particularly important because the set of instructions varies
7679 /// significantly based on whether the operand is a load or not.
7680 static bool isShuffleFoldableLoad(SDValue V) {
7681 while (V.getOpcode() == ISD::BITCAST)
7682 V = V.getOperand(0);
7684 return ISD::isNON_EXTLoad(V.getNode());
7687 /// \brief Try to lower insertion of a single element into a zero vector.
7689 /// This is a common pattern that we have especially efficient patterns to lower
7690 /// across all subtarget feature sets.
7691 static SDValue lowerVectorShuffleAsElementInsertion(
7692 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7693 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7694 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7696 MVT EltVT = VT.getVectorElementType();
7698 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7699 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7701 bool IsV1Zeroable = true;
7702 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7703 if (i != V2Index && !Zeroable[i]) {
7704 IsV1Zeroable = false;
7708 // Check for a single input from a SCALAR_TO_VECTOR node.
7709 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7710 // all the smarts here sunk into that routine. However, the current
7711 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7712 // vector shuffle lowering is dead.
7713 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7715 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7716 // We need to zext the scalar if it is smaller than an i32.
7717 V2S = DAG.getBitcast(EltVT, V2S);
7718 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7719 // Using zext to expand a narrow element won't work for non-zero
7724 // Zero-extend directly to i32.
7726 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7728 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7729 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7730 EltVT == MVT::i16) {
7731 // Either not inserting from the low element of the input or the input
7732 // element size is too small to use VZEXT_MOVL to clear the high bits.
7736 if (!IsV1Zeroable) {
7737 // If V1 can't be treated as a zero vector we have fewer options to lower
7738 // this. We can't support integer vectors or non-zero targets cheaply, and
7739 // the V1 elements can't be permuted in any way.
7740 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7741 if (!VT.isFloatingPoint() || V2Index != 0)
7743 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7744 V1Mask[V2Index] = -1;
7745 if (!isNoopShuffleMask(V1Mask))
7747 // This is essentially a special case blend operation, but if we have
7748 // general purpose blend operations, they are always faster. Bail and let
7749 // the rest of the lowering handle these as blends.
7750 if (Subtarget->hasSSE41())
7753 // Otherwise, use MOVSD or MOVSS.
7754 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7755 "Only two types of floating point element types to handle!");
7756 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7760 // This lowering only works for the low element with floating point vectors.
7761 if (VT.isFloatingPoint() && V2Index != 0)
7764 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7766 V2 = DAG.getBitcast(VT, V2);
7769 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7770 // the desired position. Otherwise it is more efficient to do a vector
7771 // shift left. We know that we can do a vector shift left because all
7772 // the inputs are zero.
7773 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7774 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7775 V2Shuffle[V2Index] = 0;
7776 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7778 V2 = DAG.getBitcast(MVT::v2i64, V2);
7780 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7781 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7782 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7783 DAG.getDataLayout(), VT)));
7784 V2 = DAG.getBitcast(VT, V2);
7790 /// \brief Try to lower broadcast of a single element.
7792 /// For convenience, this code also bundles all of the subtarget feature set
7793 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7794 /// a convenient way to factor it out.
7795 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7797 const X86Subtarget *Subtarget,
7798 SelectionDAG &DAG) {
7799 if (!Subtarget->hasAVX())
7801 if (VT.isInteger() && !Subtarget->hasAVX2())
7804 // Check that the mask is a broadcast.
7805 int BroadcastIdx = -1;
7807 if (M >= 0 && BroadcastIdx == -1)
7809 else if (M >= 0 && M != BroadcastIdx)
7812 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7813 "a sorted mask where the broadcast "
7816 // Go up the chain of (vector) values to find a scalar load that we can
7817 // combine with the broadcast.
7819 switch (V.getOpcode()) {
7820 case ISD::CONCAT_VECTORS: {
7821 int OperandSize = Mask.size() / V.getNumOperands();
7822 V = V.getOperand(BroadcastIdx / OperandSize);
7823 BroadcastIdx %= OperandSize;
7827 case ISD::INSERT_SUBVECTOR: {
7828 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7829 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7833 int BeginIdx = (int)ConstantIdx->getZExtValue();
7835 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7836 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7837 BroadcastIdx -= BeginIdx;
7848 // Check if this is a broadcast of a scalar. We special case lowering
7849 // for scalars so that we can more effectively fold with loads.
7850 // First, look through bitcast: if the original value has a larger element
7851 // type than the shuffle, the broadcast element is in essence truncated.
7852 // Make that explicit to ease folding.
7853 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7854 EVT EltVT = VT.getVectorElementType();
7855 SDValue V0 = V.getOperand(0);
7856 EVT V0VT = V0.getValueType();
7858 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7859 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7860 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7861 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7866 // Also check the simpler case, where we can directly reuse the scalar.
7867 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7868 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7869 V = V.getOperand(BroadcastIdx);
7871 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7872 // Only AVX2 has register broadcasts.
7873 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7875 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7876 // We can't broadcast from a vector register without AVX2, and we can only
7877 // broadcast from the zero-element of a vector register.
7881 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7884 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7885 // INSERTPS when the V1 elements are already in the correct locations
7886 // because otherwise we can just always use two SHUFPS instructions which
7887 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7888 // perform INSERTPS if a single V1 element is out of place and all V2
7889 // elements are zeroable.
7890 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7892 SelectionDAG &DAG) {
7893 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7894 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7895 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7896 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7898 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7901 int V1DstIndex = -1;
7902 int V2DstIndex = -1;
7903 bool V1UsedInPlace = false;
7905 for (int i = 0; i < 4; ++i) {
7906 // Synthesize a zero mask from the zeroable elements (includes undefs).
7912 // Flag if we use any V1 inputs in place.
7914 V1UsedInPlace = true;
7918 // We can only insert a single non-zeroable element.
7919 if (V1DstIndex != -1 || V2DstIndex != -1)
7923 // V1 input out of place for insertion.
7926 // V2 input for insertion.
7931 // Don't bother if we have no (non-zeroable) element for insertion.
7932 if (V1DstIndex == -1 && V2DstIndex == -1)
7935 // Determine element insertion src/dst indices. The src index is from the
7936 // start of the inserted vector, not the start of the concatenated vector.
7937 unsigned V2SrcIndex = 0;
7938 if (V1DstIndex != -1) {
7939 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7940 // and don't use the original V2 at all.
7941 V2SrcIndex = Mask[V1DstIndex];
7942 V2DstIndex = V1DstIndex;
7945 V2SrcIndex = Mask[V2DstIndex] - 4;
7948 // If no V1 inputs are used in place, then the result is created only from
7949 // the zero mask and the V2 insertion - so remove V1 dependency.
7951 V1 = DAG.getUNDEF(MVT::v4f32);
7953 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7954 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7956 // Insert the V2 element into the desired position.
7958 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7959 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7962 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7963 /// UNPCK instruction.
7965 /// This specifically targets cases where we end up with alternating between
7966 /// the two inputs, and so can permute them into something that feeds a single
7967 /// UNPCK instruction. Note that this routine only targets integer vectors
7968 /// because for floating point vectors we have a generalized SHUFPS lowering
7969 /// strategy that handles everything that doesn't *exactly* match an unpack,
7970 /// making this clever lowering unnecessary.
7971 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
7972 SDValue V1, SDValue V2,
7974 SelectionDAG &DAG) {
7975 assert(!VT.isFloatingPoint() &&
7976 "This routine only supports integer vectors.");
7977 assert(!isSingleInputShuffleMask(Mask) &&
7978 "This routine should only be used when blending two inputs.");
7979 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7981 int Size = Mask.size();
7983 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7984 return M >= 0 && M % Size < Size / 2;
7986 int NumHiInputs = std::count_if(
7987 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7989 bool UnpackLo = NumLoInputs >= NumHiInputs;
7991 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7992 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7993 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7995 for (int i = 0; i < Size; ++i) {
7999 // Each element of the unpack contains Scale elements from this mask.
8000 int UnpackIdx = i / Scale;
8002 // We only handle the case where V1 feeds the first slots of the unpack.
8003 // We rely on canonicalization to ensure this is the case.
8004 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8007 // Setup the mask for this input. The indexing is tricky as we have to
8008 // handle the unpack stride.
8009 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8010 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8014 // If we will have to shuffle both inputs to use the unpack, check whether
8015 // we can just unpack first and shuffle the result. If so, skip this unpack.
8016 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8017 !isNoopShuffleMask(V2Mask))
8020 // Shuffle the inputs into place.
8021 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8022 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8024 // Cast the inputs to the type we will use to unpack them.
8025 V1 = DAG.getBitcast(UnpackVT, V1);
8026 V2 = DAG.getBitcast(UnpackVT, V2);
8028 // Unpack the inputs and cast the result back to the desired type.
8029 return DAG.getBitcast(
8030 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8034 // We try each unpack from the largest to the smallest to try and find one
8035 // that fits this mask.
8036 int OrigNumElements = VT.getVectorNumElements();
8037 int OrigScalarSize = VT.getScalarSizeInBits();
8038 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8039 int Scale = ScalarSize / OrigScalarSize;
8040 int NumElements = OrigNumElements / Scale;
8041 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8042 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8046 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8048 if (NumLoInputs == 0 || NumHiInputs == 0) {
8049 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8050 "We have to have *some* inputs!");
8051 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8053 // FIXME: We could consider the total complexity of the permute of each
8054 // possible unpacking. Or at the least we should consider how many
8055 // half-crossings are created.
8056 // FIXME: We could consider commuting the unpacks.
8058 SmallVector<int, 32> PermMask;
8059 PermMask.assign(Size, -1);
8060 for (int i = 0; i < Size; ++i) {
8064 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8067 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8069 return DAG.getVectorShuffle(
8070 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8072 DAG.getUNDEF(VT), PermMask);
8078 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8080 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8081 /// support for floating point shuffles but not integer shuffles. These
8082 /// instructions will incur a domain crossing penalty on some chips though so
8083 /// it is better to avoid lowering through this for integer vectors where
8085 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8086 const X86Subtarget *Subtarget,
8087 SelectionDAG &DAG) {
8089 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8090 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8091 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8092 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8093 ArrayRef<int> Mask = SVOp->getMask();
8094 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8096 if (isSingleInputShuffleMask(Mask)) {
8097 // Use low duplicate instructions for masks that match their pattern.
8098 if (Subtarget->hasSSE3())
8099 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8100 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8102 // Straight shuffle of a single input vector. Simulate this by using the
8103 // single input as both of the "inputs" to this instruction..
8104 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8106 if (Subtarget->hasAVX()) {
8107 // If we have AVX, we can use VPERMILPS which will allow folding a load
8108 // into the shuffle.
8109 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8110 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8113 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8114 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8116 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8117 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8119 // If we have a single input, insert that into V1 if we can do so cheaply.
8120 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8121 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8122 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8124 // Try inverting the insertion since for v2 masks it is easy to do and we
8125 // can't reliably sort the mask one way or the other.
8126 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8127 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8128 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8129 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8133 // Try to use one of the special instruction patterns to handle two common
8134 // blend patterns if a zero-blend above didn't work.
8135 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8136 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8137 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8138 // We can either use a special instruction to load over the low double or
8139 // to move just the low double.
8141 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8143 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8145 if (Subtarget->hasSSE41())
8146 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8150 // Use dedicated unpack instructions for masks that match their pattern.
8151 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8152 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8153 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8154 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8156 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8157 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8158 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8161 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8163 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8164 /// the integer unit to minimize domain crossing penalties. However, for blends
8165 /// it falls back to the floating point shuffle operation with appropriate bit
8167 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8168 const X86Subtarget *Subtarget,
8169 SelectionDAG &DAG) {
8171 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8172 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8173 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8175 ArrayRef<int> Mask = SVOp->getMask();
8176 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8178 if (isSingleInputShuffleMask(Mask)) {
8179 // Check for being able to broadcast a single element.
8180 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8181 Mask, Subtarget, DAG))
8184 // Straight shuffle of a single input vector. For everything from SSE2
8185 // onward this has a single fast instruction with no scary immediates.
8186 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8187 V1 = DAG.getBitcast(MVT::v4i32, V1);
8188 int WidenedMask[4] = {
8189 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8190 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8191 return DAG.getBitcast(
8193 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8194 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8196 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8197 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8198 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8199 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8201 // If we have a blend of two PACKUS operations an the blend aligns with the
8202 // low and half halves, we can just merge the PACKUS operations. This is
8203 // particularly important as it lets us merge shuffles that this routine itself
8205 auto GetPackNode = [](SDValue V) {
8206 while (V.getOpcode() == ISD::BITCAST)
8207 V = V.getOperand(0);
8209 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8211 if (SDValue V1Pack = GetPackNode(V1))
8212 if (SDValue V2Pack = GetPackNode(V2))
8213 return DAG.getBitcast(MVT::v2i64,
8214 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8215 Mask[0] == 0 ? V1Pack.getOperand(0)
8216 : V1Pack.getOperand(1),
8217 Mask[1] == 2 ? V2Pack.getOperand(0)
8218 : V2Pack.getOperand(1)));
8220 // Try to use shift instructions.
8222 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8225 // When loading a scalar and then shuffling it into a vector we can often do
8226 // the insertion cheaply.
8227 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8228 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8230 // Try inverting the insertion since for v2 masks it is easy to do and we
8231 // can't reliably sort the mask one way or the other.
8232 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8233 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8234 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8237 // We have different paths for blend lowering, but they all must use the
8238 // *exact* same predicate.
8239 bool IsBlendSupported = Subtarget->hasSSE41();
8240 if (IsBlendSupported)
8241 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8245 // Use dedicated unpack instructions for masks that match their pattern.
8246 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8247 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8248 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8249 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8251 // Try to use byte rotation instructions.
8252 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8253 if (Subtarget->hasSSSE3())
8254 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8255 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8258 // If we have direct support for blends, we should lower by decomposing into
8259 // a permute. That will be faster than the domain cross.
8260 if (IsBlendSupported)
8261 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8264 // We implement this with SHUFPD which is pretty lame because it will likely
8265 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8266 // However, all the alternatives are still more cycles and newer chips don't
8267 // have this problem. It would be really nice if x86 had better shuffles here.
8268 V1 = DAG.getBitcast(MVT::v2f64, V1);
8269 V2 = DAG.getBitcast(MVT::v2f64, V2);
8270 return DAG.getBitcast(MVT::v2i64,
8271 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8274 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8276 /// This is used to disable more specialized lowerings when the shufps lowering
8277 /// will happen to be efficient.
8278 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8279 // This routine only handles 128-bit shufps.
8280 assert(Mask.size() == 4 && "Unsupported mask size!");
8282 // To lower with a single SHUFPS we need to have the low half and high half
8283 // each requiring a single input.
8284 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8286 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8292 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8294 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8295 /// It makes no assumptions about whether this is the *best* lowering, it simply
8297 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8298 ArrayRef<int> Mask, SDValue V1,
8299 SDValue V2, SelectionDAG &DAG) {
8300 SDValue LowV = V1, HighV = V2;
8301 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8304 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8306 if (NumV2Elements == 1) {
8308 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8311 // Compute the index adjacent to V2Index and in the same half by toggling
8313 int V2AdjIndex = V2Index ^ 1;
8315 if (Mask[V2AdjIndex] == -1) {
8316 // Handles all the cases where we have a single V2 element and an undef.
8317 // This will only ever happen in the high lanes because we commute the
8318 // vector otherwise.
8320 std::swap(LowV, HighV);
8321 NewMask[V2Index] -= 4;
8323 // Handle the case where the V2 element ends up adjacent to a V1 element.
8324 // To make this work, blend them together as the first step.
8325 int V1Index = V2AdjIndex;
8326 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8327 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8328 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8330 // Now proceed to reconstruct the final blend as we have the necessary
8331 // high or low half formed.
8338 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8339 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8341 } else if (NumV2Elements == 2) {
8342 if (Mask[0] < 4 && Mask[1] < 4) {
8343 // Handle the easy case where we have V1 in the low lanes and V2 in the
8347 } else if (Mask[2] < 4 && Mask[3] < 4) {
8348 // We also handle the reversed case because this utility may get called
8349 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8350 // arrange things in the right direction.
8356 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8357 // trying to place elements directly, just blend them and set up the final
8358 // shuffle to place them.
8360 // The first two blend mask elements are for V1, the second two are for
8362 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8363 Mask[2] < 4 ? Mask[2] : Mask[3],
8364 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8365 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8366 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8367 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8369 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8372 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8373 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8374 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8375 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8378 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8379 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8382 /// \brief Lower 4-lane 32-bit floating point shuffles.
8384 /// Uses instructions exclusively from the floating point unit to minimize
8385 /// domain crossing penalties, as these are sufficient to implement all v4f32
8387 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8388 const X86Subtarget *Subtarget,
8389 SelectionDAG &DAG) {
8391 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8392 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8393 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8395 ArrayRef<int> Mask = SVOp->getMask();
8396 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8399 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8401 if (NumV2Elements == 0) {
8402 // Check for being able to broadcast a single element.
8403 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8404 Mask, Subtarget, DAG))
8407 // Use even/odd duplicate instructions for masks that match their pattern.
8408 if (Subtarget->hasSSE3()) {
8409 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8410 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8411 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8412 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8415 if (Subtarget->hasAVX()) {
8416 // If we have AVX, we can use VPERMILPS which will allow folding a load
8417 // into the shuffle.
8418 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8419 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8422 // Otherwise, use a straight shuffle of a single input vector. We pass the
8423 // input vector to both operands to simulate this with a SHUFPS.
8424 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8425 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8428 // There are special ways we can lower some single-element blends. However, we
8429 // have custom ways we can lower more complex single-element blends below that
8430 // we defer to if both this and BLENDPS fail to match, so restrict this to
8431 // when the V2 input is targeting element 0 of the mask -- that is the fast
8433 if (NumV2Elements == 1 && Mask[0] >= 4)
8434 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8435 Mask, Subtarget, DAG))
8438 if (Subtarget->hasSSE41()) {
8439 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8443 // Use INSERTPS if we can complete the shuffle efficiently.
8444 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8447 if (!isSingleSHUFPSMask(Mask))
8448 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8449 DL, MVT::v4f32, V1, V2, Mask, DAG))
8453 // Use dedicated unpack instructions for masks that match their pattern.
8454 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8455 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8456 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8457 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8458 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8459 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8460 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8461 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8463 // Otherwise fall back to a SHUFPS lowering strategy.
8464 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8467 /// \brief Lower 4-lane i32 vector shuffles.
8469 /// We try to handle these with integer-domain shuffles where we can, but for
8470 /// blends we use the floating point domain blend instructions.
8471 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8472 const X86Subtarget *Subtarget,
8473 SelectionDAG &DAG) {
8475 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8476 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8477 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8479 ArrayRef<int> Mask = SVOp->getMask();
8480 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8482 // Whenever we can lower this as a zext, that instruction is strictly faster
8483 // than any alternative. It also allows us to fold memory operands into the
8484 // shuffle in many cases.
8485 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8486 Mask, Subtarget, DAG))
8490 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8492 if (NumV2Elements == 0) {
8493 // Check for being able to broadcast a single element.
8494 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8495 Mask, Subtarget, DAG))
8498 // Straight shuffle of a single input vector. For everything from SSE2
8499 // onward this has a single fast instruction with no scary immediates.
8500 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8501 // but we aren't actually going to use the UNPCK instruction because doing
8502 // so prevents folding a load into this instruction or making a copy.
8503 const int UnpackLoMask[] = {0, 0, 1, 1};
8504 const int UnpackHiMask[] = {2, 2, 3, 3};
8505 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8506 Mask = UnpackLoMask;
8507 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8508 Mask = UnpackHiMask;
8510 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8511 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8514 // Try to use shift instructions.
8516 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8519 // There are special ways we can lower some single-element blends.
8520 if (NumV2Elements == 1)
8521 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8522 Mask, Subtarget, DAG))
8525 // We have different paths for blend lowering, but they all must use the
8526 // *exact* same predicate.
8527 bool IsBlendSupported = Subtarget->hasSSE41();
8528 if (IsBlendSupported)
8529 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8533 if (SDValue Masked =
8534 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8537 // Use dedicated unpack instructions for masks that match their pattern.
8538 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8539 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8540 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8541 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8542 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8543 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8544 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8545 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8547 // Try to use byte rotation instructions.
8548 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8549 if (Subtarget->hasSSSE3())
8550 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8551 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8554 // If we have direct support for blends, we should lower by decomposing into
8555 // a permute. That will be faster than the domain cross.
8556 if (IsBlendSupported)
8557 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8560 // Try to lower by permuting the inputs into an unpack instruction.
8561 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8565 // We implement this with SHUFPS because it can blend from two vectors.
8566 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8567 // up the inputs, bypassing domain shift penalties that we would encur if we
8568 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8570 return DAG.getBitcast(
8572 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8573 DAG.getBitcast(MVT::v4f32, V2), Mask));
8576 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8577 /// shuffle lowering, and the most complex part.
8579 /// The lowering strategy is to try to form pairs of input lanes which are
8580 /// targeted at the same half of the final vector, and then use a dword shuffle
8581 /// to place them onto the right half, and finally unpack the paired lanes into
8582 /// their final position.
8584 /// The exact breakdown of how to form these dword pairs and align them on the
8585 /// correct sides is really tricky. See the comments within the function for
8586 /// more of the details.
8588 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8589 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8590 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8591 /// vector, form the analogous 128-bit 8-element Mask.
8592 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8593 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8594 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8595 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8596 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8598 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8599 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8600 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8602 SmallVector<int, 4> LoInputs;
8603 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8604 [](int M) { return M >= 0; });
8605 std::sort(LoInputs.begin(), LoInputs.end());
8606 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8607 SmallVector<int, 4> HiInputs;
8608 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8609 [](int M) { return M >= 0; });
8610 std::sort(HiInputs.begin(), HiInputs.end());
8611 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8613 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8614 int NumHToL = LoInputs.size() - NumLToL;
8616 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8617 int NumHToH = HiInputs.size() - NumLToH;
8618 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8619 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8620 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8621 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8623 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8624 // such inputs we can swap two of the dwords across the half mark and end up
8625 // with <=2 inputs to each half in each half. Once there, we can fall through
8626 // to the generic code below. For example:
8628 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8629 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8631 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8632 // and an existing 2-into-2 on the other half. In this case we may have to
8633 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8634 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8635 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8636 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8637 // half than the one we target for fixing) will be fixed when we re-enter this
8638 // path. We will also combine away any sequence of PSHUFD instructions that
8639 // result into a single instruction. Here is an example of the tricky case:
8641 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8642 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8644 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8646 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8647 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8649 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8650 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8652 // The result is fine to be handled by the generic logic.
8653 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8654 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8655 int AOffset, int BOffset) {
8656 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8657 "Must call this with A having 3 or 1 inputs from the A half.");
8658 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8659 "Must call this with B having 1 or 3 inputs from the B half.");
8660 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8661 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8663 bool ThreeAInputs = AToAInputs.size() == 3;
8665 // Compute the index of dword with only one word among the three inputs in
8666 // a half by taking the sum of the half with three inputs and subtracting
8667 // the sum of the actual three inputs. The difference is the remaining
8670 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8671 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8672 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8673 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8674 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8675 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8676 int TripleNonInputIdx =
8677 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8678 TripleDWord = TripleNonInputIdx / 2;
8680 // We use xor with one to compute the adjacent DWord to whichever one the
8682 OneInputDWord = (OneInput / 2) ^ 1;
8684 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8685 // and BToA inputs. If there is also such a problem with the BToB and AToB
8686 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8687 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8688 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8689 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8690 // Compute how many inputs will be flipped by swapping these DWords. We
8692 // to balance this to ensure we don't form a 3-1 shuffle in the other
8694 int NumFlippedAToBInputs =
8695 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8696 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8697 int NumFlippedBToBInputs =
8698 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8699 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8700 if ((NumFlippedAToBInputs == 1 &&
8701 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8702 (NumFlippedBToBInputs == 1 &&
8703 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8704 // We choose whether to fix the A half or B half based on whether that
8705 // half has zero flipped inputs. At zero, we may not be able to fix it
8706 // with that half. We also bias towards fixing the B half because that
8707 // will more commonly be the high half, and we have to bias one way.
8708 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8709 ArrayRef<int> Inputs) {
8710 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8711 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8712 PinnedIdx ^ 1) != Inputs.end();
8713 // Determine whether the free index is in the flipped dword or the
8714 // unflipped dword based on where the pinned index is. We use this bit
8715 // in an xor to conditionally select the adjacent dword.
8716 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8717 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8718 FixFreeIdx) != Inputs.end();
8719 if (IsFixIdxInput == IsFixFreeIdxInput)
8721 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8722 FixFreeIdx) != Inputs.end();
8723 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8724 "We need to be changing the number of flipped inputs!");
8725 int PSHUFHalfMask[] = {0, 1, 2, 3};
8726 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8727 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8729 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8732 if (M != -1 && M == FixIdx)
8734 else if (M != -1 && M == FixFreeIdx)
8737 if (NumFlippedBToBInputs != 0) {
8739 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8740 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8742 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8743 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8744 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8749 int PSHUFDMask[] = {0, 1, 2, 3};
8750 PSHUFDMask[ADWord] = BDWord;
8751 PSHUFDMask[BDWord] = ADWord;
8754 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8755 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8757 // Adjust the mask to match the new locations of A and B.
8759 if (M != -1 && M/2 == ADWord)
8760 M = 2 * BDWord + M % 2;
8761 else if (M != -1 && M/2 == BDWord)
8762 M = 2 * ADWord + M % 2;
8764 // Recurse back into this routine to re-compute state now that this isn't
8765 // a 3 and 1 problem.
8766 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8769 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8770 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8771 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8772 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8774 // At this point there are at most two inputs to the low and high halves from
8775 // each half. That means the inputs can always be grouped into dwords and
8776 // those dwords can then be moved to the correct half with a dword shuffle.
8777 // We use at most one low and one high word shuffle to collect these paired
8778 // inputs into dwords, and finally a dword shuffle to place them.
8779 int PSHUFLMask[4] = {-1, -1, -1, -1};
8780 int PSHUFHMask[4] = {-1, -1, -1, -1};
8781 int PSHUFDMask[4] = {-1, -1, -1, -1};
8783 // First fix the masks for all the inputs that are staying in their
8784 // original halves. This will then dictate the targets of the cross-half
8786 auto fixInPlaceInputs =
8787 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8788 MutableArrayRef<int> SourceHalfMask,
8789 MutableArrayRef<int> HalfMask, int HalfOffset) {
8790 if (InPlaceInputs.empty())
8792 if (InPlaceInputs.size() == 1) {
8793 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8794 InPlaceInputs[0] - HalfOffset;
8795 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8798 if (IncomingInputs.empty()) {
8799 // Just fix all of the in place inputs.
8800 for (int Input : InPlaceInputs) {
8801 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8802 PSHUFDMask[Input / 2] = Input / 2;
8807 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8808 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8809 InPlaceInputs[0] - HalfOffset;
8810 // Put the second input next to the first so that they are packed into
8811 // a dword. We find the adjacent index by toggling the low bit.
8812 int AdjIndex = InPlaceInputs[0] ^ 1;
8813 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8814 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8815 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8817 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8818 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8820 // Now gather the cross-half inputs and place them into a free dword of
8821 // their target half.
8822 // FIXME: This operation could almost certainly be simplified dramatically to
8823 // look more like the 3-1 fixing operation.
8824 auto moveInputsToRightHalf = [&PSHUFDMask](
8825 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8826 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8827 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8829 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8830 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8832 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8834 int LowWord = Word & ~1;
8835 int HighWord = Word | 1;
8836 return isWordClobbered(SourceHalfMask, LowWord) ||
8837 isWordClobbered(SourceHalfMask, HighWord);
8840 if (IncomingInputs.empty())
8843 if (ExistingInputs.empty()) {
8844 // Map any dwords with inputs from them into the right half.
8845 for (int Input : IncomingInputs) {
8846 // If the source half mask maps over the inputs, turn those into
8847 // swaps and use the swapped lane.
8848 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8849 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8850 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8851 Input - SourceOffset;
8852 // We have to swap the uses in our half mask in one sweep.
8853 for (int &M : HalfMask)
8854 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8856 else if (M == Input)
8857 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8859 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8860 Input - SourceOffset &&
8861 "Previous placement doesn't match!");
8863 // Note that this correctly re-maps both when we do a swap and when
8864 // we observe the other side of the swap above. We rely on that to
8865 // avoid swapping the members of the input list directly.
8866 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8869 // Map the input's dword into the correct half.
8870 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8871 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8873 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8875 "Previous placement doesn't match!");
8878 // And just directly shift any other-half mask elements to be same-half
8879 // as we will have mirrored the dword containing the element into the
8880 // same position within that half.
8881 for (int &M : HalfMask)
8882 if (M >= SourceOffset && M < SourceOffset + 4) {
8883 M = M - SourceOffset + DestOffset;
8884 assert(M >= 0 && "This should never wrap below zero!");
8889 // Ensure we have the input in a viable dword of its current half. This
8890 // is particularly tricky because the original position may be clobbered
8891 // by inputs being moved and *staying* in that half.
8892 if (IncomingInputs.size() == 1) {
8893 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8894 int InputFixed = std::find(std::begin(SourceHalfMask),
8895 std::end(SourceHalfMask), -1) -
8896 std::begin(SourceHalfMask) + SourceOffset;
8897 SourceHalfMask[InputFixed - SourceOffset] =
8898 IncomingInputs[0] - SourceOffset;
8899 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8901 IncomingInputs[0] = InputFixed;
8903 } else if (IncomingInputs.size() == 2) {
8904 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8905 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8906 // We have two non-adjacent or clobbered inputs we need to extract from
8907 // the source half. To do this, we need to map them into some adjacent
8908 // dword slot in the source mask.
8909 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8910 IncomingInputs[1] - SourceOffset};
8912 // If there is a free slot in the source half mask adjacent to one of
8913 // the inputs, place the other input in it. We use (Index XOR 1) to
8914 // compute an adjacent index.
8915 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8916 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8917 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8918 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8919 InputsFixed[1] = InputsFixed[0] ^ 1;
8920 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8921 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8922 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8923 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8924 InputsFixed[0] = InputsFixed[1] ^ 1;
8925 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8926 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8927 // The two inputs are in the same DWord but it is clobbered and the
8928 // adjacent DWord isn't used at all. Move both inputs to the free
8930 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8931 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8932 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8933 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8935 // The only way we hit this point is if there is no clobbering
8936 // (because there are no off-half inputs to this half) and there is no
8937 // free slot adjacent to one of the inputs. In this case, we have to
8938 // swap an input with a non-input.
8939 for (int i = 0; i < 4; ++i)
8940 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8941 "We can't handle any clobbers here!");
8942 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8943 "Cannot have adjacent inputs here!");
8945 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8946 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8948 // We also have to update the final source mask in this case because
8949 // it may need to undo the above swap.
8950 for (int &M : FinalSourceHalfMask)
8951 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8952 M = InputsFixed[1] + SourceOffset;
8953 else if (M == InputsFixed[1] + SourceOffset)
8954 M = (InputsFixed[0] ^ 1) + SourceOffset;
8956 InputsFixed[1] = InputsFixed[0] ^ 1;
8959 // Point everything at the fixed inputs.
8960 for (int &M : HalfMask)
8961 if (M == IncomingInputs[0])
8962 M = InputsFixed[0] + SourceOffset;
8963 else if (M == IncomingInputs[1])
8964 M = InputsFixed[1] + SourceOffset;
8966 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8967 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8970 llvm_unreachable("Unhandled input size!");
8973 // Now hoist the DWord down to the right half.
8974 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8975 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8976 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8977 for (int &M : HalfMask)
8978 for (int Input : IncomingInputs)
8980 M = FreeDWord * 2 + Input % 2;
8982 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8983 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8984 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8985 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8987 // Now enact all the shuffles we've computed to move the inputs into their
8989 if (!isNoopShuffleMask(PSHUFLMask))
8990 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8991 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8992 if (!isNoopShuffleMask(PSHUFHMask))
8993 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8994 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8995 if (!isNoopShuffleMask(PSHUFDMask))
8998 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8999 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9001 // At this point, each half should contain all its inputs, and we can then
9002 // just shuffle them into their final position.
9003 assert(std::count_if(LoMask.begin(), LoMask.end(),
9004 [](int M) { return M >= 4; }) == 0 &&
9005 "Failed to lift all the high half inputs to the low mask!");
9006 assert(std::count_if(HiMask.begin(), HiMask.end(),
9007 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9008 "Failed to lift all the low half inputs to the high mask!");
9010 // Do a half shuffle for the low mask.
9011 if (!isNoopShuffleMask(LoMask))
9012 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9013 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9015 // Do a half shuffle with the high mask after shifting its values down.
9016 for (int &M : HiMask)
9019 if (!isNoopShuffleMask(HiMask))
9020 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9021 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9026 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9027 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9028 SDValue V2, ArrayRef<int> Mask,
9029 SelectionDAG &DAG, bool &V1InUse,
9031 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9037 int Size = Mask.size();
9038 int Scale = 16 / Size;
9039 for (int i = 0; i < 16; ++i) {
9040 if (Mask[i / Scale] == -1) {
9041 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9043 const int ZeroMask = 0x80;
9044 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9046 int V2Idx = Mask[i / Scale] < Size
9048 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9049 if (Zeroable[i / Scale])
9050 V1Idx = V2Idx = ZeroMask;
9051 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9052 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9053 V1InUse |= (ZeroMask != V1Idx);
9054 V2InUse |= (ZeroMask != V2Idx);
9059 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9060 DAG.getBitcast(MVT::v16i8, V1),
9061 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9063 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9064 DAG.getBitcast(MVT::v16i8, V2),
9065 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9067 // If we need shuffled inputs from both, blend the two.
9069 if (V1InUse && V2InUse)
9070 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9072 V = V1InUse ? V1 : V2;
9074 // Cast the result back to the correct type.
9075 return DAG.getBitcast(VT, V);
9078 /// \brief Generic lowering of 8-lane i16 shuffles.
9080 /// This handles both single-input shuffles and combined shuffle/blends with
9081 /// two inputs. The single input shuffles are immediately delegated to
9082 /// a dedicated lowering routine.
9084 /// The blends are lowered in one of three fundamental ways. If there are few
9085 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9086 /// of the input is significantly cheaper when lowered as an interleaving of
9087 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9088 /// halves of the inputs separately (making them have relatively few inputs)
9089 /// and then concatenate them.
9090 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9091 const X86Subtarget *Subtarget,
9092 SelectionDAG &DAG) {
9094 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9095 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9096 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9097 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9098 ArrayRef<int> OrigMask = SVOp->getMask();
9099 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9100 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9101 MutableArrayRef<int> Mask(MaskStorage);
9103 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9105 // Whenever we can lower this as a zext, that instruction is strictly faster
9106 // than any alternative.
9107 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9108 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9111 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9113 auto isV2 = [](int M) { return M >= 8; };
9115 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9117 if (NumV2Inputs == 0) {
9118 // Check for being able to broadcast a single element.
9119 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9120 Mask, Subtarget, DAG))
9123 // Try to use shift instructions.
9125 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9128 // Use dedicated unpack instructions for masks that match their pattern.
9129 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9130 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9131 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9132 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9134 // Try to use byte rotation instructions.
9135 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9136 Mask, Subtarget, DAG))
9139 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9143 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9144 "All single-input shuffles should be canonicalized to be V1-input "
9147 // Try to use shift instructions.
9149 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9152 // See if we can use SSE4A Extraction / Insertion.
9153 if (Subtarget->hasSSE4A())
9154 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9157 // There are special ways we can lower some single-element blends.
9158 if (NumV2Inputs == 1)
9159 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9160 Mask, Subtarget, DAG))
9163 // We have different paths for blend lowering, but they all must use the
9164 // *exact* same predicate.
9165 bool IsBlendSupported = Subtarget->hasSSE41();
9166 if (IsBlendSupported)
9167 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9171 if (SDValue Masked =
9172 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9175 // Use dedicated unpack instructions for masks that match their pattern.
9176 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9177 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9178 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9179 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9181 // Try to use byte rotation instructions.
9182 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9183 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9186 if (SDValue BitBlend =
9187 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9190 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9194 // If we can't directly blend but can use PSHUFB, that will be better as it
9195 // can both shuffle and set up the inefficient blend.
9196 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9197 bool V1InUse, V2InUse;
9198 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9202 // We can always bit-blend if we have to so the fallback strategy is to
9203 // decompose into single-input permutes and blends.
9204 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9208 /// \brief Check whether a compaction lowering can be done by dropping even
9209 /// elements and compute how many times even elements must be dropped.
9211 /// This handles shuffles which take every Nth element where N is a power of
9212 /// two. Example shuffle masks:
9214 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9215 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9216 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9217 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9218 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9219 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9221 /// Any of these lanes can of course be undef.
9223 /// This routine only supports N <= 3.
9224 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9227 /// \returns N above, or the number of times even elements must be dropped if
9228 /// there is such a number. Otherwise returns zero.
9229 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9230 // Figure out whether we're looping over two inputs or just one.
9231 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9233 // The modulus for the shuffle vector entries is based on whether this is
9234 // a single input or not.
9235 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9236 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9237 "We should only be called with masks with a power-of-2 size!");
9239 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9241 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9242 // and 2^3 simultaneously. This is because we may have ambiguity with
9243 // partially undef inputs.
9244 bool ViableForN[3] = {true, true, true};
9246 for (int i = 0, e = Mask.size(); i < e; ++i) {
9247 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9252 bool IsAnyViable = false;
9253 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9254 if (ViableForN[j]) {
9257 // The shuffle mask must be equal to (i * 2^N) % M.
9258 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9261 ViableForN[j] = false;
9263 // Early exit if we exhaust the possible powers of two.
9268 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9272 // Return 0 as there is no viable power of two.
9276 /// \brief Generic lowering of v16i8 shuffles.
9278 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9279 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9280 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9281 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9283 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9284 const X86Subtarget *Subtarget,
9285 SelectionDAG &DAG) {
9287 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9288 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9289 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9290 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9291 ArrayRef<int> Mask = SVOp->getMask();
9292 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9294 // Try to use shift instructions.
9296 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9299 // Try to use byte rotation instructions.
9300 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9301 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9304 // Try to use a zext lowering.
9305 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9306 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9309 // See if we can use SSE4A Extraction / Insertion.
9310 if (Subtarget->hasSSE4A())
9311 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9315 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9317 // For single-input shuffles, there are some nicer lowering tricks we can use.
9318 if (NumV2Elements == 0) {
9319 // Check for being able to broadcast a single element.
9320 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9321 Mask, Subtarget, DAG))
9324 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9325 // Notably, this handles splat and partial-splat shuffles more efficiently.
9326 // However, it only makes sense if the pre-duplication shuffle simplifies
9327 // things significantly. Currently, this means we need to be able to
9328 // express the pre-duplication shuffle as an i16 shuffle.
9330 // FIXME: We should check for other patterns which can be widened into an
9331 // i16 shuffle as well.
9332 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9333 for (int i = 0; i < 16; i += 2)
9334 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9339 auto tryToWidenViaDuplication = [&]() -> SDValue {
9340 if (!canWidenViaDuplication(Mask))
9342 SmallVector<int, 4> LoInputs;
9343 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9344 [](int M) { return M >= 0 && M < 8; });
9345 std::sort(LoInputs.begin(), LoInputs.end());
9346 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9348 SmallVector<int, 4> HiInputs;
9349 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9350 [](int M) { return M >= 8; });
9351 std::sort(HiInputs.begin(), HiInputs.end());
9352 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9355 bool TargetLo = LoInputs.size() >= HiInputs.size();
9356 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9357 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9359 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9360 SmallDenseMap<int, int, 8> LaneMap;
9361 for (int I : InPlaceInputs) {
9362 PreDupI16Shuffle[I/2] = I/2;
9365 int j = TargetLo ? 0 : 4, je = j + 4;
9366 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9367 // Check if j is already a shuffle of this input. This happens when
9368 // there are two adjacent bytes after we move the low one.
9369 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9370 // If we haven't yet mapped the input, search for a slot into which
9372 while (j < je && PreDupI16Shuffle[j] != -1)
9376 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9379 // Map this input with the i16 shuffle.
9380 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9383 // Update the lane map based on the mapping we ended up with.
9384 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9386 V1 = DAG.getBitcast(
9388 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9389 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9391 // Unpack the bytes to form the i16s that will be shuffled into place.
9392 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9393 MVT::v16i8, V1, V1);
9395 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9396 for (int i = 0; i < 16; ++i)
9397 if (Mask[i] != -1) {
9398 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9399 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9400 if (PostDupI16Shuffle[i / 2] == -1)
9401 PostDupI16Shuffle[i / 2] = MappedMask;
9403 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9404 "Conflicting entrties in the original shuffle!");
9406 return DAG.getBitcast(
9408 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9409 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9411 if (SDValue V = tryToWidenViaDuplication())
9415 if (SDValue Masked =
9416 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9419 // Use dedicated unpack instructions for masks that match their pattern.
9420 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9421 0, 16, 1, 17, 2, 18, 3, 19,
9423 4, 20, 5, 21, 6, 22, 7, 23}))
9424 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9425 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9426 8, 24, 9, 25, 10, 26, 11, 27,
9428 12, 28, 13, 29, 14, 30, 15, 31}))
9429 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9431 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9432 // with PSHUFB. It is important to do this before we attempt to generate any
9433 // blends but after all of the single-input lowerings. If the single input
9434 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9435 // want to preserve that and we can DAG combine any longer sequences into
9436 // a PSHUFB in the end. But once we start blending from multiple inputs,
9437 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9438 // and there are *very* few patterns that would actually be faster than the
9439 // PSHUFB approach because of its ability to zero lanes.
9441 // FIXME: The only exceptions to the above are blends which are exact
9442 // interleavings with direct instructions supporting them. We currently don't
9443 // handle those well here.
9444 if (Subtarget->hasSSSE3()) {
9445 bool V1InUse = false;
9446 bool V2InUse = false;
9448 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9449 DAG, V1InUse, V2InUse);
9451 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9452 // do so. This avoids using them to handle blends-with-zero which is
9453 // important as a single pshufb is significantly faster for that.
9454 if (V1InUse && V2InUse) {
9455 if (Subtarget->hasSSE41())
9456 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9457 Mask, Subtarget, DAG))
9460 // We can use an unpack to do the blending rather than an or in some
9461 // cases. Even though the or may be (very minorly) more efficient, we
9462 // preference this lowering because there are common cases where part of
9463 // the complexity of the shuffles goes away when we do the final blend as
9465 // FIXME: It might be worth trying to detect if the unpack-feeding
9466 // shuffles will both be pshufb, in which case we shouldn't bother with
9468 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9469 DL, MVT::v16i8, V1, V2, Mask, DAG))
9476 // There are special ways we can lower some single-element blends.
9477 if (NumV2Elements == 1)
9478 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9479 Mask, Subtarget, DAG))
9482 if (SDValue BitBlend =
9483 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9486 // Check whether a compaction lowering can be done. This handles shuffles
9487 // which take every Nth element for some even N. See the helper function for
9490 // We special case these as they can be particularly efficiently handled with
9491 // the PACKUSB instruction on x86 and they show up in common patterns of
9492 // rearranging bytes to truncate wide elements.
9493 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9494 // NumEvenDrops is the power of two stride of the elements. Another way of
9495 // thinking about it is that we need to drop the even elements this many
9496 // times to get the original input.
9497 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9499 // First we need to zero all the dropped bytes.
9500 assert(NumEvenDrops <= 3 &&
9501 "No support for dropping even elements more than 3 times.");
9502 // We use the mask type to pick which bytes are preserved based on how many
9503 // elements are dropped.
9504 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9505 SDValue ByteClearMask = DAG.getBitcast(
9506 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9507 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9509 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9511 // Now pack things back together.
9512 V1 = DAG.getBitcast(MVT::v8i16, V1);
9513 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9514 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9515 for (int i = 1; i < NumEvenDrops; ++i) {
9516 Result = DAG.getBitcast(MVT::v8i16, Result);
9517 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9523 // Handle multi-input cases by blending single-input shuffles.
9524 if (NumV2Elements > 0)
9525 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9528 // The fallback path for single-input shuffles widens this into two v8i16
9529 // vectors with unpacks, shuffles those, and then pulls them back together
9533 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9534 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9535 for (int i = 0; i < 16; ++i)
9537 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9539 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9541 SDValue VLoHalf, VHiHalf;
9542 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9543 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9545 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9546 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9547 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9548 [](int M) { return M >= 0 && M % 2 == 1; })) {
9549 // Use a mask to drop the high bytes.
9550 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9551 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9552 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9554 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9555 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9557 // Squash the masks to point directly into VLoHalf.
9558 for (int &M : LoBlendMask)
9561 for (int &M : HiBlendMask)
9565 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9566 // VHiHalf so that we can blend them as i16s.
9567 VLoHalf = DAG.getBitcast(
9568 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9569 VHiHalf = DAG.getBitcast(
9570 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9573 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9574 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9576 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9579 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9581 /// This routine breaks down the specific type of 128-bit shuffle and
9582 /// dispatches to the lowering routines accordingly.
9583 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9584 MVT VT, const X86Subtarget *Subtarget,
9585 SelectionDAG &DAG) {
9586 switch (VT.SimpleTy) {
9588 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9590 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9592 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9594 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9596 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9598 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9601 llvm_unreachable("Unimplemented!");
9605 /// \brief Helper function to test whether a shuffle mask could be
9606 /// simplified by widening the elements being shuffled.
9608 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9609 /// leaves it in an unspecified state.
9611 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9612 /// shuffle masks. The latter have the special property of a '-2' representing
9613 /// a zero-ed lane of a vector.
9614 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9615 SmallVectorImpl<int> &WidenedMask) {
9616 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9617 // If both elements are undef, its trivial.
9618 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9619 WidenedMask.push_back(SM_SentinelUndef);
9623 // Check for an undef mask and a mask value properly aligned to fit with
9624 // a pair of values. If we find such a case, use the non-undef mask's value.
9625 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9626 WidenedMask.push_back(Mask[i + 1] / 2);
9629 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9630 WidenedMask.push_back(Mask[i] / 2);
9634 // When zeroing, we need to spread the zeroing across both lanes to widen.
9635 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9636 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9637 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9638 WidenedMask.push_back(SM_SentinelZero);
9644 // Finally check if the two mask values are adjacent and aligned with
9646 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9647 WidenedMask.push_back(Mask[i] / 2);
9651 // Otherwise we can't safely widen the elements used in this shuffle.
9654 assert(WidenedMask.size() == Mask.size() / 2 &&
9655 "Incorrect size of mask after widening the elements!");
9660 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9662 /// This routine just extracts two subvectors, shuffles them independently, and
9663 /// then concatenates them back together. This should work effectively with all
9664 /// AVX vector shuffle types.
9665 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9666 SDValue V2, ArrayRef<int> Mask,
9667 SelectionDAG &DAG) {
9668 assert(VT.getSizeInBits() >= 256 &&
9669 "Only for 256-bit or wider vector shuffles!");
9670 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9671 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9673 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9674 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9676 int NumElements = VT.getVectorNumElements();
9677 int SplitNumElements = NumElements / 2;
9678 MVT ScalarVT = VT.getScalarType();
9679 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9681 // Rather than splitting build-vectors, just build two narrower build
9682 // vectors. This helps shuffling with splats and zeros.
9683 auto SplitVector = [&](SDValue V) {
9684 while (V.getOpcode() == ISD::BITCAST)
9685 V = V->getOperand(0);
9687 MVT OrigVT = V.getSimpleValueType();
9688 int OrigNumElements = OrigVT.getVectorNumElements();
9689 int OrigSplitNumElements = OrigNumElements / 2;
9690 MVT OrigScalarVT = OrigVT.getScalarType();
9691 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9695 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9697 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9698 DAG.getIntPtrConstant(0, DL));
9699 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9700 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9703 SmallVector<SDValue, 16> LoOps, HiOps;
9704 for (int i = 0; i < OrigSplitNumElements; ++i) {
9705 LoOps.push_back(BV->getOperand(i));
9706 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9708 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9709 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9711 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9712 DAG.getBitcast(SplitVT, HiV));
9715 SDValue LoV1, HiV1, LoV2, HiV2;
9716 std::tie(LoV1, HiV1) = SplitVector(V1);
9717 std::tie(LoV2, HiV2) = SplitVector(V2);
9719 // Now create two 4-way blends of these half-width vectors.
9720 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9721 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9722 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9723 for (int i = 0; i < SplitNumElements; ++i) {
9724 int M = HalfMask[i];
9725 if (M >= NumElements) {
9726 if (M >= NumElements + SplitNumElements)
9730 V2BlendMask.push_back(M - NumElements);
9731 V1BlendMask.push_back(-1);
9732 BlendMask.push_back(SplitNumElements + i);
9733 } else if (M >= 0) {
9734 if (M >= SplitNumElements)
9738 V2BlendMask.push_back(-1);
9739 V1BlendMask.push_back(M);
9740 BlendMask.push_back(i);
9742 V2BlendMask.push_back(-1);
9743 V1BlendMask.push_back(-1);
9744 BlendMask.push_back(-1);
9748 // Because the lowering happens after all combining takes place, we need to
9749 // manually combine these blend masks as much as possible so that we create
9750 // a minimal number of high-level vector shuffle nodes.
9752 // First try just blending the halves of V1 or V2.
9753 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9754 return DAG.getUNDEF(SplitVT);
9755 if (!UseLoV2 && !UseHiV2)
9756 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9757 if (!UseLoV1 && !UseHiV1)
9758 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9760 SDValue V1Blend, V2Blend;
9761 if (UseLoV1 && UseHiV1) {
9763 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9765 // We only use half of V1 so map the usage down into the final blend mask.
9766 V1Blend = UseLoV1 ? LoV1 : HiV1;
9767 for (int i = 0; i < SplitNumElements; ++i)
9768 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9769 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9771 if (UseLoV2 && UseHiV2) {
9773 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9775 // We only use half of V2 so map the usage down into the final blend mask.
9776 V2Blend = UseLoV2 ? LoV2 : HiV2;
9777 for (int i = 0; i < SplitNumElements; ++i)
9778 if (BlendMask[i] >= SplitNumElements)
9779 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9781 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9783 SDValue Lo = HalfBlend(LoMask);
9784 SDValue Hi = HalfBlend(HiMask);
9785 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9788 /// \brief Either split a vector in halves or decompose the shuffles and the
9791 /// This is provided as a good fallback for many lowerings of non-single-input
9792 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9793 /// between splitting the shuffle into 128-bit components and stitching those
9794 /// back together vs. extracting the single-input shuffles and blending those
9796 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9797 SDValue V2, ArrayRef<int> Mask,
9798 SelectionDAG &DAG) {
9799 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9800 "lower single-input shuffles as it "
9801 "could then recurse on itself.");
9802 int Size = Mask.size();
9804 // If this can be modeled as a broadcast of two elements followed by a blend,
9805 // prefer that lowering. This is especially important because broadcasts can
9806 // often fold with memory operands.
9807 auto DoBothBroadcast = [&] {
9808 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9811 if (V2BroadcastIdx == -1)
9812 V2BroadcastIdx = M - Size;
9813 else if (M - Size != V2BroadcastIdx)
9815 } else if (M >= 0) {
9816 if (V1BroadcastIdx == -1)
9818 else if (M != V1BroadcastIdx)
9823 if (DoBothBroadcast())
9824 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9827 // If the inputs all stem from a single 128-bit lane of each input, then we
9828 // split them rather than blending because the split will decompose to
9829 // unusually few instructions.
9830 int LaneCount = VT.getSizeInBits() / 128;
9831 int LaneSize = Size / LaneCount;
9832 SmallBitVector LaneInputs[2];
9833 LaneInputs[0].resize(LaneCount, false);
9834 LaneInputs[1].resize(LaneCount, false);
9835 for (int i = 0; i < Size; ++i)
9837 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9838 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9839 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9841 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9842 // that the decomposed single-input shuffles don't end up here.
9843 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9846 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9847 /// a permutation and blend of those lanes.
9849 /// This essentially blends the out-of-lane inputs to each lane into the lane
9850 /// from a permuted copy of the vector. This lowering strategy results in four
9851 /// instructions in the worst case for a single-input cross lane shuffle which
9852 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9853 /// of. Special cases for each particular shuffle pattern should be handled
9854 /// prior to trying this lowering.
9855 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9856 SDValue V1, SDValue V2,
9858 SelectionDAG &DAG) {
9859 // FIXME: This should probably be generalized for 512-bit vectors as well.
9860 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9861 int LaneSize = Mask.size() / 2;
9863 // If there are only inputs from one 128-bit lane, splitting will in fact be
9864 // less expensive. The flags track whether the given lane contains an element
9865 // that crosses to another lane.
9866 bool LaneCrossing[2] = {false, false};
9867 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9868 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9869 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9870 if (!LaneCrossing[0] || !LaneCrossing[1])
9871 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9873 if (isSingleInputShuffleMask(Mask)) {
9874 SmallVector<int, 32> FlippedBlendMask;
9875 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9876 FlippedBlendMask.push_back(
9877 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9879 : Mask[i] % LaneSize +
9880 (i / LaneSize) * LaneSize + Size));
9882 // Flip the vector, and blend the results which should now be in-lane. The
9883 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9884 // 5 for the high source. The value 3 selects the high half of source 2 and
9885 // the value 2 selects the low half of source 2. We only use source 2 to
9886 // allow folding it into a memory operand.
9887 unsigned PERMMask = 3 | 2 << 4;
9888 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9889 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9890 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9893 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9894 // will be handled by the above logic and a blend of the results, much like
9895 // other patterns in AVX.
9896 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9899 /// \brief Handle lowering 2-lane 128-bit shuffles.
9900 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9901 SDValue V2, ArrayRef<int> Mask,
9902 const X86Subtarget *Subtarget,
9903 SelectionDAG &DAG) {
9904 // TODO: If minimizing size and one of the inputs is a zero vector and the
9905 // the zero vector has only one use, we could use a VPERM2X128 to save the
9906 // instruction bytes needed to explicitly generate the zero vector.
9908 // Blends are faster and handle all the non-lane-crossing cases.
9909 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9913 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9914 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9916 // If either input operand is a zero vector, use VPERM2X128 because its mask
9917 // allows us to replace the zero input with an implicit zero.
9918 if (!IsV1Zero && !IsV2Zero) {
9919 // Check for patterns which can be matched with a single insert of a 128-bit
9921 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9922 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9923 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9924 VT.getVectorNumElements() / 2);
9925 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9926 DAG.getIntPtrConstant(0, DL));
9927 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9928 OnlyUsesV1 ? V1 : V2,
9929 DAG.getIntPtrConstant(0, DL));
9930 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9934 // Otherwise form a 128-bit permutation. After accounting for undefs,
9935 // convert the 64-bit shuffle mask selection values into 128-bit
9936 // selection bits by dividing the indexes by 2 and shifting into positions
9937 // defined by a vperm2*128 instruction's immediate control byte.
9939 // The immediate permute control byte looks like this:
9940 // [1:0] - select 128 bits from sources for low half of destination
9942 // [3] - zero low half of destination
9943 // [5:4] - select 128 bits from sources for high half of destination
9945 // [7] - zero high half of destination
9947 int MaskLO = Mask[0];
9948 if (MaskLO == SM_SentinelUndef)
9949 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9951 int MaskHI = Mask[2];
9952 if (MaskHI == SM_SentinelUndef)
9953 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9955 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9957 // If either input is a zero vector, replace it with an undef input.
9958 // Shuffle mask values < 4 are selecting elements of V1.
9959 // Shuffle mask values >= 4 are selecting elements of V2.
9960 // Adjust each half of the permute mask by clearing the half that was
9961 // selecting the zero vector and setting the zero mask bit.
9963 V1 = DAG.getUNDEF(VT);
9965 PermMask = (PermMask & 0xf0) | 0x08;
9967 PermMask = (PermMask & 0x0f) | 0x80;
9970 V2 = DAG.getUNDEF(VT);
9972 PermMask = (PermMask & 0xf0) | 0x08;
9974 PermMask = (PermMask & 0x0f) | 0x80;
9977 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9978 DAG.getConstant(PermMask, DL, MVT::i8));
9981 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9982 /// shuffling each lane.
9984 /// This will only succeed when the result of fixing the 128-bit lanes results
9985 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9986 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9987 /// the lane crosses early and then use simpler shuffles within each lane.
9989 /// FIXME: It might be worthwhile at some point to support this without
9990 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9991 /// in x86 only floating point has interesting non-repeating shuffles, and even
9992 /// those are still *marginally* more expensive.
9993 static SDValue lowerVectorShuffleByMerging128BitLanes(
9994 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9995 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9996 assert(!isSingleInputShuffleMask(Mask) &&
9997 "This is only useful with multiple inputs.");
9999 int Size = Mask.size();
10000 int LaneSize = 128 / VT.getScalarSizeInBits();
10001 int NumLanes = Size / LaneSize;
10002 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10004 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10005 // check whether the in-128-bit lane shuffles share a repeating pattern.
10006 SmallVector<int, 4> Lanes;
10007 Lanes.resize(NumLanes, -1);
10008 SmallVector<int, 4> InLaneMask;
10009 InLaneMask.resize(LaneSize, -1);
10010 for (int i = 0; i < Size; ++i) {
10014 int j = i / LaneSize;
10016 if (Lanes[j] < 0) {
10017 // First entry we've seen for this lane.
10018 Lanes[j] = Mask[i] / LaneSize;
10019 } else if (Lanes[j] != Mask[i] / LaneSize) {
10020 // This doesn't match the lane selected previously!
10024 // Check that within each lane we have a consistent shuffle mask.
10025 int k = i % LaneSize;
10026 if (InLaneMask[k] < 0) {
10027 InLaneMask[k] = Mask[i] % LaneSize;
10028 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10029 // This doesn't fit a repeating in-lane mask.
10034 // First shuffle the lanes into place.
10035 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10036 VT.getSizeInBits() / 64);
10037 SmallVector<int, 8> LaneMask;
10038 LaneMask.resize(NumLanes * 2, -1);
10039 for (int i = 0; i < NumLanes; ++i)
10040 if (Lanes[i] >= 0) {
10041 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10042 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10045 V1 = DAG.getBitcast(LaneVT, V1);
10046 V2 = DAG.getBitcast(LaneVT, V2);
10047 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10049 // Cast it back to the type we actually want.
10050 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10052 // Now do a simple shuffle that isn't lane crossing.
10053 SmallVector<int, 8> NewMask;
10054 NewMask.resize(Size, -1);
10055 for (int i = 0; i < Size; ++i)
10057 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10058 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10059 "Must not introduce lane crosses at this point!");
10061 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10064 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10067 /// This returns true if the elements from a particular input are already in the
10068 /// slot required by the given mask and require no permutation.
10069 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10070 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10071 int Size = Mask.size();
10072 for (int i = 0; i < Size; ++i)
10073 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10079 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10080 ArrayRef<int> Mask, SDValue V1,
10081 SDValue V2, SelectionDAG &DAG) {
10083 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10084 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10085 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10086 int NumElts = VT.getVectorNumElements();
10087 bool ShufpdMask = true;
10088 bool CommutableMask = true;
10089 unsigned Immediate = 0;
10090 for (int i = 0; i < NumElts; ++i) {
10093 int Val = (i & 6) + NumElts * (i & 1);
10094 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10095 if (Mask[i] < Val || Mask[i] > Val + 1)
10096 ShufpdMask = false;
10097 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10098 CommutableMask = false;
10099 Immediate |= (Mask[i] % 2) << i;
10102 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10103 DAG.getConstant(Immediate, DL, MVT::i8));
10104 if (CommutableMask)
10105 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10106 DAG.getConstant(Immediate, DL, MVT::i8));
10110 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10112 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10113 /// isn't available.
10114 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10115 const X86Subtarget *Subtarget,
10116 SelectionDAG &DAG) {
10118 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10119 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10120 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10121 ArrayRef<int> Mask = SVOp->getMask();
10122 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10124 SmallVector<int, 4> WidenedMask;
10125 if (canWidenShuffleElements(Mask, WidenedMask))
10126 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10129 if (isSingleInputShuffleMask(Mask)) {
10130 // Check for being able to broadcast a single element.
10131 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10132 Mask, Subtarget, DAG))
10135 // Use low duplicate instructions for masks that match their pattern.
10136 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10137 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10139 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10140 // Non-half-crossing single input shuffles can be lowerid with an
10141 // interleaved permutation.
10142 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10143 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10144 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10145 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10148 // With AVX2 we have direct support for this permutation.
10149 if (Subtarget->hasAVX2())
10150 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10151 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10153 // Otherwise, fall back.
10154 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10158 // X86 has dedicated unpack instructions that can handle specific blend
10159 // operations: UNPCKH and UNPCKL.
10160 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10161 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10162 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10163 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10164 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10165 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10166 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10167 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10169 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10173 // Check if the blend happens to exactly fit that of SHUFPD.
10175 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10178 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10179 // shuffle. However, if we have AVX2 and either inputs are already in place,
10180 // we will be able to shuffle even across lanes the other input in a single
10181 // instruction so skip this pattern.
10182 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10183 isShuffleMaskInputInPlace(1, Mask))))
10184 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10185 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10188 // If we have AVX2 then we always want to lower with a blend because an v4 we
10189 // can fully permute the elements.
10190 if (Subtarget->hasAVX2())
10191 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10194 // Otherwise fall back on generic lowering.
10195 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10198 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10200 /// This routine is only called when we have AVX2 and thus a reasonable
10201 /// instruction set for v4i64 shuffling..
10202 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10203 const X86Subtarget *Subtarget,
10204 SelectionDAG &DAG) {
10206 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10207 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10209 ArrayRef<int> Mask = SVOp->getMask();
10210 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10211 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10213 SmallVector<int, 4> WidenedMask;
10214 if (canWidenShuffleElements(Mask, WidenedMask))
10215 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10218 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10222 // Check for being able to broadcast a single element.
10223 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10224 Mask, Subtarget, DAG))
10227 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10228 // use lower latency instructions that will operate on both 128-bit lanes.
10229 SmallVector<int, 2> RepeatedMask;
10230 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10231 if (isSingleInputShuffleMask(Mask)) {
10232 int PSHUFDMask[] = {-1, -1, -1, -1};
10233 for (int i = 0; i < 2; ++i)
10234 if (RepeatedMask[i] >= 0) {
10235 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10236 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10238 return DAG.getBitcast(
10240 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10241 DAG.getBitcast(MVT::v8i32, V1),
10242 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10246 // AVX2 provides a direct instruction for permuting a single input across
10248 if (isSingleInputShuffleMask(Mask))
10249 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10250 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10252 // Try to use shift instructions.
10253 if (SDValue Shift =
10254 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10257 // Use dedicated unpack instructions for masks that match their pattern.
10258 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10259 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10260 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10261 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10262 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10263 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10264 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10265 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10267 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10268 // shuffle. However, if we have AVX2 and either inputs are already in place,
10269 // we will be able to shuffle even across lanes the other input in a single
10270 // instruction so skip this pattern.
10271 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10272 isShuffleMaskInputInPlace(1, Mask))))
10273 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10274 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10277 // Otherwise fall back on generic blend lowering.
10278 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10282 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10284 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10285 /// isn't available.
10286 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10287 const X86Subtarget *Subtarget,
10288 SelectionDAG &DAG) {
10290 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10291 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10293 ArrayRef<int> Mask = SVOp->getMask();
10294 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10296 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10300 // Check for being able to broadcast a single element.
10301 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10302 Mask, Subtarget, DAG))
10305 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10306 // options to efficiently lower the shuffle.
10307 SmallVector<int, 4> RepeatedMask;
10308 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10309 assert(RepeatedMask.size() == 4 &&
10310 "Repeated masks must be half the mask width!");
10312 // Use even/odd duplicate instructions for masks that match their pattern.
10313 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10314 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10315 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10316 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10318 if (isSingleInputShuffleMask(Mask))
10319 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10320 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10322 // Use dedicated unpack instructions for masks that match their pattern.
10323 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10324 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10325 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10326 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10327 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10328 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10329 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10330 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10332 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10333 // have already handled any direct blends. We also need to squash the
10334 // repeated mask into a simulated v4f32 mask.
10335 for (int i = 0; i < 4; ++i)
10336 if (RepeatedMask[i] >= 8)
10337 RepeatedMask[i] -= 4;
10338 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10341 // If we have a single input shuffle with different shuffle patterns in the
10342 // two 128-bit lanes use the variable mask to VPERMILPS.
10343 if (isSingleInputShuffleMask(Mask)) {
10344 SDValue VPermMask[8];
10345 for (int i = 0; i < 8; ++i)
10346 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10347 : DAG.getConstant(Mask[i], DL, MVT::i32);
10348 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10349 return DAG.getNode(
10350 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10351 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10353 if (Subtarget->hasAVX2())
10354 return DAG.getNode(
10355 X86ISD::VPERMV, DL, MVT::v8f32,
10356 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10357 MVT::v8i32, VPermMask)),
10360 // Otherwise, fall back.
10361 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10365 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10367 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10368 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10371 // If we have AVX2 then we always want to lower with a blend because at v8 we
10372 // can fully permute the elements.
10373 if (Subtarget->hasAVX2())
10374 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10377 // Otherwise fall back on generic lowering.
10378 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10381 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10383 /// This routine is only called when we have AVX2 and thus a reasonable
10384 /// instruction set for v8i32 shuffling..
10385 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10386 const X86Subtarget *Subtarget,
10387 SelectionDAG &DAG) {
10389 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10390 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10392 ArrayRef<int> Mask = SVOp->getMask();
10393 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10394 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10396 // Whenever we can lower this as a zext, that instruction is strictly faster
10397 // than any alternative. It also allows us to fold memory operands into the
10398 // shuffle in many cases.
10399 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10400 Mask, Subtarget, DAG))
10403 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10407 // Check for being able to broadcast a single element.
10408 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10409 Mask, Subtarget, DAG))
10412 // If the shuffle mask is repeated in each 128-bit lane we can use more
10413 // efficient instructions that mirror the shuffles across the two 128-bit
10415 SmallVector<int, 4> RepeatedMask;
10416 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10417 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10418 if (isSingleInputShuffleMask(Mask))
10419 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10420 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10422 // Use dedicated unpack instructions for masks that match their pattern.
10423 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10424 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10425 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10426 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10427 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10428 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10429 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10430 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10433 // Try to use shift instructions.
10434 if (SDValue Shift =
10435 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10438 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10439 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10442 // If the shuffle patterns aren't repeated but it is a single input, directly
10443 // generate a cross-lane VPERMD instruction.
10444 if (isSingleInputShuffleMask(Mask)) {
10445 SDValue VPermMask[8];
10446 for (int i = 0; i < 8; ++i)
10447 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10448 : DAG.getConstant(Mask[i], DL, MVT::i32);
10449 return DAG.getNode(
10450 X86ISD::VPERMV, DL, MVT::v8i32,
10451 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10454 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10456 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10457 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10460 // Otherwise fall back on generic blend lowering.
10461 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10465 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10467 /// This routine is only called when we have AVX2 and thus a reasonable
10468 /// instruction set for v16i16 shuffling..
10469 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10470 const X86Subtarget *Subtarget,
10471 SelectionDAG &DAG) {
10473 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10474 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10476 ArrayRef<int> Mask = SVOp->getMask();
10477 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10478 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10480 // Whenever we can lower this as a zext, that instruction is strictly faster
10481 // than any alternative. It also allows us to fold memory operands into the
10482 // shuffle in many cases.
10483 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10484 Mask, Subtarget, DAG))
10487 // Check for being able to broadcast a single element.
10488 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10489 Mask, Subtarget, DAG))
10492 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10496 // Use dedicated unpack instructions for masks that match their pattern.
10497 if (isShuffleEquivalent(V1, V2, Mask,
10498 {// First 128-bit lane:
10499 0, 16, 1, 17, 2, 18, 3, 19,
10500 // Second 128-bit lane:
10501 8, 24, 9, 25, 10, 26, 11, 27}))
10502 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10503 if (isShuffleEquivalent(V1, V2, Mask,
10504 {// First 128-bit lane:
10505 4, 20, 5, 21, 6, 22, 7, 23,
10506 // Second 128-bit lane:
10507 12, 28, 13, 29, 14, 30, 15, 31}))
10508 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10510 // Try to use shift instructions.
10511 if (SDValue Shift =
10512 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10515 // Try to use byte rotation instructions.
10516 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10517 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10520 if (isSingleInputShuffleMask(Mask)) {
10521 // There are no generalized cross-lane shuffle operations available on i16
10523 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10524 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10527 SmallVector<int, 8> RepeatedMask;
10528 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10529 // As this is a single-input shuffle, the repeated mask should be
10530 // a strictly valid v8i16 mask that we can pass through to the v8i16
10531 // lowering to handle even the v16 case.
10532 return lowerV8I16GeneralSingleInputVectorShuffle(
10533 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10536 SDValue PSHUFBMask[32];
10537 for (int i = 0; i < 16; ++i) {
10538 if (Mask[i] == -1) {
10539 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10543 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10544 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10545 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10546 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10548 return DAG.getBitcast(MVT::v16i16,
10549 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10550 DAG.getBitcast(MVT::v32i8, V1),
10551 DAG.getNode(ISD::BUILD_VECTOR, DL,
10552 MVT::v32i8, PSHUFBMask)));
10555 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10557 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10558 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10561 // Otherwise fall back on generic lowering.
10562 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10565 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10567 /// This routine is only called when we have AVX2 and thus a reasonable
10568 /// instruction set for v32i8 shuffling..
10569 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10570 const X86Subtarget *Subtarget,
10571 SelectionDAG &DAG) {
10573 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10574 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10575 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10576 ArrayRef<int> Mask = SVOp->getMask();
10577 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10578 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10580 // Whenever we can lower this as a zext, that instruction is strictly faster
10581 // than any alternative. It also allows us to fold memory operands into the
10582 // shuffle in many cases.
10583 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10584 Mask, Subtarget, DAG))
10587 // Check for being able to broadcast a single element.
10588 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10589 Mask, Subtarget, DAG))
10592 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10596 // Use dedicated unpack instructions for masks that match their pattern.
10597 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10599 if (isShuffleEquivalent(
10601 {// First 128-bit lane:
10602 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10603 // Second 128-bit lane:
10604 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10605 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10606 if (isShuffleEquivalent(
10608 {// First 128-bit lane:
10609 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10610 // Second 128-bit lane:
10611 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10612 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10614 // Try to use shift instructions.
10615 if (SDValue Shift =
10616 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10619 // Try to use byte rotation instructions.
10620 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10621 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10624 if (isSingleInputShuffleMask(Mask)) {
10625 // There are no generalized cross-lane shuffle operations available on i8
10627 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10628 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10631 SDValue PSHUFBMask[32];
10632 for (int i = 0; i < 32; ++i)
10635 ? DAG.getUNDEF(MVT::i8)
10636 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10639 return DAG.getNode(
10640 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10641 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10644 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10646 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10647 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10650 // Otherwise fall back on generic lowering.
10651 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10654 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10656 /// This routine either breaks down the specific type of a 256-bit x86 vector
10657 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10658 /// together based on the available instructions.
10659 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10660 MVT VT, const X86Subtarget *Subtarget,
10661 SelectionDAG &DAG) {
10663 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10664 ArrayRef<int> Mask = SVOp->getMask();
10666 // If we have a single input to the zero element, insert that into V1 if we
10667 // can do so cheaply.
10668 int NumElts = VT.getVectorNumElements();
10669 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10670 return M >= NumElts;
10673 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10674 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10675 DL, VT, V1, V2, Mask, Subtarget, DAG))
10678 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10679 // can check for those subtargets here and avoid much of the subtarget
10680 // querying in the per-vector-type lowering routines. With AVX1 we have
10681 // essentially *zero* ability to manipulate a 256-bit vector with integer
10682 // types. Since we'll use floating point types there eventually, just
10683 // immediately cast everything to a float and operate entirely in that domain.
10684 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10685 int ElementBits = VT.getScalarSizeInBits();
10686 if (ElementBits < 32)
10687 // No floating point type available, decompose into 128-bit vectors.
10688 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10690 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10691 VT.getVectorNumElements());
10692 V1 = DAG.getBitcast(FpVT, V1);
10693 V2 = DAG.getBitcast(FpVT, V2);
10694 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10697 switch (VT.SimpleTy) {
10699 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10701 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10703 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10705 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10707 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10709 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10712 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10716 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10717 ArrayRef<int> Mask, SDValue V1,
10718 SDValue V2, SelectionDAG &DAG) {
10720 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10722 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10723 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10725 SmallVector<SDValue, 32> VPermMask;
10726 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10727 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10728 DAG.getConstant(Mask[i], DL, MaskEltVT));
10729 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10731 if (isSingleInputShuffleMask(Mask))
10732 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10734 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10737 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10738 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10739 const X86Subtarget *Subtarget,
10740 SelectionDAG &DAG) {
10742 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10743 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10745 ArrayRef<int> Mask = SVOp->getMask();
10746 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10748 if (SDValue Unpck =
10749 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10752 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10755 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10756 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10757 const X86Subtarget *Subtarget,
10758 SelectionDAG &DAG) {
10760 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10761 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10762 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10763 ArrayRef<int> Mask = SVOp->getMask();
10764 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10766 if (SDValue Unpck =
10767 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10770 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10773 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10774 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10775 const X86Subtarget *Subtarget,
10776 SelectionDAG &DAG) {
10778 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10779 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10780 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10781 ArrayRef<int> Mask = SVOp->getMask();
10782 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10784 if (SDValue Unpck =
10785 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10788 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10791 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10792 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10793 const X86Subtarget *Subtarget,
10794 SelectionDAG &DAG) {
10796 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10797 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10799 ArrayRef<int> Mask = SVOp->getMask();
10800 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10802 if (SDValue Unpck =
10803 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10806 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10809 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10810 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10811 const X86Subtarget *Subtarget,
10812 SelectionDAG &DAG) {
10814 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10815 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10816 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10817 ArrayRef<int> Mask = SVOp->getMask();
10818 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10819 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10821 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10824 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10825 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10826 const X86Subtarget *Subtarget,
10827 SelectionDAG &DAG) {
10829 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10830 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10832 ArrayRef<int> Mask = SVOp->getMask();
10833 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10834 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10836 // FIXME: Implement direct support for this type!
10837 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10840 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10842 /// This routine either breaks down the specific type of a 512-bit x86 vector
10843 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10844 /// together based on the available instructions.
10845 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10846 MVT VT, const X86Subtarget *Subtarget,
10847 SelectionDAG &DAG) {
10849 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10850 ArrayRef<int> Mask = SVOp->getMask();
10851 assert(Subtarget->hasAVX512() &&
10852 "Cannot lower 512-bit vectors w/ basic ISA!");
10854 // Check for being able to broadcast a single element.
10855 if (SDValue Broadcast =
10856 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10859 // Dispatch to each element type for lowering. If we don't have supprot for
10860 // specific element type shuffles at 512 bits, immediately split them and
10861 // lower them. Each lowering routine of a given type is allowed to assume that
10862 // the requisite ISA extensions for that element type are available.
10863 switch (VT.SimpleTy) {
10865 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10867 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10869 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10873 if (Subtarget->hasBWI())
10874 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10877 if (Subtarget->hasBWI())
10878 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10882 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10885 // Otherwise fall back on splitting.
10886 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10889 // Lower vXi1 vector shuffles.
10890 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10891 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10892 // vector, shuffle and then truncate it back.
10893 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10894 MVT VT, const X86Subtarget *Subtarget,
10895 SelectionDAG &DAG) {
10897 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10898 ArrayRef<int> Mask = SVOp->getMask();
10899 assert(Subtarget->hasAVX512() &&
10900 "Cannot lower 512-bit vectors w/o basic ISA!");
10902 switch (VT.SimpleTy) {
10904 assert(false && "Expected a vector of i1 elements");
10907 ExtVT = MVT::v2i64;
10910 ExtVT = MVT::v4i32;
10913 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10916 ExtVT = MVT::v16i32;
10919 ExtVT = MVT::v32i16;
10922 ExtVT = MVT::v64i8;
10926 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10927 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10928 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10929 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10931 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10934 V2 = DAG.getUNDEF(ExtVT);
10935 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10936 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10937 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10938 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10940 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10941 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10942 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10944 /// \brief Top-level lowering for x86 vector shuffles.
10946 /// This handles decomposition, canonicalization, and lowering of all x86
10947 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10948 /// above in helper routines. The canonicalization attempts to widen shuffles
10949 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10950 /// s.t. only one of the two inputs needs to be tested, etc.
10951 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10952 SelectionDAG &DAG) {
10953 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10954 ArrayRef<int> Mask = SVOp->getMask();
10955 SDValue V1 = Op.getOperand(0);
10956 SDValue V2 = Op.getOperand(1);
10957 MVT VT = Op.getSimpleValueType();
10958 int NumElements = VT.getVectorNumElements();
10960 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
10962 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
10963 "Can't lower MMX shuffles");
10965 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10966 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10967 if (V1IsUndef && V2IsUndef)
10968 return DAG.getUNDEF(VT);
10970 // When we create a shuffle node we put the UNDEF node to second operand,
10971 // but in some cases the first operand may be transformed to UNDEF.
10972 // In this case we should just commute the node.
10974 return DAG.getCommutedVectorShuffle(*SVOp);
10976 // Check for non-undef masks pointing at an undef vector and make the masks
10977 // undef as well. This makes it easier to match the shuffle based solely on
10981 if (M >= NumElements) {
10982 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10983 for (int &M : NewMask)
10984 if (M >= NumElements)
10986 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10989 // We actually see shuffles that are entirely re-arrangements of a set of
10990 // zero inputs. This mostly happens while decomposing complex shuffles into
10991 // simple ones. Directly lower these as a buildvector of zeros.
10992 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10993 if (Zeroable.all())
10994 return getZeroVector(VT, Subtarget, DAG, dl);
10996 // Try to collapse shuffles into using a vector type with fewer elements but
10997 // wider element types. We cap this to not form integers or floating point
10998 // elements wider than 64 bits, but it might be interesting to form i128
10999 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11000 SmallVector<int, 16> WidenedMask;
11001 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11002 canWidenShuffleElements(Mask, WidenedMask)) {
11003 MVT NewEltVT = VT.isFloatingPoint()
11004 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11005 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11006 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11007 // Make sure that the new vector type is legal. For example, v2f64 isn't
11009 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11010 V1 = DAG.getBitcast(NewVT, V1);
11011 V2 = DAG.getBitcast(NewVT, V2);
11012 return DAG.getBitcast(
11013 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11017 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11018 for (int M : SVOp->getMask())
11020 ++NumUndefElements;
11021 else if (M < NumElements)
11026 // Commute the shuffle as needed such that more elements come from V1 than
11027 // V2. This allows us to match the shuffle pattern strictly on how many
11028 // elements come from V1 without handling the symmetric cases.
11029 if (NumV2Elements > NumV1Elements)
11030 return DAG.getCommutedVectorShuffle(*SVOp);
11032 // When the number of V1 and V2 elements are the same, try to minimize the
11033 // number of uses of V2 in the low half of the vector. When that is tied,
11034 // ensure that the sum of indices for V1 is equal to or lower than the sum
11035 // indices for V2. When those are equal, try to ensure that the number of odd
11036 // indices for V1 is lower than the number of odd indices for V2.
11037 if (NumV1Elements == NumV2Elements) {
11038 int LowV1Elements = 0, LowV2Elements = 0;
11039 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11040 if (M >= NumElements)
11044 if (LowV2Elements > LowV1Elements) {
11045 return DAG.getCommutedVectorShuffle(*SVOp);
11046 } else if (LowV2Elements == LowV1Elements) {
11047 int SumV1Indices = 0, SumV2Indices = 0;
11048 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11049 if (SVOp->getMask()[i] >= NumElements)
11051 else if (SVOp->getMask()[i] >= 0)
11053 if (SumV2Indices < SumV1Indices) {
11054 return DAG.getCommutedVectorShuffle(*SVOp);
11055 } else if (SumV2Indices == SumV1Indices) {
11056 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11057 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11058 if (SVOp->getMask()[i] >= NumElements)
11059 NumV2OddIndices += i % 2;
11060 else if (SVOp->getMask()[i] >= 0)
11061 NumV1OddIndices += i % 2;
11062 if (NumV2OddIndices < NumV1OddIndices)
11063 return DAG.getCommutedVectorShuffle(*SVOp);
11068 // For each vector width, delegate to a specialized lowering routine.
11069 if (VT.getSizeInBits() == 128)
11070 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11072 if (VT.getSizeInBits() == 256)
11073 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11075 if (VT.getSizeInBits() == 512)
11076 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11079 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11080 llvm_unreachable("Unimplemented!");
11083 // This function assumes its argument is a BUILD_VECTOR of constants or
11084 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11086 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11087 unsigned &MaskValue) {
11089 unsigned NumElems = BuildVector->getNumOperands();
11090 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11091 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11092 unsigned NumElemsInLane = NumElems / NumLanes;
11094 // Blend for v16i16 should be symmetric for the both lanes.
11095 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11096 SDValue EltCond = BuildVector->getOperand(i);
11097 SDValue SndLaneEltCond =
11098 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11100 int Lane1Cond = -1, Lane2Cond = -1;
11101 if (isa<ConstantSDNode>(EltCond))
11102 Lane1Cond = !isZero(EltCond);
11103 if (isa<ConstantSDNode>(SndLaneEltCond))
11104 Lane2Cond = !isZero(SndLaneEltCond);
11106 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11107 // Lane1Cond != 0, means we want the first argument.
11108 // Lane1Cond == 0, means we want the second argument.
11109 // The encoding of this argument is 0 for the first argument, 1
11110 // for the second. Therefore, invert the condition.
11111 MaskValue |= !Lane1Cond << i;
11112 else if (Lane1Cond < 0)
11113 MaskValue |= !Lane2Cond << i;
11120 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11121 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11122 const X86Subtarget *Subtarget,
11123 SelectionDAG &DAG) {
11124 SDValue Cond = Op.getOperand(0);
11125 SDValue LHS = Op.getOperand(1);
11126 SDValue RHS = Op.getOperand(2);
11128 MVT VT = Op.getSimpleValueType();
11130 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11132 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11134 // Only non-legal VSELECTs reach this lowering, convert those into generic
11135 // shuffles and re-use the shuffle lowering path for blends.
11136 SmallVector<int, 32> Mask;
11137 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11138 SDValue CondElt = CondBV->getOperand(i);
11140 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11142 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11145 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11146 // A vselect where all conditions and data are constants can be optimized into
11147 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11148 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11149 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11150 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11153 // Try to lower this to a blend-style vector shuffle. This can handle all
11154 // constant condition cases.
11155 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11158 // Variable blends are only legal from SSE4.1 onward.
11159 if (!Subtarget->hasSSE41())
11162 // Only some types will be legal on some subtargets. If we can emit a legal
11163 // VSELECT-matching blend, return Op, and but if we need to expand, return
11165 switch (Op.getSimpleValueType().SimpleTy) {
11167 // Most of the vector types have blends past SSE4.1.
11171 // The byte blends for AVX vectors were introduced only in AVX2.
11172 if (Subtarget->hasAVX2())
11179 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11180 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11183 // FIXME: We should custom lower this by fixing the condition and using i8
11189 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11190 MVT VT = Op.getSimpleValueType();
11193 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11196 if (VT.getSizeInBits() == 8) {
11197 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11198 Op.getOperand(0), Op.getOperand(1));
11199 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11200 DAG.getValueType(VT));
11201 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11204 if (VT.getSizeInBits() == 16) {
11205 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11206 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11208 return DAG.getNode(
11209 ISD::TRUNCATE, dl, MVT::i16,
11210 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11211 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11212 Op.getOperand(1)));
11213 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11214 Op.getOperand(0), Op.getOperand(1));
11215 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11216 DAG.getValueType(VT));
11217 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11220 if (VT == MVT::f32) {
11221 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11222 // the result back to FR32 register. It's only worth matching if the
11223 // result has a single use which is a store or a bitcast to i32. And in
11224 // the case of a store, it's not worth it if the index is a constant 0,
11225 // because a MOVSSmr can be used instead, which is smaller and faster.
11226 if (!Op.hasOneUse())
11228 SDNode *User = *Op.getNode()->use_begin();
11229 if ((User->getOpcode() != ISD::STORE ||
11230 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11231 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11232 (User->getOpcode() != ISD::BITCAST ||
11233 User->getValueType(0) != MVT::i32))
11235 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11236 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11238 return DAG.getBitcast(MVT::f32, Extract);
11241 if (VT == MVT::i32 || VT == MVT::i64) {
11242 // ExtractPS/pextrq works with constant index.
11243 if (isa<ConstantSDNode>(Op.getOperand(1)))
11249 /// Extract one bit from mask vector, like v16i1 or v8i1.
11250 /// AVX-512 feature.
11252 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11253 SDValue Vec = Op.getOperand(0);
11255 MVT VecVT = Vec.getSimpleValueType();
11256 SDValue Idx = Op.getOperand(1);
11257 MVT EltVT = Op.getSimpleValueType();
11259 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11260 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11261 "Unexpected vector type in ExtractBitFromMaskVector");
11263 // variable index can't be handled in mask registers,
11264 // extend vector to VR512
11265 if (!isa<ConstantSDNode>(Idx)) {
11266 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11267 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11268 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11269 ExtVT.getVectorElementType(), Ext, Idx);
11270 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11273 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11274 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11275 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11276 rc = getRegClassFor(MVT::v16i1);
11277 unsigned MaxSift = rc->getSize()*8 - 1;
11278 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11279 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11280 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11281 DAG.getConstant(MaxSift, dl, MVT::i8));
11282 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11283 DAG.getIntPtrConstant(0, dl));
11287 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11288 SelectionDAG &DAG) const {
11290 SDValue Vec = Op.getOperand(0);
11291 MVT VecVT = Vec.getSimpleValueType();
11292 SDValue Idx = Op.getOperand(1);
11294 if (Op.getSimpleValueType() == MVT::i1)
11295 return ExtractBitFromMaskVector(Op, DAG);
11297 if (!isa<ConstantSDNode>(Idx)) {
11298 if (VecVT.is512BitVector() ||
11299 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11300 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11303 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11304 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11305 MaskEltVT.getSizeInBits());
11307 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11308 auto PtrVT = getPointerTy(DAG.getDataLayout());
11309 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11310 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11311 DAG.getConstant(0, dl, PtrVT));
11312 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11314 DAG.getConstant(0, dl, PtrVT));
11319 // If this is a 256-bit vector result, first extract the 128-bit vector and
11320 // then extract the element from the 128-bit vector.
11321 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11323 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11324 // Get the 128-bit vector.
11325 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11326 MVT EltVT = VecVT.getVectorElementType();
11328 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11330 //if (IdxVal >= NumElems/2)
11331 // IdxVal -= NumElems/2;
11332 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11333 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11334 DAG.getConstant(IdxVal, dl, MVT::i32));
11337 assert(VecVT.is128BitVector() && "Unexpected vector length");
11339 if (Subtarget->hasSSE41())
11340 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11343 MVT VT = Op.getSimpleValueType();
11344 // TODO: handle v16i8.
11345 if (VT.getSizeInBits() == 16) {
11346 SDValue Vec = Op.getOperand(0);
11347 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11349 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11350 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11351 DAG.getBitcast(MVT::v4i32, Vec),
11352 Op.getOperand(1)));
11353 // Transform it so it match pextrw which produces a 32-bit result.
11354 MVT EltVT = MVT::i32;
11355 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11356 Op.getOperand(0), Op.getOperand(1));
11357 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11358 DAG.getValueType(VT));
11359 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11362 if (VT.getSizeInBits() == 32) {
11363 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11367 // SHUFPS the element to the lowest double word, then movss.
11368 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11369 MVT VVT = Op.getOperand(0).getSimpleValueType();
11370 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11371 DAG.getUNDEF(VVT), Mask);
11372 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11373 DAG.getIntPtrConstant(0, dl));
11376 if (VT.getSizeInBits() == 64) {
11377 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11378 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11379 // to match extract_elt for f64.
11380 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11384 // UNPCKHPD the element to the lowest double word, then movsd.
11385 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11386 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11387 int Mask[2] = { 1, -1 };
11388 MVT VVT = Op.getOperand(0).getSimpleValueType();
11389 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11390 DAG.getUNDEF(VVT), Mask);
11391 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11392 DAG.getIntPtrConstant(0, dl));
11398 /// Insert one bit to mask vector, like v16i1 or v8i1.
11399 /// AVX-512 feature.
11401 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11403 SDValue Vec = Op.getOperand(0);
11404 SDValue Elt = Op.getOperand(1);
11405 SDValue Idx = Op.getOperand(2);
11406 MVT VecVT = Vec.getSimpleValueType();
11408 if (!isa<ConstantSDNode>(Idx)) {
11409 // Non constant index. Extend source and destination,
11410 // insert element and then truncate the result.
11411 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11412 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11413 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11414 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11415 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11416 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11419 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11420 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11422 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11423 DAG.getConstant(IdxVal, dl, MVT::i8));
11424 if (Vec.getOpcode() == ISD::UNDEF)
11426 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11429 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11430 SelectionDAG &DAG) const {
11431 MVT VT = Op.getSimpleValueType();
11432 MVT EltVT = VT.getVectorElementType();
11434 if (EltVT == MVT::i1)
11435 return InsertBitToMaskVector(Op, DAG);
11438 SDValue N0 = Op.getOperand(0);
11439 SDValue N1 = Op.getOperand(1);
11440 SDValue N2 = Op.getOperand(2);
11441 if (!isa<ConstantSDNode>(N2))
11443 auto *N2C = cast<ConstantSDNode>(N2);
11444 unsigned IdxVal = N2C->getZExtValue();
11446 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11447 // into that, and then insert the subvector back into the result.
11448 if (VT.is256BitVector() || VT.is512BitVector()) {
11449 // With a 256-bit vector, we can insert into the zero element efficiently
11450 // using a blend if we have AVX or AVX2 and the right data type.
11451 if (VT.is256BitVector() && IdxVal == 0) {
11452 // TODO: It is worthwhile to cast integer to floating point and back
11453 // and incur a domain crossing penalty if that's what we'll end up
11454 // doing anyway after extracting to a 128-bit vector.
11455 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11456 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11457 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11458 N2 = DAG.getIntPtrConstant(1, dl);
11459 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11463 // Get the desired 128-bit vector chunk.
11464 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11466 // Insert the element into the desired chunk.
11467 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11468 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11470 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11471 DAG.getConstant(IdxIn128, dl, MVT::i32));
11473 // Insert the changed part back into the bigger vector
11474 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11476 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11478 if (Subtarget->hasSSE41()) {
11479 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11481 if (VT == MVT::v8i16) {
11482 Opc = X86ISD::PINSRW;
11484 assert(VT == MVT::v16i8);
11485 Opc = X86ISD::PINSRB;
11488 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11490 if (N1.getValueType() != MVT::i32)
11491 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11492 if (N2.getValueType() != MVT::i32)
11493 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11494 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11497 if (EltVT == MVT::f32) {
11498 // Bits [7:6] of the constant are the source select. This will always be
11499 // zero here. The DAG Combiner may combine an extract_elt index into
11500 // these bits. For example (insert (extract, 3), 2) could be matched by
11501 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11502 // Bits [5:4] of the constant are the destination select. This is the
11503 // value of the incoming immediate.
11504 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11505 // combine either bitwise AND or insert of float 0.0 to set these bits.
11507 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11508 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11509 // If this is an insertion of 32-bits into the low 32-bits of
11510 // a vector, we prefer to generate a blend with immediate rather
11511 // than an insertps. Blends are simpler operations in hardware and so
11512 // will always have equal or better performance than insertps.
11513 // But if optimizing for size and there's a load folding opportunity,
11514 // generate insertps because blendps does not have a 32-bit memory
11516 N2 = DAG.getIntPtrConstant(1, dl);
11517 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11518 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11520 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11521 // Create this as a scalar to vector..
11522 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11523 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11526 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11527 // PINSR* works with constant index.
11532 if (EltVT == MVT::i8)
11535 if (EltVT.getSizeInBits() == 16) {
11536 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11537 // as its second argument.
11538 if (N1.getValueType() != MVT::i32)
11539 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11540 if (N2.getValueType() != MVT::i32)
11541 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11542 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11547 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11549 MVT OpVT = Op.getSimpleValueType();
11551 // If this is a 256-bit vector result, first insert into a 128-bit
11552 // vector and then insert into the 256-bit vector.
11553 if (!OpVT.is128BitVector()) {
11554 // Insert into a 128-bit vector.
11555 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11556 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11557 OpVT.getVectorNumElements() / SizeFactor);
11559 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11561 // Insert the 128-bit vector.
11562 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11565 if (OpVT == MVT::v1i64 &&
11566 Op.getOperand(0).getValueType() == MVT::i64)
11567 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11569 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11570 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11571 return DAG.getBitcast(
11572 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11575 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11576 // a simple subregister reference or explicit instructions to grab
11577 // upper bits of a vector.
11578 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11579 SelectionDAG &DAG) {
11581 SDValue In = Op.getOperand(0);
11582 SDValue Idx = Op.getOperand(1);
11583 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11584 MVT ResVT = Op.getSimpleValueType();
11585 MVT InVT = In.getSimpleValueType();
11587 if (Subtarget->hasFp256()) {
11588 if (ResVT.is128BitVector() &&
11589 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11590 isa<ConstantSDNode>(Idx)) {
11591 return Extract128BitVector(In, IdxVal, DAG, dl);
11593 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11594 isa<ConstantSDNode>(Idx)) {
11595 return Extract256BitVector(In, IdxVal, DAG, dl);
11601 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11602 // simple superregister reference or explicit instructions to insert
11603 // the upper bits of a vector.
11604 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11605 SelectionDAG &DAG) {
11606 if (!Subtarget->hasAVX())
11610 SDValue Vec = Op.getOperand(0);
11611 SDValue SubVec = Op.getOperand(1);
11612 SDValue Idx = Op.getOperand(2);
11614 if (!isa<ConstantSDNode>(Idx))
11617 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11618 MVT OpVT = Op.getSimpleValueType();
11619 MVT SubVecVT = SubVec.getSimpleValueType();
11621 // Fold two 16-byte subvector loads into one 32-byte load:
11622 // (insert_subvector (insert_subvector undef, (load addr), 0),
11623 // (load addr + 16), Elts/2)
11625 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11626 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11627 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11628 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11629 if (Idx2 && Idx2->getZExtValue() == 0) {
11630 SDValue SubVec2 = Vec.getOperand(1);
11631 // If needed, look through a bitcast to get to the load.
11632 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11633 SubVec2 = SubVec2.getOperand(0);
11635 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11637 unsigned Alignment = FirstLd->getAlignment();
11638 unsigned AS = FirstLd->getAddressSpace();
11639 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11640 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11641 OpVT, AS, Alignment, &Fast) && Fast) {
11642 SDValue Ops[] = { SubVec2, SubVec };
11643 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11650 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11651 SubVecVT.is128BitVector())
11652 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11654 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11655 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11657 if (OpVT.getVectorElementType() == MVT::i1) {
11658 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11660 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11661 SDValue Undef = DAG.getUNDEF(OpVT);
11662 unsigned NumElems = OpVT.getVectorNumElements();
11663 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11665 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11666 // Zero upper bits of the Vec
11667 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11668 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11670 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11672 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11673 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11676 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11678 // Zero upper bits of the Vec2
11679 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11680 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11681 // Zero lower bits of the Vec
11682 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11683 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11684 // Merge them together
11685 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11691 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11692 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11693 // one of the above mentioned nodes. It has to be wrapped because otherwise
11694 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11695 // be used to form addressing mode. These wrapped nodes will be selected
11698 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11699 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11701 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11702 // global base reg.
11703 unsigned char OpFlag = 0;
11704 unsigned WrapperKind = X86ISD::Wrapper;
11705 CodeModel::Model M = DAG.getTarget().getCodeModel();
11707 if (Subtarget->isPICStyleRIPRel() &&
11708 (M == CodeModel::Small || M == CodeModel::Kernel))
11709 WrapperKind = X86ISD::WrapperRIP;
11710 else if (Subtarget->isPICStyleGOT())
11711 OpFlag = X86II::MO_GOTOFF;
11712 else if (Subtarget->isPICStyleStubPIC())
11713 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11715 auto PtrVT = getPointerTy(DAG.getDataLayout());
11716 SDValue Result = DAG.getTargetConstantPool(
11717 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11719 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11720 // With PIC, the address is actually $g + Offset.
11723 DAG.getNode(ISD::ADD, DL, PtrVT,
11724 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11730 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11731 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11733 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11734 // global base reg.
11735 unsigned char OpFlag = 0;
11736 unsigned WrapperKind = X86ISD::Wrapper;
11737 CodeModel::Model M = DAG.getTarget().getCodeModel();
11739 if (Subtarget->isPICStyleRIPRel() &&
11740 (M == CodeModel::Small || M == CodeModel::Kernel))
11741 WrapperKind = X86ISD::WrapperRIP;
11742 else if (Subtarget->isPICStyleGOT())
11743 OpFlag = X86II::MO_GOTOFF;
11744 else if (Subtarget->isPICStyleStubPIC())
11745 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11747 auto PtrVT = getPointerTy(DAG.getDataLayout());
11748 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11750 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11752 // With PIC, the address is actually $g + Offset.
11755 DAG.getNode(ISD::ADD, DL, PtrVT,
11756 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11762 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11763 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11765 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11766 // global base reg.
11767 unsigned char OpFlag = 0;
11768 unsigned WrapperKind = X86ISD::Wrapper;
11769 CodeModel::Model M = DAG.getTarget().getCodeModel();
11771 if (Subtarget->isPICStyleRIPRel() &&
11772 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11773 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11774 OpFlag = X86II::MO_GOTPCREL;
11775 WrapperKind = X86ISD::WrapperRIP;
11776 } else if (Subtarget->isPICStyleGOT()) {
11777 OpFlag = X86II::MO_GOT;
11778 } else if (Subtarget->isPICStyleStubPIC()) {
11779 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11780 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11781 OpFlag = X86II::MO_DARWIN_NONLAZY;
11784 auto PtrVT = getPointerTy(DAG.getDataLayout());
11785 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11788 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11790 // With PIC, the address is actually $g + Offset.
11791 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11792 !Subtarget->is64Bit()) {
11794 DAG.getNode(ISD::ADD, DL, PtrVT,
11795 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11798 // For symbols that require a load from a stub to get the address, emit the
11800 if (isGlobalStubReference(OpFlag))
11801 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11802 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11803 false, false, false, 0);
11809 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11810 // Create the TargetBlockAddressAddress node.
11811 unsigned char OpFlags =
11812 Subtarget->ClassifyBlockAddressReference();
11813 CodeModel::Model M = DAG.getTarget().getCodeModel();
11814 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11815 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11817 auto PtrVT = getPointerTy(DAG.getDataLayout());
11818 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11820 if (Subtarget->isPICStyleRIPRel() &&
11821 (M == CodeModel::Small || M == CodeModel::Kernel))
11822 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11824 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11826 // With PIC, the address is actually $g + Offset.
11827 if (isGlobalRelativeToPICBase(OpFlags)) {
11828 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11829 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11836 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11837 int64_t Offset, SelectionDAG &DAG) const {
11838 // Create the TargetGlobalAddress node, folding in the constant
11839 // offset if it is legal.
11840 unsigned char OpFlags =
11841 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11842 CodeModel::Model M = DAG.getTarget().getCodeModel();
11843 auto PtrVT = getPointerTy(DAG.getDataLayout());
11845 if (OpFlags == X86II::MO_NO_FLAG &&
11846 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11847 // A direct static reference to a global.
11848 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11851 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11854 if (Subtarget->isPICStyleRIPRel() &&
11855 (M == CodeModel::Small || M == CodeModel::Kernel))
11856 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11858 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11860 // With PIC, the address is actually $g + Offset.
11861 if (isGlobalRelativeToPICBase(OpFlags)) {
11862 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11863 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11866 // For globals that require a load from a stub to get the address, emit the
11868 if (isGlobalStubReference(OpFlags))
11869 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11870 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11871 false, false, false, 0);
11873 // If there was a non-zero offset that we didn't fold, create an explicit
11874 // addition for it.
11876 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11877 DAG.getConstant(Offset, dl, PtrVT));
11883 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11884 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11885 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11886 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11890 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11891 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11892 unsigned char OperandFlags, bool LocalDynamic = false) {
11893 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11894 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11896 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11897 GA->getValueType(0),
11901 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11905 SDValue Ops[] = { Chain, TGA, *InFlag };
11906 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11908 SDValue Ops[] = { Chain, TGA };
11909 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11912 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11913 MFI->setAdjustsStack(true);
11914 MFI->setHasCalls(true);
11916 SDValue Flag = Chain.getValue(1);
11917 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11920 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11922 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11925 SDLoc dl(GA); // ? function entry point might be better
11926 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11927 DAG.getNode(X86ISD::GlobalBaseReg,
11928 SDLoc(), PtrVT), InFlag);
11929 InFlag = Chain.getValue(1);
11931 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11934 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11936 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11938 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11939 X86::RAX, X86II::MO_TLSGD);
11942 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11948 // Get the start address of the TLS block for this module.
11949 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11950 .getInfo<X86MachineFunctionInfo>();
11951 MFI->incNumLocalDynamicTLSAccesses();
11955 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11956 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11959 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11960 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11961 InFlag = Chain.getValue(1);
11962 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11963 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11966 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11970 unsigned char OperandFlags = X86II::MO_DTPOFF;
11971 unsigned WrapperKind = X86ISD::Wrapper;
11972 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11973 GA->getValueType(0),
11974 GA->getOffset(), OperandFlags);
11975 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11977 // Add x@dtpoff with the base.
11978 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11981 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11982 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11983 const EVT PtrVT, TLSModel::Model model,
11984 bool is64Bit, bool isPIC) {
11987 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11988 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11989 is64Bit ? 257 : 256));
11991 SDValue ThreadPointer =
11992 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11993 MachinePointerInfo(Ptr), false, false, false, 0);
11995 unsigned char OperandFlags = 0;
11996 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11998 unsigned WrapperKind = X86ISD::Wrapper;
11999 if (model == TLSModel::LocalExec) {
12000 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12001 } else if (model == TLSModel::InitialExec) {
12003 OperandFlags = X86II::MO_GOTTPOFF;
12004 WrapperKind = X86ISD::WrapperRIP;
12006 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12009 llvm_unreachable("Unexpected model");
12012 // emit "addl x@ntpoff,%eax" (local exec)
12013 // or "addl x@indntpoff,%eax" (initial exec)
12014 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12016 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12017 GA->getOffset(), OperandFlags);
12018 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12020 if (model == TLSModel::InitialExec) {
12021 if (isPIC && !is64Bit) {
12022 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12023 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12027 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12028 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12029 false, false, false, 0);
12032 // The address of the thread local variable is the add of the thread
12033 // pointer with the offset of the variable.
12034 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12038 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12040 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12041 const GlobalValue *GV = GA->getGlobal();
12042 auto PtrVT = getPointerTy(DAG.getDataLayout());
12044 if (Subtarget->isTargetELF()) {
12045 if (DAG.getTarget().Options.EmulatedTLS)
12046 return LowerToTLSEmulatedModel(GA, DAG);
12047 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12049 case TLSModel::GeneralDynamic:
12050 if (Subtarget->is64Bit())
12051 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12052 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12053 case TLSModel::LocalDynamic:
12054 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12055 Subtarget->is64Bit());
12056 case TLSModel::InitialExec:
12057 case TLSModel::LocalExec:
12058 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12059 DAG.getTarget().getRelocationModel() ==
12062 llvm_unreachable("Unknown TLS model.");
12065 if (Subtarget->isTargetDarwin()) {
12066 // Darwin only has one model of TLS. Lower to that.
12067 unsigned char OpFlag = 0;
12068 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12069 X86ISD::WrapperRIP : X86ISD::Wrapper;
12071 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12072 // global base reg.
12073 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12074 !Subtarget->is64Bit();
12076 OpFlag = X86II::MO_TLVP_PIC_BASE;
12078 OpFlag = X86II::MO_TLVP;
12080 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12081 GA->getValueType(0),
12082 GA->getOffset(), OpFlag);
12083 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12085 // With PIC32, the address is actually $g + Offset.
12087 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12088 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12091 // Lowering the machine isd will make sure everything is in the right
12093 SDValue Chain = DAG.getEntryNode();
12094 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12095 SDValue Args[] = { Chain, Offset };
12096 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12098 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12099 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12100 MFI->setAdjustsStack(true);
12102 // And our return value (tls address) is in the standard call return value
12104 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12105 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12108 if (Subtarget->isTargetKnownWindowsMSVC() ||
12109 Subtarget->isTargetWindowsGNU()) {
12110 // Just use the implicit TLS architecture
12111 // Need to generate someting similar to:
12112 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12114 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12115 // mov rcx, qword [rdx+rcx*8]
12116 // mov eax, .tls$:tlsvar
12117 // [rax+rcx] contains the address
12118 // Windows 64bit: gs:0x58
12119 // Windows 32bit: fs:__tls_array
12122 SDValue Chain = DAG.getEntryNode();
12124 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12125 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12126 // use its literal value of 0x2C.
12127 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12128 ? Type::getInt8PtrTy(*DAG.getContext(),
12130 : Type::getInt32PtrTy(*DAG.getContext(),
12133 SDValue TlsArray = Subtarget->is64Bit()
12134 ? DAG.getIntPtrConstant(0x58, dl)
12135 : (Subtarget->isTargetWindowsGNU()
12136 ? DAG.getIntPtrConstant(0x2C, dl)
12137 : DAG.getExternalSymbol("_tls_array", PtrVT));
12139 SDValue ThreadPointer =
12140 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12144 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12145 res = ThreadPointer;
12147 // Load the _tls_index variable
12148 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12149 if (Subtarget->is64Bit())
12150 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12151 MachinePointerInfo(), MVT::i32, false, false,
12154 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12157 auto &DL = DAG.getDataLayout();
12159 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12160 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12162 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12165 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12168 // Get the offset of start of .tls section
12169 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12170 GA->getValueType(0),
12171 GA->getOffset(), X86II::MO_SECREL);
12172 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12174 // The address of the thread local variable is the add of the thread
12175 // pointer with the offset of the variable.
12176 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12179 llvm_unreachable("TLS not implemented for this target.");
12182 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12183 /// and take a 2 x i32 value to shift plus a shift amount.
12184 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12185 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12186 MVT VT = Op.getSimpleValueType();
12187 unsigned VTBits = VT.getSizeInBits();
12189 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12190 SDValue ShOpLo = Op.getOperand(0);
12191 SDValue ShOpHi = Op.getOperand(1);
12192 SDValue ShAmt = Op.getOperand(2);
12193 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12194 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12196 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12197 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12198 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12199 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12200 : DAG.getConstant(0, dl, VT);
12202 SDValue Tmp2, Tmp3;
12203 if (Op.getOpcode() == ISD::SHL_PARTS) {
12204 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12205 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12207 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12208 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12211 // If the shift amount is larger or equal than the width of a part we can't
12212 // rely on the results of shld/shrd. Insert a test and select the appropriate
12213 // values for large shift amounts.
12214 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12215 DAG.getConstant(VTBits, dl, MVT::i8));
12216 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12217 AndNode, DAG.getConstant(0, dl, MVT::i8));
12220 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12221 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12222 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12224 if (Op.getOpcode() == ISD::SHL_PARTS) {
12225 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12226 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12228 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12229 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12232 SDValue Ops[2] = { Lo, Hi };
12233 return DAG.getMergeValues(Ops, dl);
12236 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12237 SelectionDAG &DAG) const {
12238 SDValue Src = Op.getOperand(0);
12239 MVT SrcVT = Src.getSimpleValueType();
12240 MVT VT = Op.getSimpleValueType();
12243 if (SrcVT.isVector()) {
12244 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12245 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12246 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12247 DAG.getUNDEF(SrcVT)));
12249 if (SrcVT.getVectorElementType() == MVT::i1) {
12250 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12251 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12252 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12257 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12258 "Unknown SINT_TO_FP to lower!");
12260 // These are really Legal; return the operand so the caller accepts it as
12262 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12264 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12265 Subtarget->is64Bit()) {
12269 unsigned Size = SrcVT.getSizeInBits()/8;
12270 MachineFunction &MF = DAG.getMachineFunction();
12271 auto PtrVT = getPointerTy(MF.getDataLayout());
12272 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12273 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12274 SDValue Chain = DAG.getStore(
12275 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12276 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12278 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12281 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12283 SelectionDAG &DAG) const {
12287 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12289 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12291 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12293 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12295 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12296 MachineMemOperand *MMO;
12298 int SSFI = FI->getIndex();
12299 MMO = DAG.getMachineFunction().getMachineMemOperand(
12300 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12301 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12303 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12304 StackSlot = StackSlot.getOperand(1);
12306 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12307 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12309 Tys, Ops, SrcVT, MMO);
12312 Chain = Result.getValue(1);
12313 SDValue InFlag = Result.getValue(2);
12315 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12316 // shouldn't be necessary except that RFP cannot be live across
12317 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12318 MachineFunction &MF = DAG.getMachineFunction();
12319 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12320 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12321 auto PtrVT = getPointerTy(MF.getDataLayout());
12322 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12323 Tys = DAG.getVTList(MVT::Other);
12325 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12327 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12328 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12329 MachineMemOperand::MOStore, SSFISize, SSFISize);
12331 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12332 Ops, Op.getValueType(), MMO);
12333 Result = DAG.getLoad(
12334 Op.getValueType(), DL, Chain, StackSlot,
12335 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12336 false, false, false, 0);
12342 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12343 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12344 SelectionDAG &DAG) const {
12345 // This algorithm is not obvious. Here it is what we're trying to output:
12348 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12349 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12351 haddpd %xmm0, %xmm0
12353 pshufd $0x4e, %xmm0, %xmm1
12359 LLVMContext *Context = DAG.getContext();
12361 // Build some magic constants.
12362 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12363 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12364 auto PtrVT = getPointerTy(DAG.getDataLayout());
12365 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12367 SmallVector<Constant*,2> CV1;
12369 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12370 APInt(64, 0x4330000000000000ULL))));
12372 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12373 APInt(64, 0x4530000000000000ULL))));
12374 Constant *C1 = ConstantVector::get(CV1);
12375 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12377 // Load the 64-bit value into an XMM register.
12378 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12381 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12382 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12383 false, false, false, 16);
12385 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12388 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12389 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12390 false, false, false, 16);
12391 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12392 // TODO: Are there any fast-math-flags to propagate here?
12393 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12396 if (Subtarget->hasSSE3()) {
12397 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12398 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12400 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12401 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12403 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12404 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12407 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12408 DAG.getIntPtrConstant(0, dl));
12411 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12412 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12413 SelectionDAG &DAG) const {
12415 // FP constant to bias correct the final result.
12416 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12419 // Load the 32-bit value into an XMM register.
12420 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12423 // Zero out the upper parts of the register.
12424 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12426 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12427 DAG.getBitcast(MVT::v2f64, Load),
12428 DAG.getIntPtrConstant(0, dl));
12430 // Or the load with the bias.
12431 SDValue Or = DAG.getNode(
12432 ISD::OR, dl, MVT::v2i64,
12433 DAG.getBitcast(MVT::v2i64,
12434 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12435 DAG.getBitcast(MVT::v2i64,
12436 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12438 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12439 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12441 // Subtract the bias.
12442 // TODO: Are there any fast-math-flags to propagate here?
12443 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12445 // Handle final rounding.
12446 EVT DestVT = Op.getValueType();
12448 if (DestVT.bitsLT(MVT::f64))
12449 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12450 DAG.getIntPtrConstant(0, dl));
12451 if (DestVT.bitsGT(MVT::f64))
12452 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12454 // Handle final rounding.
12458 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12459 const X86Subtarget &Subtarget) {
12460 // The algorithm is the following:
12461 // #ifdef __SSE4_1__
12462 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12463 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12464 // (uint4) 0x53000000, 0xaa);
12466 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12467 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12469 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12470 // return (float4) lo + fhi;
12473 SDValue V = Op->getOperand(0);
12474 EVT VecIntVT = V.getValueType();
12475 bool Is128 = VecIntVT == MVT::v4i32;
12476 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12477 // If we convert to something else than the supported type, e.g., to v4f64,
12479 if (VecFloatVT != Op->getValueType(0))
12482 unsigned NumElts = VecIntVT.getVectorNumElements();
12483 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12484 "Unsupported custom type");
12485 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12487 // In the #idef/#else code, we have in common:
12488 // - The vector of constants:
12494 // Create the splat vector for 0x4b000000.
12495 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12496 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12497 CstLow, CstLow, CstLow, CstLow};
12498 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12499 makeArrayRef(&CstLowArray[0], NumElts));
12500 // Create the splat vector for 0x53000000.
12501 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12502 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12503 CstHigh, CstHigh, CstHigh, CstHigh};
12504 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12505 makeArrayRef(&CstHighArray[0], NumElts));
12507 // Create the right shift.
12508 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12509 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12510 CstShift, CstShift, CstShift, CstShift};
12511 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12512 makeArrayRef(&CstShiftArray[0], NumElts));
12513 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12516 if (Subtarget.hasSSE41()) {
12517 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12518 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12519 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12520 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12521 // Low will be bitcasted right away, so do not bother bitcasting back to its
12523 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12524 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12525 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12526 // (uint4) 0x53000000, 0xaa);
12527 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12528 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12529 // High will be bitcasted right away, so do not bother bitcasting back to
12530 // its original type.
12531 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12532 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12534 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12535 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12536 CstMask, CstMask, CstMask);
12537 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12538 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12539 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12541 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12542 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12545 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12546 SDValue CstFAdd = DAG.getConstantFP(
12547 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12548 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12549 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12550 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12551 makeArrayRef(&CstFAddArray[0], NumElts));
12553 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12554 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12555 // TODO: Are there any fast-math-flags to propagate here?
12557 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12558 // return (float4) lo + fhi;
12559 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12560 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12563 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12564 SelectionDAG &DAG) const {
12565 SDValue N0 = Op.getOperand(0);
12566 MVT SVT = N0.getSimpleValueType();
12569 switch (SVT.SimpleTy) {
12571 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12576 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12577 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12578 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12582 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12585 if (Subtarget->hasAVX512())
12586 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12587 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12589 llvm_unreachable(nullptr);
12592 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12593 SelectionDAG &DAG) const {
12594 SDValue N0 = Op.getOperand(0);
12596 auto PtrVT = getPointerTy(DAG.getDataLayout());
12598 if (Op.getValueType().isVector())
12599 return lowerUINT_TO_FP_vec(Op, DAG);
12601 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12602 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12603 // the optimization here.
12604 if (DAG.SignBitIsZero(N0))
12605 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12607 MVT SrcVT = N0.getSimpleValueType();
12608 MVT DstVT = Op.getSimpleValueType();
12610 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12611 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12612 // Conversions from unsigned i32 to f32/f64 are legal,
12613 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12617 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12618 return LowerUINT_TO_FP_i64(Op, DAG);
12619 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12620 return LowerUINT_TO_FP_i32(Op, DAG);
12621 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12624 // Make a 64-bit buffer, and use it to build an FILD.
12625 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12626 if (SrcVT == MVT::i32) {
12627 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12628 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12629 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12630 StackSlot, MachinePointerInfo(),
12632 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12633 OffsetSlot, MachinePointerInfo(),
12635 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12639 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12640 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12641 StackSlot, MachinePointerInfo(),
12643 // For i64 source, we need to add the appropriate power of 2 if the input
12644 // was negative. This is the same as the optimization in
12645 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12646 // we must be careful to do the computation in x87 extended precision, not
12647 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12648 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12649 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12650 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12651 MachineMemOperand::MOLoad, 8, 8);
12653 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12654 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12655 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12658 APInt FF(32, 0x5F800000ULL);
12660 // Check whether the sign bit is set.
12661 SDValue SignSet = DAG.getSetCC(
12662 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12663 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12665 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12666 SDValue FudgePtr = DAG.getConstantPool(
12667 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12669 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12670 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12671 SDValue Four = DAG.getIntPtrConstant(4, dl);
12672 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12674 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12676 // Load the value out, extending it from f32 to f80.
12677 // FIXME: Avoid the extend by constructing the right constant pool?
12678 SDValue Fudge = DAG.getExtLoad(
12679 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12680 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12681 false, false, false, 4);
12682 // Extend everything to 80 bits to force it to be done on x87.
12683 // TODO: Are there any fast-math-flags to propagate here?
12684 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12685 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12686 DAG.getIntPtrConstant(0, dl));
12689 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12690 // is legal, or has an f16 source (which needs to be promoted to f32),
12691 // just return an <SDValue(), SDValue()> pair.
12692 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12693 // to i16, i32 or i64, and we lower it to a legal sequence.
12694 // If lowered to the final integer result we return a <result, SDValue()> pair.
12695 // Otherwise we lower it to a sequence ending with a FIST, return a
12696 // <FIST, StackSlot> pair, and the caller is responsible for loading
12697 // the final integer result from StackSlot.
12698 std::pair<SDValue,SDValue>
12699 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12700 bool IsSigned, bool IsReplace) const {
12703 EVT DstTy = Op.getValueType();
12704 EVT TheVT = Op.getOperand(0).getValueType();
12705 auto PtrVT = getPointerTy(DAG.getDataLayout());
12707 if (TheVT == MVT::f16)
12708 // We need to promote the f16 to f32 before using the lowering
12709 // in this routine.
12710 return std::make_pair(SDValue(), SDValue());
12712 assert((TheVT == MVT::f32 ||
12713 TheVT == MVT::f64 ||
12714 TheVT == MVT::f80) &&
12715 "Unexpected FP operand type in FP_TO_INTHelper");
12717 // If using FIST to compute an unsigned i64, we'll need some fixup
12718 // to handle values above the maximum signed i64. A FIST is always
12719 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12720 bool UnsignedFixup = !IsSigned &&
12721 DstTy == MVT::i64 &&
12722 (!Subtarget->is64Bit() ||
12723 !isScalarFPTypeInSSEReg(TheVT));
12725 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12726 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12727 // The low 32 bits of the fist result will have the correct uint32 result.
12728 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12732 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12733 DstTy.getSimpleVT() >= MVT::i16 &&
12734 "Unknown FP_TO_INT to lower!");
12736 // These are really Legal.
12737 if (DstTy == MVT::i32 &&
12738 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12739 return std::make_pair(SDValue(), SDValue());
12740 if (Subtarget->is64Bit() &&
12741 DstTy == MVT::i64 &&
12742 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12743 return std::make_pair(SDValue(), SDValue());
12745 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12747 MachineFunction &MF = DAG.getMachineFunction();
12748 unsigned MemSize = DstTy.getSizeInBits()/8;
12749 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12750 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12753 switch (DstTy.getSimpleVT().SimpleTy) {
12754 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12755 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12756 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12757 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12760 SDValue Chain = DAG.getEntryNode();
12761 SDValue Value = Op.getOperand(0);
12762 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12764 if (UnsignedFixup) {
12766 // Conversion to unsigned i64 is implemented with a select,
12767 // depending on whether the source value fits in the range
12768 // of a signed i64. Let Thresh be the FP equivalent of
12769 // 0x8000000000000000ULL.
12771 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12772 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12773 // Fist-to-mem64 FistSrc
12774 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12775 // to XOR'ing the high 32 bits with Adjust.
12777 // Being a power of 2, Thresh is exactly representable in all FP formats.
12778 // For X87 we'd like to use the smallest FP type for this constant, but
12779 // for DAG type consistency we have to match the FP operand type.
12781 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12782 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12783 bool LosesInfo = false;
12784 if (TheVT == MVT::f64)
12785 // The rounding mode is irrelevant as the conversion should be exact.
12786 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12788 else if (TheVT == MVT::f80)
12789 Status = Thresh.convert(APFloat::x87DoubleExtended,
12790 APFloat::rmNearestTiesToEven, &LosesInfo);
12792 assert(Status == APFloat::opOK && !LosesInfo &&
12793 "FP conversion should have been exact");
12795 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12797 SDValue Cmp = DAG.getSetCC(DL,
12798 getSetCCResultType(DAG.getDataLayout(),
12799 *DAG.getContext(), TheVT),
12800 Value, ThreshVal, ISD::SETLT);
12801 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12802 DAG.getConstant(0, DL, MVT::i32),
12803 DAG.getConstant(0x80000000, DL, MVT::i32));
12804 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12805 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12806 *DAG.getContext(), TheVT),
12807 Value, ThreshVal, ISD::SETLT);
12808 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12811 // FIXME This causes a redundant load/store if the SSE-class value is already
12812 // in memory, such as if it is on the callstack.
12813 if (isScalarFPTypeInSSEReg(TheVT)) {
12814 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12815 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12816 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12818 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12820 Chain, StackSlot, DAG.getValueType(TheVT)
12823 MachineMemOperand *MMO =
12824 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12825 MachineMemOperand::MOLoad, MemSize, MemSize);
12826 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12827 Chain = Value.getValue(1);
12828 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12829 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12832 MachineMemOperand *MMO =
12833 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12834 MachineMemOperand::MOStore, MemSize, MemSize);
12836 if (UnsignedFixup) {
12838 // Insert the FIST, load its result as two i32's,
12839 // and XOR the high i32 with Adjust.
12841 SDValue FistOps[] = { Chain, Value, StackSlot };
12842 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12843 FistOps, DstTy, MMO);
12845 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12846 MachinePointerInfo(),
12847 false, false, false, 0);
12848 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12849 DAG.getConstant(4, DL, PtrVT));
12851 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12852 MachinePointerInfo(),
12853 false, false, false, 0);
12854 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12856 if (Subtarget->is64Bit()) {
12857 // Join High32 and Low32 into a 64-bit result.
12858 // (High32 << 32) | Low32
12859 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12860 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12861 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12862 DAG.getConstant(32, DL, MVT::i8));
12863 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12864 return std::make_pair(Result, SDValue());
12867 SDValue ResultOps[] = { Low32, High32 };
12869 SDValue pair = IsReplace
12870 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12871 : DAG.getMergeValues(ResultOps, DL);
12872 return std::make_pair(pair, SDValue());
12874 // Build the FP_TO_INT*_IN_MEM
12875 SDValue Ops[] = { Chain, Value, StackSlot };
12876 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12878 return std::make_pair(FIST, StackSlot);
12882 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12883 const X86Subtarget *Subtarget) {
12884 MVT VT = Op->getSimpleValueType(0);
12885 SDValue In = Op->getOperand(0);
12886 MVT InVT = In.getSimpleValueType();
12889 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12890 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12892 // Optimize vectors in AVX mode:
12895 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12896 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12897 // Concat upper and lower parts.
12900 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12901 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12902 // Concat upper and lower parts.
12905 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12906 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12907 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12910 if (Subtarget->hasInt256())
12911 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12913 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12914 SDValue Undef = DAG.getUNDEF(InVT);
12915 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12916 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12917 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12919 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12920 VT.getVectorNumElements()/2);
12922 OpLo = DAG.getBitcast(HVT, OpLo);
12923 OpHi = DAG.getBitcast(HVT, OpHi);
12925 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12928 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12929 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12930 MVT VT = Op->getSimpleValueType(0);
12931 SDValue In = Op->getOperand(0);
12932 MVT InVT = In.getSimpleValueType();
12934 unsigned int NumElts = VT.getVectorNumElements();
12935 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12938 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12939 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12941 assert(InVT.getVectorElementType() == MVT::i1);
12942 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12944 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12946 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12948 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12949 if (VT.is512BitVector())
12951 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12954 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12955 SelectionDAG &DAG) {
12956 if (Subtarget->hasFp256())
12957 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12963 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12964 SelectionDAG &DAG) {
12966 MVT VT = Op.getSimpleValueType();
12967 SDValue In = Op.getOperand(0);
12968 MVT SVT = In.getSimpleValueType();
12970 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12971 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12973 if (Subtarget->hasFp256())
12974 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12977 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12978 VT.getVectorNumElements() != SVT.getVectorNumElements());
12982 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12984 MVT VT = Op.getSimpleValueType();
12985 SDValue In = Op.getOperand(0);
12986 MVT InVT = In.getSimpleValueType();
12988 if (VT == MVT::i1) {
12989 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12990 "Invalid scalar TRUNCATE operation");
12991 if (InVT.getSizeInBits() >= 32)
12993 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12994 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12996 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12997 "Invalid TRUNCATE operation");
12999 // move vector to mask - truncate solution for SKX
13000 if (VT.getVectorElementType() == MVT::i1) {
13001 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13002 Subtarget->hasBWI())
13003 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13004 if ((InVT.is256BitVector() || InVT.is128BitVector())
13005 && InVT.getScalarSizeInBits() <= 16 &&
13006 Subtarget->hasBWI() && Subtarget->hasVLX())
13007 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13008 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13009 Subtarget->hasDQI())
13010 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13011 if ((InVT.is256BitVector() || InVT.is128BitVector())
13012 && InVT.getScalarSizeInBits() >= 32 &&
13013 Subtarget->hasDQI() && Subtarget->hasVLX())
13014 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13017 if (VT.getVectorElementType() == MVT::i1) {
13018 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13019 unsigned NumElts = InVT.getVectorNumElements();
13020 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13021 if (InVT.getSizeInBits() < 512) {
13022 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13023 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13028 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13029 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13030 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13033 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13034 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13035 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13036 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13038 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13039 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13040 if (Subtarget->hasInt256()) {
13041 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13042 In = DAG.getBitcast(MVT::v8i32, In);
13043 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13045 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13046 DAG.getIntPtrConstant(0, DL));
13049 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13050 DAG.getIntPtrConstant(0, DL));
13051 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13052 DAG.getIntPtrConstant(2, DL));
13053 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13054 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13055 static const int ShufMask[] = {0, 2, 4, 6};
13056 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13059 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13060 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13061 if (Subtarget->hasInt256()) {
13062 In = DAG.getBitcast(MVT::v32i8, In);
13064 SmallVector<SDValue,32> pshufbMask;
13065 for (unsigned i = 0; i < 2; ++i) {
13066 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13067 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13068 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13069 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13070 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13071 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13072 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13073 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13074 for (unsigned j = 0; j < 8; ++j)
13075 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13077 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13078 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13079 In = DAG.getBitcast(MVT::v4i64, In);
13081 static const int ShufMask[] = {0, 2, -1, -1};
13082 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13084 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13085 DAG.getIntPtrConstant(0, DL));
13086 return DAG.getBitcast(VT, In);
13089 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13090 DAG.getIntPtrConstant(0, DL));
13092 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13093 DAG.getIntPtrConstant(4, DL));
13095 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13096 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13098 // The PSHUFB mask:
13099 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13100 -1, -1, -1, -1, -1, -1, -1, -1};
13102 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13103 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13104 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13106 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13107 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13109 // The MOVLHPS Mask:
13110 static const int ShufMask2[] = {0, 1, 4, 5};
13111 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13112 return DAG.getBitcast(MVT::v8i16, res);
13115 // Handle truncation of V256 to V128 using shuffles.
13116 if (!VT.is128BitVector() || !InVT.is256BitVector())
13119 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13121 unsigned NumElems = VT.getVectorNumElements();
13122 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13124 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13125 // Prepare truncation shuffle mask
13126 for (unsigned i = 0; i != NumElems; ++i)
13127 MaskVec[i] = i * 2;
13128 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13129 DAG.getUNDEF(NVT), &MaskVec[0]);
13130 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13131 DAG.getIntPtrConstant(0, DL));
13134 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13135 SelectionDAG &DAG) const {
13136 assert(!Op.getSimpleValueType().isVector());
13138 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13139 /*IsSigned=*/ true, /*IsReplace=*/ false);
13140 SDValue FIST = Vals.first, StackSlot = Vals.second;
13141 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13142 if (!FIST.getNode())
13145 if (StackSlot.getNode())
13146 // Load the result.
13147 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13148 FIST, StackSlot, MachinePointerInfo(),
13149 false, false, false, 0);
13151 // The node is the result.
13155 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13156 SelectionDAG &DAG) const {
13157 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13158 /*IsSigned=*/ false, /*IsReplace=*/ false);
13159 SDValue FIST = Vals.first, StackSlot = Vals.second;
13160 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13161 if (!FIST.getNode())
13164 if (StackSlot.getNode())
13165 // Load the result.
13166 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13167 FIST, StackSlot, MachinePointerInfo(),
13168 false, false, false, 0);
13170 // The node is the result.
13174 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13176 MVT VT = Op.getSimpleValueType();
13177 SDValue In = Op.getOperand(0);
13178 MVT SVT = In.getSimpleValueType();
13180 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13182 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13183 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13184 In, DAG.getUNDEF(SVT)));
13187 /// The only differences between FABS and FNEG are the mask and the logic op.
13188 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13189 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13190 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13191 "Wrong opcode for lowering FABS or FNEG.");
13193 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13195 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13196 // into an FNABS. We'll lower the FABS after that if it is still in use.
13198 for (SDNode *User : Op->uses())
13199 if (User->getOpcode() == ISD::FNEG)
13203 MVT VT = Op.getSimpleValueType();
13205 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13206 // decide if we should generate a 16-byte constant mask when we only need 4 or
13207 // 8 bytes for the scalar case.
13213 if (VT.isVector()) {
13215 EltVT = VT.getVectorElementType();
13216 NumElts = VT.getVectorNumElements();
13218 // There are no scalar bitwise logical SSE/AVX instructions, so we
13219 // generate a 16-byte vector constant and logic op even for the scalar case.
13220 // Using a 16-byte mask allows folding the load of the mask with
13221 // the logic op, so it can save (~4 bytes) on code size.
13222 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13224 NumElts = (VT == MVT::f64) ? 2 : 4;
13227 unsigned EltBits = EltVT.getSizeInBits();
13228 LLVMContext *Context = DAG.getContext();
13229 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13231 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13232 Constant *C = ConstantInt::get(*Context, MaskElt);
13233 C = ConstantVector::getSplat(NumElts, C);
13234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13235 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13236 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13238 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13239 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13240 false, false, false, Alignment);
13242 SDValue Op0 = Op.getOperand(0);
13243 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13245 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13246 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13249 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13251 // For the scalar case extend to a 128-bit vector, perform the logic op,
13252 // and extract the scalar result back out.
13253 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13254 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13255 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13256 DAG.getIntPtrConstant(0, dl));
13259 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13260 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13261 LLVMContext *Context = DAG.getContext();
13262 SDValue Op0 = Op.getOperand(0);
13263 SDValue Op1 = Op.getOperand(1);
13265 MVT VT = Op.getSimpleValueType();
13266 MVT SrcVT = Op1.getSimpleValueType();
13268 // If second operand is smaller, extend it first.
13269 if (SrcVT.bitsLT(VT)) {
13270 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13273 // And if it is bigger, shrink it first.
13274 if (SrcVT.bitsGT(VT)) {
13275 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13279 // At this point the operands and the result should have the same
13280 // type, and that won't be f80 since that is not custom lowered.
13282 const fltSemantics &Sem =
13283 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13284 const unsigned SizeInBits = VT.getSizeInBits();
13286 SmallVector<Constant *, 4> CV(
13287 VT == MVT::f64 ? 2 : 4,
13288 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13290 // First, clear all bits but the sign bit from the second operand (sign).
13291 CV[0] = ConstantFP::get(*Context,
13292 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13293 Constant *C = ConstantVector::get(CV);
13294 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13295 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13297 // Perform all logic operations as 16-byte vectors because there are no
13298 // scalar FP logic instructions in SSE. This allows load folding of the
13299 // constants into the logic instructions.
13300 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13302 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13303 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13304 false, false, false, 16);
13305 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13306 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13308 // Next, clear the sign bit from the first operand (magnitude).
13309 // If it's a constant, we can clear it here.
13310 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13311 APFloat APF = Op0CN->getValueAPF();
13312 // If the magnitude is a positive zero, the sign bit alone is enough.
13313 if (APF.isPosZero())
13314 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13315 DAG.getIntPtrConstant(0, dl));
13317 CV[0] = ConstantFP::get(*Context, APF);
13319 CV[0] = ConstantFP::get(
13321 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13323 C = ConstantVector::get(CV);
13324 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13326 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13327 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13328 false, false, false, 16);
13329 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13330 if (!isa<ConstantFPSDNode>(Op0)) {
13331 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13332 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13334 // OR the magnitude value with the sign bit.
13335 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13336 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13337 DAG.getIntPtrConstant(0, dl));
13340 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13341 SDValue N0 = Op.getOperand(0);
13343 MVT VT = Op.getSimpleValueType();
13345 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13346 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13347 DAG.getConstant(1, dl, VT));
13348 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13351 // Check whether an OR'd tree is PTEST-able.
13352 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13353 SelectionDAG &DAG) {
13354 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13356 if (!Subtarget->hasSSE41())
13359 if (!Op->hasOneUse())
13362 SDNode *N = Op.getNode();
13365 SmallVector<SDValue, 8> Opnds;
13366 DenseMap<SDValue, unsigned> VecInMap;
13367 SmallVector<SDValue, 8> VecIns;
13368 EVT VT = MVT::Other;
13370 // Recognize a special case where a vector is casted into wide integer to
13372 Opnds.push_back(N->getOperand(0));
13373 Opnds.push_back(N->getOperand(1));
13375 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13376 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13377 // BFS traverse all OR'd operands.
13378 if (I->getOpcode() == ISD::OR) {
13379 Opnds.push_back(I->getOperand(0));
13380 Opnds.push_back(I->getOperand(1));
13381 // Re-evaluate the number of nodes to be traversed.
13382 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13386 // Quit if a non-EXTRACT_VECTOR_ELT
13387 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13390 // Quit if without a constant index.
13391 SDValue Idx = I->getOperand(1);
13392 if (!isa<ConstantSDNode>(Idx))
13395 SDValue ExtractedFromVec = I->getOperand(0);
13396 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13397 if (M == VecInMap.end()) {
13398 VT = ExtractedFromVec.getValueType();
13399 // Quit if not 128/256-bit vector.
13400 if (!VT.is128BitVector() && !VT.is256BitVector())
13402 // Quit if not the same type.
13403 if (VecInMap.begin() != VecInMap.end() &&
13404 VT != VecInMap.begin()->first.getValueType())
13406 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13407 VecIns.push_back(ExtractedFromVec);
13409 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13412 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13413 "Not extracted from 128-/256-bit vector.");
13415 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13417 for (DenseMap<SDValue, unsigned>::const_iterator
13418 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13419 // Quit if not all elements are used.
13420 if (I->second != FullMask)
13424 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13426 // Cast all vectors into TestVT for PTEST.
13427 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13428 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13430 // If more than one full vectors are evaluated, OR them first before PTEST.
13431 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13432 // Each iteration will OR 2 nodes and append the result until there is only
13433 // 1 node left, i.e. the final OR'd value of all vectors.
13434 SDValue LHS = VecIns[Slot];
13435 SDValue RHS = VecIns[Slot + 1];
13436 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13439 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13440 VecIns.back(), VecIns.back());
13443 /// \brief return true if \c Op has a use that doesn't just read flags.
13444 static bool hasNonFlagsUse(SDValue Op) {
13445 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13447 SDNode *User = *UI;
13448 unsigned UOpNo = UI.getOperandNo();
13449 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13450 // Look pass truncate.
13451 UOpNo = User->use_begin().getOperandNo();
13452 User = *User->use_begin();
13455 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13456 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13462 /// Emit nodes that will be selected as "test Op0,Op0", or something
13464 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13465 SelectionDAG &DAG) const {
13466 if (Op.getValueType() == MVT::i1) {
13467 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13468 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13469 DAG.getConstant(0, dl, MVT::i8));
13471 // CF and OF aren't always set the way we want. Determine which
13472 // of these we need.
13473 bool NeedCF = false;
13474 bool NeedOF = false;
13477 case X86::COND_A: case X86::COND_AE:
13478 case X86::COND_B: case X86::COND_BE:
13481 case X86::COND_G: case X86::COND_GE:
13482 case X86::COND_L: case X86::COND_LE:
13483 case X86::COND_O: case X86::COND_NO: {
13484 // Check if we really need to set the
13485 // Overflow flag. If NoSignedWrap is present
13486 // that is not actually needed.
13487 switch (Op->getOpcode()) {
13492 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13493 if (BinNode->Flags.hasNoSignedWrap())
13503 // See if we can use the EFLAGS value from the operand instead of
13504 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13505 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13506 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13507 // Emit a CMP with 0, which is the TEST pattern.
13508 //if (Op.getValueType() == MVT::i1)
13509 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13510 // DAG.getConstant(0, MVT::i1));
13511 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13512 DAG.getConstant(0, dl, Op.getValueType()));
13514 unsigned Opcode = 0;
13515 unsigned NumOperands = 0;
13517 // Truncate operations may prevent the merge of the SETCC instruction
13518 // and the arithmetic instruction before it. Attempt to truncate the operands
13519 // of the arithmetic instruction and use a reduced bit-width instruction.
13520 bool NeedTruncation = false;
13521 SDValue ArithOp = Op;
13522 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13523 SDValue Arith = Op->getOperand(0);
13524 // Both the trunc and the arithmetic op need to have one user each.
13525 if (Arith->hasOneUse())
13526 switch (Arith.getOpcode()) {
13533 NeedTruncation = true;
13539 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13540 // which may be the result of a CAST. We use the variable 'Op', which is the
13541 // non-casted variable when we check for possible users.
13542 switch (ArithOp.getOpcode()) {
13544 // Due to an isel shortcoming, be conservative if this add is likely to be
13545 // selected as part of a load-modify-store instruction. When the root node
13546 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13547 // uses of other nodes in the match, such as the ADD in this case. This
13548 // leads to the ADD being left around and reselected, with the result being
13549 // two adds in the output. Alas, even if none our users are stores, that
13550 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13551 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13552 // climbing the DAG back to the root, and it doesn't seem to be worth the
13554 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13555 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13556 if (UI->getOpcode() != ISD::CopyToReg &&
13557 UI->getOpcode() != ISD::SETCC &&
13558 UI->getOpcode() != ISD::STORE)
13561 if (ConstantSDNode *C =
13562 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13563 // An add of one will be selected as an INC.
13564 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13565 Opcode = X86ISD::INC;
13570 // An add of negative one (subtract of one) will be selected as a DEC.
13571 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13572 Opcode = X86ISD::DEC;
13578 // Otherwise use a regular EFLAGS-setting add.
13579 Opcode = X86ISD::ADD;
13584 // If we have a constant logical shift that's only used in a comparison
13585 // against zero turn it into an equivalent AND. This allows turning it into
13586 // a TEST instruction later.
13587 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13588 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13589 EVT VT = Op.getValueType();
13590 unsigned BitWidth = VT.getSizeInBits();
13591 unsigned ShAmt = Op->getConstantOperandVal(1);
13592 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13594 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13595 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13596 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13597 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13599 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13600 DAG.getConstant(Mask, dl, VT));
13601 DAG.ReplaceAllUsesWith(Op, New);
13607 // If the primary and result isn't used, don't bother using X86ISD::AND,
13608 // because a TEST instruction will be better.
13609 if (!hasNonFlagsUse(Op))
13615 // Due to the ISEL shortcoming noted above, be conservative if this op is
13616 // likely to be selected as part of a load-modify-store instruction.
13617 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13618 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13619 if (UI->getOpcode() == ISD::STORE)
13622 // Otherwise use a regular EFLAGS-setting instruction.
13623 switch (ArithOp.getOpcode()) {
13624 default: llvm_unreachable("unexpected operator!");
13625 case ISD::SUB: Opcode = X86ISD::SUB; break;
13626 case ISD::XOR: Opcode = X86ISD::XOR; break;
13627 case ISD::AND: Opcode = X86ISD::AND; break;
13629 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13630 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13631 if (EFLAGS.getNode())
13634 Opcode = X86ISD::OR;
13648 return SDValue(Op.getNode(), 1);
13654 // If we found that truncation is beneficial, perform the truncation and
13656 if (NeedTruncation) {
13657 EVT VT = Op.getValueType();
13658 SDValue WideVal = Op->getOperand(0);
13659 EVT WideVT = WideVal.getValueType();
13660 unsigned ConvertedOp = 0;
13661 // Use a target machine opcode to prevent further DAGCombine
13662 // optimizations that may separate the arithmetic operations
13663 // from the setcc node.
13664 switch (WideVal.getOpcode()) {
13666 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13667 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13668 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13669 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13670 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13674 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13675 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13676 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13677 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13678 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13684 // Emit a CMP with 0, which is the TEST pattern.
13685 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13686 DAG.getConstant(0, dl, Op.getValueType()));
13688 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13689 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13691 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13692 DAG.ReplaceAllUsesWith(Op, New);
13693 return SDValue(New.getNode(), 1);
13696 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13698 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13699 SDLoc dl, SelectionDAG &DAG) const {
13700 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13701 if (C->getAPIntValue() == 0)
13702 return EmitTest(Op0, X86CC, dl, DAG);
13704 if (Op0.getValueType() == MVT::i1)
13705 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13708 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13709 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13710 // Do the comparison at i32 if it's smaller, besides the Atom case.
13711 // This avoids subregister aliasing issues. Keep the smaller reference
13712 // if we're optimizing for size, however, as that'll allow better folding
13713 // of memory operations.
13714 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13715 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13716 !Subtarget->isAtom()) {
13717 unsigned ExtendOp =
13718 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13719 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13720 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13722 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13723 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13724 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13726 return SDValue(Sub.getNode(), 1);
13728 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13731 /// Convert a comparison if required by the subtarget.
13732 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13733 SelectionDAG &DAG) const {
13734 // If the subtarget does not support the FUCOMI instruction, floating-point
13735 // comparisons have to be converted.
13736 if (Subtarget->hasCMov() ||
13737 Cmp.getOpcode() != X86ISD::CMP ||
13738 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13739 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13742 // The instruction selector will select an FUCOM instruction instead of
13743 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13744 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13745 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13747 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13748 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13749 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13750 DAG.getConstant(8, dl, MVT::i8));
13751 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13752 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13755 /// The minimum architected relative accuracy is 2^-12. We need one
13756 /// Newton-Raphson step to have a good float result (24 bits of precision).
13757 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13758 DAGCombinerInfo &DCI,
13759 unsigned &RefinementSteps,
13760 bool &UseOneConstNR) const {
13761 EVT VT = Op.getValueType();
13762 const char *RecipOp;
13764 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13765 // TODO: Add support for AVX512 (v16f32).
13766 // It is likely not profitable to do this for f64 because a double-precision
13767 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13768 // instructions: convert to single, rsqrtss, convert back to double, refine
13769 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13770 // along with FMA, this could be a throughput win.
13771 if (VT == MVT::f32 && Subtarget->hasSSE1())
13773 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13774 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13775 RecipOp = "vec-sqrtf";
13779 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13780 if (!Recips.isEnabled(RecipOp))
13783 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13784 UseOneConstNR = false;
13785 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13788 /// The minimum architected relative accuracy is 2^-12. We need one
13789 /// Newton-Raphson step to have a good float result (24 bits of precision).
13790 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13791 DAGCombinerInfo &DCI,
13792 unsigned &RefinementSteps) const {
13793 EVT VT = Op.getValueType();
13794 const char *RecipOp;
13796 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13797 // TODO: Add support for AVX512 (v16f32).
13798 // It is likely not profitable to do this for f64 because a double-precision
13799 // reciprocal estimate with refinement on x86 prior to FMA requires
13800 // 15 instructions: convert to single, rcpss, convert back to double, refine
13801 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13802 // along with FMA, this could be a throughput win.
13803 if (VT == MVT::f32 && Subtarget->hasSSE1())
13805 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13806 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13807 RecipOp = "vec-divf";
13811 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13812 if (!Recips.isEnabled(RecipOp))
13815 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13816 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13819 /// If we have at least two divisions that use the same divisor, convert to
13820 /// multplication by a reciprocal. This may need to be adjusted for a given
13821 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13822 /// This is because we still need one division to calculate the reciprocal and
13823 /// then we need two multiplies by that reciprocal as replacements for the
13824 /// original divisions.
13825 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13829 static bool isAllOnes(SDValue V) {
13830 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13831 return C && C->isAllOnesValue();
13834 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13835 /// if it's possible.
13836 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13837 SDLoc dl, SelectionDAG &DAG) const {
13838 SDValue Op0 = And.getOperand(0);
13839 SDValue Op1 = And.getOperand(1);
13840 if (Op0.getOpcode() == ISD::TRUNCATE)
13841 Op0 = Op0.getOperand(0);
13842 if (Op1.getOpcode() == ISD::TRUNCATE)
13843 Op1 = Op1.getOperand(0);
13846 if (Op1.getOpcode() == ISD::SHL)
13847 std::swap(Op0, Op1);
13848 if (Op0.getOpcode() == ISD::SHL) {
13849 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13850 if (And00C->getZExtValue() == 1) {
13851 // If we looked past a truncate, check that it's only truncating away
13853 unsigned BitWidth = Op0.getValueSizeInBits();
13854 unsigned AndBitWidth = And.getValueSizeInBits();
13855 if (BitWidth > AndBitWidth) {
13857 DAG.computeKnownBits(Op0, Zeros, Ones);
13858 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13862 RHS = Op0.getOperand(1);
13864 } else if (Op1.getOpcode() == ISD::Constant) {
13865 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13866 uint64_t AndRHSVal = AndRHS->getZExtValue();
13867 SDValue AndLHS = Op0;
13869 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13870 LHS = AndLHS.getOperand(0);
13871 RHS = AndLHS.getOperand(1);
13874 // Use BT if the immediate can't be encoded in a TEST instruction.
13875 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13877 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13881 if (LHS.getNode()) {
13882 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13883 // instruction. Since the shift amount is in-range-or-undefined, we know
13884 // that doing a bittest on the i32 value is ok. We extend to i32 because
13885 // the encoding for the i16 version is larger than the i32 version.
13886 // Also promote i16 to i32 for performance / code size reason.
13887 if (LHS.getValueType() == MVT::i8 ||
13888 LHS.getValueType() == MVT::i16)
13889 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13891 // If the operand types disagree, extend the shift amount to match. Since
13892 // BT ignores high bits (like shifts) we can use anyextend.
13893 if (LHS.getValueType() != RHS.getValueType())
13894 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13896 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13897 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13898 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13899 DAG.getConstant(Cond, dl, MVT::i8), BT);
13905 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13907 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13912 // SSE Condition code mapping:
13921 switch (SetCCOpcode) {
13922 default: llvm_unreachable("Unexpected SETCC condition");
13924 case ISD::SETEQ: SSECC = 0; break;
13926 case ISD::SETGT: Swap = true; // Fallthrough
13928 case ISD::SETOLT: SSECC = 1; break;
13930 case ISD::SETGE: Swap = true; // Fallthrough
13932 case ISD::SETOLE: SSECC = 2; break;
13933 case ISD::SETUO: SSECC = 3; break;
13935 case ISD::SETNE: SSECC = 4; break;
13936 case ISD::SETULE: Swap = true; // Fallthrough
13937 case ISD::SETUGE: SSECC = 5; break;
13938 case ISD::SETULT: Swap = true; // Fallthrough
13939 case ISD::SETUGT: SSECC = 6; break;
13940 case ISD::SETO: SSECC = 7; break;
13942 case ISD::SETONE: SSECC = 8; break;
13945 std::swap(Op0, Op1);
13950 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13951 // ones, and then concatenate the result back.
13952 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13953 MVT VT = Op.getSimpleValueType();
13955 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13956 "Unsupported value type for operation");
13958 unsigned NumElems = VT.getVectorNumElements();
13960 SDValue CC = Op.getOperand(2);
13962 // Extract the LHS vectors
13963 SDValue LHS = Op.getOperand(0);
13964 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13965 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13967 // Extract the RHS vectors
13968 SDValue RHS = Op.getOperand(1);
13969 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13970 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13972 // Issue the operation on the smaller types and concatenate the result back
13973 MVT EltVT = VT.getVectorElementType();
13974 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13975 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13976 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13977 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13980 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13981 SDValue Op0 = Op.getOperand(0);
13982 SDValue Op1 = Op.getOperand(1);
13983 SDValue CC = Op.getOperand(2);
13984 MVT VT = Op.getSimpleValueType();
13987 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13988 "Unexpected type for boolean compare operation");
13989 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13990 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13991 DAG.getConstant(-1, dl, VT));
13992 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13993 DAG.getConstant(-1, dl, VT));
13994 switch (SetCCOpcode) {
13995 default: llvm_unreachable("Unexpected SETCC condition");
13997 // (x == y) -> ~(x ^ y)
13998 return DAG.getNode(ISD::XOR, dl, VT,
13999 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14000 DAG.getConstant(-1, dl, VT));
14002 // (x != y) -> (x ^ y)
14003 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14006 // (x > y) -> (x & ~y)
14007 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14010 // (x < y) -> (~x & y)
14011 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14014 // (x <= y) -> (~x | y)
14015 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14018 // (x >=y) -> (x | ~y)
14019 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14023 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14024 const X86Subtarget *Subtarget) {
14025 SDValue Op0 = Op.getOperand(0);
14026 SDValue Op1 = Op.getOperand(1);
14027 SDValue CC = Op.getOperand(2);
14028 MVT VT = Op.getSimpleValueType();
14031 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14032 Op.getValueType().getScalarType() == MVT::i1 &&
14033 "Cannot set masked compare for this operation");
14035 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14037 bool Unsigned = false;
14040 switch (SetCCOpcode) {
14041 default: llvm_unreachable("Unexpected SETCC condition");
14042 case ISD::SETNE: SSECC = 4; break;
14043 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14044 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14045 case ISD::SETLT: Swap = true; //fall-through
14046 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14047 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14048 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14049 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14050 case ISD::SETULE: Unsigned = true; //fall-through
14051 case ISD::SETLE: SSECC = 2; break;
14055 std::swap(Op0, Op1);
14057 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14058 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14059 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14060 DAG.getConstant(SSECC, dl, MVT::i8));
14063 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14064 /// operand \p Op1. If non-trivial (for example because it's not constant)
14065 /// return an empty value.
14066 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14068 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14072 MVT VT = Op1.getSimpleValueType();
14073 MVT EVT = VT.getVectorElementType();
14074 unsigned n = VT.getVectorNumElements();
14075 SmallVector<SDValue, 8> ULTOp1;
14077 for (unsigned i = 0; i < n; ++i) {
14078 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14079 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14082 // Avoid underflow.
14083 APInt Val = Elt->getAPIntValue();
14087 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14090 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14093 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14094 SelectionDAG &DAG) {
14095 SDValue Op0 = Op.getOperand(0);
14096 SDValue Op1 = Op.getOperand(1);
14097 SDValue CC = Op.getOperand(2);
14098 MVT VT = Op.getSimpleValueType();
14099 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14100 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14105 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14106 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14109 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14110 unsigned Opc = X86ISD::CMPP;
14111 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14112 assert(VT.getVectorNumElements() <= 16);
14113 Opc = X86ISD::CMPM;
14115 // In the two special cases we can't handle, emit two comparisons.
14118 unsigned CombineOpc;
14119 if (SetCCOpcode == ISD::SETUEQ) {
14120 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14122 assert(SetCCOpcode == ISD::SETONE);
14123 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14126 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14127 DAG.getConstant(CC0, dl, MVT::i8));
14128 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14129 DAG.getConstant(CC1, dl, MVT::i8));
14130 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14132 // Handle all other FP comparisons here.
14133 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14134 DAG.getConstant(SSECC, dl, MVT::i8));
14137 // Break 256-bit integer vector compare into smaller ones.
14138 if (VT.is256BitVector() && !Subtarget->hasInt256())
14139 return Lower256IntVSETCC(Op, DAG);
14141 EVT OpVT = Op1.getValueType();
14142 if (OpVT.getVectorElementType() == MVT::i1)
14143 return LowerBoolVSETCC_AVX512(Op, DAG);
14145 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14146 if (Subtarget->hasAVX512()) {
14147 if (Op1.getValueType().is512BitVector() ||
14148 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14149 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14150 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14152 // In AVX-512 architecture setcc returns mask with i1 elements,
14153 // But there is no compare instruction for i8 and i16 elements in KNL.
14154 // We are not talking about 512-bit operands in this case, these
14155 // types are illegal.
14157 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14158 OpVT.getVectorElementType().getSizeInBits() >= 8))
14159 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14160 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14163 // We are handling one of the integer comparisons here. Since SSE only has
14164 // GT and EQ comparisons for integer, swapping operands and multiple
14165 // operations may be required for some comparisons.
14167 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14168 bool Subus = false;
14170 switch (SetCCOpcode) {
14171 default: llvm_unreachable("Unexpected SETCC condition");
14172 case ISD::SETNE: Invert = true;
14173 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14174 case ISD::SETLT: Swap = true;
14175 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14176 case ISD::SETGE: Swap = true;
14177 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14178 Invert = true; break;
14179 case ISD::SETULT: Swap = true;
14180 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14181 FlipSigns = true; break;
14182 case ISD::SETUGE: Swap = true;
14183 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14184 FlipSigns = true; Invert = true; break;
14187 // Special case: Use min/max operations for SETULE/SETUGE
14188 MVT VET = VT.getVectorElementType();
14190 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14191 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14194 switch (SetCCOpcode) {
14196 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14197 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14200 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14203 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14204 if (!MinMax && hasSubus) {
14205 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14207 // t = psubus Op0, Op1
14208 // pcmpeq t, <0..0>
14209 switch (SetCCOpcode) {
14211 case ISD::SETULT: {
14212 // If the comparison is against a constant we can turn this into a
14213 // setule. With psubus, setule does not require a swap. This is
14214 // beneficial because the constant in the register is no longer
14215 // destructed as the destination so it can be hoisted out of a loop.
14216 // Only do this pre-AVX since vpcmp* is no longer destructive.
14217 if (Subtarget->hasAVX())
14219 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14220 if (ULEOp1.getNode()) {
14222 Subus = true; Invert = false; Swap = false;
14226 // Psubus is better than flip-sign because it requires no inversion.
14227 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14228 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14232 Opc = X86ISD::SUBUS;
14238 std::swap(Op0, Op1);
14240 // Check that the operation in question is available (most are plain SSE2,
14241 // but PCMPGTQ and PCMPEQQ have different requirements).
14242 if (VT == MVT::v2i64) {
14243 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14244 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14246 // First cast everything to the right type.
14247 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14248 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14250 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14251 // bits of the inputs before performing those operations. The lower
14252 // compare is always unsigned.
14255 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14257 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14258 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14259 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14260 Sign, Zero, Sign, Zero);
14262 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14263 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14265 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14266 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14267 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14269 // Create masks for only the low parts/high parts of the 64 bit integers.
14270 static const int MaskHi[] = { 1, 1, 3, 3 };
14271 static const int MaskLo[] = { 0, 0, 2, 2 };
14272 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14273 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14274 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14276 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14277 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14280 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14282 return DAG.getBitcast(VT, Result);
14285 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14286 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14287 // pcmpeqd + pshufd + pand.
14288 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14290 // First cast everything to the right type.
14291 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14292 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14295 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14297 // Make sure the lower and upper halves are both all-ones.
14298 static const int Mask[] = { 1, 0, 3, 2 };
14299 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14300 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14303 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14305 return DAG.getBitcast(VT, Result);
14309 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14310 // bits of the inputs before performing those operations.
14312 EVT EltVT = VT.getVectorElementType();
14313 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14315 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14316 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14319 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14321 // If the logical-not of the result is required, perform that now.
14323 Result = DAG.getNOT(dl, Result, VT);
14326 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14329 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14330 getZeroVector(VT, Subtarget, DAG, dl));
14335 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14337 MVT VT = Op.getSimpleValueType();
14339 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14341 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14342 && "SetCC type must be 8-bit or 1-bit integer");
14343 SDValue Op0 = Op.getOperand(0);
14344 SDValue Op1 = Op.getOperand(1);
14346 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14348 // Optimize to BT if possible.
14349 // Lower (X & (1 << N)) == 0 to BT(X, N).
14350 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14351 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14352 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14353 Op1.getOpcode() == ISD::Constant &&
14354 cast<ConstantSDNode>(Op1)->isNullValue() &&
14355 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14356 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14357 if (NewSetCC.getNode()) {
14359 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14364 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14366 if (Op1.getOpcode() == ISD::Constant &&
14367 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14368 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14369 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14371 // If the input is a setcc, then reuse the input setcc or use a new one with
14372 // the inverted condition.
14373 if (Op0.getOpcode() == X86ISD::SETCC) {
14374 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14375 bool Invert = (CC == ISD::SETNE) ^
14376 cast<ConstantSDNode>(Op1)->isNullValue();
14380 CCode = X86::GetOppositeBranchCondition(CCode);
14381 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14382 DAG.getConstant(CCode, dl, MVT::i8),
14383 Op0.getOperand(1));
14385 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14389 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14390 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14391 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14393 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14394 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14397 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14398 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14399 if (X86CC == X86::COND_INVALID)
14402 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14403 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14404 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14405 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14407 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14411 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14412 static bool isX86LogicalCmp(SDValue Op) {
14413 unsigned Opc = Op.getNode()->getOpcode();
14414 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14415 Opc == X86ISD::SAHF)
14417 if (Op.getResNo() == 1 &&
14418 (Opc == X86ISD::ADD ||
14419 Opc == X86ISD::SUB ||
14420 Opc == X86ISD::ADC ||
14421 Opc == X86ISD::SBB ||
14422 Opc == X86ISD::SMUL ||
14423 Opc == X86ISD::UMUL ||
14424 Opc == X86ISD::INC ||
14425 Opc == X86ISD::DEC ||
14426 Opc == X86ISD::OR ||
14427 Opc == X86ISD::XOR ||
14428 Opc == X86ISD::AND))
14431 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14437 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14438 if (V.getOpcode() != ISD::TRUNCATE)
14441 SDValue VOp0 = V.getOperand(0);
14442 unsigned InBits = VOp0.getValueSizeInBits();
14443 unsigned Bits = V.getValueSizeInBits();
14444 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14447 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14448 bool addTest = true;
14449 SDValue Cond = Op.getOperand(0);
14450 SDValue Op1 = Op.getOperand(1);
14451 SDValue Op2 = Op.getOperand(2);
14453 EVT VT = Op1.getValueType();
14456 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14457 // are available or VBLENDV if AVX is available.
14458 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14459 if (Cond.getOpcode() == ISD::SETCC &&
14460 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14461 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14462 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14463 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14464 int SSECC = translateX86FSETCC(
14465 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14468 if (Subtarget->hasAVX512()) {
14469 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14470 DAG.getConstant(SSECC, DL, MVT::i8));
14471 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14474 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14475 DAG.getConstant(SSECC, DL, MVT::i8));
14477 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14478 // of 3 logic instructions for size savings and potentially speed.
14479 // Unfortunately, there is no scalar form of VBLENDV.
14481 // If either operand is a constant, don't try this. We can expect to
14482 // optimize away at least one of the logic instructions later in that
14483 // case, so that sequence would be faster than a variable blend.
14485 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14486 // uses XMM0 as the selection register. That may need just as many
14487 // instructions as the AND/ANDN/OR sequence due to register moves, so
14490 if (Subtarget->hasAVX() &&
14491 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14493 // Convert to vectors, do a VSELECT, and convert back to scalar.
14494 // All of the conversions should be optimized away.
14496 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14497 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14498 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14499 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14501 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14502 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14504 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14506 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14507 VSel, DAG.getIntPtrConstant(0, DL));
14509 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14510 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14511 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14515 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14517 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14518 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14519 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14520 Op1Scalar = Op1.getOperand(0);
14522 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14523 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14524 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14525 Op2Scalar = Op2.getOperand(0);
14526 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14527 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14528 Op1Scalar.getValueType(),
14529 Cond, Op1Scalar, Op2Scalar);
14530 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14531 return DAG.getBitcast(VT, newSelect);
14532 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14533 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14534 DAG.getIntPtrConstant(0, DL));
14538 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14539 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14540 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14541 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14542 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14543 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14544 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14546 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14549 if (Cond.getOpcode() == ISD::SETCC) {
14550 SDValue NewCond = LowerSETCC(Cond, DAG);
14551 if (NewCond.getNode())
14555 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14556 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14557 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14558 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14559 if (Cond.getOpcode() == X86ISD::SETCC &&
14560 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14561 isZero(Cond.getOperand(1).getOperand(1))) {
14562 SDValue Cmp = Cond.getOperand(1);
14564 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14566 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14567 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14568 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14570 SDValue CmpOp0 = Cmp.getOperand(0);
14571 // Apply further optimizations for special cases
14572 // (select (x != 0), -1, 0) -> neg & sbb
14573 // (select (x == 0), 0, -1) -> neg & sbb
14574 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14575 if (YC->isNullValue() &&
14576 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14577 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14578 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14579 DAG.getConstant(0, DL,
14580 CmpOp0.getValueType()),
14582 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14583 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14584 SDValue(Neg.getNode(), 1));
14588 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14589 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14590 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14592 SDValue Res = // Res = 0 or -1.
14593 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14594 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14596 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14597 Res = DAG.getNOT(DL, Res, Res.getValueType());
14599 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14600 if (!N2C || !N2C->isNullValue())
14601 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14606 // Look past (and (setcc_carry (cmp ...)), 1).
14607 if (Cond.getOpcode() == ISD::AND &&
14608 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14609 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14610 if (C && C->getAPIntValue() == 1)
14611 Cond = Cond.getOperand(0);
14614 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14615 // setting operand in place of the X86ISD::SETCC.
14616 unsigned CondOpcode = Cond.getOpcode();
14617 if (CondOpcode == X86ISD::SETCC ||
14618 CondOpcode == X86ISD::SETCC_CARRY) {
14619 CC = Cond.getOperand(0);
14621 SDValue Cmp = Cond.getOperand(1);
14622 unsigned Opc = Cmp.getOpcode();
14623 MVT VT = Op.getSimpleValueType();
14625 bool IllegalFPCMov = false;
14626 if (VT.isFloatingPoint() && !VT.isVector() &&
14627 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14628 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14630 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14631 Opc == X86ISD::BT) { // FIXME
14635 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14636 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14637 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14638 Cond.getOperand(0).getValueType() != MVT::i8)) {
14639 SDValue LHS = Cond.getOperand(0);
14640 SDValue RHS = Cond.getOperand(1);
14641 unsigned X86Opcode;
14644 switch (CondOpcode) {
14645 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14646 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14647 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14648 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14649 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14650 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14651 default: llvm_unreachable("unexpected overflowing operator");
14653 if (CondOpcode == ISD::UMULO)
14654 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14657 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14659 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14661 if (CondOpcode == ISD::UMULO)
14662 Cond = X86Op.getValue(2);
14664 Cond = X86Op.getValue(1);
14666 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14671 // Look past the truncate if the high bits are known zero.
14672 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14673 Cond = Cond.getOperand(0);
14675 // We know the result of AND is compared against zero. Try to match
14677 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14678 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14679 if (NewSetCC.getNode()) {
14680 CC = NewSetCC.getOperand(0);
14681 Cond = NewSetCC.getOperand(1);
14688 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14689 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14692 // a < b ? -1 : 0 -> RES = ~setcc_carry
14693 // a < b ? 0 : -1 -> RES = setcc_carry
14694 // a >= b ? -1 : 0 -> RES = setcc_carry
14695 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14696 if (Cond.getOpcode() == X86ISD::SUB) {
14697 Cond = ConvertCmpIfNecessary(Cond, DAG);
14698 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14700 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14701 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14702 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14703 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14705 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14706 return DAG.getNOT(DL, Res, Res.getValueType());
14711 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14712 // widen the cmov and push the truncate through. This avoids introducing a new
14713 // branch during isel and doesn't add any extensions.
14714 if (Op.getValueType() == MVT::i8 &&
14715 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14716 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14717 if (T1.getValueType() == T2.getValueType() &&
14718 // Blacklist CopyFromReg to avoid partial register stalls.
14719 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14720 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14721 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14722 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14726 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14727 // condition is true.
14728 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14729 SDValue Ops[] = { Op2, Op1, CC, Cond };
14730 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14733 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14734 const X86Subtarget *Subtarget,
14735 SelectionDAG &DAG) {
14736 MVT VT = Op->getSimpleValueType(0);
14737 SDValue In = Op->getOperand(0);
14738 MVT InVT = In.getSimpleValueType();
14739 MVT VTElt = VT.getVectorElementType();
14740 MVT InVTElt = InVT.getVectorElementType();
14744 if ((InVTElt == MVT::i1) &&
14745 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14746 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14748 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14749 VTElt.getSizeInBits() <= 16)) ||
14751 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14752 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14754 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14755 VTElt.getSizeInBits() >= 32))))
14756 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14758 unsigned int NumElts = VT.getVectorNumElements();
14760 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14763 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14764 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14765 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14766 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14769 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14770 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14772 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14775 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14777 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14778 if (VT.is512BitVector())
14780 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14783 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14784 const X86Subtarget *Subtarget,
14785 SelectionDAG &DAG) {
14786 SDValue In = Op->getOperand(0);
14787 MVT VT = Op->getSimpleValueType(0);
14788 MVT InVT = In.getSimpleValueType();
14789 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14791 MVT InSVT = InVT.getScalarType();
14792 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14794 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14796 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14801 // SSE41 targets can use the pmovsx* instructions directly.
14802 if (Subtarget->hasSSE41())
14803 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14805 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14809 // As SRAI is only available on i16/i32 types, we expand only up to i32
14810 // and handle i64 separately.
14811 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14812 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14813 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14814 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14815 Curr = DAG.getBitcast(CurrVT, Curr);
14818 SDValue SignExt = Curr;
14819 if (CurrVT != InVT) {
14820 unsigned SignExtShift =
14821 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14822 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14823 DAG.getConstant(SignExtShift, dl, MVT::i8));
14829 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14830 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14831 DAG.getConstant(31, dl, MVT::i8));
14832 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14833 return DAG.getBitcast(VT, Ext);
14839 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14840 SelectionDAG &DAG) {
14841 MVT VT = Op->getSimpleValueType(0);
14842 SDValue In = Op->getOperand(0);
14843 MVT InVT = In.getSimpleValueType();
14846 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14847 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14849 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14850 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14851 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14854 if (Subtarget->hasInt256())
14855 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14857 // Optimize vectors in AVX mode
14858 // Sign extend v8i16 to v8i32 and
14861 // Divide input vector into two parts
14862 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14863 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14864 // concat the vectors to original VT
14866 unsigned NumElems = InVT.getVectorNumElements();
14867 SDValue Undef = DAG.getUNDEF(InVT);
14869 SmallVector<int,8> ShufMask1(NumElems, -1);
14870 for (unsigned i = 0; i != NumElems/2; ++i)
14873 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14875 SmallVector<int,8> ShufMask2(NumElems, -1);
14876 for (unsigned i = 0; i != NumElems/2; ++i)
14877 ShufMask2[i] = i + NumElems/2;
14879 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14881 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14882 VT.getVectorNumElements()/2);
14884 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14885 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14887 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14890 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14891 // may emit an illegal shuffle but the expansion is still better than scalar
14892 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14893 // we'll emit a shuffle and a arithmetic shift.
14894 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14895 // TODO: It is possible to support ZExt by zeroing the undef values during
14896 // the shuffle phase or after the shuffle.
14897 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14898 SelectionDAG &DAG) {
14899 MVT RegVT = Op.getSimpleValueType();
14900 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14901 assert(RegVT.isInteger() &&
14902 "We only custom lower integer vector sext loads.");
14904 // Nothing useful we can do without SSE2 shuffles.
14905 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14907 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14909 EVT MemVT = Ld->getMemoryVT();
14910 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14911 unsigned RegSz = RegVT.getSizeInBits();
14913 ISD::LoadExtType Ext = Ld->getExtensionType();
14915 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14916 && "Only anyext and sext are currently implemented.");
14917 assert(MemVT != RegVT && "Cannot extend to the same type");
14918 assert(MemVT.isVector() && "Must load a vector from memory");
14920 unsigned NumElems = RegVT.getVectorNumElements();
14921 unsigned MemSz = MemVT.getSizeInBits();
14922 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14924 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14925 // The only way in which we have a legal 256-bit vector result but not the
14926 // integer 256-bit operations needed to directly lower a sextload is if we
14927 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14928 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14929 // correctly legalized. We do this late to allow the canonical form of
14930 // sextload to persist throughout the rest of the DAG combiner -- it wants
14931 // to fold together any extensions it can, and so will fuse a sign_extend
14932 // of an sextload into a sextload targeting a wider value.
14934 if (MemSz == 128) {
14935 // Just switch this to a normal load.
14936 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14937 "it must be a legal 128-bit vector "
14939 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14940 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14941 Ld->isInvariant(), Ld->getAlignment());
14943 assert(MemSz < 128 &&
14944 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14945 // Do an sext load to a 128-bit vector type. We want to use the same
14946 // number of elements, but elements half as wide. This will end up being
14947 // recursively lowered by this routine, but will succeed as we definitely
14948 // have all the necessary features if we're using AVX1.
14950 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14951 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14953 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14954 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14955 Ld->isNonTemporal(), Ld->isInvariant(),
14956 Ld->getAlignment());
14959 // Replace chain users with the new chain.
14960 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14961 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14963 // Finally, do a normal sign-extend to the desired register.
14964 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14967 // All sizes must be a power of two.
14968 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14969 "Non-power-of-two elements are not custom lowered!");
14971 // Attempt to load the original value using scalar loads.
14972 // Find the largest scalar type that divides the total loaded size.
14973 MVT SclrLoadTy = MVT::i8;
14974 for (MVT Tp : MVT::integer_valuetypes()) {
14975 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14980 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14981 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14983 SclrLoadTy = MVT::f64;
14985 // Calculate the number of scalar loads that we need to perform
14986 // in order to load our vector from memory.
14987 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14989 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14990 "Can only lower sext loads with a single scalar load!");
14992 unsigned loadRegZize = RegSz;
14993 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14996 // Represent our vector as a sequence of elements which are the
14997 // largest scalar that we can load.
14998 EVT LoadUnitVecVT = EVT::getVectorVT(
14999 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15001 // Represent the data using the same element type that is stored in
15002 // memory. In practice, we ''widen'' MemVT.
15004 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15005 loadRegZize / MemVT.getScalarType().getSizeInBits());
15007 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15008 "Invalid vector type");
15010 // We can't shuffle using an illegal type.
15011 assert(TLI.isTypeLegal(WideVecVT) &&
15012 "We only lower types that form legal widened vector types");
15014 SmallVector<SDValue, 8> Chains;
15015 SDValue Ptr = Ld->getBasePtr();
15016 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15017 TLI.getPointerTy(DAG.getDataLayout()));
15018 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15020 for (unsigned i = 0; i < NumLoads; ++i) {
15021 // Perform a single load.
15022 SDValue ScalarLoad =
15023 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15024 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15025 Ld->getAlignment());
15026 Chains.push_back(ScalarLoad.getValue(1));
15027 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15028 // another round of DAGCombining.
15030 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15032 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15033 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15035 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15038 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15040 // Bitcast the loaded value to a vector of the original element type, in
15041 // the size of the target vector type.
15042 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15043 unsigned SizeRatio = RegSz / MemSz;
15045 if (Ext == ISD::SEXTLOAD) {
15046 // If we have SSE4.1, we can directly emit a VSEXT node.
15047 if (Subtarget->hasSSE41()) {
15048 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15049 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15053 // Otherwise we'll shuffle the small elements in the high bits of the
15054 // larger type and perform an arithmetic shift. If the shift is not legal
15055 // it's better to scalarize.
15056 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15057 "We can't implement a sext load without an arithmetic right shift!");
15059 // Redistribute the loaded elements into the different locations.
15060 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15061 for (unsigned i = 0; i != NumElems; ++i)
15062 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15064 SDValue Shuff = DAG.getVectorShuffle(
15065 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15067 Shuff = DAG.getBitcast(RegVT, Shuff);
15069 // Build the arithmetic shift.
15070 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15071 MemVT.getVectorElementType().getSizeInBits();
15073 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
15074 DAG.getConstant(Amt, dl, RegVT));
15076 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15080 // Redistribute the loaded elements into the different locations.
15081 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15082 for (unsigned i = 0; i != NumElems; ++i)
15083 ShuffleVec[i * SizeRatio] = i;
15085 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15086 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15088 // Bitcast to the requested type.
15089 Shuff = DAG.getBitcast(RegVT, Shuff);
15090 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15094 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15095 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15096 // from the AND / OR.
15097 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15098 Opc = Op.getOpcode();
15099 if (Opc != ISD::OR && Opc != ISD::AND)
15101 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15102 Op.getOperand(0).hasOneUse() &&
15103 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15104 Op.getOperand(1).hasOneUse());
15107 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15108 // 1 and that the SETCC node has a single use.
15109 static bool isXor1OfSetCC(SDValue Op) {
15110 if (Op.getOpcode() != ISD::XOR)
15112 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15113 if (N1C && N1C->getAPIntValue() == 1) {
15114 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15115 Op.getOperand(0).hasOneUse();
15120 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15121 bool addTest = true;
15122 SDValue Chain = Op.getOperand(0);
15123 SDValue Cond = Op.getOperand(1);
15124 SDValue Dest = Op.getOperand(2);
15127 bool Inverted = false;
15129 if (Cond.getOpcode() == ISD::SETCC) {
15130 // Check for setcc([su]{add,sub,mul}o == 0).
15131 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15132 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15133 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15134 Cond.getOperand(0).getResNo() == 1 &&
15135 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15136 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15137 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15138 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15139 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15140 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15142 Cond = Cond.getOperand(0);
15144 SDValue NewCond = LowerSETCC(Cond, DAG);
15145 if (NewCond.getNode())
15150 // FIXME: LowerXALUO doesn't handle these!!
15151 else if (Cond.getOpcode() == X86ISD::ADD ||
15152 Cond.getOpcode() == X86ISD::SUB ||
15153 Cond.getOpcode() == X86ISD::SMUL ||
15154 Cond.getOpcode() == X86ISD::UMUL)
15155 Cond = LowerXALUO(Cond, DAG);
15158 // Look pass (and (setcc_carry (cmp ...)), 1).
15159 if (Cond.getOpcode() == ISD::AND &&
15160 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15161 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15162 if (C && C->getAPIntValue() == 1)
15163 Cond = Cond.getOperand(0);
15166 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15167 // setting operand in place of the X86ISD::SETCC.
15168 unsigned CondOpcode = Cond.getOpcode();
15169 if (CondOpcode == X86ISD::SETCC ||
15170 CondOpcode == X86ISD::SETCC_CARRY) {
15171 CC = Cond.getOperand(0);
15173 SDValue Cmp = Cond.getOperand(1);
15174 unsigned Opc = Cmp.getOpcode();
15175 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15176 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15180 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15184 // These can only come from an arithmetic instruction with overflow,
15185 // e.g. SADDO, UADDO.
15186 Cond = Cond.getNode()->getOperand(1);
15192 CondOpcode = Cond.getOpcode();
15193 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15194 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15195 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15196 Cond.getOperand(0).getValueType() != MVT::i8)) {
15197 SDValue LHS = Cond.getOperand(0);
15198 SDValue RHS = Cond.getOperand(1);
15199 unsigned X86Opcode;
15202 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15203 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15205 switch (CondOpcode) {
15206 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15208 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15210 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15213 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15214 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15216 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15218 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15221 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15222 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15223 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15224 default: llvm_unreachable("unexpected overflowing operator");
15227 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15228 if (CondOpcode == ISD::UMULO)
15229 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15232 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15234 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15236 if (CondOpcode == ISD::UMULO)
15237 Cond = X86Op.getValue(2);
15239 Cond = X86Op.getValue(1);
15241 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15245 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15246 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15247 if (CondOpc == ISD::OR) {
15248 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15249 // two branches instead of an explicit OR instruction with a
15251 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15252 isX86LogicalCmp(Cmp)) {
15253 CC = Cond.getOperand(0).getOperand(0);
15254 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15255 Chain, Dest, CC, Cmp);
15256 CC = Cond.getOperand(1).getOperand(0);
15260 } else { // ISD::AND
15261 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15262 // two branches instead of an explicit AND instruction with a
15263 // separate test. However, we only do this if this block doesn't
15264 // have a fall-through edge, because this requires an explicit
15265 // jmp when the condition is false.
15266 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15267 isX86LogicalCmp(Cmp) &&
15268 Op.getNode()->hasOneUse()) {
15269 X86::CondCode CCode =
15270 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15271 CCode = X86::GetOppositeBranchCondition(CCode);
15272 CC = DAG.getConstant(CCode, dl, MVT::i8);
15273 SDNode *User = *Op.getNode()->use_begin();
15274 // Look for an unconditional branch following this conditional branch.
15275 // We need this because we need to reverse the successors in order
15276 // to implement FCMP_OEQ.
15277 if (User->getOpcode() == ISD::BR) {
15278 SDValue FalseBB = User->getOperand(1);
15280 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15281 assert(NewBR == User);
15285 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15286 Chain, Dest, CC, Cmp);
15287 X86::CondCode CCode =
15288 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15289 CCode = X86::GetOppositeBranchCondition(CCode);
15290 CC = DAG.getConstant(CCode, dl, MVT::i8);
15296 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15297 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15298 // It should be transformed during dag combiner except when the condition
15299 // is set by a arithmetics with overflow node.
15300 X86::CondCode CCode =
15301 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15302 CCode = X86::GetOppositeBranchCondition(CCode);
15303 CC = DAG.getConstant(CCode, dl, MVT::i8);
15304 Cond = Cond.getOperand(0).getOperand(1);
15306 } else if (Cond.getOpcode() == ISD::SETCC &&
15307 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15308 // For FCMP_OEQ, we can emit
15309 // two branches instead of an explicit AND instruction with a
15310 // separate test. However, we only do this if this block doesn't
15311 // have a fall-through edge, because this requires an explicit
15312 // jmp when the condition is false.
15313 if (Op.getNode()->hasOneUse()) {
15314 SDNode *User = *Op.getNode()->use_begin();
15315 // Look for an unconditional branch following this conditional branch.
15316 // We need this because we need to reverse the successors in order
15317 // to implement FCMP_OEQ.
15318 if (User->getOpcode() == ISD::BR) {
15319 SDValue FalseBB = User->getOperand(1);
15321 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15322 assert(NewBR == User);
15326 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15327 Cond.getOperand(0), Cond.getOperand(1));
15328 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15329 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15330 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15331 Chain, Dest, CC, Cmp);
15332 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15337 } else if (Cond.getOpcode() == ISD::SETCC &&
15338 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15339 // For FCMP_UNE, we can emit
15340 // two branches instead of an explicit AND instruction with a
15341 // separate test. However, we only do this if this block doesn't
15342 // have a fall-through edge, because this requires an explicit
15343 // jmp when the condition is false.
15344 if (Op.getNode()->hasOneUse()) {
15345 SDNode *User = *Op.getNode()->use_begin();
15346 // Look for an unconditional branch following this conditional branch.
15347 // We need this because we need to reverse the successors in order
15348 // to implement FCMP_UNE.
15349 if (User->getOpcode() == ISD::BR) {
15350 SDValue FalseBB = User->getOperand(1);
15352 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15353 assert(NewBR == User);
15356 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15357 Cond.getOperand(0), Cond.getOperand(1));
15358 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15359 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15360 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15361 Chain, Dest, CC, Cmp);
15362 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15372 // Look pass the truncate if the high bits are known zero.
15373 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15374 Cond = Cond.getOperand(0);
15376 // We know the result of AND is compared against zero. Try to match
15378 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15379 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15380 if (NewSetCC.getNode()) {
15381 CC = NewSetCC.getOperand(0);
15382 Cond = NewSetCC.getOperand(1);
15389 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15390 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15391 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15393 Cond = ConvertCmpIfNecessary(Cond, DAG);
15394 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15395 Chain, Dest, CC, Cond);
15398 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15399 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15400 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15401 // that the guard pages used by the OS virtual memory manager are allocated in
15402 // correct sequence.
15404 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15405 SelectionDAG &DAG) const {
15406 MachineFunction &MF = DAG.getMachineFunction();
15407 bool SplitStack = MF.shouldSplitStack();
15408 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15413 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15414 SDNode* Node = Op.getNode();
15416 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15417 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15418 " not tell us which reg is the stack pointer!");
15419 EVT VT = Node->getValueType(0);
15420 SDValue Tmp1 = SDValue(Node, 0);
15421 SDValue Tmp2 = SDValue(Node, 1);
15422 SDValue Tmp3 = Node->getOperand(2);
15423 SDValue Chain = Tmp1.getOperand(0);
15425 // Chain the dynamic stack allocation so that it doesn't modify the stack
15426 // pointer when other instructions are using the stack.
15427 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15430 SDValue Size = Tmp2.getOperand(1);
15431 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15432 Chain = SP.getValue(1);
15433 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15434 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15435 unsigned StackAlign = TFI.getStackAlignment();
15436 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15437 if (Align > StackAlign)
15438 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15439 DAG.getConstant(-(uint64_t)Align, dl, VT));
15440 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15442 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15443 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15446 SDValue Ops[2] = { Tmp1, Tmp2 };
15447 return DAG.getMergeValues(Ops, dl);
15451 SDValue Chain = Op.getOperand(0);
15452 SDValue Size = Op.getOperand(1);
15453 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15454 EVT VT = Op.getNode()->getValueType(0);
15456 bool Is64Bit = Subtarget->is64Bit();
15457 MVT SPTy = getPointerTy(DAG.getDataLayout());
15460 MachineRegisterInfo &MRI = MF.getRegInfo();
15463 // The 64 bit implementation of segmented stacks needs to clobber both r10
15464 // r11. This makes it impossible to use it along with nested parameters.
15465 const Function *F = MF.getFunction();
15467 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15469 if (I->hasNestAttr())
15470 report_fatal_error("Cannot use segmented stacks with functions that "
15471 "have nested arguments.");
15474 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15475 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15476 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15477 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15478 DAG.getRegister(Vreg, SPTy));
15479 SDValue Ops1[2] = { Value, Chain };
15480 return DAG.getMergeValues(Ops1, dl);
15483 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15485 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15486 Flag = Chain.getValue(1);
15487 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15489 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15491 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15492 unsigned SPReg = RegInfo->getStackRegister();
15493 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15494 Chain = SP.getValue(1);
15497 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15498 DAG.getConstant(-(uint64_t)Align, dl, VT));
15499 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15502 SDValue Ops1[2] = { SP, Chain };
15503 return DAG.getMergeValues(Ops1, dl);
15507 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15508 MachineFunction &MF = DAG.getMachineFunction();
15509 auto PtrVT = getPointerTy(MF.getDataLayout());
15510 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15512 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15515 if (!Subtarget->is64Bit() ||
15516 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15517 // vastart just stores the address of the VarArgsFrameIndex slot into the
15518 // memory location argument.
15519 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15520 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15521 MachinePointerInfo(SV), false, false, 0);
15525 // gp_offset (0 - 6 * 8)
15526 // fp_offset (48 - 48 + 8 * 16)
15527 // overflow_arg_area (point to parameters coming in memory).
15529 SmallVector<SDValue, 8> MemOps;
15530 SDValue FIN = Op.getOperand(1);
15532 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15533 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15535 FIN, MachinePointerInfo(SV), false, false, 0);
15536 MemOps.push_back(Store);
15539 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15540 Store = DAG.getStore(Op.getOperand(0), DL,
15541 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15543 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15544 MemOps.push_back(Store);
15546 // Store ptr to overflow_arg_area
15547 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15548 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15549 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15550 MachinePointerInfo(SV, 8),
15552 MemOps.push_back(Store);
15554 // Store ptr to reg_save_area.
15555 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15556 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15557 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15558 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15559 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15560 MemOps.push_back(Store);
15561 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15564 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15565 assert(Subtarget->is64Bit() &&
15566 "LowerVAARG only handles 64-bit va_arg!");
15567 assert(Op.getNode()->getNumOperands() == 4);
15569 MachineFunction &MF = DAG.getMachineFunction();
15570 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15571 // The Win64 ABI uses char* instead of a structure.
15572 return DAG.expandVAArg(Op.getNode());
15574 SDValue Chain = Op.getOperand(0);
15575 SDValue SrcPtr = Op.getOperand(1);
15576 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15577 unsigned Align = Op.getConstantOperandVal(3);
15580 EVT ArgVT = Op.getNode()->getValueType(0);
15581 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15582 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15585 // Decide which area this value should be read from.
15586 // TODO: Implement the AMD64 ABI in its entirety. This simple
15587 // selection mechanism works only for the basic types.
15588 if (ArgVT == MVT::f80) {
15589 llvm_unreachable("va_arg for f80 not yet implemented");
15590 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15591 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15592 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15593 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15595 llvm_unreachable("Unhandled argument type in LowerVAARG");
15598 if (ArgMode == 2) {
15599 // Sanity Check: Make sure using fp_offset makes sense.
15600 assert(!Subtarget->useSoftFloat() &&
15601 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15602 Subtarget->hasSSE1());
15605 // Insert VAARG_64 node into the DAG
15606 // VAARG_64 returns two values: Variable Argument Address, Chain
15607 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15608 DAG.getConstant(ArgMode, dl, MVT::i8),
15609 DAG.getConstant(Align, dl, MVT::i32)};
15610 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15611 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15612 VTs, InstOps, MVT::i64,
15613 MachinePointerInfo(SV),
15615 /*Volatile=*/false,
15617 /*WriteMem=*/true);
15618 Chain = VAARG.getValue(1);
15620 // Load the next argument and return it
15621 return DAG.getLoad(ArgVT, dl,
15624 MachinePointerInfo(),
15625 false, false, false, 0);
15628 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15629 SelectionDAG &DAG) {
15630 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15631 // where a va_list is still an i8*.
15632 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15633 if (Subtarget->isCallingConvWin64(
15634 DAG.getMachineFunction().getFunction()->getCallingConv()))
15635 // Probably a Win64 va_copy.
15636 return DAG.expandVACopy(Op.getNode());
15638 SDValue Chain = Op.getOperand(0);
15639 SDValue DstPtr = Op.getOperand(1);
15640 SDValue SrcPtr = Op.getOperand(2);
15641 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15642 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15645 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15646 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15648 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15651 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15652 // amount is a constant. Takes immediate version of shift as input.
15653 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15654 SDValue SrcOp, uint64_t ShiftAmt,
15655 SelectionDAG &DAG) {
15656 MVT ElementType = VT.getVectorElementType();
15658 // Fold this packed shift into its first operand if ShiftAmt is 0.
15662 // Check for ShiftAmt >= element width
15663 if (ShiftAmt >= ElementType.getSizeInBits()) {
15664 if (Opc == X86ISD::VSRAI)
15665 ShiftAmt = ElementType.getSizeInBits() - 1;
15667 return DAG.getConstant(0, dl, VT);
15670 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15671 && "Unknown target vector shift-by-constant node");
15673 // Fold this packed vector shift into a build vector if SrcOp is a
15674 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15675 if (VT == SrcOp.getSimpleValueType() &&
15676 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15677 SmallVector<SDValue, 8> Elts;
15678 unsigned NumElts = SrcOp->getNumOperands();
15679 ConstantSDNode *ND;
15682 default: llvm_unreachable(nullptr);
15683 case X86ISD::VSHLI:
15684 for (unsigned i=0; i!=NumElts; ++i) {
15685 SDValue CurrentOp = SrcOp->getOperand(i);
15686 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15687 Elts.push_back(CurrentOp);
15690 ND = cast<ConstantSDNode>(CurrentOp);
15691 const APInt &C = ND->getAPIntValue();
15692 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15695 case X86ISD::VSRLI:
15696 for (unsigned i=0; i!=NumElts; ++i) {
15697 SDValue CurrentOp = SrcOp->getOperand(i);
15698 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15699 Elts.push_back(CurrentOp);
15702 ND = cast<ConstantSDNode>(CurrentOp);
15703 const APInt &C = ND->getAPIntValue();
15704 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15707 case X86ISD::VSRAI:
15708 for (unsigned i=0; i!=NumElts; ++i) {
15709 SDValue CurrentOp = SrcOp->getOperand(i);
15710 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15711 Elts.push_back(CurrentOp);
15714 ND = cast<ConstantSDNode>(CurrentOp);
15715 const APInt &C = ND->getAPIntValue();
15716 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15721 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15724 return DAG.getNode(Opc, dl, VT, SrcOp,
15725 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15728 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15729 // may or may not be a constant. Takes immediate version of shift as input.
15730 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15731 SDValue SrcOp, SDValue ShAmt,
15732 SelectionDAG &DAG) {
15733 MVT SVT = ShAmt.getSimpleValueType();
15734 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15736 // Catch shift-by-constant.
15737 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15738 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15739 CShAmt->getZExtValue(), DAG);
15741 // Change opcode to non-immediate version
15743 default: llvm_unreachable("Unknown target vector shift node");
15744 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15745 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15746 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15749 const X86Subtarget &Subtarget =
15750 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15751 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15752 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15753 // Let the shuffle legalizer expand this shift amount node.
15754 SDValue Op0 = ShAmt.getOperand(0);
15755 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15756 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15758 // Need to build a vector containing shift amount.
15759 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15760 SmallVector<SDValue, 4> ShOps;
15761 ShOps.push_back(ShAmt);
15762 if (SVT == MVT::i32) {
15763 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15764 ShOps.push_back(DAG.getUNDEF(SVT));
15766 ShOps.push_back(DAG.getUNDEF(SVT));
15768 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15769 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15772 // The return type has to be a 128-bit type with the same element
15773 // type as the input type.
15774 MVT EltVT = VT.getVectorElementType();
15775 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15777 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15778 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15781 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15782 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15783 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15784 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15785 SDValue PreservedSrc,
15786 const X86Subtarget *Subtarget,
15787 SelectionDAG &DAG) {
15788 EVT VT = Op.getValueType();
15789 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15790 MVT::i1, VT.getVectorNumElements());
15791 SDValue VMask = SDValue();
15792 unsigned OpcodeSelect = ISD::VSELECT;
15795 assert(MaskVT.isSimple() && "invalid mask type");
15797 if (isAllOnes(Mask))
15800 if (MaskVT.bitsGT(Mask.getValueType())) {
15801 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15802 MaskVT.getSizeInBits());
15803 VMask = DAG.getBitcast(MaskVT,
15804 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15806 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15807 Mask.getValueType().getSizeInBits());
15808 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15809 // are extracted by EXTRACT_SUBVECTOR.
15810 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15811 DAG.getBitcast(BitcastVT, Mask),
15812 DAG.getIntPtrConstant(0, dl));
15815 switch (Op.getOpcode()) {
15817 case X86ISD::PCMPEQM:
15818 case X86ISD::PCMPGTM:
15820 case X86ISD::CMPMU:
15821 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15822 case X86ISD::VFPCLASS:
15823 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15824 case X86ISD::VTRUNC:
15825 case X86ISD::VTRUNCS:
15826 case X86ISD::VTRUNCUS:
15827 // We can't use ISD::VSELECT here because it is not always "Legal"
15828 // for the destination type. For example vpmovqb require only AVX512
15829 // and vselect that can operate on byte element type require BWI
15830 OpcodeSelect = X86ISD::SELECT;
15833 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15834 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15835 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15838 /// \brief Creates an SDNode for a predicated scalar operation.
15839 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15840 /// The mask is coming as MVT::i8 and it should be truncated
15841 /// to MVT::i1 while lowering masking intrinsics.
15842 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15843 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15844 /// for a scalar instruction.
15845 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15846 SDValue PreservedSrc,
15847 const X86Subtarget *Subtarget,
15848 SelectionDAG &DAG) {
15849 if (isAllOnes(Mask))
15852 EVT VT = Op.getValueType();
15854 // The mask should be of type MVT::i1
15855 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15857 if (Op.getOpcode() == X86ISD::FSETCC)
15858 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15860 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15861 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15862 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15865 static int getSEHRegistrationNodeSize(const Function *Fn) {
15866 if (!Fn->hasPersonalityFn())
15867 report_fatal_error(
15868 "querying registration node size for function without personality");
15869 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15870 // WinEHStatePass for the full struct definition.
15871 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15872 case EHPersonality::MSVC_X86SEH: return 24;
15873 case EHPersonality::MSVC_CXX: return 16;
15876 report_fatal_error("can only recover FP for MSVC EH personality functions");
15879 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15880 /// function or when returning to a parent frame after catching an exception, we
15881 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15882 /// Here's the math:
15883 /// RegNodeBase = EntryEBP - RegNodeSize
15884 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15885 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15886 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15887 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15888 SDValue EntryEBP) {
15889 MachineFunction &MF = DAG.getMachineFunction();
15892 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15893 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15895 // It's possible that the parent function no longer has a personality function
15896 // if the exceptional code was optimized away, in which case we just return
15897 // the incoming EBP.
15898 if (!Fn->hasPersonalityFn())
15901 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15903 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15905 MCSymbol *OffsetSym =
15906 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15907 GlobalValue::getRealLinkageName(Fn->getName()));
15908 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15909 SDValue RegNodeFrameOffset =
15910 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15912 // RegNodeBase = EntryEBP - RegNodeSize
15913 // ParentFP = RegNodeBase - RegNodeFrameOffset
15914 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15915 DAG.getConstant(RegNodeSize, dl, PtrVT));
15916 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15919 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15920 SelectionDAG &DAG) {
15922 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15923 EVT VT = Op.getValueType();
15924 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15926 switch(IntrData->Type) {
15927 case INTR_TYPE_1OP:
15928 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15929 case INTR_TYPE_2OP:
15930 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15932 case INTR_TYPE_2OP_IMM8:
15933 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15934 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15935 case INTR_TYPE_3OP:
15936 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15937 Op.getOperand(2), Op.getOperand(3));
15938 case INTR_TYPE_4OP:
15939 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15940 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15941 case INTR_TYPE_1OP_MASK_RM: {
15942 SDValue Src = Op.getOperand(1);
15943 SDValue PassThru = Op.getOperand(2);
15944 SDValue Mask = Op.getOperand(3);
15945 SDValue RoundingMode;
15946 // We allways add rounding mode to the Node.
15947 // If the rounding mode is not specified, we add the
15948 // "current direction" mode.
15949 if (Op.getNumOperands() == 4)
15951 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15953 RoundingMode = Op.getOperand(4);
15954 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15955 if (IntrWithRoundingModeOpcode != 0)
15956 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15957 X86::STATIC_ROUNDING::CUR_DIRECTION)
15958 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15959 dl, Op.getValueType(), Src, RoundingMode),
15960 Mask, PassThru, Subtarget, DAG);
15961 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15963 Mask, PassThru, Subtarget, DAG);
15965 case INTR_TYPE_1OP_MASK: {
15966 SDValue Src = Op.getOperand(1);
15967 SDValue PassThru = Op.getOperand(2);
15968 SDValue Mask = Op.getOperand(3);
15969 // We add rounding mode to the Node when
15970 // - RM Opcode is specified and
15971 // - RM is not "current direction".
15972 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15973 if (IntrWithRoundingModeOpcode != 0) {
15974 SDValue Rnd = Op.getOperand(4);
15975 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15976 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15977 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15978 dl, Op.getValueType(),
15980 Mask, PassThru, Subtarget, DAG);
15983 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15984 Mask, PassThru, Subtarget, DAG);
15986 case INTR_TYPE_SCALAR_MASK: {
15987 SDValue Src1 = Op.getOperand(1);
15988 SDValue Src2 = Op.getOperand(2);
15989 SDValue passThru = Op.getOperand(3);
15990 SDValue Mask = Op.getOperand(4);
15991 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
15992 Mask, passThru, Subtarget, DAG);
15994 case INTR_TYPE_SCALAR_MASK_RM: {
15995 SDValue Src1 = Op.getOperand(1);
15996 SDValue Src2 = Op.getOperand(2);
15997 SDValue Src0 = Op.getOperand(3);
15998 SDValue Mask = Op.getOperand(4);
15999 // There are 2 kinds of intrinsics in this group:
16000 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16001 // (2) With rounding mode and sae - 7 operands.
16002 if (Op.getNumOperands() == 6) {
16003 SDValue Sae = Op.getOperand(5);
16004 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16005 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16007 Mask, Src0, Subtarget, DAG);
16009 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16010 SDValue RoundingMode = Op.getOperand(5);
16011 SDValue Sae = Op.getOperand(6);
16012 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16013 RoundingMode, Sae),
16014 Mask, Src0, Subtarget, DAG);
16016 case INTR_TYPE_2OP_MASK: {
16017 SDValue Src1 = Op.getOperand(1);
16018 SDValue Src2 = Op.getOperand(2);
16019 SDValue PassThru = Op.getOperand(3);
16020 SDValue Mask = Op.getOperand(4);
16021 // We specify 2 possible opcodes for intrinsics with rounding modes.
16022 // First, we check if the intrinsic may have non-default rounding mode,
16023 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16024 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16025 if (IntrWithRoundingModeOpcode != 0) {
16026 SDValue Rnd = Op.getOperand(5);
16027 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16028 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16029 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16030 dl, Op.getValueType(),
16032 Mask, PassThru, Subtarget, DAG);
16035 // TODO: Intrinsics should have fast-math-flags to propagate.
16036 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16037 Mask, PassThru, Subtarget, DAG);
16039 case INTR_TYPE_2OP_MASK_RM: {
16040 SDValue Src1 = Op.getOperand(1);
16041 SDValue Src2 = Op.getOperand(2);
16042 SDValue PassThru = Op.getOperand(3);
16043 SDValue Mask = Op.getOperand(4);
16044 // We specify 2 possible modes for intrinsics, with/without rounding
16046 // First, we check if the intrinsic have rounding mode (6 operands),
16047 // if not, we set rounding mode to "current".
16049 if (Op.getNumOperands() == 6)
16050 Rnd = Op.getOperand(5);
16052 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16053 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16055 Mask, PassThru, Subtarget, DAG);
16057 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16058 SDValue Src1 = Op.getOperand(1);
16059 SDValue Src2 = Op.getOperand(2);
16060 SDValue Src3 = Op.getOperand(3);
16061 SDValue PassThru = Op.getOperand(4);
16062 SDValue Mask = Op.getOperand(5);
16063 SDValue Sae = Op.getOperand(6);
16065 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16067 Mask, PassThru, Subtarget, DAG);
16069 case INTR_TYPE_3OP_MASK_RM: {
16070 SDValue Src1 = Op.getOperand(1);
16071 SDValue Src2 = Op.getOperand(2);
16072 SDValue Imm = Op.getOperand(3);
16073 SDValue PassThru = Op.getOperand(4);
16074 SDValue Mask = Op.getOperand(5);
16075 // We specify 2 possible modes for intrinsics, with/without rounding
16077 // First, we check if the intrinsic have rounding mode (7 operands),
16078 // if not, we set rounding mode to "current".
16080 if (Op.getNumOperands() == 7)
16081 Rnd = Op.getOperand(6);
16083 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16084 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16085 Src1, Src2, Imm, Rnd),
16086 Mask, PassThru, Subtarget, DAG);
16088 case INTR_TYPE_3OP_IMM8_MASK:
16089 case INTR_TYPE_3OP_MASK:
16090 case INSERT_SUBVEC: {
16091 SDValue Src1 = Op.getOperand(1);
16092 SDValue Src2 = Op.getOperand(2);
16093 SDValue Src3 = Op.getOperand(3);
16094 SDValue PassThru = Op.getOperand(4);
16095 SDValue Mask = Op.getOperand(5);
16097 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16098 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16099 else if (IntrData->Type == INSERT_SUBVEC) {
16100 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16101 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16102 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16103 Imm *= Src2.getValueType().getVectorNumElements();
16104 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16107 // We specify 2 possible opcodes for intrinsics with rounding modes.
16108 // First, we check if the intrinsic may have non-default rounding mode,
16109 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16110 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16111 if (IntrWithRoundingModeOpcode != 0) {
16112 SDValue Rnd = Op.getOperand(6);
16113 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16114 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16115 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16116 dl, Op.getValueType(),
16117 Src1, Src2, Src3, Rnd),
16118 Mask, PassThru, Subtarget, DAG);
16121 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16123 Mask, PassThru, Subtarget, DAG);
16125 case VPERM_3OP_MASKZ:
16126 case VPERM_3OP_MASK:
16129 case FMA_OP_MASK: {
16130 SDValue Src1 = Op.getOperand(1);
16131 SDValue Src2 = Op.getOperand(2);
16132 SDValue Src3 = Op.getOperand(3);
16133 SDValue Mask = Op.getOperand(4);
16134 EVT VT = Op.getValueType();
16135 SDValue PassThru = SDValue();
16137 // set PassThru element
16138 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16139 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16140 else if (IntrData->Type == FMA_OP_MASK3)
16145 // We specify 2 possible opcodes for intrinsics with rounding modes.
16146 // First, we check if the intrinsic may have non-default rounding mode,
16147 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16148 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16149 if (IntrWithRoundingModeOpcode != 0) {
16150 SDValue Rnd = Op.getOperand(5);
16151 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16152 X86::STATIC_ROUNDING::CUR_DIRECTION)
16153 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16154 dl, Op.getValueType(),
16155 Src1, Src2, Src3, Rnd),
16156 Mask, PassThru, Subtarget, DAG);
16158 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16159 dl, Op.getValueType(),
16161 Mask, PassThru, Subtarget, DAG);
16164 // FPclass intrinsics with mask
16165 SDValue Src1 = Op.getOperand(1);
16166 EVT VT = Src1.getValueType();
16167 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16168 VT.getVectorNumElements());
16169 SDValue Imm = Op.getOperand(2);
16170 SDValue Mask = Op.getOperand(3);
16171 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16172 Mask.getValueType().getSizeInBits());
16173 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16174 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16175 DAG.getTargetConstant(0, dl, MaskVT),
16177 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16178 DAG.getUNDEF(BitcastVT), FPclassMask,
16179 DAG.getIntPtrConstant(0, dl));
16180 return DAG.getBitcast(Op.getValueType(), Res);
16183 case CMP_MASK_CC: {
16184 // Comparison intrinsics with masks.
16185 // Example of transformation:
16186 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16187 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16189 // (v8i1 (insert_subvector undef,
16190 // (v2i1 (and (PCMPEQM %a, %b),
16191 // (extract_subvector
16192 // (v8i1 (bitcast %mask)), 0))), 0))))
16193 EVT VT = Op.getOperand(1).getValueType();
16194 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16195 VT.getVectorNumElements());
16196 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16197 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16198 Mask.getValueType().getSizeInBits());
16200 if (IntrData->Type == CMP_MASK_CC) {
16201 SDValue CC = Op.getOperand(3);
16202 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16203 // We specify 2 possible opcodes for intrinsics with rounding modes.
16204 // First, we check if the intrinsic may have non-default rounding mode,
16205 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16206 if (IntrData->Opc1 != 0) {
16207 SDValue Rnd = Op.getOperand(5);
16208 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16209 X86::STATIC_ROUNDING::CUR_DIRECTION)
16210 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16211 Op.getOperand(2), CC, Rnd);
16213 //default rounding mode
16215 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16216 Op.getOperand(2), CC);
16219 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16220 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16223 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16224 DAG.getTargetConstant(0, dl,
16227 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16228 DAG.getUNDEF(BitcastVT), CmpMask,
16229 DAG.getIntPtrConstant(0, dl));
16230 return DAG.getBitcast(Op.getValueType(), Res);
16232 case CMP_MASK_SCALAR_CC: {
16233 SDValue Src1 = Op.getOperand(1);
16234 SDValue Src2 = Op.getOperand(2);
16235 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16236 SDValue Mask = Op.getOperand(4);
16239 if (IntrData->Opc1 != 0) {
16240 SDValue Rnd = Op.getOperand(5);
16241 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16242 X86::STATIC_ROUNDING::CUR_DIRECTION)
16243 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16245 //default rounding mode
16247 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16249 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16250 DAG.getTargetConstant(0, dl,
16254 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16255 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16256 DAG.getValueType(MVT::i1));
16258 case COMI: { // Comparison intrinsics
16259 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16260 SDValue LHS = Op.getOperand(1);
16261 SDValue RHS = Op.getOperand(2);
16262 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16263 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16264 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16265 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16266 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16267 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16270 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16271 Op.getOperand(1), Op.getOperand(2), DAG);
16273 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16274 Op.getSimpleValueType(),
16276 Op.getOperand(2), DAG),
16277 Op.getOperand(4), Op.getOperand(3), Subtarget,
16279 case COMPRESS_EXPAND_IN_REG: {
16280 SDValue Mask = Op.getOperand(3);
16281 SDValue DataToCompress = Op.getOperand(1);
16282 SDValue PassThru = Op.getOperand(2);
16283 if (isAllOnes(Mask)) // return data as is
16284 return Op.getOperand(1);
16286 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16288 Mask, PassThru, Subtarget, DAG);
16291 SDValue Mask = Op.getOperand(3);
16292 EVT VT = Op.getValueType();
16293 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16294 VT.getVectorNumElements());
16295 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16296 Mask.getValueType().getSizeInBits());
16298 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16299 DAG.getBitcast(BitcastVT, Mask),
16300 DAG.getIntPtrConstant(0, dl));
16301 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16310 default: return SDValue(); // Don't custom lower most intrinsics.
16312 case Intrinsic::x86_avx2_permd:
16313 case Intrinsic::x86_avx2_permps:
16314 // Operands intentionally swapped. Mask is last operand to intrinsic,
16315 // but second operand for node/instruction.
16316 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16317 Op.getOperand(2), Op.getOperand(1));
16319 // ptest and testp intrinsics. The intrinsic these come from are designed to
16320 // return an integer value, not just an instruction so lower it to the ptest
16321 // or testp pattern and a setcc for the result.
16322 case Intrinsic::x86_sse41_ptestz:
16323 case Intrinsic::x86_sse41_ptestc:
16324 case Intrinsic::x86_sse41_ptestnzc:
16325 case Intrinsic::x86_avx_ptestz_256:
16326 case Intrinsic::x86_avx_ptestc_256:
16327 case Intrinsic::x86_avx_ptestnzc_256:
16328 case Intrinsic::x86_avx_vtestz_ps:
16329 case Intrinsic::x86_avx_vtestc_ps:
16330 case Intrinsic::x86_avx_vtestnzc_ps:
16331 case Intrinsic::x86_avx_vtestz_pd:
16332 case Intrinsic::x86_avx_vtestc_pd:
16333 case Intrinsic::x86_avx_vtestnzc_pd:
16334 case Intrinsic::x86_avx_vtestz_ps_256:
16335 case Intrinsic::x86_avx_vtestc_ps_256:
16336 case Intrinsic::x86_avx_vtestnzc_ps_256:
16337 case Intrinsic::x86_avx_vtestz_pd_256:
16338 case Intrinsic::x86_avx_vtestc_pd_256:
16339 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16340 bool IsTestPacked = false;
16343 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16344 case Intrinsic::x86_avx_vtestz_ps:
16345 case Intrinsic::x86_avx_vtestz_pd:
16346 case Intrinsic::x86_avx_vtestz_ps_256:
16347 case Intrinsic::x86_avx_vtestz_pd_256:
16348 IsTestPacked = true; // Fallthrough
16349 case Intrinsic::x86_sse41_ptestz:
16350 case Intrinsic::x86_avx_ptestz_256:
16352 X86CC = X86::COND_E;
16354 case Intrinsic::x86_avx_vtestc_ps:
16355 case Intrinsic::x86_avx_vtestc_pd:
16356 case Intrinsic::x86_avx_vtestc_ps_256:
16357 case Intrinsic::x86_avx_vtestc_pd_256:
16358 IsTestPacked = true; // Fallthrough
16359 case Intrinsic::x86_sse41_ptestc:
16360 case Intrinsic::x86_avx_ptestc_256:
16362 X86CC = X86::COND_B;
16364 case Intrinsic::x86_avx_vtestnzc_ps:
16365 case Intrinsic::x86_avx_vtestnzc_pd:
16366 case Intrinsic::x86_avx_vtestnzc_ps_256:
16367 case Intrinsic::x86_avx_vtestnzc_pd_256:
16368 IsTestPacked = true; // Fallthrough
16369 case Intrinsic::x86_sse41_ptestnzc:
16370 case Intrinsic::x86_avx_ptestnzc_256:
16372 X86CC = X86::COND_A;
16376 SDValue LHS = Op.getOperand(1);
16377 SDValue RHS = Op.getOperand(2);
16378 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16379 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16380 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16381 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16382 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16384 case Intrinsic::x86_avx512_kortestz_w:
16385 case Intrinsic::x86_avx512_kortestc_w: {
16386 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16387 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16388 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16389 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16390 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16391 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16392 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16395 case Intrinsic::x86_sse42_pcmpistria128:
16396 case Intrinsic::x86_sse42_pcmpestria128:
16397 case Intrinsic::x86_sse42_pcmpistric128:
16398 case Intrinsic::x86_sse42_pcmpestric128:
16399 case Intrinsic::x86_sse42_pcmpistrio128:
16400 case Intrinsic::x86_sse42_pcmpestrio128:
16401 case Intrinsic::x86_sse42_pcmpistris128:
16402 case Intrinsic::x86_sse42_pcmpestris128:
16403 case Intrinsic::x86_sse42_pcmpistriz128:
16404 case Intrinsic::x86_sse42_pcmpestriz128: {
16408 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16409 case Intrinsic::x86_sse42_pcmpistria128:
16410 Opcode = X86ISD::PCMPISTRI;
16411 X86CC = X86::COND_A;
16413 case Intrinsic::x86_sse42_pcmpestria128:
16414 Opcode = X86ISD::PCMPESTRI;
16415 X86CC = X86::COND_A;
16417 case Intrinsic::x86_sse42_pcmpistric128:
16418 Opcode = X86ISD::PCMPISTRI;
16419 X86CC = X86::COND_B;
16421 case Intrinsic::x86_sse42_pcmpestric128:
16422 Opcode = X86ISD::PCMPESTRI;
16423 X86CC = X86::COND_B;
16425 case Intrinsic::x86_sse42_pcmpistrio128:
16426 Opcode = X86ISD::PCMPISTRI;
16427 X86CC = X86::COND_O;
16429 case Intrinsic::x86_sse42_pcmpestrio128:
16430 Opcode = X86ISD::PCMPESTRI;
16431 X86CC = X86::COND_O;
16433 case Intrinsic::x86_sse42_pcmpistris128:
16434 Opcode = X86ISD::PCMPISTRI;
16435 X86CC = X86::COND_S;
16437 case Intrinsic::x86_sse42_pcmpestris128:
16438 Opcode = X86ISD::PCMPESTRI;
16439 X86CC = X86::COND_S;
16441 case Intrinsic::x86_sse42_pcmpistriz128:
16442 Opcode = X86ISD::PCMPISTRI;
16443 X86CC = X86::COND_E;
16445 case Intrinsic::x86_sse42_pcmpestriz128:
16446 Opcode = X86ISD::PCMPESTRI;
16447 X86CC = X86::COND_E;
16450 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16451 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16452 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16453 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16454 DAG.getConstant(X86CC, dl, MVT::i8),
16455 SDValue(PCMP.getNode(), 1));
16456 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16459 case Intrinsic::x86_sse42_pcmpistri128:
16460 case Intrinsic::x86_sse42_pcmpestri128: {
16462 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16463 Opcode = X86ISD::PCMPISTRI;
16465 Opcode = X86ISD::PCMPESTRI;
16467 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16468 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16469 return DAG.getNode(Opcode, dl, VTs, NewOps);
16472 case Intrinsic::x86_seh_lsda: {
16473 // Compute the symbol for the LSDA. We know it'll get emitted later.
16474 MachineFunction &MF = DAG.getMachineFunction();
16475 SDValue Op1 = Op.getOperand(1);
16476 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16477 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16478 GlobalValue::getRealLinkageName(Fn->getName()));
16480 // Generate a simple absolute symbol reference. This intrinsic is only
16481 // supported on 32-bit Windows, which isn't PIC.
16482 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16483 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16486 case Intrinsic::x86_seh_recoverfp: {
16487 SDValue FnOp = Op.getOperand(1);
16488 SDValue IncomingFPOp = Op.getOperand(2);
16489 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16490 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16492 report_fatal_error(
16493 "llvm.x86.seh.recoverfp must take a function as the first argument");
16494 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16497 case Intrinsic::localaddress: {
16498 // Returns one of the stack, base, or frame pointer registers, depending on
16499 // which is used to reference local variables.
16500 MachineFunction &MF = DAG.getMachineFunction();
16501 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16503 if (RegInfo->hasBasePointer(MF))
16504 Reg = RegInfo->getBaseRegister();
16505 else // This function handles the SP or FP case.
16506 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16507 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16512 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16513 SDValue Src, SDValue Mask, SDValue Base,
16514 SDValue Index, SDValue ScaleOp, SDValue Chain,
16515 const X86Subtarget * Subtarget) {
16517 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16519 llvm_unreachable("Invalid scale type");
16520 unsigned ScaleVal = C->getZExtValue();
16521 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16522 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16524 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16525 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16526 Index.getSimpleValueType().getVectorNumElements());
16528 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16530 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16532 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16533 Mask.getValueType().getSizeInBits());
16535 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16536 // are extracted by EXTRACT_SUBVECTOR.
16537 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16538 DAG.getBitcast(BitcastVT, Mask),
16539 DAG.getIntPtrConstant(0, dl));
16541 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16542 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16543 SDValue Segment = DAG.getRegister(0, MVT::i32);
16544 if (Src.getOpcode() == ISD::UNDEF)
16545 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16546 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16547 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16548 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16549 return DAG.getMergeValues(RetOps, dl);
16552 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16553 SDValue Src, SDValue Mask, SDValue Base,
16554 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16556 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16558 llvm_unreachable("Invalid scale type");
16559 unsigned ScaleVal = C->getZExtValue();
16560 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16561 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16563 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16564 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16565 SDValue Segment = DAG.getRegister(0, MVT::i32);
16566 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16567 Index.getSimpleValueType().getVectorNumElements());
16569 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16571 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16573 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16574 Mask.getValueType().getSizeInBits());
16576 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16577 // are extracted by EXTRACT_SUBVECTOR.
16578 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16579 DAG.getBitcast(BitcastVT, Mask),
16580 DAG.getIntPtrConstant(0, dl));
16582 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16583 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16584 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16585 return SDValue(Res, 1);
16588 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16589 SDValue Mask, SDValue Base, SDValue Index,
16590 SDValue ScaleOp, SDValue Chain) {
16592 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16593 assert(C && "Invalid scale type");
16594 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16595 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16596 SDValue Segment = DAG.getRegister(0, MVT::i32);
16598 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16600 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16602 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16604 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16605 //SDVTList VTs = DAG.getVTList(MVT::Other);
16606 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16607 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16608 return SDValue(Res, 0);
16611 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16612 // read performance monitor counters (x86_rdpmc).
16613 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16614 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16615 SmallVectorImpl<SDValue> &Results) {
16616 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16617 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16620 // The ECX register is used to select the index of the performance counter
16622 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16624 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16626 // Reads the content of a 64-bit performance counter and returns it in the
16627 // registers EDX:EAX.
16628 if (Subtarget->is64Bit()) {
16629 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16630 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16633 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16634 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16637 Chain = HI.getValue(1);
16639 if (Subtarget->is64Bit()) {
16640 // The EAX register is loaded with the low-order 32 bits. The EDX register
16641 // is loaded with the supported high-order bits of the counter.
16642 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16643 DAG.getConstant(32, DL, MVT::i8));
16644 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16645 Results.push_back(Chain);
16649 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16650 SDValue Ops[] = { LO, HI };
16651 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16652 Results.push_back(Pair);
16653 Results.push_back(Chain);
16656 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16657 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16658 // also used to custom lower READCYCLECOUNTER nodes.
16659 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16660 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16661 SmallVectorImpl<SDValue> &Results) {
16662 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16663 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16666 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16667 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16668 // and the EAX register is loaded with the low-order 32 bits.
16669 if (Subtarget->is64Bit()) {
16670 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16671 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16674 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16675 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16678 SDValue Chain = HI.getValue(1);
16680 if (Opcode == X86ISD::RDTSCP_DAG) {
16681 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16683 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16684 // the ECX register. Add 'ecx' explicitly to the chain.
16685 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16687 // Explicitly store the content of ECX at the location passed in input
16688 // to the 'rdtscp' intrinsic.
16689 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16690 MachinePointerInfo(), false, false, 0);
16693 if (Subtarget->is64Bit()) {
16694 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16695 // the EAX register is loaded with the low-order 32 bits.
16696 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16697 DAG.getConstant(32, DL, MVT::i8));
16698 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16699 Results.push_back(Chain);
16703 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16704 SDValue Ops[] = { LO, HI };
16705 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16706 Results.push_back(Pair);
16707 Results.push_back(Chain);
16710 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16711 SelectionDAG &DAG) {
16712 SmallVector<SDValue, 2> Results;
16714 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16716 return DAG.getMergeValues(Results, DL);
16719 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16720 SelectionDAG &DAG) {
16721 MachineFunction &MF = DAG.getMachineFunction();
16722 const Function *Fn = MF.getFunction();
16724 SDValue Chain = Op.getOperand(0);
16726 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16727 "using llvm.x86.seh.restoreframe requires a frame pointer");
16729 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16730 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16732 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16733 unsigned FrameReg =
16734 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16735 unsigned SPReg = RegInfo->getStackRegister();
16736 unsigned SlotSize = RegInfo->getSlotSize();
16738 // Get incoming EBP.
16739 SDValue IncomingEBP =
16740 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16742 // SP is saved in the first field of every registration node, so load
16743 // [EBP-RegNodeSize] into SP.
16744 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16745 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16746 DAG.getConstant(-RegNodeSize, dl, VT));
16748 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16749 false, VT.getScalarSizeInBits() / 8);
16750 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16752 if (!RegInfo->needsStackRealignment(MF)) {
16753 // Adjust EBP to point back to the original frame position.
16754 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16755 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16757 assert(RegInfo->hasBasePointer(MF) &&
16758 "functions with Win32 EH must use frame or base pointer register");
16760 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16761 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16762 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16764 // Reload the spilled EBP value, now that the stack and base pointers are
16766 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16767 X86FI->setHasSEHFramePtrSave(true);
16768 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16769 X86FI->setSEHFramePtrSaveIndex(FI);
16770 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16771 MachinePointerInfo(), false, false, false,
16772 VT.getScalarSizeInBits() / 8);
16773 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16779 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16780 /// return truncate Store/MaskedStore Node
16781 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16785 SDValue Mask = Op.getOperand(4);
16786 SDValue DataToTruncate = Op.getOperand(3);
16787 SDValue Addr = Op.getOperand(2);
16788 SDValue Chain = Op.getOperand(0);
16790 EVT VT = DataToTruncate.getValueType();
16791 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16792 ElementType, VT.getVectorNumElements());
16794 if (isAllOnes(Mask)) // return just a truncate store
16795 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16796 MachinePointerInfo(), SVT, false, false,
16797 SVT.getScalarSizeInBits()/8);
16799 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16800 MVT::i1, VT.getVectorNumElements());
16801 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16802 Mask.getValueType().getSizeInBits());
16803 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16804 // are extracted by EXTRACT_SUBVECTOR.
16805 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16806 DAG.getBitcast(BitcastVT, Mask),
16807 DAG.getIntPtrConstant(0, dl));
16809 MachineMemOperand *MMO = DAG.getMachineFunction().
16810 getMachineMemOperand(MachinePointerInfo(),
16811 MachineMemOperand::MOStore, SVT.getStoreSize(),
16812 SVT.getScalarSizeInBits()/8);
16814 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16815 VMask, SVT, MMO, true);
16818 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16819 SelectionDAG &DAG) {
16820 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16822 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16824 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16825 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16830 switch(IntrData->Type) {
16832 llvm_unreachable("Unknown Intrinsic Type");
16836 // Emit the node with the right value type.
16837 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16838 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16840 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16841 // Otherwise return the value from Rand, which is always 0, casted to i32.
16842 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16843 DAG.getConstant(1, dl, Op->getValueType(1)),
16844 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16845 SDValue(Result.getNode(), 1) };
16846 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16847 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16850 // Return { result, isValid, chain }.
16851 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16852 SDValue(Result.getNode(), 2));
16855 //gather(v1, mask, index, base, scale);
16856 SDValue Chain = Op.getOperand(0);
16857 SDValue Src = Op.getOperand(2);
16858 SDValue Base = Op.getOperand(3);
16859 SDValue Index = Op.getOperand(4);
16860 SDValue Mask = Op.getOperand(5);
16861 SDValue Scale = Op.getOperand(6);
16862 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16866 //scatter(base, mask, index, v1, scale);
16867 SDValue Chain = Op.getOperand(0);
16868 SDValue Base = Op.getOperand(2);
16869 SDValue Mask = Op.getOperand(3);
16870 SDValue Index = Op.getOperand(4);
16871 SDValue Src = Op.getOperand(5);
16872 SDValue Scale = Op.getOperand(6);
16873 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16877 SDValue Hint = Op.getOperand(6);
16878 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16879 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16880 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16881 SDValue Chain = Op.getOperand(0);
16882 SDValue Mask = Op.getOperand(2);
16883 SDValue Index = Op.getOperand(3);
16884 SDValue Base = Op.getOperand(4);
16885 SDValue Scale = Op.getOperand(5);
16886 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16888 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16890 SmallVector<SDValue, 2> Results;
16891 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16893 return DAG.getMergeValues(Results, dl);
16895 // Read Performance Monitoring Counters.
16897 SmallVector<SDValue, 2> Results;
16898 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16899 return DAG.getMergeValues(Results, dl);
16901 // XTEST intrinsics.
16903 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16904 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16905 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16906 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16908 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16909 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16910 Ret, SDValue(InTrans.getNode(), 1));
16914 SmallVector<SDValue, 2> Results;
16915 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16916 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16917 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16918 DAG.getConstant(-1, dl, MVT::i8));
16919 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16920 Op.getOperand(4), GenCF.getValue(1));
16921 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16922 Op.getOperand(5), MachinePointerInfo(),
16924 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16925 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16927 Results.push_back(SetCC);
16928 Results.push_back(Store);
16929 return DAG.getMergeValues(Results, dl);
16931 case COMPRESS_TO_MEM: {
16933 SDValue Mask = Op.getOperand(4);
16934 SDValue DataToCompress = Op.getOperand(3);
16935 SDValue Addr = Op.getOperand(2);
16936 SDValue Chain = Op.getOperand(0);
16938 EVT VT = DataToCompress.getValueType();
16939 if (isAllOnes(Mask)) // return just a store
16940 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16941 MachinePointerInfo(), false, false,
16942 VT.getScalarSizeInBits()/8);
16944 SDValue Compressed =
16945 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16946 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16947 return DAG.getStore(Chain, dl, Compressed, Addr,
16948 MachinePointerInfo(), false, false,
16949 VT.getScalarSizeInBits()/8);
16951 case TRUNCATE_TO_MEM_VI8:
16952 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16953 case TRUNCATE_TO_MEM_VI16:
16954 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16955 case TRUNCATE_TO_MEM_VI32:
16956 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16957 case EXPAND_FROM_MEM: {
16959 SDValue Mask = Op.getOperand(4);
16960 SDValue PassThru = Op.getOperand(3);
16961 SDValue Addr = Op.getOperand(2);
16962 SDValue Chain = Op.getOperand(0);
16963 EVT VT = Op.getValueType();
16965 if (isAllOnes(Mask)) // return just a load
16966 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16967 false, VT.getScalarSizeInBits()/8);
16969 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16970 false, false, false,
16971 VT.getScalarSizeInBits()/8);
16973 SDValue Results[] = {
16974 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16975 Mask, PassThru, Subtarget, DAG), Chain};
16976 return DAG.getMergeValues(Results, dl);
16981 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16982 SelectionDAG &DAG) const {
16983 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16984 MFI->setReturnAddressIsTaken(true);
16986 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16989 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16991 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16994 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16995 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16996 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16997 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16998 DAG.getNode(ISD::ADD, dl, PtrVT,
16999 FrameAddr, Offset),
17000 MachinePointerInfo(), false, false, false, 0);
17003 // Just load the return address.
17004 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17005 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17006 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17009 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17010 MachineFunction &MF = DAG.getMachineFunction();
17011 MachineFrameInfo *MFI = MF.getFrameInfo();
17012 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17013 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17014 EVT VT = Op.getValueType();
17016 MFI->setFrameAddressIsTaken(true);
17018 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17019 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17020 // is not possible to crawl up the stack without looking at the unwind codes
17022 int FrameAddrIndex = FuncInfo->getFAIndex();
17023 if (!FrameAddrIndex) {
17024 // Set up a frame object for the return address.
17025 unsigned SlotSize = RegInfo->getSlotSize();
17026 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17027 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17028 FuncInfo->setFAIndex(FrameAddrIndex);
17030 return DAG.getFrameIndex(FrameAddrIndex, VT);
17033 unsigned FrameReg =
17034 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17035 SDLoc dl(Op); // FIXME probably not meaningful
17036 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17037 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17038 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17039 "Invalid Frame Register!");
17040 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17042 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17043 MachinePointerInfo(),
17044 false, false, false, 0);
17048 // FIXME? Maybe this could be a TableGen attribute on some registers and
17049 // this table could be generated automatically from RegInfo.
17050 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17051 SelectionDAG &DAG) const {
17052 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17053 const MachineFunction &MF = DAG.getMachineFunction();
17055 unsigned Reg = StringSwitch<unsigned>(RegName)
17056 .Case("esp", X86::ESP)
17057 .Case("rsp", X86::RSP)
17058 .Case("ebp", X86::EBP)
17059 .Case("rbp", X86::RBP)
17062 if (Reg == X86::EBP || Reg == X86::RBP) {
17063 if (!TFI.hasFP(MF))
17064 report_fatal_error("register " + StringRef(RegName) +
17065 " is allocatable: function has no frame pointer");
17068 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17069 unsigned FrameReg =
17070 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17071 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17072 "Invalid Frame Register!");
17080 report_fatal_error("Invalid register name global variable");
17083 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17084 SelectionDAG &DAG) const {
17085 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17086 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17089 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17090 SDValue Chain = Op.getOperand(0);
17091 SDValue Offset = Op.getOperand(1);
17092 SDValue Handler = Op.getOperand(2);
17095 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17096 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17097 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17098 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17099 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17100 "Invalid Frame Register!");
17101 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17102 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17104 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17105 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17107 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17108 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17110 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17112 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17113 DAG.getRegister(StoreAddrReg, PtrVT));
17116 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17117 SelectionDAG &DAG) const {
17119 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17120 DAG.getVTList(MVT::i32, MVT::Other),
17121 Op.getOperand(0), Op.getOperand(1));
17124 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17125 SelectionDAG &DAG) const {
17127 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17128 Op.getOperand(0), Op.getOperand(1));
17131 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17132 return Op.getOperand(0);
17135 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17136 SelectionDAG &DAG) const {
17137 SDValue Root = Op.getOperand(0);
17138 SDValue Trmp = Op.getOperand(1); // trampoline
17139 SDValue FPtr = Op.getOperand(2); // nested function
17140 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17143 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17144 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17146 if (Subtarget->is64Bit()) {
17147 SDValue OutChains[6];
17149 // Large code-model.
17150 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17151 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17153 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17154 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17156 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17158 // Load the pointer to the nested function into R11.
17159 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17160 SDValue Addr = Trmp;
17161 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17162 Addr, MachinePointerInfo(TrmpAddr),
17165 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17166 DAG.getConstant(2, dl, MVT::i64));
17167 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17168 MachinePointerInfo(TrmpAddr, 2),
17171 // Load the 'nest' parameter value into R10.
17172 // R10 is specified in X86CallingConv.td
17173 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17174 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17175 DAG.getConstant(10, dl, MVT::i64));
17176 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17177 Addr, MachinePointerInfo(TrmpAddr, 10),
17180 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17181 DAG.getConstant(12, dl, MVT::i64));
17182 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17183 MachinePointerInfo(TrmpAddr, 12),
17186 // Jump to the nested function.
17187 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17188 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17189 DAG.getConstant(20, dl, MVT::i64));
17190 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17191 Addr, MachinePointerInfo(TrmpAddr, 20),
17194 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17195 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17196 DAG.getConstant(22, dl, MVT::i64));
17197 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17198 Addr, MachinePointerInfo(TrmpAddr, 22),
17201 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17203 const Function *Func =
17204 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17205 CallingConv::ID CC = Func->getCallingConv();
17210 llvm_unreachable("Unsupported calling convention");
17211 case CallingConv::C:
17212 case CallingConv::X86_StdCall: {
17213 // Pass 'nest' parameter in ECX.
17214 // Must be kept in sync with X86CallingConv.td
17215 NestReg = X86::ECX;
17217 // Check that ECX wasn't needed by an 'inreg' parameter.
17218 FunctionType *FTy = Func->getFunctionType();
17219 const AttributeSet &Attrs = Func->getAttributes();
17221 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17222 unsigned InRegCount = 0;
17225 for (FunctionType::param_iterator I = FTy->param_begin(),
17226 E = FTy->param_end(); I != E; ++I, ++Idx)
17227 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17228 auto &DL = DAG.getDataLayout();
17229 // FIXME: should only count parameters that are lowered to integers.
17230 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17233 if (InRegCount > 2) {
17234 report_fatal_error("Nest register in use - reduce number of inreg"
17240 case CallingConv::X86_FastCall:
17241 case CallingConv::X86_ThisCall:
17242 case CallingConv::Fast:
17243 // Pass 'nest' parameter in EAX.
17244 // Must be kept in sync with X86CallingConv.td
17245 NestReg = X86::EAX;
17249 SDValue OutChains[4];
17250 SDValue Addr, Disp;
17252 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17253 DAG.getConstant(10, dl, MVT::i32));
17254 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17256 // This is storing the opcode for MOV32ri.
17257 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17258 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17259 OutChains[0] = DAG.getStore(Root, dl,
17260 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17261 Trmp, MachinePointerInfo(TrmpAddr),
17264 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17265 DAG.getConstant(1, dl, MVT::i32));
17266 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17267 MachinePointerInfo(TrmpAddr, 1),
17270 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17271 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17272 DAG.getConstant(5, dl, MVT::i32));
17273 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17274 Addr, MachinePointerInfo(TrmpAddr, 5),
17277 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17278 DAG.getConstant(6, dl, MVT::i32));
17279 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17280 MachinePointerInfo(TrmpAddr, 6),
17283 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17287 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17288 SelectionDAG &DAG) const {
17290 The rounding mode is in bits 11:10 of FPSR, and has the following
17292 00 Round to nearest
17297 FLT_ROUNDS, on the other hand, expects the following:
17304 To perform the conversion, we do:
17305 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17308 MachineFunction &MF = DAG.getMachineFunction();
17309 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17310 unsigned StackAlignment = TFI.getStackAlignment();
17311 MVT VT = Op.getSimpleValueType();
17314 // Save FP Control Word to stack slot
17315 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17316 SDValue StackSlot =
17317 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17319 MachineMemOperand *MMO =
17320 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17321 MachineMemOperand::MOStore, 2, 2);
17323 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17324 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17325 DAG.getVTList(MVT::Other),
17326 Ops, MVT::i16, MMO);
17328 // Load FP Control Word from stack slot
17329 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17330 MachinePointerInfo(), false, false, false, 0);
17332 // Transform as necessary
17334 DAG.getNode(ISD::SRL, DL, MVT::i16,
17335 DAG.getNode(ISD::AND, DL, MVT::i16,
17336 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17337 DAG.getConstant(11, DL, MVT::i8));
17339 DAG.getNode(ISD::SRL, DL, MVT::i16,
17340 DAG.getNode(ISD::AND, DL, MVT::i16,
17341 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17342 DAG.getConstant(9, DL, MVT::i8));
17345 DAG.getNode(ISD::AND, DL, MVT::i16,
17346 DAG.getNode(ISD::ADD, DL, MVT::i16,
17347 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17348 DAG.getConstant(1, DL, MVT::i16)),
17349 DAG.getConstant(3, DL, MVT::i16));
17351 return DAG.getNode((VT.getSizeInBits() < 16 ?
17352 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17355 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17356 MVT VT = Op.getSimpleValueType();
17358 unsigned NumBits = VT.getSizeInBits();
17361 Op = Op.getOperand(0);
17362 if (VT == MVT::i8) {
17363 // Zero extend to i32 since there is not an i8 bsr.
17365 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17368 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17369 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17370 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17372 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17375 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17376 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17379 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17381 // Finally xor with NumBits-1.
17382 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17383 DAG.getConstant(NumBits - 1, dl, OpVT));
17386 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17390 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17391 MVT VT = Op.getSimpleValueType();
17393 unsigned NumBits = VT.getSizeInBits();
17396 Op = Op.getOperand(0);
17397 if (VT == MVT::i8) {
17398 // Zero extend to i32 since there is not an i8 bsr.
17400 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17403 // Issue a bsr (scan bits in reverse).
17404 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17405 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17407 // And xor with NumBits-1.
17408 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17409 DAG.getConstant(NumBits - 1, dl, OpVT));
17412 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17416 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17417 MVT VT = Op.getSimpleValueType();
17418 unsigned NumBits = VT.getScalarSizeInBits();
17421 if (VT.isVector()) {
17422 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17424 SDValue N0 = Op.getOperand(0);
17425 SDValue Zero = DAG.getConstant(0, dl, VT);
17427 // lsb(x) = (x & -x)
17428 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17429 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17431 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17432 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17433 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17434 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17435 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17436 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17439 // cttz(x) = ctpop(lsb - 1)
17440 SDValue One = DAG.getConstant(1, dl, VT);
17441 return DAG.getNode(ISD::CTPOP, dl, VT,
17442 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17445 assert(Op.getOpcode() == ISD::CTTZ &&
17446 "Only scalar CTTZ requires custom lowering");
17448 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17449 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17450 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17452 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17455 DAG.getConstant(NumBits, dl, VT),
17456 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17459 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17462 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17463 // ones, and then concatenate the result back.
17464 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17465 MVT VT = Op.getSimpleValueType();
17467 assert(VT.is256BitVector() && VT.isInteger() &&
17468 "Unsupported value type for operation");
17470 unsigned NumElems = VT.getVectorNumElements();
17473 // Extract the LHS vectors
17474 SDValue LHS = Op.getOperand(0);
17475 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17476 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17478 // Extract the RHS vectors
17479 SDValue RHS = Op.getOperand(1);
17480 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17481 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17483 MVT EltVT = VT.getVectorElementType();
17484 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17486 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17487 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17488 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17491 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17492 if (Op.getValueType() == MVT::i1)
17493 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17494 Op.getOperand(0), Op.getOperand(1));
17495 assert(Op.getSimpleValueType().is256BitVector() &&
17496 Op.getSimpleValueType().isInteger() &&
17497 "Only handle AVX 256-bit vector integer operation");
17498 return Lower256IntArith(Op, DAG);
17501 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17502 if (Op.getValueType() == MVT::i1)
17503 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17504 Op.getOperand(0), Op.getOperand(1));
17505 assert(Op.getSimpleValueType().is256BitVector() &&
17506 Op.getSimpleValueType().isInteger() &&
17507 "Only handle AVX 256-bit vector integer operation");
17508 return Lower256IntArith(Op, DAG);
17511 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17512 assert(Op.getSimpleValueType().is256BitVector() &&
17513 Op.getSimpleValueType().isInteger() &&
17514 "Only handle AVX 256-bit vector integer operation");
17515 return Lower256IntArith(Op, DAG);
17518 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17519 SelectionDAG &DAG) {
17521 MVT VT = Op.getSimpleValueType();
17524 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17526 // Decompose 256-bit ops into smaller 128-bit ops.
17527 if (VT.is256BitVector() && !Subtarget->hasInt256())
17528 return Lower256IntArith(Op, DAG);
17530 SDValue A = Op.getOperand(0);
17531 SDValue B = Op.getOperand(1);
17533 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17534 // pairs, multiply and truncate.
17535 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17536 if (Subtarget->hasInt256()) {
17537 if (VT == MVT::v32i8) {
17538 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17539 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17540 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17541 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17542 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17543 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17544 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17545 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17546 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17547 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17550 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17551 return DAG.getNode(
17552 ISD::TRUNCATE, dl, VT,
17553 DAG.getNode(ISD::MUL, dl, ExVT,
17554 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17555 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17558 assert(VT == MVT::v16i8 &&
17559 "Pre-AVX2 support only supports v16i8 multiplication");
17560 MVT ExVT = MVT::v8i16;
17562 // Extract the lo parts and sign extend to i16
17564 if (Subtarget->hasSSE41()) {
17565 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17566 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17568 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17569 -1, 4, -1, 5, -1, 6, -1, 7};
17570 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17571 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17572 ALo = DAG.getBitcast(ExVT, ALo);
17573 BLo = DAG.getBitcast(ExVT, BLo);
17574 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17575 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17578 // Extract the hi parts and sign extend to i16
17580 if (Subtarget->hasSSE41()) {
17581 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17582 -1, -1, -1, -1, -1, -1, -1, -1};
17583 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17584 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17585 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17586 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17588 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17589 -1, 12, -1, 13, -1, 14, -1, 15};
17590 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17591 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17592 AHi = DAG.getBitcast(ExVT, AHi);
17593 BHi = DAG.getBitcast(ExVT, BHi);
17594 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17595 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17598 // Multiply, mask the lower 8bits of the lo/hi results and pack
17599 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17600 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17601 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17602 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17603 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17606 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17607 if (VT == MVT::v4i32) {
17608 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17609 "Should not custom lower when pmuldq is available!");
17611 // Extract the odd parts.
17612 static const int UnpackMask[] = { 1, -1, 3, -1 };
17613 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17614 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17616 // Multiply the even parts.
17617 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17618 // Now multiply odd parts.
17619 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17621 Evens = DAG.getBitcast(VT, Evens);
17622 Odds = DAG.getBitcast(VT, Odds);
17624 // Merge the two vectors back together with a shuffle. This expands into 2
17626 static const int ShufMask[] = { 0, 4, 2, 6 };
17627 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17630 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17631 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17633 // Ahi = psrlqi(a, 32);
17634 // Bhi = psrlqi(b, 32);
17636 // AloBlo = pmuludq(a, b);
17637 // AloBhi = pmuludq(a, Bhi);
17638 // AhiBlo = pmuludq(Ahi, b);
17640 // AloBhi = psllqi(AloBhi, 32);
17641 // AhiBlo = psllqi(AhiBlo, 32);
17642 // return AloBlo + AloBhi + AhiBlo;
17644 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17645 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17647 SDValue AhiBlo = Ahi;
17648 SDValue AloBhi = Bhi;
17649 // Bit cast to 32-bit vectors for MULUDQ
17650 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17651 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17652 A = DAG.getBitcast(MulVT, A);
17653 B = DAG.getBitcast(MulVT, B);
17654 Ahi = DAG.getBitcast(MulVT, Ahi);
17655 Bhi = DAG.getBitcast(MulVT, Bhi);
17657 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17658 // After shifting right const values the result may be all-zero.
17659 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17660 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17661 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17663 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17664 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17665 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17668 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17669 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17672 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17673 assert(Subtarget->isTargetWin64() && "Unexpected target");
17674 EVT VT = Op.getValueType();
17675 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17676 "Unexpected return type for lowering");
17680 switch (Op->getOpcode()) {
17681 default: llvm_unreachable("Unexpected request for libcall!");
17682 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17683 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17684 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17685 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17686 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17687 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17691 SDValue InChain = DAG.getEntryNode();
17693 TargetLowering::ArgListTy Args;
17694 TargetLowering::ArgListEntry Entry;
17695 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17696 EVT ArgVT = Op->getOperand(i).getValueType();
17697 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17698 "Unexpected argument type for lowering");
17699 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17700 Entry.Node = StackPtr;
17701 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17703 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17704 Entry.Ty = PointerType::get(ArgTy,0);
17705 Entry.isSExt = false;
17706 Entry.isZExt = false;
17707 Args.push_back(Entry);
17710 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17711 getPointerTy(DAG.getDataLayout()));
17713 TargetLowering::CallLoweringInfo CLI(DAG);
17714 CLI.setDebugLoc(dl).setChain(InChain)
17715 .setCallee(getLibcallCallingConv(LC),
17716 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17717 Callee, std::move(Args), 0)
17718 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17720 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17721 return DAG.getBitcast(VT, CallInfo.first);
17724 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17725 SelectionDAG &DAG) {
17726 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17727 EVT VT = Op0.getValueType();
17730 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17731 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17733 // PMULxD operations multiply each even value (starting at 0) of LHS with
17734 // the related value of RHS and produce a widen result.
17735 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17736 // => <2 x i64> <ae|cg>
17738 // In other word, to have all the results, we need to perform two PMULxD:
17739 // 1. one with the even values.
17740 // 2. one with the odd values.
17741 // To achieve #2, with need to place the odd values at an even position.
17743 // Place the odd value at an even position (basically, shift all values 1
17744 // step to the left):
17745 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17746 // <a|b|c|d> => <b|undef|d|undef>
17747 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17748 // <e|f|g|h> => <f|undef|h|undef>
17749 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17751 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17753 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17754 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17756 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17757 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17758 // => <2 x i64> <ae|cg>
17759 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17760 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17761 // => <2 x i64> <bf|dh>
17762 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17764 // Shuffle it back into the right order.
17765 SDValue Highs, Lows;
17766 if (VT == MVT::v8i32) {
17767 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17768 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17769 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17770 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17772 const int HighMask[] = {1, 5, 3, 7};
17773 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17774 const int LowMask[] = {0, 4, 2, 6};
17775 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17778 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17779 // unsigned multiply.
17780 if (IsSigned && !Subtarget->hasSSE41()) {
17781 SDValue ShAmt = DAG.getConstant(
17783 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17784 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17785 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17786 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17787 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17789 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17790 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17793 // The first result of MUL_LOHI is actually the low value, followed by the
17795 SDValue Ops[] = {Lows, Highs};
17796 return DAG.getMergeValues(Ops, dl);
17799 // Return true if the required (according to Opcode) shift-imm form is natively
17800 // supported by the Subtarget
17801 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17803 if (VT.getScalarSizeInBits() < 16)
17806 if (VT.is512BitVector() &&
17807 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17810 bool LShift = VT.is128BitVector() ||
17811 (VT.is256BitVector() && Subtarget->hasInt256());
17813 bool AShift = LShift && (Subtarget->hasVLX() ||
17814 (VT != MVT::v2i64 && VT != MVT::v4i64));
17815 return (Opcode == ISD::SRA) ? AShift : LShift;
17818 // The shift amount is a variable, but it is the same for all vector lanes.
17819 // These instructions are defined together with shift-immediate.
17821 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17823 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17826 // Return true if the required (according to Opcode) variable-shift form is
17827 // natively supported by the Subtarget
17828 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17831 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17834 // vXi16 supported only on AVX-512, BWI
17835 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17838 if (VT.is512BitVector() || Subtarget->hasVLX())
17841 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17842 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17843 return (Opcode == ISD::SRA) ? AShift : LShift;
17846 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17847 const X86Subtarget *Subtarget) {
17848 MVT VT = Op.getSimpleValueType();
17850 SDValue R = Op.getOperand(0);
17851 SDValue Amt = Op.getOperand(1);
17853 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17854 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17856 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17857 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17858 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17859 SDValue Ex = DAG.getBitcast(ExVT, R);
17861 if (ShiftAmt >= 32) {
17862 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17864 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17865 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17866 ShiftAmt - 32, DAG);
17867 if (VT == MVT::v2i64)
17868 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17869 if (VT == MVT::v4i64)
17870 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17871 {9, 1, 11, 3, 13, 5, 15, 7});
17873 // SRA upper i32, SHL whole i64 and select lower i32.
17874 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17877 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17878 Lower = DAG.getBitcast(ExVT, Lower);
17879 if (VT == MVT::v2i64)
17880 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17881 if (VT == MVT::v4i64)
17882 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17883 {8, 1, 10, 3, 12, 5, 14, 7});
17885 return DAG.getBitcast(VT, Ex);
17888 // Optimize shl/srl/sra with constant shift amount.
17889 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17890 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17891 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17893 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17894 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17896 // i64 SRA needs to be performed as partial shifts.
17897 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17898 Op.getOpcode() == ISD::SRA)
17899 return ArithmeticShiftRight64(ShiftAmt);
17901 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17902 unsigned NumElts = VT.getVectorNumElements();
17903 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17905 if (Op.getOpcode() == ISD::SHL) {
17906 // Simple i8 add case
17908 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17910 // Make a large shift.
17911 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17913 SHL = DAG.getBitcast(VT, SHL);
17914 // Zero out the rightmost bits.
17915 SmallVector<SDValue, 32> V(
17916 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17917 return DAG.getNode(ISD::AND, dl, VT, SHL,
17918 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17920 if (Op.getOpcode() == ISD::SRL) {
17921 // Make a large shift.
17922 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17924 SRL = DAG.getBitcast(VT, SRL);
17925 // Zero out the leftmost bits.
17926 SmallVector<SDValue, 32> V(
17927 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17928 return DAG.getNode(ISD::AND, dl, VT, SRL,
17929 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17931 if (Op.getOpcode() == ISD::SRA) {
17932 if (ShiftAmt == 7) {
17933 // ashr(R, 7) === cmp_slt(R, 0)
17934 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17935 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17938 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17939 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17940 SmallVector<SDValue, 32> V(NumElts,
17941 DAG.getConstant(128 >> ShiftAmt, dl,
17943 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17944 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17945 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17948 llvm_unreachable("Unknown shift opcode.");
17953 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17954 if (!Subtarget->is64Bit() &&
17955 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17957 // Peek through any splat that was introduced for i64 shift vectorization.
17958 int SplatIndex = -1;
17959 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17960 if (SVN->isSplat()) {
17961 SplatIndex = SVN->getSplatIndex();
17962 Amt = Amt.getOperand(0);
17963 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17964 "Splat shuffle referencing second operand");
17967 if (Amt.getOpcode() != ISD::BITCAST ||
17968 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17971 Amt = Amt.getOperand(0);
17972 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17973 VT.getVectorNumElements();
17974 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17975 uint64_t ShiftAmt = 0;
17976 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17977 for (unsigned i = 0; i != Ratio; ++i) {
17978 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17982 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17985 // Check remaining shift amounts (if not a splat).
17986 if (SplatIndex < 0) {
17987 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17988 uint64_t ShAmt = 0;
17989 for (unsigned j = 0; j != Ratio; ++j) {
17990 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17994 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17996 if (ShAmt != ShiftAmt)
18001 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18002 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18004 if (Op.getOpcode() == ISD::SRA)
18005 return ArithmeticShiftRight64(ShiftAmt);
18011 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18012 const X86Subtarget* Subtarget) {
18013 MVT VT = Op.getSimpleValueType();
18015 SDValue R = Op.getOperand(0);
18016 SDValue Amt = Op.getOperand(1);
18018 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18019 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18021 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18022 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18024 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18026 EVT EltVT = VT.getVectorElementType();
18028 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18029 // Check if this build_vector node is doing a splat.
18030 // If so, then set BaseShAmt equal to the splat value.
18031 BaseShAmt = BV->getSplatValue();
18032 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18033 BaseShAmt = SDValue();
18035 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18036 Amt = Amt.getOperand(0);
18038 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18039 if (SVN && SVN->isSplat()) {
18040 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18041 SDValue InVec = Amt.getOperand(0);
18042 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18043 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18044 "Unexpected shuffle index found!");
18045 BaseShAmt = InVec.getOperand(SplatIdx);
18046 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18047 if (ConstantSDNode *C =
18048 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18049 if (C->getZExtValue() == SplatIdx)
18050 BaseShAmt = InVec.getOperand(1);
18055 // Avoid introducing an extract element from a shuffle.
18056 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18057 DAG.getIntPtrConstant(SplatIdx, dl));
18061 if (BaseShAmt.getNode()) {
18062 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18063 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18064 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18065 else if (EltVT.bitsLT(MVT::i32))
18066 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18068 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18072 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18073 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18074 Amt.getOpcode() == ISD::BITCAST &&
18075 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18076 Amt = Amt.getOperand(0);
18077 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18078 VT.getVectorNumElements();
18079 std::vector<SDValue> Vals(Ratio);
18080 for (unsigned i = 0; i != Ratio; ++i)
18081 Vals[i] = Amt.getOperand(i);
18082 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18083 for (unsigned j = 0; j != Ratio; ++j)
18084 if (Vals[j] != Amt.getOperand(i + j))
18088 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18089 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18094 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18095 SelectionDAG &DAG) {
18096 MVT VT = Op.getSimpleValueType();
18098 SDValue R = Op.getOperand(0);
18099 SDValue Amt = Op.getOperand(1);
18101 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18102 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18104 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18107 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18110 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18113 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18114 // shifts per-lane and then shuffle the partial results back together.
18115 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18116 // Splat the shift amounts so the scalar shifts above will catch it.
18117 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18118 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18119 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18120 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18121 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18124 // i64 vector arithmetic shift can be emulated with the transform:
18125 // M = lshr(SIGN_BIT, Amt)
18126 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18127 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18128 Op.getOpcode() == ISD::SRA) {
18129 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18130 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18131 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18132 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18133 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18137 // If possible, lower this packed shift into a vector multiply instead of
18138 // expanding it into a sequence of scalar shifts.
18139 // Do this only if the vector shift count is a constant build_vector.
18140 if (Op.getOpcode() == ISD::SHL &&
18141 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18142 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18143 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18144 SmallVector<SDValue, 8> Elts;
18145 EVT SVT = VT.getScalarType();
18146 unsigned SVTBits = SVT.getSizeInBits();
18147 const APInt &One = APInt(SVTBits, 1);
18148 unsigned NumElems = VT.getVectorNumElements();
18150 for (unsigned i=0; i !=NumElems; ++i) {
18151 SDValue Op = Amt->getOperand(i);
18152 if (Op->getOpcode() == ISD::UNDEF) {
18153 Elts.push_back(Op);
18157 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18158 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18159 uint64_t ShAmt = C.getZExtValue();
18160 if (ShAmt >= SVTBits) {
18161 Elts.push_back(DAG.getUNDEF(SVT));
18164 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18166 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18167 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18170 // Lower SHL with variable shift amount.
18171 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18172 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18174 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18175 DAG.getConstant(0x3f800000U, dl, VT));
18176 Op = DAG.getBitcast(MVT::v4f32, Op);
18177 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18178 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18181 // If possible, lower this shift as a sequence of two shifts by
18182 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18184 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18186 // Could be rewritten as:
18187 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18189 // The advantage is that the two shifts from the example would be
18190 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18191 // the vector shift into four scalar shifts plus four pairs of vector
18193 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18194 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18195 unsigned TargetOpcode = X86ISD::MOVSS;
18196 bool CanBeSimplified;
18197 // The splat value for the first packed shift (the 'X' from the example).
18198 SDValue Amt1 = Amt->getOperand(0);
18199 // The splat value for the second packed shift (the 'Y' from the example).
18200 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18201 Amt->getOperand(2);
18203 // See if it is possible to replace this node with a sequence of
18204 // two shifts followed by a MOVSS/MOVSD
18205 if (VT == MVT::v4i32) {
18206 // Check if it is legal to use a MOVSS.
18207 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18208 Amt2 == Amt->getOperand(3);
18209 if (!CanBeSimplified) {
18210 // Otherwise, check if we can still simplify this node using a MOVSD.
18211 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18212 Amt->getOperand(2) == Amt->getOperand(3);
18213 TargetOpcode = X86ISD::MOVSD;
18214 Amt2 = Amt->getOperand(2);
18217 // Do similar checks for the case where the machine value type
18219 CanBeSimplified = Amt1 == Amt->getOperand(1);
18220 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18221 CanBeSimplified = Amt2 == Amt->getOperand(i);
18223 if (!CanBeSimplified) {
18224 TargetOpcode = X86ISD::MOVSD;
18225 CanBeSimplified = true;
18226 Amt2 = Amt->getOperand(4);
18227 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18228 CanBeSimplified = Amt1 == Amt->getOperand(i);
18229 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18230 CanBeSimplified = Amt2 == Amt->getOperand(j);
18234 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18235 isa<ConstantSDNode>(Amt2)) {
18236 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18237 EVT CastVT = MVT::v4i32;
18239 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18240 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18242 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18243 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18244 if (TargetOpcode == X86ISD::MOVSD)
18245 CastVT = MVT::v2i64;
18246 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18247 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18248 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18250 return DAG.getBitcast(VT, Result);
18254 // v4i32 Non Uniform Shifts.
18255 // If the shift amount is constant we can shift each lane using the SSE2
18256 // immediate shifts, else we need to zero-extend each lane to the lower i64
18257 // and shift using the SSE2 variable shifts.
18258 // The separate results can then be blended together.
18259 if (VT == MVT::v4i32) {
18260 unsigned Opc = Op.getOpcode();
18261 SDValue Amt0, Amt1, Amt2, Amt3;
18262 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18263 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18264 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18265 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18266 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18268 // ISD::SHL is handled above but we include it here for completeness.
18271 llvm_unreachable("Unknown target vector shift node");
18273 Opc = X86ISD::VSHL;
18276 Opc = X86ISD::VSRL;
18279 Opc = X86ISD::VSRA;
18282 // The SSE2 shifts use the lower i64 as the same shift amount for
18283 // all lanes and the upper i64 is ignored. These shuffle masks
18284 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18285 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18286 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18287 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18288 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18289 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18292 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18293 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18294 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18295 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18296 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18297 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18298 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18301 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
18302 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18303 unsigned ShiftOpcode = Op->getOpcode();
18305 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18306 // On SSE41 targets we make use of the fact that VSELECT lowers
18307 // to PBLENDVB which selects bytes based just on the sign bit.
18308 if (Subtarget->hasSSE41()) {
18309 V0 = DAG.getBitcast(VT, V0);
18310 V1 = DAG.getBitcast(VT, V1);
18311 Sel = DAG.getBitcast(VT, Sel);
18312 return DAG.getBitcast(SelVT,
18313 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18315 // On pre-SSE41 targets we test for the sign bit by comparing to
18316 // zero - a negative value will set all bits of the lanes to true
18317 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18318 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18319 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18320 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18323 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18324 // We can safely do this using i16 shifts as we're only interested in
18325 // the 3 lower bits of each byte.
18326 Amt = DAG.getBitcast(ExtVT, Amt);
18327 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18328 Amt = DAG.getBitcast(VT, Amt);
18330 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18331 // r = VSELECT(r, shift(r, 4), a);
18333 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18334 R = SignBitSelect(VT, Amt, M, R);
18337 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18339 // r = VSELECT(r, shift(r, 2), a);
18340 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18341 R = SignBitSelect(VT, Amt, M, R);
18344 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18346 // return VSELECT(r, shift(r, 1), a);
18347 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18348 R = SignBitSelect(VT, Amt, M, R);
18352 if (Op->getOpcode() == ISD::SRA) {
18353 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18354 // so we can correctly sign extend. We don't care what happens to the
18356 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18357 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18358 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18359 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18360 ALo = DAG.getBitcast(ExtVT, ALo);
18361 AHi = DAG.getBitcast(ExtVT, AHi);
18362 RLo = DAG.getBitcast(ExtVT, RLo);
18363 RHi = DAG.getBitcast(ExtVT, RHi);
18365 // r = VSELECT(r, shift(r, 4), a);
18366 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18367 DAG.getConstant(4, dl, ExtVT));
18368 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18369 DAG.getConstant(4, dl, ExtVT));
18370 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18371 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18374 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18375 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18377 // r = VSELECT(r, shift(r, 2), a);
18378 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18379 DAG.getConstant(2, dl, ExtVT));
18380 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18381 DAG.getConstant(2, dl, ExtVT));
18382 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18383 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18386 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18387 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18389 // r = VSELECT(r, shift(r, 1), a);
18390 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18391 DAG.getConstant(1, dl, ExtVT));
18392 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18393 DAG.getConstant(1, dl, ExtVT));
18394 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18395 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18397 // Logical shift the result back to the lower byte, leaving a zero upper
18399 // meaning that we can safely pack with PACKUSWB.
18401 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18403 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18404 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18408 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18409 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18410 // solution better.
18411 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18412 MVT ExtVT = MVT::v8i32;
18414 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18415 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18416 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18417 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18418 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18421 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
18422 MVT ExtVT = MVT::v8i32;
18423 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18424 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18425 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18426 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18427 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18428 ALo = DAG.getBitcast(ExtVT, ALo);
18429 AHi = DAG.getBitcast(ExtVT, AHi);
18430 RLo = DAG.getBitcast(ExtVT, RLo);
18431 RHi = DAG.getBitcast(ExtVT, RHi);
18432 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18433 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18434 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18435 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18436 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18439 if (VT == MVT::v8i16) {
18440 unsigned ShiftOpcode = Op->getOpcode();
18442 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18443 // On SSE41 targets we make use of the fact that VSELECT lowers
18444 // to PBLENDVB which selects bytes based just on the sign bit.
18445 if (Subtarget->hasSSE41()) {
18446 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18447 V0 = DAG.getBitcast(ExtVT, V0);
18448 V1 = DAG.getBitcast(ExtVT, V1);
18449 Sel = DAG.getBitcast(ExtVT, Sel);
18450 return DAG.getBitcast(
18451 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18453 // On pre-SSE41 targets we splat the sign bit - a negative value will
18454 // set all bits of the lanes to true and VSELECT uses that in
18455 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18457 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18458 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18461 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18462 if (Subtarget->hasSSE41()) {
18463 // On SSE41 targets we need to replicate the shift mask in both
18464 // bytes for PBLENDVB.
18467 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18468 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18470 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18473 // r = VSELECT(r, shift(r, 8), a);
18474 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18475 R = SignBitSelect(Amt, M, R);
18478 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18480 // r = VSELECT(r, shift(r, 4), a);
18481 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18482 R = SignBitSelect(Amt, M, R);
18485 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18487 // r = VSELECT(r, shift(r, 2), a);
18488 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18489 R = SignBitSelect(Amt, M, R);
18492 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18494 // return VSELECT(r, shift(r, 1), a);
18495 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18496 R = SignBitSelect(Amt, M, R);
18500 // Decompose 256-bit shifts into smaller 128-bit shifts.
18501 if (VT.is256BitVector()) {
18502 unsigned NumElems = VT.getVectorNumElements();
18503 MVT EltVT = VT.getVectorElementType();
18504 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18506 // Extract the two vectors
18507 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18508 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18510 // Recreate the shift amount vectors
18511 SDValue Amt1, Amt2;
18512 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18513 // Constant shift amount
18514 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18515 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18516 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18518 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18519 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18521 // Variable shift amount
18522 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18523 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18526 // Issue new vector shifts for the smaller types
18527 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18528 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18530 // Concatenate the result back
18531 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18537 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18538 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18539 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18540 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18541 // has only one use.
18542 SDNode *N = Op.getNode();
18543 SDValue LHS = N->getOperand(0);
18544 SDValue RHS = N->getOperand(1);
18545 unsigned BaseOp = 0;
18548 switch (Op.getOpcode()) {
18549 default: llvm_unreachable("Unknown ovf instruction!");
18551 // A subtract of one will be selected as a INC. Note that INC doesn't
18552 // set CF, so we can't do this for UADDO.
18553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18555 BaseOp = X86ISD::INC;
18556 Cond = X86::COND_O;
18559 BaseOp = X86ISD::ADD;
18560 Cond = X86::COND_O;
18563 BaseOp = X86ISD::ADD;
18564 Cond = X86::COND_B;
18567 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18568 // set CF, so we can't do this for USUBO.
18569 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18571 BaseOp = X86ISD::DEC;
18572 Cond = X86::COND_O;
18575 BaseOp = X86ISD::SUB;
18576 Cond = X86::COND_O;
18579 BaseOp = X86ISD::SUB;
18580 Cond = X86::COND_B;
18583 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18584 Cond = X86::COND_O;
18586 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18587 if (N->getValueType(0) == MVT::i8) {
18588 BaseOp = X86ISD::UMUL8;
18589 Cond = X86::COND_O;
18592 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18594 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18597 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18598 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18599 SDValue(Sum.getNode(), 2));
18601 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18605 // Also sets EFLAGS.
18606 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18607 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18610 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18611 DAG.getConstant(Cond, DL, MVT::i32),
18612 SDValue(Sum.getNode(), 1));
18614 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18617 /// Returns true if the operand type is exactly twice the native width, and
18618 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18619 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18620 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18621 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18622 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18625 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18626 else if (OpWidth == 128)
18627 return Subtarget->hasCmpxchg16b();
18632 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18633 return needsCmpXchgNb(SI->getValueOperand()->getType());
18636 // Note: this turns large loads into lock cmpxchg8b/16b.
18637 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18638 TargetLowering::AtomicExpansionKind
18639 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18640 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18641 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18642 : AtomicExpansionKind::None;
18645 TargetLowering::AtomicExpansionKind
18646 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18647 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18648 Type *MemType = AI->getType();
18650 // If the operand is too big, we must see if cmpxchg8/16b is available
18651 // and default to library calls otherwise.
18652 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18653 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18654 : AtomicExpansionKind::None;
18657 AtomicRMWInst::BinOp Op = AI->getOperation();
18660 llvm_unreachable("Unknown atomic operation");
18661 case AtomicRMWInst::Xchg:
18662 case AtomicRMWInst::Add:
18663 case AtomicRMWInst::Sub:
18664 // It's better to use xadd, xsub or xchg for these in all cases.
18665 return AtomicExpansionKind::None;
18666 case AtomicRMWInst::Or:
18667 case AtomicRMWInst::And:
18668 case AtomicRMWInst::Xor:
18669 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18670 // prefix to a normal instruction for these operations.
18671 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18672 : AtomicExpansionKind::None;
18673 case AtomicRMWInst::Nand:
18674 case AtomicRMWInst::Max:
18675 case AtomicRMWInst::Min:
18676 case AtomicRMWInst::UMax:
18677 case AtomicRMWInst::UMin:
18678 // These always require a non-trivial set of data operations on x86. We must
18679 // use a cmpxchg loop.
18680 return AtomicExpansionKind::CmpXChg;
18684 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18685 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18686 // no-sse2). There isn't any reason to disable it if the target processor
18688 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18692 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18693 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18694 Type *MemType = AI->getType();
18695 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18696 // there is no benefit in turning such RMWs into loads, and it is actually
18697 // harmful as it introduces a mfence.
18698 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18701 auto Builder = IRBuilder<>(AI);
18702 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18703 auto SynchScope = AI->getSynchScope();
18704 // We must restrict the ordering to avoid generating loads with Release or
18705 // ReleaseAcquire orderings.
18706 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18707 auto Ptr = AI->getPointerOperand();
18709 // Before the load we need a fence. Here is an example lifted from
18710 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18713 // x.store(1, relaxed);
18714 // r1 = y.fetch_add(0, release);
18716 // y.fetch_add(42, acquire);
18717 // r2 = x.load(relaxed);
18718 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18719 // lowered to just a load without a fence. A mfence flushes the store buffer,
18720 // making the optimization clearly correct.
18721 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18722 // otherwise, we might be able to be more aggressive on relaxed idempotent
18723 // rmw. In practice, they do not look useful, so we don't try to be
18724 // especially clever.
18725 if (SynchScope == SingleThread)
18726 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18727 // the IR level, so we must wrap it in an intrinsic.
18730 if (!hasMFENCE(*Subtarget))
18731 // FIXME: it might make sense to use a locked operation here but on a
18732 // different cache-line to prevent cache-line bouncing. In practice it
18733 // is probably a small win, and x86 processors without mfence are rare
18734 // enough that we do not bother.
18738 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18739 Builder.CreateCall(MFence, {});
18741 // Finally we can emit the atomic load.
18742 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18743 AI->getType()->getPrimitiveSizeInBits());
18744 Loaded->setAtomic(Order, SynchScope);
18745 AI->replaceAllUsesWith(Loaded);
18746 AI->eraseFromParent();
18750 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18751 SelectionDAG &DAG) {
18753 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18754 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18755 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18756 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18758 // The only fence that needs an instruction is a sequentially-consistent
18759 // cross-thread fence.
18760 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18761 if (hasMFENCE(*Subtarget))
18762 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18764 SDValue Chain = Op.getOperand(0);
18765 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18767 DAG.getRegister(X86::ESP, MVT::i32), // Base
18768 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18769 DAG.getRegister(0, MVT::i32), // Index
18770 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18771 DAG.getRegister(0, MVT::i32), // Segment.
18775 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18776 return SDValue(Res, 0);
18779 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18780 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18783 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18784 SelectionDAG &DAG) {
18785 MVT T = Op.getSimpleValueType();
18789 switch(T.SimpleTy) {
18790 default: llvm_unreachable("Invalid value type!");
18791 case MVT::i8: Reg = X86::AL; size = 1; break;
18792 case MVT::i16: Reg = X86::AX; size = 2; break;
18793 case MVT::i32: Reg = X86::EAX; size = 4; break;
18795 assert(Subtarget->is64Bit() && "Node not type legal!");
18796 Reg = X86::RAX; size = 8;
18799 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18800 Op.getOperand(2), SDValue());
18801 SDValue Ops[] = { cpIn.getValue(0),
18804 DAG.getTargetConstant(size, DL, MVT::i8),
18805 cpIn.getValue(1) };
18806 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18807 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18808 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18812 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18813 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18814 MVT::i32, cpOut.getValue(2));
18815 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18816 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18819 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18820 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18821 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18825 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18826 SelectionDAG &DAG) {
18827 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18828 MVT DstVT = Op.getSimpleValueType();
18830 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18831 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18832 if (DstVT != MVT::f64)
18833 // This conversion needs to be expanded.
18836 SDValue InVec = Op->getOperand(0);
18838 unsigned NumElts = SrcVT.getVectorNumElements();
18839 EVT SVT = SrcVT.getVectorElementType();
18841 // Widen the vector in input in the case of MVT::v2i32.
18842 // Example: from MVT::v2i32 to MVT::v4i32.
18843 SmallVector<SDValue, 16> Elts;
18844 for (unsigned i = 0, e = NumElts; i != e; ++i)
18845 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18846 DAG.getIntPtrConstant(i, dl)));
18848 // Explicitly mark the extra elements as Undef.
18849 Elts.append(NumElts, DAG.getUNDEF(SVT));
18851 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18852 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18853 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18854 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18855 DAG.getIntPtrConstant(0, dl));
18858 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18859 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18860 assert((DstVT == MVT::i64 ||
18861 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18862 "Unexpected custom BITCAST");
18863 // i64 <=> MMX conversions are Legal.
18864 if (SrcVT==MVT::i64 && DstVT.isVector())
18866 if (DstVT==MVT::i64 && SrcVT.isVector())
18868 // MMX <=> MMX conversions are Legal.
18869 if (SrcVT.isVector() && DstVT.isVector())
18871 // All other conversions need to be expanded.
18875 /// Compute the horizontal sum of bytes in V for the elements of VT.
18877 /// Requires V to be a byte vector and VT to be an integer vector type with
18878 /// wider elements than V's type. The width of the elements of VT determines
18879 /// how many bytes of V are summed horizontally to produce each element of the
18881 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18882 const X86Subtarget *Subtarget,
18883 SelectionDAG &DAG) {
18885 MVT ByteVecVT = V.getSimpleValueType();
18886 MVT EltVT = VT.getVectorElementType();
18887 int NumElts = VT.getVectorNumElements();
18888 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18889 "Expected value to have byte element type.");
18890 assert(EltVT != MVT::i8 &&
18891 "Horizontal byte sum only makes sense for wider elements!");
18892 unsigned VecSize = VT.getSizeInBits();
18893 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18895 // PSADBW instruction horizontally add all bytes and leave the result in i64
18896 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18897 if (EltVT == MVT::i64) {
18898 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18899 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18900 return DAG.getBitcast(VT, V);
18903 if (EltVT == MVT::i32) {
18904 // We unpack the low half and high half into i32s interleaved with zeros so
18905 // that we can use PSADBW to horizontally sum them. The most useful part of
18906 // this is that it lines up the results of two PSADBW instructions to be
18907 // two v2i64 vectors which concatenated are the 4 population counts. We can
18908 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18909 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18910 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18911 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18913 // Do the horizontal sums into two v2i64s.
18914 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18915 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18916 DAG.getBitcast(ByteVecVT, Low), Zeros);
18917 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18918 DAG.getBitcast(ByteVecVT, High), Zeros);
18920 // Merge them together.
18921 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18922 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18923 DAG.getBitcast(ShortVecVT, Low),
18924 DAG.getBitcast(ShortVecVT, High));
18926 return DAG.getBitcast(VT, V);
18929 // The only element type left is i16.
18930 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18932 // To obtain pop count for each i16 element starting from the pop count for
18933 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18934 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18935 // directly supported.
18936 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18937 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18938 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18939 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18940 DAG.getBitcast(ByteVecVT, V));
18941 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18944 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18945 const X86Subtarget *Subtarget,
18946 SelectionDAG &DAG) {
18947 MVT VT = Op.getSimpleValueType();
18948 MVT EltVT = VT.getVectorElementType();
18949 unsigned VecSize = VT.getSizeInBits();
18951 // Implement a lookup table in register by using an algorithm based on:
18952 // http://wm.ite.pl/articles/sse-popcount.html
18954 // The general idea is that every lower byte nibble in the input vector is an
18955 // index into a in-register pre-computed pop count table. We then split up the
18956 // input vector in two new ones: (1) a vector with only the shifted-right
18957 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18958 // masked out higher ones) for each byte. PSHUB is used separately with both
18959 // to index the in-register table. Next, both are added and the result is a
18960 // i8 vector where each element contains the pop count for input byte.
18962 // To obtain the pop count for elements != i8, we follow up with the same
18963 // approach and use additional tricks as described below.
18965 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18966 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18967 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18968 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18970 int NumByteElts = VecSize / 8;
18971 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18972 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18973 SmallVector<SDValue, 16> LUTVec;
18974 for (int i = 0; i < NumByteElts; ++i)
18975 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18976 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18977 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18978 DAG.getConstant(0x0F, DL, MVT::i8));
18979 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18982 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18983 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18984 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18987 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18989 // The input vector is used as the shuffle mask that index elements into the
18990 // LUT. After counting low and high nibbles, add the vector to obtain the
18991 // final pop count per i8 element.
18992 SDValue HighPopCnt =
18993 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18994 SDValue LowPopCnt =
18995 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18996 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18998 if (EltVT == MVT::i8)
19001 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19004 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19005 const X86Subtarget *Subtarget,
19006 SelectionDAG &DAG) {
19007 MVT VT = Op.getSimpleValueType();
19008 assert(VT.is128BitVector() &&
19009 "Only 128-bit vector bitmath lowering supported.");
19011 int VecSize = VT.getSizeInBits();
19012 MVT EltVT = VT.getVectorElementType();
19013 int Len = EltVT.getSizeInBits();
19015 // This is the vectorized version of the "best" algorithm from
19016 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19017 // with a minor tweak to use a series of adds + shifts instead of vector
19018 // multiplications. Implemented for all integer vector types. We only use
19019 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19020 // much faster, even faster than using native popcnt instructions.
19022 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19023 MVT VT = V.getSimpleValueType();
19024 SmallVector<SDValue, 32> Shifters(
19025 VT.getVectorNumElements(),
19026 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19027 return DAG.getNode(OpCode, DL, VT, V,
19028 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19030 auto GetMask = [&](SDValue V, APInt Mask) {
19031 MVT VT = V.getSimpleValueType();
19032 SmallVector<SDValue, 32> Masks(
19033 VT.getVectorNumElements(),
19034 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19035 return DAG.getNode(ISD::AND, DL, VT, V,
19036 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19039 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19040 // x86, so set the SRL type to have elements at least i16 wide. This is
19041 // correct because all of our SRLs are followed immediately by a mask anyways
19042 // that handles any bits that sneak into the high bits of the byte elements.
19043 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19047 // v = v - ((v >> 1) & 0x55555555...)
19049 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19050 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19051 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19053 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19054 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19055 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19056 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19057 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19059 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19060 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19061 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19062 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19064 // At this point, V contains the byte-wise population count, and we are
19065 // merely doing a horizontal sum if necessary to get the wider element
19067 if (EltVT == MVT::i8)
19070 return LowerHorizontalByteSum(
19071 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19075 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19076 SelectionDAG &DAG) {
19077 MVT VT = Op.getSimpleValueType();
19078 // FIXME: Need to add AVX-512 support here!
19079 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19080 "Unknown CTPOP type to handle");
19081 SDLoc DL(Op.getNode());
19082 SDValue Op0 = Op.getOperand(0);
19084 if (!Subtarget->hasSSSE3()) {
19085 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19086 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19087 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19090 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19091 unsigned NumElems = VT.getVectorNumElements();
19093 // Extract each 128-bit vector, compute pop count and concat the result.
19094 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19095 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19097 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19098 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19099 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19102 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19105 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19106 SelectionDAG &DAG) {
19107 assert(Op.getValueType().isVector() &&
19108 "We only do custom lowering for vector population count.");
19109 return LowerVectorCTPOP(Op, Subtarget, DAG);
19112 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19113 SDNode *Node = Op.getNode();
19115 EVT T = Node->getValueType(0);
19116 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19117 DAG.getConstant(0, dl, T), Node->getOperand(2));
19118 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19119 cast<AtomicSDNode>(Node)->getMemoryVT(),
19120 Node->getOperand(0),
19121 Node->getOperand(1), negOp,
19122 cast<AtomicSDNode>(Node)->getMemOperand(),
19123 cast<AtomicSDNode>(Node)->getOrdering(),
19124 cast<AtomicSDNode>(Node)->getSynchScope());
19127 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19128 SDNode *Node = Op.getNode();
19130 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19132 // Convert seq_cst store -> xchg
19133 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19134 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19135 // (The only way to get a 16-byte store is cmpxchg16b)
19136 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19137 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19138 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19139 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19140 cast<AtomicSDNode>(Node)->getMemoryVT(),
19141 Node->getOperand(0),
19142 Node->getOperand(1), Node->getOperand(2),
19143 cast<AtomicSDNode>(Node)->getMemOperand(),
19144 cast<AtomicSDNode>(Node)->getOrdering(),
19145 cast<AtomicSDNode>(Node)->getSynchScope());
19146 return Swap.getValue(1);
19148 // Other atomic stores have a simple pattern.
19152 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19153 EVT VT = Op.getNode()->getSimpleValueType(0);
19155 // Let legalize expand this if it isn't a legal type yet.
19156 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19159 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19162 bool ExtraOp = false;
19163 switch (Op.getOpcode()) {
19164 default: llvm_unreachable("Invalid code");
19165 case ISD::ADDC: Opc = X86ISD::ADD; break;
19166 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19167 case ISD::SUBC: Opc = X86ISD::SUB; break;
19168 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19172 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19174 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19175 Op.getOperand(1), Op.getOperand(2));
19178 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19179 SelectionDAG &DAG) {
19180 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19182 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19183 // which returns the values as { float, float } (in XMM0) or
19184 // { double, double } (which is returned in XMM0, XMM1).
19186 SDValue Arg = Op.getOperand(0);
19187 EVT ArgVT = Arg.getValueType();
19188 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19190 TargetLowering::ArgListTy Args;
19191 TargetLowering::ArgListEntry Entry;
19195 Entry.isSExt = false;
19196 Entry.isZExt = false;
19197 Args.push_back(Entry);
19199 bool isF64 = ArgVT == MVT::f64;
19200 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19201 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19202 // the results are returned via SRet in memory.
19203 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19204 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19206 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19208 Type *RetTy = isF64
19209 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19210 : (Type*)VectorType::get(ArgTy, 4);
19212 TargetLowering::CallLoweringInfo CLI(DAG);
19213 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19214 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19216 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19219 // Returned in xmm0 and xmm1.
19220 return CallResult.first;
19222 // Returned in bits 0:31 and 32:64 xmm0.
19223 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19224 CallResult.first, DAG.getIntPtrConstant(0, dl));
19225 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19226 CallResult.first, DAG.getIntPtrConstant(1, dl));
19227 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19228 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19231 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19232 SelectionDAG &DAG) {
19233 assert(Subtarget->hasAVX512() &&
19234 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19236 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19237 EVT VT = N->getValue().getValueType();
19238 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19241 // X86 scatter kills mask register, so its type should be added to
19242 // the list of return values
19243 if (N->getNumValues() == 1) {
19244 SDValue Index = N->getIndex();
19245 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19246 !Index.getValueType().is512BitVector())
19247 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19249 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19250 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19251 N->getOperand(3), Index };
19253 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19254 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19255 return SDValue(NewScatter.getNode(), 0);
19260 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19261 SelectionDAG &DAG) {
19262 assert(Subtarget->hasAVX512() &&
19263 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19265 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19266 EVT VT = Op.getValueType();
19267 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19270 SDValue Index = N->getIndex();
19271 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19272 !Index.getValueType().is512BitVector()) {
19273 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19274 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19275 N->getOperand(3), Index };
19276 DAG.UpdateNodeOperands(N, Ops);
19281 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19282 SelectionDAG &DAG) const {
19283 // TODO: Eventually, the lowering of these nodes should be informed by or
19284 // deferred to the GC strategy for the function in which they appear. For
19285 // now, however, they must be lowered to something. Since they are logically
19286 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19287 // require special handling for these nodes), lower them as literal NOOPs for
19289 SmallVector<SDValue, 2> Ops;
19291 Ops.push_back(Op.getOperand(0));
19292 if (Op->getGluedNode())
19293 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19296 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19297 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19302 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19303 SelectionDAG &DAG) const {
19304 // TODO: Eventually, the lowering of these nodes should be informed by or
19305 // deferred to the GC strategy for the function in which they appear. For
19306 // now, however, they must be lowered to something. Since they are logically
19307 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19308 // require special handling for these nodes), lower them as literal NOOPs for
19310 SmallVector<SDValue, 2> Ops;
19312 Ops.push_back(Op.getOperand(0));
19313 if (Op->getGluedNode())
19314 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19317 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19318 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19323 /// LowerOperation - Provide custom lowering hooks for some operations.
19325 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19326 switch (Op.getOpcode()) {
19327 default: llvm_unreachable("Should not custom lower this!");
19328 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19329 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19330 return LowerCMP_SWAP(Op, Subtarget, DAG);
19331 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19332 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19333 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19334 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19335 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19336 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19337 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19338 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19339 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19340 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19341 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19342 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19343 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19344 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19345 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19346 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19347 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19348 case ISD::SHL_PARTS:
19349 case ISD::SRA_PARTS:
19350 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19351 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19352 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19353 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19354 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19355 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19356 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19357 case ISD::SIGN_EXTEND_VECTOR_INREG:
19358 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19359 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19360 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19361 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19362 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19364 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19365 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19366 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19367 case ISD::SETCC: return LowerSETCC(Op, DAG);
19368 case ISD::SELECT: return LowerSELECT(Op, DAG);
19369 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19370 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19371 case ISD::VASTART: return LowerVASTART(Op, DAG);
19372 case ISD::VAARG: return LowerVAARG(Op, DAG);
19373 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19374 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19375 case ISD::INTRINSIC_VOID:
19376 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19377 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19378 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19379 case ISD::FRAME_TO_ARGS_OFFSET:
19380 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19381 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19382 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19383 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19384 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19385 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19386 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19387 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19388 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19389 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19391 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19392 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19393 case ISD::UMUL_LOHI:
19394 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19397 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19403 case ISD::UMULO: return LowerXALUO(Op, DAG);
19404 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19405 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19409 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19410 case ISD::ADD: return LowerADD(Op, DAG);
19411 case ISD::SUB: return LowerSUB(Op, DAG);
19415 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19416 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19417 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19418 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19419 case ISD::GC_TRANSITION_START:
19420 return LowerGC_TRANSITION_START(Op, DAG);
19421 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19425 /// ReplaceNodeResults - Replace a node with an illegal result type
19426 /// with a new node built out of custom code.
19427 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19428 SmallVectorImpl<SDValue>&Results,
19429 SelectionDAG &DAG) const {
19431 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19432 switch (N->getOpcode()) {
19434 llvm_unreachable("Do not know how to custom type legalize this operation!");
19435 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19436 case X86ISD::FMINC:
19438 case X86ISD::FMAXC:
19439 case X86ISD::FMAX: {
19440 EVT VT = N->getValueType(0);
19441 if (VT != MVT::v2f32)
19442 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19443 SDValue UNDEF = DAG.getUNDEF(VT);
19444 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19445 N->getOperand(0), UNDEF);
19446 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19447 N->getOperand(1), UNDEF);
19448 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19451 case ISD::SIGN_EXTEND_INREG:
19456 // We don't want to expand or promote these.
19463 case ISD::UDIVREM: {
19464 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19465 Results.push_back(V);
19468 case ISD::FP_TO_SINT:
19469 case ISD::FP_TO_UINT: {
19470 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19472 std::pair<SDValue,SDValue> Vals =
19473 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19474 SDValue FIST = Vals.first, StackSlot = Vals.second;
19475 if (FIST.getNode()) {
19476 EVT VT = N->getValueType(0);
19477 // Return a load from the stack slot.
19478 if (StackSlot.getNode())
19479 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19480 MachinePointerInfo(),
19481 false, false, false, 0));
19483 Results.push_back(FIST);
19487 case ISD::UINT_TO_FP: {
19488 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19489 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19490 N->getValueType(0) != MVT::v2f32)
19492 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19494 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19496 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19497 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19498 DAG.getBitcast(MVT::v2i64, VBias));
19499 Or = DAG.getBitcast(MVT::v2f64, Or);
19500 // TODO: Are there any fast-math-flags to propagate here?
19501 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19502 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19505 case ISD::FP_ROUND: {
19506 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19508 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19509 Results.push_back(V);
19512 case ISD::FP_EXTEND: {
19513 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19514 // No other ValueType for FP_EXTEND should reach this point.
19515 assert(N->getValueType(0) == MVT::v2f32 &&
19516 "Do not know how to legalize this Node");
19519 case ISD::INTRINSIC_W_CHAIN: {
19520 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19522 default : llvm_unreachable("Do not know how to custom type "
19523 "legalize this intrinsic operation!");
19524 case Intrinsic::x86_rdtsc:
19525 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19527 case Intrinsic::x86_rdtscp:
19528 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19530 case Intrinsic::x86_rdpmc:
19531 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19534 case ISD::READCYCLECOUNTER: {
19535 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19538 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19539 EVT T = N->getValueType(0);
19540 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19541 bool Regs64bit = T == MVT::i128;
19542 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19543 SDValue cpInL, cpInH;
19544 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19545 DAG.getConstant(0, dl, HalfT));
19546 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19547 DAG.getConstant(1, dl, HalfT));
19548 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19549 Regs64bit ? X86::RAX : X86::EAX,
19551 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19552 Regs64bit ? X86::RDX : X86::EDX,
19553 cpInH, cpInL.getValue(1));
19554 SDValue swapInL, swapInH;
19555 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19556 DAG.getConstant(0, dl, HalfT));
19557 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19558 DAG.getConstant(1, dl, HalfT));
19559 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19560 Regs64bit ? X86::RBX : X86::EBX,
19561 swapInL, cpInH.getValue(1));
19562 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19563 Regs64bit ? X86::RCX : X86::ECX,
19564 swapInH, swapInL.getValue(1));
19565 SDValue Ops[] = { swapInH.getValue(0),
19567 swapInH.getValue(1) };
19568 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19569 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19570 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19571 X86ISD::LCMPXCHG8_DAG;
19572 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19573 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19574 Regs64bit ? X86::RAX : X86::EAX,
19575 HalfT, Result.getValue(1));
19576 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19577 Regs64bit ? X86::RDX : X86::EDX,
19578 HalfT, cpOutL.getValue(2));
19579 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19581 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19582 MVT::i32, cpOutH.getValue(2));
19584 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19585 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19586 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19588 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19589 Results.push_back(Success);
19590 Results.push_back(EFLAGS.getValue(1));
19593 case ISD::ATOMIC_SWAP:
19594 case ISD::ATOMIC_LOAD_ADD:
19595 case ISD::ATOMIC_LOAD_SUB:
19596 case ISD::ATOMIC_LOAD_AND:
19597 case ISD::ATOMIC_LOAD_OR:
19598 case ISD::ATOMIC_LOAD_XOR:
19599 case ISD::ATOMIC_LOAD_NAND:
19600 case ISD::ATOMIC_LOAD_MIN:
19601 case ISD::ATOMIC_LOAD_MAX:
19602 case ISD::ATOMIC_LOAD_UMIN:
19603 case ISD::ATOMIC_LOAD_UMAX:
19604 case ISD::ATOMIC_LOAD: {
19605 // Delegate to generic TypeLegalization. Situations we can really handle
19606 // should have already been dealt with by AtomicExpandPass.cpp.
19609 case ISD::BITCAST: {
19610 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19611 EVT DstVT = N->getValueType(0);
19612 EVT SrcVT = N->getOperand(0)->getValueType(0);
19614 if (SrcVT != MVT::f64 ||
19615 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19618 unsigned NumElts = DstVT.getVectorNumElements();
19619 EVT SVT = DstVT.getVectorElementType();
19620 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19621 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19622 MVT::v2f64, N->getOperand(0));
19623 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19625 if (ExperimentalVectorWideningLegalization) {
19626 // If we are legalizing vectors by widening, we already have the desired
19627 // legal vector type, just return it.
19628 Results.push_back(ToVecInt);
19632 SmallVector<SDValue, 8> Elts;
19633 for (unsigned i = 0, e = NumElts; i != e; ++i)
19634 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19635 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19637 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19642 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19643 switch ((X86ISD::NodeType)Opcode) {
19644 case X86ISD::FIRST_NUMBER: break;
19645 case X86ISD::BSF: return "X86ISD::BSF";
19646 case X86ISD::BSR: return "X86ISD::BSR";
19647 case X86ISD::SHLD: return "X86ISD::SHLD";
19648 case X86ISD::SHRD: return "X86ISD::SHRD";
19649 case X86ISD::FAND: return "X86ISD::FAND";
19650 case X86ISD::FANDN: return "X86ISD::FANDN";
19651 case X86ISD::FOR: return "X86ISD::FOR";
19652 case X86ISD::FXOR: return "X86ISD::FXOR";
19653 case X86ISD::FILD: return "X86ISD::FILD";
19654 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19655 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19656 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19657 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19658 case X86ISD::FLD: return "X86ISD::FLD";
19659 case X86ISD::FST: return "X86ISD::FST";
19660 case X86ISD::CALL: return "X86ISD::CALL";
19661 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19662 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19663 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19664 case X86ISD::BT: return "X86ISD::BT";
19665 case X86ISD::CMP: return "X86ISD::CMP";
19666 case X86ISD::COMI: return "X86ISD::COMI";
19667 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19668 case X86ISD::CMPM: return "X86ISD::CMPM";
19669 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19670 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19671 case X86ISD::SETCC: return "X86ISD::SETCC";
19672 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19673 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19674 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19675 case X86ISD::CMOV: return "X86ISD::CMOV";
19676 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19677 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19678 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19679 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19680 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19681 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19682 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19683 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19684 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19685 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19686 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19687 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19688 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19689 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19690 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19691 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19692 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19693 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19694 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19695 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19696 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19697 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19698 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19699 case X86ISD::HADD: return "X86ISD::HADD";
19700 case X86ISD::HSUB: return "X86ISD::HSUB";
19701 case X86ISD::FHADD: return "X86ISD::FHADD";
19702 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19703 case X86ISD::ABS: return "X86ISD::ABS";
19704 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19705 case X86ISD::FMAX: return "X86ISD::FMAX";
19706 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19707 case X86ISD::FMIN: return "X86ISD::FMIN";
19708 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19709 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19710 case X86ISD::FMINC: return "X86ISD::FMINC";
19711 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19712 case X86ISD::FRCP: return "X86ISD::FRCP";
19713 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19714 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19715 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19716 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19717 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19718 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19719 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19720 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19721 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19722 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19723 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19724 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19725 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19726 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19727 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19728 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19729 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19730 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19731 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19732 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19733 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19734 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19735 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19736 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19737 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19738 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19739 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19740 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19741 case X86ISD::VSHL: return "X86ISD::VSHL";
19742 case X86ISD::VSRL: return "X86ISD::VSRL";
19743 case X86ISD::VSRA: return "X86ISD::VSRA";
19744 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19745 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19746 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19747 case X86ISD::CMPP: return "X86ISD::CMPP";
19748 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19749 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19750 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19751 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19752 case X86ISD::ADD: return "X86ISD::ADD";
19753 case X86ISD::SUB: return "X86ISD::SUB";
19754 case X86ISD::ADC: return "X86ISD::ADC";
19755 case X86ISD::SBB: return "X86ISD::SBB";
19756 case X86ISD::SMUL: return "X86ISD::SMUL";
19757 case X86ISD::UMUL: return "X86ISD::UMUL";
19758 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19759 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19760 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19761 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19762 case X86ISD::INC: return "X86ISD::INC";
19763 case X86ISD::DEC: return "X86ISD::DEC";
19764 case X86ISD::OR: return "X86ISD::OR";
19765 case X86ISD::XOR: return "X86ISD::XOR";
19766 case X86ISD::AND: return "X86ISD::AND";
19767 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19768 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19769 case X86ISD::PTEST: return "X86ISD::PTEST";
19770 case X86ISD::TESTP: return "X86ISD::TESTP";
19771 case X86ISD::TESTM: return "X86ISD::TESTM";
19772 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19773 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19774 case X86ISD::KTEST: return "X86ISD::KTEST";
19775 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19776 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19777 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19778 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19779 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19780 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19781 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19782 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19783 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19784 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19785 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19786 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19787 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19788 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19789 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19790 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19791 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19792 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19793 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19794 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19795 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19796 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19797 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19798 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19799 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19800 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19801 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19802 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19803 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19804 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19805 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19806 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19807 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19808 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19809 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19810 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19811 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19812 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19813 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19814 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19815 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19816 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19817 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19818 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19819 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19820 case X86ISD::SAHF: return "X86ISD::SAHF";
19821 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19822 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19823 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19824 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19825 case X86ISD::FMADD: return "X86ISD::FMADD";
19826 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19827 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19828 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19829 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19830 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19831 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19832 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19833 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19834 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19835 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19836 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19837 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19838 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19839 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19840 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19841 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19842 case X86ISD::XTEST: return "X86ISD::XTEST";
19843 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19844 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19845 case X86ISD::SELECT: return "X86ISD::SELECT";
19846 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19847 case X86ISD::RCP28: return "X86ISD::RCP28";
19848 case X86ISD::EXP2: return "X86ISD::EXP2";
19849 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19850 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19851 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19852 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19853 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19854 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19855 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19856 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19857 case X86ISD::ADDS: return "X86ISD::ADDS";
19858 case X86ISD::SUBS: return "X86ISD::SUBS";
19859 case X86ISD::AVG: return "X86ISD::AVG";
19860 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19861 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19862 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19863 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19864 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19865 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
19870 // isLegalAddressingMode - Return true if the addressing mode represented
19871 // by AM is legal for this target, for a load/store of the specified type.
19872 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19873 const AddrMode &AM, Type *Ty,
19874 unsigned AS) const {
19875 // X86 supports extremely general addressing modes.
19876 CodeModel::Model M = getTargetMachine().getCodeModel();
19877 Reloc::Model R = getTargetMachine().getRelocationModel();
19879 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19880 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19885 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19887 // If a reference to this global requires an extra load, we can't fold it.
19888 if (isGlobalStubReference(GVFlags))
19891 // If BaseGV requires a register for the PIC base, we cannot also have a
19892 // BaseReg specified.
19893 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19896 // If lower 4G is not available, then we must use rip-relative addressing.
19897 if ((M != CodeModel::Small || R != Reloc::Static) &&
19898 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19902 switch (AM.Scale) {
19908 // These scales always work.
19913 // These scales are formed with basereg+scalereg. Only accept if there is
19918 default: // Other stuff never works.
19925 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19926 unsigned Bits = Ty->getScalarSizeInBits();
19928 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19929 // particularly cheaper than those without.
19933 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19934 // variable shifts just as cheap as scalar ones.
19935 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19938 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19939 // fully general vector.
19943 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19944 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19946 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19947 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19948 return NumBits1 > NumBits2;
19951 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19952 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19955 if (!isTypeLegal(EVT::getEVT(Ty1)))
19958 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19960 // Assuming the caller doesn't have a zeroext or signext return parameter,
19961 // truncation all the way down to i1 is valid.
19965 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19966 return isInt<32>(Imm);
19969 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19970 // Can also use sub to handle negated immediates.
19971 return isInt<32>(Imm);
19974 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19975 if (!VT1.isInteger() || !VT2.isInteger())
19977 unsigned NumBits1 = VT1.getSizeInBits();
19978 unsigned NumBits2 = VT2.getSizeInBits();
19979 return NumBits1 > NumBits2;
19982 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19983 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19984 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19987 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19988 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19989 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19992 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19993 EVT VT1 = Val.getValueType();
19994 if (isZExtFree(VT1, VT2))
19997 if (Val.getOpcode() != ISD::LOAD)
20000 if (!VT1.isSimple() || !VT1.isInteger() ||
20001 !VT2.isSimple() || !VT2.isInteger())
20004 switch (VT1.getSimpleVT().SimpleTy) {
20009 // X86 has 8, 16, and 32-bit zero-extending loads.
20016 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20019 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20020 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20023 VT = VT.getScalarType();
20025 if (!VT.isSimple())
20028 switch (VT.getSimpleVT().SimpleTy) {
20039 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20040 // i16 instructions are longer (0x66 prefix) and potentially slower.
20041 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20044 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20045 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20046 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20047 /// are assumed to be legal.
20049 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20051 if (!VT.isSimple())
20054 // Not for i1 vectors
20055 if (VT.getScalarType() == MVT::i1)
20058 // Very little shuffling can be done for 64-bit vectors right now.
20059 if (VT.getSizeInBits() == 64)
20062 // We only care that the types being shuffled are legal. The lowering can
20063 // handle any possible shuffle mask that results.
20064 return isTypeLegal(VT.getSimpleVT());
20068 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20070 // Just delegate to the generic legality, clear masks aren't special.
20071 return isShuffleMaskLegal(Mask, VT);
20074 //===----------------------------------------------------------------------===//
20075 // X86 Scheduler Hooks
20076 //===----------------------------------------------------------------------===//
20078 /// Utility function to emit xbegin specifying the start of an RTM region.
20079 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20080 const TargetInstrInfo *TII) {
20081 DebugLoc DL = MI->getDebugLoc();
20083 const BasicBlock *BB = MBB->getBasicBlock();
20084 MachineFunction::iterator I = MBB;
20087 // For the v = xbegin(), we generate
20098 MachineBasicBlock *thisMBB = MBB;
20099 MachineFunction *MF = MBB->getParent();
20100 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20101 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20102 MF->insert(I, mainMBB);
20103 MF->insert(I, sinkMBB);
20105 // Transfer the remainder of BB and its successor edges to sinkMBB.
20106 sinkMBB->splice(sinkMBB->begin(), MBB,
20107 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20108 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20112 // # fallthrough to mainMBB
20113 // # abortion to sinkMBB
20114 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20115 thisMBB->addSuccessor(mainMBB);
20116 thisMBB->addSuccessor(sinkMBB);
20120 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20121 mainMBB->addSuccessor(sinkMBB);
20124 // EAX is live into the sinkMBB
20125 sinkMBB->addLiveIn(X86::EAX);
20126 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20127 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20130 MI->eraseFromParent();
20134 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20135 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20136 // in the .td file.
20137 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20138 const TargetInstrInfo *TII) {
20140 switch (MI->getOpcode()) {
20141 default: llvm_unreachable("illegal opcode!");
20142 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20143 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20144 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20145 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20146 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20147 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20148 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20149 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20152 DebugLoc dl = MI->getDebugLoc();
20153 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20155 unsigned NumArgs = MI->getNumOperands();
20156 for (unsigned i = 1; i < NumArgs; ++i) {
20157 MachineOperand &Op = MI->getOperand(i);
20158 if (!(Op.isReg() && Op.isImplicit()))
20159 MIB.addOperand(Op);
20161 if (MI->hasOneMemOperand())
20162 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20164 BuildMI(*BB, MI, dl,
20165 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20166 .addReg(X86::XMM0);
20168 MI->eraseFromParent();
20172 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20173 // defs in an instruction pattern
20174 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20175 const TargetInstrInfo *TII) {
20177 switch (MI->getOpcode()) {
20178 default: llvm_unreachable("illegal opcode!");
20179 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20180 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20181 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20182 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20183 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20184 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20185 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20186 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20189 DebugLoc dl = MI->getDebugLoc();
20190 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20192 unsigned NumArgs = MI->getNumOperands(); // remove the results
20193 for (unsigned i = 1; i < NumArgs; ++i) {
20194 MachineOperand &Op = MI->getOperand(i);
20195 if (!(Op.isReg() && Op.isImplicit()))
20196 MIB.addOperand(Op);
20198 if (MI->hasOneMemOperand())
20199 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20201 BuildMI(*BB, MI, dl,
20202 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20205 MI->eraseFromParent();
20209 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20210 const X86Subtarget *Subtarget) {
20211 DebugLoc dl = MI->getDebugLoc();
20212 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20213 // Address into RAX/EAX, other two args into ECX, EDX.
20214 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20215 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20216 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20217 for (int i = 0; i < X86::AddrNumOperands; ++i)
20218 MIB.addOperand(MI->getOperand(i));
20220 unsigned ValOps = X86::AddrNumOperands;
20221 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20222 .addReg(MI->getOperand(ValOps).getReg());
20223 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20224 .addReg(MI->getOperand(ValOps+1).getReg());
20226 // The instruction doesn't actually take any operands though.
20227 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20229 MI->eraseFromParent(); // The pseudo is gone now.
20233 MachineBasicBlock *
20234 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20235 MachineBasicBlock *MBB) const {
20236 // Emit va_arg instruction on X86-64.
20238 // Operands to this pseudo-instruction:
20239 // 0 ) Output : destination address (reg)
20240 // 1-5) Input : va_list address (addr, i64mem)
20241 // 6 ) ArgSize : Size (in bytes) of vararg type
20242 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20243 // 8 ) Align : Alignment of type
20244 // 9 ) EFLAGS (implicit-def)
20246 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20247 static_assert(X86::AddrNumOperands == 5,
20248 "VAARG_64 assumes 5 address operands");
20250 unsigned DestReg = MI->getOperand(0).getReg();
20251 MachineOperand &Base = MI->getOperand(1);
20252 MachineOperand &Scale = MI->getOperand(2);
20253 MachineOperand &Index = MI->getOperand(3);
20254 MachineOperand &Disp = MI->getOperand(4);
20255 MachineOperand &Segment = MI->getOperand(5);
20256 unsigned ArgSize = MI->getOperand(6).getImm();
20257 unsigned ArgMode = MI->getOperand(7).getImm();
20258 unsigned Align = MI->getOperand(8).getImm();
20260 // Memory Reference
20261 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20262 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20263 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20265 // Machine Information
20266 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20267 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20268 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20269 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20270 DebugLoc DL = MI->getDebugLoc();
20272 // struct va_list {
20275 // i64 overflow_area (address)
20276 // i64 reg_save_area (address)
20278 // sizeof(va_list) = 24
20279 // alignment(va_list) = 8
20281 unsigned TotalNumIntRegs = 6;
20282 unsigned TotalNumXMMRegs = 8;
20283 bool UseGPOffset = (ArgMode == 1);
20284 bool UseFPOffset = (ArgMode == 2);
20285 unsigned MaxOffset = TotalNumIntRegs * 8 +
20286 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20288 /* Align ArgSize to a multiple of 8 */
20289 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20290 bool NeedsAlign = (Align > 8);
20292 MachineBasicBlock *thisMBB = MBB;
20293 MachineBasicBlock *overflowMBB;
20294 MachineBasicBlock *offsetMBB;
20295 MachineBasicBlock *endMBB;
20297 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20298 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20299 unsigned OffsetReg = 0;
20301 if (!UseGPOffset && !UseFPOffset) {
20302 // If we only pull from the overflow region, we don't create a branch.
20303 // We don't need to alter control flow.
20304 OffsetDestReg = 0; // unused
20305 OverflowDestReg = DestReg;
20307 offsetMBB = nullptr;
20308 overflowMBB = thisMBB;
20311 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20312 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20313 // If not, pull from overflow_area. (branch to overflowMBB)
20318 // offsetMBB overflowMBB
20323 // Registers for the PHI in endMBB
20324 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20325 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20327 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20328 MachineFunction *MF = MBB->getParent();
20329 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20330 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20331 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20333 MachineFunction::iterator MBBIter = MBB;
20336 // Insert the new basic blocks
20337 MF->insert(MBBIter, offsetMBB);
20338 MF->insert(MBBIter, overflowMBB);
20339 MF->insert(MBBIter, endMBB);
20341 // Transfer the remainder of MBB and its successor edges to endMBB.
20342 endMBB->splice(endMBB->begin(), thisMBB,
20343 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20344 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20346 // Make offsetMBB and overflowMBB successors of thisMBB
20347 thisMBB->addSuccessor(offsetMBB);
20348 thisMBB->addSuccessor(overflowMBB);
20350 // endMBB is a successor of both offsetMBB and overflowMBB
20351 offsetMBB->addSuccessor(endMBB);
20352 overflowMBB->addSuccessor(endMBB);
20354 // Load the offset value into a register
20355 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20356 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20360 .addDisp(Disp, UseFPOffset ? 4 : 0)
20361 .addOperand(Segment)
20362 .setMemRefs(MMOBegin, MMOEnd);
20364 // Check if there is enough room left to pull this argument.
20365 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20367 .addImm(MaxOffset + 8 - ArgSizeA8);
20369 // Branch to "overflowMBB" if offset >= max
20370 // Fall through to "offsetMBB" otherwise
20371 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20372 .addMBB(overflowMBB);
20375 // In offsetMBB, emit code to use the reg_save_area.
20377 assert(OffsetReg != 0);
20379 // Read the reg_save_area address.
20380 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20381 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20386 .addOperand(Segment)
20387 .setMemRefs(MMOBegin, MMOEnd);
20389 // Zero-extend the offset
20390 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20391 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20394 .addImm(X86::sub_32bit);
20396 // Add the offset to the reg_save_area to get the final address.
20397 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20398 .addReg(OffsetReg64)
20399 .addReg(RegSaveReg);
20401 // Compute the offset for the next argument
20402 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20403 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20405 .addImm(UseFPOffset ? 16 : 8);
20407 // Store it back into the va_list.
20408 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20412 .addDisp(Disp, UseFPOffset ? 4 : 0)
20413 .addOperand(Segment)
20414 .addReg(NextOffsetReg)
20415 .setMemRefs(MMOBegin, MMOEnd);
20418 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20423 // Emit code to use overflow area
20426 // Load the overflow_area address into a register.
20427 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20428 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20433 .addOperand(Segment)
20434 .setMemRefs(MMOBegin, MMOEnd);
20436 // If we need to align it, do so. Otherwise, just copy the address
20437 // to OverflowDestReg.
20439 // Align the overflow address
20440 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20441 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20443 // aligned_addr = (addr + (align-1)) & ~(align-1)
20444 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20445 .addReg(OverflowAddrReg)
20448 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20450 .addImm(~(uint64_t)(Align-1));
20452 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20453 .addReg(OverflowAddrReg);
20456 // Compute the next overflow address after this argument.
20457 // (the overflow address should be kept 8-byte aligned)
20458 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20459 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20460 .addReg(OverflowDestReg)
20461 .addImm(ArgSizeA8);
20463 // Store the new overflow address.
20464 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20469 .addOperand(Segment)
20470 .addReg(NextAddrReg)
20471 .setMemRefs(MMOBegin, MMOEnd);
20473 // If we branched, emit the PHI to the front of endMBB.
20475 BuildMI(*endMBB, endMBB->begin(), DL,
20476 TII->get(X86::PHI), DestReg)
20477 .addReg(OffsetDestReg).addMBB(offsetMBB)
20478 .addReg(OverflowDestReg).addMBB(overflowMBB);
20481 // Erase the pseudo instruction
20482 MI->eraseFromParent();
20487 MachineBasicBlock *
20488 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20490 MachineBasicBlock *MBB) const {
20491 // Emit code to save XMM registers to the stack. The ABI says that the
20492 // number of registers to save is given in %al, so it's theoretically
20493 // possible to do an indirect jump trick to avoid saving all of them,
20494 // however this code takes a simpler approach and just executes all
20495 // of the stores if %al is non-zero. It's less code, and it's probably
20496 // easier on the hardware branch predictor, and stores aren't all that
20497 // expensive anyway.
20499 // Create the new basic blocks. One block contains all the XMM stores,
20500 // and one block is the final destination regardless of whether any
20501 // stores were performed.
20502 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20503 MachineFunction *F = MBB->getParent();
20504 MachineFunction::iterator MBBIter = MBB;
20506 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20507 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20508 F->insert(MBBIter, XMMSaveMBB);
20509 F->insert(MBBIter, EndMBB);
20511 // Transfer the remainder of MBB and its successor edges to EndMBB.
20512 EndMBB->splice(EndMBB->begin(), MBB,
20513 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20514 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20516 // The original block will now fall through to the XMM save block.
20517 MBB->addSuccessor(XMMSaveMBB);
20518 // The XMMSaveMBB will fall through to the end block.
20519 XMMSaveMBB->addSuccessor(EndMBB);
20521 // Now add the instructions.
20522 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20523 DebugLoc DL = MI->getDebugLoc();
20525 unsigned CountReg = MI->getOperand(0).getReg();
20526 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20527 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20529 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20530 // If %al is 0, branch around the XMM save block.
20531 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20532 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20533 MBB->addSuccessor(EndMBB);
20536 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20537 // that was just emitted, but clearly shouldn't be "saved".
20538 assert((MI->getNumOperands() <= 3 ||
20539 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20540 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20541 && "Expected last argument to be EFLAGS");
20542 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20543 // In the XMM save block, save all the XMM argument registers.
20544 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20545 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20546 MachineMemOperand *MMO = F->getMachineMemOperand(
20547 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20548 MachineMemOperand::MOStore,
20549 /*Size=*/16, /*Align=*/16);
20550 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20551 .addFrameIndex(RegSaveFrameIndex)
20552 .addImm(/*Scale=*/1)
20553 .addReg(/*IndexReg=*/0)
20554 .addImm(/*Disp=*/Offset)
20555 .addReg(/*Segment=*/0)
20556 .addReg(MI->getOperand(i).getReg())
20557 .addMemOperand(MMO);
20560 MI->eraseFromParent(); // The pseudo instruction is gone now.
20565 // The EFLAGS operand of SelectItr might be missing a kill marker
20566 // because there were multiple uses of EFLAGS, and ISel didn't know
20567 // which to mark. Figure out whether SelectItr should have had a
20568 // kill marker, and set it if it should. Returns the correct kill
20570 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20571 MachineBasicBlock* BB,
20572 const TargetRegisterInfo* TRI) {
20573 // Scan forward through BB for a use/def of EFLAGS.
20574 MachineBasicBlock::iterator miI(std::next(SelectItr));
20575 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20576 const MachineInstr& mi = *miI;
20577 if (mi.readsRegister(X86::EFLAGS))
20579 if (mi.definesRegister(X86::EFLAGS))
20580 break; // Should have kill-flag - update below.
20583 // If we hit the end of the block, check whether EFLAGS is live into a
20585 if (miI == BB->end()) {
20586 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20587 sEnd = BB->succ_end();
20588 sItr != sEnd; ++sItr) {
20589 MachineBasicBlock* succ = *sItr;
20590 if (succ->isLiveIn(X86::EFLAGS))
20595 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20596 // out. SelectMI should have a kill flag on EFLAGS.
20597 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20601 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20602 // together with other CMOV pseudo-opcodes into a single basic-block with
20603 // conditional jump around it.
20604 static bool isCMOVPseudo(MachineInstr *MI) {
20605 switch (MI->getOpcode()) {
20606 case X86::CMOV_FR32:
20607 case X86::CMOV_FR64:
20608 case X86::CMOV_GR8:
20609 case X86::CMOV_GR16:
20610 case X86::CMOV_GR32:
20611 case X86::CMOV_RFP32:
20612 case X86::CMOV_RFP64:
20613 case X86::CMOV_RFP80:
20614 case X86::CMOV_V2F64:
20615 case X86::CMOV_V2I64:
20616 case X86::CMOV_V4F32:
20617 case X86::CMOV_V4F64:
20618 case X86::CMOV_V4I64:
20619 case X86::CMOV_V16F32:
20620 case X86::CMOV_V8F32:
20621 case X86::CMOV_V8F64:
20622 case X86::CMOV_V8I64:
20623 case X86::CMOV_V8I1:
20624 case X86::CMOV_V16I1:
20625 case X86::CMOV_V32I1:
20626 case X86::CMOV_V64I1:
20634 MachineBasicBlock *
20635 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20636 MachineBasicBlock *BB) const {
20637 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20638 DebugLoc DL = MI->getDebugLoc();
20640 // To "insert" a SELECT_CC instruction, we actually have to insert the
20641 // diamond control-flow pattern. The incoming instruction knows the
20642 // destination vreg to set, the condition code register to branch on, the
20643 // true/false values to select between, and a branch opcode to use.
20644 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20645 MachineFunction::iterator It = BB;
20651 // cmpTY ccX, r1, r2
20653 // fallthrough --> copy0MBB
20654 MachineBasicBlock *thisMBB = BB;
20655 MachineFunction *F = BB->getParent();
20657 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20658 // as described above, by inserting a BB, and then making a PHI at the join
20659 // point to select the true and false operands of the CMOV in the PHI.
20661 // The code also handles two different cases of multiple CMOV opcodes
20665 // In this case, there are multiple CMOVs in a row, all which are based on
20666 // the same condition setting (or the exact opposite condition setting).
20667 // In this case we can lower all the CMOVs using a single inserted BB, and
20668 // then make a number of PHIs at the join point to model the CMOVs. The only
20669 // trickiness here, is that in a case like:
20671 // t2 = CMOV cond1 t1, f1
20672 // t3 = CMOV cond1 t2, f2
20674 // when rewriting this into PHIs, we have to perform some renaming on the
20675 // temps since you cannot have a PHI operand refer to a PHI result earlier
20676 // in the same block. The "simple" but wrong lowering would be:
20678 // t2 = PHI t1(BB1), f1(BB2)
20679 // t3 = PHI t2(BB1), f2(BB2)
20681 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20682 // renaming is to note that on the path through BB1, t2 is really just a
20683 // copy of t1, and do that renaming, properly generating:
20685 // t2 = PHI t1(BB1), f1(BB2)
20686 // t3 = PHI t1(BB1), f2(BB2)
20688 // Case 2, we lower cascaded CMOVs such as
20690 // (CMOV (CMOV F, T, cc1), T, cc2)
20692 // to two successives branches. For that, we look for another CMOV as the
20693 // following instruction.
20695 // Without this, we would add a PHI between the two jumps, which ends up
20696 // creating a few copies all around. For instance, for
20698 // (sitofp (zext (fcmp une)))
20700 // we would generate:
20702 // ucomiss %xmm1, %xmm0
20703 // movss <1.0f>, %xmm0
20704 // movaps %xmm0, %xmm1
20706 // xorps %xmm1, %xmm1
20709 // movaps %xmm1, %xmm0
20713 // because this custom-inserter would have generated:
20725 // A: X = ...; Y = ...
20727 // C: Z = PHI [X, A], [Y, B]
20729 // E: PHI [X, C], [Z, D]
20731 // If we lower both CMOVs in a single step, we can instead generate:
20743 // A: X = ...; Y = ...
20745 // E: PHI [X, A], [X, C], [Y, D]
20747 // Which, in our sitofp/fcmp example, gives us something like:
20749 // ucomiss %xmm1, %xmm0
20750 // movss <1.0f>, %xmm0
20753 // xorps %xmm0, %xmm0
20757 MachineInstr *CascadedCMOV = nullptr;
20758 MachineInstr *LastCMOV = MI;
20759 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20760 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20761 MachineBasicBlock::iterator NextMIIt =
20762 std::next(MachineBasicBlock::iterator(MI));
20764 // Check for case 1, where there are multiple CMOVs with the same condition
20765 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20766 // number of jumps the most.
20768 if (isCMOVPseudo(MI)) {
20769 // See if we have a string of CMOVS with the same condition.
20770 while (NextMIIt != BB->end() &&
20771 isCMOVPseudo(NextMIIt) &&
20772 (NextMIIt->getOperand(3).getImm() == CC ||
20773 NextMIIt->getOperand(3).getImm() == OppCC)) {
20774 LastCMOV = &*NextMIIt;
20779 // This checks for case 2, but only do this if we didn't already find
20780 // case 1, as indicated by LastCMOV == MI.
20781 if (LastCMOV == MI &&
20782 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20783 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20784 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20785 CascadedCMOV = &*NextMIIt;
20788 MachineBasicBlock *jcc1MBB = nullptr;
20790 // If we have a cascaded CMOV, we lower it to two successive branches to
20791 // the same block. EFLAGS is used by both, so mark it as live in the second.
20792 if (CascadedCMOV) {
20793 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20794 F->insert(It, jcc1MBB);
20795 jcc1MBB->addLiveIn(X86::EFLAGS);
20798 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20799 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20800 F->insert(It, copy0MBB);
20801 F->insert(It, sinkMBB);
20803 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20804 // live into the sink and copy blocks.
20805 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20807 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20808 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20809 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20810 copy0MBB->addLiveIn(X86::EFLAGS);
20811 sinkMBB->addLiveIn(X86::EFLAGS);
20814 // Transfer the remainder of BB and its successor edges to sinkMBB.
20815 sinkMBB->splice(sinkMBB->begin(), BB,
20816 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20817 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20819 // Add the true and fallthrough blocks as its successors.
20820 if (CascadedCMOV) {
20821 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20822 BB->addSuccessor(jcc1MBB);
20824 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20825 // jump to the sinkMBB.
20826 jcc1MBB->addSuccessor(copy0MBB);
20827 jcc1MBB->addSuccessor(sinkMBB);
20829 BB->addSuccessor(copy0MBB);
20832 // The true block target of the first (or only) branch is always sinkMBB.
20833 BB->addSuccessor(sinkMBB);
20835 // Create the conditional branch instruction.
20836 unsigned Opc = X86::GetCondBranchFromCond(CC);
20837 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20839 if (CascadedCMOV) {
20840 unsigned Opc2 = X86::GetCondBranchFromCond(
20841 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20842 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20846 // %FalseValue = ...
20847 // # fallthrough to sinkMBB
20848 copy0MBB->addSuccessor(sinkMBB);
20851 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20853 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20854 MachineBasicBlock::iterator MIItEnd =
20855 std::next(MachineBasicBlock::iterator(LastCMOV));
20856 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20857 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20858 MachineInstrBuilder MIB;
20860 // As we are creating the PHIs, we have to be careful if there is more than
20861 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20862 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20863 // That also means that PHI construction must work forward from earlier to
20864 // later, and that the code must maintain a mapping from earlier PHI's
20865 // destination registers, and the registers that went into the PHI.
20867 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20868 unsigned DestReg = MIIt->getOperand(0).getReg();
20869 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20870 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20872 // If this CMOV we are generating is the opposite condition from
20873 // the jump we generated, then we have to swap the operands for the
20874 // PHI that is going to be generated.
20875 if (MIIt->getOperand(3).getImm() == OppCC)
20876 std::swap(Op1Reg, Op2Reg);
20878 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20879 Op1Reg = RegRewriteTable[Op1Reg].first;
20881 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20882 Op2Reg = RegRewriteTable[Op2Reg].second;
20884 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20885 TII->get(X86::PHI), DestReg)
20886 .addReg(Op1Reg).addMBB(copy0MBB)
20887 .addReg(Op2Reg).addMBB(thisMBB);
20889 // Add this PHI to the rewrite table.
20890 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20893 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20894 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20895 if (CascadedCMOV) {
20896 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20897 // Copy the PHI result to the register defined by the second CMOV.
20898 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20899 DL, TII->get(TargetOpcode::COPY),
20900 CascadedCMOV->getOperand(0).getReg())
20901 .addReg(MI->getOperand(0).getReg());
20902 CascadedCMOV->eraseFromParent();
20905 // Now remove the CMOV(s).
20906 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20907 (MIIt++)->eraseFromParent();
20912 MachineBasicBlock *
20913 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20914 MachineBasicBlock *BB) const {
20915 // Combine the following atomic floating-point modification pattern:
20916 // a.store(reg OP a.load(acquire), release)
20917 // Transform them into:
20918 // OPss (%gpr), %xmm
20919 // movss %xmm, (%gpr)
20920 // Or sd equivalent for 64-bit operations.
20922 switch (MI->getOpcode()) {
20923 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20924 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20925 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20927 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20928 DebugLoc DL = MI->getDebugLoc();
20929 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20930 unsigned MSrc = MI->getOperand(0).getReg();
20931 unsigned VSrc = MI->getOperand(5).getReg();
20932 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20933 .addReg(/*Base=*/MSrc)
20934 .addImm(/*Scale=*/1)
20935 .addReg(/*Index=*/0)
20938 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20939 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20941 .addReg(/*Base=*/MSrc)
20942 .addImm(/*Scale=*/1)
20943 .addReg(/*Index=*/0)
20944 .addImm(/*Disp=*/0)
20945 .addReg(/*Segment=*/0);
20946 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20947 MI->eraseFromParent(); // The pseudo instruction is gone now.
20951 MachineBasicBlock *
20952 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20953 MachineBasicBlock *BB) const {
20954 MachineFunction *MF = BB->getParent();
20955 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20956 DebugLoc DL = MI->getDebugLoc();
20957 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20959 assert(MF->shouldSplitStack());
20961 const bool Is64Bit = Subtarget->is64Bit();
20962 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20964 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20965 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20968 // ... [Till the alloca]
20969 // If stacklet is not large enough, jump to mallocMBB
20972 // Allocate by subtracting from RSP
20973 // Jump to continueMBB
20976 // Allocate by call to runtime
20980 // [rest of original BB]
20983 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20984 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20985 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20987 MachineRegisterInfo &MRI = MF->getRegInfo();
20988 const TargetRegisterClass *AddrRegClass =
20989 getRegClassFor(getPointerTy(MF->getDataLayout()));
20991 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20992 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20993 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20994 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20995 sizeVReg = MI->getOperand(1).getReg(),
20996 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20998 MachineFunction::iterator MBBIter = BB;
21001 MF->insert(MBBIter, bumpMBB);
21002 MF->insert(MBBIter, mallocMBB);
21003 MF->insert(MBBIter, continueMBB);
21005 continueMBB->splice(continueMBB->begin(), BB,
21006 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21007 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21009 // Add code to the main basic block to check if the stack limit has been hit,
21010 // and if so, jump to mallocMBB otherwise to bumpMBB.
21011 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21012 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21013 .addReg(tmpSPVReg).addReg(sizeVReg);
21014 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21015 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21016 .addReg(SPLimitVReg);
21017 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21019 // bumpMBB simply decreases the stack pointer, since we know the current
21020 // stacklet has enough space.
21021 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21022 .addReg(SPLimitVReg);
21023 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21024 .addReg(SPLimitVReg);
21025 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21027 // Calls into a routine in libgcc to allocate more space from the heap.
21028 const uint32_t *RegMask =
21029 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21031 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21033 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21034 .addExternalSymbol("__morestack_allocate_stack_space")
21035 .addRegMask(RegMask)
21036 .addReg(X86::RDI, RegState::Implicit)
21037 .addReg(X86::RAX, RegState::ImplicitDefine);
21038 } else if (Is64Bit) {
21039 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21041 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21042 .addExternalSymbol("__morestack_allocate_stack_space")
21043 .addRegMask(RegMask)
21044 .addReg(X86::EDI, RegState::Implicit)
21045 .addReg(X86::EAX, RegState::ImplicitDefine);
21047 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21049 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21050 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21051 .addExternalSymbol("__morestack_allocate_stack_space")
21052 .addRegMask(RegMask)
21053 .addReg(X86::EAX, RegState::ImplicitDefine);
21057 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21060 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21061 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21062 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21064 // Set up the CFG correctly.
21065 BB->addSuccessor(bumpMBB);
21066 BB->addSuccessor(mallocMBB);
21067 mallocMBB->addSuccessor(continueMBB);
21068 bumpMBB->addSuccessor(continueMBB);
21070 // Take care of the PHI nodes.
21071 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21072 MI->getOperand(0).getReg())
21073 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21074 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21076 // Delete the original pseudo instruction.
21077 MI->eraseFromParent();
21080 return continueMBB;
21083 MachineBasicBlock *
21084 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21085 MachineBasicBlock *BB) const {
21086 DebugLoc DL = MI->getDebugLoc();
21088 assert(!Subtarget->isTargetMachO());
21090 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21093 MI->eraseFromParent(); // The pseudo instruction is gone now.
21097 MachineBasicBlock *
21098 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21099 MachineBasicBlock *BB) const {
21100 // This is pretty easy. We're taking the value that we received from
21101 // our load from the relocation, sticking it in either RDI (x86-64)
21102 // or EAX and doing an indirect call. The return value will then
21103 // be in the normal return register.
21104 MachineFunction *F = BB->getParent();
21105 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21106 DebugLoc DL = MI->getDebugLoc();
21108 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21109 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21111 // Get a register mask for the lowered call.
21112 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21113 // proper register mask.
21114 const uint32_t *RegMask =
21115 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21116 if (Subtarget->is64Bit()) {
21117 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21118 TII->get(X86::MOV64rm), X86::RDI)
21120 .addImm(0).addReg(0)
21121 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21122 MI->getOperand(3).getTargetFlags())
21124 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21125 addDirectMem(MIB, X86::RDI);
21126 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21127 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21128 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21129 TII->get(X86::MOV32rm), X86::EAX)
21131 .addImm(0).addReg(0)
21132 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21133 MI->getOperand(3).getTargetFlags())
21135 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21136 addDirectMem(MIB, X86::EAX);
21137 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21139 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21140 TII->get(X86::MOV32rm), X86::EAX)
21141 .addReg(TII->getGlobalBaseReg(F))
21142 .addImm(0).addReg(0)
21143 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21144 MI->getOperand(3).getTargetFlags())
21146 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21147 addDirectMem(MIB, X86::EAX);
21148 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21151 MI->eraseFromParent(); // The pseudo instruction is gone now.
21155 MachineBasicBlock *
21156 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21157 MachineBasicBlock *MBB) const {
21158 DebugLoc DL = MI->getDebugLoc();
21159 MachineFunction *MF = MBB->getParent();
21160 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21161 MachineRegisterInfo &MRI = MF->getRegInfo();
21163 const BasicBlock *BB = MBB->getBasicBlock();
21164 MachineFunction::iterator I = MBB;
21167 // Memory Reference
21168 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21169 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21172 unsigned MemOpndSlot = 0;
21174 unsigned CurOp = 0;
21176 DstReg = MI->getOperand(CurOp++).getReg();
21177 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21178 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21179 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21180 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21182 MemOpndSlot = CurOp;
21184 MVT PVT = getPointerTy(MF->getDataLayout());
21185 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21186 "Invalid Pointer Size!");
21188 // For v = setjmp(buf), we generate
21191 // buf[LabelOffset] = restoreMBB
21192 // SjLjSetup restoreMBB
21198 // v = phi(main, restore)
21201 // if base pointer being used, load it from frame
21204 MachineBasicBlock *thisMBB = MBB;
21205 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21206 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21207 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21208 MF->insert(I, mainMBB);
21209 MF->insert(I, sinkMBB);
21210 MF->push_back(restoreMBB);
21212 MachineInstrBuilder MIB;
21214 // Transfer the remainder of BB and its successor edges to sinkMBB.
21215 sinkMBB->splice(sinkMBB->begin(), MBB,
21216 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21217 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21220 unsigned PtrStoreOpc = 0;
21221 unsigned LabelReg = 0;
21222 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21223 Reloc::Model RM = MF->getTarget().getRelocationModel();
21224 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21225 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21227 // Prepare IP either in reg or imm.
21228 if (!UseImmLabel) {
21229 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21230 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21231 LabelReg = MRI.createVirtualRegister(PtrRC);
21232 if (Subtarget->is64Bit()) {
21233 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21237 .addMBB(restoreMBB)
21240 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21241 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21242 .addReg(XII->getGlobalBaseReg(MF))
21245 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21249 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21251 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21252 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21253 if (i == X86::AddrDisp)
21254 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21256 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21259 MIB.addReg(LabelReg);
21261 MIB.addMBB(restoreMBB);
21262 MIB.setMemRefs(MMOBegin, MMOEnd);
21264 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21265 .addMBB(restoreMBB);
21267 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21268 MIB.addRegMask(RegInfo->getNoPreservedMask());
21269 thisMBB->addSuccessor(mainMBB);
21270 thisMBB->addSuccessor(restoreMBB);
21274 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21275 mainMBB->addSuccessor(sinkMBB);
21278 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21279 TII->get(X86::PHI), DstReg)
21280 .addReg(mainDstReg).addMBB(mainMBB)
21281 .addReg(restoreDstReg).addMBB(restoreMBB);
21284 if (RegInfo->hasBasePointer(*MF)) {
21285 const bool Uses64BitFramePtr =
21286 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21287 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21288 X86FI->setRestoreBasePointer(MF);
21289 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21290 unsigned BasePtr = RegInfo->getBaseRegister();
21291 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21292 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21293 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21294 .setMIFlag(MachineInstr::FrameSetup);
21296 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21297 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21298 restoreMBB->addSuccessor(sinkMBB);
21300 MI->eraseFromParent();
21304 MachineBasicBlock *
21305 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21306 MachineBasicBlock *MBB) const {
21307 DebugLoc DL = MI->getDebugLoc();
21308 MachineFunction *MF = MBB->getParent();
21309 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21310 MachineRegisterInfo &MRI = MF->getRegInfo();
21312 // Memory Reference
21313 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21314 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21316 MVT PVT = getPointerTy(MF->getDataLayout());
21317 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21318 "Invalid Pointer Size!");
21320 const TargetRegisterClass *RC =
21321 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21322 unsigned Tmp = MRI.createVirtualRegister(RC);
21323 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21324 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21325 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21326 unsigned SP = RegInfo->getStackRegister();
21328 MachineInstrBuilder MIB;
21330 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21331 const int64_t SPOffset = 2 * PVT.getStoreSize();
21333 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21334 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21337 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21338 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21339 MIB.addOperand(MI->getOperand(i));
21340 MIB.setMemRefs(MMOBegin, MMOEnd);
21342 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21343 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21344 if (i == X86::AddrDisp)
21345 MIB.addDisp(MI->getOperand(i), LabelOffset);
21347 MIB.addOperand(MI->getOperand(i));
21349 MIB.setMemRefs(MMOBegin, MMOEnd);
21351 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21352 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21353 if (i == X86::AddrDisp)
21354 MIB.addDisp(MI->getOperand(i), SPOffset);
21356 MIB.addOperand(MI->getOperand(i));
21358 MIB.setMemRefs(MMOBegin, MMOEnd);
21360 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21362 MI->eraseFromParent();
21366 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21367 // accumulator loops. Writing back to the accumulator allows the coalescer
21368 // to remove extra copies in the loop.
21369 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21370 MachineBasicBlock *
21371 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21372 MachineBasicBlock *MBB) const {
21373 MachineOperand &AddendOp = MI->getOperand(3);
21375 // Bail out early if the addend isn't a register - we can't switch these.
21376 if (!AddendOp.isReg())
21379 MachineFunction &MF = *MBB->getParent();
21380 MachineRegisterInfo &MRI = MF.getRegInfo();
21382 // Check whether the addend is defined by a PHI:
21383 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21384 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21385 if (!AddendDef.isPHI())
21388 // Look for the following pattern:
21390 // %addend = phi [%entry, 0], [%loop, %result]
21392 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21396 // %addend = phi [%entry, 0], [%loop, %result]
21398 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21400 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21401 assert(AddendDef.getOperand(i).isReg());
21402 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21403 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21404 if (&PHISrcInst == MI) {
21405 // Found a matching instruction.
21406 unsigned NewFMAOpc = 0;
21407 switch (MI->getOpcode()) {
21408 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21409 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21410 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21411 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21412 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21413 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21414 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21415 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21416 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21417 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21418 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21419 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21420 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21421 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21422 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21423 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21424 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21425 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21426 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21427 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21429 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21430 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21431 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21432 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21433 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21434 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21435 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21436 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21437 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21438 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21439 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21440 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21441 default: llvm_unreachable("Unrecognized FMA variant.");
21444 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21445 MachineInstrBuilder MIB =
21446 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21447 .addOperand(MI->getOperand(0))
21448 .addOperand(MI->getOperand(3))
21449 .addOperand(MI->getOperand(2))
21450 .addOperand(MI->getOperand(1));
21451 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21452 MI->eraseFromParent();
21459 MachineBasicBlock *
21460 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21461 MachineBasicBlock *BB) const {
21462 switch (MI->getOpcode()) {
21463 default: llvm_unreachable("Unexpected instr type to insert");
21464 case X86::TAILJMPd64:
21465 case X86::TAILJMPr64:
21466 case X86::TAILJMPm64:
21467 case X86::TAILJMPd64_REX:
21468 case X86::TAILJMPr64_REX:
21469 case X86::TAILJMPm64_REX:
21470 llvm_unreachable("TAILJMP64 would not be touched here.");
21471 case X86::TCRETURNdi64:
21472 case X86::TCRETURNri64:
21473 case X86::TCRETURNmi64:
21475 case X86::WIN_ALLOCA:
21476 return EmitLoweredWinAlloca(MI, BB);
21477 case X86::SEG_ALLOCA_32:
21478 case X86::SEG_ALLOCA_64:
21479 return EmitLoweredSegAlloca(MI, BB);
21480 case X86::TLSCall_32:
21481 case X86::TLSCall_64:
21482 return EmitLoweredTLSCall(MI, BB);
21483 case X86::CMOV_FR32:
21484 case X86::CMOV_FR64:
21485 case X86::CMOV_GR8:
21486 case X86::CMOV_GR16:
21487 case X86::CMOV_GR32:
21488 case X86::CMOV_RFP32:
21489 case X86::CMOV_RFP64:
21490 case X86::CMOV_RFP80:
21491 case X86::CMOV_V2F64:
21492 case X86::CMOV_V2I64:
21493 case X86::CMOV_V4F32:
21494 case X86::CMOV_V4F64:
21495 case X86::CMOV_V4I64:
21496 case X86::CMOV_V16F32:
21497 case X86::CMOV_V8F32:
21498 case X86::CMOV_V8F64:
21499 case X86::CMOV_V8I64:
21500 case X86::CMOV_V8I1:
21501 case X86::CMOV_V16I1:
21502 case X86::CMOV_V32I1:
21503 case X86::CMOV_V64I1:
21504 return EmitLoweredSelect(MI, BB);
21506 case X86::RELEASE_FADD32mr:
21507 case X86::RELEASE_FADD64mr:
21508 return EmitLoweredAtomicFP(MI, BB);
21510 case X86::FP32_TO_INT16_IN_MEM:
21511 case X86::FP32_TO_INT32_IN_MEM:
21512 case X86::FP32_TO_INT64_IN_MEM:
21513 case X86::FP64_TO_INT16_IN_MEM:
21514 case X86::FP64_TO_INT32_IN_MEM:
21515 case X86::FP64_TO_INT64_IN_MEM:
21516 case X86::FP80_TO_INT16_IN_MEM:
21517 case X86::FP80_TO_INT32_IN_MEM:
21518 case X86::FP80_TO_INT64_IN_MEM: {
21519 MachineFunction *F = BB->getParent();
21520 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21521 DebugLoc DL = MI->getDebugLoc();
21523 // Change the floating point control register to use "round towards zero"
21524 // mode when truncating to an integer value.
21525 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21526 addFrameReference(BuildMI(*BB, MI, DL,
21527 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21529 // Load the old value of the high byte of the control word...
21531 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21532 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21535 // Set the high part to be round to zero...
21536 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21539 // Reload the modified control word now...
21540 addFrameReference(BuildMI(*BB, MI, DL,
21541 TII->get(X86::FLDCW16m)), CWFrameIdx);
21543 // Restore the memory image of control word to original value
21544 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21547 // Get the X86 opcode to use.
21549 switch (MI->getOpcode()) {
21550 default: llvm_unreachable("illegal opcode!");
21551 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21552 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21553 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21554 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21555 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21556 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21557 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21558 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21559 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21563 MachineOperand &Op = MI->getOperand(0);
21565 AM.BaseType = X86AddressMode::RegBase;
21566 AM.Base.Reg = Op.getReg();
21568 AM.BaseType = X86AddressMode::FrameIndexBase;
21569 AM.Base.FrameIndex = Op.getIndex();
21571 Op = MI->getOperand(1);
21573 AM.Scale = Op.getImm();
21574 Op = MI->getOperand(2);
21576 AM.IndexReg = Op.getImm();
21577 Op = MI->getOperand(3);
21578 if (Op.isGlobal()) {
21579 AM.GV = Op.getGlobal();
21581 AM.Disp = Op.getImm();
21583 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21584 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21586 // Reload the original control word now.
21587 addFrameReference(BuildMI(*BB, MI, DL,
21588 TII->get(X86::FLDCW16m)), CWFrameIdx);
21590 MI->eraseFromParent(); // The pseudo instruction is gone now.
21593 // String/text processing lowering.
21594 case X86::PCMPISTRM128REG:
21595 case X86::VPCMPISTRM128REG:
21596 case X86::PCMPISTRM128MEM:
21597 case X86::VPCMPISTRM128MEM:
21598 case X86::PCMPESTRM128REG:
21599 case X86::VPCMPESTRM128REG:
21600 case X86::PCMPESTRM128MEM:
21601 case X86::VPCMPESTRM128MEM:
21602 assert(Subtarget->hasSSE42() &&
21603 "Target must have SSE4.2 or AVX features enabled");
21604 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21606 // String/text processing lowering.
21607 case X86::PCMPISTRIREG:
21608 case X86::VPCMPISTRIREG:
21609 case X86::PCMPISTRIMEM:
21610 case X86::VPCMPISTRIMEM:
21611 case X86::PCMPESTRIREG:
21612 case X86::VPCMPESTRIREG:
21613 case X86::PCMPESTRIMEM:
21614 case X86::VPCMPESTRIMEM:
21615 assert(Subtarget->hasSSE42() &&
21616 "Target must have SSE4.2 or AVX features enabled");
21617 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21619 // Thread synchronization.
21621 return EmitMonitor(MI, BB, Subtarget);
21625 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21627 case X86::VASTART_SAVE_XMM_REGS:
21628 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21630 case X86::VAARG_64:
21631 return EmitVAARG64WithCustomInserter(MI, BB);
21633 case X86::EH_SjLj_SetJmp32:
21634 case X86::EH_SjLj_SetJmp64:
21635 return emitEHSjLjSetJmp(MI, BB);
21637 case X86::EH_SjLj_LongJmp32:
21638 case X86::EH_SjLj_LongJmp64:
21639 return emitEHSjLjLongJmp(MI, BB);
21641 case TargetOpcode::STATEPOINT:
21642 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21643 // this point in the process. We diverge later.
21644 return emitPatchPoint(MI, BB);
21646 case TargetOpcode::STACKMAP:
21647 case TargetOpcode::PATCHPOINT:
21648 return emitPatchPoint(MI, BB);
21650 case X86::VFMADDPDr213r:
21651 case X86::VFMADDPSr213r:
21652 case X86::VFMADDSDr213r:
21653 case X86::VFMADDSSr213r:
21654 case X86::VFMSUBPDr213r:
21655 case X86::VFMSUBPSr213r:
21656 case X86::VFMSUBSDr213r:
21657 case X86::VFMSUBSSr213r:
21658 case X86::VFNMADDPDr213r:
21659 case X86::VFNMADDPSr213r:
21660 case X86::VFNMADDSDr213r:
21661 case X86::VFNMADDSSr213r:
21662 case X86::VFNMSUBPDr213r:
21663 case X86::VFNMSUBPSr213r:
21664 case X86::VFNMSUBSDr213r:
21665 case X86::VFNMSUBSSr213r:
21666 case X86::VFMADDSUBPDr213r:
21667 case X86::VFMADDSUBPSr213r:
21668 case X86::VFMSUBADDPDr213r:
21669 case X86::VFMSUBADDPSr213r:
21670 case X86::VFMADDPDr213rY:
21671 case X86::VFMADDPSr213rY:
21672 case X86::VFMSUBPDr213rY:
21673 case X86::VFMSUBPSr213rY:
21674 case X86::VFNMADDPDr213rY:
21675 case X86::VFNMADDPSr213rY:
21676 case X86::VFNMSUBPDr213rY:
21677 case X86::VFNMSUBPSr213rY:
21678 case X86::VFMADDSUBPDr213rY:
21679 case X86::VFMADDSUBPSr213rY:
21680 case X86::VFMSUBADDPDr213rY:
21681 case X86::VFMSUBADDPSr213rY:
21682 return emitFMA3Instr(MI, BB);
21686 //===----------------------------------------------------------------------===//
21687 // X86 Optimization Hooks
21688 //===----------------------------------------------------------------------===//
21690 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21693 const SelectionDAG &DAG,
21694 unsigned Depth) const {
21695 unsigned BitWidth = KnownZero.getBitWidth();
21696 unsigned Opc = Op.getOpcode();
21697 assert((Opc >= ISD::BUILTIN_OP_END ||
21698 Opc == ISD::INTRINSIC_WO_CHAIN ||
21699 Opc == ISD::INTRINSIC_W_CHAIN ||
21700 Opc == ISD::INTRINSIC_VOID) &&
21701 "Should use MaskedValueIsZero if you don't know whether Op"
21702 " is a target node!");
21704 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21718 // These nodes' second result is a boolean.
21719 if (Op.getResNo() == 0)
21722 case X86ISD::SETCC:
21723 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21725 case ISD::INTRINSIC_WO_CHAIN: {
21726 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21727 unsigned NumLoBits = 0;
21730 case Intrinsic::x86_sse_movmsk_ps:
21731 case Intrinsic::x86_avx_movmsk_ps_256:
21732 case Intrinsic::x86_sse2_movmsk_pd:
21733 case Intrinsic::x86_avx_movmsk_pd_256:
21734 case Intrinsic::x86_mmx_pmovmskb:
21735 case Intrinsic::x86_sse2_pmovmskb_128:
21736 case Intrinsic::x86_avx2_pmovmskb: {
21737 // High bits of movmskp{s|d}, pmovmskb are known zero.
21739 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21740 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21741 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21742 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21743 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21744 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21745 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21746 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21748 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21757 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21759 const SelectionDAG &,
21760 unsigned Depth) const {
21761 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21762 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21763 return Op.getValueType().getScalarType().getSizeInBits();
21769 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21770 /// node is a GlobalAddress + offset.
21771 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21772 const GlobalValue* &GA,
21773 int64_t &Offset) const {
21774 if (N->getOpcode() == X86ISD::Wrapper) {
21775 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21776 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21777 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21781 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21784 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21785 /// same as extracting the high 128-bit part of 256-bit vector and then
21786 /// inserting the result into the low part of a new 256-bit vector
21787 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21788 EVT VT = SVOp->getValueType(0);
21789 unsigned NumElems = VT.getVectorNumElements();
21791 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21792 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21793 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21794 SVOp->getMaskElt(j) >= 0)
21800 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21801 /// same as extracting the low 128-bit part of 256-bit vector and then
21802 /// inserting the result into the high part of a new 256-bit vector
21803 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21804 EVT VT = SVOp->getValueType(0);
21805 unsigned NumElems = VT.getVectorNumElements();
21807 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21808 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21809 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21810 SVOp->getMaskElt(j) >= 0)
21816 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21817 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21818 TargetLowering::DAGCombinerInfo &DCI,
21819 const X86Subtarget* Subtarget) {
21821 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21822 SDValue V1 = SVOp->getOperand(0);
21823 SDValue V2 = SVOp->getOperand(1);
21824 EVT VT = SVOp->getValueType(0);
21825 unsigned NumElems = VT.getVectorNumElements();
21827 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21828 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21832 // V UNDEF BUILD_VECTOR UNDEF
21834 // CONCAT_VECTOR CONCAT_VECTOR
21837 // RESULT: V + zero extended
21839 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21840 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21841 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21844 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21847 // To match the shuffle mask, the first half of the mask should
21848 // be exactly the first vector, and all the rest a splat with the
21849 // first element of the second one.
21850 for (unsigned i = 0; i != NumElems/2; ++i)
21851 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21852 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21855 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21856 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21857 if (Ld->hasNUsesOfValue(1, 0)) {
21858 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21859 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21861 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21863 Ld->getPointerInfo(),
21864 Ld->getAlignment(),
21865 false/*isVolatile*/, true/*ReadMem*/,
21866 false/*WriteMem*/);
21868 // Make sure the newly-created LOAD is in the same position as Ld in
21869 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21870 // and update uses of Ld's output chain to use the TokenFactor.
21871 if (Ld->hasAnyUseOfValue(1)) {
21872 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21873 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21874 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21875 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21876 SDValue(ResNode.getNode(), 1));
21879 return DAG.getBitcast(VT, ResNode);
21883 // Emit a zeroed vector and insert the desired subvector on its
21885 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21886 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21887 return DCI.CombineTo(N, InsV);
21890 //===--------------------------------------------------------------------===//
21891 // Combine some shuffles into subvector extracts and inserts:
21894 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21895 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21896 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21897 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21898 return DCI.CombineTo(N, InsV);
21901 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21902 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21903 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21904 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21905 return DCI.CombineTo(N, InsV);
21911 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21914 /// This is the leaf of the recursive combinine below. When we have found some
21915 /// chain of single-use x86 shuffle instructions and accumulated the combined
21916 /// shuffle mask represented by them, this will try to pattern match that mask
21917 /// into either a single instruction if there is a special purpose instruction
21918 /// for this operation, or into a PSHUFB instruction which is a fully general
21919 /// instruction but should only be used to replace chains over a certain depth.
21920 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21921 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21922 TargetLowering::DAGCombinerInfo &DCI,
21923 const X86Subtarget *Subtarget) {
21924 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21926 // Find the operand that enters the chain. Note that multiple uses are OK
21927 // here, we're not going to remove the operand we find.
21928 SDValue Input = Op.getOperand(0);
21929 while (Input.getOpcode() == ISD::BITCAST)
21930 Input = Input.getOperand(0);
21932 MVT VT = Input.getSimpleValueType();
21933 MVT RootVT = Root.getSimpleValueType();
21936 // Just remove no-op shuffle masks.
21937 if (Mask.size() == 1) {
21938 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21943 // Use the float domain if the operand type is a floating point type.
21944 bool FloatDomain = VT.isFloatingPoint();
21946 // For floating point shuffles, we don't have free copies in the shuffle
21947 // instructions or the ability to load as part of the instruction, so
21948 // canonicalize their shuffles to UNPCK or MOV variants.
21950 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21951 // vectors because it can have a load folded into it that UNPCK cannot. This
21952 // doesn't preclude something switching to the shorter encoding post-RA.
21954 // FIXME: Should teach these routines about AVX vector widths.
21955 if (FloatDomain && VT.getSizeInBits() == 128) {
21956 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21957 bool Lo = Mask.equals({0, 0});
21960 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21961 // is no slower than UNPCKLPD but has the option to fold the input operand
21962 // into even an unaligned memory load.
21963 if (Lo && Subtarget->hasSSE3()) {
21964 Shuffle = X86ISD::MOVDDUP;
21965 ShuffleVT = MVT::v2f64;
21967 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21968 // than the UNPCK variants.
21969 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21970 ShuffleVT = MVT::v4f32;
21972 if (Depth == 1 && Root->getOpcode() == Shuffle)
21973 return false; // Nothing to do!
21974 Op = DAG.getBitcast(ShuffleVT, Input);
21975 DCI.AddToWorklist(Op.getNode());
21976 if (Shuffle == X86ISD::MOVDDUP)
21977 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21979 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21980 DCI.AddToWorklist(Op.getNode());
21981 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21985 if (Subtarget->hasSSE3() &&
21986 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
21987 bool Lo = Mask.equals({0, 0, 2, 2});
21988 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21989 MVT ShuffleVT = MVT::v4f32;
21990 if (Depth == 1 && Root->getOpcode() == Shuffle)
21991 return false; // Nothing to do!
21992 Op = DAG.getBitcast(ShuffleVT, Input);
21993 DCI.AddToWorklist(Op.getNode());
21994 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21995 DCI.AddToWorklist(Op.getNode());
21996 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22000 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22001 bool Lo = Mask.equals({0, 0, 1, 1});
22002 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22003 MVT ShuffleVT = MVT::v4f32;
22004 if (Depth == 1 && Root->getOpcode() == Shuffle)
22005 return false; // Nothing to do!
22006 Op = DAG.getBitcast(ShuffleVT, Input);
22007 DCI.AddToWorklist(Op.getNode());
22008 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22009 DCI.AddToWorklist(Op.getNode());
22010 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22016 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22017 // variants as none of these have single-instruction variants that are
22018 // superior to the UNPCK formulation.
22019 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22020 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22021 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22022 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22024 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22025 bool Lo = Mask[0] == 0;
22026 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22027 if (Depth == 1 && Root->getOpcode() == Shuffle)
22028 return false; // Nothing to do!
22030 switch (Mask.size()) {
22032 ShuffleVT = MVT::v8i16;
22035 ShuffleVT = MVT::v16i8;
22038 llvm_unreachable("Impossible mask size!");
22040 Op = DAG.getBitcast(ShuffleVT, Input);
22041 DCI.AddToWorklist(Op.getNode());
22042 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22043 DCI.AddToWorklist(Op.getNode());
22044 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22049 // Don't try to re-form single instruction chains under any circumstances now
22050 // that we've done encoding canonicalization for them.
22054 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22055 // can replace them with a single PSHUFB instruction profitably. Intel's
22056 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22057 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22058 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22059 SmallVector<SDValue, 16> PSHUFBMask;
22060 int NumBytes = VT.getSizeInBits() / 8;
22061 int Ratio = NumBytes / Mask.size();
22062 for (int i = 0; i < NumBytes; ++i) {
22063 if (Mask[i / Ratio] == SM_SentinelUndef) {
22064 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22067 int M = Mask[i / Ratio] != SM_SentinelZero
22068 ? Ratio * Mask[i / Ratio] + i % Ratio
22070 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22072 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22073 Op = DAG.getBitcast(ByteVT, Input);
22074 DCI.AddToWorklist(Op.getNode());
22075 SDValue PSHUFBMaskOp =
22076 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22077 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22078 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22079 DCI.AddToWorklist(Op.getNode());
22080 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22085 // Failed to find any combines.
22089 /// \brief Fully generic combining of x86 shuffle instructions.
22091 /// This should be the last combine run over the x86 shuffle instructions. Once
22092 /// they have been fully optimized, this will recursively consider all chains
22093 /// of single-use shuffle instructions, build a generic model of the cumulative
22094 /// shuffle operation, and check for simpler instructions which implement this
22095 /// operation. We use this primarily for two purposes:
22097 /// 1) Collapse generic shuffles to specialized single instructions when
22098 /// equivalent. In most cases, this is just an encoding size win, but
22099 /// sometimes we will collapse multiple generic shuffles into a single
22100 /// special-purpose shuffle.
22101 /// 2) Look for sequences of shuffle instructions with 3 or more total
22102 /// instructions, and replace them with the slightly more expensive SSSE3
22103 /// PSHUFB instruction if available. We do this as the last combining step
22104 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22105 /// a suitable short sequence of other instructions. The PHUFB will either
22106 /// use a register or have to read from memory and so is slightly (but only
22107 /// slightly) more expensive than the other shuffle instructions.
22109 /// Because this is inherently a quadratic operation (for each shuffle in
22110 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22111 /// This should never be an issue in practice as the shuffle lowering doesn't
22112 /// produce sequences of more than 8 instructions.
22114 /// FIXME: We will currently miss some cases where the redundant shuffling
22115 /// would simplify under the threshold for PSHUFB formation because of
22116 /// combine-ordering. To fix this, we should do the redundant instruction
22117 /// combining in this recursive walk.
22118 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22119 ArrayRef<int> RootMask,
22120 int Depth, bool HasPSHUFB,
22122 TargetLowering::DAGCombinerInfo &DCI,
22123 const X86Subtarget *Subtarget) {
22124 // Bound the depth of our recursive combine because this is ultimately
22125 // quadratic in nature.
22129 // Directly rip through bitcasts to find the underlying operand.
22130 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22131 Op = Op.getOperand(0);
22133 MVT VT = Op.getSimpleValueType();
22134 if (!VT.isVector())
22135 return false; // Bail if we hit a non-vector.
22137 assert(Root.getSimpleValueType().isVector() &&
22138 "Shuffles operate on vector types!");
22139 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22140 "Can only combine shuffles of the same vector register size.");
22142 if (!isTargetShuffle(Op.getOpcode()))
22144 SmallVector<int, 16> OpMask;
22146 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22147 // We only can combine unary shuffles which we can decode the mask for.
22148 if (!HaveMask || !IsUnary)
22151 assert(VT.getVectorNumElements() == OpMask.size() &&
22152 "Different mask size from vector size!");
22153 assert(((RootMask.size() > OpMask.size() &&
22154 RootMask.size() % OpMask.size() == 0) ||
22155 (OpMask.size() > RootMask.size() &&
22156 OpMask.size() % RootMask.size() == 0) ||
22157 OpMask.size() == RootMask.size()) &&
22158 "The smaller number of elements must divide the larger.");
22159 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22160 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22161 assert(((RootRatio == 1 && OpRatio == 1) ||
22162 (RootRatio == 1) != (OpRatio == 1)) &&
22163 "Must not have a ratio for both incoming and op masks!");
22165 SmallVector<int, 16> Mask;
22166 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22168 // Merge this shuffle operation's mask into our accumulated mask. Note that
22169 // this shuffle's mask will be the first applied to the input, followed by the
22170 // root mask to get us all the way to the root value arrangement. The reason
22171 // for this order is that we are recursing up the operation chain.
22172 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22173 int RootIdx = i / RootRatio;
22174 if (RootMask[RootIdx] < 0) {
22175 // This is a zero or undef lane, we're done.
22176 Mask.push_back(RootMask[RootIdx]);
22180 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22181 int OpIdx = RootMaskedIdx / OpRatio;
22182 if (OpMask[OpIdx] < 0) {
22183 // The incoming lanes are zero or undef, it doesn't matter which ones we
22185 Mask.push_back(OpMask[OpIdx]);
22189 // Ok, we have non-zero lanes, map them through.
22190 Mask.push_back(OpMask[OpIdx] * OpRatio +
22191 RootMaskedIdx % OpRatio);
22194 // See if we can recurse into the operand to combine more things.
22195 switch (Op.getOpcode()) {
22196 case X86ISD::PSHUFB:
22198 case X86ISD::PSHUFD:
22199 case X86ISD::PSHUFHW:
22200 case X86ISD::PSHUFLW:
22201 if (Op.getOperand(0).hasOneUse() &&
22202 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22203 HasPSHUFB, DAG, DCI, Subtarget))
22207 case X86ISD::UNPCKL:
22208 case X86ISD::UNPCKH:
22209 assert(Op.getOperand(0) == Op.getOperand(1) &&
22210 "We only combine unary shuffles!");
22211 // We can't check for single use, we have to check that this shuffle is the
22213 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22214 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22215 HasPSHUFB, DAG, DCI, Subtarget))
22220 // Minor canonicalization of the accumulated shuffle mask to make it easier
22221 // to match below. All this does is detect masks with squential pairs of
22222 // elements, and shrink them to the half-width mask. It does this in a loop
22223 // so it will reduce the size of the mask to the minimal width mask which
22224 // performs an equivalent shuffle.
22225 SmallVector<int, 16> WidenedMask;
22226 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22227 Mask = std::move(WidenedMask);
22228 WidenedMask.clear();
22231 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22235 /// \brief Get the PSHUF-style mask from PSHUF node.
22237 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22238 /// PSHUF-style masks that can be reused with such instructions.
22239 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22240 MVT VT = N.getSimpleValueType();
22241 SmallVector<int, 4> Mask;
22243 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22247 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22248 // matter. Check that the upper masks are repeats and remove them.
22249 if (VT.getSizeInBits() > 128) {
22250 int LaneElts = 128 / VT.getScalarSizeInBits();
22252 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22253 for (int j = 0; j < LaneElts; ++j)
22254 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22255 "Mask doesn't repeat in high 128-bit lanes!");
22257 Mask.resize(LaneElts);
22260 switch (N.getOpcode()) {
22261 case X86ISD::PSHUFD:
22263 case X86ISD::PSHUFLW:
22266 case X86ISD::PSHUFHW:
22267 Mask.erase(Mask.begin(), Mask.begin() + 4);
22268 for (int &M : Mask)
22272 llvm_unreachable("No valid shuffle instruction found!");
22276 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22278 /// We walk up the chain and look for a combinable shuffle, skipping over
22279 /// shuffles that we could hoist this shuffle's transformation past without
22280 /// altering anything.
22282 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22284 TargetLowering::DAGCombinerInfo &DCI) {
22285 assert(N.getOpcode() == X86ISD::PSHUFD &&
22286 "Called with something other than an x86 128-bit half shuffle!");
22289 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22290 // of the shuffles in the chain so that we can form a fresh chain to replace
22292 SmallVector<SDValue, 8> Chain;
22293 SDValue V = N.getOperand(0);
22294 for (; V.hasOneUse(); V = V.getOperand(0)) {
22295 switch (V.getOpcode()) {
22297 return SDValue(); // Nothing combined!
22300 // Skip bitcasts as we always know the type for the target specific
22304 case X86ISD::PSHUFD:
22305 // Found another dword shuffle.
22308 case X86ISD::PSHUFLW:
22309 // Check that the low words (being shuffled) are the identity in the
22310 // dword shuffle, and the high words are self-contained.
22311 if (Mask[0] != 0 || Mask[1] != 1 ||
22312 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22315 Chain.push_back(V);
22318 case X86ISD::PSHUFHW:
22319 // Check that the high words (being shuffled) are the identity in the
22320 // dword shuffle, and the low words are self-contained.
22321 if (Mask[2] != 2 || Mask[3] != 3 ||
22322 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22325 Chain.push_back(V);
22328 case X86ISD::UNPCKL:
22329 case X86ISD::UNPCKH:
22330 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22331 // shuffle into a preceding word shuffle.
22332 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22333 V.getSimpleValueType().getScalarType() != MVT::i16)
22336 // Search for a half-shuffle which we can combine with.
22337 unsigned CombineOp =
22338 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22339 if (V.getOperand(0) != V.getOperand(1) ||
22340 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22342 Chain.push_back(V);
22343 V = V.getOperand(0);
22345 switch (V.getOpcode()) {
22347 return SDValue(); // Nothing to combine.
22349 case X86ISD::PSHUFLW:
22350 case X86ISD::PSHUFHW:
22351 if (V.getOpcode() == CombineOp)
22354 Chain.push_back(V);
22358 V = V.getOperand(0);
22362 } while (V.hasOneUse());
22365 // Break out of the loop if we break out of the switch.
22369 if (!V.hasOneUse())
22370 // We fell out of the loop without finding a viable combining instruction.
22373 // Merge this node's mask and our incoming mask.
22374 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22375 for (int &M : Mask)
22377 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22378 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22380 // Rebuild the chain around this new shuffle.
22381 while (!Chain.empty()) {
22382 SDValue W = Chain.pop_back_val();
22384 if (V.getValueType() != W.getOperand(0).getValueType())
22385 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22387 switch (W.getOpcode()) {
22389 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22391 case X86ISD::UNPCKL:
22392 case X86ISD::UNPCKH:
22393 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22396 case X86ISD::PSHUFD:
22397 case X86ISD::PSHUFLW:
22398 case X86ISD::PSHUFHW:
22399 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22403 if (V.getValueType() != N.getValueType())
22404 V = DAG.getBitcast(N.getValueType(), V);
22406 // Return the new chain to replace N.
22410 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22413 /// We walk up the chain, skipping shuffles of the other half and looking
22414 /// through shuffles which switch halves trying to find a shuffle of the same
22415 /// pair of dwords.
22416 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22418 TargetLowering::DAGCombinerInfo &DCI) {
22420 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22421 "Called with something other than an x86 128-bit half shuffle!");
22423 unsigned CombineOpcode = N.getOpcode();
22425 // Walk up a single-use chain looking for a combinable shuffle.
22426 SDValue V = N.getOperand(0);
22427 for (; V.hasOneUse(); V = V.getOperand(0)) {
22428 switch (V.getOpcode()) {
22430 return false; // Nothing combined!
22433 // Skip bitcasts as we always know the type for the target specific
22437 case X86ISD::PSHUFLW:
22438 case X86ISD::PSHUFHW:
22439 if (V.getOpcode() == CombineOpcode)
22442 // Other-half shuffles are no-ops.
22445 // Break out of the loop if we break out of the switch.
22449 if (!V.hasOneUse())
22450 // We fell out of the loop without finding a viable combining instruction.
22453 // Combine away the bottom node as its shuffle will be accumulated into
22454 // a preceding shuffle.
22455 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22457 // Record the old value.
22460 // Merge this node's mask and our incoming mask (adjusted to account for all
22461 // the pshufd instructions encountered).
22462 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22463 for (int &M : Mask)
22465 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22466 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22468 // Check that the shuffles didn't cancel each other out. If not, we need to
22469 // combine to the new one.
22471 // Replace the combinable shuffle with the combined one, updating all users
22472 // so that we re-evaluate the chain here.
22473 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22478 /// \brief Try to combine x86 target specific shuffles.
22479 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22480 TargetLowering::DAGCombinerInfo &DCI,
22481 const X86Subtarget *Subtarget) {
22483 MVT VT = N.getSimpleValueType();
22484 SmallVector<int, 4> Mask;
22486 switch (N.getOpcode()) {
22487 case X86ISD::PSHUFD:
22488 case X86ISD::PSHUFLW:
22489 case X86ISD::PSHUFHW:
22490 Mask = getPSHUFShuffleMask(N);
22491 assert(Mask.size() == 4);
22497 // Nuke no-op shuffles that show up after combining.
22498 if (isNoopShuffleMask(Mask))
22499 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22501 // Look for simplifications involving one or two shuffle instructions.
22502 SDValue V = N.getOperand(0);
22503 switch (N.getOpcode()) {
22506 case X86ISD::PSHUFLW:
22507 case X86ISD::PSHUFHW:
22508 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22510 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22511 return SDValue(); // We combined away this shuffle, so we're done.
22513 // See if this reduces to a PSHUFD which is no more expensive and can
22514 // combine with more operations. Note that it has to at least flip the
22515 // dwords as otherwise it would have been removed as a no-op.
22516 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22517 int DMask[] = {0, 1, 2, 3};
22518 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22519 DMask[DOffset + 0] = DOffset + 1;
22520 DMask[DOffset + 1] = DOffset + 0;
22521 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22522 V = DAG.getBitcast(DVT, V);
22523 DCI.AddToWorklist(V.getNode());
22524 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22525 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22526 DCI.AddToWorklist(V.getNode());
22527 return DAG.getBitcast(VT, V);
22530 // Look for shuffle patterns which can be implemented as a single unpack.
22531 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22532 // only works when we have a PSHUFD followed by two half-shuffles.
22533 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22534 (V.getOpcode() == X86ISD::PSHUFLW ||
22535 V.getOpcode() == X86ISD::PSHUFHW) &&
22536 V.getOpcode() != N.getOpcode() &&
22538 SDValue D = V.getOperand(0);
22539 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22540 D = D.getOperand(0);
22541 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22542 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22543 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22544 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22545 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22547 for (int i = 0; i < 4; ++i) {
22548 WordMask[i + NOffset] = Mask[i] + NOffset;
22549 WordMask[i + VOffset] = VMask[i] + VOffset;
22551 // Map the word mask through the DWord mask.
22553 for (int i = 0; i < 8; ++i)
22554 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22555 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22556 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22557 // We can replace all three shuffles with an unpack.
22558 V = DAG.getBitcast(VT, D.getOperand(0));
22559 DCI.AddToWorklist(V.getNode());
22560 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22569 case X86ISD::PSHUFD:
22570 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22579 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22581 /// We combine this directly on the abstract vector shuffle nodes so it is
22582 /// easier to generically match. We also insert dummy vector shuffle nodes for
22583 /// the operands which explicitly discard the lanes which are unused by this
22584 /// operation to try to flow through the rest of the combiner the fact that
22585 /// they're unused.
22586 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22588 EVT VT = N->getValueType(0);
22590 // We only handle target-independent shuffles.
22591 // FIXME: It would be easy and harmless to use the target shuffle mask
22592 // extraction tool to support more.
22593 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22596 auto *SVN = cast<ShuffleVectorSDNode>(N);
22597 ArrayRef<int> Mask = SVN->getMask();
22598 SDValue V1 = N->getOperand(0);
22599 SDValue V2 = N->getOperand(1);
22601 // We require the first shuffle operand to be the SUB node, and the second to
22602 // be the ADD node.
22603 // FIXME: We should support the commuted patterns.
22604 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22607 // If there are other uses of these operations we can't fold them.
22608 if (!V1->hasOneUse() || !V2->hasOneUse())
22611 // Ensure that both operations have the same operands. Note that we can
22612 // commute the FADD operands.
22613 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22614 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22615 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22618 // We're looking for blends between FADD and FSUB nodes. We insist on these
22619 // nodes being lined up in a specific expected pattern.
22620 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22621 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22622 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22625 // Only specific types are legal at this point, assert so we notice if and
22626 // when these change.
22627 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22628 VT == MVT::v4f64) &&
22629 "Unknown vector type encountered!");
22631 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22634 /// PerformShuffleCombine - Performs several different shuffle combines.
22635 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22636 TargetLowering::DAGCombinerInfo &DCI,
22637 const X86Subtarget *Subtarget) {
22639 SDValue N0 = N->getOperand(0);
22640 SDValue N1 = N->getOperand(1);
22641 EVT VT = N->getValueType(0);
22643 // Don't create instructions with illegal types after legalize types has run.
22644 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22645 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22648 // If we have legalized the vector types, look for blends of FADD and FSUB
22649 // nodes that we can fuse into an ADDSUB node.
22650 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22651 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22654 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22655 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22656 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22657 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22659 // During Type Legalization, when promoting illegal vector types,
22660 // the backend might introduce new shuffle dag nodes and bitcasts.
22662 // This code performs the following transformation:
22663 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22664 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22666 // We do this only if both the bitcast and the BINOP dag nodes have
22667 // one use. Also, perform this transformation only if the new binary
22668 // operation is legal. This is to avoid introducing dag nodes that
22669 // potentially need to be further expanded (or custom lowered) into a
22670 // less optimal sequence of dag nodes.
22671 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22672 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22673 N0.getOpcode() == ISD::BITCAST) {
22674 SDValue BC0 = N0.getOperand(0);
22675 EVT SVT = BC0.getValueType();
22676 unsigned Opcode = BC0.getOpcode();
22677 unsigned NumElts = VT.getVectorNumElements();
22679 if (BC0.hasOneUse() && SVT.isVector() &&
22680 SVT.getVectorNumElements() * 2 == NumElts &&
22681 TLI.isOperationLegal(Opcode, VT)) {
22682 bool CanFold = false;
22694 unsigned SVTNumElts = SVT.getVectorNumElements();
22695 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22696 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22697 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22698 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22699 CanFold = SVOp->getMaskElt(i) < 0;
22702 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22703 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22704 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22705 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22710 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22711 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22712 // consecutive, non-overlapping, and in the right order.
22713 SmallVector<SDValue, 16> Elts;
22714 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22715 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22717 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22720 if (isTargetShuffle(N->getOpcode())) {
22722 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22723 if (Shuffle.getNode())
22726 // Try recursively combining arbitrary sequences of x86 shuffle
22727 // instructions into higher-order shuffles. We do this after combining
22728 // specific PSHUF instruction sequences into their minimal form so that we
22729 // can evaluate how many specialized shuffle instructions are involved in
22730 // a particular chain.
22731 SmallVector<int, 1> NonceMask; // Just a placeholder.
22732 NonceMask.push_back(0);
22733 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22734 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22736 return SDValue(); // This routine will use CombineTo to replace N.
22742 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22743 /// specific shuffle of a load can be folded into a single element load.
22744 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22745 /// shuffles have been custom lowered so we need to handle those here.
22746 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22747 TargetLowering::DAGCombinerInfo &DCI) {
22748 if (DCI.isBeforeLegalizeOps())
22751 SDValue InVec = N->getOperand(0);
22752 SDValue EltNo = N->getOperand(1);
22754 if (!isa<ConstantSDNode>(EltNo))
22757 EVT OriginalVT = InVec.getValueType();
22759 if (InVec.getOpcode() == ISD::BITCAST) {
22760 // Don't duplicate a load with other uses.
22761 if (!InVec.hasOneUse())
22763 EVT BCVT = InVec.getOperand(0).getValueType();
22764 if (!BCVT.isVector() ||
22765 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22767 InVec = InVec.getOperand(0);
22770 EVT CurrentVT = InVec.getValueType();
22772 if (!isTargetShuffle(InVec.getOpcode()))
22775 // Don't duplicate a load with other uses.
22776 if (!InVec.hasOneUse())
22779 SmallVector<int, 16> ShuffleMask;
22781 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22782 ShuffleMask, UnaryShuffle))
22785 // Select the input vector, guarding against out of range extract vector.
22786 unsigned NumElems = CurrentVT.getVectorNumElements();
22787 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22788 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22789 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22790 : InVec.getOperand(1);
22792 // If inputs to shuffle are the same for both ops, then allow 2 uses
22793 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22794 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22796 if (LdNode.getOpcode() == ISD::BITCAST) {
22797 // Don't duplicate a load with other uses.
22798 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22801 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22802 LdNode = LdNode.getOperand(0);
22805 if (!ISD::isNormalLoad(LdNode.getNode()))
22808 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22810 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22813 EVT EltVT = N->getValueType(0);
22814 // If there's a bitcast before the shuffle, check if the load type and
22815 // alignment is valid.
22816 unsigned Align = LN0->getAlignment();
22817 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22818 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22819 EltVT.getTypeForEVT(*DAG.getContext()));
22821 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22824 // All checks match so transform back to vector_shuffle so that DAG combiner
22825 // can finish the job
22828 // Create shuffle node taking into account the case that its a unary shuffle
22829 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22830 : InVec.getOperand(1);
22831 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22832 InVec.getOperand(0), Shuffle,
22834 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22835 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22839 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22840 /// special and don't usually play with other vector types, it's better to
22841 /// handle them early to be sure we emit efficient code by avoiding
22842 /// store-load conversions.
22843 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22844 if (N->getValueType(0) != MVT::x86mmx ||
22845 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22846 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22849 SDValue V = N->getOperand(0);
22850 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22851 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22852 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22853 N->getValueType(0), V.getOperand(0));
22858 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22859 /// generation and convert it from being a bunch of shuffles and extracts
22860 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22861 /// storing the value and loading scalars back, while for x64 we should
22862 /// use 64-bit extracts and shifts.
22863 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22864 TargetLowering::DAGCombinerInfo &DCI) {
22865 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22868 SDValue InputVector = N->getOperand(0);
22869 SDLoc dl(InputVector);
22870 // Detect mmx to i32 conversion through a v2i32 elt extract.
22871 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22872 N->getValueType(0) == MVT::i32 &&
22873 InputVector.getValueType() == MVT::v2i32) {
22875 // The bitcast source is a direct mmx result.
22876 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22877 if (MMXSrc.getValueType() == MVT::x86mmx)
22878 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22879 N->getValueType(0),
22880 InputVector.getNode()->getOperand(0));
22882 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22883 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22884 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22885 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22886 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22887 MMXSrcOp.getValueType() == MVT::v1i64 &&
22888 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22889 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22890 N->getValueType(0),
22891 MMXSrcOp.getOperand(0));
22894 EVT VT = N->getValueType(0);
22896 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22897 InputVector.getOpcode() == ISD::BITCAST &&
22898 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22899 uint64_t ExtractedElt =
22900 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22901 uint64_t InputValue =
22902 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22903 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22904 return DAG.getConstant(Res, dl, MVT::i1);
22906 // Only operate on vectors of 4 elements, where the alternative shuffling
22907 // gets to be more expensive.
22908 if (InputVector.getValueType() != MVT::v4i32)
22911 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22912 // single use which is a sign-extend or zero-extend, and all elements are
22914 SmallVector<SDNode *, 4> Uses;
22915 unsigned ExtractedElements = 0;
22916 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22917 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22918 if (UI.getUse().getResNo() != InputVector.getResNo())
22921 SDNode *Extract = *UI;
22922 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22925 if (Extract->getValueType(0) != MVT::i32)
22927 if (!Extract->hasOneUse())
22929 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22930 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22932 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22935 // Record which element was extracted.
22936 ExtractedElements |=
22937 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22939 Uses.push_back(Extract);
22942 // If not all the elements were used, this may not be worthwhile.
22943 if (ExtractedElements != 15)
22946 // Ok, we've now decided to do the transformation.
22947 // If 64-bit shifts are legal, use the extract-shift sequence,
22948 // otherwise bounce the vector off the cache.
22949 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22952 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22953 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22954 auto &DL = DAG.getDataLayout();
22955 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22956 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22957 DAG.getConstant(0, dl, VecIdxTy));
22958 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22959 DAG.getConstant(1, dl, VecIdxTy));
22961 SDValue ShAmt = DAG.getConstant(
22962 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22963 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22964 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22965 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22966 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22967 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22968 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22970 // Store the value to a temporary stack slot.
22971 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22972 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22973 MachinePointerInfo(), false, false, 0);
22975 EVT ElementType = InputVector.getValueType().getVectorElementType();
22976 unsigned EltSize = ElementType.getSizeInBits() / 8;
22978 // Replace each use (extract) with a load of the appropriate element.
22979 for (unsigned i = 0; i < 4; ++i) {
22980 uint64_t Offset = EltSize * i;
22981 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
22982 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
22984 SDValue ScalarAddr =
22985 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
22987 // Load the scalar.
22988 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22989 ScalarAddr, MachinePointerInfo(),
22990 false, false, false, 0);
22995 // Replace the extracts
22996 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22997 UE = Uses.end(); UI != UE; ++UI) {
22998 SDNode *Extract = *UI;
23000 SDValue Idx = Extract->getOperand(1);
23001 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23002 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23005 // The replacement was made in place; don't return anything.
23010 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23011 const X86Subtarget *Subtarget) {
23013 SDValue Cond = N->getOperand(0);
23014 SDValue LHS = N->getOperand(1);
23015 SDValue RHS = N->getOperand(2);
23017 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23018 SDValue CondSrc = Cond->getOperand(0);
23019 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23020 Cond = CondSrc->getOperand(0);
23023 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23026 // A vselect where all conditions and data are constants can be optimized into
23027 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23028 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23029 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23032 unsigned MaskValue = 0;
23033 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23036 MVT VT = N->getSimpleValueType(0);
23037 unsigned NumElems = VT.getVectorNumElements();
23038 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23039 for (unsigned i = 0; i < NumElems; ++i) {
23040 // Be sure we emit undef where we can.
23041 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23042 ShuffleMask[i] = -1;
23044 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23048 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23050 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23053 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23055 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23056 TargetLowering::DAGCombinerInfo &DCI,
23057 const X86Subtarget *Subtarget) {
23059 SDValue Cond = N->getOperand(0);
23060 // Get the LHS/RHS of the select.
23061 SDValue LHS = N->getOperand(1);
23062 SDValue RHS = N->getOperand(2);
23063 EVT VT = LHS.getValueType();
23064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23066 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23067 // instructions match the semantics of the common C idiom x<y?x:y but not
23068 // x<=y?x:y, because of how they handle negative zero (which can be
23069 // ignored in unsafe-math mode).
23070 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23071 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23072 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23073 (Subtarget->hasSSE2() ||
23074 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23075 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23077 unsigned Opcode = 0;
23078 // Check for x CC y ? x : y.
23079 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23080 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23084 // Converting this to a min would handle NaNs incorrectly, and swapping
23085 // the operands would cause it to handle comparisons between positive
23086 // and negative zero incorrectly.
23087 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23088 if (!DAG.getTarget().Options.UnsafeFPMath &&
23089 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23091 std::swap(LHS, RHS);
23093 Opcode = X86ISD::FMIN;
23096 // Converting this to a min would handle comparisons between positive
23097 // and negative zero incorrectly.
23098 if (!DAG.getTarget().Options.UnsafeFPMath &&
23099 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23101 Opcode = X86ISD::FMIN;
23104 // Converting this to a min would handle both negative zeros and NaNs
23105 // incorrectly, but we can swap the operands to fix both.
23106 std::swap(LHS, RHS);
23110 Opcode = X86ISD::FMIN;
23114 // Converting this to a max would handle comparisons between positive
23115 // and negative zero incorrectly.
23116 if (!DAG.getTarget().Options.UnsafeFPMath &&
23117 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23119 Opcode = X86ISD::FMAX;
23122 // Converting this to a max would handle NaNs incorrectly, and swapping
23123 // the operands would cause it to handle comparisons between positive
23124 // and negative zero incorrectly.
23125 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23126 if (!DAG.getTarget().Options.UnsafeFPMath &&
23127 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23129 std::swap(LHS, RHS);
23131 Opcode = X86ISD::FMAX;
23134 // Converting this to a max would handle both negative zeros and NaNs
23135 // incorrectly, but we can swap the operands to fix both.
23136 std::swap(LHS, RHS);
23140 Opcode = X86ISD::FMAX;
23143 // Check for x CC y ? y : x -- a min/max with reversed arms.
23144 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23145 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23149 // Converting this to a min would handle comparisons between positive
23150 // and negative zero incorrectly, and swapping the operands would
23151 // cause it to handle NaNs incorrectly.
23152 if (!DAG.getTarget().Options.UnsafeFPMath &&
23153 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23154 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23156 std::swap(LHS, RHS);
23158 Opcode = X86ISD::FMIN;
23161 // Converting this to a min would handle NaNs incorrectly.
23162 if (!DAG.getTarget().Options.UnsafeFPMath &&
23163 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23165 Opcode = X86ISD::FMIN;
23168 // Converting this to a min would handle both negative zeros and NaNs
23169 // incorrectly, but we can swap the operands to fix both.
23170 std::swap(LHS, RHS);
23174 Opcode = X86ISD::FMIN;
23178 // Converting this to a max would handle NaNs incorrectly.
23179 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23181 Opcode = X86ISD::FMAX;
23184 // Converting this to a max would handle comparisons between positive
23185 // and negative zero incorrectly, and swapping the operands would
23186 // cause it to handle NaNs incorrectly.
23187 if (!DAG.getTarget().Options.UnsafeFPMath &&
23188 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23189 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23191 std::swap(LHS, RHS);
23193 Opcode = X86ISD::FMAX;
23196 // Converting this to a max would handle both negative zeros and NaNs
23197 // incorrectly, but we can swap the operands to fix both.
23198 std::swap(LHS, RHS);
23202 Opcode = X86ISD::FMAX;
23208 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23211 EVT CondVT = Cond.getValueType();
23212 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23213 CondVT.getVectorElementType() == MVT::i1) {
23214 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23215 // lowering on KNL. In this case we convert it to
23216 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23217 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23218 // Since SKX these selects have a proper lowering.
23219 EVT OpVT = LHS.getValueType();
23220 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23221 (OpVT.getVectorElementType() == MVT::i8 ||
23222 OpVT.getVectorElementType() == MVT::i16) &&
23223 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23224 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23225 DCI.AddToWorklist(Cond.getNode());
23226 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23229 // If this is a select between two integer constants, try to do some
23231 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23232 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23233 // Don't do this for crazy integer types.
23234 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23235 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23236 // so that TrueC (the true value) is larger than FalseC.
23237 bool NeedsCondInvert = false;
23239 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23240 // Efficiently invertible.
23241 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23242 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23243 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23244 NeedsCondInvert = true;
23245 std::swap(TrueC, FalseC);
23248 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23249 if (FalseC->getAPIntValue() == 0 &&
23250 TrueC->getAPIntValue().isPowerOf2()) {
23251 if (NeedsCondInvert) // Invert the condition if needed.
23252 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23253 DAG.getConstant(1, DL, Cond.getValueType()));
23255 // Zero extend the condition if needed.
23256 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23258 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23259 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23260 DAG.getConstant(ShAmt, DL, MVT::i8));
23263 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23264 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23265 if (NeedsCondInvert) // Invert the condition if needed.
23266 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23267 DAG.getConstant(1, DL, Cond.getValueType()));
23269 // Zero extend the condition if needed.
23270 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23271 FalseC->getValueType(0), Cond);
23272 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23273 SDValue(FalseC, 0));
23276 // Optimize cases that will turn into an LEA instruction. This requires
23277 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23278 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23279 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23280 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23282 bool isFastMultiplier = false;
23284 switch ((unsigned char)Diff) {
23286 case 1: // result = add base, cond
23287 case 2: // result = lea base( , cond*2)
23288 case 3: // result = lea base(cond, cond*2)
23289 case 4: // result = lea base( , cond*4)
23290 case 5: // result = lea base(cond, cond*4)
23291 case 8: // result = lea base( , cond*8)
23292 case 9: // result = lea base(cond, cond*8)
23293 isFastMultiplier = true;
23298 if (isFastMultiplier) {
23299 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23300 if (NeedsCondInvert) // Invert the condition if needed.
23301 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23302 DAG.getConstant(1, DL, Cond.getValueType()));
23304 // Zero extend the condition if needed.
23305 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23307 // Scale the condition by the difference.
23309 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23310 DAG.getConstant(Diff, DL,
23311 Cond.getValueType()));
23313 // Add the base if non-zero.
23314 if (FalseC->getAPIntValue() != 0)
23315 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23316 SDValue(FalseC, 0));
23323 // Canonicalize max and min:
23324 // (x > y) ? x : y -> (x >= y) ? x : y
23325 // (x < y) ? x : y -> (x <= y) ? x : y
23326 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23327 // the need for an extra compare
23328 // against zero. e.g.
23329 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23331 // testl %edi, %edi
23333 // cmovgl %edi, %eax
23337 // cmovsl %eax, %edi
23338 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23339 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23340 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23341 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23346 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23347 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23348 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23349 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23354 // Early exit check
23355 if (!TLI.isTypeLegal(VT))
23358 // Match VSELECTs into subs with unsigned saturation.
23359 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23360 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23361 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23362 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23363 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23365 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23366 // left side invert the predicate to simplify logic below.
23368 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23370 CC = ISD::getSetCCInverse(CC, true);
23371 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23375 if (Other.getNode() && Other->getNumOperands() == 2 &&
23376 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23377 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23378 SDValue CondRHS = Cond->getOperand(1);
23380 // Look for a general sub with unsigned saturation first.
23381 // x >= y ? x-y : 0 --> subus x, y
23382 // x > y ? x-y : 0 --> subus x, y
23383 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23384 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23385 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23387 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23388 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23389 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23390 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23391 // If the RHS is a constant we have to reverse the const
23392 // canonicalization.
23393 // x > C-1 ? x+-C : 0 --> subus x, C
23394 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23395 CondRHSConst->getAPIntValue() ==
23396 (-OpRHSConst->getAPIntValue() - 1))
23397 return DAG.getNode(
23398 X86ISD::SUBUS, DL, VT, OpLHS,
23399 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23401 // Another special case: If C was a sign bit, the sub has been
23402 // canonicalized into a xor.
23403 // FIXME: Would it be better to use computeKnownBits to determine
23404 // whether it's safe to decanonicalize the xor?
23405 // x s< 0 ? x^C : 0 --> subus x, C
23406 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23407 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23408 OpRHSConst->getAPIntValue().isSignBit())
23409 // Note that we have to rebuild the RHS constant here to ensure we
23410 // don't rely on particular values of undef lanes.
23411 return DAG.getNode(
23412 X86ISD::SUBUS, DL, VT, OpLHS,
23413 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23418 // Simplify vector selection if condition value type matches vselect
23420 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23421 assert(Cond.getValueType().isVector() &&
23422 "vector select expects a vector selector!");
23424 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23425 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23427 // Try invert the condition if true value is not all 1s and false value
23429 if (!TValIsAllOnes && !FValIsAllZeros &&
23430 // Check if the selector will be produced by CMPP*/PCMP*
23431 Cond.getOpcode() == ISD::SETCC &&
23432 // Check if SETCC has already been promoted
23433 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23435 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23436 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23438 if (TValIsAllZeros || FValIsAllOnes) {
23439 SDValue CC = Cond.getOperand(2);
23440 ISD::CondCode NewCC =
23441 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23442 Cond.getOperand(0).getValueType().isInteger());
23443 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23444 std::swap(LHS, RHS);
23445 TValIsAllOnes = FValIsAllOnes;
23446 FValIsAllZeros = TValIsAllZeros;
23450 if (TValIsAllOnes || FValIsAllZeros) {
23453 if (TValIsAllOnes && FValIsAllZeros)
23455 else if (TValIsAllOnes)
23457 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23458 else if (FValIsAllZeros)
23459 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23460 DAG.getBitcast(CondVT, LHS));
23462 return DAG.getBitcast(VT, Ret);
23466 // We should generate an X86ISD::BLENDI from a vselect if its argument
23467 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23468 // constants. This specific pattern gets generated when we split a
23469 // selector for a 512 bit vector in a machine without AVX512 (but with
23470 // 256-bit vectors), during legalization:
23472 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23474 // Iff we find this pattern and the build_vectors are built from
23475 // constants, we translate the vselect into a shuffle_vector that we
23476 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23477 if ((N->getOpcode() == ISD::VSELECT ||
23478 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23479 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23480 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23481 if (Shuffle.getNode())
23485 // If this is a *dynamic* select (non-constant condition) and we can match
23486 // this node with one of the variable blend instructions, restructure the
23487 // condition so that the blends can use the high bit of each element and use
23488 // SimplifyDemandedBits to simplify the condition operand.
23489 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23490 !DCI.isBeforeLegalize() &&
23491 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23492 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23494 // Don't optimize vector selects that map to mask-registers.
23498 // We can only handle the cases where VSELECT is directly legal on the
23499 // subtarget. We custom lower VSELECT nodes with constant conditions and
23500 // this makes it hard to see whether a dynamic VSELECT will correctly
23501 // lower, so we both check the operation's status and explicitly handle the
23502 // cases where a *dynamic* blend will fail even though a constant-condition
23503 // blend could be custom lowered.
23504 // FIXME: We should find a better way to handle this class of problems.
23505 // Potentially, we should combine constant-condition vselect nodes
23506 // pre-legalization into shuffles and not mark as many types as custom
23508 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23510 // FIXME: We don't support i16-element blends currently. We could and
23511 // should support them by making *all* the bits in the condition be set
23512 // rather than just the high bit and using an i8-element blend.
23513 if (VT.getScalarType() == MVT::i16)
23515 // Dynamic blending was only available from SSE4.1 onward.
23516 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23518 // Byte blends are only available in AVX2
23519 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23520 !Subtarget->hasAVX2())
23523 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23524 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23526 APInt KnownZero, KnownOne;
23527 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23528 DCI.isBeforeLegalizeOps());
23529 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23530 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23532 // If we changed the computation somewhere in the DAG, this change
23533 // will affect all users of Cond.
23534 // Make sure it is fine and update all the nodes so that we do not
23535 // use the generic VSELECT anymore. Otherwise, we may perform
23536 // wrong optimizations as we messed up with the actual expectation
23537 // for the vector boolean values.
23538 if (Cond != TLO.Old) {
23539 // Check all uses of that condition operand to check whether it will be
23540 // consumed by non-BLEND instructions, which may depend on all bits are
23542 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23544 if (I->getOpcode() != ISD::VSELECT)
23545 // TODO: Add other opcodes eventually lowered into BLEND.
23548 // Update all the users of the condition, before committing the change,
23549 // so that the VSELECT optimizations that expect the correct vector
23550 // boolean value will not be triggered.
23551 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23553 DAG.ReplaceAllUsesOfValueWith(
23555 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23556 Cond, I->getOperand(1), I->getOperand(2)));
23557 DCI.CommitTargetLoweringOpt(TLO);
23560 // At this point, only Cond is changed. Change the condition
23561 // just for N to keep the opportunity to optimize all other
23562 // users their own way.
23563 DAG.ReplaceAllUsesOfValueWith(
23565 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23566 TLO.New, N->getOperand(1), N->getOperand(2)));
23574 // Check whether a boolean test is testing a boolean value generated by
23575 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23578 // Simplify the following patterns:
23579 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23580 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23581 // to (Op EFLAGS Cond)
23583 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23584 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23585 // to (Op EFLAGS !Cond)
23587 // where Op could be BRCOND or CMOV.
23589 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23590 // Quit if not CMP and SUB with its value result used.
23591 if (Cmp.getOpcode() != X86ISD::CMP &&
23592 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23595 // Quit if not used as a boolean value.
23596 if (CC != X86::COND_E && CC != X86::COND_NE)
23599 // Check CMP operands. One of them should be 0 or 1 and the other should be
23600 // an SetCC or extended from it.
23601 SDValue Op1 = Cmp.getOperand(0);
23602 SDValue Op2 = Cmp.getOperand(1);
23605 const ConstantSDNode* C = nullptr;
23606 bool needOppositeCond = (CC == X86::COND_E);
23607 bool checkAgainstTrue = false; // Is it a comparison against 1?
23609 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23611 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23613 else // Quit if all operands are not constants.
23616 if (C->getZExtValue() == 1) {
23617 needOppositeCond = !needOppositeCond;
23618 checkAgainstTrue = true;
23619 } else if (C->getZExtValue() != 0)
23620 // Quit if the constant is neither 0 or 1.
23623 bool truncatedToBoolWithAnd = false;
23624 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23625 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23626 SetCC.getOpcode() == ISD::TRUNCATE ||
23627 SetCC.getOpcode() == ISD::AND) {
23628 if (SetCC.getOpcode() == ISD::AND) {
23630 ConstantSDNode *CS;
23631 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23632 CS->getZExtValue() == 1)
23634 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23635 CS->getZExtValue() == 1)
23639 SetCC = SetCC.getOperand(OpIdx);
23640 truncatedToBoolWithAnd = true;
23642 SetCC = SetCC.getOperand(0);
23645 switch (SetCC.getOpcode()) {
23646 case X86ISD::SETCC_CARRY:
23647 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23648 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23649 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23650 // truncated to i1 using 'and'.
23651 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23653 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23654 "Invalid use of SETCC_CARRY!");
23656 case X86ISD::SETCC:
23657 // Set the condition code or opposite one if necessary.
23658 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23659 if (needOppositeCond)
23660 CC = X86::GetOppositeBranchCondition(CC);
23661 return SetCC.getOperand(1);
23662 case X86ISD::CMOV: {
23663 // Check whether false/true value has canonical one, i.e. 0 or 1.
23664 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23665 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23666 // Quit if true value is not a constant.
23669 // Quit if false value is not a constant.
23671 SDValue Op = SetCC.getOperand(0);
23672 // Skip 'zext' or 'trunc' node.
23673 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23674 Op.getOpcode() == ISD::TRUNCATE)
23675 Op = Op.getOperand(0);
23676 // A special case for rdrand/rdseed, where 0 is set if false cond is
23678 if ((Op.getOpcode() != X86ISD::RDRAND &&
23679 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23682 // Quit if false value is not the constant 0 or 1.
23683 bool FValIsFalse = true;
23684 if (FVal && FVal->getZExtValue() != 0) {
23685 if (FVal->getZExtValue() != 1)
23687 // If FVal is 1, opposite cond is needed.
23688 needOppositeCond = !needOppositeCond;
23689 FValIsFalse = false;
23691 // Quit if TVal is not the constant opposite of FVal.
23692 if (FValIsFalse && TVal->getZExtValue() != 1)
23694 if (!FValIsFalse && TVal->getZExtValue() != 0)
23696 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23697 if (needOppositeCond)
23698 CC = X86::GetOppositeBranchCondition(CC);
23699 return SetCC.getOperand(3);
23706 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23708 /// (X86or (X86setcc) (X86setcc))
23709 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23710 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23711 X86::CondCode &CC1, SDValue &Flags,
23713 if (Cond->getOpcode() == X86ISD::CMP) {
23714 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23715 if (!CondOp1C || !CondOp1C->isNullValue())
23718 Cond = Cond->getOperand(0);
23723 SDValue SetCC0, SetCC1;
23724 switch (Cond->getOpcode()) {
23725 default: return false;
23732 SetCC0 = Cond->getOperand(0);
23733 SetCC1 = Cond->getOperand(1);
23737 // Make sure we have SETCC nodes, using the same flags value.
23738 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23739 SetCC1.getOpcode() != X86ISD::SETCC ||
23740 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23743 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23744 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23745 Flags = SetCC0->getOperand(1);
23749 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23750 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23751 TargetLowering::DAGCombinerInfo &DCI,
23752 const X86Subtarget *Subtarget) {
23755 // If the flag operand isn't dead, don't touch this CMOV.
23756 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23759 SDValue FalseOp = N->getOperand(0);
23760 SDValue TrueOp = N->getOperand(1);
23761 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23762 SDValue Cond = N->getOperand(3);
23764 if (CC == X86::COND_E || CC == X86::COND_NE) {
23765 switch (Cond.getOpcode()) {
23769 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23770 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23771 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23777 Flags = checkBoolTestSetCCCombine(Cond, CC);
23778 if (Flags.getNode() &&
23779 // Extra check as FCMOV only supports a subset of X86 cond.
23780 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23781 SDValue Ops[] = { FalseOp, TrueOp,
23782 DAG.getConstant(CC, DL, MVT::i8), Flags };
23783 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23786 // If this is a select between two integer constants, try to do some
23787 // optimizations. Note that the operands are ordered the opposite of SELECT
23789 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23790 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23791 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23792 // larger than FalseC (the false value).
23793 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23794 CC = X86::GetOppositeBranchCondition(CC);
23795 std::swap(TrueC, FalseC);
23796 std::swap(TrueOp, FalseOp);
23799 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23800 // This is efficient for any integer data type (including i8/i16) and
23802 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23803 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23804 DAG.getConstant(CC, DL, MVT::i8), Cond);
23806 // Zero extend the condition if needed.
23807 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23809 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23810 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23811 DAG.getConstant(ShAmt, DL, MVT::i8));
23812 if (N->getNumValues() == 2) // Dead flag value?
23813 return DCI.CombineTo(N, Cond, SDValue());
23817 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23818 // for any integer data type, including i8/i16.
23819 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23820 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23821 DAG.getConstant(CC, DL, MVT::i8), Cond);
23823 // Zero extend the condition if needed.
23824 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23825 FalseC->getValueType(0), Cond);
23826 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23827 SDValue(FalseC, 0));
23829 if (N->getNumValues() == 2) // Dead flag value?
23830 return DCI.CombineTo(N, Cond, SDValue());
23834 // Optimize cases that will turn into an LEA instruction. This requires
23835 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23836 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23837 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23838 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23840 bool isFastMultiplier = false;
23842 switch ((unsigned char)Diff) {
23844 case 1: // result = add base, cond
23845 case 2: // result = lea base( , cond*2)
23846 case 3: // result = lea base(cond, cond*2)
23847 case 4: // result = lea base( , cond*4)
23848 case 5: // result = lea base(cond, cond*4)
23849 case 8: // result = lea base( , cond*8)
23850 case 9: // result = lea base(cond, cond*8)
23851 isFastMultiplier = true;
23856 if (isFastMultiplier) {
23857 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23858 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23859 DAG.getConstant(CC, DL, MVT::i8), Cond);
23860 // Zero extend the condition if needed.
23861 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23863 // Scale the condition by the difference.
23865 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23866 DAG.getConstant(Diff, DL, Cond.getValueType()));
23868 // Add the base if non-zero.
23869 if (FalseC->getAPIntValue() != 0)
23870 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23871 SDValue(FalseC, 0));
23872 if (N->getNumValues() == 2) // Dead flag value?
23873 return DCI.CombineTo(N, Cond, SDValue());
23880 // Handle these cases:
23881 // (select (x != c), e, c) -> select (x != c), e, x),
23882 // (select (x == c), c, e) -> select (x == c), x, e)
23883 // where the c is an integer constant, and the "select" is the combination
23884 // of CMOV and CMP.
23886 // The rationale for this change is that the conditional-move from a constant
23887 // needs two instructions, however, conditional-move from a register needs
23888 // only one instruction.
23890 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23891 // some instruction-combining opportunities. This opt needs to be
23892 // postponed as late as possible.
23894 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23895 // the DCI.xxxx conditions are provided to postpone the optimization as
23896 // late as possible.
23898 ConstantSDNode *CmpAgainst = nullptr;
23899 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23900 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23901 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23903 if (CC == X86::COND_NE &&
23904 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23905 CC = X86::GetOppositeBranchCondition(CC);
23906 std::swap(TrueOp, FalseOp);
23909 if (CC == X86::COND_E &&
23910 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23911 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23912 DAG.getConstant(CC, DL, MVT::i8), Cond };
23913 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23918 // Fold and/or of setcc's to double CMOV:
23919 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23920 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23922 // This combine lets us generate:
23923 // cmovcc1 (jcc1 if we don't have CMOV)
23929 // cmovne (jne if we don't have CMOV)
23930 // When we can't use the CMOV instruction, it might increase branch
23932 // When we can use CMOV, or when there is no mispredict, this improves
23933 // throughput and reduces register pressure.
23935 if (CC == X86::COND_NE) {
23937 X86::CondCode CC0, CC1;
23939 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23941 std::swap(FalseOp, TrueOp);
23942 CC0 = X86::GetOppositeBranchCondition(CC0);
23943 CC1 = X86::GetOppositeBranchCondition(CC1);
23946 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23948 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23949 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23950 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23951 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23959 /// PerformMulCombine - Optimize a single multiply with constant into two
23960 /// in order to implement it with two cheaper instructions, e.g.
23961 /// LEA + SHL, LEA + LEA.
23962 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23963 TargetLowering::DAGCombinerInfo &DCI) {
23964 // An imul is usually smaller than the alternative sequence.
23965 if (DAG.getMachineFunction().getFunction()->optForMinSize())
23968 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23971 EVT VT = N->getValueType(0);
23972 if (VT != MVT::i64 && VT != MVT::i32)
23975 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23978 uint64_t MulAmt = C->getZExtValue();
23979 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23982 uint64_t MulAmt1 = 0;
23983 uint64_t MulAmt2 = 0;
23984 if ((MulAmt % 9) == 0) {
23986 MulAmt2 = MulAmt / 9;
23987 } else if ((MulAmt % 5) == 0) {
23989 MulAmt2 = MulAmt / 5;
23990 } else if ((MulAmt % 3) == 0) {
23992 MulAmt2 = MulAmt / 3;
23995 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23998 if (isPowerOf2_64(MulAmt2) &&
23999 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24000 // If second multiplifer is pow2, issue it first. We want the multiply by
24001 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24003 std::swap(MulAmt1, MulAmt2);
24006 if (isPowerOf2_64(MulAmt1))
24007 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24008 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24010 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24011 DAG.getConstant(MulAmt1, DL, VT));
24013 if (isPowerOf2_64(MulAmt2))
24014 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24015 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24017 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24018 DAG.getConstant(MulAmt2, DL, VT));
24020 // Do not add new nodes to DAG combiner worklist.
24021 DCI.CombineTo(N, NewMul, false);
24026 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24027 SDValue N0 = N->getOperand(0);
24028 SDValue N1 = N->getOperand(1);
24029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24030 EVT VT = N0.getValueType();
24032 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24033 // since the result of setcc_c is all zero's or all ones.
24034 if (VT.isInteger() && !VT.isVector() &&
24035 N1C && N0.getOpcode() == ISD::AND &&
24036 N0.getOperand(1).getOpcode() == ISD::Constant) {
24037 SDValue N00 = N0.getOperand(0);
24038 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24039 APInt ShAmt = N1C->getAPIntValue();
24040 Mask = Mask.shl(ShAmt);
24041 bool MaskOK = false;
24042 // We can handle cases concerning bit-widening nodes containing setcc_c if
24043 // we carefully interrogate the mask to make sure we are semantics
24045 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24046 // of the underlying setcc_c operation if the setcc_c was zero extended.
24047 // Consider the following example:
24048 // zext(setcc_c) -> i32 0x0000FFFF
24049 // c1 -> i32 0x0000FFFF
24050 // c2 -> i32 0x00000001
24051 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24052 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24053 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24055 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24056 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24058 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24059 N00.getOpcode() == ISD::ANY_EXTEND) &&
24060 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24061 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24063 if (MaskOK && Mask != 0) {
24065 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24069 // Hardware support for vector shifts is sparse which makes us scalarize the
24070 // vector operations in many cases. Also, on sandybridge ADD is faster than
24072 // (shl V, 1) -> add V,V
24073 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24074 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24075 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24076 // We shift all of the values by one. In many cases we do not have
24077 // hardware support for this operation. This is better expressed as an ADD
24079 if (N1SplatC->getAPIntValue() == 1)
24080 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24086 /// \brief Returns a vector of 0s if the node in input is a vector logical
24087 /// shift by a constant amount which is known to be bigger than or equal
24088 /// to the vector element size in bits.
24089 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24090 const X86Subtarget *Subtarget) {
24091 EVT VT = N->getValueType(0);
24093 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24094 (!Subtarget->hasInt256() ||
24095 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24098 SDValue Amt = N->getOperand(1);
24100 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24101 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24102 APInt ShiftAmt = AmtSplat->getAPIntValue();
24103 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24105 // SSE2/AVX2 logical shifts always return a vector of 0s
24106 // if the shift amount is bigger than or equal to
24107 // the element size. The constant shift amount will be
24108 // encoded as a 8-bit immediate.
24109 if (ShiftAmt.trunc(8).uge(MaxAmount))
24110 return getZeroVector(VT, Subtarget, DAG, DL);
24116 /// PerformShiftCombine - Combine shifts.
24117 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24118 TargetLowering::DAGCombinerInfo &DCI,
24119 const X86Subtarget *Subtarget) {
24120 if (N->getOpcode() == ISD::SHL)
24121 if (SDValue V = PerformSHLCombine(N, DAG))
24124 // Try to fold this logical shift into a zero vector.
24125 if (N->getOpcode() != ISD::SRA)
24126 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24132 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24133 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24134 // and friends. Likewise for OR -> CMPNEQSS.
24135 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24136 TargetLowering::DAGCombinerInfo &DCI,
24137 const X86Subtarget *Subtarget) {
24140 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24141 // we're requiring SSE2 for both.
24142 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24143 SDValue N0 = N->getOperand(0);
24144 SDValue N1 = N->getOperand(1);
24145 SDValue CMP0 = N0->getOperand(1);
24146 SDValue CMP1 = N1->getOperand(1);
24149 // The SETCCs should both refer to the same CMP.
24150 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24153 SDValue CMP00 = CMP0->getOperand(0);
24154 SDValue CMP01 = CMP0->getOperand(1);
24155 EVT VT = CMP00.getValueType();
24157 if (VT == MVT::f32 || VT == MVT::f64) {
24158 bool ExpectingFlags = false;
24159 // Check for any users that want flags:
24160 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24161 !ExpectingFlags && UI != UE; ++UI)
24162 switch (UI->getOpcode()) {
24167 ExpectingFlags = true;
24169 case ISD::CopyToReg:
24170 case ISD::SIGN_EXTEND:
24171 case ISD::ZERO_EXTEND:
24172 case ISD::ANY_EXTEND:
24176 if (!ExpectingFlags) {
24177 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24178 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24180 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24181 X86::CondCode tmp = cc0;
24186 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24187 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24188 // FIXME: need symbolic constants for these magic numbers.
24189 // See X86ATTInstPrinter.cpp:printSSECC().
24190 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24191 if (Subtarget->hasAVX512()) {
24192 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24194 DAG.getConstant(x86cc, DL, MVT::i8));
24195 if (N->getValueType(0) != MVT::i1)
24196 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24200 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24201 CMP00.getValueType(), CMP00, CMP01,
24202 DAG.getConstant(x86cc, DL,
24205 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24206 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24208 if (is64BitFP && !Subtarget->is64Bit()) {
24209 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24210 // 64-bit integer, since that's not a legal type. Since
24211 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24212 // bits, but can do this little dance to extract the lowest 32 bits
24213 // and work with those going forward.
24214 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24216 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24217 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24218 Vector32, DAG.getIntPtrConstant(0, DL));
24222 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24223 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24224 DAG.getConstant(1, DL, IntVT));
24225 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24227 return OneBitOfTruth;
24235 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24236 /// so it can be folded inside ANDNP.
24237 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24238 EVT VT = N->getValueType(0);
24240 // Match direct AllOnes for 128 and 256-bit vectors
24241 if (ISD::isBuildVectorAllOnes(N))
24244 // Look through a bit convert.
24245 if (N->getOpcode() == ISD::BITCAST)
24246 N = N->getOperand(0).getNode();
24248 // Sometimes the operand may come from a insert_subvector building a 256-bit
24250 if (VT.is256BitVector() &&
24251 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24252 SDValue V1 = N->getOperand(0);
24253 SDValue V2 = N->getOperand(1);
24255 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24256 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24257 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24258 ISD::isBuildVectorAllOnes(V2.getNode()))
24265 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24266 // register. In most cases we actually compare or select YMM-sized registers
24267 // and mixing the two types creates horrible code. This method optimizes
24268 // some of the transition sequences.
24269 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24270 TargetLowering::DAGCombinerInfo &DCI,
24271 const X86Subtarget *Subtarget) {
24272 EVT VT = N->getValueType(0);
24273 if (!VT.is256BitVector())
24276 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24277 N->getOpcode() == ISD::ZERO_EXTEND ||
24278 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24280 SDValue Narrow = N->getOperand(0);
24281 EVT NarrowVT = Narrow->getValueType(0);
24282 if (!NarrowVT.is128BitVector())
24285 if (Narrow->getOpcode() != ISD::XOR &&
24286 Narrow->getOpcode() != ISD::AND &&
24287 Narrow->getOpcode() != ISD::OR)
24290 SDValue N0 = Narrow->getOperand(0);
24291 SDValue N1 = Narrow->getOperand(1);
24294 // The Left side has to be a trunc.
24295 if (N0.getOpcode() != ISD::TRUNCATE)
24298 // The type of the truncated inputs.
24299 EVT WideVT = N0->getOperand(0)->getValueType(0);
24303 // The right side has to be a 'trunc' or a constant vector.
24304 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24305 ConstantSDNode *RHSConstSplat = nullptr;
24306 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24307 RHSConstSplat = RHSBV->getConstantSplatNode();
24308 if (!RHSTrunc && !RHSConstSplat)
24311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24313 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24316 // Set N0 and N1 to hold the inputs to the new wide operation.
24317 N0 = N0->getOperand(0);
24318 if (RHSConstSplat) {
24319 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24320 SDValue(RHSConstSplat, 0));
24321 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24322 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24323 } else if (RHSTrunc) {
24324 N1 = N1->getOperand(0);
24327 // Generate the wide operation.
24328 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24329 unsigned Opcode = N->getOpcode();
24331 case ISD::ANY_EXTEND:
24333 case ISD::ZERO_EXTEND: {
24334 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24335 APInt Mask = APInt::getAllOnesValue(InBits);
24336 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24337 return DAG.getNode(ISD::AND, DL, VT,
24338 Op, DAG.getConstant(Mask, DL, VT));
24340 case ISD::SIGN_EXTEND:
24341 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24342 Op, DAG.getValueType(NarrowVT));
24344 llvm_unreachable("Unexpected opcode");
24348 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24349 TargetLowering::DAGCombinerInfo &DCI,
24350 const X86Subtarget *Subtarget) {
24351 SDValue N0 = N->getOperand(0);
24352 SDValue N1 = N->getOperand(1);
24355 // A vector zext_in_reg may be represented as a shuffle,
24356 // feeding into a bitcast (this represents anyext) feeding into
24357 // an and with a mask.
24358 // We'd like to try to combine that into a shuffle with zero
24359 // plus a bitcast, removing the and.
24360 if (N0.getOpcode() != ISD::BITCAST ||
24361 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24364 // The other side of the AND should be a splat of 2^C, where C
24365 // is the number of bits in the source type.
24366 if (N1.getOpcode() == ISD::BITCAST)
24367 N1 = N1.getOperand(0);
24368 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24370 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24372 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24373 EVT SrcType = Shuffle->getValueType(0);
24375 // We expect a single-source shuffle
24376 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24379 unsigned SrcSize = SrcType.getScalarSizeInBits();
24381 APInt SplatValue, SplatUndef;
24382 unsigned SplatBitSize;
24384 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24385 SplatBitSize, HasAnyUndefs))
24388 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24389 // Make sure the splat matches the mask we expect
24390 if (SplatBitSize > ResSize ||
24391 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24394 // Make sure the input and output size make sense
24395 if (SrcSize >= ResSize || ResSize % SrcSize)
24398 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24399 // The number of u's between each two values depends on the ratio between
24400 // the source and dest type.
24401 unsigned ZextRatio = ResSize / SrcSize;
24402 bool IsZext = true;
24403 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24404 if (i % ZextRatio) {
24405 if (Shuffle->getMaskElt(i) > 0) {
24411 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24412 // Expected element number
24422 // Ok, perform the transformation - replace the shuffle with
24423 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24424 // (instead of undef) where the k elements come from the zero vector.
24425 SmallVector<int, 8> Mask;
24426 unsigned NumElems = SrcType.getVectorNumElements();
24427 for (unsigned i = 0; i < NumElems; ++i)
24429 Mask.push_back(NumElems);
24431 Mask.push_back(i / ZextRatio);
24433 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24434 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24435 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24438 /// If both input operands of a logic op are being cast from floating point
24439 /// types, try to convert this into a floating point logic node to avoid
24440 /// unnecessary moves from SSE to integer registers.
24441 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24442 const X86Subtarget *Subtarget) {
24443 unsigned FPOpcode = ISD::DELETED_NODE;
24444 if (N->getOpcode() == ISD::AND)
24445 FPOpcode = X86ISD::FAND;
24446 else if (N->getOpcode() == ISD::OR)
24447 FPOpcode = X86ISD::FOR;
24448 else if (N->getOpcode() == ISD::XOR)
24449 FPOpcode = X86ISD::FXOR;
24451 assert(FPOpcode != ISD::DELETED_NODE &&
24452 "Unexpected input node for FP logic conversion");
24454 EVT VT = N->getValueType(0);
24455 SDValue N0 = N->getOperand(0);
24456 SDValue N1 = N->getOperand(1);
24458 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24459 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24460 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24461 SDValue N00 = N0.getOperand(0);
24462 SDValue N10 = N1.getOperand(0);
24463 EVT N00Type = N00.getValueType();
24464 EVT N10Type = N10.getValueType();
24465 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24466 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24467 return DAG.getBitcast(VT, FPLogic);
24473 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24474 TargetLowering::DAGCombinerInfo &DCI,
24475 const X86Subtarget *Subtarget) {
24476 if (DCI.isBeforeLegalizeOps())
24479 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24482 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24485 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24488 EVT VT = N->getValueType(0);
24489 SDValue N0 = N->getOperand(0);
24490 SDValue N1 = N->getOperand(1);
24493 // Create BEXTR instructions
24494 // BEXTR is ((X >> imm) & (2**size-1))
24495 if (VT == MVT::i32 || VT == MVT::i64) {
24496 // Check for BEXTR.
24497 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24498 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24499 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24500 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24501 if (MaskNode && ShiftNode) {
24502 uint64_t Mask = MaskNode->getZExtValue();
24503 uint64_t Shift = ShiftNode->getZExtValue();
24504 if (isMask_64(Mask)) {
24505 uint64_t MaskSize = countPopulation(Mask);
24506 if (Shift + MaskSize <= VT.getSizeInBits())
24507 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24508 DAG.getConstant(Shift | (MaskSize << 8), DL,
24517 // Want to form ANDNP nodes:
24518 // 1) In the hopes of then easily combining them with OR and AND nodes
24519 // to form PBLEND/PSIGN.
24520 // 2) To match ANDN packed intrinsics
24521 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24524 // Check LHS for vnot
24525 if (N0.getOpcode() == ISD::XOR &&
24526 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24527 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24528 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24530 // Check RHS for vnot
24531 if (N1.getOpcode() == ISD::XOR &&
24532 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24533 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24534 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24539 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24540 TargetLowering::DAGCombinerInfo &DCI,
24541 const X86Subtarget *Subtarget) {
24542 if (DCI.isBeforeLegalizeOps())
24545 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24548 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24551 SDValue N0 = N->getOperand(0);
24552 SDValue N1 = N->getOperand(1);
24553 EVT VT = N->getValueType(0);
24555 // look for psign/blend
24556 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24557 if (!Subtarget->hasSSSE3() ||
24558 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24561 // Canonicalize pandn to RHS
24562 if (N0.getOpcode() == X86ISD::ANDNP)
24564 // or (and (m, y), (pandn m, x))
24565 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24566 SDValue Mask = N1.getOperand(0);
24567 SDValue X = N1.getOperand(1);
24569 if (N0.getOperand(0) == Mask)
24570 Y = N0.getOperand(1);
24571 if (N0.getOperand(1) == Mask)
24572 Y = N0.getOperand(0);
24574 // Check to see if the mask appeared in both the AND and ANDNP and
24578 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24579 // Look through mask bitcast.
24580 if (Mask.getOpcode() == ISD::BITCAST)
24581 Mask = Mask.getOperand(0);
24582 if (X.getOpcode() == ISD::BITCAST)
24583 X = X.getOperand(0);
24584 if (Y.getOpcode() == ISD::BITCAST)
24585 Y = Y.getOperand(0);
24587 EVT MaskVT = Mask.getValueType();
24589 // Validate that the Mask operand is a vector sra node.
24590 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24591 // there is no psrai.b
24592 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24593 unsigned SraAmt = ~0;
24594 if (Mask.getOpcode() == ISD::SRA) {
24595 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24596 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24597 SraAmt = AmtConst->getZExtValue();
24598 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24599 SDValue SraC = Mask.getOperand(1);
24600 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24602 if ((SraAmt + 1) != EltBits)
24607 // Now we know we at least have a plendvb with the mask val. See if
24608 // we can form a psignb/w/d.
24609 // psign = x.type == y.type == mask.type && y = sub(0, x);
24610 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24611 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24612 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24613 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24614 "Unsupported VT for PSIGN");
24615 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24616 return DAG.getBitcast(VT, Mask);
24618 // PBLENDVB only available on SSE 4.1
24619 if (!Subtarget->hasSSE41())
24622 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24624 X = DAG.getBitcast(BlendVT, X);
24625 Y = DAG.getBitcast(BlendVT, Y);
24626 Mask = DAG.getBitcast(BlendVT, Mask);
24627 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24628 return DAG.getBitcast(VT, Mask);
24632 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24635 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24636 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24638 // SHLD/SHRD instructions have lower register pressure, but on some
24639 // platforms they have higher latency than the equivalent
24640 // series of shifts/or that would otherwise be generated.
24641 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24642 // have higher latencies and we are not optimizing for size.
24643 if (!OptForSize && Subtarget->isSHLDSlow())
24646 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24648 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24650 if (!N0.hasOneUse() || !N1.hasOneUse())
24653 SDValue ShAmt0 = N0.getOperand(1);
24654 if (ShAmt0.getValueType() != MVT::i8)
24656 SDValue ShAmt1 = N1.getOperand(1);
24657 if (ShAmt1.getValueType() != MVT::i8)
24659 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24660 ShAmt0 = ShAmt0.getOperand(0);
24661 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24662 ShAmt1 = ShAmt1.getOperand(0);
24665 unsigned Opc = X86ISD::SHLD;
24666 SDValue Op0 = N0.getOperand(0);
24667 SDValue Op1 = N1.getOperand(0);
24668 if (ShAmt0.getOpcode() == ISD::SUB) {
24669 Opc = X86ISD::SHRD;
24670 std::swap(Op0, Op1);
24671 std::swap(ShAmt0, ShAmt1);
24674 unsigned Bits = VT.getSizeInBits();
24675 if (ShAmt1.getOpcode() == ISD::SUB) {
24676 SDValue Sum = ShAmt1.getOperand(0);
24677 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24678 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24679 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24680 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24681 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24682 return DAG.getNode(Opc, DL, VT,
24684 DAG.getNode(ISD::TRUNCATE, DL,
24687 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24688 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24690 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24691 return DAG.getNode(Opc, DL, VT,
24692 N0.getOperand(0), N1.getOperand(0),
24693 DAG.getNode(ISD::TRUNCATE, DL,
24700 // Generate NEG and CMOV for integer abs.
24701 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24702 EVT VT = N->getValueType(0);
24704 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24705 // 8-bit integer abs to NEG and CMOV.
24706 if (VT.isInteger() && VT.getSizeInBits() == 8)
24709 SDValue N0 = N->getOperand(0);
24710 SDValue N1 = N->getOperand(1);
24713 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24714 // and change it to SUB and CMOV.
24715 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24716 N0.getOpcode() == ISD::ADD &&
24717 N0.getOperand(1) == N1 &&
24718 N1.getOpcode() == ISD::SRA &&
24719 N1.getOperand(0) == N0.getOperand(0))
24720 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24721 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24722 // Generate SUB & CMOV.
24723 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24724 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24726 SDValue Ops[] = { N0.getOperand(0), Neg,
24727 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24728 SDValue(Neg.getNode(), 1) };
24729 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24734 // Try to turn tests against the signbit in the form of:
24735 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24738 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24739 // This is only worth doing if the output type is i8.
24740 if (N->getValueType(0) != MVT::i8)
24743 SDValue N0 = N->getOperand(0);
24744 SDValue N1 = N->getOperand(1);
24746 // We should be performing an xor against a truncated shift.
24747 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24750 // Make sure we are performing an xor against one.
24751 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24754 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24755 SDValue Shift = N0.getOperand(0);
24756 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24759 // Make sure we are truncating from one of i16, i32 or i64.
24760 EVT ShiftTy = Shift.getValueType();
24761 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24764 // Make sure the shift amount extracts the sign bit.
24765 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24766 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24769 // Create a greater-than comparison against -1.
24770 // N.B. Using SETGE against 0 works but we want a canonical looking
24771 // comparison, using SETGT matches up with what TranslateX86CC.
24773 SDValue ShiftOp = Shift.getOperand(0);
24774 EVT ShiftOpTy = ShiftOp.getValueType();
24775 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24776 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24780 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24781 TargetLowering::DAGCombinerInfo &DCI,
24782 const X86Subtarget *Subtarget) {
24783 if (DCI.isBeforeLegalizeOps())
24786 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24789 if (Subtarget->hasCMov())
24790 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24793 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24799 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24800 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24801 TargetLowering::DAGCombinerInfo &DCI,
24802 const X86Subtarget *Subtarget) {
24803 LoadSDNode *Ld = cast<LoadSDNode>(N);
24804 EVT RegVT = Ld->getValueType(0);
24805 EVT MemVT = Ld->getMemoryVT();
24807 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24809 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24810 // into two 16-byte operations.
24811 ISD::LoadExtType Ext = Ld->getExtensionType();
24813 unsigned AddressSpace = Ld->getAddressSpace();
24814 unsigned Alignment = Ld->getAlignment();
24815 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24816 Ext == ISD::NON_EXTLOAD &&
24817 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24818 AddressSpace, Alignment, &Fast) && !Fast) {
24819 unsigned NumElems = RegVT.getVectorNumElements();
24823 SDValue Ptr = Ld->getBasePtr();
24824 SDValue Increment =
24825 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24827 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24829 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24830 Ld->getPointerInfo(), Ld->isVolatile(),
24831 Ld->isNonTemporal(), Ld->isInvariant(),
24833 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24834 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24835 Ld->getPointerInfo(), Ld->isVolatile(),
24836 Ld->isNonTemporal(), Ld->isInvariant(),
24837 std::min(16U, Alignment));
24838 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24840 Load2.getValue(1));
24842 SDValue NewVec = DAG.getUNDEF(RegVT);
24843 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24844 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24845 return DCI.CombineTo(N, NewVec, TF, true);
24851 /// PerformMLOADCombine - Resolve extending loads
24852 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24853 TargetLowering::DAGCombinerInfo &DCI,
24854 const X86Subtarget *Subtarget) {
24855 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24856 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24859 EVT VT = Mld->getValueType(0);
24860 unsigned NumElems = VT.getVectorNumElements();
24861 EVT LdVT = Mld->getMemoryVT();
24864 assert(LdVT != VT && "Cannot extend to the same type");
24865 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24866 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24867 // From, To sizes and ElemCount must be pow of two
24868 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24869 "Unexpected size for extending masked load");
24871 unsigned SizeRatio = ToSz / FromSz;
24872 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24874 // Create a type on which we perform the shuffle
24875 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24876 LdVT.getScalarType(), NumElems*SizeRatio);
24877 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24879 // Convert Src0 value
24880 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24881 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24882 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24883 for (unsigned i = 0; i != NumElems; ++i)
24884 ShuffleVec[i] = i * SizeRatio;
24886 // Can't shuffle using an illegal type.
24887 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24888 "WideVecVT should be legal");
24889 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24890 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24892 // Prepare the new mask
24894 SDValue Mask = Mld->getMask();
24895 if (Mask.getValueType() == VT) {
24896 // Mask and original value have the same type
24897 NewMask = DAG.getBitcast(WideVecVT, Mask);
24898 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24899 for (unsigned i = 0; i != NumElems; ++i)
24900 ShuffleVec[i] = i * SizeRatio;
24901 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24902 ShuffleVec[i] = NumElems*SizeRatio;
24903 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24904 DAG.getConstant(0, dl, WideVecVT),
24908 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24909 unsigned WidenNumElts = NumElems*SizeRatio;
24910 unsigned MaskNumElts = VT.getVectorNumElements();
24911 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24914 unsigned NumConcat = WidenNumElts / MaskNumElts;
24915 SmallVector<SDValue, 16> Ops(NumConcat);
24916 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24918 for (unsigned i = 1; i != NumConcat; ++i)
24921 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24924 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24925 Mld->getBasePtr(), NewMask, WideSrc0,
24926 Mld->getMemoryVT(), Mld->getMemOperand(),
24928 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24929 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24931 /// PerformMSTORECombine - Resolve truncating stores
24932 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24933 const X86Subtarget *Subtarget) {
24934 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24935 if (!Mst->isTruncatingStore())
24938 EVT VT = Mst->getValue().getValueType();
24939 unsigned NumElems = VT.getVectorNumElements();
24940 EVT StVT = Mst->getMemoryVT();
24943 assert(StVT != VT && "Cannot truncate to the same type");
24944 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24945 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24947 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24949 // The truncating store is legal in some cases. For example
24950 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24951 // are designated for truncate store.
24952 // In this case we don't need any further transformations.
24953 if (TLI.isTruncStoreLegal(VT, StVT))
24956 // From, To sizes and ElemCount must be pow of two
24957 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24958 "Unexpected size for truncating masked store");
24959 // We are going to use the original vector elt for storing.
24960 // Accumulated smaller vector elements must be a multiple of the store size.
24961 assert (((NumElems * FromSz) % ToSz) == 0 &&
24962 "Unexpected ratio for truncating masked store");
24964 unsigned SizeRatio = FromSz / ToSz;
24965 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24967 // Create a type on which we perform the shuffle
24968 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24969 StVT.getScalarType(), NumElems*SizeRatio);
24971 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24973 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
24974 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24975 for (unsigned i = 0; i != NumElems; ++i)
24976 ShuffleVec[i] = i * SizeRatio;
24978 // Can't shuffle using an illegal type.
24979 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24980 "WideVecVT should be legal");
24982 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24983 DAG.getUNDEF(WideVecVT),
24987 SDValue Mask = Mst->getMask();
24988 if (Mask.getValueType() == VT) {
24989 // Mask and original value have the same type
24990 NewMask = DAG.getBitcast(WideVecVT, Mask);
24991 for (unsigned i = 0; i != NumElems; ++i)
24992 ShuffleVec[i] = i * SizeRatio;
24993 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24994 ShuffleVec[i] = NumElems*SizeRatio;
24995 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24996 DAG.getConstant(0, dl, WideVecVT),
25000 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25001 unsigned WidenNumElts = NumElems*SizeRatio;
25002 unsigned MaskNumElts = VT.getVectorNumElements();
25003 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25006 unsigned NumConcat = WidenNumElts / MaskNumElts;
25007 SmallVector<SDValue, 16> Ops(NumConcat);
25008 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25010 for (unsigned i = 1; i != NumConcat; ++i)
25013 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25016 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25017 NewMask, StVT, Mst->getMemOperand(), false);
25019 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25020 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25021 const X86Subtarget *Subtarget) {
25022 StoreSDNode *St = cast<StoreSDNode>(N);
25023 EVT VT = St->getValue().getValueType();
25024 EVT StVT = St->getMemoryVT();
25026 SDValue StoredVal = St->getOperand(1);
25027 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25029 // If we are saving a concatenation of two XMM registers and 32-byte stores
25030 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25032 unsigned AddressSpace = St->getAddressSpace();
25033 unsigned Alignment = St->getAlignment();
25034 if (VT.is256BitVector() && StVT == VT &&
25035 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25036 AddressSpace, Alignment, &Fast) && !Fast) {
25037 unsigned NumElems = VT.getVectorNumElements();
25041 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25042 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25045 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25046 SDValue Ptr0 = St->getBasePtr();
25047 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25049 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25050 St->getPointerInfo(), St->isVolatile(),
25051 St->isNonTemporal(), Alignment);
25052 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25053 St->getPointerInfo(), St->isVolatile(),
25054 St->isNonTemporal(),
25055 std::min(16U, Alignment));
25056 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25059 // Optimize trunc store (of multiple scalars) to shuffle and store.
25060 // First, pack all of the elements in one place. Next, store to memory
25061 // in fewer chunks.
25062 if (St->isTruncatingStore() && VT.isVector()) {
25063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25064 unsigned NumElems = VT.getVectorNumElements();
25065 assert(StVT != VT && "Cannot truncate to the same type");
25066 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25067 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25069 // The truncating store is legal in some cases. For example
25070 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25071 // are designated for truncate store.
25072 // In this case we don't need any further transformations.
25073 if (TLI.isTruncStoreLegal(VT, StVT))
25076 // From, To sizes and ElemCount must be pow of two
25077 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25078 // We are going to use the original vector elt for storing.
25079 // Accumulated smaller vector elements must be a multiple of the store size.
25080 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25082 unsigned SizeRatio = FromSz / ToSz;
25084 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25086 // Create a type on which we perform the shuffle
25087 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25088 StVT.getScalarType(), NumElems*SizeRatio);
25090 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25092 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25093 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25094 for (unsigned i = 0; i != NumElems; ++i)
25095 ShuffleVec[i] = i * SizeRatio;
25097 // Can't shuffle using an illegal type.
25098 if (!TLI.isTypeLegal(WideVecVT))
25101 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25102 DAG.getUNDEF(WideVecVT),
25104 // At this point all of the data is stored at the bottom of the
25105 // register. We now need to save it to mem.
25107 // Find the largest store unit
25108 MVT StoreType = MVT::i8;
25109 for (MVT Tp : MVT::integer_valuetypes()) {
25110 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25114 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25115 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25116 (64 <= NumElems * ToSz))
25117 StoreType = MVT::f64;
25119 // Bitcast the original vector into a vector of store-size units
25120 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25121 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25122 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25123 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25124 SmallVector<SDValue, 8> Chains;
25125 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25126 TLI.getPointerTy(DAG.getDataLayout()));
25127 SDValue Ptr = St->getBasePtr();
25129 // Perform one or more big stores into memory.
25130 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25131 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25132 StoreType, ShuffWide,
25133 DAG.getIntPtrConstant(i, dl));
25134 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25135 St->getPointerInfo(), St->isVolatile(),
25136 St->isNonTemporal(), St->getAlignment());
25137 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25138 Chains.push_back(Ch);
25141 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25144 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25145 // the FP state in cases where an emms may be missing.
25146 // A preferable solution to the general problem is to figure out the right
25147 // places to insert EMMS. This qualifies as a quick hack.
25149 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25150 if (VT.getSizeInBits() != 64)
25153 const Function *F = DAG.getMachineFunction().getFunction();
25154 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25156 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25157 if ((VT.isVector() ||
25158 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25159 isa<LoadSDNode>(St->getValue()) &&
25160 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25161 St->getChain().hasOneUse() && !St->isVolatile()) {
25162 SDNode* LdVal = St->getValue().getNode();
25163 LoadSDNode *Ld = nullptr;
25164 int TokenFactorIndex = -1;
25165 SmallVector<SDValue, 8> Ops;
25166 SDNode* ChainVal = St->getChain().getNode();
25167 // Must be a store of a load. We currently handle two cases: the load
25168 // is a direct child, and it's under an intervening TokenFactor. It is
25169 // possible to dig deeper under nested TokenFactors.
25170 if (ChainVal == LdVal)
25171 Ld = cast<LoadSDNode>(St->getChain());
25172 else if (St->getValue().hasOneUse() &&
25173 ChainVal->getOpcode() == ISD::TokenFactor) {
25174 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25175 if (ChainVal->getOperand(i).getNode() == LdVal) {
25176 TokenFactorIndex = i;
25177 Ld = cast<LoadSDNode>(St->getValue());
25179 Ops.push_back(ChainVal->getOperand(i));
25183 if (!Ld || !ISD::isNormalLoad(Ld))
25186 // If this is not the MMX case, i.e. we are just turning i64 load/store
25187 // into f64 load/store, avoid the transformation if there are multiple
25188 // uses of the loaded value.
25189 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25194 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25195 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25197 if (Subtarget->is64Bit() || F64IsLegal) {
25198 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25199 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25200 Ld->getPointerInfo(), Ld->isVolatile(),
25201 Ld->isNonTemporal(), Ld->isInvariant(),
25202 Ld->getAlignment());
25203 SDValue NewChain = NewLd.getValue(1);
25204 if (TokenFactorIndex != -1) {
25205 Ops.push_back(NewChain);
25206 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25208 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25209 St->getPointerInfo(),
25210 St->isVolatile(), St->isNonTemporal(),
25211 St->getAlignment());
25214 // Otherwise, lower to two pairs of 32-bit loads / stores.
25215 SDValue LoAddr = Ld->getBasePtr();
25216 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25217 DAG.getConstant(4, LdDL, MVT::i32));
25219 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25220 Ld->getPointerInfo(),
25221 Ld->isVolatile(), Ld->isNonTemporal(),
25222 Ld->isInvariant(), Ld->getAlignment());
25223 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25224 Ld->getPointerInfo().getWithOffset(4),
25225 Ld->isVolatile(), Ld->isNonTemporal(),
25227 MinAlign(Ld->getAlignment(), 4));
25229 SDValue NewChain = LoLd.getValue(1);
25230 if (TokenFactorIndex != -1) {
25231 Ops.push_back(LoLd);
25232 Ops.push_back(HiLd);
25233 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25236 LoAddr = St->getBasePtr();
25237 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25238 DAG.getConstant(4, StDL, MVT::i32));
25240 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25241 St->getPointerInfo(),
25242 St->isVolatile(), St->isNonTemporal(),
25243 St->getAlignment());
25244 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25245 St->getPointerInfo().getWithOffset(4),
25247 St->isNonTemporal(),
25248 MinAlign(St->getAlignment(), 4));
25249 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25252 // This is similar to the above case, but here we handle a scalar 64-bit
25253 // integer store that is extracted from a vector on a 32-bit target.
25254 // If we have SSE2, then we can treat it like a floating-point double
25255 // to get past legalization. The execution dependencies fixup pass will
25256 // choose the optimal machine instruction for the store if this really is
25257 // an integer or v2f32 rather than an f64.
25258 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25259 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25260 SDValue OldExtract = St->getOperand(1);
25261 SDValue ExtOp0 = OldExtract.getOperand(0);
25262 unsigned VecSize = ExtOp0.getValueSizeInBits();
25263 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25264 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25265 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25266 BitCast, OldExtract.getOperand(1));
25267 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25268 St->getPointerInfo(), St->isVolatile(),
25269 St->isNonTemporal(), St->getAlignment());
25275 /// Return 'true' if this vector operation is "horizontal"
25276 /// and return the operands for the horizontal operation in LHS and RHS. A
25277 /// horizontal operation performs the binary operation on successive elements
25278 /// of its first operand, then on successive elements of its second operand,
25279 /// returning the resulting values in a vector. For example, if
25280 /// A = < float a0, float a1, float a2, float a3 >
25282 /// B = < float b0, float b1, float b2, float b3 >
25283 /// then the result of doing a horizontal operation on A and B is
25284 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25285 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25286 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25287 /// set to A, RHS to B, and the routine returns 'true'.
25288 /// Note that the binary operation should have the property that if one of the
25289 /// operands is UNDEF then the result is UNDEF.
25290 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25291 // Look for the following pattern: if
25292 // A = < float a0, float a1, float a2, float a3 >
25293 // B = < float b0, float b1, float b2, float b3 >
25295 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25296 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25297 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25298 // which is A horizontal-op B.
25300 // At least one of the operands should be a vector shuffle.
25301 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25302 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25305 MVT VT = LHS.getSimpleValueType();
25307 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25308 "Unsupported vector type for horizontal add/sub");
25310 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25311 // operate independently on 128-bit lanes.
25312 unsigned NumElts = VT.getVectorNumElements();
25313 unsigned NumLanes = VT.getSizeInBits()/128;
25314 unsigned NumLaneElts = NumElts / NumLanes;
25315 assert((NumLaneElts % 2 == 0) &&
25316 "Vector type should have an even number of elements in each lane");
25317 unsigned HalfLaneElts = NumLaneElts/2;
25319 // View LHS in the form
25320 // LHS = VECTOR_SHUFFLE A, B, LMask
25321 // If LHS is not a shuffle then pretend it is the shuffle
25322 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25323 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25326 SmallVector<int, 16> LMask(NumElts);
25327 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25328 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25329 A = LHS.getOperand(0);
25330 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25331 B = LHS.getOperand(1);
25332 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25333 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25335 if (LHS.getOpcode() != ISD::UNDEF)
25337 for (unsigned i = 0; i != NumElts; ++i)
25341 // Likewise, view RHS in the form
25342 // RHS = VECTOR_SHUFFLE C, D, RMask
25344 SmallVector<int, 16> RMask(NumElts);
25345 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25346 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25347 C = RHS.getOperand(0);
25348 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25349 D = RHS.getOperand(1);
25350 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25351 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25353 if (RHS.getOpcode() != ISD::UNDEF)
25355 for (unsigned i = 0; i != NumElts; ++i)
25359 // Check that the shuffles are both shuffling the same vectors.
25360 if (!(A == C && B == D) && !(A == D && B == C))
25363 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25364 if (!A.getNode() && !B.getNode())
25367 // If A and B occur in reverse order in RHS, then "swap" them (which means
25368 // rewriting the mask).
25370 ShuffleVectorSDNode::commuteMask(RMask);
25372 // At this point LHS and RHS are equivalent to
25373 // LHS = VECTOR_SHUFFLE A, B, LMask
25374 // RHS = VECTOR_SHUFFLE A, B, RMask
25375 // Check that the masks correspond to performing a horizontal operation.
25376 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25377 for (unsigned i = 0; i != NumLaneElts; ++i) {
25378 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25380 // Ignore any UNDEF components.
25381 if (LIdx < 0 || RIdx < 0 ||
25382 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25383 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25386 // Check that successive elements are being operated on. If not, this is
25387 // not a horizontal operation.
25388 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25389 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25390 if (!(LIdx == Index && RIdx == Index + 1) &&
25391 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25396 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25397 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25401 /// Do target-specific dag combines on floating point adds.
25402 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25403 const X86Subtarget *Subtarget) {
25404 EVT VT = N->getValueType(0);
25405 SDValue LHS = N->getOperand(0);
25406 SDValue RHS = N->getOperand(1);
25408 // Try to synthesize horizontal adds from adds of shuffles.
25409 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25410 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25411 isHorizontalBinOp(LHS, RHS, true))
25412 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25416 /// Do target-specific dag combines on floating point subs.
25417 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25418 const X86Subtarget *Subtarget) {
25419 EVT VT = N->getValueType(0);
25420 SDValue LHS = N->getOperand(0);
25421 SDValue RHS = N->getOperand(1);
25423 // Try to synthesize horizontal subs from subs of shuffles.
25424 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25425 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25426 isHorizontalBinOp(LHS, RHS, false))
25427 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25431 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25432 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25433 const X86Subtarget *Subtarget) {
25434 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25436 // F[X]OR(0.0, x) -> x
25437 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25438 if (C->getValueAPF().isPosZero())
25439 return N->getOperand(1);
25441 // F[X]OR(x, 0.0) -> x
25442 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25443 if (C->getValueAPF().isPosZero())
25444 return N->getOperand(0);
25446 EVT VT = N->getValueType(0);
25447 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25449 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25450 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25452 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25453 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25454 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25455 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25456 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25461 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25462 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25463 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25465 // Only perform optimizations if UnsafeMath is used.
25466 if (!DAG.getTarget().Options.UnsafeFPMath)
25469 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25470 // into FMINC and FMAXC, which are Commutative operations.
25471 unsigned NewOp = 0;
25472 switch (N->getOpcode()) {
25473 default: llvm_unreachable("unknown opcode");
25474 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25475 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25478 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25479 N->getOperand(0), N->getOperand(1));
25482 /// Do target-specific dag combines on X86ISD::FAND nodes.
25483 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25484 // FAND(0.0, x) -> 0.0
25485 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25486 if (C->getValueAPF().isPosZero())
25487 return N->getOperand(0);
25489 // FAND(x, 0.0) -> 0.0
25490 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25491 if (C->getValueAPF().isPosZero())
25492 return N->getOperand(1);
25497 /// Do target-specific dag combines on X86ISD::FANDN nodes
25498 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25499 // FANDN(0.0, x) -> x
25500 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25501 if (C->getValueAPF().isPosZero())
25502 return N->getOperand(1);
25504 // FANDN(x, 0.0) -> 0.0
25505 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25506 if (C->getValueAPF().isPosZero())
25507 return N->getOperand(1);
25512 static SDValue PerformBTCombine(SDNode *N,
25514 TargetLowering::DAGCombinerInfo &DCI) {
25515 // BT ignores high bits in the bit index operand.
25516 SDValue Op1 = N->getOperand(1);
25517 if (Op1.hasOneUse()) {
25518 unsigned BitWidth = Op1.getValueSizeInBits();
25519 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25520 APInt KnownZero, KnownOne;
25521 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25522 !DCI.isBeforeLegalizeOps());
25523 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25524 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25525 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25526 DCI.CommitTargetLoweringOpt(TLO);
25531 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25532 SDValue Op = N->getOperand(0);
25533 if (Op.getOpcode() == ISD::BITCAST)
25534 Op = Op.getOperand(0);
25535 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25536 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25537 VT.getVectorElementType().getSizeInBits() ==
25538 OpVT.getVectorElementType().getSizeInBits()) {
25539 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25544 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25545 const X86Subtarget *Subtarget) {
25546 EVT VT = N->getValueType(0);
25547 if (!VT.isVector())
25550 SDValue N0 = N->getOperand(0);
25551 SDValue N1 = N->getOperand(1);
25552 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25555 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25556 // both SSE and AVX2 since there is no sign-extended shift right
25557 // operation on a vector with 64-bit elements.
25558 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25559 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25560 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25561 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25562 SDValue N00 = N0.getOperand(0);
25564 // EXTLOAD has a better solution on AVX2,
25565 // it may be replaced with X86ISD::VSEXT node.
25566 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25567 if (!ISD::isNormalLoad(N00.getNode()))
25570 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25571 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25573 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25579 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25580 TargetLowering::DAGCombinerInfo &DCI,
25581 const X86Subtarget *Subtarget) {
25582 SDValue N0 = N->getOperand(0);
25583 EVT VT = N->getValueType(0);
25584 EVT SVT = VT.getScalarType();
25585 EVT InVT = N0.getValueType();
25586 EVT InSVT = InVT.getScalarType();
25589 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25590 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25591 // This exposes the sext to the sdivrem lowering, so that it directly extends
25592 // from AH (which we otherwise need to do contortions to access).
25593 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25594 InVT == MVT::i8 && VT == MVT::i32) {
25595 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25596 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25597 N0.getOperand(0), N0.getOperand(1));
25598 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25599 return R.getValue(1);
25602 if (!DCI.isBeforeLegalizeOps()) {
25603 if (InVT == MVT::i1) {
25604 SDValue Zero = DAG.getConstant(0, DL, VT);
25606 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25607 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25612 if (VT.isVector() && Subtarget->hasSSE2()) {
25613 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25614 EVT InVT = N.getValueType();
25615 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25616 Size / InVT.getScalarSizeInBits());
25617 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25618 DAG.getUNDEF(InVT));
25620 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25623 // If target-size is less than 128-bits, extend to a type that would extend
25624 // to 128 bits, extend that and extract the original target vector.
25625 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25626 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25627 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25628 unsigned Scale = 128 / VT.getSizeInBits();
25630 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25631 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25632 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25633 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25634 DAG.getIntPtrConstant(0, DL));
25637 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25638 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25639 if (VT.getSizeInBits() == 128 &&
25640 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25641 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25642 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25643 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25646 // On pre-AVX2 targets, split into 128-bit nodes of
25647 // ISD::SIGN_EXTEND_VECTOR_INREG.
25648 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25649 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25650 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25651 unsigned NumVecs = VT.getSizeInBits() / 128;
25652 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25653 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25654 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25656 SmallVector<SDValue, 8> Opnds;
25657 for (unsigned i = 0, Offset = 0; i != NumVecs;
25658 ++i, Offset += NumSubElts) {
25659 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25660 DAG.getIntPtrConstant(Offset, DL));
25661 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25662 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25663 Opnds.push_back(SrcVec);
25665 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25669 if (!Subtarget->hasFp256())
25672 if (VT.isVector() && VT.getSizeInBits() == 256)
25673 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25679 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25680 const X86Subtarget* Subtarget) {
25682 EVT VT = N->getValueType(0);
25684 // Let legalize expand this if it isn't a legal type yet.
25685 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25688 EVT ScalarVT = VT.getScalarType();
25689 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25690 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25691 !Subtarget->hasAVX512()))
25694 SDValue A = N->getOperand(0);
25695 SDValue B = N->getOperand(1);
25696 SDValue C = N->getOperand(2);
25698 bool NegA = (A.getOpcode() == ISD::FNEG);
25699 bool NegB = (B.getOpcode() == ISD::FNEG);
25700 bool NegC = (C.getOpcode() == ISD::FNEG);
25702 // Negative multiplication when NegA xor NegB
25703 bool NegMul = (NegA != NegB);
25705 A = A.getOperand(0);
25707 B = B.getOperand(0);
25709 C = C.getOperand(0);
25713 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25715 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25717 return DAG.getNode(Opcode, dl, VT, A, B, C);
25720 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25721 TargetLowering::DAGCombinerInfo &DCI,
25722 const X86Subtarget *Subtarget) {
25723 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25724 // (and (i32 x86isd::setcc_carry), 1)
25725 // This eliminates the zext. This transformation is necessary because
25726 // ISD::SETCC is always legalized to i8.
25728 SDValue N0 = N->getOperand(0);
25729 EVT VT = N->getValueType(0);
25731 if (N0.getOpcode() == ISD::AND &&
25733 N0.getOperand(0).hasOneUse()) {
25734 SDValue N00 = N0.getOperand(0);
25735 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25736 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25737 if (!C || C->getZExtValue() != 1)
25739 return DAG.getNode(ISD::AND, dl, VT,
25740 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25741 N00.getOperand(0), N00.getOperand(1)),
25742 DAG.getConstant(1, dl, VT));
25746 if (N0.getOpcode() == ISD::TRUNCATE &&
25748 N0.getOperand(0).hasOneUse()) {
25749 SDValue N00 = N0.getOperand(0);
25750 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25751 return DAG.getNode(ISD::AND, dl, VT,
25752 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25753 N00.getOperand(0), N00.getOperand(1)),
25754 DAG.getConstant(1, dl, VT));
25758 if (VT.is256BitVector())
25759 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25762 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25763 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25764 // This exposes the zext to the udivrem lowering, so that it directly extends
25765 // from AH (which we otherwise need to do contortions to access).
25766 if (N0.getOpcode() == ISD::UDIVREM &&
25767 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25768 (VT == MVT::i32 || VT == MVT::i64)) {
25769 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25770 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25771 N0.getOperand(0), N0.getOperand(1));
25772 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25773 return R.getValue(1);
25779 // Optimize x == -y --> x+y == 0
25780 // x != -y --> x+y != 0
25781 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25782 const X86Subtarget* Subtarget) {
25783 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25784 SDValue LHS = N->getOperand(0);
25785 SDValue RHS = N->getOperand(1);
25786 EVT VT = N->getValueType(0);
25789 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25790 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25791 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25792 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25793 LHS.getOperand(1));
25794 return DAG.getSetCC(DL, N->getValueType(0), addV,
25795 DAG.getConstant(0, DL, addV.getValueType()), CC);
25797 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25799 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25800 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25801 RHS.getOperand(1));
25802 return DAG.getSetCC(DL, N->getValueType(0), addV,
25803 DAG.getConstant(0, DL, addV.getValueType()), CC);
25806 if (VT.getScalarType() == MVT::i1 &&
25807 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25809 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25810 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25811 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25813 if (!IsSEXT0 || !IsVZero1) {
25814 // Swap the operands and update the condition code.
25815 std::swap(LHS, RHS);
25816 CC = ISD::getSetCCSwappedOperands(CC);
25818 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25819 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25820 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25823 if (IsSEXT0 && IsVZero1) {
25824 assert(VT == LHS.getOperand(0).getValueType() &&
25825 "Uexpected operand type");
25826 if (CC == ISD::SETGT)
25827 return DAG.getConstant(0, DL, VT);
25828 if (CC == ISD::SETLE)
25829 return DAG.getConstant(1, DL, VT);
25830 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25831 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25833 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25834 "Unexpected condition code!");
25835 return LHS.getOperand(0);
25842 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25843 SelectionDAG &DAG) {
25845 MVT VT = Load->getSimpleValueType(0);
25846 MVT EVT = VT.getVectorElementType();
25847 SDValue Addr = Load->getOperand(1);
25848 SDValue NewAddr = DAG.getNode(
25849 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25850 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25851 Addr.getSimpleValueType()));
25854 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25855 DAG.getMachineFunction().getMachineMemOperand(
25856 Load->getMemOperand(), 0, EVT.getStoreSize()));
25860 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25861 const X86Subtarget *Subtarget) {
25863 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25864 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25865 "X86insertps is only defined for v4x32");
25867 SDValue Ld = N->getOperand(1);
25868 if (MayFoldLoad(Ld)) {
25869 // Extract the countS bits from the immediate so we can get the proper
25870 // address when narrowing the vector load to a specific element.
25871 // When the second source op is a memory address, insertps doesn't use
25872 // countS and just gets an f32 from that address.
25873 unsigned DestIndex =
25874 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25876 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25878 // Create this as a scalar to vector to match the instruction pattern.
25879 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25880 // countS bits are ignored when loading from memory on insertps, which
25881 // means we don't need to explicitly set them to 0.
25882 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25883 LoadScalarToVector, N->getOperand(2));
25888 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25889 SDValue V0 = N->getOperand(0);
25890 SDValue V1 = N->getOperand(1);
25892 EVT VT = N->getValueType(0);
25894 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25895 // operands and changing the mask to 1. This saves us a bunch of
25896 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25897 // x86InstrInfo knows how to commute this back after instruction selection
25898 // if it would help register allocation.
25900 // TODO: If optimizing for size or a processor that doesn't suffer from
25901 // partial register update stalls, this should be transformed into a MOVSD
25902 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25904 if (VT == MVT::v2f64)
25905 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25906 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25907 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25908 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25914 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25915 // as "sbb reg,reg", since it can be extended without zext and produces
25916 // an all-ones bit which is more useful than 0/1 in some cases.
25917 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25920 return DAG.getNode(ISD::AND, DL, VT,
25921 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25922 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25924 DAG.getConstant(1, DL, VT));
25925 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25926 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25927 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25928 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25932 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25933 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25934 TargetLowering::DAGCombinerInfo &DCI,
25935 const X86Subtarget *Subtarget) {
25937 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25938 SDValue EFLAGS = N->getOperand(1);
25940 if (CC == X86::COND_A) {
25941 // Try to convert COND_A into COND_B in an attempt to facilitate
25942 // materializing "setb reg".
25944 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25945 // cannot take an immediate as its first operand.
25947 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25948 EFLAGS.getValueType().isInteger() &&
25949 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25950 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25951 EFLAGS.getNode()->getVTList(),
25952 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25953 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25954 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25958 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25959 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25961 if (CC == X86::COND_B)
25962 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25964 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25965 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25966 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25972 // Optimize branch condition evaluation.
25974 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25975 TargetLowering::DAGCombinerInfo &DCI,
25976 const X86Subtarget *Subtarget) {
25978 SDValue Chain = N->getOperand(0);
25979 SDValue Dest = N->getOperand(1);
25980 SDValue EFLAGS = N->getOperand(3);
25981 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25983 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25984 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25985 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25992 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25993 SelectionDAG &DAG) {
25994 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25995 // optimize away operation when it's from a constant.
25997 // The general transformation is:
25998 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25999 // AND(VECTOR_CMP(x,y), constant2)
26000 // constant2 = UNARYOP(constant)
26002 // Early exit if this isn't a vector operation, the operand of the
26003 // unary operation isn't a bitwise AND, or if the sizes of the operations
26004 // aren't the same.
26005 EVT VT = N->getValueType(0);
26006 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26007 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26008 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26011 // Now check that the other operand of the AND is a constant. We could
26012 // make the transformation for non-constant splats as well, but it's unclear
26013 // that would be a benefit as it would not eliminate any operations, just
26014 // perform one more step in scalar code before moving to the vector unit.
26015 if (BuildVectorSDNode *BV =
26016 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26017 // Bail out if the vector isn't a constant.
26018 if (!BV->isConstant())
26021 // Everything checks out. Build up the new and improved node.
26023 EVT IntVT = BV->getValueType(0);
26024 // Create a new constant of the appropriate type for the transformed
26026 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26027 // The AND node needs bitcasts to/from an integer vector type around it.
26028 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26029 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26030 N->getOperand(0)->getOperand(0), MaskConst);
26031 SDValue Res = DAG.getBitcast(VT, NewAnd);
26038 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26039 const X86Subtarget *Subtarget) {
26040 SDValue Op0 = N->getOperand(0);
26041 EVT VT = N->getValueType(0);
26042 EVT InVT = Op0.getValueType();
26043 EVT InSVT = InVT.getScalarType();
26044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26046 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26047 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26048 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26050 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26051 InVT.getVectorNumElements());
26052 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26054 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26055 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26057 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26063 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26064 const X86Subtarget *Subtarget) {
26065 // First try to optimize away the conversion entirely when it's
26066 // conditionally from a constant. Vectors only.
26067 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26070 // Now move on to more general possibilities.
26071 SDValue Op0 = N->getOperand(0);
26072 EVT VT = N->getValueType(0);
26073 EVT InVT = Op0.getValueType();
26074 EVT InSVT = InVT.getScalarType();
26076 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26077 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26078 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26080 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26081 InVT.getVectorNumElements());
26082 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26083 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26086 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26087 // a 32-bit target where SSE doesn't support i64->FP operations.
26088 if (Op0.getOpcode() == ISD::LOAD) {
26089 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26090 EVT LdVT = Ld->getValueType(0);
26092 // This transformation is not supported if the result type is f16
26093 if (VT == MVT::f16)
26096 if (!Ld->isVolatile() && !VT.isVector() &&
26097 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26098 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26099 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26100 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26101 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26108 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26109 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26110 X86TargetLowering::DAGCombinerInfo &DCI) {
26111 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26112 // the result is either zero or one (depending on the input carry bit).
26113 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26114 if (X86::isZeroNode(N->getOperand(0)) &&
26115 X86::isZeroNode(N->getOperand(1)) &&
26116 // We don't have a good way to replace an EFLAGS use, so only do this when
26118 SDValue(N, 1).use_empty()) {
26120 EVT VT = N->getValueType(0);
26121 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26122 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26123 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26124 DAG.getConstant(X86::COND_B, DL,
26127 DAG.getConstant(1, DL, VT));
26128 return DCI.CombineTo(N, Res1, CarryOut);
26134 // fold (add Y, (sete X, 0)) -> adc 0, Y
26135 // (add Y, (setne X, 0)) -> sbb -1, Y
26136 // (sub (sete X, 0), Y) -> sbb 0, Y
26137 // (sub (setne X, 0), Y) -> adc -1, Y
26138 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26141 // Look through ZExts.
26142 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26143 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26146 SDValue SetCC = Ext.getOperand(0);
26147 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26150 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26151 if (CC != X86::COND_E && CC != X86::COND_NE)
26154 SDValue Cmp = SetCC.getOperand(1);
26155 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26156 !X86::isZeroNode(Cmp.getOperand(1)) ||
26157 !Cmp.getOperand(0).getValueType().isInteger())
26160 SDValue CmpOp0 = Cmp.getOperand(0);
26161 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26162 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26164 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26165 if (CC == X86::COND_NE)
26166 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26167 DL, OtherVal.getValueType(), OtherVal,
26168 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26170 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26171 DL, OtherVal.getValueType(), OtherVal,
26172 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26175 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26176 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26177 const X86Subtarget *Subtarget) {
26178 EVT VT = N->getValueType(0);
26179 SDValue Op0 = N->getOperand(0);
26180 SDValue Op1 = N->getOperand(1);
26182 // Try to synthesize horizontal adds from adds of shuffles.
26183 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26184 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26185 isHorizontalBinOp(Op0, Op1, true))
26186 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26188 return OptimizeConditionalInDecrement(N, DAG);
26191 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26192 const X86Subtarget *Subtarget) {
26193 SDValue Op0 = N->getOperand(0);
26194 SDValue Op1 = N->getOperand(1);
26196 // X86 can't encode an immediate LHS of a sub. See if we can push the
26197 // negation into a preceding instruction.
26198 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26199 // If the RHS of the sub is a XOR with one use and a constant, invert the
26200 // immediate. Then add one to the LHS of the sub so we can turn
26201 // X-Y -> X+~Y+1, saving one register.
26202 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26203 isa<ConstantSDNode>(Op1.getOperand(1))) {
26204 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26205 EVT VT = Op0.getValueType();
26206 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26208 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26209 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26210 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26214 // Try to synthesize horizontal adds from adds of shuffles.
26215 EVT VT = N->getValueType(0);
26216 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26217 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26218 isHorizontalBinOp(Op0, Op1, true))
26219 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26221 return OptimizeConditionalInDecrement(N, DAG);
26224 /// performVZEXTCombine - Performs build vector combines
26225 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26226 TargetLowering::DAGCombinerInfo &DCI,
26227 const X86Subtarget *Subtarget) {
26229 MVT VT = N->getSimpleValueType(0);
26230 SDValue Op = N->getOperand(0);
26231 MVT OpVT = Op.getSimpleValueType();
26232 MVT OpEltVT = OpVT.getVectorElementType();
26233 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26235 // (vzext (bitcast (vzext (x)) -> (vzext x)
26237 while (V.getOpcode() == ISD::BITCAST)
26238 V = V.getOperand(0);
26240 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26241 MVT InnerVT = V.getSimpleValueType();
26242 MVT InnerEltVT = InnerVT.getVectorElementType();
26244 // If the element sizes match exactly, we can just do one larger vzext. This
26245 // is always an exact type match as vzext operates on integer types.
26246 if (OpEltVT == InnerEltVT) {
26247 assert(OpVT == InnerVT && "Types must match for vzext!");
26248 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26251 // The only other way we can combine them is if only a single element of the
26252 // inner vzext is used in the input to the outer vzext.
26253 if (InnerEltVT.getSizeInBits() < InputBits)
26256 // In this case, the inner vzext is completely dead because we're going to
26257 // only look at bits inside of the low element. Just do the outer vzext on
26258 // a bitcast of the input to the inner.
26259 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26262 // Check if we can bypass extracting and re-inserting an element of an input
26263 // vector. Essentially:
26264 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26265 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26266 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26267 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26268 SDValue ExtractedV = V.getOperand(0);
26269 SDValue OrigV = ExtractedV.getOperand(0);
26270 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26271 if (ExtractIdx->getZExtValue() == 0) {
26272 MVT OrigVT = OrigV.getSimpleValueType();
26273 // Extract a subvector if necessary...
26274 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26275 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26276 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26277 OrigVT.getVectorNumElements() / Ratio);
26278 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26279 DAG.getIntPtrConstant(0, DL));
26281 Op = DAG.getBitcast(OpVT, OrigV);
26282 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26289 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26290 DAGCombinerInfo &DCI) const {
26291 SelectionDAG &DAG = DCI.DAG;
26292 switch (N->getOpcode()) {
26294 case ISD::EXTRACT_VECTOR_ELT:
26295 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26298 case X86ISD::SHRUNKBLEND:
26299 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26300 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26301 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26302 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26303 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26304 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26305 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26308 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26309 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26310 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26311 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26312 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26313 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26314 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26315 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26316 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26317 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26318 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26319 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26321 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26323 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26324 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26325 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26326 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26327 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26328 case ISD::ANY_EXTEND:
26329 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26330 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26331 case ISD::SIGN_EXTEND_INREG:
26332 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26333 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26334 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26335 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26336 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26337 case X86ISD::SHUFP: // Handle all target specific shuffles
26338 case X86ISD::PALIGNR:
26339 case X86ISD::UNPCKH:
26340 case X86ISD::UNPCKL:
26341 case X86ISD::MOVHLPS:
26342 case X86ISD::MOVLHPS:
26343 case X86ISD::PSHUFB:
26344 case X86ISD::PSHUFD:
26345 case X86ISD::PSHUFHW:
26346 case X86ISD::PSHUFLW:
26347 case X86ISD::MOVSS:
26348 case X86ISD::MOVSD:
26349 case X86ISD::VPERMILPI:
26350 case X86ISD::VPERM2X128:
26351 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26352 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26353 case X86ISD::INSERTPS: {
26354 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26355 return PerformINSERTPSCombine(N, DAG, Subtarget);
26358 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26364 /// isTypeDesirableForOp - Return true if the target has native support for
26365 /// the specified value type and it is 'desirable' to use the type for the
26366 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26367 /// instruction encodings are longer and some i16 instructions are slow.
26368 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26369 if (!isTypeLegal(VT))
26371 if (VT != MVT::i16)
26378 case ISD::SIGN_EXTEND:
26379 case ISD::ZERO_EXTEND:
26380 case ISD::ANY_EXTEND:
26393 /// IsDesirableToPromoteOp - This method query the target whether it is
26394 /// beneficial for dag combiner to promote the specified node. If true, it
26395 /// should return the desired promotion type by reference.
26396 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26397 EVT VT = Op.getValueType();
26398 if (VT != MVT::i16)
26401 bool Promote = false;
26402 bool Commute = false;
26403 switch (Op.getOpcode()) {
26406 LoadSDNode *LD = cast<LoadSDNode>(Op);
26407 // If the non-extending load has a single use and it's not live out, then it
26408 // might be folded.
26409 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26410 Op.hasOneUse()*/) {
26411 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26412 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26413 // The only case where we'd want to promote LOAD (rather then it being
26414 // promoted as an operand is when it's only use is liveout.
26415 if (UI->getOpcode() != ISD::CopyToReg)
26422 case ISD::SIGN_EXTEND:
26423 case ISD::ZERO_EXTEND:
26424 case ISD::ANY_EXTEND:
26429 SDValue N0 = Op.getOperand(0);
26430 // Look out for (store (shl (load), x)).
26431 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26444 SDValue N0 = Op.getOperand(0);
26445 SDValue N1 = Op.getOperand(1);
26446 if (!Commute && MayFoldLoad(N1))
26448 // Avoid disabling potential load folding opportunities.
26449 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26451 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26461 //===----------------------------------------------------------------------===//
26462 // X86 Inline Assembly Support
26463 //===----------------------------------------------------------------------===//
26465 // Helper to match a string separated by whitespace.
26466 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26467 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26469 for (StringRef Piece : Pieces) {
26470 if (!S.startswith(Piece)) // Check if the piece matches.
26473 S = S.substr(Piece.size());
26474 StringRef::size_type Pos = S.find_first_not_of(" \t");
26475 if (Pos == 0) // We matched a prefix.
26484 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26486 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26487 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26488 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26489 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26491 if (AsmPieces.size() == 3)
26493 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26500 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26501 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26503 std::string AsmStr = IA->getAsmString();
26505 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26506 if (!Ty || Ty->getBitWidth() % 16 != 0)
26509 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26510 SmallVector<StringRef, 4> AsmPieces;
26511 SplitString(AsmStr, AsmPieces, ";\n");
26513 switch (AsmPieces.size()) {
26514 default: return false;
26516 // FIXME: this should verify that we are targeting a 486 or better. If not,
26517 // we will turn this bswap into something that will be lowered to logical
26518 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26519 // lower so don't worry about this.
26521 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26522 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26523 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26524 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26525 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26526 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26527 // No need to check constraints, nothing other than the equivalent of
26528 // "=r,0" would be valid here.
26529 return IntrinsicLowering::LowerToByteSwap(CI);
26532 // rorw $$8, ${0:w} --> llvm.bswap.i16
26533 if (CI->getType()->isIntegerTy(16) &&
26534 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26535 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26536 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26538 StringRef ConstraintsStr = IA->getConstraintString();
26539 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26540 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26541 if (clobbersFlagRegisters(AsmPieces))
26542 return IntrinsicLowering::LowerToByteSwap(CI);
26546 if (CI->getType()->isIntegerTy(32) &&
26547 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26548 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26549 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26550 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26552 StringRef ConstraintsStr = IA->getConstraintString();
26553 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26554 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26555 if (clobbersFlagRegisters(AsmPieces))
26556 return IntrinsicLowering::LowerToByteSwap(CI);
26559 if (CI->getType()->isIntegerTy(64)) {
26560 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26561 if (Constraints.size() >= 2 &&
26562 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26563 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26564 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26565 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26566 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26567 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26568 return IntrinsicLowering::LowerToByteSwap(CI);
26576 /// getConstraintType - Given a constraint letter, return the type of
26577 /// constraint it is for this target.
26578 X86TargetLowering::ConstraintType
26579 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26580 if (Constraint.size() == 1) {
26581 switch (Constraint[0]) {
26592 return C_RegisterClass;
26616 return TargetLowering::getConstraintType(Constraint);
26619 /// Examine constraint type and operand type and determine a weight value.
26620 /// This object must already have been set up with the operand type
26621 /// and the current alternative constraint selected.
26622 TargetLowering::ConstraintWeight
26623 X86TargetLowering::getSingleConstraintMatchWeight(
26624 AsmOperandInfo &info, const char *constraint) const {
26625 ConstraintWeight weight = CW_Invalid;
26626 Value *CallOperandVal = info.CallOperandVal;
26627 // If we don't have a value, we can't do a match,
26628 // but allow it at the lowest weight.
26629 if (!CallOperandVal)
26631 Type *type = CallOperandVal->getType();
26632 // Look at the constraint type.
26633 switch (*constraint) {
26635 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26646 if (CallOperandVal->getType()->isIntegerTy())
26647 weight = CW_SpecificReg;
26652 if (type->isFloatingPointTy())
26653 weight = CW_SpecificReg;
26656 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26657 weight = CW_SpecificReg;
26661 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26662 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26663 weight = CW_Register;
26666 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26667 if (C->getZExtValue() <= 31)
26668 weight = CW_Constant;
26672 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26673 if (C->getZExtValue() <= 63)
26674 weight = CW_Constant;
26678 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26679 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26680 weight = CW_Constant;
26684 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26685 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26686 weight = CW_Constant;
26690 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26691 if (C->getZExtValue() <= 3)
26692 weight = CW_Constant;
26696 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26697 if (C->getZExtValue() <= 0xff)
26698 weight = CW_Constant;
26703 if (isa<ConstantFP>(CallOperandVal)) {
26704 weight = CW_Constant;
26708 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26709 if ((C->getSExtValue() >= -0x80000000LL) &&
26710 (C->getSExtValue() <= 0x7fffffffLL))
26711 weight = CW_Constant;
26715 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26716 if (C->getZExtValue() <= 0xffffffff)
26717 weight = CW_Constant;
26724 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26725 /// with another that has more specific requirements based on the type of the
26726 /// corresponding operand.
26727 const char *X86TargetLowering::
26728 LowerXConstraint(EVT ConstraintVT) const {
26729 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26730 // 'f' like normal targets.
26731 if (ConstraintVT.isFloatingPoint()) {
26732 if (Subtarget->hasSSE2())
26734 if (Subtarget->hasSSE1())
26738 return TargetLowering::LowerXConstraint(ConstraintVT);
26741 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26742 /// vector. If it is invalid, don't add anything to Ops.
26743 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26744 std::string &Constraint,
26745 std::vector<SDValue>&Ops,
26746 SelectionDAG &DAG) const {
26749 // Only support length 1 constraints for now.
26750 if (Constraint.length() > 1) return;
26752 char ConstraintLetter = Constraint[0];
26753 switch (ConstraintLetter) {
26756 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26757 if (C->getZExtValue() <= 31) {
26758 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26759 Op.getValueType());
26765 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26766 if (C->getZExtValue() <= 63) {
26767 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26768 Op.getValueType());
26774 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26775 if (isInt<8>(C->getSExtValue())) {
26776 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26777 Op.getValueType());
26783 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26784 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26785 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26786 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26787 Op.getValueType());
26793 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26794 if (C->getZExtValue() <= 3) {
26795 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26796 Op.getValueType());
26802 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26803 if (C->getZExtValue() <= 255) {
26804 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26805 Op.getValueType());
26811 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26812 if (C->getZExtValue() <= 127) {
26813 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26814 Op.getValueType());
26820 // 32-bit signed value
26821 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26822 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26823 C->getSExtValue())) {
26824 // Widen to 64 bits here to get it sign extended.
26825 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26828 // FIXME gcc accepts some relocatable values here too, but only in certain
26829 // memory models; it's complicated.
26834 // 32-bit unsigned value
26835 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26836 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26837 C->getZExtValue())) {
26838 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26839 Op.getValueType());
26843 // FIXME gcc accepts some relocatable values here too, but only in certain
26844 // memory models; it's complicated.
26848 // Literal immediates are always ok.
26849 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26850 // Widen to 64 bits here to get it sign extended.
26851 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26855 // In any sort of PIC mode addresses need to be computed at runtime by
26856 // adding in a register or some sort of table lookup. These can't
26857 // be used as immediates.
26858 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26861 // If we are in non-pic codegen mode, we allow the address of a global (with
26862 // an optional displacement) to be used with 'i'.
26863 GlobalAddressSDNode *GA = nullptr;
26864 int64_t Offset = 0;
26866 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26868 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26869 Offset += GA->getOffset();
26871 } else if (Op.getOpcode() == ISD::ADD) {
26872 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26873 Offset += C->getZExtValue();
26874 Op = Op.getOperand(0);
26877 } else if (Op.getOpcode() == ISD::SUB) {
26878 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26879 Offset += -C->getZExtValue();
26880 Op = Op.getOperand(0);
26885 // Otherwise, this isn't something we can handle, reject it.
26889 const GlobalValue *GV = GA->getGlobal();
26890 // If we require an extra load to get this address, as in PIC mode, we
26891 // can't accept it.
26892 if (isGlobalStubReference(
26893 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26896 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26897 GA->getValueType(0), Offset);
26902 if (Result.getNode()) {
26903 Ops.push_back(Result);
26906 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26909 std::pair<unsigned, const TargetRegisterClass *>
26910 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26911 StringRef Constraint,
26913 // First, see if this is a constraint that directly corresponds to an LLVM
26915 if (Constraint.size() == 1) {
26916 // GCC Constraint Letters
26917 switch (Constraint[0]) {
26919 // TODO: Slight differences here in allocation order and leaving
26920 // RIP in the class. Do they matter any more here than they do
26921 // in the normal allocation?
26922 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26923 if (Subtarget->is64Bit()) {
26924 if (VT == MVT::i32 || VT == MVT::f32)
26925 return std::make_pair(0U, &X86::GR32RegClass);
26926 if (VT == MVT::i16)
26927 return std::make_pair(0U, &X86::GR16RegClass);
26928 if (VT == MVT::i8 || VT == MVT::i1)
26929 return std::make_pair(0U, &X86::GR8RegClass);
26930 if (VT == MVT::i64 || VT == MVT::f64)
26931 return std::make_pair(0U, &X86::GR64RegClass);
26934 // 32-bit fallthrough
26935 case 'Q': // Q_REGS
26936 if (VT == MVT::i32 || VT == MVT::f32)
26937 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26938 if (VT == MVT::i16)
26939 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26940 if (VT == MVT::i8 || VT == MVT::i1)
26941 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26942 if (VT == MVT::i64)
26943 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26945 case 'r': // GENERAL_REGS
26946 case 'l': // INDEX_REGS
26947 if (VT == MVT::i8 || VT == MVT::i1)
26948 return std::make_pair(0U, &X86::GR8RegClass);
26949 if (VT == MVT::i16)
26950 return std::make_pair(0U, &X86::GR16RegClass);
26951 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26952 return std::make_pair(0U, &X86::GR32RegClass);
26953 return std::make_pair(0U, &X86::GR64RegClass);
26954 case 'R': // LEGACY_REGS
26955 if (VT == MVT::i8 || VT == MVT::i1)
26956 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26957 if (VT == MVT::i16)
26958 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26959 if (VT == MVT::i32 || !Subtarget->is64Bit())
26960 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26961 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26962 case 'f': // FP Stack registers.
26963 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26964 // value to the correct fpstack register class.
26965 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26966 return std::make_pair(0U, &X86::RFP32RegClass);
26967 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26968 return std::make_pair(0U, &X86::RFP64RegClass);
26969 return std::make_pair(0U, &X86::RFP80RegClass);
26970 case 'y': // MMX_REGS if MMX allowed.
26971 if (!Subtarget->hasMMX()) break;
26972 return std::make_pair(0U, &X86::VR64RegClass);
26973 case 'Y': // SSE_REGS if SSE2 allowed
26974 if (!Subtarget->hasSSE2()) break;
26976 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26977 if (!Subtarget->hasSSE1()) break;
26979 switch (VT.SimpleTy) {
26981 // Scalar SSE types.
26984 return std::make_pair(0U, &X86::FR32RegClass);
26987 return std::make_pair(0U, &X86::FR64RegClass);
26995 return std::make_pair(0U, &X86::VR128RegClass);
27003 return std::make_pair(0U, &X86::VR256RegClass);
27008 return std::make_pair(0U, &X86::VR512RegClass);
27014 // Use the default implementation in TargetLowering to convert the register
27015 // constraint into a member of a register class.
27016 std::pair<unsigned, const TargetRegisterClass*> Res;
27017 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27019 // Not found as a standard register?
27021 // Map st(0) -> st(7) -> ST0
27022 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27023 tolower(Constraint[1]) == 's' &&
27024 tolower(Constraint[2]) == 't' &&
27025 Constraint[3] == '(' &&
27026 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27027 Constraint[5] == ')' &&
27028 Constraint[6] == '}') {
27030 Res.first = X86::FP0+Constraint[4]-'0';
27031 Res.second = &X86::RFP80RegClass;
27035 // GCC allows "st(0)" to be called just plain "st".
27036 if (StringRef("{st}").equals_lower(Constraint)) {
27037 Res.first = X86::FP0;
27038 Res.second = &X86::RFP80RegClass;
27043 if (StringRef("{flags}").equals_lower(Constraint)) {
27044 Res.first = X86::EFLAGS;
27045 Res.second = &X86::CCRRegClass;
27049 // 'A' means EAX + EDX.
27050 if (Constraint == "A") {
27051 Res.first = X86::EAX;
27052 Res.second = &X86::GR32_ADRegClass;
27058 // Otherwise, check to see if this is a register class of the wrong value
27059 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27060 // turn into {ax},{dx}.
27061 // MVT::Other is used to specify clobber names.
27062 if (Res.second->hasType(VT) || VT == MVT::Other)
27063 return Res; // Correct type already, nothing to do.
27065 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27066 // return "eax". This should even work for things like getting 64bit integer
27067 // registers when given an f64 type.
27068 const TargetRegisterClass *Class = Res.second;
27069 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27070 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27071 unsigned Size = VT.getSizeInBits();
27072 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27073 : Size == 16 ? MVT::i16
27074 : Size == 32 ? MVT::i32
27075 : Size == 64 ? MVT::i64
27077 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27079 Res.first = DestReg;
27080 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27081 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27082 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27083 : &X86::GR64RegClass;
27084 assert(Res.second->contains(Res.first) && "Register in register class");
27086 // No register found/type mismatch.
27088 Res.second = nullptr;
27090 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27091 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27092 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27093 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27094 Class == &X86::VR512RegClass) {
27095 // Handle references to XMM physical registers that got mapped into the
27096 // wrong class. This can happen with constraints like {xmm0} where the
27097 // target independent register mapper will just pick the first match it can
27098 // find, ignoring the required type.
27100 if (VT == MVT::f32 || VT == MVT::i32)
27101 Res.second = &X86::FR32RegClass;
27102 else if (VT == MVT::f64 || VT == MVT::i64)
27103 Res.second = &X86::FR64RegClass;
27104 else if (X86::VR128RegClass.hasType(VT))
27105 Res.second = &X86::VR128RegClass;
27106 else if (X86::VR256RegClass.hasType(VT))
27107 Res.second = &X86::VR256RegClass;
27108 else if (X86::VR512RegClass.hasType(VT))
27109 Res.second = &X86::VR512RegClass;
27111 // Type mismatch and not a clobber: Return an error;
27113 Res.second = nullptr;
27120 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27121 const AddrMode &AM, Type *Ty,
27122 unsigned AS) const {
27123 // Scaling factors are not free at all.
27124 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27125 // will take 2 allocations in the out of order engine instead of 1
27126 // for plain addressing mode, i.e. inst (reg1).
27128 // vaddps (%rsi,%drx), %ymm0, %ymm1
27129 // Requires two allocations (one for the load, one for the computation)
27131 // vaddps (%rsi), %ymm0, %ymm1
27132 // Requires just 1 allocation, i.e., freeing allocations for other operations
27133 // and having less micro operations to execute.
27135 // For some X86 architectures, this is even worse because for instance for
27136 // stores, the complex addressing mode forces the instruction to use the
27137 // "load" ports instead of the dedicated "store" port.
27138 // E.g., on Haswell:
27139 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27140 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27141 if (isLegalAddressingMode(DL, AM, Ty, AS))
27142 // Scale represents reg2 * scale, thus account for 1
27143 // as soon as we use a second register.
27144 return AM.Scale != 0;
27148 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27149 // Integer division on x86 is expensive. However, when aggressively optimizing
27150 // for code size, we prefer to use a div instruction, as it is usually smaller
27151 // than the alternative sequence.
27152 // The exception to this is vector division. Since x86 doesn't have vector
27153 // integer division, leaving the division as-is is a loss even in terms of
27154 // size, because it will have to be scalarized, while the alternative code
27155 // sequence can be performed in vector form.
27156 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27157 Attribute::MinSize);
27158 return OptSize && !VT.isVector();