1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!Subtarget->useSoftFloat()) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!Subtarget->useSoftFloat()) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!Subtarget->useSoftFloat()) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
835 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
836 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
837 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
845 // Only provide customized ctpop vector bit twiddling for vector types we
846 // know to perform better than using the popcnt instructions on each vector
847 // element. If popcnt isn't supported, always provide the custom version.
848 if (!Subtarget->hasPOPCNT()) {
849 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
853 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
854 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
855 MVT VT = (MVT::SimpleValueType)i;
856 // Do not attempt to custom lower non-power-of-2 vectors
857 if (!isPowerOf2_32(VT.getVectorNumElements()))
859 // Do not attempt to custom lower non-128-bit vectors
860 if (!VT.is128BitVector())
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::VSELECT, VT, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
868 // We support custom legalizing of sext and anyext loads for specific
869 // memory vector types which we can load as a scalar (or sequence of
870 // scalars) and extend in-register to a legal 128-bit vector type. For sext
871 // loads these must work with a single scalar load.
872 for (MVT VT : MVT::integer_vector_valuetypes()) {
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
889 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to promote non-128-bit vectors
903 if (!VT.is128BitVector())
906 setOperationAction(ISD::AND, VT, Promote);
907 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
908 setOperationAction(ISD::OR, VT, Promote);
909 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
910 setOperationAction(ISD::XOR, VT, Promote);
911 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
912 setOperationAction(ISD::LOAD, VT, Promote);
913 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
914 setOperationAction(ISD::SELECT, VT, Promote);
915 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
918 // Custom lower v2i64 and v2f64 selects.
919 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
920 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
921 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
922 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
924 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 // FIXME: Do we need to handle scalar-to-vector here?
955 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
957 // We directly match byte blends in the backend as they match the VSELECT
959 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
961 // SSE41 brings specific instructions for doing vector sign extend even in
962 // cases where we don't have SRA.
963 for (MVT VT : MVT::integer_vector_valuetypes()) {
964 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
965 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
966 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
969 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
970 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
971 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
972 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
973 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
974 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
977 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
978 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
979 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
980 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
981 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
984 // i8 and i16 vectors are custom because the source register and source
985 // source memory operand types are not the same width. f32 vectors are
986 // custom since the immediate controlling the insert encodes additional
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
994 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
998 // FIXME: these should be Legal, but that's only for the case where
999 // the index is constant. For now custom expand to deal with that.
1000 if (Subtarget->is64Bit()) {
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1006 if (Subtarget->hasSSE2()) {
1007 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1008 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1010 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1011 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1013 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1014 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1016 // In the customized shift lowering, the legal cases in AVX2 will be
1018 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1019 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1021 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1022 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1024 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1027 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1028 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1029 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1030 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1031 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1032 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1033 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1035 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1036 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1037 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1039 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1047 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1049 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1050 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1052 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1058 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1060 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1061 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1062 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1063 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1065 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1066 // even though v8i16 is a legal type.
1067 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1068 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1071 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1072 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1073 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1075 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1076 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1078 for (MVT VT : MVT::fp_vector_valuetypes())
1079 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1081 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1084 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1085 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1087 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1088 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1090 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1091 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1092 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1093 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1095 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1096 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1097 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1099 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1100 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1101 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1103 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1104 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1105 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1106 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1107 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1108 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1109 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1110 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1112 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1113 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1114 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1115 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1116 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FMA, MVT::f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::f64, Legal);
1121 if (Subtarget->hasInt256()) {
1122 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1123 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1124 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1125 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1127 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1128 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1129 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1130 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1132 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1133 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1134 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1135 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1137 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1139 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1140 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1142 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1143 // when we have a 256bit-wide blend with immediate.
1144 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1146 // Only provide customized ctpop vector bit twiddling for vector types we
1147 // know to perform better than using the popcnt instructions on each
1148 // vector element. If popcnt isn't supported, always provide the custom
1150 if (!Subtarget->hasPOPCNT())
1151 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1153 // Custom CTPOP always performs better on natively supported v8i32
1154 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1156 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1157 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1158 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1159 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1160 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1161 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1162 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1164 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1165 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1166 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1167 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1168 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1169 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1171 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1172 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1173 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1174 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1177 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1181 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1182 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1183 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1184 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1187 // In the customized shift lowering, the legal cases in AVX2 will be
1189 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1190 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1192 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1195 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1197 // Custom lower several nodes for 256-bit types.
1198 for (MVT VT : MVT::vector_valuetypes()) {
1199 if (VT.getScalarSizeInBits() >= 32) {
1200 setOperationAction(ISD::MLOAD, VT, Legal);
1201 setOperationAction(ISD::MSTORE, VT, Legal);
1203 // Extract subvector is special because the value type
1204 // (result) is 128-bit but the source is 256-bit wide.
1205 if (VT.is128BitVector()) {
1206 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1208 // Do not attempt to custom lower other non-256-bit vectors
1209 if (!VT.is256BitVector())
1212 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1213 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1214 setOperationAction(ISD::VSELECT, VT, Custom);
1215 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1216 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1217 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1218 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1219 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1222 if (Subtarget->hasInt256())
1223 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1226 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1227 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1228 MVT VT = (MVT::SimpleValueType)i;
1230 // Do not attempt to promote non-256-bit vectors
1231 if (!VT.is256BitVector())
1234 setOperationAction(ISD::AND, VT, Promote);
1235 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1236 setOperationAction(ISD::OR, VT, Promote);
1237 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1238 setOperationAction(ISD::XOR, VT, Promote);
1239 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1240 setOperationAction(ISD::LOAD, VT, Promote);
1241 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1242 setOperationAction(ISD::SELECT, VT, Promote);
1243 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1247 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1248 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1249 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1250 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1251 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1253 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1254 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1255 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1257 for (MVT VT : MVT::fp_vector_valuetypes())
1258 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1260 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1261 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1262 setOperationAction(ISD::XOR, MVT::i1, Legal);
1263 setOperationAction(ISD::OR, MVT::i1, Legal);
1264 setOperationAction(ISD::AND, MVT::i1, Legal);
1265 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1266 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1267 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1268 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1269 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1271 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1272 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1273 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1274 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1275 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1276 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1278 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1279 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1280 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1281 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1282 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1283 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1284 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1285 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1287 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1288 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1289 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1290 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1291 if (Subtarget->is64Bit()) {
1292 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1293 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1294 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1295 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1297 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1298 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1299 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1300 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1301 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1302 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1303 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1304 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1305 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1306 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1307 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1308 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1309 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1310 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1311 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1312 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1314 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1315 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1316 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1317 if (Subtarget->hasDQI()) {
1318 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1319 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1321 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1322 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1323 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1324 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1325 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1326 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1327 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1328 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1329 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1330 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1331 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1332 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1333 if (Subtarget->hasDQI()) {
1334 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1335 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1337 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1339 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1341 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1343 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1348 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1349 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1350 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1351 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1352 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1354 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1355 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1357 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1359 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1360 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1361 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1362 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1363 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1364 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1365 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1366 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1367 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1368 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1371 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1372 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1374 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1375 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1377 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1379 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1380 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1382 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1383 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1385 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1386 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1388 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1389 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1390 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1391 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1392 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1393 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1395 if (Subtarget->hasCDI()) {
1396 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1397 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1401 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1402 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1404 // Custom lower several nodes.
1405 for (MVT VT : MVT::vector_valuetypes()) {
1406 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1408 setOperationAction(ISD::AND, VT, Legal);
1409 setOperationAction(ISD::OR, VT, Legal);
1410 setOperationAction(ISD::XOR, VT, Legal);
1412 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1413 setOperationAction(ISD::MGATHER, VT, Custom);
1414 setOperationAction(ISD::MSCATTER, VT, Custom);
1416 // Extract subvector is special because the value type
1417 // (result) is 256/128-bit but the source is 512-bit wide.
1418 if (VT.is128BitVector() || VT.is256BitVector()) {
1419 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1421 if (VT.getVectorElementType() == MVT::i1)
1422 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1424 // Do not attempt to custom lower other non-512-bit vectors
1425 if (!VT.is512BitVector())
1428 if (EltSize >= 32) {
1429 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1430 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1431 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1432 setOperationAction(ISD::VSELECT, VT, Legal);
1433 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1434 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1435 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1436 setOperationAction(ISD::MLOAD, VT, Legal);
1437 setOperationAction(ISD::MSTORE, VT, Legal);
1440 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1441 MVT VT = (MVT::SimpleValueType)i;
1443 // Do not attempt to promote non-512-bit vectors.
1444 if (!VT.is512BitVector())
1447 setOperationAction(ISD::SELECT, VT, Promote);
1448 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1452 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1453 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1454 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1456 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1457 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1459 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1460 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1463 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1464 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1465 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1466 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1467 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1468 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1470 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1471 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1475 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1476 const MVT VT = (MVT::SimpleValueType)i;
1478 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1480 // Do not attempt to promote non-512-bit vectors.
1481 if (!VT.is512BitVector())
1485 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1486 setOperationAction(ISD::VSELECT, VT, Legal);
1491 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1492 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1493 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1495 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1496 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1497 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1498 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1499 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1500 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1501 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1502 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1507 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1510 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1511 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1514 // We want to custom lower some of our intrinsics.
1515 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1516 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1517 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1518 if (!Subtarget->is64Bit())
1519 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1521 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1522 // handle type legalization for these operations here.
1524 // FIXME: We really should do custom legalization for addition and
1525 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1526 // than generic legalization for 64-bit multiplication-with-overflow, though.
1527 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1528 // Add/Sub/Mul with overflow operations are custom lowered.
1530 setOperationAction(ISD::SADDO, VT, Custom);
1531 setOperationAction(ISD::UADDO, VT, Custom);
1532 setOperationAction(ISD::SSUBO, VT, Custom);
1533 setOperationAction(ISD::USUBO, VT, Custom);
1534 setOperationAction(ISD::SMULO, VT, Custom);
1535 setOperationAction(ISD::UMULO, VT, Custom);
1539 if (!Subtarget->is64Bit()) {
1540 // These libcalls are not available in 32-bit.
1541 setLibcallName(RTLIB::SHL_I128, nullptr);
1542 setLibcallName(RTLIB::SRL_I128, nullptr);
1543 setLibcallName(RTLIB::SRA_I128, nullptr);
1546 // Combine sin / cos into one node or libcall if possible.
1547 if (Subtarget->hasSinCos()) {
1548 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1549 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1550 if (Subtarget->isTargetDarwin()) {
1551 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1552 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1553 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1554 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1558 if (Subtarget->isTargetWin64()) {
1559 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1560 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1561 setOperationAction(ISD::SREM, MVT::i128, Custom);
1562 setOperationAction(ISD::UREM, MVT::i128, Custom);
1563 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1564 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1567 // We have target-specific dag combine patterns for the following nodes:
1568 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1569 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1570 setTargetDAGCombine(ISD::BITCAST);
1571 setTargetDAGCombine(ISD::VSELECT);
1572 setTargetDAGCombine(ISD::SELECT);
1573 setTargetDAGCombine(ISD::SHL);
1574 setTargetDAGCombine(ISD::SRA);
1575 setTargetDAGCombine(ISD::SRL);
1576 setTargetDAGCombine(ISD::OR);
1577 setTargetDAGCombine(ISD::AND);
1578 setTargetDAGCombine(ISD::ADD);
1579 setTargetDAGCombine(ISD::FADD);
1580 setTargetDAGCombine(ISD::FSUB);
1581 setTargetDAGCombine(ISD::FMA);
1582 setTargetDAGCombine(ISD::SUB);
1583 setTargetDAGCombine(ISD::LOAD);
1584 setTargetDAGCombine(ISD::MLOAD);
1585 setTargetDAGCombine(ISD::STORE);
1586 setTargetDAGCombine(ISD::MSTORE);
1587 setTargetDAGCombine(ISD::ZERO_EXTEND);
1588 setTargetDAGCombine(ISD::ANY_EXTEND);
1589 setTargetDAGCombine(ISD::SIGN_EXTEND);
1590 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1591 setTargetDAGCombine(ISD::SINT_TO_FP);
1592 setTargetDAGCombine(ISD::SETCC);
1593 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1594 setTargetDAGCombine(ISD::BUILD_VECTOR);
1595 setTargetDAGCombine(ISD::MUL);
1596 setTargetDAGCombine(ISD::XOR);
1598 computeRegisterProperties(Subtarget->getRegisterInfo());
1600 // On Darwin, -Os means optimize for size without hurting performance,
1601 // do not reduce the limit.
1602 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1603 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1604 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1605 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1606 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1607 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1608 setPrefLoopAlignment(4); // 2^4 bytes.
1610 // Predictable cmov don't hurt on atom because it's in-order.
1611 PredictableSelectIsExpensive = !Subtarget->isAtom();
1612 EnableExtLdPromotion = true;
1613 setPrefFunctionAlignment(4); // 2^4 bytes.
1615 verifyIntrinsicTables();
1618 // This has so far only been implemented for 64-bit MachO.
1619 bool X86TargetLowering::useLoadStackGuardNode() const {
1620 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1623 TargetLoweringBase::LegalizeTypeAction
1624 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1625 if (ExperimentalVectorWideningLegalization &&
1626 VT.getVectorNumElements() != 1 &&
1627 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1628 return TypeWidenVector;
1630 return TargetLoweringBase::getPreferredVectorAction(VT);
1633 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1635 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1637 const unsigned NumElts = VT.getVectorNumElements();
1638 const EVT EltVT = VT.getVectorElementType();
1639 if (VT.is512BitVector()) {
1640 if (Subtarget->hasAVX512())
1641 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1642 EltVT == MVT::f32 || EltVT == MVT::f64)
1644 case 8: return MVT::v8i1;
1645 case 16: return MVT::v16i1;
1647 if (Subtarget->hasBWI())
1648 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1650 case 32: return MVT::v32i1;
1651 case 64: return MVT::v64i1;
1655 if (VT.is256BitVector() || VT.is128BitVector()) {
1656 if (Subtarget->hasVLX())
1657 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1658 EltVT == MVT::f32 || EltVT == MVT::f64)
1660 case 2: return MVT::v2i1;
1661 case 4: return MVT::v4i1;
1662 case 8: return MVT::v8i1;
1664 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1665 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1667 case 8: return MVT::v8i1;
1668 case 16: return MVT::v16i1;
1669 case 32: return MVT::v32i1;
1673 return VT.changeVectorElementTypeToInteger();
1676 /// Helper for getByValTypeAlignment to determine
1677 /// the desired ByVal argument alignment.
1678 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1681 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1682 if (VTy->getBitWidth() == 128)
1684 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1685 unsigned EltAlign = 0;
1686 getMaxByValAlign(ATy->getElementType(), EltAlign);
1687 if (EltAlign > MaxAlign)
1688 MaxAlign = EltAlign;
1689 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1690 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1691 unsigned EltAlign = 0;
1692 getMaxByValAlign(STy->getElementType(i), EltAlign);
1693 if (EltAlign > MaxAlign)
1694 MaxAlign = EltAlign;
1701 /// Return the desired alignment for ByVal aggregate
1702 /// function arguments in the caller parameter area. For X86, aggregates
1703 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1704 /// are at 4-byte boundaries.
1705 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1706 if (Subtarget->is64Bit()) {
1707 // Max of 8 and alignment of type.
1708 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1715 if (Subtarget->hasSSE1())
1716 getMaxByValAlign(Ty, Align);
1720 /// Returns the target specific optimal type for load
1721 /// and store operations as a result of memset, memcpy, and memmove
1722 /// lowering. If DstAlign is zero that means it's safe to destination
1723 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1724 /// means there isn't a need to check it against alignment requirement,
1725 /// probably because the source does not need to be loaded. If 'IsMemset' is
1726 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1727 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1728 /// source is constant so it does not need to be loaded.
1729 /// It returns EVT::Other if the type should be determined using generic
1730 /// target-independent logic.
1732 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1733 unsigned DstAlign, unsigned SrcAlign,
1734 bool IsMemset, bool ZeroMemset,
1736 MachineFunction &MF) const {
1737 const Function *F = MF.getFunction();
1738 if ((!IsMemset || ZeroMemset) &&
1739 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1741 (Subtarget->isUnalignedMemAccessFast() ||
1742 ((DstAlign == 0 || DstAlign >= 16) &&
1743 (SrcAlign == 0 || SrcAlign >= 16)))) {
1745 if (Subtarget->hasInt256())
1747 if (Subtarget->hasFp256())
1750 if (Subtarget->hasSSE2())
1752 if (Subtarget->hasSSE1())
1754 } else if (!MemcpyStrSrc && Size >= 8 &&
1755 !Subtarget->is64Bit() &&
1756 Subtarget->hasSSE2()) {
1757 // Do not use f64 to lower memcpy if source is string constant. It's
1758 // better to use i32 to avoid the loads.
1762 if (Subtarget->is64Bit() && Size >= 8)
1767 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1769 return X86ScalarSSEf32;
1770 else if (VT == MVT::f64)
1771 return X86ScalarSSEf64;
1776 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1781 *Fast = Subtarget->isUnalignedMemAccessFast();
1785 /// Return the entry encoding for a jump table in the
1786 /// current function. The returned value is a member of the
1787 /// MachineJumpTableInfo::JTEntryKind enum.
1788 unsigned X86TargetLowering::getJumpTableEncoding() const {
1789 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1791 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1792 Subtarget->isPICStyleGOT())
1793 return MachineJumpTableInfo::EK_Custom32;
1795 // Otherwise, use the normal jump table encoding heuristics.
1796 return TargetLowering::getJumpTableEncoding();
1799 bool X86TargetLowering::useSoftFloat() const {
1800 return Subtarget->useSoftFloat();
1804 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1805 const MachineBasicBlock *MBB,
1806 unsigned uid,MCContext &Ctx) const{
1807 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1808 Subtarget->isPICStyleGOT());
1809 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1811 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1812 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1815 /// Returns relocation base for the given PIC jumptable.
1816 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1817 SelectionDAG &DAG) const {
1818 if (!Subtarget->is64Bit())
1819 // This doesn't have SDLoc associated with it, but is not really the
1820 // same as a Register.
1821 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1825 /// This returns the relocation base for the given PIC jumptable,
1826 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1827 const MCExpr *X86TargetLowering::
1828 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1829 MCContext &Ctx) const {
1830 // X86-64 uses RIP relative addressing based on the jump table label.
1831 if (Subtarget->isPICStyleRIPRel())
1832 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1834 // Otherwise, the reference is relative to the PIC base.
1835 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1838 std::pair<const TargetRegisterClass *, uint8_t>
1839 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1841 const TargetRegisterClass *RRC = nullptr;
1843 switch (VT.SimpleTy) {
1845 return TargetLowering::findRepresentativeClass(TRI, VT);
1846 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1847 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1850 RRC = &X86::VR64RegClass;
1852 case MVT::f32: case MVT::f64:
1853 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1854 case MVT::v4f32: case MVT::v2f64:
1855 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1857 RRC = &X86::VR128RegClass;
1860 return std::make_pair(RRC, Cost);
1863 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1864 unsigned &Offset) const {
1865 if (!Subtarget->isTargetLinux())
1868 if (Subtarget->is64Bit()) {
1869 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1871 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1883 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1884 unsigned DestAS) const {
1885 assert(SrcAS != DestAS && "Expected different address spaces!");
1887 return SrcAS < 256 && DestAS < 256;
1890 //===----------------------------------------------------------------------===//
1891 // Return Value Calling Convention Implementation
1892 //===----------------------------------------------------------------------===//
1894 #include "X86GenCallingConv.inc"
1897 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1898 MachineFunction &MF, bool isVarArg,
1899 const SmallVectorImpl<ISD::OutputArg> &Outs,
1900 LLVMContext &Context) const {
1901 SmallVector<CCValAssign, 16> RVLocs;
1902 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1903 return CCInfo.CheckReturn(Outs, RetCC_X86);
1906 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1907 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1912 X86TargetLowering::LowerReturn(SDValue Chain,
1913 CallingConv::ID CallConv, bool isVarArg,
1914 const SmallVectorImpl<ISD::OutputArg> &Outs,
1915 const SmallVectorImpl<SDValue> &OutVals,
1916 SDLoc dl, SelectionDAG &DAG) const {
1917 MachineFunction &MF = DAG.getMachineFunction();
1918 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1920 SmallVector<CCValAssign, 16> RVLocs;
1921 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1922 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1925 SmallVector<SDValue, 6> RetOps;
1926 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1927 // Operand #1 = Bytes To Pop
1928 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1931 // Copy the result values into the output registers.
1932 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1933 CCValAssign &VA = RVLocs[i];
1934 assert(VA.isRegLoc() && "Can only return in registers!");
1935 SDValue ValToCopy = OutVals[i];
1936 EVT ValVT = ValToCopy.getValueType();
1938 // Promote values to the appropriate types.
1939 if (VA.getLocInfo() == CCValAssign::SExt)
1940 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1941 else if (VA.getLocInfo() == CCValAssign::ZExt)
1942 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1943 else if (VA.getLocInfo() == CCValAssign::AExt) {
1944 if (ValVT.getScalarType() == MVT::i1)
1945 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1947 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1949 else if (VA.getLocInfo() == CCValAssign::BCvt)
1950 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1952 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1953 "Unexpected FP-extend for return value.");
1955 // If this is x86-64, and we disabled SSE, we can't return FP values,
1956 // or SSE or MMX vectors.
1957 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1958 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1959 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1960 report_fatal_error("SSE register return with SSE disabled");
1962 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1963 // llvm-gcc has never done it right and no one has noticed, so this
1964 // should be OK for now.
1965 if (ValVT == MVT::f64 &&
1966 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1967 report_fatal_error("SSE2 register return with SSE2 disabled");
1969 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1970 // the RET instruction and handled by the FP Stackifier.
1971 if (VA.getLocReg() == X86::FP0 ||
1972 VA.getLocReg() == X86::FP1) {
1973 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1974 // change the value to the FP stack register class.
1975 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1976 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1977 RetOps.push_back(ValToCopy);
1978 // Don't emit a copytoreg.
1982 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1983 // which is returned in RAX / RDX.
1984 if (Subtarget->is64Bit()) {
1985 if (ValVT == MVT::x86mmx) {
1986 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1987 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1988 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1990 // If we don't have SSE2 available, convert to v4f32 so the generated
1991 // register is legal.
1992 if (!Subtarget->hasSSE2())
1993 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1998 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1999 Flag = Chain.getValue(1);
2000 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2003 // The x86-64 ABIs require that for returning structs by value we copy
2004 // the sret argument into %rax/%eax (depending on ABI) for the return.
2005 // Win32 requires us to put the sret argument to %eax as well.
2006 // We saved the argument into a virtual register in the entry block,
2007 // so now we copy the value out and into %rax/%eax.
2009 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2010 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2011 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2012 // either case FuncInfo->setSRetReturnReg() will have been called.
2013 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2014 assert((Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) &&
2015 "No need for an sret register");
2016 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2019 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2020 X86::RAX : X86::EAX;
2021 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2022 Flag = Chain.getValue(1);
2024 // RAX/EAX now acts like a return value.
2025 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2028 RetOps[0] = Chain; // Update chain.
2030 // Add the flag if we have it.
2032 RetOps.push_back(Flag);
2034 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2037 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2038 if (N->getNumValues() != 1)
2040 if (!N->hasNUsesOfValue(1, 0))
2043 SDValue TCChain = Chain;
2044 SDNode *Copy = *N->use_begin();
2045 if (Copy->getOpcode() == ISD::CopyToReg) {
2046 // If the copy has a glue operand, we conservatively assume it isn't safe to
2047 // perform a tail call.
2048 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2050 TCChain = Copy->getOperand(0);
2051 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2054 bool HasRet = false;
2055 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2057 if (UI->getOpcode() != X86ISD::RET_FLAG)
2059 // If we are returning more than one value, we can definitely
2060 // not make a tail call see PR19530
2061 if (UI->getNumOperands() > 4)
2063 if (UI->getNumOperands() == 4 &&
2064 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2077 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2078 ISD::NodeType ExtendKind) const {
2080 // TODO: Is this also valid on 32-bit?
2081 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2082 ReturnMVT = MVT::i8;
2084 ReturnMVT = MVT::i32;
2086 EVT MinVT = getRegisterType(Context, ReturnMVT);
2087 return VT.bitsLT(MinVT) ? MinVT : VT;
2090 /// Lower the result values of a call into the
2091 /// appropriate copies out of appropriate physical registers.
2094 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2095 CallingConv::ID CallConv, bool isVarArg,
2096 const SmallVectorImpl<ISD::InputArg> &Ins,
2097 SDLoc dl, SelectionDAG &DAG,
2098 SmallVectorImpl<SDValue> &InVals) const {
2100 // Assign locations to each value returned by this call.
2101 SmallVector<CCValAssign, 16> RVLocs;
2102 bool Is64Bit = Subtarget->is64Bit();
2103 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2105 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2107 // Copy all of the result registers out of their specified physreg.
2108 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2109 CCValAssign &VA = RVLocs[i];
2110 EVT CopyVT = VA.getLocVT();
2112 // If this is x86-64, and we disabled SSE, we can't return FP values
2113 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2114 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2115 report_fatal_error("SSE register return with SSE disabled");
2118 // If we prefer to use the value in xmm registers, copy it out as f80 and
2119 // use a truncate to move it from fp stack reg to xmm reg.
2120 bool RoundAfterCopy = false;
2121 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2122 isScalarFPTypeInSSEReg(VA.getValVT())) {
2124 RoundAfterCopy = (CopyVT != VA.getLocVT());
2127 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2128 CopyVT, InFlag).getValue(1);
2129 SDValue Val = Chain.getValue(0);
2132 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2133 // This truncation won't change the value.
2134 DAG.getIntPtrConstant(1, dl));
2136 InFlag = Chain.getValue(2);
2137 InVals.push_back(Val);
2143 //===----------------------------------------------------------------------===//
2144 // C & StdCall & Fast Calling Convention implementation
2145 //===----------------------------------------------------------------------===//
2146 // StdCall calling convention seems to be standard for many Windows' API
2147 // routines and around. It differs from C calling convention just a little:
2148 // callee should clean up the stack, not caller. Symbols should be also
2149 // decorated in some fancy way :) It doesn't support any vector arguments.
2150 // For info on fast calling convention see Fast Calling Convention (tail call)
2151 // implementation LowerX86_32FastCCCallTo.
2153 /// CallIsStructReturn - Determines whether a call uses struct return
2155 enum StructReturnType {
2160 static StructReturnType
2161 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2163 return NotStructReturn;
2165 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2166 if (!Flags.isSRet())
2167 return NotStructReturn;
2168 if (Flags.isInReg())
2169 return RegStructReturn;
2170 return StackStructReturn;
2173 /// Determines whether a function uses struct return semantics.
2174 static StructReturnType
2175 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2177 return NotStructReturn;
2179 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2180 if (!Flags.isSRet())
2181 return NotStructReturn;
2182 if (Flags.isInReg())
2183 return RegStructReturn;
2184 return StackStructReturn;
2187 /// Make a copy of an aggregate at address specified by "Src" to address
2188 /// "Dst" with size and alignment information specified by the specific
2189 /// parameter attribute. The copy will be passed as a byval function parameter.
2191 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2192 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2194 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2196 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2197 /*isVolatile*/false, /*AlwaysInline=*/true,
2198 /*isTailCall*/false,
2199 MachinePointerInfo(), MachinePointerInfo());
2202 /// Return true if the calling convention is one that
2203 /// supports tail call optimization.
2204 static bool IsTailCallConvention(CallingConv::ID CC) {
2205 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2206 CC == CallingConv::HiPE);
2209 /// \brief Return true if the calling convention is a C calling convention.
2210 static bool IsCCallConvention(CallingConv::ID CC) {
2211 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2212 CC == CallingConv::X86_64_SysV);
2215 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2216 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2220 CallingConv::ID CalleeCC = CS.getCallingConv();
2221 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2227 /// Return true if the function is being made into
2228 /// a tailcall target by changing its ABI.
2229 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2230 bool GuaranteedTailCallOpt) {
2231 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2235 X86TargetLowering::LowerMemArgument(SDValue Chain,
2236 CallingConv::ID CallConv,
2237 const SmallVectorImpl<ISD::InputArg> &Ins,
2238 SDLoc dl, SelectionDAG &DAG,
2239 const CCValAssign &VA,
2240 MachineFrameInfo *MFI,
2242 // Create the nodes corresponding to a load from this parameter slot.
2243 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2244 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2245 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2246 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2249 // If value is passed by pointer we have address passed instead of the value
2251 if (VA.getLocInfo() == CCValAssign::Indirect)
2252 ValVT = VA.getLocVT();
2254 ValVT = VA.getValVT();
2256 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2257 // changed with more analysis.
2258 // In case of tail call optimization mark all arguments mutable. Since they
2259 // could be overwritten by lowering of arguments in case of a tail call.
2260 if (Flags.isByVal()) {
2261 unsigned Bytes = Flags.getByValSize();
2262 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2263 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2264 return DAG.getFrameIndex(FI, getPointerTy());
2266 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2267 VA.getLocMemOffset(), isImmutable);
2268 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2269 return DAG.getLoad(ValVT, dl, Chain, FIN,
2270 MachinePointerInfo::getFixedStack(FI),
2271 false, false, false, 0);
2275 // FIXME: Get this from tablegen.
2276 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2277 const X86Subtarget *Subtarget) {
2278 assert(Subtarget->is64Bit());
2280 if (Subtarget->isCallingConvWin64(CallConv)) {
2281 static const MCPhysReg GPR64ArgRegsWin64[] = {
2282 X86::RCX, X86::RDX, X86::R8, X86::R9
2284 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2287 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2288 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2290 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2293 // FIXME: Get this from tablegen.
2294 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2295 CallingConv::ID CallConv,
2296 const X86Subtarget *Subtarget) {
2297 assert(Subtarget->is64Bit());
2298 if (Subtarget->isCallingConvWin64(CallConv)) {
2299 // The XMM registers which might contain var arg parameters are shadowed
2300 // in their paired GPR. So we only need to save the GPR to their home
2302 // TODO: __vectorcall will change this.
2306 const Function *Fn = MF.getFunction();
2307 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2308 bool isSoftFloat = Subtarget->useSoftFloat();
2309 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2310 "SSE register cannot be used when SSE is disabled!");
2311 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2312 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2316 static const MCPhysReg XMMArgRegs64Bit[] = {
2317 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2318 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2320 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2324 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2325 CallingConv::ID CallConv,
2327 const SmallVectorImpl<ISD::InputArg> &Ins,
2330 SmallVectorImpl<SDValue> &InVals)
2332 MachineFunction &MF = DAG.getMachineFunction();
2333 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2334 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2336 const Function* Fn = MF.getFunction();
2337 if (Fn->hasExternalLinkage() &&
2338 Subtarget->isTargetCygMing() &&
2339 Fn->getName() == "main")
2340 FuncInfo->setForceFramePointer(true);
2342 MachineFrameInfo *MFI = MF.getFrameInfo();
2343 bool Is64Bit = Subtarget->is64Bit();
2344 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2346 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2347 "Var args not supported with calling convention fastcc, ghc or hipe");
2349 // Assign locations to all of the incoming arguments.
2350 SmallVector<CCValAssign, 16> ArgLocs;
2351 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2353 // Allocate shadow area for Win64
2355 CCInfo.AllocateStack(32, 8);
2357 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2359 unsigned LastVal = ~0U;
2361 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2362 CCValAssign &VA = ArgLocs[i];
2363 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2365 assert(VA.getValNo() != LastVal &&
2366 "Don't support value assigned to multiple locs yet");
2368 LastVal = VA.getValNo();
2370 if (VA.isRegLoc()) {
2371 EVT RegVT = VA.getLocVT();
2372 const TargetRegisterClass *RC;
2373 if (RegVT == MVT::i32)
2374 RC = &X86::GR32RegClass;
2375 else if (Is64Bit && RegVT == MVT::i64)
2376 RC = &X86::GR64RegClass;
2377 else if (RegVT == MVT::f32)
2378 RC = &X86::FR32RegClass;
2379 else if (RegVT == MVT::f64)
2380 RC = &X86::FR64RegClass;
2381 else if (RegVT.is512BitVector())
2382 RC = &X86::VR512RegClass;
2383 else if (RegVT.is256BitVector())
2384 RC = &X86::VR256RegClass;
2385 else if (RegVT.is128BitVector())
2386 RC = &X86::VR128RegClass;
2387 else if (RegVT == MVT::x86mmx)
2388 RC = &X86::VR64RegClass;
2389 else if (RegVT == MVT::i1)
2390 RC = &X86::VK1RegClass;
2391 else if (RegVT == MVT::v8i1)
2392 RC = &X86::VK8RegClass;
2393 else if (RegVT == MVT::v16i1)
2394 RC = &X86::VK16RegClass;
2395 else if (RegVT == MVT::v32i1)
2396 RC = &X86::VK32RegClass;
2397 else if (RegVT == MVT::v64i1)
2398 RC = &X86::VK64RegClass;
2400 llvm_unreachable("Unknown argument type!");
2402 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2403 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2405 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2406 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2408 if (VA.getLocInfo() == CCValAssign::SExt)
2409 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2410 DAG.getValueType(VA.getValVT()));
2411 else if (VA.getLocInfo() == CCValAssign::ZExt)
2412 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2413 DAG.getValueType(VA.getValVT()));
2414 else if (VA.getLocInfo() == CCValAssign::BCvt)
2415 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2417 if (VA.isExtInLoc()) {
2418 // Handle MMX values passed in XMM regs.
2419 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2420 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2422 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2425 assert(VA.isMemLoc());
2426 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2429 // If value is passed via pointer - do a load.
2430 if (VA.getLocInfo() == CCValAssign::Indirect)
2431 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2432 MachinePointerInfo(), false, false, false, 0);
2434 InVals.push_back(ArgValue);
2437 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2438 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2439 // The x86-64 ABIs require that for returning structs by value we copy
2440 // the sret argument into %rax/%eax (depending on ABI) for the return.
2441 // Win32 requires us to put the sret argument to %eax as well.
2442 // Save the argument into a virtual register so that we can access it
2443 // from the return points.
2444 if (Ins[i].Flags.isSRet()) {
2445 unsigned Reg = FuncInfo->getSRetReturnReg();
2447 MVT PtrTy = getPointerTy();
2448 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2449 FuncInfo->setSRetReturnReg(Reg);
2451 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2452 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2458 unsigned StackSize = CCInfo.getNextStackOffset();
2459 // Align stack specially for tail calls.
2460 if (FuncIsMadeTailCallSafe(CallConv,
2461 MF.getTarget().Options.GuaranteedTailCallOpt))
2462 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2464 // If the function takes variable number of arguments, make a frame index for
2465 // the start of the first vararg value... for expansion of llvm.va_start. We
2466 // can skip this if there are no va_start calls.
2467 if (MFI->hasVAStart() &&
2468 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2469 CallConv != CallingConv::X86_ThisCall))) {
2470 FuncInfo->setVarArgsFrameIndex(
2471 MFI->CreateFixedObject(1, StackSize, true));
2474 MachineModuleInfo &MMI = MF.getMMI();
2475 const Function *WinEHParent = nullptr;
2476 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2477 WinEHParent = MMI.getWinEHParent(Fn);
2478 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2479 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2481 // Figure out if XMM registers are in use.
2482 assert(!(Subtarget->useSoftFloat() &&
2483 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2484 "SSE register cannot be used when SSE is disabled!");
2486 // 64-bit calling conventions support varargs and register parameters, so we
2487 // have to do extra work to spill them in the prologue.
2488 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2489 // Find the first unallocated argument registers.
2490 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2491 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2492 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2493 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2494 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2495 "SSE register cannot be used when SSE is disabled!");
2497 // Gather all the live in physical registers.
2498 SmallVector<SDValue, 6> LiveGPRs;
2499 SmallVector<SDValue, 8> LiveXMMRegs;
2501 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2502 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2504 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2506 if (!ArgXMMs.empty()) {
2507 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2508 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2509 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2510 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2511 LiveXMMRegs.push_back(
2512 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2517 // Get to the caller-allocated home save location. Add 8 to account
2518 // for the return address.
2519 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2520 FuncInfo->setRegSaveFrameIndex(
2521 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2522 // Fixup to set vararg frame on shadow area (4 x i64).
2524 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2526 // For X86-64, if there are vararg parameters that are passed via
2527 // registers, then we must store them to their spots on the stack so
2528 // they may be loaded by deferencing the result of va_next.
2529 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2530 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2531 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2532 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2535 // Store the integer parameter registers.
2536 SmallVector<SDValue, 8> MemOps;
2537 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2539 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2540 for (SDValue Val : LiveGPRs) {
2541 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2542 DAG.getIntPtrConstant(Offset, dl));
2544 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2545 MachinePointerInfo::getFixedStack(
2546 FuncInfo->getRegSaveFrameIndex(), Offset),
2548 MemOps.push_back(Store);
2552 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2553 // Now store the XMM (fp + vector) parameter registers.
2554 SmallVector<SDValue, 12> SaveXMMOps;
2555 SaveXMMOps.push_back(Chain);
2556 SaveXMMOps.push_back(ALVal);
2557 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2558 FuncInfo->getRegSaveFrameIndex(), dl));
2559 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2560 FuncInfo->getVarArgsFPOffset(), dl));
2561 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2563 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2564 MVT::Other, SaveXMMOps));
2567 if (!MemOps.empty())
2568 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2569 } else if (IsWinEHOutlined) {
2570 // Get to the caller-allocated home save location. Add 8 to account
2571 // for the return address.
2572 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2573 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2574 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2576 MMI.getWinEHFuncInfo(Fn)
2577 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2578 FuncInfo->getRegSaveFrameIndex();
2580 // Store the second integer parameter (rdx) into rsp+16 relative to the
2581 // stack pointer at the entry of the function.
2583 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2584 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2585 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2586 Chain = DAG.getStore(
2587 Val.getValue(1), dl, Val, RSFIN,
2588 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2589 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2592 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2593 // Find the largest legal vector type.
2594 MVT VecVT = MVT::Other;
2595 // FIXME: Only some x86_32 calling conventions support AVX512.
2596 if (Subtarget->hasAVX512() &&
2597 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2598 CallConv == CallingConv::Intel_OCL_BI)))
2599 VecVT = MVT::v16f32;
2600 else if (Subtarget->hasAVX())
2602 else if (Subtarget->hasSSE2())
2605 // We forward some GPRs and some vector types.
2606 SmallVector<MVT, 2> RegParmTypes;
2607 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2608 RegParmTypes.push_back(IntVT);
2609 if (VecVT != MVT::Other)
2610 RegParmTypes.push_back(VecVT);
2612 // Compute the set of forwarded registers. The rest are scratch.
2613 SmallVectorImpl<ForwardedRegister> &Forwards =
2614 FuncInfo->getForwardedMustTailRegParms();
2615 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2617 // Conservatively forward AL on x86_64, since it might be used for varargs.
2618 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2619 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2620 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2623 // Copy all forwards from physical to virtual registers.
2624 for (ForwardedRegister &F : Forwards) {
2625 // FIXME: Can we use a less constrained schedule?
2626 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2627 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2628 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2632 // Some CCs need callee pop.
2633 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2634 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2635 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2637 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2638 // If this is an sret function, the return should pop the hidden pointer.
2639 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2640 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2641 argsAreStructReturn(Ins) == StackStructReturn)
2642 FuncInfo->setBytesToPopOnReturn(4);
2646 // RegSaveFrameIndex is X86-64 only.
2647 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2648 if (CallConv == CallingConv::X86_FastCall ||
2649 CallConv == CallingConv::X86_ThisCall)
2650 // fastcc functions can't have varargs.
2651 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2654 FuncInfo->setArgumentStackSize(StackSize);
2656 if (IsWinEHParent) {
2657 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2658 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2659 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2660 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2661 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2662 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2663 /*isVolatile=*/true,
2664 /*isNonTemporal=*/false, /*Alignment=*/0);
2671 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2672 SDValue StackPtr, SDValue Arg,
2673 SDLoc dl, SelectionDAG &DAG,
2674 const CCValAssign &VA,
2675 ISD::ArgFlagsTy Flags) const {
2676 unsigned LocMemOffset = VA.getLocMemOffset();
2677 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2678 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2679 if (Flags.isByVal())
2680 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2682 return DAG.getStore(Chain, dl, Arg, PtrOff,
2683 MachinePointerInfo::getStack(LocMemOffset),
2687 /// Emit a load of return address if tail call
2688 /// optimization is performed and it is required.
2690 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2691 SDValue &OutRetAddr, SDValue Chain,
2692 bool IsTailCall, bool Is64Bit,
2693 int FPDiff, SDLoc dl) const {
2694 // Adjust the Return address stack slot.
2695 EVT VT = getPointerTy();
2696 OutRetAddr = getReturnAddressFrameIndex(DAG);
2698 // Load the "old" Return address.
2699 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2700 false, false, false, 0);
2701 return SDValue(OutRetAddr.getNode(), 1);
2704 /// Emit a store of the return address if tail call
2705 /// optimization is performed and it is required (FPDiff!=0).
2706 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2707 SDValue Chain, SDValue RetAddrFrIdx,
2708 EVT PtrVT, unsigned SlotSize,
2709 int FPDiff, SDLoc dl) {
2710 // Store the return address to the appropriate stack slot.
2711 if (!FPDiff) return Chain;
2712 // Calculate the new stack slot for the return address.
2713 int NewReturnAddrFI =
2714 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2716 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2717 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2718 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2724 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2725 SmallVectorImpl<SDValue> &InVals) const {
2726 SelectionDAG &DAG = CLI.DAG;
2728 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2729 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2730 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2731 SDValue Chain = CLI.Chain;
2732 SDValue Callee = CLI.Callee;
2733 CallingConv::ID CallConv = CLI.CallConv;
2734 bool &isTailCall = CLI.IsTailCall;
2735 bool isVarArg = CLI.IsVarArg;
2737 MachineFunction &MF = DAG.getMachineFunction();
2738 bool Is64Bit = Subtarget->is64Bit();
2739 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2740 StructReturnType SR = callIsStructReturn(Outs);
2741 bool IsSibcall = false;
2742 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2744 if (MF.getTarget().Options.DisableTailCalls)
2747 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2749 // Force this to be a tail call. The verifier rules are enough to ensure
2750 // that we can lower this successfully without moving the return address
2753 } else if (isTailCall) {
2754 // Check if it's really possible to do a tail call.
2755 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2756 isVarArg, SR != NotStructReturn,
2757 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2758 Outs, OutVals, Ins, DAG);
2760 // Sibcalls are automatically detected tailcalls which do not require
2762 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2769 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2770 "Var args not supported with calling convention fastcc, ghc or hipe");
2772 // Analyze operands of the call, assigning locations to each operand.
2773 SmallVector<CCValAssign, 16> ArgLocs;
2774 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2776 // Allocate shadow area for Win64
2778 CCInfo.AllocateStack(32, 8);
2780 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2782 // Get a count of how many bytes are to be pushed on the stack.
2783 unsigned NumBytes = CCInfo.getNextStackOffset();
2785 // This is a sibcall. The memory operands are available in caller's
2786 // own caller's stack.
2788 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2789 IsTailCallConvention(CallConv))
2790 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2793 if (isTailCall && !IsSibcall && !IsMustTail) {
2794 // Lower arguments at fp - stackoffset + fpdiff.
2795 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2797 FPDiff = NumBytesCallerPushed - NumBytes;
2799 // Set the delta of movement of the returnaddr stackslot.
2800 // But only set if delta is greater than previous delta.
2801 if (FPDiff < X86Info->getTCReturnAddrDelta())
2802 X86Info->setTCReturnAddrDelta(FPDiff);
2805 unsigned NumBytesToPush = NumBytes;
2806 unsigned NumBytesToPop = NumBytes;
2808 // If we have an inalloca argument, all stack space has already been allocated
2809 // for us and be right at the top of the stack. We don't support multiple
2810 // arguments passed in memory when using inalloca.
2811 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2813 if (!ArgLocs.back().isMemLoc())
2814 report_fatal_error("cannot use inalloca attribute on a register "
2816 if (ArgLocs.back().getLocMemOffset() != 0)
2817 report_fatal_error("any parameter with the inalloca attribute must be "
2818 "the only memory argument");
2822 Chain = DAG.getCALLSEQ_START(
2823 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2825 SDValue RetAddrFrIdx;
2826 // Load return address for tail calls.
2827 if (isTailCall && FPDiff)
2828 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2829 Is64Bit, FPDiff, dl);
2831 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2832 SmallVector<SDValue, 8> MemOpChains;
2835 // Walk the register/memloc assignments, inserting copies/loads. In the case
2836 // of tail call optimization arguments are handle later.
2837 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2838 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2839 // Skip inalloca arguments, they have already been written.
2840 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2841 if (Flags.isInAlloca())
2844 CCValAssign &VA = ArgLocs[i];
2845 EVT RegVT = VA.getLocVT();
2846 SDValue Arg = OutVals[i];
2847 bool isByVal = Flags.isByVal();
2849 // Promote the value if needed.
2850 switch (VA.getLocInfo()) {
2851 default: llvm_unreachable("Unknown loc info!");
2852 case CCValAssign::Full: break;
2853 case CCValAssign::SExt:
2854 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2856 case CCValAssign::ZExt:
2857 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2859 case CCValAssign::AExt:
2860 if (Arg.getValueType().getScalarType() == MVT::i1)
2861 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2862 else if (RegVT.is128BitVector()) {
2863 // Special case: passing MMX values in XMM registers.
2864 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2865 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2866 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2868 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2870 case CCValAssign::BCvt:
2871 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2873 case CCValAssign::Indirect: {
2874 // Store the argument.
2875 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2876 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2877 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2878 MachinePointerInfo::getFixedStack(FI),
2885 if (VA.isRegLoc()) {
2886 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2887 if (isVarArg && IsWin64) {
2888 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2889 // shadow reg if callee is a varargs function.
2890 unsigned ShadowReg = 0;
2891 switch (VA.getLocReg()) {
2892 case X86::XMM0: ShadowReg = X86::RCX; break;
2893 case X86::XMM1: ShadowReg = X86::RDX; break;
2894 case X86::XMM2: ShadowReg = X86::R8; break;
2895 case X86::XMM3: ShadowReg = X86::R9; break;
2898 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2900 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2901 assert(VA.isMemLoc());
2902 if (!StackPtr.getNode())
2903 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2905 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2906 dl, DAG, VA, Flags));
2910 if (!MemOpChains.empty())
2911 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2913 if (Subtarget->isPICStyleGOT()) {
2914 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2917 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2918 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2920 // If we are tail calling and generating PIC/GOT style code load the
2921 // address of the callee into ECX. The value in ecx is used as target of
2922 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2923 // for tail calls on PIC/GOT architectures. Normally we would just put the
2924 // address of GOT into ebx and then call target@PLT. But for tail calls
2925 // ebx would be restored (since ebx is callee saved) before jumping to the
2928 // Note: The actual moving to ECX is done further down.
2929 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2930 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2931 !G->getGlobal()->hasProtectedVisibility())
2932 Callee = LowerGlobalAddress(Callee, DAG);
2933 else if (isa<ExternalSymbolSDNode>(Callee))
2934 Callee = LowerExternalSymbol(Callee, DAG);
2938 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2939 // From AMD64 ABI document:
2940 // For calls that may call functions that use varargs or stdargs
2941 // (prototype-less calls or calls to functions containing ellipsis (...) in
2942 // the declaration) %al is used as hidden argument to specify the number
2943 // of SSE registers used. The contents of %al do not need to match exactly
2944 // the number of registers, but must be an ubound on the number of SSE
2945 // registers used and is in the range 0 - 8 inclusive.
2947 // Count the number of XMM registers allocated.
2948 static const MCPhysReg XMMArgRegs[] = {
2949 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2950 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2952 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2953 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2954 && "SSE registers cannot be used when SSE is disabled");
2956 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2957 DAG.getConstant(NumXMMRegs, dl,
2961 if (isVarArg && IsMustTail) {
2962 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2963 for (const auto &F : Forwards) {
2964 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2965 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2969 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2970 // don't need this because the eligibility check rejects calls that require
2971 // shuffling arguments passed in memory.
2972 if (!IsSibcall && isTailCall) {
2973 // Force all the incoming stack arguments to be loaded from the stack
2974 // before any new outgoing arguments are stored to the stack, because the
2975 // outgoing stack slots may alias the incoming argument stack slots, and
2976 // the alias isn't otherwise explicit. This is slightly more conservative
2977 // than necessary, because it means that each store effectively depends
2978 // on every argument instead of just those arguments it would clobber.
2979 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2981 SmallVector<SDValue, 8> MemOpChains2;
2984 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2985 CCValAssign &VA = ArgLocs[i];
2988 assert(VA.isMemLoc());
2989 SDValue Arg = OutVals[i];
2990 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2991 // Skip inalloca arguments. They don't require any work.
2992 if (Flags.isInAlloca())
2994 // Create frame index.
2995 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2996 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2997 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2998 FIN = DAG.getFrameIndex(FI, getPointerTy());
3000 if (Flags.isByVal()) {
3001 // Copy relative to framepointer.
3002 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3003 if (!StackPtr.getNode())
3004 StackPtr = DAG.getCopyFromReg(Chain, dl,
3005 RegInfo->getStackRegister(),
3007 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3009 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3013 // Store relative to framepointer.
3014 MemOpChains2.push_back(
3015 DAG.getStore(ArgChain, dl, Arg, FIN,
3016 MachinePointerInfo::getFixedStack(FI),
3021 if (!MemOpChains2.empty())
3022 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3024 // Store the return address to the appropriate stack slot.
3025 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3026 getPointerTy(), RegInfo->getSlotSize(),
3030 // Build a sequence of copy-to-reg nodes chained together with token chain
3031 // and flag operands which copy the outgoing args into registers.
3033 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3034 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3035 RegsToPass[i].second, InFlag);
3036 InFlag = Chain.getValue(1);
3039 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3040 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3041 // In the 64-bit large code model, we have to make all calls
3042 // through a register, since the call instruction's 32-bit
3043 // pc-relative offset may not be large enough to hold the whole
3045 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3046 // If the callee is a GlobalAddress node (quite common, every direct call
3047 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3049 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3051 // We should use extra load for direct calls to dllimported functions in
3053 const GlobalValue *GV = G->getGlobal();
3054 if (!GV->hasDLLImportStorageClass()) {
3055 unsigned char OpFlags = 0;
3056 bool ExtraLoad = false;
3057 unsigned WrapperKind = ISD::DELETED_NODE;
3059 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3060 // external symbols most go through the PLT in PIC mode. If the symbol
3061 // has hidden or protected visibility, or if it is static or local, then
3062 // we don't need to use the PLT - we can directly call it.
3063 if (Subtarget->isTargetELF() &&
3064 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3065 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3066 OpFlags = X86II::MO_PLT;
3067 } else if (Subtarget->isPICStyleStubAny() &&
3068 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3069 (!Subtarget->getTargetTriple().isMacOSX() ||
3070 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3071 // PC-relative references to external symbols should go through $stub,
3072 // unless we're building with the leopard linker or later, which
3073 // automatically synthesizes these stubs.
3074 OpFlags = X86II::MO_DARWIN_STUB;
3075 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3076 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3077 // If the function is marked as non-lazy, generate an indirect call
3078 // which loads from the GOT directly. This avoids runtime overhead
3079 // at the cost of eager binding (and one extra byte of encoding).
3080 OpFlags = X86II::MO_GOTPCREL;
3081 WrapperKind = X86ISD::WrapperRIP;
3085 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3086 G->getOffset(), OpFlags);
3088 // Add a wrapper if needed.
3089 if (WrapperKind != ISD::DELETED_NODE)
3090 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3091 // Add extra indirection if needed.
3093 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3094 MachinePointerInfo::getGOT(),
3095 false, false, false, 0);
3097 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3098 unsigned char OpFlags = 0;
3100 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3101 // external symbols should go through the PLT.
3102 if (Subtarget->isTargetELF() &&
3103 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3104 OpFlags = X86II::MO_PLT;
3105 } else if (Subtarget->isPICStyleStubAny() &&
3106 (!Subtarget->getTargetTriple().isMacOSX() ||
3107 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3108 // PC-relative references to external symbols should go through $stub,
3109 // unless we're building with the leopard linker or later, which
3110 // automatically synthesizes these stubs.
3111 OpFlags = X86II::MO_DARWIN_STUB;
3114 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3116 } else if (Subtarget->isTarget64BitILP32() &&
3117 Callee->getValueType(0) == MVT::i32) {
3118 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3119 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3122 // Returns a chain & a flag for retval copy to use.
3123 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3124 SmallVector<SDValue, 8> Ops;
3126 if (!IsSibcall && isTailCall) {
3127 Chain = DAG.getCALLSEQ_END(Chain,
3128 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3129 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3130 InFlag = Chain.getValue(1);
3133 Ops.push_back(Chain);
3134 Ops.push_back(Callee);
3137 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3139 // Add argument registers to the end of the list so that they are known live
3141 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3142 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3143 RegsToPass[i].second.getValueType()));
3145 // Add a register mask operand representing the call-preserved registers.
3146 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3147 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3148 assert(Mask && "Missing call preserved mask for calling convention");
3149 Ops.push_back(DAG.getRegisterMask(Mask));
3151 if (InFlag.getNode())
3152 Ops.push_back(InFlag);
3156 //// If this is the first return lowered for this function, add the regs
3157 //// to the liveout set for the function.
3158 // This isn't right, although it's probably harmless on x86; liveouts
3159 // should be computed from returns not tail calls. Consider a void
3160 // function making a tail call to a function returning int.
3161 MF.getFrameInfo()->setHasTailCall();
3162 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3165 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3166 InFlag = Chain.getValue(1);
3168 // Create the CALLSEQ_END node.
3169 unsigned NumBytesForCalleeToPop;
3170 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3171 DAG.getTarget().Options.GuaranteedTailCallOpt))
3172 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3173 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3174 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3175 SR == StackStructReturn)
3176 // If this is a call to a struct-return function, the callee
3177 // pops the hidden struct pointer, so we have to push it back.
3178 // This is common for Darwin/X86, Linux & Mingw32 targets.
3179 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3180 NumBytesForCalleeToPop = 4;
3182 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3184 // Returns a flag for retval copy to use.
3186 Chain = DAG.getCALLSEQ_END(Chain,
3187 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3188 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3191 InFlag = Chain.getValue(1);
3194 // Handle result values, copying them out of physregs into vregs that we
3196 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3197 Ins, dl, DAG, InVals);
3200 //===----------------------------------------------------------------------===//
3201 // Fast Calling Convention (tail call) implementation
3202 //===----------------------------------------------------------------------===//
3204 // Like std call, callee cleans arguments, convention except that ECX is
3205 // reserved for storing the tail called function address. Only 2 registers are
3206 // free for argument passing (inreg). Tail call optimization is performed
3208 // * tailcallopt is enabled
3209 // * caller/callee are fastcc
3210 // On X86_64 architecture with GOT-style position independent code only local
3211 // (within module) calls are supported at the moment.
3212 // To keep the stack aligned according to platform abi the function
3213 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3214 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3215 // If a tail called function callee has more arguments than the caller the
3216 // caller needs to make sure that there is room to move the RETADDR to. This is
3217 // achieved by reserving an area the size of the argument delta right after the
3218 // original RETADDR, but before the saved framepointer or the spilled registers
3219 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3231 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3232 /// for a 16 byte align requirement.
3234 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3235 SelectionDAG& DAG) const {
3236 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3237 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3238 unsigned StackAlignment = TFI.getStackAlignment();
3239 uint64_t AlignMask = StackAlignment - 1;
3240 int64_t Offset = StackSize;
3241 unsigned SlotSize = RegInfo->getSlotSize();
3242 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3243 // Number smaller than 12 so just add the difference.
3244 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3246 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3247 Offset = ((~AlignMask) & Offset) + StackAlignment +
3248 (StackAlignment-SlotSize);
3253 /// MatchingStackOffset - Return true if the given stack call argument is
3254 /// already available in the same position (relatively) of the caller's
3255 /// incoming argument stack.
3257 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3258 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3259 const X86InstrInfo *TII) {
3260 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3262 if (Arg.getOpcode() == ISD::CopyFromReg) {
3263 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3264 if (!TargetRegisterInfo::isVirtualRegister(VR))
3266 MachineInstr *Def = MRI->getVRegDef(VR);
3269 if (!Flags.isByVal()) {
3270 if (!TII->isLoadFromStackSlot(Def, FI))
3273 unsigned Opcode = Def->getOpcode();
3274 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3275 Opcode == X86::LEA64_32r) &&
3276 Def->getOperand(1).isFI()) {
3277 FI = Def->getOperand(1).getIndex();
3278 Bytes = Flags.getByValSize();
3282 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3283 if (Flags.isByVal())
3284 // ByVal argument is passed in as a pointer but it's now being
3285 // dereferenced. e.g.
3286 // define @foo(%struct.X* %A) {
3287 // tail call @bar(%struct.X* byval %A)
3290 SDValue Ptr = Ld->getBasePtr();
3291 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3294 FI = FINode->getIndex();
3295 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3296 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3297 FI = FINode->getIndex();
3298 Bytes = Flags.getByValSize();
3302 assert(FI != INT_MAX);
3303 if (!MFI->isFixedObjectIndex(FI))
3305 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3308 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3309 /// for tail call optimization. Targets which want to do tail call
3310 /// optimization should implement this function.
3312 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3313 CallingConv::ID CalleeCC,
3315 bool isCalleeStructRet,
3316 bool isCallerStructRet,
3318 const SmallVectorImpl<ISD::OutputArg> &Outs,
3319 const SmallVectorImpl<SDValue> &OutVals,
3320 const SmallVectorImpl<ISD::InputArg> &Ins,
3321 SelectionDAG &DAG) const {
3322 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3325 // If -tailcallopt is specified, make fastcc functions tail-callable.
3326 const MachineFunction &MF = DAG.getMachineFunction();
3327 const Function *CallerF = MF.getFunction();
3329 // If the function return type is x86_fp80 and the callee return type is not,
3330 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3331 // perform a tailcall optimization here.
3332 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3335 CallingConv::ID CallerCC = CallerF->getCallingConv();
3336 bool CCMatch = CallerCC == CalleeCC;
3337 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3338 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3340 // Win64 functions have extra shadow space for argument homing. Don't do the
3341 // sibcall if the caller and callee have mismatched expectations for this
3343 if (IsCalleeWin64 != IsCallerWin64)
3346 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3347 if (IsTailCallConvention(CalleeCC) && CCMatch)
3352 // Look for obvious safe cases to perform tail call optimization that do not
3353 // require ABI changes. This is what gcc calls sibcall.
3355 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3356 // emit a special epilogue.
3357 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3358 if (RegInfo->needsStackRealignment(MF))
3361 // Also avoid sibcall optimization if either caller or callee uses struct
3362 // return semantics.
3363 if (isCalleeStructRet || isCallerStructRet)
3366 // An stdcall/thiscall caller is expected to clean up its arguments; the
3367 // callee isn't going to do that.
3368 // FIXME: this is more restrictive than needed. We could produce a tailcall
3369 // when the stack adjustment matches. For example, with a thiscall that takes
3370 // only one argument.
3371 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3372 CallerCC == CallingConv::X86_ThisCall))
3375 // Do not sibcall optimize vararg calls unless all arguments are passed via
3377 if (isVarArg && !Outs.empty()) {
3379 // Optimizing for varargs on Win64 is unlikely to be safe without
3380 // additional testing.
3381 if (IsCalleeWin64 || IsCallerWin64)
3384 SmallVector<CCValAssign, 16> ArgLocs;
3385 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3388 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3389 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3390 if (!ArgLocs[i].isRegLoc())
3394 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3395 // stack. Therefore, if it's not used by the call it is not safe to optimize
3396 // this into a sibcall.
3397 bool Unused = false;
3398 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3405 SmallVector<CCValAssign, 16> RVLocs;
3406 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3408 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3409 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3410 CCValAssign &VA = RVLocs[i];
3411 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3416 // If the calling conventions do not match, then we'd better make sure the
3417 // results are returned in the same way as what the caller expects.
3419 SmallVector<CCValAssign, 16> RVLocs1;
3420 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3422 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3424 SmallVector<CCValAssign, 16> RVLocs2;
3425 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3427 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3429 if (RVLocs1.size() != RVLocs2.size())
3431 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3432 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3434 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3436 if (RVLocs1[i].isRegLoc()) {
3437 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3440 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3446 // If the callee takes no arguments then go on to check the results of the
3448 if (!Outs.empty()) {
3449 // Check if stack adjustment is needed. For now, do not do this if any
3450 // argument is passed on the stack.
3451 SmallVector<CCValAssign, 16> ArgLocs;
3452 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3455 // Allocate shadow area for Win64
3457 CCInfo.AllocateStack(32, 8);
3459 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3460 if (CCInfo.getNextStackOffset()) {
3461 MachineFunction &MF = DAG.getMachineFunction();
3462 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3465 // Check if the arguments are already laid out in the right way as
3466 // the caller's fixed stack objects.
3467 MachineFrameInfo *MFI = MF.getFrameInfo();
3468 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3469 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3471 CCValAssign &VA = ArgLocs[i];
3472 SDValue Arg = OutVals[i];
3473 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3474 if (VA.getLocInfo() == CCValAssign::Indirect)
3476 if (!VA.isRegLoc()) {
3477 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3484 // If the tailcall address may be in a register, then make sure it's
3485 // possible to register allocate for it. In 32-bit, the call address can
3486 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3487 // callee-saved registers are restored. These happen to be the same
3488 // registers used to pass 'inreg' arguments so watch out for those.
3489 if (!Subtarget->is64Bit() &&
3490 ((!isa<GlobalAddressSDNode>(Callee) &&
3491 !isa<ExternalSymbolSDNode>(Callee)) ||
3492 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3493 unsigned NumInRegs = 0;
3494 // In PIC we need an extra register to formulate the address computation
3496 unsigned MaxInRegs =
3497 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3499 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3500 CCValAssign &VA = ArgLocs[i];
3503 unsigned Reg = VA.getLocReg();
3506 case X86::EAX: case X86::EDX: case X86::ECX:
3507 if (++NumInRegs == MaxInRegs)
3519 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3520 const TargetLibraryInfo *libInfo) const {
3521 return X86::createFastISel(funcInfo, libInfo);
3524 //===----------------------------------------------------------------------===//
3525 // Other Lowering Hooks
3526 //===----------------------------------------------------------------------===//
3528 static bool MayFoldLoad(SDValue Op) {
3529 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3532 static bool MayFoldIntoStore(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3536 static bool isTargetShuffle(unsigned Opcode) {
3538 default: return false;
3539 case X86ISD::BLENDI:
3540 case X86ISD::PSHUFB:
3541 case X86ISD::PSHUFD:
3542 case X86ISD::PSHUFHW:
3543 case X86ISD::PSHUFLW:
3545 case X86ISD::PALIGNR:
3546 case X86ISD::MOVLHPS:
3547 case X86ISD::MOVLHPD:
3548 case X86ISD::MOVHLPS:
3549 case X86ISD::MOVLPS:
3550 case X86ISD::MOVLPD:
3551 case X86ISD::MOVSHDUP:
3552 case X86ISD::MOVSLDUP:
3553 case X86ISD::MOVDDUP:
3556 case X86ISD::UNPCKL:
3557 case X86ISD::UNPCKH:
3558 case X86ISD::VPERMILPI:
3559 case X86ISD::VPERM2X128:
3560 case X86ISD::VPERMI:
3565 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3566 SDValue V1, unsigned TargetMask,
3567 SelectionDAG &DAG) {
3569 default: llvm_unreachable("Unknown x86 shuffle node");
3570 case X86ISD::PSHUFD:
3571 case X86ISD::PSHUFHW:
3572 case X86ISD::PSHUFLW:
3573 case X86ISD::VPERMILPI:
3574 case X86ISD::VPERMI:
3575 return DAG.getNode(Opc, dl, VT, V1,
3576 DAG.getConstant(TargetMask, dl, MVT::i8));
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::MOVLHPS:
3585 case X86ISD::MOVLHPD:
3586 case X86ISD::MOVHLPS:
3587 case X86ISD::MOVLPS:
3588 case X86ISD::MOVLPD:
3591 case X86ISD::UNPCKL:
3592 case X86ISD::UNPCKH:
3593 return DAG.getNode(Opc, dl, VT, V1, V2);
3597 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3598 MachineFunction &MF = DAG.getMachineFunction();
3599 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3600 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3601 int ReturnAddrIndex = FuncInfo->getRAIndex();
3603 if (ReturnAddrIndex == 0) {
3604 // Set up a frame object for the return address.
3605 unsigned SlotSize = RegInfo->getSlotSize();
3606 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3609 FuncInfo->setRAIndex(ReturnAddrIndex);
3612 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3615 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3616 bool hasSymbolicDisplacement) {
3617 // Offset should fit into 32 bit immediate field.
3618 if (!isInt<32>(Offset))
3621 // If we don't have a symbolic displacement - we don't have any extra
3623 if (!hasSymbolicDisplacement)
3626 // FIXME: Some tweaks might be needed for medium code model.
3627 if (M != CodeModel::Small && M != CodeModel::Kernel)
3630 // For small code model we assume that latest object is 16MB before end of 31
3631 // bits boundary. We may also accept pretty large negative constants knowing
3632 // that all objects are in the positive half of address space.
3633 if (M == CodeModel::Small && Offset < 16*1024*1024)
3636 // For kernel code model we know that all object resist in the negative half
3637 // of 32bits address space. We may not accept negative offsets, since they may
3638 // be just off and we may accept pretty large positive ones.
3639 if (M == CodeModel::Kernel && Offset >= 0)
3645 /// isCalleePop - Determines whether the callee is required to pop its
3646 /// own arguments. Callee pop is necessary to support tail calls.
3647 bool X86::isCalleePop(CallingConv::ID CallingConv,
3648 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3649 switch (CallingConv) {
3652 case CallingConv::X86_StdCall:
3653 case CallingConv::X86_FastCall:
3654 case CallingConv::X86_ThisCall:
3656 case CallingConv::Fast:
3657 case CallingConv::GHC:
3658 case CallingConv::HiPE:
3665 /// \brief Return true if the condition is an unsigned comparison operation.
3666 static bool isX86CCUnsigned(unsigned X86CC) {
3668 default: llvm_unreachable("Invalid integer condition!");
3669 case X86::COND_E: return true;
3670 case X86::COND_G: return false;
3671 case X86::COND_GE: return false;
3672 case X86::COND_L: return false;
3673 case X86::COND_LE: return false;
3674 case X86::COND_NE: return true;
3675 case X86::COND_B: return true;
3676 case X86::COND_A: return true;
3677 case X86::COND_BE: return true;
3678 case X86::COND_AE: return true;
3680 llvm_unreachable("covered switch fell through?!");
3683 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3684 /// specific condition code, returning the condition code and the LHS/RHS of the
3685 /// comparison to make.
3686 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3687 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3689 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3690 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3691 // X > -1 -> X == 0, jump !sign.
3692 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3693 return X86::COND_NS;
3695 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3696 // X < 0 -> X == 0, jump on sign.
3699 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3701 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3702 return X86::COND_LE;
3706 switch (SetCCOpcode) {
3707 default: llvm_unreachable("Invalid integer condition!");
3708 case ISD::SETEQ: return X86::COND_E;
3709 case ISD::SETGT: return X86::COND_G;
3710 case ISD::SETGE: return X86::COND_GE;
3711 case ISD::SETLT: return X86::COND_L;
3712 case ISD::SETLE: return X86::COND_LE;
3713 case ISD::SETNE: return X86::COND_NE;
3714 case ISD::SETULT: return X86::COND_B;
3715 case ISD::SETUGT: return X86::COND_A;
3716 case ISD::SETULE: return X86::COND_BE;
3717 case ISD::SETUGE: return X86::COND_AE;
3721 // First determine if it is required or is profitable to flip the operands.
3723 // If LHS is a foldable load, but RHS is not, flip the condition.
3724 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3725 !ISD::isNON_EXTLoad(RHS.getNode())) {
3726 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3727 std::swap(LHS, RHS);
3730 switch (SetCCOpcode) {
3736 std::swap(LHS, RHS);
3740 // On a floating point condition, the flags are set as follows:
3742 // 0 | 0 | 0 | X > Y
3743 // 0 | 0 | 1 | X < Y
3744 // 1 | 0 | 0 | X == Y
3745 // 1 | 1 | 1 | unordered
3746 switch (SetCCOpcode) {
3747 default: llvm_unreachable("Condcode should be pre-legalized away");
3749 case ISD::SETEQ: return X86::COND_E;
3750 case ISD::SETOLT: // flipped
3752 case ISD::SETGT: return X86::COND_A;
3753 case ISD::SETOLE: // flipped
3755 case ISD::SETGE: return X86::COND_AE;
3756 case ISD::SETUGT: // flipped
3758 case ISD::SETLT: return X86::COND_B;
3759 case ISD::SETUGE: // flipped
3761 case ISD::SETLE: return X86::COND_BE;
3763 case ISD::SETNE: return X86::COND_NE;
3764 case ISD::SETUO: return X86::COND_P;
3765 case ISD::SETO: return X86::COND_NP;
3767 case ISD::SETUNE: return X86::COND_INVALID;
3771 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3772 /// code. Current x86 isa includes the following FP cmov instructions:
3773 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3774 static bool hasFPCMov(unsigned X86CC) {
3790 /// isFPImmLegal - Returns true if the target can instruction select the
3791 /// specified FP immediate natively. If false, the legalizer will
3792 /// materialize the FP immediate as a load from a constant pool.
3793 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3794 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3795 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3801 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3802 ISD::LoadExtType ExtTy,
3804 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3805 // relocation target a movq or addq instruction: don't let the load shrink.
3806 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3807 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3808 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3809 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3813 /// \brief Returns true if it is beneficial to convert a load of a constant
3814 /// to just the constant itself.
3815 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3817 assert(Ty->isIntegerTy());
3819 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3820 if (BitSize == 0 || BitSize > 64)
3825 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3826 unsigned Index) const {
3827 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3830 return (Index == 0 || Index == ResVT.getVectorNumElements());
3833 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3834 // Speculate cttz only if we can directly use TZCNT.
3835 return Subtarget->hasBMI();
3838 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3839 // Speculate ctlz only if we can directly use LZCNT.
3840 return Subtarget->hasLZCNT();
3843 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3844 /// the specified range (L, H].
3845 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3846 return (Val < 0) || (Val >= Low && Val < Hi);
3849 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3850 /// specified value.
3851 static bool isUndefOrEqual(int Val, int CmpVal) {
3852 return (Val < 0 || Val == CmpVal);
3855 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3856 /// from position Pos and ending in Pos+Size, falls within the specified
3857 /// sequential range (Low, Low+Size]. or is undef.
3858 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3859 unsigned Pos, unsigned Size, int Low) {
3860 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3861 if (!isUndefOrEqual(Mask[i], Low))
3866 /// isVEXTRACTIndex - Return true if the specified
3867 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3868 /// suitable for instruction that extract 128 or 256 bit vectors
3869 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3870 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3874 // The index should be aligned on a vecWidth-bit boundary.
3876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3878 MVT VT = N->getSimpleValueType(0);
3879 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3880 bool Result = (Index * ElSize) % vecWidth == 0;
3885 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3886 /// operand specifies a subvector insert that is suitable for input to
3887 /// insertion of 128 or 256-bit subvectors
3888 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3889 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3890 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3892 // The index should be aligned on a vecWidth-bit boundary.
3894 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3896 MVT VT = N->getSimpleValueType(0);
3897 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3898 bool Result = (Index * ElSize) % vecWidth == 0;
3903 bool X86::isVINSERT128Index(SDNode *N) {
3904 return isVINSERTIndex(N, 128);
3907 bool X86::isVINSERT256Index(SDNode *N) {
3908 return isVINSERTIndex(N, 256);
3911 bool X86::isVEXTRACT128Index(SDNode *N) {
3912 return isVEXTRACTIndex(N, 128);
3915 bool X86::isVEXTRACT256Index(SDNode *N) {
3916 return isVEXTRACTIndex(N, 256);
3919 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3920 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3921 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3922 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3925 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3927 MVT VecVT = N->getOperand(0).getSimpleValueType();
3928 MVT ElVT = VecVT.getVectorElementType();
3930 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3931 return Index / NumElemsPerChunk;
3934 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3935 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3936 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3937 llvm_unreachable("Illegal insert subvector for VINSERT");
3940 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3942 MVT VecVT = N->getSimpleValueType(0);
3943 MVT ElVT = VecVT.getVectorElementType();
3945 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3946 return Index / NumElemsPerChunk;
3949 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3950 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3951 /// and VINSERTI128 instructions.
3952 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3953 return getExtractVEXTRACTImmediate(N, 128);
3956 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3957 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3958 /// and VINSERTI64x4 instructions.
3959 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3960 return getExtractVEXTRACTImmediate(N, 256);
3963 /// getInsertVINSERT128Immediate - Return the appropriate immediate
3964 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3965 /// and VINSERTI128 instructions.
3966 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
3967 return getInsertVINSERTImmediate(N, 128);
3970 /// getInsertVINSERT256Immediate - Return the appropriate immediate
3971 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
3972 /// and VINSERTI64x4 instructions.
3973 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
3974 return getInsertVINSERTImmediate(N, 256);
3977 /// isZero - Returns true if Elt is a constant integer zero
3978 static bool isZero(SDValue V) {
3979 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
3980 return C && C->isNullValue();
3983 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3985 bool X86::isZeroNode(SDValue Elt) {
3988 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
3989 return CFP->getValueAPF().isPosZero();
3993 /// getZeroVector - Returns a vector of specified type with all zero elements.
3995 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
3996 SelectionDAG &DAG, SDLoc dl) {
3997 assert(VT.isVector() && "Expected a vector type");
3999 // Always build SSE zero vectors as <4 x i32> bitcasted
4000 // to their dest type. This ensures they get CSE'd.
4002 if (VT.is128BitVector()) { // SSE
4003 if (Subtarget->hasSSE2()) { // SSE2
4004 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4005 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4007 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4008 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4010 } else if (VT.is256BitVector()) { // AVX
4011 if (Subtarget->hasInt256()) { // AVX2
4012 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4013 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4014 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4016 // 256-bit logic and arithmetic instructions in AVX are all
4017 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4018 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4019 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4020 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4022 } else if (VT.is512BitVector()) { // AVX-512
4023 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4024 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4025 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4026 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4027 } else if (VT.getScalarType() == MVT::i1) {
4029 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4030 && "Unexpected vector type");
4031 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4032 && "Unexpected vector type");
4033 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4034 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4035 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4037 llvm_unreachable("Unexpected vector type");
4039 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4042 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4043 SelectionDAG &DAG, SDLoc dl,
4044 unsigned vectorWidth) {
4045 assert((vectorWidth == 128 || vectorWidth == 256) &&
4046 "Unsupported vector width");
4047 EVT VT = Vec.getValueType();
4048 EVT ElVT = VT.getVectorElementType();
4049 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4050 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4051 VT.getVectorNumElements()/Factor);
4053 // Extract from UNDEF is UNDEF.
4054 if (Vec.getOpcode() == ISD::UNDEF)
4055 return DAG.getUNDEF(ResultVT);
4057 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4058 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4060 // This is the index of the first element of the vectorWidth-bit chunk
4062 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4065 // If the input is a buildvector just emit a smaller one.
4066 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4067 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4068 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4071 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4072 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4075 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4076 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4077 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4078 /// instructions or a simple subregister reference. Idx is an index in the
4079 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4080 /// lowering EXTRACT_VECTOR_ELT operations easier.
4081 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4082 SelectionDAG &DAG, SDLoc dl) {
4083 assert((Vec.getValueType().is256BitVector() ||
4084 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4085 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4088 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4089 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4090 SelectionDAG &DAG, SDLoc dl) {
4091 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4092 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4095 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4096 unsigned IdxVal, SelectionDAG &DAG,
4097 SDLoc dl, unsigned vectorWidth) {
4098 assert((vectorWidth == 128 || vectorWidth == 256) &&
4099 "Unsupported vector width");
4100 // Inserting UNDEF is Result
4101 if (Vec.getOpcode() == ISD::UNDEF)
4103 EVT VT = Vec.getValueType();
4104 EVT ElVT = VT.getVectorElementType();
4105 EVT ResultVT = Result.getValueType();
4107 // Insert the relevant vectorWidth bits.
4108 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4110 // This is the index of the first element of the vectorWidth-bit chunk
4112 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4115 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4116 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4119 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4120 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4121 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4122 /// simple superregister reference. Idx is an index in the 128 bits
4123 /// we want. It need not be aligned to a 128-bit boundary. That makes
4124 /// lowering INSERT_VECTOR_ELT operations easier.
4125 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4126 SelectionDAG &DAG, SDLoc dl) {
4127 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4129 // For insertion into the zero index (low half) of a 256-bit vector, it is
4130 // more efficient to generate a blend with immediate instead of an insert*128.
4131 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4132 // extend the subvector to the size of the result vector. Make sure that
4133 // we are not recursing on that node by checking for undef here.
4134 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4135 Result.getOpcode() != ISD::UNDEF) {
4136 EVT ResultVT = Result.getValueType();
4137 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4138 SDValue Undef = DAG.getUNDEF(ResultVT);
4139 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4142 // The blend instruction, and therefore its mask, depend on the data type.
4143 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4144 if (ScalarType.isFloatingPoint()) {
4145 // Choose either vblendps (float) or vblendpd (double).
4146 unsigned ScalarSize = ScalarType.getSizeInBits();
4147 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4148 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4149 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4150 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4153 const X86Subtarget &Subtarget =
4154 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4156 // AVX2 is needed for 256-bit integer blend support.
4157 // Integers must be cast to 32-bit because there is only vpblendd;
4158 // vpblendw can't be used for this because it has a handicapped mask.
4160 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4161 // is still more efficient than using the wrong domain vinsertf128 that
4162 // will be created by InsertSubVector().
4163 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4165 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4166 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4167 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4168 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4171 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4174 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4175 SelectionDAG &DAG, SDLoc dl) {
4176 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4177 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4180 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4181 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4182 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4183 /// large BUILD_VECTORS.
4184 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4185 unsigned NumElems, SelectionDAG &DAG,
4187 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4188 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4191 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4192 unsigned NumElems, SelectionDAG &DAG,
4194 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4195 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4198 /// getOnesVector - Returns a vector of specified type with all bits set.
4199 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4200 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4201 /// Then bitcast to their original type, ensuring they get CSE'd.
4202 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4204 assert(VT.isVector() && "Expected a vector type");
4206 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4208 if (VT.is256BitVector()) {
4209 if (HasInt256) { // AVX2
4210 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4211 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4213 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4214 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4216 } else if (VT.is128BitVector()) {
4217 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4219 llvm_unreachable("Unexpected vector type");
4221 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4224 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4225 /// operation of specified width.
4226 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4228 unsigned NumElems = VT.getVectorNumElements();
4229 SmallVector<int, 8> Mask;
4230 Mask.push_back(NumElems);
4231 for (unsigned i = 1; i != NumElems; ++i)
4233 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4236 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4237 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4239 unsigned NumElems = VT.getVectorNumElements();
4240 SmallVector<int, 8> Mask;
4241 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4243 Mask.push_back(i + NumElems);
4245 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4248 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4249 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4251 unsigned NumElems = VT.getVectorNumElements();
4252 SmallVector<int, 8> Mask;
4253 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4254 Mask.push_back(i + Half);
4255 Mask.push_back(i + NumElems + Half);
4257 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4261 /// vector of zero or undef vector. This produces a shuffle where the low
4262 /// element of V2 is swizzled into the zero/undef vector, landing at element
4263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4266 const X86Subtarget *Subtarget,
4267 SelectionDAG &DAG) {
4268 MVT VT = V2.getSimpleValueType();
4270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4271 unsigned NumElems = VT.getVectorNumElements();
4272 SmallVector<int, 16> MaskVec;
4273 for (unsigned i = 0; i != NumElems; ++i)
4274 // If this is the insertion idx, put the low elt of V2 here.
4275 MaskVec.push_back(i == Idx ? NumElems : i);
4276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4282 /// shuffles which use a single input multiple times, and in those cases it will
4283 /// adjust the mask to only have indices within that single input.
4284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4286 unsigned NumElems = VT.getVectorNumElements();
4290 bool IsFakeUnary = false;
4291 switch(N->getOpcode()) {
4292 case X86ISD::BLENDI:
4293 ImmN = N->getOperand(N->getNumOperands()-1);
4294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4297 ImmN = N->getOperand(N->getNumOperands()-1);
4298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4301 case X86ISD::UNPCKH:
4302 DecodeUNPCKHMask(VT, Mask);
4303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4305 case X86ISD::UNPCKL:
4306 DecodeUNPCKLMask(VT, Mask);
4307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4309 case X86ISD::MOVHLPS:
4310 DecodeMOVHLPSMask(NumElems, Mask);
4311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4313 case X86ISD::MOVLHPS:
4314 DecodeMOVLHPSMask(NumElems, Mask);
4315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4317 case X86ISD::PALIGNR:
4318 ImmN = N->getOperand(N->getNumOperands()-1);
4319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4321 case X86ISD::PSHUFD:
4322 case X86ISD::VPERMILPI:
4323 ImmN = N->getOperand(N->getNumOperands()-1);
4324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4327 case X86ISD::PSHUFHW:
4328 ImmN = N->getOperand(N->getNumOperands()-1);
4329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4332 case X86ISD::PSHUFLW:
4333 ImmN = N->getOperand(N->getNumOperands()-1);
4334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4337 case X86ISD::PSHUFB: {
4339 SDValue MaskNode = N->getOperand(1);
4340 while (MaskNode->getOpcode() == ISD::BITCAST)
4341 MaskNode = MaskNode->getOperand(0);
4343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4344 // If we have a build-vector, then things are easy.
4345 EVT VT = MaskNode.getValueType();
4346 assert(VT.isVector() &&
4347 "Can't produce a non-vector with a build_vector!");
4348 if (!VT.isInteger())
4351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4353 SmallVector<uint64_t, 32> RawMask;
4354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4355 SDValue Op = MaskNode->getOperand(i);
4356 if (Op->getOpcode() == ISD::UNDEF) {
4357 RawMask.push_back((uint64_t)SM_SentinelUndef);
4360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4363 APInt MaskElement = CN->getAPIntValue();
4365 // We now have to decode the element which could be any integer size and
4366 // extract each byte of it.
4367 for (int j = 0; j < NumBytesPerElement; ++j) {
4368 // Note that this is x86 and so always little endian: the low byte is
4369 // the first byte of the mask.
4370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4371 MaskElement = MaskElement.lshr(8);
4374 DecodePSHUFBMask(RawMask, Mask);
4378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4382 SDValue Ptr = MaskLoad->getBasePtr();
4383 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4384 Ptr->getOpcode() == X86ISD::WrapperRIP)
4385 Ptr = Ptr->getOperand(0);
4387 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4388 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4391 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4392 DecodePSHUFBMask(C, Mask);
4400 case X86ISD::VPERMI:
4401 ImmN = N->getOperand(N->getNumOperands()-1);
4402 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4407 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4409 case X86ISD::VPERM2X128:
4410 ImmN = N->getOperand(N->getNumOperands()-1);
4411 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4412 if (Mask.empty()) return false;
4414 case X86ISD::MOVSLDUP:
4415 DecodeMOVSLDUPMask(VT, Mask);
4418 case X86ISD::MOVSHDUP:
4419 DecodeMOVSHDUPMask(VT, Mask);
4422 case X86ISD::MOVDDUP:
4423 DecodeMOVDDUPMask(VT, Mask);
4426 case X86ISD::MOVLHPD:
4427 case X86ISD::MOVLPD:
4428 case X86ISD::MOVLPS:
4429 // Not yet implemented
4431 default: llvm_unreachable("unknown target shuffle node");
4434 // If we have a fake unary shuffle, the shuffle mask is spread across two
4435 // inputs that are actually the same node. Re-map the mask to always point
4436 // into the first input.
4439 if (M >= (int)Mask.size())
4445 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4446 /// element of the result of the vector shuffle.
4447 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4450 return SDValue(); // Limit search depth.
4452 SDValue V = SDValue(N, 0);
4453 EVT VT = V.getValueType();
4454 unsigned Opcode = V.getOpcode();
4456 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4457 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4458 int Elt = SV->getMaskElt(Index);
4461 return DAG.getUNDEF(VT.getVectorElementType());
4463 unsigned NumElems = VT.getVectorNumElements();
4464 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4465 : SV->getOperand(1);
4466 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4469 // Recurse into target specific vector shuffles to find scalars.
4470 if (isTargetShuffle(Opcode)) {
4471 MVT ShufVT = V.getSimpleValueType();
4472 unsigned NumElems = ShufVT.getVectorNumElements();
4473 SmallVector<int, 16> ShuffleMask;
4476 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4479 int Elt = ShuffleMask[Index];
4481 return DAG.getUNDEF(ShufVT.getVectorElementType());
4483 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4485 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4489 // Actual nodes that may contain scalar elements
4490 if (Opcode == ISD::BITCAST) {
4491 V = V.getOperand(0);
4492 EVT SrcVT = V.getValueType();
4493 unsigned NumElems = VT.getVectorNumElements();
4495 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4499 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4500 return (Index == 0) ? V.getOperand(0)
4501 : DAG.getUNDEF(VT.getVectorElementType());
4503 if (V.getOpcode() == ISD::BUILD_VECTOR)
4504 return V.getOperand(Index);
4509 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4511 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4512 unsigned NumNonZero, unsigned NumZero,
4514 const X86Subtarget* Subtarget,
4515 const TargetLowering &TLI) {
4523 // SSE4.1 - use PINSRB to insert each byte directly.
4524 if (Subtarget->hasSSE41()) {
4525 for (unsigned i = 0; i < 16; ++i) {
4526 bool isNonZero = (NonZeros & (1 << i)) != 0;
4530 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4532 V = DAG.getUNDEF(MVT::v16i8);
4535 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4536 MVT::v16i8, V, Op.getOperand(i),
4537 DAG.getIntPtrConstant(i, dl));
4544 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4545 for (unsigned i = 0; i < 16; ++i) {
4546 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4547 if (ThisIsNonZero && First) {
4549 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4551 V = DAG.getUNDEF(MVT::v8i16);
4556 SDValue ThisElt, LastElt;
4557 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4558 if (LastIsNonZero) {
4559 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4560 MVT::i16, Op.getOperand(i-1));
4562 if (ThisIsNonZero) {
4563 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4564 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4565 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4567 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4571 if (ThisElt.getNode())
4572 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4573 DAG.getIntPtrConstant(i/2, dl));
4577 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4580 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4582 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4583 unsigned NumNonZero, unsigned NumZero,
4585 const X86Subtarget* Subtarget,
4586 const TargetLowering &TLI) {
4593 for (unsigned i = 0; i < 8; ++i) {
4594 bool isNonZero = (NonZeros & (1 << i)) != 0;
4598 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4600 V = DAG.getUNDEF(MVT::v8i16);
4603 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4604 MVT::v8i16, V, Op.getOperand(i),
4605 DAG.getIntPtrConstant(i, dl));
4612 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4613 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4614 const X86Subtarget *Subtarget,
4615 const TargetLowering &TLI) {
4616 // Find all zeroable elements.
4617 std::bitset<4> Zeroable;
4618 for (int i=0; i < 4; ++i) {
4619 SDValue Elt = Op->getOperand(i);
4620 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4622 assert(Zeroable.size() - Zeroable.count() > 1 &&
4623 "We expect at least two non-zero elements!");
4625 // We only know how to deal with build_vector nodes where elements are either
4626 // zeroable or extract_vector_elt with constant index.
4627 SDValue FirstNonZero;
4628 unsigned FirstNonZeroIdx;
4629 for (unsigned i=0; i < 4; ++i) {
4632 SDValue Elt = Op->getOperand(i);
4633 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4634 !isa<ConstantSDNode>(Elt.getOperand(1)))
4636 // Make sure that this node is extracting from a 128-bit vector.
4637 MVT VT = Elt.getOperand(0).getSimpleValueType();
4638 if (!VT.is128BitVector())
4640 if (!FirstNonZero.getNode()) {
4642 FirstNonZeroIdx = i;
4646 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4647 SDValue V1 = FirstNonZero.getOperand(0);
4648 MVT VT = V1.getSimpleValueType();
4650 // See if this build_vector can be lowered as a blend with zero.
4652 unsigned EltMaskIdx, EltIdx;
4654 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4655 if (Zeroable[EltIdx]) {
4656 // The zero vector will be on the right hand side.
4657 Mask[EltIdx] = EltIdx+4;
4661 Elt = Op->getOperand(EltIdx);
4662 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4663 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4664 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4666 Mask[EltIdx] = EltIdx;
4670 // Let the shuffle legalizer deal with blend operations.
4671 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4672 if (V1.getSimpleValueType() != VT)
4673 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4674 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4677 // See if we can lower this build_vector to a INSERTPS.
4678 if (!Subtarget->hasSSE41())
4681 SDValue V2 = Elt.getOperand(0);
4682 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4685 bool CanFold = true;
4686 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4690 SDValue Current = Op->getOperand(i);
4691 SDValue SrcVector = Current->getOperand(0);
4694 CanFold = SrcVector == V1 &&
4695 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4701 assert(V1.getNode() && "Expected at least two non-zero elements!");
4702 if (V1.getSimpleValueType() != MVT::v4f32)
4703 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4704 if (V2.getSimpleValueType() != MVT::v4f32)
4705 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4707 // Ok, we can emit an INSERTPS instruction.
4708 unsigned ZMask = Zeroable.to_ulong();
4710 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4711 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4713 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4714 DAG.getIntPtrConstant(InsertPSMask, DL));
4715 return DAG.getNode(ISD::BITCAST, DL, VT, Result);
4718 /// Return a vector logical shift node.
4719 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4720 unsigned NumBits, SelectionDAG &DAG,
4721 const TargetLowering &TLI, SDLoc dl) {
4722 assert(VT.is128BitVector() && "Unknown type for VShift");
4723 MVT ShVT = MVT::v2i64;
4724 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4725 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4726 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4727 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4728 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4729 return DAG.getNode(ISD::BITCAST, dl, VT,
4730 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4734 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4736 // Check if the scalar load can be widened into a vector load. And if
4737 // the address is "base + cst" see if the cst can be "absorbed" into
4738 // the shuffle mask.
4739 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4740 SDValue Ptr = LD->getBasePtr();
4741 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4743 EVT PVT = LD->getValueType(0);
4744 if (PVT != MVT::i32 && PVT != MVT::f32)
4749 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4750 FI = FINode->getIndex();
4752 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4753 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4754 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4755 Offset = Ptr.getConstantOperandVal(1);
4756 Ptr = Ptr.getOperand(0);
4761 // FIXME: 256-bit vector instructions don't require a strict alignment,
4762 // improve this code to support it better.
4763 unsigned RequiredAlign = VT.getSizeInBits()/8;
4764 SDValue Chain = LD->getChain();
4765 // Make sure the stack object alignment is at least 16 or 32.
4766 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4767 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4768 if (MFI->isFixedObjectIndex(FI)) {
4769 // Can't change the alignment. FIXME: It's possible to compute
4770 // the exact stack offset and reference FI + adjust offset instead.
4771 // If someone *really* cares about this. That's the way to implement it.
4774 MFI->setObjectAlignment(FI, RequiredAlign);
4778 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4779 // Ptr + (Offset & ~15).
4782 if ((Offset % RequiredAlign) & 3)
4784 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4787 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4788 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4791 int EltNo = (Offset - StartOffset) >> 2;
4792 unsigned NumElems = VT.getVectorNumElements();
4794 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4795 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4796 LD->getPointerInfo().getWithOffset(StartOffset),
4797 false, false, false, 0);
4799 SmallVector<int, 8> Mask(NumElems, EltNo);
4801 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4807 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4808 /// elements can be replaced by a single large load which has the same value as
4809 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4811 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4813 /// FIXME: we'd also like to handle the case where the last elements are zero
4814 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4815 /// There's even a handy isZeroNode for that purpose.
4816 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4817 SDLoc &DL, SelectionDAG &DAG,
4818 bool isAfterLegalize) {
4819 unsigned NumElems = Elts.size();
4821 LoadSDNode *LDBase = nullptr;
4822 unsigned LastLoadedElt = -1U;
4824 // For each element in the initializer, see if we've found a load or an undef.
4825 // If we don't find an initial load element, or later load elements are
4826 // non-consecutive, bail out.
4827 for (unsigned i = 0; i < NumElems; ++i) {
4828 SDValue Elt = Elts[i];
4829 // Look through a bitcast.
4830 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4831 Elt = Elt.getOperand(0);
4832 if (!Elt.getNode() ||
4833 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4836 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4838 LDBase = cast<LoadSDNode>(Elt.getNode());
4842 if (Elt.getOpcode() == ISD::UNDEF)
4845 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4846 EVT LdVT = Elt.getValueType();
4847 // Each loaded element must be the correct fractional portion of the
4848 // requested vector load.
4849 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4851 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4856 // If we have found an entire vector of loads and undefs, then return a large
4857 // load of the entire vector width starting at the base pointer. If we found
4858 // consecutive loads for the low half, generate a vzext_load node.
4859 if (LastLoadedElt == NumElems - 1) {
4860 assert(LDBase && "Did not find base load for merging consecutive loads");
4861 EVT EltVT = LDBase->getValueType(0);
4862 // Ensure that the input vector size for the merged loads matches the
4863 // cumulative size of the input elements.
4864 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4867 if (isAfterLegalize &&
4868 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4871 SDValue NewLd = SDValue();
4873 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4874 LDBase->getPointerInfo(), LDBase->isVolatile(),
4875 LDBase->isNonTemporal(), LDBase->isInvariant(),
4876 LDBase->getAlignment());
4878 if (LDBase->hasAnyUseOfValue(1)) {
4879 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4881 SDValue(NewLd.getNode(), 1));
4882 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4883 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4884 SDValue(NewLd.getNode(), 1));
4890 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4891 //of a v4i32 / v4f32. It's probably worth generalizing.
4892 EVT EltVT = VT.getVectorElementType();
4893 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4894 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4895 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4896 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4898 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4899 LDBase->getPointerInfo(),
4900 LDBase->getAlignment(),
4901 false/*isVolatile*/, true/*ReadMem*/,
4904 // Make sure the newly-created LOAD is in the same position as LDBase in
4905 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4906 // update uses of LDBase's output chain to use the TokenFactor.
4907 if (LDBase->hasAnyUseOfValue(1)) {
4908 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4909 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4910 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4911 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4912 SDValue(ResNode.getNode(), 1));
4915 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4920 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4921 /// to generate a splat value for the following cases:
4922 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4923 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4924 /// a scalar load, or a constant.
4925 /// The VBROADCAST node is returned when a pattern is found,
4926 /// or SDValue() otherwise.
4927 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4928 SelectionDAG &DAG) {
4929 // VBROADCAST requires AVX.
4930 // TODO: Splats could be generated for non-AVX CPUs using SSE
4931 // instructions, but there's less potential gain for only 128-bit vectors.
4932 if (!Subtarget->hasAVX())
4935 MVT VT = Op.getSimpleValueType();
4938 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4939 "Unsupported vector type for broadcast.");
4944 switch (Op.getOpcode()) {
4946 // Unknown pattern found.
4949 case ISD::BUILD_VECTOR: {
4950 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4951 BitVector UndefElements;
4952 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4954 // We need a splat of a single value to use broadcast, and it doesn't
4955 // make any sense if the value is only in one element of the vector.
4956 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4960 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4961 Ld.getOpcode() == ISD::ConstantFP);
4963 // Make sure that all of the users of a non-constant load are from the
4964 // BUILD_VECTOR node.
4965 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4970 case ISD::VECTOR_SHUFFLE: {
4971 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4973 // Shuffles must have a splat mask where the first element is
4975 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4978 SDValue Sc = Op.getOperand(0);
4979 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4980 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4982 if (!Subtarget->hasInt256())
4985 // Use the register form of the broadcast instruction available on AVX2.
4986 if (VT.getSizeInBits() >= 256)
4987 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4988 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4991 Ld = Sc.getOperand(0);
4992 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4993 Ld.getOpcode() == ISD::ConstantFP);
4995 // The scalar_to_vector node and the suspected
4996 // load node must have exactly one user.
4997 // Constants may have multiple users.
4999 // AVX-512 has register version of the broadcast
5000 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5001 Ld.getValueType().getSizeInBits() >= 32;
5002 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5009 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5010 bool IsGE256 = (VT.getSizeInBits() >= 256);
5012 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5013 // instruction to save 8 or more bytes of constant pool data.
5014 // TODO: If multiple splats are generated to load the same constant,
5015 // it may be detrimental to overall size. There needs to be a way to detect
5016 // that condition to know if this is truly a size win.
5017 const Function *F = DAG.getMachineFunction().getFunction();
5018 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5020 // Handle broadcasting a single constant scalar from the constant pool
5022 // On Sandybridge (no AVX2), it is still better to load a constant vector
5023 // from the constant pool and not to broadcast it from a scalar.
5024 // But override that restriction when optimizing for size.
5025 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5026 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5027 EVT CVT = Ld.getValueType();
5028 assert(!CVT.isVector() && "Must not broadcast a vector type");
5030 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5031 // For size optimization, also splat v2f64 and v2i64, and for size opt
5032 // with AVX2, also splat i8 and i16.
5033 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5034 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5035 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5036 const Constant *C = nullptr;
5037 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5038 C = CI->getConstantIntValue();
5039 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5040 C = CF->getConstantFPValue();
5042 assert(C && "Invalid constant type");
5044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5045 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5046 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5047 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5048 MachinePointerInfo::getConstantPool(),
5049 false, false, false, Alignment);
5051 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5055 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5057 // Handle AVX2 in-register broadcasts.
5058 if (!IsLoad && Subtarget->hasInt256() &&
5059 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5060 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5062 // The scalar source must be a normal load.
5066 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5067 (Subtarget->hasVLX() && ScalarSize == 64))
5068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5070 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5071 // double since there is no vbroadcastsd xmm
5072 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5073 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5074 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5077 // Unsupported broadcast.
5081 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5082 /// underlying vector and index.
5084 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5086 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5088 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5089 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5092 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5094 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5096 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5097 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5100 // In this case the vector is the extract_subvector expression and the index
5101 // is 2, as specified by the shuffle.
5102 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5103 SDValue ShuffleVec = SVOp->getOperand(0);
5104 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5105 assert(ShuffleVecVT.getVectorElementType() ==
5106 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5108 int ShuffleIdx = SVOp->getMaskElt(Idx);
5109 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5110 ExtractedFromVec = ShuffleVec;
5116 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5117 MVT VT = Op.getSimpleValueType();
5119 // Skip if insert_vec_elt is not supported.
5120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5121 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5125 unsigned NumElems = Op.getNumOperands();
5129 SmallVector<unsigned, 4> InsertIndices;
5130 SmallVector<int, 8> Mask(NumElems, -1);
5132 for (unsigned i = 0; i != NumElems; ++i) {
5133 unsigned Opc = Op.getOperand(i).getOpcode();
5135 if (Opc == ISD::UNDEF)
5138 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5139 // Quit if more than 1 elements need inserting.
5140 if (InsertIndices.size() > 1)
5143 InsertIndices.push_back(i);
5147 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5148 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5149 // Quit if non-constant index.
5150 if (!isa<ConstantSDNode>(ExtIdx))
5152 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5154 // Quit if extracted from vector of different type.
5155 if (ExtractedFromVec.getValueType() != VT)
5158 if (!VecIn1.getNode())
5159 VecIn1 = ExtractedFromVec;
5160 else if (VecIn1 != ExtractedFromVec) {
5161 if (!VecIn2.getNode())
5162 VecIn2 = ExtractedFromVec;
5163 else if (VecIn2 != ExtractedFromVec)
5164 // Quit if more than 2 vectors to shuffle
5168 if (ExtractedFromVec == VecIn1)
5170 else if (ExtractedFromVec == VecIn2)
5171 Mask[i] = Idx + NumElems;
5174 if (!VecIn1.getNode())
5177 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5178 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5179 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5180 unsigned Idx = InsertIndices[i];
5181 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5182 DAG.getIntPtrConstant(Idx, DL));
5188 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5190 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5192 MVT VT = Op.getSimpleValueType();
5193 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5194 "Unexpected type in LowerBUILD_VECTORvXi1!");
5197 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5198 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5199 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5200 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5203 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5204 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5205 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5206 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5209 bool AllContants = true;
5210 uint64_t Immediate = 0;
5211 int NonConstIdx = -1;
5212 bool IsSplat = true;
5213 unsigned NumNonConsts = 0;
5214 unsigned NumConsts = 0;
5215 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5216 SDValue In = Op.getOperand(idx);
5217 if (In.getOpcode() == ISD::UNDEF)
5219 if (!isa<ConstantSDNode>(In)) {
5220 AllContants = false;
5225 if (cast<ConstantSDNode>(In)->getZExtValue())
5226 Immediate |= (1ULL << idx);
5228 if (In != Op.getOperand(0))
5233 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5234 DAG.getConstant(Immediate, dl, MVT::i16));
5235 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5236 DAG.getIntPtrConstant(0, dl));
5239 if (NumNonConsts == 1 && NonConstIdx != 0) {
5242 SDValue VecAsImm = DAG.getConstant(Immediate, dl,
5243 MVT::getIntegerVT(VT.getSizeInBits()));
5244 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5247 DstVec = DAG.getUNDEF(VT);
5248 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5249 Op.getOperand(NonConstIdx),
5250 DAG.getIntPtrConstant(NonConstIdx, dl));
5252 if (!IsSplat && (NonConstIdx != 0))
5253 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5254 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5257 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5258 DAG.getConstant(-1, dl, SelectVT),
5259 DAG.getConstant(0, dl, SelectVT));
5261 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5262 DAG.getConstant((Immediate | 1), dl, SelectVT),
5263 DAG.getConstant(Immediate, dl, SelectVT));
5264 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5267 /// \brief Return true if \p N implements a horizontal binop and return the
5268 /// operands for the horizontal binop into V0 and V1.
5270 /// This is a helper function of LowerToHorizontalOp().
5271 /// This function checks that the build_vector \p N in input implements a
5272 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5273 /// operation to match.
5274 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5275 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5276 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5279 /// This function only analyzes elements of \p N whose indices are
5280 /// in range [BaseIdx, LastIdx).
5281 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5283 unsigned BaseIdx, unsigned LastIdx,
5284 SDValue &V0, SDValue &V1) {
5285 EVT VT = N->getValueType(0);
5287 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5288 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5289 "Invalid Vector in input!");
5291 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5292 bool CanFold = true;
5293 unsigned ExpectedVExtractIdx = BaseIdx;
5294 unsigned NumElts = LastIdx - BaseIdx;
5295 V0 = DAG.getUNDEF(VT);
5296 V1 = DAG.getUNDEF(VT);
5298 // Check if N implements a horizontal binop.
5299 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5300 SDValue Op = N->getOperand(i + BaseIdx);
5303 if (Op->getOpcode() == ISD::UNDEF) {
5304 // Update the expected vector extract index.
5305 if (i * 2 == NumElts)
5306 ExpectedVExtractIdx = BaseIdx;
5307 ExpectedVExtractIdx += 2;
5311 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5316 SDValue Op0 = Op.getOperand(0);
5317 SDValue Op1 = Op.getOperand(1);
5319 // Try to match the following pattern:
5320 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5321 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5322 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5323 Op0.getOperand(0) == Op1.getOperand(0) &&
5324 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5325 isa<ConstantSDNode>(Op1.getOperand(1)));
5329 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5330 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5332 if (i * 2 < NumElts) {
5333 if (V0.getOpcode() == ISD::UNDEF) {
5334 V0 = Op0.getOperand(0);
5335 if (V0.getValueType() != VT)
5339 if (V1.getOpcode() == ISD::UNDEF) {
5340 V1 = Op0.getOperand(0);
5341 if (V1.getValueType() != VT)
5344 if (i * 2 == NumElts)
5345 ExpectedVExtractIdx = BaseIdx;
5348 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5349 if (I0 == ExpectedVExtractIdx)
5350 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5351 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5352 // Try to match the following dag sequence:
5353 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5354 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5358 ExpectedVExtractIdx += 2;
5364 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5365 /// a concat_vector.
5367 /// This is a helper function of LowerToHorizontalOp().
5368 /// This function expects two 256-bit vectors called V0 and V1.
5369 /// At first, each vector is split into two separate 128-bit vectors.
5370 /// Then, the resulting 128-bit vectors are used to implement two
5371 /// horizontal binary operations.
5373 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5375 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5376 /// the two new horizontal binop.
5377 /// When Mode is set, the first horizontal binop dag node would take as input
5378 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5379 /// horizontal binop dag node would take as input the lower 128-bit of V1
5380 /// and the upper 128-bit of V1.
5382 /// HADD V0_LO, V0_HI
5383 /// HADD V1_LO, V1_HI
5385 /// Otherwise, the first horizontal binop dag node takes as input the lower
5386 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5387 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5389 /// HADD V0_LO, V1_LO
5390 /// HADD V0_HI, V1_HI
5392 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5393 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5394 /// the upper 128-bits of the result.
5395 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5396 SDLoc DL, SelectionDAG &DAG,
5397 unsigned X86Opcode, bool Mode,
5398 bool isUndefLO, bool isUndefHI) {
5399 EVT VT = V0.getValueType();
5400 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5401 "Invalid nodes in input!");
5403 unsigned NumElts = VT.getVectorNumElements();
5404 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5405 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5406 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5407 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5408 EVT NewVT = V0_LO.getValueType();
5410 SDValue LO = DAG.getUNDEF(NewVT);
5411 SDValue HI = DAG.getUNDEF(NewVT);
5414 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5415 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5416 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5417 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5418 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5420 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5421 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5422 V1_LO->getOpcode() != ISD::UNDEF))
5423 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5425 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5426 V1_HI->getOpcode() != ISD::UNDEF))
5427 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5430 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5433 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5435 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5436 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5437 EVT VT = BV->getValueType(0);
5438 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5439 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5443 unsigned NumElts = VT.getVectorNumElements();
5444 SDValue InVec0 = DAG.getUNDEF(VT);
5445 SDValue InVec1 = DAG.getUNDEF(VT);
5447 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5448 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5450 // Odd-numbered elements in the input build vector are obtained from
5451 // adding two integer/float elements.
5452 // Even-numbered elements in the input build vector are obtained from
5453 // subtracting two integer/float elements.
5454 unsigned ExpectedOpcode = ISD::FSUB;
5455 unsigned NextExpectedOpcode = ISD::FADD;
5456 bool AddFound = false;
5457 bool SubFound = false;
5459 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5460 SDValue Op = BV->getOperand(i);
5462 // Skip 'undef' values.
5463 unsigned Opcode = Op.getOpcode();
5464 if (Opcode == ISD::UNDEF) {
5465 std::swap(ExpectedOpcode, NextExpectedOpcode);
5469 // Early exit if we found an unexpected opcode.
5470 if (Opcode != ExpectedOpcode)
5473 SDValue Op0 = Op.getOperand(0);
5474 SDValue Op1 = Op.getOperand(1);
5476 // Try to match the following pattern:
5477 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5478 // Early exit if we cannot match that sequence.
5479 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5480 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5481 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5482 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5483 Op0.getOperand(1) != Op1.getOperand(1))
5486 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5490 // We found a valid add/sub node. Update the information accordingly.
5496 // Update InVec0 and InVec1.
5497 if (InVec0.getOpcode() == ISD::UNDEF) {
5498 InVec0 = Op0.getOperand(0);
5499 if (InVec0.getValueType() != VT)
5502 if (InVec1.getOpcode() == ISD::UNDEF) {
5503 InVec1 = Op1.getOperand(0);
5504 if (InVec1.getValueType() != VT)
5508 // Make sure that operands in input to each add/sub node always
5509 // come from a same pair of vectors.
5510 if (InVec0 != Op0.getOperand(0)) {
5511 if (ExpectedOpcode == ISD::FSUB)
5514 // FADD is commutable. Try to commute the operands
5515 // and then test again.
5516 std::swap(Op0, Op1);
5517 if (InVec0 != Op0.getOperand(0))
5521 if (InVec1 != Op1.getOperand(0))
5524 // Update the pair of expected opcodes.
5525 std::swap(ExpectedOpcode, NextExpectedOpcode);
5528 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5529 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5530 InVec1.getOpcode() != ISD::UNDEF)
5531 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5536 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5537 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5538 const X86Subtarget *Subtarget,
5539 SelectionDAG &DAG) {
5540 EVT VT = BV->getValueType(0);
5541 unsigned NumElts = VT.getVectorNumElements();
5542 unsigned NumUndefsLO = 0;
5543 unsigned NumUndefsHI = 0;
5544 unsigned Half = NumElts/2;
5546 // Count the number of UNDEF operands in the build_vector in input.
5547 for (unsigned i = 0, e = Half; i != e; ++i)
5548 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5551 for (unsigned i = Half, e = NumElts; i != e; ++i)
5552 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5555 // Early exit if this is either a build_vector of all UNDEFs or all the
5556 // operands but one are UNDEF.
5557 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5561 SDValue InVec0, InVec1;
5562 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5563 // Try to match an SSE3 float HADD/HSUB.
5564 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5565 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5567 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5568 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5569 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5570 // Try to match an SSSE3 integer HADD/HSUB.
5571 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5572 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5574 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5575 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5578 if (!Subtarget->hasAVX())
5581 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5582 // Try to match an AVX horizontal add/sub of packed single/double
5583 // precision floating point values from 256-bit vectors.
5584 SDValue InVec2, InVec3;
5585 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5586 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5587 ((InVec0.getOpcode() == ISD::UNDEF ||
5588 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5589 ((InVec1.getOpcode() == ISD::UNDEF ||
5590 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5591 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5593 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5594 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5595 ((InVec0.getOpcode() == ISD::UNDEF ||
5596 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5597 ((InVec1.getOpcode() == ISD::UNDEF ||
5598 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5599 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5600 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5601 // Try to match an AVX2 horizontal add/sub of signed integers.
5602 SDValue InVec2, InVec3;
5604 bool CanFold = true;
5606 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5607 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5608 ((InVec0.getOpcode() == ISD::UNDEF ||
5609 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5610 ((InVec1.getOpcode() == ISD::UNDEF ||
5611 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5612 X86Opcode = X86ISD::HADD;
5613 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5614 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5615 ((InVec0.getOpcode() == ISD::UNDEF ||
5616 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5617 ((InVec1.getOpcode() == ISD::UNDEF ||
5618 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5619 X86Opcode = X86ISD::HSUB;
5624 // Fold this build_vector into a single horizontal add/sub.
5625 // Do this only if the target has AVX2.
5626 if (Subtarget->hasAVX2())
5627 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5629 // Do not try to expand this build_vector into a pair of horizontal
5630 // add/sub if we can emit a pair of scalar add/sub.
5631 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5634 // Convert this build_vector into a pair of horizontal binop followed by
5636 bool isUndefLO = NumUndefsLO == Half;
5637 bool isUndefHI = NumUndefsHI == Half;
5638 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5639 isUndefLO, isUndefHI);
5643 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5644 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5646 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5647 X86Opcode = X86ISD::HADD;
5648 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5649 X86Opcode = X86ISD::HSUB;
5650 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5651 X86Opcode = X86ISD::FHADD;
5652 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5653 X86Opcode = X86ISD::FHSUB;
5657 // Don't try to expand this build_vector into a pair of horizontal add/sub
5658 // if we can simply emit a pair of scalar add/sub.
5659 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5662 // Convert this build_vector into two horizontal add/sub followed by
5664 bool isUndefLO = NumUndefsLO == Half;
5665 bool isUndefHI = NumUndefsHI == Half;
5666 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5667 isUndefLO, isUndefHI);
5674 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5677 MVT VT = Op.getSimpleValueType();
5678 MVT ExtVT = VT.getVectorElementType();
5679 unsigned NumElems = Op.getNumOperands();
5681 // Generate vectors for predicate vectors.
5682 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5683 return LowerBUILD_VECTORvXi1(Op, DAG);
5685 // Vectors containing all zeros can be matched by pxor and xorps later
5686 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5687 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5688 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5689 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5692 return getZeroVector(VT, Subtarget, DAG, dl);
5695 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5696 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5697 // vpcmpeqd on 256-bit vectors.
5698 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5699 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5702 if (!VT.is512BitVector())
5703 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5706 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5707 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5709 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5710 return HorizontalOp;
5711 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5714 unsigned EVTBits = ExtVT.getSizeInBits();
5716 unsigned NumZero = 0;
5717 unsigned NumNonZero = 0;
5718 unsigned NonZeros = 0;
5719 bool IsAllConstants = true;
5720 SmallSet<SDValue, 8> Values;
5721 for (unsigned i = 0; i < NumElems; ++i) {
5722 SDValue Elt = Op.getOperand(i);
5723 if (Elt.getOpcode() == ISD::UNDEF)
5726 if (Elt.getOpcode() != ISD::Constant &&
5727 Elt.getOpcode() != ISD::ConstantFP)
5728 IsAllConstants = false;
5729 if (X86::isZeroNode(Elt))
5732 NonZeros |= (1 << i);
5737 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5738 if (NumNonZero == 0)
5739 return DAG.getUNDEF(VT);
5741 // Special case for single non-zero, non-undef, element.
5742 if (NumNonZero == 1) {
5743 unsigned Idx = countTrailingZeros(NonZeros);
5744 SDValue Item = Op.getOperand(Idx);
5746 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5747 // the value are obviously zero, truncate the value to i32 and do the
5748 // insertion that way. Only do this if the value is non-constant or if the
5749 // value is a constant being inserted into element 0. It is cheaper to do
5750 // a constant pool load than it is to do a movd + shuffle.
5751 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5752 (!IsAllConstants || Idx == 0)) {
5753 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5755 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5756 EVT VecVT = MVT::v4i32;
5758 // Truncate the value (which may itself be a constant) to i32, and
5759 // convert it to a vector with movd (S2V+shuffle to zero extend).
5760 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5761 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5763 ISD::BITCAST, dl, VT,
5764 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5768 // If we have a constant or non-constant insertion into the low element of
5769 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5770 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5771 // depending on what the source datatype is.
5774 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5776 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5777 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5778 if (VT.is512BitVector()) {
5779 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5780 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5781 Item, DAG.getIntPtrConstant(0, dl));
5783 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5784 "Expected an SSE value type!");
5785 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5786 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5787 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5790 // We can't directly insert an i8 or i16 into a vector, so zero extend
5792 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5793 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5794 if (VT.is256BitVector()) {
5795 if (Subtarget->hasAVX()) {
5796 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5797 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5799 // Without AVX, we need to extend to a 128-bit vector and then
5800 // insert into the 256-bit vector.
5801 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5802 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5803 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5806 assert(VT.is128BitVector() && "Expected an SSE value type!");
5807 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5808 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5810 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5814 // Is it a vector logical left shift?
5815 if (NumElems == 2 && Idx == 1 &&
5816 X86::isZeroNode(Op.getOperand(0)) &&
5817 !X86::isZeroNode(Op.getOperand(1))) {
5818 unsigned NumBits = VT.getSizeInBits();
5819 return getVShift(true, VT,
5820 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5821 VT, Op.getOperand(1)),
5822 NumBits/2, DAG, *this, dl);
5825 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5828 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5829 // is a non-constant being inserted into an element other than the low one,
5830 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5831 // movd/movss) to move this into the low element, then shuffle it into
5833 if (EVTBits == 32) {
5834 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5835 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5839 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5840 if (Values.size() == 1) {
5841 if (EVTBits == 32) {
5842 // Instead of a shuffle like this:
5843 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5844 // Check if it's possible to issue this instead.
5845 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5846 unsigned Idx = countTrailingZeros(NonZeros);
5847 SDValue Item = Op.getOperand(Idx);
5848 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5849 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5854 // A vector full of immediates; various special cases are already
5855 // handled, so this is best done with a single constant-pool load.
5859 // For AVX-length vectors, see if we can use a vector load to get all of the
5860 // elements, otherwise build the individual 128-bit pieces and use
5861 // shuffles to put them in place.
5862 if (VT.is256BitVector() || VT.is512BitVector()) {
5863 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5865 // Check for a build vector of consecutive loads.
5866 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5869 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5871 // Build both the lower and upper subvector.
5872 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5873 makeArrayRef(&V[0], NumElems/2));
5874 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5875 makeArrayRef(&V[NumElems / 2], NumElems/2));
5877 // Recreate the wider vector with the lower and upper part.
5878 if (VT.is256BitVector())
5879 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5880 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5883 // Let legalizer expand 2-wide build_vectors.
5884 if (EVTBits == 64) {
5885 if (NumNonZero == 1) {
5886 // One half is zero or undef.
5887 unsigned Idx = countTrailingZeros(NonZeros);
5888 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5889 Op.getOperand(Idx));
5890 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5895 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5896 if (EVTBits == 8 && NumElems == 16)
5897 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5901 if (EVTBits == 16 && NumElems == 8)
5902 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5906 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5907 if (EVTBits == 32 && NumElems == 4)
5908 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5911 // If element VT is == 32 bits, turn it into a number of shuffles.
5912 SmallVector<SDValue, 8> V(NumElems);
5913 if (NumElems == 4 && NumZero > 0) {
5914 for (unsigned i = 0; i < 4; ++i) {
5915 bool isZero = !(NonZeros & (1 << i));
5917 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5919 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5922 for (unsigned i = 0; i < 2; ++i) {
5923 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5926 V[i] = V[i*2]; // Must be a zero vector.
5929 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5932 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5935 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5940 bool Reverse1 = (NonZeros & 0x3) == 2;
5941 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5945 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5946 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5948 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5951 if (Values.size() > 1 && VT.is128BitVector()) {
5952 // Check for a build vector of consecutive loads.
5953 for (unsigned i = 0; i < NumElems; ++i)
5954 V[i] = Op.getOperand(i);
5956 // Check for elements which are consecutive loads.
5957 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5960 // Check for a build vector from mostly shuffle plus few inserting.
5961 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
5964 // For SSE 4.1, use insertps to put the high elements into the low element.
5965 if (Subtarget->hasSSE41()) {
5967 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5968 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5970 Result = DAG.getUNDEF(VT);
5972 for (unsigned i = 1; i < NumElems; ++i) {
5973 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5974 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5975 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
5980 // Otherwise, expand into a number of unpckl*, start by extending each of
5981 // our (non-undef) elements to the full vector width with the element in the
5982 // bottom slot of the vector (which generates no code for SSE).
5983 for (unsigned i = 0; i < NumElems; ++i) {
5984 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5985 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5987 V[i] = DAG.getUNDEF(VT);
5990 // Next, we iteratively mix elements, e.g. for v4f32:
5991 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5992 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5993 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5994 unsigned EltStride = NumElems >> 1;
5995 while (EltStride != 0) {
5996 for (unsigned i = 0; i < EltStride; ++i) {
5997 // If V[i+EltStride] is undef and this is the first round of mixing,
5998 // then it is safe to just drop this shuffle: V[i] is already in the
5999 // right place, the one element (since it's the first round) being
6000 // inserted as undef can be dropped. This isn't safe for successive
6001 // rounds because they will permute elements within both vectors.
6002 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6003 EltStride == NumElems/2)
6006 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6015 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6016 // to create 256-bit vectors from two other 128-bit ones.
6017 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6019 MVT ResVT = Op.getSimpleValueType();
6021 assert((ResVT.is256BitVector() ||
6022 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6024 SDValue V1 = Op.getOperand(0);
6025 SDValue V2 = Op.getOperand(1);
6026 unsigned NumElems = ResVT.getVectorNumElements();
6027 if (ResVT.is256BitVector())
6028 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6030 if (Op.getNumOperands() == 4) {
6031 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6032 ResVT.getVectorNumElements()/2);
6033 SDValue V3 = Op.getOperand(2);
6034 SDValue V4 = Op.getOperand(3);
6035 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6036 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6038 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6041 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6042 const X86Subtarget *Subtarget,
6043 SelectionDAG & DAG) {
6045 MVT ResVT = Op.getSimpleValueType();
6046 unsigned NumOfOperands = Op.getNumOperands();
6048 assert(isPowerOf2_32(NumOfOperands) &&
6049 "Unexpected number of operands in CONCAT_VECTORS");
6051 if (NumOfOperands > 2) {
6052 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6053 ResVT.getVectorNumElements()/2);
6054 SmallVector<SDValue, 2> Ops;
6055 for (unsigned i = 0; i < NumOfOperands/2; i++)
6056 Ops.push_back(Op.getOperand(i));
6057 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6059 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6060 Ops.push_back(Op.getOperand(i));
6061 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6062 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6065 SDValue V1 = Op.getOperand(0);
6066 SDValue V2 = Op.getOperand(1);
6067 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6068 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6070 if (IsZeroV1 && IsZeroV2)
6071 return getZeroVector(ResVT, Subtarget, DAG, dl);
6073 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6074 SDValue Undef = DAG.getUNDEF(ResVT);
6075 unsigned NumElems = ResVT.getVectorNumElements();
6076 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6078 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6079 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6083 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6084 // Zero the upper bits of V1
6085 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6086 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6089 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6092 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6093 const X86Subtarget *Subtarget,
6094 SelectionDAG &DAG) {
6095 MVT VT = Op.getSimpleValueType();
6096 if (VT.getVectorElementType() == MVT::i1)
6097 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6099 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6100 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6101 Op.getNumOperands() == 4)));
6103 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6104 // from two other 128-bit ones.
6106 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6107 return LowerAVXCONCAT_VECTORS(Op, DAG);
6111 //===----------------------------------------------------------------------===//
6112 // Vector shuffle lowering
6114 // This is an experimental code path for lowering vector shuffles on x86. It is
6115 // designed to handle arbitrary vector shuffles and blends, gracefully
6116 // degrading performance as necessary. It works hard to recognize idiomatic
6117 // shuffles and lower them to optimal instruction patterns without leaving
6118 // a framework that allows reasonably efficient handling of all vector shuffle
6120 //===----------------------------------------------------------------------===//
6122 /// \brief Tiny helper function to identify a no-op mask.
6124 /// This is a somewhat boring predicate function. It checks whether the mask
6125 /// array input, which is assumed to be a single-input shuffle mask of the kind
6126 /// used by the X86 shuffle instructions (not a fully general
6127 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6128 /// in-place shuffle are 'no-op's.
6129 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6130 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6131 if (Mask[i] != -1 && Mask[i] != i)
6136 /// \brief Helper function to classify a mask as a single-input mask.
6138 /// This isn't a generic single-input test because in the vector shuffle
6139 /// lowering we canonicalize single inputs to be the first input operand. This
6140 /// means we can more quickly test for a single input by only checking whether
6141 /// an input from the second operand exists. We also assume that the size of
6142 /// mask corresponds to the size of the input vectors which isn't true in the
6143 /// fully general case.
6144 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6146 if (M >= (int)Mask.size())
6151 /// \brief Test whether there are elements crossing 128-bit lanes in this
6154 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6155 /// and we routinely test for these.
6156 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6157 int LaneSize = 128 / VT.getScalarSizeInBits();
6158 int Size = Mask.size();
6159 for (int i = 0; i < Size; ++i)
6160 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6165 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6167 /// This checks a shuffle mask to see if it is performing the same
6168 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6169 /// that it is also not lane-crossing. It may however involve a blend from the
6170 /// same lane of a second vector.
6172 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6173 /// non-trivial to compute in the face of undef lanes. The representation is
6174 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6175 /// entries from both V1 and V2 inputs to the wider mask.
6177 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6178 SmallVectorImpl<int> &RepeatedMask) {
6179 int LaneSize = 128 / VT.getScalarSizeInBits();
6180 RepeatedMask.resize(LaneSize, -1);
6181 int Size = Mask.size();
6182 for (int i = 0; i < Size; ++i) {
6185 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6186 // This entry crosses lanes, so there is no way to model this shuffle.
6189 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6190 if (RepeatedMask[i % LaneSize] == -1)
6191 // This is the first non-undef entry in this slot of a 128-bit lane.
6192 RepeatedMask[i % LaneSize] =
6193 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6194 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6195 // Found a mismatch with the repeated mask.
6201 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6204 /// This is a fast way to test a shuffle mask against a fixed pattern:
6206 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6208 /// It returns true if the mask is exactly as wide as the argument list, and
6209 /// each element of the mask is either -1 (signifying undef) or the value given
6210 /// in the argument.
6211 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6212 ArrayRef<int> ExpectedMask) {
6213 if (Mask.size() != ExpectedMask.size())
6216 int Size = Mask.size();
6218 // If the values are build vectors, we can look through them to find
6219 // equivalent inputs that make the shuffles equivalent.
6220 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6221 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6223 for (int i = 0; i < Size; ++i)
6224 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6225 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6226 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6227 if (!MaskBV || !ExpectedBV ||
6228 MaskBV->getOperand(Mask[i] % Size) !=
6229 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6236 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6238 /// This helper function produces an 8-bit shuffle immediate corresponding to
6239 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6240 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6243 /// NB: We rely heavily on "undef" masks preserving the input lane.
6244 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6245 SelectionDAG &DAG) {
6246 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6247 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6248 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6249 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6250 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6253 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6254 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6255 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6256 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6257 return DAG.getConstant(Imm, DL, MVT::i8);
6260 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6262 /// This is used as a fallback approach when first class blend instructions are
6263 /// unavailable. Currently it is only suitable for integer vectors, but could
6264 /// be generalized for floating point vectors if desirable.
6265 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6266 SDValue V2, ArrayRef<int> Mask,
6267 SelectionDAG &DAG) {
6268 assert(VT.isInteger() && "Only supports integer vector types!");
6269 MVT EltVT = VT.getScalarType();
6270 int NumEltBits = EltVT.getSizeInBits();
6271 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6272 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6274 SmallVector<SDValue, 16> MaskOps;
6275 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6276 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6277 return SDValue(); // Shuffled input!
6278 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6281 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6282 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6283 // We have to cast V2 around.
6284 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6285 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6286 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6287 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6288 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6289 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6292 /// \brief Try to emit a blend instruction for a shuffle.
6294 /// This doesn't do any checks for the availability of instructions for blending
6295 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6296 /// be matched in the backend with the type given. What it does check for is
6297 /// that the shuffle mask is in fact a blend.
6298 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6299 SDValue V2, ArrayRef<int> Mask,
6300 const X86Subtarget *Subtarget,
6301 SelectionDAG &DAG) {
6302 unsigned BlendMask = 0;
6303 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6304 if (Mask[i] >= Size) {
6305 if (Mask[i] != i + Size)
6306 return SDValue(); // Shuffled V2 input!
6307 BlendMask |= 1u << i;
6310 if (Mask[i] >= 0 && Mask[i] != i)
6311 return SDValue(); // Shuffled V1 input!
6313 switch (VT.SimpleTy) {
6318 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6319 DAG.getConstant(BlendMask, DL, MVT::i8));
6323 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6327 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6328 // that instruction.
6329 if (Subtarget->hasAVX2()) {
6330 // Scale the blend by the number of 32-bit dwords per element.
6331 int Scale = VT.getScalarSizeInBits() / 32;
6333 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6334 if (Mask[i] >= Size)
6335 for (int j = 0; j < Scale; ++j)
6336 BlendMask |= 1u << (i * Scale + j);
6338 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6339 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6340 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6341 return DAG.getNode(ISD::BITCAST, DL, VT,
6342 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6343 DAG.getConstant(BlendMask, DL, MVT::i8)));
6347 // For integer shuffles we need to expand the mask and cast the inputs to
6348 // v8i16s prior to blending.
6349 int Scale = 8 / VT.getVectorNumElements();
6351 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6352 if (Mask[i] >= Size)
6353 for (int j = 0; j < Scale; ++j)
6354 BlendMask |= 1u << (i * Scale + j);
6356 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6357 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6358 return DAG.getNode(ISD::BITCAST, DL, VT,
6359 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6360 DAG.getConstant(BlendMask, DL, MVT::i8)));
6364 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6365 SmallVector<int, 8> RepeatedMask;
6366 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6367 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6368 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6370 for (int i = 0; i < 8; ++i)
6371 if (RepeatedMask[i] >= 16)
6372 BlendMask |= 1u << i;
6373 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6374 DAG.getConstant(BlendMask, DL, MVT::i8));
6380 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6381 "256-bit byte-blends require AVX2 support!");
6383 // Scale the blend by the number of bytes per element.
6384 int Scale = VT.getScalarSizeInBits() / 8;
6386 // This form of blend is always done on bytes. Compute the byte vector
6388 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6390 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6391 // mix of LLVM's code generator and the x86 backend. We tell the code
6392 // generator that boolean values in the elements of an x86 vector register
6393 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6394 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6395 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6396 // of the element (the remaining are ignored) and 0 in that high bit would
6397 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6398 // the LLVM model for boolean values in vector elements gets the relevant
6399 // bit set, it is set backwards and over constrained relative to x86's
6401 SmallVector<SDValue, 32> VSELECTMask;
6402 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6403 for (int j = 0; j < Scale; ++j)
6404 VSELECTMask.push_back(
6405 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6406 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6409 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6410 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6412 ISD::BITCAST, DL, VT,
6413 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6414 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6419 llvm_unreachable("Not a supported integer vector type!");
6423 /// \brief Try to lower as a blend of elements from two inputs followed by
6424 /// a single-input permutation.
6426 /// This matches the pattern where we can blend elements from two inputs and
6427 /// then reduce the shuffle to a single-input permutation.
6428 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6431 SelectionDAG &DAG) {
6432 // We build up the blend mask while checking whether a blend is a viable way
6433 // to reduce the shuffle.
6434 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6435 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6437 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6441 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6443 if (BlendMask[Mask[i] % Size] == -1)
6444 BlendMask[Mask[i] % Size] = Mask[i];
6445 else if (BlendMask[Mask[i] % Size] != Mask[i])
6446 return SDValue(); // Can't blend in the needed input!
6448 PermuteMask[i] = Mask[i] % Size;
6451 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6452 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6455 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6456 /// blends and permutes.
6458 /// This matches the extremely common pattern for handling combined
6459 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6460 /// operations. It will try to pick the best arrangement of shuffles and
6462 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6466 SelectionDAG &DAG) {
6467 // Shuffle the input elements into the desired positions in V1 and V2 and
6468 // blend them together.
6469 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6470 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6471 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6472 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6473 if (Mask[i] >= 0 && Mask[i] < Size) {
6474 V1Mask[i] = Mask[i];
6476 } else if (Mask[i] >= Size) {
6477 V2Mask[i] = Mask[i] - Size;
6478 BlendMask[i] = i + Size;
6481 // Try to lower with the simpler initial blend strategy unless one of the
6482 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6483 // shuffle may be able to fold with a load or other benefit. However, when
6484 // we'll have to do 2x as many shuffles in order to achieve this, blending
6485 // first is a better strategy.
6486 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6487 if (SDValue BlendPerm =
6488 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6491 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6492 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6493 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6496 /// \brief Try to lower a vector shuffle as a byte rotation.
6498 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6499 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6500 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6501 /// try to generically lower a vector shuffle through such an pattern. It
6502 /// does not check for the profitability of lowering either as PALIGNR or
6503 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6504 /// This matches shuffle vectors that look like:
6506 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6508 /// Essentially it concatenates V1 and V2, shifts right by some number of
6509 /// elements, and takes the low elements as the result. Note that while this is
6510 /// specified as a *right shift* because x86 is little-endian, it is a *left
6511 /// rotate* of the vector lanes.
6512 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6515 const X86Subtarget *Subtarget,
6516 SelectionDAG &DAG) {
6517 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6519 int NumElts = Mask.size();
6520 int NumLanes = VT.getSizeInBits() / 128;
6521 int NumLaneElts = NumElts / NumLanes;
6523 // We need to detect various ways of spelling a rotation:
6524 // [11, 12, 13, 14, 15, 0, 1, 2]
6525 // [-1, 12, 13, 14, -1, -1, 1, -1]
6526 // [-1, -1, -1, -1, -1, -1, 1, 2]
6527 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6528 // [-1, 4, 5, 6, -1, -1, 9, -1]
6529 // [-1, 4, 5, 6, -1, -1, -1, -1]
6532 for (int l = 0; l < NumElts; l += NumLaneElts) {
6533 for (int i = 0; i < NumLaneElts; ++i) {
6534 if (Mask[l + i] == -1)
6536 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6538 // Get the mod-Size index and lane correct it.
6539 int LaneIdx = (Mask[l + i] % NumElts) - l;
6540 // Make sure it was in this lane.
6541 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6544 // Determine where a rotated vector would have started.
6545 int StartIdx = i - LaneIdx;
6547 // The identity rotation isn't interesting, stop.
6550 // If we found the tail of a vector the rotation must be the missing
6551 // front. If we found the head of a vector, it must be how much of the
6553 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6556 Rotation = CandidateRotation;
6557 else if (Rotation != CandidateRotation)
6558 // The rotations don't match, so we can't match this mask.
6561 // Compute which value this mask is pointing at.
6562 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6564 // Compute which of the two target values this index should be assigned
6565 // to. This reflects whether the high elements are remaining or the low
6566 // elements are remaining.
6567 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6569 // Either set up this value if we've not encountered it before, or check
6570 // that it remains consistent.
6573 else if (TargetV != MaskV)
6574 // This may be a rotation, but it pulls from the inputs in some
6575 // unsupported interleaving.
6580 // Check that we successfully analyzed the mask, and normalize the results.
6581 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6582 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6588 // The actual rotate instruction rotates bytes, so we need to scale the
6589 // rotation based on how many bytes are in the vector lane.
6590 int Scale = 16 / NumLaneElts;
6592 // SSSE3 targets can use the palignr instruction.
6593 if (Subtarget->hasSSSE3()) {
6594 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6595 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6596 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6597 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6599 return DAG.getNode(ISD::BITCAST, DL, VT,
6600 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6601 DAG.getConstant(Rotation * Scale, DL,
6605 assert(VT.getSizeInBits() == 128 &&
6606 "Rotate-based lowering only supports 128-bit lowering!");
6607 assert(Mask.size() <= 16 &&
6608 "Can shuffle at most 16 bytes in a 128-bit vector!");
6610 // Default SSE2 implementation
6611 int LoByteShift = 16 - Rotation * Scale;
6612 int HiByteShift = Rotation * Scale;
6614 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6615 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6616 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6618 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6619 DAG.getConstant(LoByteShift, DL, MVT::i8));
6620 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6621 DAG.getConstant(HiByteShift, DL, MVT::i8));
6622 return DAG.getNode(ISD::BITCAST, DL, VT,
6623 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6626 /// \brief Compute whether each element of a shuffle is zeroable.
6628 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6629 /// Either it is an undef element in the shuffle mask, the element of the input
6630 /// referenced is undef, or the element of the input referenced is known to be
6631 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6632 /// as many lanes with this technique as possible to simplify the remaining
6634 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6635 SDValue V1, SDValue V2) {
6636 SmallBitVector Zeroable(Mask.size(), false);
6638 while (V1.getOpcode() == ISD::BITCAST)
6639 V1 = V1->getOperand(0);
6640 while (V2.getOpcode() == ISD::BITCAST)
6641 V2 = V2->getOperand(0);
6643 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6644 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6646 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6648 // Handle the easy cases.
6649 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6654 // If this is an index into a build_vector node (which has the same number
6655 // of elements), dig out the input value and use it.
6656 SDValue V = M < Size ? V1 : V2;
6657 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6660 SDValue Input = V.getOperand(M % Size);
6661 // The UNDEF opcode check really should be dead code here, but not quite
6662 // worth asserting on (it isn't invalid, just unexpected).
6663 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6670 /// \brief Try to emit a bitmask instruction for a shuffle.
6672 /// This handles cases where we can model a blend exactly as a bitmask due to
6673 /// one of the inputs being zeroable.
6674 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6675 SDValue V2, ArrayRef<int> Mask,
6676 SelectionDAG &DAG) {
6677 MVT EltVT = VT.getScalarType();
6678 int NumEltBits = EltVT.getSizeInBits();
6679 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6680 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6681 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6683 if (EltVT.isFloatingPoint()) {
6684 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6685 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6687 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6688 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6690 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6693 if (Mask[i] % Size != i)
6694 return SDValue(); // Not a blend.
6696 V = Mask[i] < Size ? V1 : V2;
6697 else if (V != (Mask[i] < Size ? V1 : V2))
6698 return SDValue(); // Can only let one input through the mask.
6700 VMaskOps[i] = AllOnes;
6703 return SDValue(); // No non-zeroable elements!
6705 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6706 V = DAG.getNode(VT.isFloatingPoint()
6707 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6712 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6714 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6715 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6716 /// matches elements from one of the input vectors shuffled to the left or
6717 /// right with zeroable elements 'shifted in'. It handles both the strictly
6718 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6721 /// PSHL : (little-endian) left bit shift.
6722 /// [ zz, 0, zz, 2 ]
6723 /// [ -1, 4, zz, -1 ]
6724 /// PSRL : (little-endian) right bit shift.
6726 /// [ -1, -1, 7, zz]
6727 /// PSLLDQ : (little-endian) left byte shift
6728 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6729 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6730 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6731 /// PSRLDQ : (little-endian) right byte shift
6732 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6733 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6734 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6735 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6736 SDValue V2, ArrayRef<int> Mask,
6737 SelectionDAG &DAG) {
6738 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6740 int Size = Mask.size();
6741 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6743 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6744 for (int i = 0; i < Size; i += Scale)
6745 for (int j = 0; j < Shift; ++j)
6746 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6752 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6753 for (int i = 0; i != Size; i += Scale) {
6754 unsigned Pos = Left ? i + Shift : i;
6755 unsigned Low = Left ? i : i + Shift;
6756 unsigned Len = Scale - Shift;
6757 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6758 Low + (V == V1 ? 0 : Size)))
6762 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6763 bool ByteShift = ShiftEltBits > 64;
6764 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6765 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6766 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6768 // Normalize the scale for byte shifts to still produce an i64 element
6770 Scale = ByteShift ? Scale / 2 : Scale;
6772 // We need to round trip through the appropriate type for the shift.
6773 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6774 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6775 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6776 "Illegal integer vector type");
6777 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6779 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6780 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6781 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6784 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6785 // keep doubling the size of the integer elements up to that. We can
6786 // then shift the elements of the integer vector by whole multiples of
6787 // their width within the elements of the larger integer vector. Test each
6788 // multiple to see if we can find a match with the moved element indices
6789 // and that the shifted in elements are all zeroable.
6790 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6791 for (int Shift = 1; Shift != Scale; ++Shift)
6792 for (bool Left : {true, false})
6793 if (CheckZeros(Shift, Scale, Left))
6794 for (SDValue V : {V1, V2})
6795 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6802 /// \brief Lower a vector shuffle as a zero or any extension.
6804 /// Given a specific number of elements, element bit width, and extension
6805 /// stride, produce either a zero or any extension based on the available
6806 /// features of the subtarget.
6807 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6808 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6809 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6810 assert(Scale > 1 && "Need a scale to extend.");
6811 int NumElements = VT.getVectorNumElements();
6812 int EltBits = VT.getScalarSizeInBits();
6813 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6814 "Only 8, 16, and 32 bit elements can be extended.");
6815 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6817 // Found a valid zext mask! Try various lowering strategies based on the
6818 // input type and available ISA extensions.
6819 if (Subtarget->hasSSE41()) {
6820 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6821 NumElements / Scale);
6822 return DAG.getNode(ISD::BITCAST, DL, VT,
6823 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6826 // For any extends we can cheat for larger element sizes and use shuffle
6827 // instructions that can fold with a load and/or copy.
6828 if (AnyExt && EltBits == 32) {
6829 int PSHUFDMask[4] = {0, -1, 1, -1};
6831 ISD::BITCAST, DL, VT,
6832 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6833 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6834 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6836 if (AnyExt && EltBits == 16 && Scale > 2) {
6837 int PSHUFDMask[4] = {0, -1, 0, -1};
6838 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6839 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6840 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6841 int PSHUFHWMask[4] = {1, -1, -1, -1};
6843 ISD::BITCAST, DL, VT,
6844 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6845 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6846 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6849 // If this would require more than 2 unpack instructions to expand, use
6850 // pshufb when available. We can only use more than 2 unpack instructions
6851 // when zero extending i8 elements which also makes it easier to use pshufb.
6852 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6853 assert(NumElements == 16 && "Unexpected byte vector width!");
6854 SDValue PSHUFBMask[16];
6855 for (int i = 0; i < 16; ++i)
6857 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6858 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6859 return DAG.getNode(ISD::BITCAST, DL, VT,
6860 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6861 DAG.getNode(ISD::BUILD_VECTOR, DL,
6862 MVT::v16i8, PSHUFBMask)));
6865 // Otherwise emit a sequence of unpacks.
6867 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6868 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6869 : getZeroVector(InputVT, Subtarget, DAG, DL);
6870 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6871 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6875 } while (Scale > 1);
6876 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6879 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6881 /// This routine will try to do everything in its power to cleverly lower
6882 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6883 /// check for the profitability of this lowering, it tries to aggressively
6884 /// match this pattern. It will use all of the micro-architectural details it
6885 /// can to emit an efficient lowering. It handles both blends with all-zero
6886 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6887 /// masking out later).
6889 /// The reason we have dedicated lowering for zext-style shuffles is that they
6890 /// are both incredibly common and often quite performance sensitive.
6891 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6892 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6893 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6894 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6896 int Bits = VT.getSizeInBits();
6897 int NumElements = VT.getVectorNumElements();
6898 assert(VT.getScalarSizeInBits() <= 32 &&
6899 "Exceeds 32-bit integer zero extension limit");
6900 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6902 // Define a helper function to check a particular ext-scale and lower to it if
6904 auto Lower = [&](int Scale) -> SDValue {
6907 for (int i = 0; i < NumElements; ++i) {
6909 continue; // Valid anywhere but doesn't tell us anything.
6910 if (i % Scale != 0) {
6911 // Each of the extended elements need to be zeroable.
6915 // We no longer are in the anyext case.
6920 // Each of the base elements needs to be consecutive indices into the
6921 // same input vector.
6922 SDValue V = Mask[i] < NumElements ? V1 : V2;
6925 else if (InputV != V)
6926 return SDValue(); // Flip-flopping inputs.
6928 if (Mask[i] % NumElements != i / Scale)
6929 return SDValue(); // Non-consecutive strided elements.
6932 // If we fail to find an input, we have a zero-shuffle which should always
6933 // have already been handled.
6934 // FIXME: Maybe handle this here in case during blending we end up with one?
6938 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6939 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6942 // The widest scale possible for extending is to a 64-bit integer.
6943 assert(Bits % 64 == 0 &&
6944 "The number of bits in a vector must be divisible by 64 on x86!");
6945 int NumExtElements = Bits / 64;
6947 // Each iteration, try extending the elements half as much, but into twice as
6949 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6950 assert(NumElements % NumExtElements == 0 &&
6951 "The input vector size must be divisible by the extended size.");
6952 if (SDValue V = Lower(NumElements / NumExtElements))
6956 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6960 // Returns one of the source operands if the shuffle can be reduced to a
6961 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6962 auto CanZExtLowHalf = [&]() {
6963 for (int i = NumElements / 2; i != NumElements; ++i)
6966 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6968 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6973 if (SDValue V = CanZExtLowHalf()) {
6974 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6975 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6976 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6979 // No viable ext lowering found.
6983 /// \brief Try to get a scalar value for a specific element of a vector.
6985 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6986 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6987 SelectionDAG &DAG) {
6988 MVT VT = V.getSimpleValueType();
6989 MVT EltVT = VT.getVectorElementType();
6990 while (V.getOpcode() == ISD::BITCAST)
6991 V = V.getOperand(0);
6992 // If the bitcasts shift the element size, we can't extract an equivalent
6994 MVT NewVT = V.getSimpleValueType();
6995 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
6998 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6999 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7000 // Ensure the scalar operand is the same size as the destination.
7001 // FIXME: Add support for scalar truncation where possible.
7002 SDValue S = V.getOperand(Idx);
7003 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7004 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7010 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7012 /// This is particularly important because the set of instructions varies
7013 /// significantly based on whether the operand is a load or not.
7014 static bool isShuffleFoldableLoad(SDValue V) {
7015 while (V.getOpcode() == ISD::BITCAST)
7016 V = V.getOperand(0);
7018 return ISD::isNON_EXTLoad(V.getNode());
7021 /// \brief Try to lower insertion of a single element into a zero vector.
7023 /// This is a common pattern that we have especially efficient patterns to lower
7024 /// across all subtarget feature sets.
7025 static SDValue lowerVectorShuffleAsElementInsertion(
7026 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7027 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7028 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7030 MVT EltVT = VT.getVectorElementType();
7032 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7033 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7035 bool IsV1Zeroable = true;
7036 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7037 if (i != V2Index && !Zeroable[i]) {
7038 IsV1Zeroable = false;
7042 // Check for a single input from a SCALAR_TO_VECTOR node.
7043 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7044 // all the smarts here sunk into that routine. However, the current
7045 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7046 // vector shuffle lowering is dead.
7047 if (SDValue V2S = getScalarValueForVectorElement(
7048 V2, Mask[V2Index] - Mask.size(), DAG)) {
7049 // We need to zext the scalar if it is smaller than an i32.
7050 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7051 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7052 // Using zext to expand a narrow element won't work for non-zero
7057 // Zero-extend directly to i32.
7059 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7061 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7062 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7063 EltVT == MVT::i16) {
7064 // Either not inserting from the low element of the input or the input
7065 // element size is too small to use VZEXT_MOVL to clear the high bits.
7069 if (!IsV1Zeroable) {
7070 // If V1 can't be treated as a zero vector we have fewer options to lower
7071 // this. We can't support integer vectors or non-zero targets cheaply, and
7072 // the V1 elements can't be permuted in any way.
7073 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7074 if (!VT.isFloatingPoint() || V2Index != 0)
7076 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7077 V1Mask[V2Index] = -1;
7078 if (!isNoopShuffleMask(V1Mask))
7080 // This is essentially a special case blend operation, but if we have
7081 // general purpose blend operations, they are always faster. Bail and let
7082 // the rest of the lowering handle these as blends.
7083 if (Subtarget->hasSSE41())
7086 // Otherwise, use MOVSD or MOVSS.
7087 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7088 "Only two types of floating point element types to handle!");
7089 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7093 // This lowering only works for the low element with floating point vectors.
7094 if (VT.isFloatingPoint() && V2Index != 0)
7097 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7099 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7102 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7103 // the desired position. Otherwise it is more efficient to do a vector
7104 // shift left. We know that we can do a vector shift left because all
7105 // the inputs are zero.
7106 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7107 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7108 V2Shuffle[V2Index] = 0;
7109 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7111 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7113 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7115 V2Index * EltVT.getSizeInBits()/8, DL,
7116 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7117 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7123 /// \brief Try to lower broadcast of a single element.
7125 /// For convenience, this code also bundles all of the subtarget feature set
7126 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7127 /// a convenient way to factor it out.
7128 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7130 const X86Subtarget *Subtarget,
7131 SelectionDAG &DAG) {
7132 if (!Subtarget->hasAVX())
7134 if (VT.isInteger() && !Subtarget->hasAVX2())
7137 // Check that the mask is a broadcast.
7138 int BroadcastIdx = -1;
7140 if (M >= 0 && BroadcastIdx == -1)
7142 else if (M >= 0 && M != BroadcastIdx)
7145 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7146 "a sorted mask where the broadcast "
7149 // Go up the chain of (vector) values to find a scalar load that we can
7150 // combine with the broadcast.
7152 switch (V.getOpcode()) {
7153 case ISD::CONCAT_VECTORS: {
7154 int OperandSize = Mask.size() / V.getNumOperands();
7155 V = V.getOperand(BroadcastIdx / OperandSize);
7156 BroadcastIdx %= OperandSize;
7160 case ISD::INSERT_SUBVECTOR: {
7161 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7162 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7166 int BeginIdx = (int)ConstantIdx->getZExtValue();
7168 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7169 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7170 BroadcastIdx -= BeginIdx;
7181 // Check if this is a broadcast of a scalar. We special case lowering
7182 // for scalars so that we can more effectively fold with loads.
7183 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7184 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7185 V = V.getOperand(BroadcastIdx);
7187 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7188 // Only AVX2 has register broadcasts.
7189 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7191 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7192 // We can't broadcast from a vector register without AVX2, and we can only
7193 // broadcast from the zero-element of a vector register.
7197 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7200 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7201 // INSERTPS when the V1 elements are already in the correct locations
7202 // because otherwise we can just always use two SHUFPS instructions which
7203 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7204 // perform INSERTPS if a single V1 element is out of place and all V2
7205 // elements are zeroable.
7206 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7208 SelectionDAG &DAG) {
7209 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7210 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7211 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7212 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7214 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7217 int V1DstIndex = -1;
7218 int V2DstIndex = -1;
7219 bool V1UsedInPlace = false;
7221 for (int i = 0; i < 4; ++i) {
7222 // Synthesize a zero mask from the zeroable elements (includes undefs).
7228 // Flag if we use any V1 inputs in place.
7230 V1UsedInPlace = true;
7234 // We can only insert a single non-zeroable element.
7235 if (V1DstIndex != -1 || V2DstIndex != -1)
7239 // V1 input out of place for insertion.
7242 // V2 input for insertion.
7247 // Don't bother if we have no (non-zeroable) element for insertion.
7248 if (V1DstIndex == -1 && V2DstIndex == -1)
7251 // Determine element insertion src/dst indices. The src index is from the
7252 // start of the inserted vector, not the start of the concatenated vector.
7253 unsigned V2SrcIndex = 0;
7254 if (V1DstIndex != -1) {
7255 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7256 // and don't use the original V2 at all.
7257 V2SrcIndex = Mask[V1DstIndex];
7258 V2DstIndex = V1DstIndex;
7261 V2SrcIndex = Mask[V2DstIndex] - 4;
7264 // If no V1 inputs are used in place, then the result is created only from
7265 // the zero mask and the V2 insertion - so remove V1 dependency.
7267 V1 = DAG.getUNDEF(MVT::v4f32);
7269 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7270 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7272 // Insert the V2 element into the desired position.
7274 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7275 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7278 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7279 /// UNPCK instruction.
7281 /// This specifically targets cases where we end up with alternating between
7282 /// the two inputs, and so can permute them into something that feeds a single
7283 /// UNPCK instruction. Note that this routine only targets integer vectors
7284 /// because for floating point vectors we have a generalized SHUFPS lowering
7285 /// strategy that handles everything that doesn't *exactly* match an unpack,
7286 /// making this clever lowering unnecessary.
7287 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7288 SDValue V2, ArrayRef<int> Mask,
7289 SelectionDAG &DAG) {
7290 assert(!VT.isFloatingPoint() &&
7291 "This routine only supports integer vectors.");
7292 assert(!isSingleInputShuffleMask(Mask) &&
7293 "This routine should only be used when blending two inputs.");
7294 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7296 int Size = Mask.size();
7298 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7299 return M >= 0 && M % Size < Size / 2;
7301 int NumHiInputs = std::count_if(
7302 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7304 bool UnpackLo = NumLoInputs >= NumHiInputs;
7306 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7307 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7308 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7310 for (int i = 0; i < Size; ++i) {
7314 // Each element of the unpack contains Scale elements from this mask.
7315 int UnpackIdx = i / Scale;
7317 // We only handle the case where V1 feeds the first slots of the unpack.
7318 // We rely on canonicalization to ensure this is the case.
7319 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7322 // Setup the mask for this input. The indexing is tricky as we have to
7323 // handle the unpack stride.
7324 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7325 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7329 // If we will have to shuffle both inputs to use the unpack, check whether
7330 // we can just unpack first and shuffle the result. If so, skip this unpack.
7331 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7332 !isNoopShuffleMask(V2Mask))
7335 // Shuffle the inputs into place.
7336 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7337 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7339 // Cast the inputs to the type we will use to unpack them.
7340 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7341 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7343 // Unpack the inputs and cast the result back to the desired type.
7344 return DAG.getNode(ISD::BITCAST, DL, VT,
7345 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7346 DL, UnpackVT, V1, V2));
7349 // We try each unpack from the largest to the smallest to try and find one
7350 // that fits this mask.
7351 int OrigNumElements = VT.getVectorNumElements();
7352 int OrigScalarSize = VT.getScalarSizeInBits();
7353 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7354 int Scale = ScalarSize / OrigScalarSize;
7355 int NumElements = OrigNumElements / Scale;
7356 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7357 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7361 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7363 if (NumLoInputs == 0 || NumHiInputs == 0) {
7364 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7365 "We have to have *some* inputs!");
7366 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7368 // FIXME: We could consider the total complexity of the permute of each
7369 // possible unpacking. Or at the least we should consider how many
7370 // half-crossings are created.
7371 // FIXME: We could consider commuting the unpacks.
7373 SmallVector<int, 32> PermMask;
7374 PermMask.assign(Size, -1);
7375 for (int i = 0; i < Size; ++i) {
7379 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7382 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7384 return DAG.getVectorShuffle(
7385 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7387 DAG.getUNDEF(VT), PermMask);
7393 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7395 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7396 /// support for floating point shuffles but not integer shuffles. These
7397 /// instructions will incur a domain crossing penalty on some chips though so
7398 /// it is better to avoid lowering through this for integer vectors where
7400 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7401 const X86Subtarget *Subtarget,
7402 SelectionDAG &DAG) {
7404 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7405 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7406 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7407 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7408 ArrayRef<int> Mask = SVOp->getMask();
7409 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7411 if (isSingleInputShuffleMask(Mask)) {
7412 // Use low duplicate instructions for masks that match their pattern.
7413 if (Subtarget->hasSSE3())
7414 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7415 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7417 // Straight shuffle of a single input vector. Simulate this by using the
7418 // single input as both of the "inputs" to this instruction..
7419 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7421 if (Subtarget->hasAVX()) {
7422 // If we have AVX, we can use VPERMILPS which will allow folding a load
7423 // into the shuffle.
7424 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7425 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7428 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7429 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7431 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7432 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7434 // If we have a single input, insert that into V1 if we can do so cheaply.
7435 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7436 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7437 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7439 // Try inverting the insertion since for v2 masks it is easy to do and we
7440 // can't reliably sort the mask one way or the other.
7441 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7442 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7443 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7444 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7448 // Try to use one of the special instruction patterns to handle two common
7449 // blend patterns if a zero-blend above didn't work.
7450 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7451 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7452 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7453 // We can either use a special instruction to load over the low double or
7454 // to move just the low double.
7456 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7458 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7460 if (Subtarget->hasSSE41())
7461 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7465 // Use dedicated unpack instructions for masks that match their pattern.
7466 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7467 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7468 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7469 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7471 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7472 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7473 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7476 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7478 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7479 /// the integer unit to minimize domain crossing penalties. However, for blends
7480 /// it falls back to the floating point shuffle operation with appropriate bit
7482 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7483 const X86Subtarget *Subtarget,
7484 SelectionDAG &DAG) {
7486 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7487 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7488 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7489 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7490 ArrayRef<int> Mask = SVOp->getMask();
7491 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7493 if (isSingleInputShuffleMask(Mask)) {
7494 // Check for being able to broadcast a single element.
7495 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7496 Mask, Subtarget, DAG))
7499 // Straight shuffle of a single input vector. For everything from SSE2
7500 // onward this has a single fast instruction with no scary immediates.
7501 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7502 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7503 int WidenedMask[4] = {
7504 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7505 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7507 ISD::BITCAST, DL, MVT::v2i64,
7508 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7509 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7511 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7512 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7513 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7514 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7516 // If we have a blend of two PACKUS operations an the blend aligns with the
7517 // low and half halves, we can just merge the PACKUS operations. This is
7518 // particularly important as it lets us merge shuffles that this routine itself
7520 auto GetPackNode = [](SDValue V) {
7521 while (V.getOpcode() == ISD::BITCAST)
7522 V = V.getOperand(0);
7524 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7526 if (SDValue V1Pack = GetPackNode(V1))
7527 if (SDValue V2Pack = GetPackNode(V2))
7528 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7529 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7530 Mask[0] == 0 ? V1Pack.getOperand(0)
7531 : V1Pack.getOperand(1),
7532 Mask[1] == 2 ? V2Pack.getOperand(0)
7533 : V2Pack.getOperand(1)));
7535 // Try to use shift instructions.
7537 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7540 // When loading a scalar and then shuffling it into a vector we can often do
7541 // the insertion cheaply.
7542 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7543 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7545 // Try inverting the insertion since for v2 masks it is easy to do and we
7546 // can't reliably sort the mask one way or the other.
7547 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7548 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7549 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7552 // We have different paths for blend lowering, but they all must use the
7553 // *exact* same predicate.
7554 bool IsBlendSupported = Subtarget->hasSSE41();
7555 if (IsBlendSupported)
7556 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7560 // Use dedicated unpack instructions for masks that match their pattern.
7561 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7562 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7563 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7564 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7566 // Try to use byte rotation instructions.
7567 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7568 if (Subtarget->hasSSSE3())
7569 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7570 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7573 // If we have direct support for blends, we should lower by decomposing into
7574 // a permute. That will be faster than the domain cross.
7575 if (IsBlendSupported)
7576 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7579 // We implement this with SHUFPD which is pretty lame because it will likely
7580 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7581 // However, all the alternatives are still more cycles and newer chips don't
7582 // have this problem. It would be really nice if x86 had better shuffles here.
7583 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7584 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7585 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7586 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7589 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7591 /// This is used to disable more specialized lowerings when the shufps lowering
7592 /// will happen to be efficient.
7593 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7594 // This routine only handles 128-bit shufps.
7595 assert(Mask.size() == 4 && "Unsupported mask size!");
7597 // To lower with a single SHUFPS we need to have the low half and high half
7598 // each requiring a single input.
7599 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7601 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7607 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7609 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7610 /// It makes no assumptions about whether this is the *best* lowering, it simply
7612 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7613 ArrayRef<int> Mask, SDValue V1,
7614 SDValue V2, SelectionDAG &DAG) {
7615 SDValue LowV = V1, HighV = V2;
7616 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7619 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7621 if (NumV2Elements == 1) {
7623 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7626 // Compute the index adjacent to V2Index and in the same half by toggling
7628 int V2AdjIndex = V2Index ^ 1;
7630 if (Mask[V2AdjIndex] == -1) {
7631 // Handles all the cases where we have a single V2 element and an undef.
7632 // This will only ever happen in the high lanes because we commute the
7633 // vector otherwise.
7635 std::swap(LowV, HighV);
7636 NewMask[V2Index] -= 4;
7638 // Handle the case where the V2 element ends up adjacent to a V1 element.
7639 // To make this work, blend them together as the first step.
7640 int V1Index = V2AdjIndex;
7641 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7642 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7643 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7645 // Now proceed to reconstruct the final blend as we have the necessary
7646 // high or low half formed.
7653 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7654 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7656 } else if (NumV2Elements == 2) {
7657 if (Mask[0] < 4 && Mask[1] < 4) {
7658 // Handle the easy case where we have V1 in the low lanes and V2 in the
7662 } else if (Mask[2] < 4 && Mask[3] < 4) {
7663 // We also handle the reversed case because this utility may get called
7664 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7665 // arrange things in the right direction.
7671 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7672 // trying to place elements directly, just blend them and set up the final
7673 // shuffle to place them.
7675 // The first two blend mask elements are for V1, the second two are for
7677 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7678 Mask[2] < 4 ? Mask[2] : Mask[3],
7679 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7680 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7681 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7682 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7684 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7687 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7688 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7689 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7690 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7693 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7694 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7697 /// \brief Lower 4-lane 32-bit floating point shuffles.
7699 /// Uses instructions exclusively from the floating point unit to minimize
7700 /// domain crossing penalties, as these are sufficient to implement all v4f32
7702 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7703 const X86Subtarget *Subtarget,
7704 SelectionDAG &DAG) {
7706 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7707 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7708 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7709 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7710 ArrayRef<int> Mask = SVOp->getMask();
7711 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7714 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7716 if (NumV2Elements == 0) {
7717 // Check for being able to broadcast a single element.
7718 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7719 Mask, Subtarget, DAG))
7722 // Use even/odd duplicate instructions for masks that match their pattern.
7723 if (Subtarget->hasSSE3()) {
7724 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7725 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7726 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7727 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7730 if (Subtarget->hasAVX()) {
7731 // If we have AVX, we can use VPERMILPS which will allow folding a load
7732 // into the shuffle.
7733 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7734 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7737 // Otherwise, use a straight shuffle of a single input vector. We pass the
7738 // input vector to both operands to simulate this with a SHUFPS.
7739 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7740 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7743 // There are special ways we can lower some single-element blends. However, we
7744 // have custom ways we can lower more complex single-element blends below that
7745 // we defer to if both this and BLENDPS fail to match, so restrict this to
7746 // when the V2 input is targeting element 0 of the mask -- that is the fast
7748 if (NumV2Elements == 1 && Mask[0] >= 4)
7749 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7750 Mask, Subtarget, DAG))
7753 if (Subtarget->hasSSE41()) {
7754 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7758 // Use INSERTPS if we can complete the shuffle efficiently.
7759 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7762 if (!isSingleSHUFPSMask(Mask))
7763 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7764 DL, MVT::v4f32, V1, V2, Mask, DAG))
7768 // Use dedicated unpack instructions for masks that match their pattern.
7769 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7770 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7771 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7772 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7773 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7774 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7775 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7776 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7778 // Otherwise fall back to a SHUFPS lowering strategy.
7779 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7782 /// \brief Lower 4-lane i32 vector shuffles.
7784 /// We try to handle these with integer-domain shuffles where we can, but for
7785 /// blends we use the floating point domain blend instructions.
7786 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7787 const X86Subtarget *Subtarget,
7788 SelectionDAG &DAG) {
7790 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7791 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7792 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7793 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7794 ArrayRef<int> Mask = SVOp->getMask();
7795 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7797 // Whenever we can lower this as a zext, that instruction is strictly faster
7798 // than any alternative. It also allows us to fold memory operands into the
7799 // shuffle in many cases.
7800 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7801 Mask, Subtarget, DAG))
7805 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7807 if (NumV2Elements == 0) {
7808 // Check for being able to broadcast a single element.
7809 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7810 Mask, Subtarget, DAG))
7813 // Straight shuffle of a single input vector. For everything from SSE2
7814 // onward this has a single fast instruction with no scary immediates.
7815 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7816 // but we aren't actually going to use the UNPCK instruction because doing
7817 // so prevents folding a load into this instruction or making a copy.
7818 const int UnpackLoMask[] = {0, 0, 1, 1};
7819 const int UnpackHiMask[] = {2, 2, 3, 3};
7820 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7821 Mask = UnpackLoMask;
7822 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7823 Mask = UnpackHiMask;
7825 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7826 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7829 // Try to use shift instructions.
7831 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7834 // There are special ways we can lower some single-element blends.
7835 if (NumV2Elements == 1)
7836 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7837 Mask, Subtarget, DAG))
7840 // We have different paths for blend lowering, but they all must use the
7841 // *exact* same predicate.
7842 bool IsBlendSupported = Subtarget->hasSSE41();
7843 if (IsBlendSupported)
7844 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7848 if (SDValue Masked =
7849 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7852 // Use dedicated unpack instructions for masks that match their pattern.
7853 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7854 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7855 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7856 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7857 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7858 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7859 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7860 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7862 // Try to use byte rotation instructions.
7863 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7864 if (Subtarget->hasSSSE3())
7865 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7866 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7869 // If we have direct support for blends, we should lower by decomposing into
7870 // a permute. That will be faster than the domain cross.
7871 if (IsBlendSupported)
7872 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7875 // Try to lower by permuting the inputs into an unpack instruction.
7876 if (SDValue Unpack =
7877 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7880 // We implement this with SHUFPS because it can blend from two vectors.
7881 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7882 // up the inputs, bypassing domain shift penalties that we would encur if we
7883 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7885 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7886 DAG.getVectorShuffle(
7888 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7889 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7892 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7893 /// shuffle lowering, and the most complex part.
7895 /// The lowering strategy is to try to form pairs of input lanes which are
7896 /// targeted at the same half of the final vector, and then use a dword shuffle
7897 /// to place them onto the right half, and finally unpack the paired lanes into
7898 /// their final position.
7900 /// The exact breakdown of how to form these dword pairs and align them on the
7901 /// correct sides is really tricky. See the comments within the function for
7902 /// more of the details.
7904 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7905 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7906 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7907 /// vector, form the analogous 128-bit 8-element Mask.
7908 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7909 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7910 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7911 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7912 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7914 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7915 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7916 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7918 SmallVector<int, 4> LoInputs;
7919 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7920 [](int M) { return M >= 0; });
7921 std::sort(LoInputs.begin(), LoInputs.end());
7922 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7923 SmallVector<int, 4> HiInputs;
7924 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7925 [](int M) { return M >= 0; });
7926 std::sort(HiInputs.begin(), HiInputs.end());
7927 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7929 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7930 int NumHToL = LoInputs.size() - NumLToL;
7932 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7933 int NumHToH = HiInputs.size() - NumLToH;
7934 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7935 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7936 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7937 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7939 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7940 // such inputs we can swap two of the dwords across the half mark and end up
7941 // with <=2 inputs to each half in each half. Once there, we can fall through
7942 // to the generic code below. For example:
7944 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7945 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7947 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7948 // and an existing 2-into-2 on the other half. In this case we may have to
7949 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7950 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7951 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7952 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7953 // half than the one we target for fixing) will be fixed when we re-enter this
7954 // path. We will also combine away any sequence of PSHUFD instructions that
7955 // result into a single instruction. Here is an example of the tricky case:
7957 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7958 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7960 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7962 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7963 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7965 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7966 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7968 // The result is fine to be handled by the generic logic.
7969 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7970 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7971 int AOffset, int BOffset) {
7972 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7973 "Must call this with A having 3 or 1 inputs from the A half.");
7974 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7975 "Must call this with B having 1 or 3 inputs from the B half.");
7976 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7977 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7979 // Compute the index of dword with only one word among the three inputs in
7980 // a half by taking the sum of the half with three inputs and subtracting
7981 // the sum of the actual three inputs. The difference is the remaining
7984 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7985 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7986 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7987 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7988 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7989 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7990 int TripleNonInputIdx =
7991 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7992 TripleDWord = TripleNonInputIdx / 2;
7994 // We use xor with one to compute the adjacent DWord to whichever one the
7996 OneInputDWord = (OneInput / 2) ^ 1;
7998 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7999 // and BToA inputs. If there is also such a problem with the BToB and AToB
8000 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8001 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8002 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8003 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8004 // Compute how many inputs will be flipped by swapping these DWords. We
8006 // to balance this to ensure we don't form a 3-1 shuffle in the other
8008 int NumFlippedAToBInputs =
8009 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8010 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8011 int NumFlippedBToBInputs =
8012 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8013 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8014 if ((NumFlippedAToBInputs == 1 &&
8015 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8016 (NumFlippedBToBInputs == 1 &&
8017 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8018 // We choose whether to fix the A half or B half based on whether that
8019 // half has zero flipped inputs. At zero, we may not be able to fix it
8020 // with that half. We also bias towards fixing the B half because that
8021 // will more commonly be the high half, and we have to bias one way.
8022 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8023 ArrayRef<int> Inputs) {
8024 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8025 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8026 PinnedIdx ^ 1) != Inputs.end();
8027 // Determine whether the free index is in the flipped dword or the
8028 // unflipped dword based on where the pinned index is. We use this bit
8029 // in an xor to conditionally select the adjacent dword.
8030 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8031 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8032 FixFreeIdx) != Inputs.end();
8033 if (IsFixIdxInput == IsFixFreeIdxInput)
8035 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8036 FixFreeIdx) != Inputs.end();
8037 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8038 "We need to be changing the number of flipped inputs!");
8039 int PSHUFHalfMask[] = {0, 1, 2, 3};
8040 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8041 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8043 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8046 if (M != -1 && M == FixIdx)
8048 else if (M != -1 && M == FixFreeIdx)
8051 if (NumFlippedBToBInputs != 0) {
8053 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8054 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8056 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8058 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8059 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8064 int PSHUFDMask[] = {0, 1, 2, 3};
8065 PSHUFDMask[ADWord] = BDWord;
8066 PSHUFDMask[BDWord] = ADWord;
8067 V = DAG.getNode(ISD::BITCAST, DL, VT,
8068 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8069 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8070 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8073 // Adjust the mask to match the new locations of A and B.
8075 if (M != -1 && M/2 == ADWord)
8076 M = 2 * BDWord + M % 2;
8077 else if (M != -1 && M/2 == BDWord)
8078 M = 2 * ADWord + M % 2;
8080 // Recurse back into this routine to re-compute state now that this isn't
8081 // a 3 and 1 problem.
8082 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8085 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8086 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8087 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8088 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8090 // At this point there are at most two inputs to the low and high halves from
8091 // each half. That means the inputs can always be grouped into dwords and
8092 // those dwords can then be moved to the correct half with a dword shuffle.
8093 // We use at most one low and one high word shuffle to collect these paired
8094 // inputs into dwords, and finally a dword shuffle to place them.
8095 int PSHUFLMask[4] = {-1, -1, -1, -1};
8096 int PSHUFHMask[4] = {-1, -1, -1, -1};
8097 int PSHUFDMask[4] = {-1, -1, -1, -1};
8099 // First fix the masks for all the inputs that are staying in their
8100 // original halves. This will then dictate the targets of the cross-half
8102 auto fixInPlaceInputs =
8103 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8104 MutableArrayRef<int> SourceHalfMask,
8105 MutableArrayRef<int> HalfMask, int HalfOffset) {
8106 if (InPlaceInputs.empty())
8108 if (InPlaceInputs.size() == 1) {
8109 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8110 InPlaceInputs[0] - HalfOffset;
8111 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8114 if (IncomingInputs.empty()) {
8115 // Just fix all of the in place inputs.
8116 for (int Input : InPlaceInputs) {
8117 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8118 PSHUFDMask[Input / 2] = Input / 2;
8123 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8124 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8125 InPlaceInputs[0] - HalfOffset;
8126 // Put the second input next to the first so that they are packed into
8127 // a dword. We find the adjacent index by toggling the low bit.
8128 int AdjIndex = InPlaceInputs[0] ^ 1;
8129 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8130 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8131 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8133 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8134 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8136 // Now gather the cross-half inputs and place them into a free dword of
8137 // their target half.
8138 // FIXME: This operation could almost certainly be simplified dramatically to
8139 // look more like the 3-1 fixing operation.
8140 auto moveInputsToRightHalf = [&PSHUFDMask](
8141 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8142 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8143 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8145 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8146 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8148 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8150 int LowWord = Word & ~1;
8151 int HighWord = Word | 1;
8152 return isWordClobbered(SourceHalfMask, LowWord) ||
8153 isWordClobbered(SourceHalfMask, HighWord);
8156 if (IncomingInputs.empty())
8159 if (ExistingInputs.empty()) {
8160 // Map any dwords with inputs from them into the right half.
8161 for (int Input : IncomingInputs) {
8162 // If the source half mask maps over the inputs, turn those into
8163 // swaps and use the swapped lane.
8164 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8165 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8166 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8167 Input - SourceOffset;
8168 // We have to swap the uses in our half mask in one sweep.
8169 for (int &M : HalfMask)
8170 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8172 else if (M == Input)
8173 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8175 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8176 Input - SourceOffset &&
8177 "Previous placement doesn't match!");
8179 // Note that this correctly re-maps both when we do a swap and when
8180 // we observe the other side of the swap above. We rely on that to
8181 // avoid swapping the members of the input list directly.
8182 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8185 // Map the input's dword into the correct half.
8186 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8187 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8189 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8191 "Previous placement doesn't match!");
8194 // And just directly shift any other-half mask elements to be same-half
8195 // as we will have mirrored the dword containing the element into the
8196 // same position within that half.
8197 for (int &M : HalfMask)
8198 if (M >= SourceOffset && M < SourceOffset + 4) {
8199 M = M - SourceOffset + DestOffset;
8200 assert(M >= 0 && "This should never wrap below zero!");
8205 // Ensure we have the input in a viable dword of its current half. This
8206 // is particularly tricky because the original position may be clobbered
8207 // by inputs being moved and *staying* in that half.
8208 if (IncomingInputs.size() == 1) {
8209 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8210 int InputFixed = std::find(std::begin(SourceHalfMask),
8211 std::end(SourceHalfMask), -1) -
8212 std::begin(SourceHalfMask) + SourceOffset;
8213 SourceHalfMask[InputFixed - SourceOffset] =
8214 IncomingInputs[0] - SourceOffset;
8215 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8217 IncomingInputs[0] = InputFixed;
8219 } else if (IncomingInputs.size() == 2) {
8220 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8221 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8222 // We have two non-adjacent or clobbered inputs we need to extract from
8223 // the source half. To do this, we need to map them into some adjacent
8224 // dword slot in the source mask.
8225 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8226 IncomingInputs[1] - SourceOffset};
8228 // If there is a free slot in the source half mask adjacent to one of
8229 // the inputs, place the other input in it. We use (Index XOR 1) to
8230 // compute an adjacent index.
8231 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8232 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8233 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8234 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8235 InputsFixed[1] = InputsFixed[0] ^ 1;
8236 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8237 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8238 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8239 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8240 InputsFixed[0] = InputsFixed[1] ^ 1;
8241 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8242 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8243 // The two inputs are in the same DWord but it is clobbered and the
8244 // adjacent DWord isn't used at all. Move both inputs to the free
8246 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8247 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8248 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8249 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8251 // The only way we hit this point is if there is no clobbering
8252 // (because there are no off-half inputs to this half) and there is no
8253 // free slot adjacent to one of the inputs. In this case, we have to
8254 // swap an input with a non-input.
8255 for (int i = 0; i < 4; ++i)
8256 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8257 "We can't handle any clobbers here!");
8258 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8259 "Cannot have adjacent inputs here!");
8261 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8262 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8264 // We also have to update the final source mask in this case because
8265 // it may need to undo the above swap.
8266 for (int &M : FinalSourceHalfMask)
8267 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8268 M = InputsFixed[1] + SourceOffset;
8269 else if (M == InputsFixed[1] + SourceOffset)
8270 M = (InputsFixed[0] ^ 1) + SourceOffset;
8272 InputsFixed[1] = InputsFixed[0] ^ 1;
8275 // Point everything at the fixed inputs.
8276 for (int &M : HalfMask)
8277 if (M == IncomingInputs[0])
8278 M = InputsFixed[0] + SourceOffset;
8279 else if (M == IncomingInputs[1])
8280 M = InputsFixed[1] + SourceOffset;
8282 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8283 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8286 llvm_unreachable("Unhandled input size!");
8289 // Now hoist the DWord down to the right half.
8290 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8291 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8292 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8293 for (int &M : HalfMask)
8294 for (int Input : IncomingInputs)
8296 M = FreeDWord * 2 + Input % 2;
8298 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8299 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8300 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8301 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8303 // Now enact all the shuffles we've computed to move the inputs into their
8305 if (!isNoopShuffleMask(PSHUFLMask))
8306 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8307 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8308 if (!isNoopShuffleMask(PSHUFHMask))
8309 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8310 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8311 if (!isNoopShuffleMask(PSHUFDMask))
8312 V = DAG.getNode(ISD::BITCAST, DL, VT,
8313 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8314 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8315 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8318 // At this point, each half should contain all its inputs, and we can then
8319 // just shuffle them into their final position.
8320 assert(std::count_if(LoMask.begin(), LoMask.end(),
8321 [](int M) { return M >= 4; }) == 0 &&
8322 "Failed to lift all the high half inputs to the low mask!");
8323 assert(std::count_if(HiMask.begin(), HiMask.end(),
8324 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8325 "Failed to lift all the low half inputs to the high mask!");
8327 // Do a half shuffle for the low mask.
8328 if (!isNoopShuffleMask(LoMask))
8329 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8330 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8332 // Do a half shuffle with the high mask after shifting its values down.
8333 for (int &M : HiMask)
8336 if (!isNoopShuffleMask(HiMask))
8337 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8338 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8343 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8344 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8345 SDValue V2, ArrayRef<int> Mask,
8346 SelectionDAG &DAG, bool &V1InUse,
8348 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8354 int Size = Mask.size();
8355 int Scale = 16 / Size;
8356 for (int i = 0; i < 16; ++i) {
8357 if (Mask[i / Scale] == -1) {
8358 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8360 const int ZeroMask = 0x80;
8361 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8363 int V2Idx = Mask[i / Scale] < Size
8365 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8366 if (Zeroable[i / Scale])
8367 V1Idx = V2Idx = ZeroMask;
8368 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8369 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8370 V1InUse |= (ZeroMask != V1Idx);
8371 V2InUse |= (ZeroMask != V2Idx);
8376 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8377 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8378 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8380 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8381 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8382 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8384 // If we need shuffled inputs from both, blend the two.
8386 if (V1InUse && V2InUse)
8387 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8389 V = V1InUse ? V1 : V2;
8391 // Cast the result back to the correct type.
8392 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8395 /// \brief Generic lowering of 8-lane i16 shuffles.
8397 /// This handles both single-input shuffles and combined shuffle/blends with
8398 /// two inputs. The single input shuffles are immediately delegated to
8399 /// a dedicated lowering routine.
8401 /// The blends are lowered in one of three fundamental ways. If there are few
8402 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8403 /// of the input is significantly cheaper when lowered as an interleaving of
8404 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8405 /// halves of the inputs separately (making them have relatively few inputs)
8406 /// and then concatenate them.
8407 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8408 const X86Subtarget *Subtarget,
8409 SelectionDAG &DAG) {
8411 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8412 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8413 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8414 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8415 ArrayRef<int> OrigMask = SVOp->getMask();
8416 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8417 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8418 MutableArrayRef<int> Mask(MaskStorage);
8420 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8422 // Whenever we can lower this as a zext, that instruction is strictly faster
8423 // than any alternative.
8424 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8425 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8428 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8430 auto isV2 = [](int M) { return M >= 8; };
8432 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8434 if (NumV2Inputs == 0) {
8435 // Check for being able to broadcast a single element.
8436 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8437 Mask, Subtarget, DAG))
8440 // Try to use shift instructions.
8442 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8445 // Use dedicated unpack instructions for masks that match their pattern.
8446 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8447 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8448 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8449 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8451 // Try to use byte rotation instructions.
8452 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8453 Mask, Subtarget, DAG))
8456 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8460 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8461 "All single-input shuffles should be canonicalized to be V1-input "
8464 // Try to use shift instructions.
8466 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8469 // There are special ways we can lower some single-element blends.
8470 if (NumV2Inputs == 1)
8471 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8472 Mask, Subtarget, DAG))
8475 // We have different paths for blend lowering, but they all must use the
8476 // *exact* same predicate.
8477 bool IsBlendSupported = Subtarget->hasSSE41();
8478 if (IsBlendSupported)
8479 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8483 if (SDValue Masked =
8484 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8487 // Use dedicated unpack instructions for masks that match their pattern.
8488 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8489 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8490 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8491 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8493 // Try to use byte rotation instructions.
8494 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8495 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8498 if (SDValue BitBlend =
8499 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8502 if (SDValue Unpack =
8503 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8506 // If we can't directly blend but can use PSHUFB, that will be better as it
8507 // can both shuffle and set up the inefficient blend.
8508 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8509 bool V1InUse, V2InUse;
8510 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8514 // We can always bit-blend if we have to so the fallback strategy is to
8515 // decompose into single-input permutes and blends.
8516 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8520 /// \brief Check whether a compaction lowering can be done by dropping even
8521 /// elements and compute how many times even elements must be dropped.
8523 /// This handles shuffles which take every Nth element where N is a power of
8524 /// two. Example shuffle masks:
8526 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8527 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8528 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8529 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8530 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8531 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8533 /// Any of these lanes can of course be undef.
8535 /// This routine only supports N <= 3.
8536 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8539 /// \returns N above, or the number of times even elements must be dropped if
8540 /// there is such a number. Otherwise returns zero.
8541 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8542 // Figure out whether we're looping over two inputs or just one.
8543 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8545 // The modulus for the shuffle vector entries is based on whether this is
8546 // a single input or not.
8547 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8548 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8549 "We should only be called with masks with a power-of-2 size!");
8551 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8553 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8554 // and 2^3 simultaneously. This is because we may have ambiguity with
8555 // partially undef inputs.
8556 bool ViableForN[3] = {true, true, true};
8558 for (int i = 0, e = Mask.size(); i < e; ++i) {
8559 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8564 bool IsAnyViable = false;
8565 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8566 if (ViableForN[j]) {
8569 // The shuffle mask must be equal to (i * 2^N) % M.
8570 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8573 ViableForN[j] = false;
8575 // Early exit if we exhaust the possible powers of two.
8580 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8584 // Return 0 as there is no viable power of two.
8588 /// \brief Generic lowering of v16i8 shuffles.
8590 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8591 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8592 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8593 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8595 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8596 const X86Subtarget *Subtarget,
8597 SelectionDAG &DAG) {
8599 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8600 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8601 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8602 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8603 ArrayRef<int> Mask = SVOp->getMask();
8604 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8606 // Try to use shift instructions.
8608 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8611 // Try to use byte rotation instructions.
8612 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8613 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8616 // Try to use a zext lowering.
8617 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8618 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8622 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8624 // For single-input shuffles, there are some nicer lowering tricks we can use.
8625 if (NumV2Elements == 0) {
8626 // Check for being able to broadcast a single element.
8627 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8628 Mask, Subtarget, DAG))
8631 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8632 // Notably, this handles splat and partial-splat shuffles more efficiently.
8633 // However, it only makes sense if the pre-duplication shuffle simplifies
8634 // things significantly. Currently, this means we need to be able to
8635 // express the pre-duplication shuffle as an i16 shuffle.
8637 // FIXME: We should check for other patterns which can be widened into an
8638 // i16 shuffle as well.
8639 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8640 for (int i = 0; i < 16; i += 2)
8641 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8646 auto tryToWidenViaDuplication = [&]() -> SDValue {
8647 if (!canWidenViaDuplication(Mask))
8649 SmallVector<int, 4> LoInputs;
8650 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8651 [](int M) { return M >= 0 && M < 8; });
8652 std::sort(LoInputs.begin(), LoInputs.end());
8653 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8655 SmallVector<int, 4> HiInputs;
8656 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8657 [](int M) { return M >= 8; });
8658 std::sort(HiInputs.begin(), HiInputs.end());
8659 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8662 bool TargetLo = LoInputs.size() >= HiInputs.size();
8663 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8664 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8666 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8667 SmallDenseMap<int, int, 8> LaneMap;
8668 for (int I : InPlaceInputs) {
8669 PreDupI16Shuffle[I/2] = I/2;
8672 int j = TargetLo ? 0 : 4, je = j + 4;
8673 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8674 // Check if j is already a shuffle of this input. This happens when
8675 // there are two adjacent bytes after we move the low one.
8676 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8677 // If we haven't yet mapped the input, search for a slot into which
8679 while (j < je && PreDupI16Shuffle[j] != -1)
8683 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8686 // Map this input with the i16 shuffle.
8687 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8690 // Update the lane map based on the mapping we ended up with.
8691 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8694 ISD::BITCAST, DL, MVT::v16i8,
8695 DAG.getVectorShuffle(MVT::v8i16, DL,
8696 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8697 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8699 // Unpack the bytes to form the i16s that will be shuffled into place.
8700 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8701 MVT::v16i8, V1, V1);
8703 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8704 for (int i = 0; i < 16; ++i)
8705 if (Mask[i] != -1) {
8706 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8707 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8708 if (PostDupI16Shuffle[i / 2] == -1)
8709 PostDupI16Shuffle[i / 2] = MappedMask;
8711 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8712 "Conflicting entrties in the original shuffle!");
8715 ISD::BITCAST, DL, MVT::v16i8,
8716 DAG.getVectorShuffle(MVT::v8i16, DL,
8717 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8718 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8720 if (SDValue V = tryToWidenViaDuplication())
8724 // Use dedicated unpack instructions for masks that match their pattern.
8725 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8726 0, 16, 1, 17, 2, 18, 3, 19,
8728 4, 20, 5, 21, 6, 22, 7, 23}))
8729 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8730 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8731 8, 24, 9, 25, 10, 26, 11, 27,
8733 12, 28, 13, 29, 14, 30, 15, 31}))
8734 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8736 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8737 // with PSHUFB. It is important to do this before we attempt to generate any
8738 // blends but after all of the single-input lowerings. If the single input
8739 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8740 // want to preserve that and we can DAG combine any longer sequences into
8741 // a PSHUFB in the end. But once we start blending from multiple inputs,
8742 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8743 // and there are *very* few patterns that would actually be faster than the
8744 // PSHUFB approach because of its ability to zero lanes.
8746 // FIXME: The only exceptions to the above are blends which are exact
8747 // interleavings with direct instructions supporting them. We currently don't
8748 // handle those well here.
8749 if (Subtarget->hasSSSE3()) {
8750 bool V1InUse = false;
8751 bool V2InUse = false;
8753 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8754 DAG, V1InUse, V2InUse);
8756 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8757 // do so. This avoids using them to handle blends-with-zero which is
8758 // important as a single pshufb is significantly faster for that.
8759 if (V1InUse && V2InUse) {
8760 if (Subtarget->hasSSE41())
8761 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8762 Mask, Subtarget, DAG))
8765 // We can use an unpack to do the blending rather than an or in some
8766 // cases. Even though the or may be (very minorly) more efficient, we
8767 // preference this lowering because there are common cases where part of
8768 // the complexity of the shuffles goes away when we do the final blend as
8770 // FIXME: It might be worth trying to detect if the unpack-feeding
8771 // shuffles will both be pshufb, in which case we shouldn't bother with
8773 if (SDValue Unpack =
8774 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8781 // There are special ways we can lower some single-element blends.
8782 if (NumV2Elements == 1)
8783 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8784 Mask, Subtarget, DAG))
8787 if (SDValue BitBlend =
8788 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8791 // Check whether a compaction lowering can be done. This handles shuffles
8792 // which take every Nth element for some even N. See the helper function for
8795 // We special case these as they can be particularly efficiently handled with
8796 // the PACKUSB instruction on x86 and they show up in common patterns of
8797 // rearranging bytes to truncate wide elements.
8798 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8799 // NumEvenDrops is the power of two stride of the elements. Another way of
8800 // thinking about it is that we need to drop the even elements this many
8801 // times to get the original input.
8802 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8804 // First we need to zero all the dropped bytes.
8805 assert(NumEvenDrops <= 3 &&
8806 "No support for dropping even elements more than 3 times.");
8807 // We use the mask type to pick which bytes are preserved based on how many
8808 // elements are dropped.
8809 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8810 SDValue ByteClearMask =
8811 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8812 DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8813 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8815 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8817 // Now pack things back together.
8818 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8819 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8820 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8821 for (int i = 1; i < NumEvenDrops; ++i) {
8822 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8823 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8829 // Handle multi-input cases by blending single-input shuffles.
8830 if (NumV2Elements > 0)
8831 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8834 // The fallback path for single-input shuffles widens this into two v8i16
8835 // vectors with unpacks, shuffles those, and then pulls them back together
8839 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8840 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8841 for (int i = 0; i < 16; ++i)
8843 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8845 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8847 SDValue VLoHalf, VHiHalf;
8848 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8849 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8851 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8852 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8853 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8854 [](int M) { return M >= 0 && M % 2 == 1; })) {
8855 // Use a mask to drop the high bytes.
8856 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8857 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8858 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8860 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8861 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8863 // Squash the masks to point directly into VLoHalf.
8864 for (int &M : LoBlendMask)
8867 for (int &M : HiBlendMask)
8871 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8872 // VHiHalf so that we can blend them as i16s.
8873 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8874 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8875 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8876 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8879 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8880 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8882 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8885 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8887 /// This routine breaks down the specific type of 128-bit shuffle and
8888 /// dispatches to the lowering routines accordingly.
8889 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8890 MVT VT, const X86Subtarget *Subtarget,
8891 SelectionDAG &DAG) {
8892 switch (VT.SimpleTy) {
8894 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8896 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8898 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8900 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8902 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8904 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8907 llvm_unreachable("Unimplemented!");
8911 /// \brief Helper function to test whether a shuffle mask could be
8912 /// simplified by widening the elements being shuffled.
8914 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8915 /// leaves it in an unspecified state.
8917 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8918 /// shuffle masks. The latter have the special property of a '-2' representing
8919 /// a zero-ed lane of a vector.
8920 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8921 SmallVectorImpl<int> &WidenedMask) {
8922 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8923 // If both elements are undef, its trivial.
8924 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8925 WidenedMask.push_back(SM_SentinelUndef);
8929 // Check for an undef mask and a mask value properly aligned to fit with
8930 // a pair of values. If we find such a case, use the non-undef mask's value.
8931 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8932 WidenedMask.push_back(Mask[i + 1] / 2);
8935 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8936 WidenedMask.push_back(Mask[i] / 2);
8940 // When zeroing, we need to spread the zeroing across both lanes to widen.
8941 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8942 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8943 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8944 WidenedMask.push_back(SM_SentinelZero);
8950 // Finally check if the two mask values are adjacent and aligned with
8952 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8953 WidenedMask.push_back(Mask[i] / 2);
8957 // Otherwise we can't safely widen the elements used in this shuffle.
8960 assert(WidenedMask.size() == Mask.size() / 2 &&
8961 "Incorrect size of mask after widening the elements!");
8966 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8968 /// This routine just extracts two subvectors, shuffles them independently, and
8969 /// then concatenates them back together. This should work effectively with all
8970 /// AVX vector shuffle types.
8971 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8972 SDValue V2, ArrayRef<int> Mask,
8973 SelectionDAG &DAG) {
8974 assert(VT.getSizeInBits() >= 256 &&
8975 "Only for 256-bit or wider vector shuffles!");
8976 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8977 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8979 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8980 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8982 int NumElements = VT.getVectorNumElements();
8983 int SplitNumElements = NumElements / 2;
8984 MVT ScalarVT = VT.getScalarType();
8985 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8987 // Rather than splitting build-vectors, just build two narrower build
8988 // vectors. This helps shuffling with splats and zeros.
8989 auto SplitVector = [&](SDValue V) {
8990 while (V.getOpcode() == ISD::BITCAST)
8991 V = V->getOperand(0);
8993 MVT OrigVT = V.getSimpleValueType();
8994 int OrigNumElements = OrigVT.getVectorNumElements();
8995 int OrigSplitNumElements = OrigNumElements / 2;
8996 MVT OrigScalarVT = OrigVT.getScalarType();
8997 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9001 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9003 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9004 DAG.getIntPtrConstant(0, DL));
9005 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9006 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9009 SmallVector<SDValue, 16> LoOps, HiOps;
9010 for (int i = 0; i < OrigSplitNumElements; ++i) {
9011 LoOps.push_back(BV->getOperand(i));
9012 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9014 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9015 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9017 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
9018 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
9021 SDValue LoV1, HiV1, LoV2, HiV2;
9022 std::tie(LoV1, HiV1) = SplitVector(V1);
9023 std::tie(LoV2, HiV2) = SplitVector(V2);
9025 // Now create two 4-way blends of these half-width vectors.
9026 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9027 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9028 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9029 for (int i = 0; i < SplitNumElements; ++i) {
9030 int M = HalfMask[i];
9031 if (M >= NumElements) {
9032 if (M >= NumElements + SplitNumElements)
9036 V2BlendMask.push_back(M - NumElements);
9037 V1BlendMask.push_back(-1);
9038 BlendMask.push_back(SplitNumElements + i);
9039 } else if (M >= 0) {
9040 if (M >= SplitNumElements)
9044 V2BlendMask.push_back(-1);
9045 V1BlendMask.push_back(M);
9046 BlendMask.push_back(i);
9048 V2BlendMask.push_back(-1);
9049 V1BlendMask.push_back(-1);
9050 BlendMask.push_back(-1);
9054 // Because the lowering happens after all combining takes place, we need to
9055 // manually combine these blend masks as much as possible so that we create
9056 // a minimal number of high-level vector shuffle nodes.
9058 // First try just blending the halves of V1 or V2.
9059 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9060 return DAG.getUNDEF(SplitVT);
9061 if (!UseLoV2 && !UseHiV2)
9062 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9063 if (!UseLoV1 && !UseHiV1)
9064 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9066 SDValue V1Blend, V2Blend;
9067 if (UseLoV1 && UseHiV1) {
9069 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9071 // We only use half of V1 so map the usage down into the final blend mask.
9072 V1Blend = UseLoV1 ? LoV1 : HiV1;
9073 for (int i = 0; i < SplitNumElements; ++i)
9074 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9075 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9077 if (UseLoV2 && UseHiV2) {
9079 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9081 // We only use half of V2 so map the usage down into the final blend mask.
9082 V2Blend = UseLoV2 ? LoV2 : HiV2;
9083 for (int i = 0; i < SplitNumElements; ++i)
9084 if (BlendMask[i] >= SplitNumElements)
9085 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9087 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9089 SDValue Lo = HalfBlend(LoMask);
9090 SDValue Hi = HalfBlend(HiMask);
9091 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9094 /// \brief Either split a vector in halves or decompose the shuffles and the
9097 /// This is provided as a good fallback for many lowerings of non-single-input
9098 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9099 /// between splitting the shuffle into 128-bit components and stitching those
9100 /// back together vs. extracting the single-input shuffles and blending those
9102 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9103 SDValue V2, ArrayRef<int> Mask,
9104 SelectionDAG &DAG) {
9105 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9106 "lower single-input shuffles as it "
9107 "could then recurse on itself.");
9108 int Size = Mask.size();
9110 // If this can be modeled as a broadcast of two elements followed by a blend,
9111 // prefer that lowering. This is especially important because broadcasts can
9112 // often fold with memory operands.
9113 auto DoBothBroadcast = [&] {
9114 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9117 if (V2BroadcastIdx == -1)
9118 V2BroadcastIdx = M - Size;
9119 else if (M - Size != V2BroadcastIdx)
9121 } else if (M >= 0) {
9122 if (V1BroadcastIdx == -1)
9124 else if (M != V1BroadcastIdx)
9129 if (DoBothBroadcast())
9130 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9133 // If the inputs all stem from a single 128-bit lane of each input, then we
9134 // split them rather than blending because the split will decompose to
9135 // unusually few instructions.
9136 int LaneCount = VT.getSizeInBits() / 128;
9137 int LaneSize = Size / LaneCount;
9138 SmallBitVector LaneInputs[2];
9139 LaneInputs[0].resize(LaneCount, false);
9140 LaneInputs[1].resize(LaneCount, false);
9141 for (int i = 0; i < Size; ++i)
9143 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9144 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9145 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9147 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9148 // that the decomposed single-input shuffles don't end up here.
9149 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9152 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9153 /// a permutation and blend of those lanes.
9155 /// This essentially blends the out-of-lane inputs to each lane into the lane
9156 /// from a permuted copy of the vector. This lowering strategy results in four
9157 /// instructions in the worst case for a single-input cross lane shuffle which
9158 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9159 /// of. Special cases for each particular shuffle pattern should be handled
9160 /// prior to trying this lowering.
9161 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9162 SDValue V1, SDValue V2,
9164 SelectionDAG &DAG) {
9165 // FIXME: This should probably be generalized for 512-bit vectors as well.
9166 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9167 int LaneSize = Mask.size() / 2;
9169 // If there are only inputs from one 128-bit lane, splitting will in fact be
9170 // less expensive. The flags track whether the given lane contains an element
9171 // that crosses to another lane.
9172 bool LaneCrossing[2] = {false, false};
9173 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9174 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9175 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9176 if (!LaneCrossing[0] || !LaneCrossing[1])
9177 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9179 if (isSingleInputShuffleMask(Mask)) {
9180 SmallVector<int, 32> FlippedBlendMask;
9181 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9182 FlippedBlendMask.push_back(
9183 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9185 : Mask[i] % LaneSize +
9186 (i / LaneSize) * LaneSize + Size));
9188 // Flip the vector, and blend the results which should now be in-lane. The
9189 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9190 // 5 for the high source. The value 3 selects the high half of source 2 and
9191 // the value 2 selects the low half of source 2. We only use source 2 to
9192 // allow folding it into a memory operand.
9193 unsigned PERMMask = 3 | 2 << 4;
9194 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9195 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9196 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9199 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9200 // will be handled by the above logic and a blend of the results, much like
9201 // other patterns in AVX.
9202 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9205 /// \brief Handle lowering 2-lane 128-bit shuffles.
9206 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9207 SDValue V2, ArrayRef<int> Mask,
9208 const X86Subtarget *Subtarget,
9209 SelectionDAG &DAG) {
9210 // TODO: If minimizing size and one of the inputs is a zero vector and the
9211 // the zero vector has only one use, we could use a VPERM2X128 to save the
9212 // instruction bytes needed to explicitly generate the zero vector.
9214 // Blends are faster and handle all the non-lane-crossing cases.
9215 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9219 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9220 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9222 // If either input operand is a zero vector, use VPERM2X128 because its mask
9223 // allows us to replace the zero input with an implicit zero.
9224 if (!IsV1Zero && !IsV2Zero) {
9225 // Check for patterns which can be matched with a single insert of a 128-bit
9227 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9228 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9229 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9230 VT.getVectorNumElements() / 2);
9231 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9232 DAG.getIntPtrConstant(0, DL));
9233 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9234 OnlyUsesV1 ? V1 : V2,
9235 DAG.getIntPtrConstant(0, DL));
9236 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9240 // Otherwise form a 128-bit permutation. After accounting for undefs,
9241 // convert the 64-bit shuffle mask selection values into 128-bit
9242 // selection bits by dividing the indexes by 2 and shifting into positions
9243 // defined by a vperm2*128 instruction's immediate control byte.
9245 // The immediate permute control byte looks like this:
9246 // [1:0] - select 128 bits from sources for low half of destination
9248 // [3] - zero low half of destination
9249 // [5:4] - select 128 bits from sources for high half of destination
9251 // [7] - zero high half of destination
9253 int MaskLO = Mask[0];
9254 if (MaskLO == SM_SentinelUndef)
9255 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9257 int MaskHI = Mask[2];
9258 if (MaskHI == SM_SentinelUndef)
9259 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9261 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9263 // If either input is a zero vector, replace it with an undef input.
9264 // Shuffle mask values < 4 are selecting elements of V1.
9265 // Shuffle mask values >= 4 are selecting elements of V2.
9266 // Adjust each half of the permute mask by clearing the half that was
9267 // selecting the zero vector and setting the zero mask bit.
9269 V1 = DAG.getUNDEF(VT);
9271 PermMask = (PermMask & 0xf0) | 0x08;
9273 PermMask = (PermMask & 0x0f) | 0x80;
9276 V2 = DAG.getUNDEF(VT);
9278 PermMask = (PermMask & 0xf0) | 0x08;
9280 PermMask = (PermMask & 0x0f) | 0x80;
9283 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9284 DAG.getConstant(PermMask, DL, MVT::i8));
9287 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9288 /// shuffling each lane.
9290 /// This will only succeed when the result of fixing the 128-bit lanes results
9291 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9292 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9293 /// the lane crosses early and then use simpler shuffles within each lane.
9295 /// FIXME: It might be worthwhile at some point to support this without
9296 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9297 /// in x86 only floating point has interesting non-repeating shuffles, and even
9298 /// those are still *marginally* more expensive.
9299 static SDValue lowerVectorShuffleByMerging128BitLanes(
9300 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9301 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9302 assert(!isSingleInputShuffleMask(Mask) &&
9303 "This is only useful with multiple inputs.");
9305 int Size = Mask.size();
9306 int LaneSize = 128 / VT.getScalarSizeInBits();
9307 int NumLanes = Size / LaneSize;
9308 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9310 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9311 // check whether the in-128-bit lane shuffles share a repeating pattern.
9312 SmallVector<int, 4> Lanes;
9313 Lanes.resize(NumLanes, -1);
9314 SmallVector<int, 4> InLaneMask;
9315 InLaneMask.resize(LaneSize, -1);
9316 for (int i = 0; i < Size; ++i) {
9320 int j = i / LaneSize;
9323 // First entry we've seen for this lane.
9324 Lanes[j] = Mask[i] / LaneSize;
9325 } else if (Lanes[j] != Mask[i] / LaneSize) {
9326 // This doesn't match the lane selected previously!
9330 // Check that within each lane we have a consistent shuffle mask.
9331 int k = i % LaneSize;
9332 if (InLaneMask[k] < 0) {
9333 InLaneMask[k] = Mask[i] % LaneSize;
9334 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9335 // This doesn't fit a repeating in-lane mask.
9340 // First shuffle the lanes into place.
9341 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9342 VT.getSizeInBits() / 64);
9343 SmallVector<int, 8> LaneMask;
9344 LaneMask.resize(NumLanes * 2, -1);
9345 for (int i = 0; i < NumLanes; ++i)
9346 if (Lanes[i] >= 0) {
9347 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9348 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9351 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9352 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9353 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9355 // Cast it back to the type we actually want.
9356 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9358 // Now do a simple shuffle that isn't lane crossing.
9359 SmallVector<int, 8> NewMask;
9360 NewMask.resize(Size, -1);
9361 for (int i = 0; i < Size; ++i)
9363 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9364 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9365 "Must not introduce lane crosses at this point!");
9367 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9370 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9373 /// This returns true if the elements from a particular input are already in the
9374 /// slot required by the given mask and require no permutation.
9375 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9376 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9377 int Size = Mask.size();
9378 for (int i = 0; i < Size; ++i)
9379 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9385 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9387 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9388 /// isn't available.
9389 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9390 const X86Subtarget *Subtarget,
9391 SelectionDAG &DAG) {
9393 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9394 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9395 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9396 ArrayRef<int> Mask = SVOp->getMask();
9397 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9399 SmallVector<int, 4> WidenedMask;
9400 if (canWidenShuffleElements(Mask, WidenedMask))
9401 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9404 if (isSingleInputShuffleMask(Mask)) {
9405 // Check for being able to broadcast a single element.
9406 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9407 Mask, Subtarget, DAG))
9410 // Use low duplicate instructions for masks that match their pattern.
9411 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9412 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9414 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9415 // Non-half-crossing single input shuffles can be lowerid with an
9416 // interleaved permutation.
9417 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9418 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9419 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9420 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9423 // With AVX2 we have direct support for this permutation.
9424 if (Subtarget->hasAVX2())
9425 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9426 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9428 // Otherwise, fall back.
9429 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9433 // X86 has dedicated unpack instructions that can handle specific blend
9434 // operations: UNPCKH and UNPCKL.
9435 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9436 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9437 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9438 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9439 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9440 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9441 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9442 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9444 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9448 // Check if the blend happens to exactly fit that of SHUFPD.
9449 if ((Mask[0] == -1 || Mask[0] < 2) &&
9450 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9451 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9452 (Mask[3] == -1 || Mask[3] >= 6)) {
9453 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9454 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9455 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9456 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9458 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9459 (Mask[1] == -1 || Mask[1] < 2) &&
9460 (Mask[2] == -1 || Mask[2] >= 6) &&
9461 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9462 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9463 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9464 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9465 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9468 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9469 // shuffle. However, if we have AVX2 and either inputs are already in place,
9470 // we will be able to shuffle even across lanes the other input in a single
9471 // instruction so skip this pattern.
9472 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9473 isShuffleMaskInputInPlace(1, Mask))))
9474 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9475 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9478 // If we have AVX2 then we always want to lower with a blend because an v4 we
9479 // can fully permute the elements.
9480 if (Subtarget->hasAVX2())
9481 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9484 // Otherwise fall back on generic lowering.
9485 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9488 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9490 /// This routine is only called when we have AVX2 and thus a reasonable
9491 /// instruction set for v4i64 shuffling..
9492 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9493 const X86Subtarget *Subtarget,
9494 SelectionDAG &DAG) {
9496 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9497 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9498 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9499 ArrayRef<int> Mask = SVOp->getMask();
9500 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9501 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9503 SmallVector<int, 4> WidenedMask;
9504 if (canWidenShuffleElements(Mask, WidenedMask))
9505 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9508 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9512 // Check for being able to broadcast a single element.
9513 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9514 Mask, Subtarget, DAG))
9517 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9518 // use lower latency instructions that will operate on both 128-bit lanes.
9519 SmallVector<int, 2> RepeatedMask;
9520 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9521 if (isSingleInputShuffleMask(Mask)) {
9522 int PSHUFDMask[] = {-1, -1, -1, -1};
9523 for (int i = 0; i < 2; ++i)
9524 if (RepeatedMask[i] >= 0) {
9525 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9526 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9529 ISD::BITCAST, DL, MVT::v4i64,
9530 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9531 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9532 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9536 // AVX2 provides a direct instruction for permuting a single input across
9538 if (isSingleInputShuffleMask(Mask))
9539 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9540 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9542 // Try to use shift instructions.
9544 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9547 // Use dedicated unpack instructions for masks that match their pattern.
9548 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9549 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9550 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9551 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9552 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9553 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9554 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9555 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9557 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9558 // shuffle. However, if we have AVX2 and either inputs are already in place,
9559 // we will be able to shuffle even across lanes the other input in a single
9560 // instruction so skip this pattern.
9561 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9562 isShuffleMaskInputInPlace(1, Mask))))
9563 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9564 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9567 // Otherwise fall back on generic blend lowering.
9568 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9572 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9574 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9575 /// isn't available.
9576 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9577 const X86Subtarget *Subtarget,
9578 SelectionDAG &DAG) {
9580 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9581 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9582 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9583 ArrayRef<int> Mask = SVOp->getMask();
9584 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9586 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9590 // Check for being able to broadcast a single element.
9591 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9592 Mask, Subtarget, DAG))
9595 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9596 // options to efficiently lower the shuffle.
9597 SmallVector<int, 4> RepeatedMask;
9598 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9599 assert(RepeatedMask.size() == 4 &&
9600 "Repeated masks must be half the mask width!");
9602 // Use even/odd duplicate instructions for masks that match their pattern.
9603 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9604 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9605 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9606 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9608 if (isSingleInputShuffleMask(Mask))
9609 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9610 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9612 // Use dedicated unpack instructions for masks that match their pattern.
9613 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9614 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9615 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9616 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9617 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9618 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9619 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9620 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9622 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9623 // have already handled any direct blends. We also need to squash the
9624 // repeated mask into a simulated v4f32 mask.
9625 for (int i = 0; i < 4; ++i)
9626 if (RepeatedMask[i] >= 8)
9627 RepeatedMask[i] -= 4;
9628 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9631 // If we have a single input shuffle with different shuffle patterns in the
9632 // two 128-bit lanes use the variable mask to VPERMILPS.
9633 if (isSingleInputShuffleMask(Mask)) {
9634 SDValue VPermMask[8];
9635 for (int i = 0; i < 8; ++i)
9636 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9637 : DAG.getConstant(Mask[i], DL, MVT::i32);
9638 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9640 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9641 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9643 if (Subtarget->hasAVX2())
9644 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9645 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9646 DAG.getNode(ISD::BUILD_VECTOR, DL,
9647 MVT::v8i32, VPermMask)),
9650 // Otherwise, fall back.
9651 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9655 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9657 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9658 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9661 // If we have AVX2 then we always want to lower with a blend because at v8 we
9662 // can fully permute the elements.
9663 if (Subtarget->hasAVX2())
9664 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9667 // Otherwise fall back on generic lowering.
9668 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9671 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9673 /// This routine is only called when we have AVX2 and thus a reasonable
9674 /// instruction set for v8i32 shuffling..
9675 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9676 const X86Subtarget *Subtarget,
9677 SelectionDAG &DAG) {
9679 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9680 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9681 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9682 ArrayRef<int> Mask = SVOp->getMask();
9683 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9684 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9686 // Whenever we can lower this as a zext, that instruction is strictly faster
9687 // than any alternative. It also allows us to fold memory operands into the
9688 // shuffle in many cases.
9689 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9690 Mask, Subtarget, DAG))
9693 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9697 // Check for being able to broadcast a single element.
9698 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9699 Mask, Subtarget, DAG))
9702 // If the shuffle mask is repeated in each 128-bit lane we can use more
9703 // efficient instructions that mirror the shuffles across the two 128-bit
9705 SmallVector<int, 4> RepeatedMask;
9706 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9707 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9708 if (isSingleInputShuffleMask(Mask))
9709 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9710 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9712 // Use dedicated unpack instructions for masks that match their pattern.
9713 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9714 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9715 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9716 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9717 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9718 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9719 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9720 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9723 // Try to use shift instructions.
9725 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9728 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9729 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9732 // If the shuffle patterns aren't repeated but it is a single input, directly
9733 // generate a cross-lane VPERMD instruction.
9734 if (isSingleInputShuffleMask(Mask)) {
9735 SDValue VPermMask[8];
9736 for (int i = 0; i < 8; ++i)
9737 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9738 : DAG.getConstant(Mask[i], DL, MVT::i32);
9740 X86ISD::VPERMV, DL, MVT::v8i32,
9741 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9744 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9746 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9747 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9750 // Otherwise fall back on generic blend lowering.
9751 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9755 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9757 /// This routine is only called when we have AVX2 and thus a reasonable
9758 /// instruction set for v16i16 shuffling..
9759 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9760 const X86Subtarget *Subtarget,
9761 SelectionDAG &DAG) {
9763 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9764 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9765 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9766 ArrayRef<int> Mask = SVOp->getMask();
9767 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9768 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9770 // Whenever we can lower this as a zext, that instruction is strictly faster
9771 // than any alternative. It also allows us to fold memory operands into the
9772 // shuffle in many cases.
9773 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9774 Mask, Subtarget, DAG))
9777 // Check for being able to broadcast a single element.
9778 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9779 Mask, Subtarget, DAG))
9782 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9786 // Use dedicated unpack instructions for masks that match their pattern.
9787 if (isShuffleEquivalent(V1, V2, Mask,
9788 {// First 128-bit lane:
9789 0, 16, 1, 17, 2, 18, 3, 19,
9790 // Second 128-bit lane:
9791 8, 24, 9, 25, 10, 26, 11, 27}))
9792 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9793 if (isShuffleEquivalent(V1, V2, Mask,
9794 {// First 128-bit lane:
9795 4, 20, 5, 21, 6, 22, 7, 23,
9796 // Second 128-bit lane:
9797 12, 28, 13, 29, 14, 30, 15, 31}))
9798 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9800 // Try to use shift instructions.
9802 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9805 // Try to use byte rotation instructions.
9806 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9807 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9810 if (isSingleInputShuffleMask(Mask)) {
9811 // There are no generalized cross-lane shuffle operations available on i16
9813 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9814 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9817 SmallVector<int, 8> RepeatedMask;
9818 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9819 // As this is a single-input shuffle, the repeated mask should be
9820 // a strictly valid v8i16 mask that we can pass through to the v8i16
9821 // lowering to handle even the v16 case.
9822 return lowerV8I16GeneralSingleInputVectorShuffle(
9823 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9826 SDValue PSHUFBMask[32];
9827 for (int i = 0; i < 16; ++i) {
9828 if (Mask[i] == -1) {
9829 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9833 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9834 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9835 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9836 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9839 ISD::BITCAST, DL, MVT::v16i16,
9841 X86ISD::PSHUFB, DL, MVT::v32i8,
9842 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9843 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9846 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9848 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9849 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9852 // Otherwise fall back on generic lowering.
9853 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9856 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9858 /// This routine is only called when we have AVX2 and thus a reasonable
9859 /// instruction set for v32i8 shuffling..
9860 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9861 const X86Subtarget *Subtarget,
9862 SelectionDAG &DAG) {
9864 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9865 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9866 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9867 ArrayRef<int> Mask = SVOp->getMask();
9868 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9869 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9871 // Whenever we can lower this as a zext, that instruction is strictly faster
9872 // than any alternative. It also allows us to fold memory operands into the
9873 // shuffle in many cases.
9874 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9875 Mask, Subtarget, DAG))
9878 // Check for being able to broadcast a single element.
9879 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9880 Mask, Subtarget, DAG))
9883 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9887 // Use dedicated unpack instructions for masks that match their pattern.
9888 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9890 if (isShuffleEquivalent(
9892 {// First 128-bit lane:
9893 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9894 // Second 128-bit lane:
9895 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9896 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9897 if (isShuffleEquivalent(
9899 {// First 128-bit lane:
9900 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9901 // Second 128-bit lane:
9902 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9903 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9905 // Try to use shift instructions.
9907 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9910 // Try to use byte rotation instructions.
9911 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9912 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9915 if (isSingleInputShuffleMask(Mask)) {
9916 // There are no generalized cross-lane shuffle operations available on i8
9918 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9919 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9922 SDValue PSHUFBMask[32];
9923 for (int i = 0; i < 32; ++i)
9926 ? DAG.getUNDEF(MVT::i8)
9927 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
9931 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9932 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9935 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9937 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9938 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9941 // Otherwise fall back on generic lowering.
9942 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9945 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9947 /// This routine either breaks down the specific type of a 256-bit x86 vector
9948 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9949 /// together based on the available instructions.
9950 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9951 MVT VT, const X86Subtarget *Subtarget,
9952 SelectionDAG &DAG) {
9954 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9955 ArrayRef<int> Mask = SVOp->getMask();
9957 // If we have a single input to the zero element, insert that into V1 if we
9958 // can do so cheaply.
9959 int NumElts = VT.getVectorNumElements();
9960 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
9961 return M >= NumElts;
9964 if (NumV2Elements == 1 && Mask[0] >= NumElts)
9965 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9966 DL, VT, V1, V2, Mask, Subtarget, DAG))
9969 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9970 // check for those subtargets here and avoid much of the subtarget querying in
9971 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9972 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9973 // floating point types there eventually, just immediately cast everything to
9974 // a float and operate entirely in that domain.
9975 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9976 int ElementBits = VT.getScalarSizeInBits();
9977 if (ElementBits < 32)
9978 // No floating point type available, decompose into 128-bit vectors.
9979 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9981 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9982 VT.getVectorNumElements());
9983 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9984 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9985 return DAG.getNode(ISD::BITCAST, DL, VT,
9986 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9989 switch (VT.SimpleTy) {
9991 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9993 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9995 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9997 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9999 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10001 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10004 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10008 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10009 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10010 const X86Subtarget *Subtarget,
10011 SelectionDAG &DAG) {
10013 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10014 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10015 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10016 ArrayRef<int> Mask = SVOp->getMask();
10017 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10019 // X86 has dedicated unpack instructions that can handle specific blend
10020 // operations: UNPCKH and UNPCKL.
10021 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10022 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10023 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10024 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10026 // FIXME: Implement direct support for this type!
10027 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10030 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10031 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10032 const X86Subtarget *Subtarget,
10033 SelectionDAG &DAG) {
10035 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10036 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10038 ArrayRef<int> Mask = SVOp->getMask();
10039 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10041 // Use dedicated unpack instructions for masks that match their pattern.
10042 if (isShuffleEquivalent(V1, V2, Mask,
10043 {// First 128-bit lane.
10044 0, 16, 1, 17, 4, 20, 5, 21,
10045 // Second 128-bit lane.
10046 8, 24, 9, 25, 12, 28, 13, 29}))
10047 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10048 if (isShuffleEquivalent(V1, V2, Mask,
10049 {// First 128-bit lane.
10050 2, 18, 3, 19, 6, 22, 7, 23,
10051 // Second 128-bit lane.
10052 10, 26, 11, 27, 14, 30, 15, 31}))
10053 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10055 // FIXME: Implement direct support for this type!
10056 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10059 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10060 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10061 const X86Subtarget *Subtarget,
10062 SelectionDAG &DAG) {
10064 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10065 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10066 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10067 ArrayRef<int> Mask = SVOp->getMask();
10068 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10070 // X86 has dedicated unpack instructions that can handle specific blend
10071 // operations: UNPCKH and UNPCKL.
10072 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10073 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10074 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10075 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10077 // FIXME: Implement direct support for this type!
10078 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10081 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10082 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10083 const X86Subtarget *Subtarget,
10084 SelectionDAG &DAG) {
10086 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10087 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10088 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10089 ArrayRef<int> Mask = SVOp->getMask();
10090 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10092 // Use dedicated unpack instructions for masks that match their pattern.
10093 if (isShuffleEquivalent(V1, V2, Mask,
10094 {// First 128-bit lane.
10095 0, 16, 1, 17, 4, 20, 5, 21,
10096 // Second 128-bit lane.
10097 8, 24, 9, 25, 12, 28, 13, 29}))
10098 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10099 if (isShuffleEquivalent(V1, V2, Mask,
10100 {// First 128-bit lane.
10101 2, 18, 3, 19, 6, 22, 7, 23,
10102 // Second 128-bit lane.
10103 10, 26, 11, 27, 14, 30, 15, 31}))
10104 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10106 // FIXME: Implement direct support for this type!
10107 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10110 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10111 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10112 const X86Subtarget *Subtarget,
10113 SelectionDAG &DAG) {
10115 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10116 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10117 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10118 ArrayRef<int> Mask = SVOp->getMask();
10119 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10120 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10122 // FIXME: Implement direct support for this type!
10123 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10126 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10127 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10128 const X86Subtarget *Subtarget,
10129 SelectionDAG &DAG) {
10131 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10132 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10133 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10134 ArrayRef<int> Mask = SVOp->getMask();
10135 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10136 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10138 // FIXME: Implement direct support for this type!
10139 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10142 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10144 /// This routine either breaks down the specific type of a 512-bit x86 vector
10145 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10146 /// together based on the available instructions.
10147 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10148 MVT VT, const X86Subtarget *Subtarget,
10149 SelectionDAG &DAG) {
10151 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10152 ArrayRef<int> Mask = SVOp->getMask();
10153 assert(Subtarget->hasAVX512() &&
10154 "Cannot lower 512-bit vectors w/ basic ISA!");
10156 // Check for being able to broadcast a single element.
10157 if (SDValue Broadcast =
10158 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10161 // Dispatch to each element type for lowering. If we don't have supprot for
10162 // specific element type shuffles at 512 bits, immediately split them and
10163 // lower them. Each lowering routine of a given type is allowed to assume that
10164 // the requisite ISA extensions for that element type are available.
10165 switch (VT.SimpleTy) {
10167 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10169 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10171 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10173 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10175 if (Subtarget->hasBWI())
10176 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10179 if (Subtarget->hasBWI())
10180 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10184 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10187 // Otherwise fall back on splitting.
10188 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10191 /// \brief Top-level lowering for x86 vector shuffles.
10193 /// This handles decomposition, canonicalization, and lowering of all x86
10194 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10195 /// above in helper routines. The canonicalization attempts to widen shuffles
10196 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10197 /// s.t. only one of the two inputs needs to be tested, etc.
10198 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10199 SelectionDAG &DAG) {
10200 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10201 ArrayRef<int> Mask = SVOp->getMask();
10202 SDValue V1 = Op.getOperand(0);
10203 SDValue V2 = Op.getOperand(1);
10204 MVT VT = Op.getSimpleValueType();
10205 int NumElements = VT.getVectorNumElements();
10208 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10210 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10211 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10212 if (V1IsUndef && V2IsUndef)
10213 return DAG.getUNDEF(VT);
10215 // When we create a shuffle node we put the UNDEF node to second operand,
10216 // but in some cases the first operand may be transformed to UNDEF.
10217 // In this case we should just commute the node.
10219 return DAG.getCommutedVectorShuffle(*SVOp);
10221 // Check for non-undef masks pointing at an undef vector and make the masks
10222 // undef as well. This makes it easier to match the shuffle based solely on
10226 if (M >= NumElements) {
10227 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10228 for (int &M : NewMask)
10229 if (M >= NumElements)
10231 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10234 // We actually see shuffles that are entirely re-arrangements of a set of
10235 // zero inputs. This mostly happens while decomposing complex shuffles into
10236 // simple ones. Directly lower these as a buildvector of zeros.
10237 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10238 if (Zeroable.all())
10239 return getZeroVector(VT, Subtarget, DAG, dl);
10241 // Try to collapse shuffles into using a vector type with fewer elements but
10242 // wider element types. We cap this to not form integers or floating point
10243 // elements wider than 64 bits, but it might be interesting to form i128
10244 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10245 SmallVector<int, 16> WidenedMask;
10246 if (VT.getScalarSizeInBits() < 64 &&
10247 canWidenShuffleElements(Mask, WidenedMask)) {
10248 MVT NewEltVT = VT.isFloatingPoint()
10249 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10250 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10251 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10252 // Make sure that the new vector type is legal. For example, v2f64 isn't
10254 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10255 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10256 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10257 return DAG.getNode(ISD::BITCAST, dl, VT,
10258 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10262 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10263 for (int M : SVOp->getMask())
10265 ++NumUndefElements;
10266 else if (M < NumElements)
10271 // Commute the shuffle as needed such that more elements come from V1 than
10272 // V2. This allows us to match the shuffle pattern strictly on how many
10273 // elements come from V1 without handling the symmetric cases.
10274 if (NumV2Elements > NumV1Elements)
10275 return DAG.getCommutedVectorShuffle(*SVOp);
10277 // When the number of V1 and V2 elements are the same, try to minimize the
10278 // number of uses of V2 in the low half of the vector. When that is tied,
10279 // ensure that the sum of indices for V1 is equal to or lower than the sum
10280 // indices for V2. When those are equal, try to ensure that the number of odd
10281 // indices for V1 is lower than the number of odd indices for V2.
10282 if (NumV1Elements == NumV2Elements) {
10283 int LowV1Elements = 0, LowV2Elements = 0;
10284 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10285 if (M >= NumElements)
10289 if (LowV2Elements > LowV1Elements) {
10290 return DAG.getCommutedVectorShuffle(*SVOp);
10291 } else if (LowV2Elements == LowV1Elements) {
10292 int SumV1Indices = 0, SumV2Indices = 0;
10293 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10294 if (SVOp->getMask()[i] >= NumElements)
10296 else if (SVOp->getMask()[i] >= 0)
10298 if (SumV2Indices < SumV1Indices) {
10299 return DAG.getCommutedVectorShuffle(*SVOp);
10300 } else if (SumV2Indices == SumV1Indices) {
10301 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10302 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10303 if (SVOp->getMask()[i] >= NumElements)
10304 NumV2OddIndices += i % 2;
10305 else if (SVOp->getMask()[i] >= 0)
10306 NumV1OddIndices += i % 2;
10307 if (NumV2OddIndices < NumV1OddIndices)
10308 return DAG.getCommutedVectorShuffle(*SVOp);
10313 // For each vector width, delegate to a specialized lowering routine.
10314 if (VT.getSizeInBits() == 128)
10315 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10317 if (VT.getSizeInBits() == 256)
10318 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10320 // Force AVX-512 vectors to be scalarized for now.
10321 // FIXME: Implement AVX-512 support!
10322 if (VT.getSizeInBits() == 512)
10323 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10325 llvm_unreachable("Unimplemented!");
10328 // This function assumes its argument is a BUILD_VECTOR of constants or
10329 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10331 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10332 unsigned &MaskValue) {
10334 unsigned NumElems = BuildVector->getNumOperands();
10335 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10336 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10337 unsigned NumElemsInLane = NumElems / NumLanes;
10339 // Blend for v16i16 should be symetric for the both lanes.
10340 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10341 SDValue EltCond = BuildVector->getOperand(i);
10342 SDValue SndLaneEltCond =
10343 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10345 int Lane1Cond = -1, Lane2Cond = -1;
10346 if (isa<ConstantSDNode>(EltCond))
10347 Lane1Cond = !isZero(EltCond);
10348 if (isa<ConstantSDNode>(SndLaneEltCond))
10349 Lane2Cond = !isZero(SndLaneEltCond);
10351 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10352 // Lane1Cond != 0, means we want the first argument.
10353 // Lane1Cond == 0, means we want the second argument.
10354 // The encoding of this argument is 0 for the first argument, 1
10355 // for the second. Therefore, invert the condition.
10356 MaskValue |= !Lane1Cond << i;
10357 else if (Lane1Cond < 0)
10358 MaskValue |= !Lane2Cond << i;
10365 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10366 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10367 const X86Subtarget *Subtarget,
10368 SelectionDAG &DAG) {
10369 SDValue Cond = Op.getOperand(0);
10370 SDValue LHS = Op.getOperand(1);
10371 SDValue RHS = Op.getOperand(2);
10373 MVT VT = Op.getSimpleValueType();
10375 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10377 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10379 // Only non-legal VSELECTs reach this lowering, convert those into generic
10380 // shuffles and re-use the shuffle lowering path for blends.
10381 SmallVector<int, 32> Mask;
10382 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10383 SDValue CondElt = CondBV->getOperand(i);
10385 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10387 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10390 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10391 // A vselect where all conditions and data are constants can be optimized into
10392 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10393 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10394 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10395 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10398 // Try to lower this to a blend-style vector shuffle. This can handle all
10399 // constant condition cases.
10400 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10403 // Variable blends are only legal from SSE4.1 onward.
10404 if (!Subtarget->hasSSE41())
10407 // Only some types will be legal on some subtargets. If we can emit a legal
10408 // VSELECT-matching blend, return Op, and but if we need to expand, return
10410 switch (Op.getSimpleValueType().SimpleTy) {
10412 // Most of the vector types have blends past SSE4.1.
10416 // The byte blends for AVX vectors were introduced only in AVX2.
10417 if (Subtarget->hasAVX2())
10424 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10425 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10428 // FIXME: We should custom lower this by fixing the condition and using i8
10434 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10435 MVT VT = Op.getSimpleValueType();
10438 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10441 if (VT.getSizeInBits() == 8) {
10442 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10443 Op.getOperand(0), Op.getOperand(1));
10444 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10445 DAG.getValueType(VT));
10446 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10449 if (VT.getSizeInBits() == 16) {
10450 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10451 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10453 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10454 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10455 DAG.getNode(ISD::BITCAST, dl,
10458 Op.getOperand(1)));
10459 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10460 Op.getOperand(0), Op.getOperand(1));
10461 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10462 DAG.getValueType(VT));
10463 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10466 if (VT == MVT::f32) {
10467 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10468 // the result back to FR32 register. It's only worth matching if the
10469 // result has a single use which is a store or a bitcast to i32. And in
10470 // the case of a store, it's not worth it if the index is a constant 0,
10471 // because a MOVSSmr can be used instead, which is smaller and faster.
10472 if (!Op.hasOneUse())
10474 SDNode *User = *Op.getNode()->use_begin();
10475 if ((User->getOpcode() != ISD::STORE ||
10476 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10477 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10478 (User->getOpcode() != ISD::BITCAST ||
10479 User->getValueType(0) != MVT::i32))
10481 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10482 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10485 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10488 if (VT == MVT::i32 || VT == MVT::i64) {
10489 // ExtractPS/pextrq works with constant index.
10490 if (isa<ConstantSDNode>(Op.getOperand(1)))
10496 /// Extract one bit from mask vector, like v16i1 or v8i1.
10497 /// AVX-512 feature.
10499 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10500 SDValue Vec = Op.getOperand(0);
10502 MVT VecVT = Vec.getSimpleValueType();
10503 SDValue Idx = Op.getOperand(1);
10504 MVT EltVT = Op.getSimpleValueType();
10506 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10507 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10508 "Unexpected vector type in ExtractBitFromMaskVector");
10510 // variable index can't be handled in mask registers,
10511 // extend vector to VR512
10512 if (!isa<ConstantSDNode>(Idx)) {
10513 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10514 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10515 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10516 ExtVT.getVectorElementType(), Ext, Idx);
10517 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10520 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10521 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10522 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10523 rc = getRegClassFor(MVT::v16i1);
10524 unsigned MaxSift = rc->getSize()*8 - 1;
10525 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10526 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10527 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10528 DAG.getConstant(MaxSift, dl, MVT::i8));
10529 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10530 DAG.getIntPtrConstant(0, dl));
10534 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10535 SelectionDAG &DAG) const {
10537 SDValue Vec = Op.getOperand(0);
10538 MVT VecVT = Vec.getSimpleValueType();
10539 SDValue Idx = Op.getOperand(1);
10541 if (Op.getSimpleValueType() == MVT::i1)
10542 return ExtractBitFromMaskVector(Op, DAG);
10544 if (!isa<ConstantSDNode>(Idx)) {
10545 if (VecVT.is512BitVector() ||
10546 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10547 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10550 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10551 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10552 MaskEltVT.getSizeInBits());
10554 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10555 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10556 getZeroVector(MaskVT, Subtarget, DAG, dl),
10557 Idx, DAG.getConstant(0, dl, getPointerTy()));
10558 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10559 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10560 Perm, DAG.getConstant(0, dl, getPointerTy()));
10565 // If this is a 256-bit vector result, first extract the 128-bit vector and
10566 // then extract the element from the 128-bit vector.
10567 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10569 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10570 // Get the 128-bit vector.
10571 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10572 MVT EltVT = VecVT.getVectorElementType();
10574 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10576 //if (IdxVal >= NumElems/2)
10577 // IdxVal -= NumElems/2;
10578 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10579 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10580 DAG.getConstant(IdxVal, dl, MVT::i32));
10583 assert(VecVT.is128BitVector() && "Unexpected vector length");
10585 if (Subtarget->hasSSE41()) {
10586 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10591 MVT VT = Op.getSimpleValueType();
10592 // TODO: handle v16i8.
10593 if (VT.getSizeInBits() == 16) {
10594 SDValue Vec = Op.getOperand(0);
10595 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10597 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10598 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10599 DAG.getNode(ISD::BITCAST, dl,
10601 Op.getOperand(1)));
10602 // Transform it so it match pextrw which produces a 32-bit result.
10603 MVT EltVT = MVT::i32;
10604 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10605 Op.getOperand(0), Op.getOperand(1));
10606 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10607 DAG.getValueType(VT));
10608 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10611 if (VT.getSizeInBits() == 32) {
10612 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10616 // SHUFPS the element to the lowest double word, then movss.
10617 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10618 MVT VVT = Op.getOperand(0).getSimpleValueType();
10619 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10620 DAG.getUNDEF(VVT), Mask);
10621 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10622 DAG.getIntPtrConstant(0, dl));
10625 if (VT.getSizeInBits() == 64) {
10626 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10627 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10628 // to match extract_elt for f64.
10629 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10633 // UNPCKHPD the element to the lowest double word, then movsd.
10634 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10635 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10636 int Mask[2] = { 1, -1 };
10637 MVT VVT = Op.getOperand(0).getSimpleValueType();
10638 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10639 DAG.getUNDEF(VVT), Mask);
10640 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10641 DAG.getIntPtrConstant(0, dl));
10647 /// Insert one bit to mask vector, like v16i1 or v8i1.
10648 /// AVX-512 feature.
10650 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10652 SDValue Vec = Op.getOperand(0);
10653 SDValue Elt = Op.getOperand(1);
10654 SDValue Idx = Op.getOperand(2);
10655 MVT VecVT = Vec.getSimpleValueType();
10657 if (!isa<ConstantSDNode>(Idx)) {
10658 // Non constant index. Extend source and destination,
10659 // insert element and then truncate the result.
10660 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10661 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10662 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10663 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10664 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10665 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10668 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10669 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10670 if (Vec.getOpcode() == ISD::UNDEF)
10671 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10672 DAG.getConstant(IdxVal, dl, MVT::i8));
10673 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10674 unsigned MaxSift = rc->getSize()*8 - 1;
10675 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10676 DAG.getConstant(MaxSift, dl, MVT::i8));
10677 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10678 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10679 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10682 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10683 SelectionDAG &DAG) const {
10684 MVT VT = Op.getSimpleValueType();
10685 MVT EltVT = VT.getVectorElementType();
10687 if (EltVT == MVT::i1)
10688 return InsertBitToMaskVector(Op, DAG);
10691 SDValue N0 = Op.getOperand(0);
10692 SDValue N1 = Op.getOperand(1);
10693 SDValue N2 = Op.getOperand(2);
10694 if (!isa<ConstantSDNode>(N2))
10696 auto *N2C = cast<ConstantSDNode>(N2);
10697 unsigned IdxVal = N2C->getZExtValue();
10699 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10700 // into that, and then insert the subvector back into the result.
10701 if (VT.is256BitVector() || VT.is512BitVector()) {
10702 // With a 256-bit vector, we can insert into the zero element efficiently
10703 // using a blend if we have AVX or AVX2 and the right data type.
10704 if (VT.is256BitVector() && IdxVal == 0) {
10705 // TODO: It is worthwhile to cast integer to floating point and back
10706 // and incur a domain crossing penalty if that's what we'll end up
10707 // doing anyway after extracting to a 128-bit vector.
10708 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10709 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10710 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10711 N2 = DAG.getIntPtrConstant(1, dl);
10712 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10716 // Get the desired 128-bit vector chunk.
10717 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10719 // Insert the element into the desired chunk.
10720 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10721 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10723 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10724 DAG.getConstant(IdxIn128, dl, MVT::i32));
10726 // Insert the changed part back into the bigger vector
10727 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10729 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10731 if (Subtarget->hasSSE41()) {
10732 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10734 if (VT == MVT::v8i16) {
10735 Opc = X86ISD::PINSRW;
10737 assert(VT == MVT::v16i8);
10738 Opc = X86ISD::PINSRB;
10741 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10743 if (N1.getValueType() != MVT::i32)
10744 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10745 if (N2.getValueType() != MVT::i32)
10746 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10747 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10750 if (EltVT == MVT::f32) {
10751 // Bits [7:6] of the constant are the source select. This will always be
10752 // zero here. The DAG Combiner may combine an extract_elt index into
10753 // these bits. For example (insert (extract, 3), 2) could be matched by
10754 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10755 // Bits [5:4] of the constant are the destination select. This is the
10756 // value of the incoming immediate.
10757 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10758 // combine either bitwise AND or insert of float 0.0 to set these bits.
10760 const Function *F = DAG.getMachineFunction().getFunction();
10761 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10762 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10763 // If this is an insertion of 32-bits into the low 32-bits of
10764 // a vector, we prefer to generate a blend with immediate rather
10765 // than an insertps. Blends are simpler operations in hardware and so
10766 // will always have equal or better performance than insertps.
10767 // But if optimizing for size and there's a load folding opportunity,
10768 // generate insertps because blendps does not have a 32-bit memory
10770 N2 = DAG.getIntPtrConstant(1, dl);
10771 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10772 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10774 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10775 // Create this as a scalar to vector..
10776 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10777 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10780 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10781 // PINSR* works with constant index.
10786 if (EltVT == MVT::i8)
10789 if (EltVT.getSizeInBits() == 16) {
10790 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10791 // as its second argument.
10792 if (N1.getValueType() != MVT::i32)
10793 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10794 if (N2.getValueType() != MVT::i32)
10795 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10796 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10801 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10803 MVT OpVT = Op.getSimpleValueType();
10805 // If this is a 256-bit vector result, first insert into a 128-bit
10806 // vector and then insert into the 256-bit vector.
10807 if (!OpVT.is128BitVector()) {
10808 // Insert into a 128-bit vector.
10809 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10810 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10811 OpVT.getVectorNumElements() / SizeFactor);
10813 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10815 // Insert the 128-bit vector.
10816 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10819 if (OpVT == MVT::v1i64 &&
10820 Op.getOperand(0).getValueType() == MVT::i64)
10821 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10823 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10824 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10825 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10826 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10829 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10830 // a simple subregister reference or explicit instructions to grab
10831 // upper bits of a vector.
10832 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10833 SelectionDAG &DAG) {
10835 SDValue In = Op.getOperand(0);
10836 SDValue Idx = Op.getOperand(1);
10837 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10838 MVT ResVT = Op.getSimpleValueType();
10839 MVT InVT = In.getSimpleValueType();
10841 if (Subtarget->hasFp256()) {
10842 if (ResVT.is128BitVector() &&
10843 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10844 isa<ConstantSDNode>(Idx)) {
10845 return Extract128BitVector(In, IdxVal, DAG, dl);
10847 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10848 isa<ConstantSDNode>(Idx)) {
10849 return Extract256BitVector(In, IdxVal, DAG, dl);
10855 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10856 // simple superregister reference or explicit instructions to insert
10857 // the upper bits of a vector.
10858 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10859 SelectionDAG &DAG) {
10860 if (!Subtarget->hasAVX())
10864 SDValue Vec = Op.getOperand(0);
10865 SDValue SubVec = Op.getOperand(1);
10866 SDValue Idx = Op.getOperand(2);
10868 if (!isa<ConstantSDNode>(Idx))
10871 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10872 MVT OpVT = Op.getSimpleValueType();
10873 MVT SubVecVT = SubVec.getSimpleValueType();
10875 // Fold two 16-byte subvector loads into one 32-byte load:
10876 // (insert_subvector (insert_subvector undef, (load addr), 0),
10877 // (load addr + 16), Elts/2)
10879 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10880 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10881 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10882 !Subtarget->isUnalignedMem32Slow()) {
10883 SDValue SubVec2 = Vec.getOperand(1);
10884 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10885 if (Idx2->getZExtValue() == 0) {
10886 SDValue Ops[] = { SubVec2, SubVec };
10887 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10894 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10895 SubVecVT.is128BitVector())
10896 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10898 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10899 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10901 if (OpVT.getVectorElementType() == MVT::i1) {
10902 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10904 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10905 SDValue Undef = DAG.getUNDEF(OpVT);
10906 unsigned NumElems = OpVT.getVectorNumElements();
10907 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10909 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10910 // Zero upper bits of the Vec
10911 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10912 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10914 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10916 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10917 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10920 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10922 // Zero upper bits of the Vec2
10923 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10924 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10925 // Zero lower bits of the Vec
10926 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10927 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10928 // Merge them together
10929 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10935 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10936 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10937 // one of the above mentioned nodes. It has to be wrapped because otherwise
10938 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10939 // be used to form addressing mode. These wrapped nodes will be selected
10942 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10943 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10945 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10946 // global base reg.
10947 unsigned char OpFlag = 0;
10948 unsigned WrapperKind = X86ISD::Wrapper;
10949 CodeModel::Model M = DAG.getTarget().getCodeModel();
10951 if (Subtarget->isPICStyleRIPRel() &&
10952 (M == CodeModel::Small || M == CodeModel::Kernel))
10953 WrapperKind = X86ISD::WrapperRIP;
10954 else if (Subtarget->isPICStyleGOT())
10955 OpFlag = X86II::MO_GOTOFF;
10956 else if (Subtarget->isPICStyleStubPIC())
10957 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10959 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10960 CP->getAlignment(),
10961 CP->getOffset(), OpFlag);
10963 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10964 // With PIC, the address is actually $g + Offset.
10966 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10967 DAG.getNode(X86ISD::GlobalBaseReg,
10968 SDLoc(), getPointerTy()),
10975 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10976 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10978 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10979 // global base reg.
10980 unsigned char OpFlag = 0;
10981 unsigned WrapperKind = X86ISD::Wrapper;
10982 CodeModel::Model M = DAG.getTarget().getCodeModel();
10984 if (Subtarget->isPICStyleRIPRel() &&
10985 (M == CodeModel::Small || M == CodeModel::Kernel))
10986 WrapperKind = X86ISD::WrapperRIP;
10987 else if (Subtarget->isPICStyleGOT())
10988 OpFlag = X86II::MO_GOTOFF;
10989 else if (Subtarget->isPICStyleStubPIC())
10990 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10992 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10995 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10997 // With PIC, the address is actually $g + Offset.
10999 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11000 DAG.getNode(X86ISD::GlobalBaseReg,
11001 SDLoc(), getPointerTy()),
11008 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11009 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11011 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11012 // global base reg.
11013 unsigned char OpFlag = 0;
11014 unsigned WrapperKind = X86ISD::Wrapper;
11015 CodeModel::Model M = DAG.getTarget().getCodeModel();
11017 if (Subtarget->isPICStyleRIPRel() &&
11018 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11019 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11020 OpFlag = X86II::MO_GOTPCREL;
11021 WrapperKind = X86ISD::WrapperRIP;
11022 } else if (Subtarget->isPICStyleGOT()) {
11023 OpFlag = X86II::MO_GOT;
11024 } else if (Subtarget->isPICStyleStubPIC()) {
11025 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11026 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11027 OpFlag = X86II::MO_DARWIN_NONLAZY;
11030 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11033 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11035 // With PIC, the address is actually $g + Offset.
11036 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11037 !Subtarget->is64Bit()) {
11038 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11039 DAG.getNode(X86ISD::GlobalBaseReg,
11040 SDLoc(), getPointerTy()),
11044 // For symbols that require a load from a stub to get the address, emit the
11046 if (isGlobalStubReference(OpFlag))
11047 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11048 MachinePointerInfo::getGOT(), false, false, false, 0);
11054 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11055 // Create the TargetBlockAddressAddress node.
11056 unsigned char OpFlags =
11057 Subtarget->ClassifyBlockAddressReference();
11058 CodeModel::Model M = DAG.getTarget().getCodeModel();
11059 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11060 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11062 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11065 if (Subtarget->isPICStyleRIPRel() &&
11066 (M == CodeModel::Small || M == CodeModel::Kernel))
11067 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11069 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11071 // With PIC, the address is actually $g + Offset.
11072 if (isGlobalRelativeToPICBase(OpFlags)) {
11073 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11074 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11082 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11083 int64_t Offset, SelectionDAG &DAG) const {
11084 // Create the TargetGlobalAddress node, folding in the constant
11085 // offset if it is legal.
11086 unsigned char OpFlags =
11087 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11088 CodeModel::Model M = DAG.getTarget().getCodeModel();
11090 if (OpFlags == X86II::MO_NO_FLAG &&
11091 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11092 // A direct static reference to a global.
11093 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11096 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11099 if (Subtarget->isPICStyleRIPRel() &&
11100 (M == CodeModel::Small || M == CodeModel::Kernel))
11101 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11103 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11105 // With PIC, the address is actually $g + Offset.
11106 if (isGlobalRelativeToPICBase(OpFlags)) {
11107 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11108 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11112 // For globals that require a load from a stub to get the address, emit the
11114 if (isGlobalStubReference(OpFlags))
11115 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11116 MachinePointerInfo::getGOT(), false, false, false, 0);
11118 // If there was a non-zero offset that we didn't fold, create an explicit
11119 // addition for it.
11121 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11122 DAG.getConstant(Offset, dl, getPointerTy()));
11128 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11129 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11130 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11131 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11135 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11136 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11137 unsigned char OperandFlags, bool LocalDynamic = false) {
11138 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11139 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11141 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11142 GA->getValueType(0),
11146 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11150 SDValue Ops[] = { Chain, TGA, *InFlag };
11151 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11153 SDValue Ops[] = { Chain, TGA };
11154 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11157 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11158 MFI->setAdjustsStack(true);
11159 MFI->setHasCalls(true);
11161 SDValue Flag = Chain.getValue(1);
11162 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11165 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11167 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11170 SDLoc dl(GA); // ? function entry point might be better
11171 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11172 DAG.getNode(X86ISD::GlobalBaseReg,
11173 SDLoc(), PtrVT), InFlag);
11174 InFlag = Chain.getValue(1);
11176 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11179 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11181 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11183 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11184 X86::RAX, X86II::MO_TLSGD);
11187 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11193 // Get the start address of the TLS block for this module.
11194 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11195 .getInfo<X86MachineFunctionInfo>();
11196 MFI->incNumLocalDynamicTLSAccesses();
11200 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11201 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11204 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11205 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11206 InFlag = Chain.getValue(1);
11207 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11208 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11211 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11215 unsigned char OperandFlags = X86II::MO_DTPOFF;
11216 unsigned WrapperKind = X86ISD::Wrapper;
11217 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11218 GA->getValueType(0),
11219 GA->getOffset(), OperandFlags);
11220 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11222 // Add x@dtpoff with the base.
11223 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11226 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11227 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11228 const EVT PtrVT, TLSModel::Model model,
11229 bool is64Bit, bool isPIC) {
11232 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11233 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11234 is64Bit ? 257 : 256));
11236 SDValue ThreadPointer =
11237 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11238 MachinePointerInfo(Ptr), false, false, false, 0);
11240 unsigned char OperandFlags = 0;
11241 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11243 unsigned WrapperKind = X86ISD::Wrapper;
11244 if (model == TLSModel::LocalExec) {
11245 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11246 } else if (model == TLSModel::InitialExec) {
11248 OperandFlags = X86II::MO_GOTTPOFF;
11249 WrapperKind = X86ISD::WrapperRIP;
11251 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11254 llvm_unreachable("Unexpected model");
11257 // emit "addl x@ntpoff,%eax" (local exec)
11258 // or "addl x@indntpoff,%eax" (initial exec)
11259 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11261 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11262 GA->getOffset(), OperandFlags);
11263 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11265 if (model == TLSModel::InitialExec) {
11266 if (isPIC && !is64Bit) {
11267 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11268 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11272 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11273 MachinePointerInfo::getGOT(), false, false, false, 0);
11276 // The address of the thread local variable is the add of the thread
11277 // pointer with the offset of the variable.
11278 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11282 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11284 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11285 const GlobalValue *GV = GA->getGlobal();
11287 if (Subtarget->isTargetELF()) {
11288 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11291 case TLSModel::GeneralDynamic:
11292 if (Subtarget->is64Bit())
11293 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11294 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11295 case TLSModel::LocalDynamic:
11296 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11297 Subtarget->is64Bit());
11298 case TLSModel::InitialExec:
11299 case TLSModel::LocalExec:
11300 return LowerToTLSExecModel(
11301 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11302 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11304 llvm_unreachable("Unknown TLS model.");
11307 if (Subtarget->isTargetDarwin()) {
11308 // Darwin only has one model of TLS. Lower to that.
11309 unsigned char OpFlag = 0;
11310 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11311 X86ISD::WrapperRIP : X86ISD::Wrapper;
11313 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11314 // global base reg.
11315 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11316 !Subtarget->is64Bit();
11318 OpFlag = X86II::MO_TLVP_PIC_BASE;
11320 OpFlag = X86II::MO_TLVP;
11322 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11323 GA->getValueType(0),
11324 GA->getOffset(), OpFlag);
11325 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11327 // With PIC32, the address is actually $g + Offset.
11329 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11330 DAG.getNode(X86ISD::GlobalBaseReg,
11331 SDLoc(), getPointerTy()),
11334 // Lowering the machine isd will make sure everything is in the right
11336 SDValue Chain = DAG.getEntryNode();
11337 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11338 SDValue Args[] = { Chain, Offset };
11339 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11341 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11342 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11343 MFI->setAdjustsStack(true);
11345 // And our return value (tls address) is in the standard call return value
11347 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11348 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11349 Chain.getValue(1));
11352 if (Subtarget->isTargetKnownWindowsMSVC() ||
11353 Subtarget->isTargetWindowsGNU()) {
11354 // Just use the implicit TLS architecture
11355 // Need to generate someting similar to:
11356 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11358 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11359 // mov rcx, qword [rdx+rcx*8]
11360 // mov eax, .tls$:tlsvar
11361 // [rax+rcx] contains the address
11362 // Windows 64bit: gs:0x58
11363 // Windows 32bit: fs:__tls_array
11366 SDValue Chain = DAG.getEntryNode();
11368 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11369 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11370 // use its literal value of 0x2C.
11371 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11372 ? Type::getInt8PtrTy(*DAG.getContext(),
11374 : Type::getInt32PtrTy(*DAG.getContext(),
11378 Subtarget->is64Bit()
11379 ? DAG.getIntPtrConstant(0x58, dl)
11380 : (Subtarget->isTargetWindowsGNU()
11381 ? DAG.getIntPtrConstant(0x2C, dl)
11382 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11384 SDValue ThreadPointer =
11385 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11386 MachinePointerInfo(Ptr), false, false, false, 0);
11388 // Load the _tls_index variable
11389 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11390 if (Subtarget->is64Bit())
11391 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11392 IDX, MachinePointerInfo(), MVT::i32,
11393 false, false, false, 0);
11395 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11396 false, false, false, 0);
11398 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11400 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11402 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11403 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11404 false, false, false, 0);
11406 // Get the offset of start of .tls section
11407 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11408 GA->getValueType(0),
11409 GA->getOffset(), X86II::MO_SECREL);
11410 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11412 // The address of the thread local variable is the add of the thread
11413 // pointer with the offset of the variable.
11414 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11417 llvm_unreachable("TLS not implemented for this target.");
11420 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11421 /// and take a 2 x i32 value to shift plus a shift amount.
11422 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11423 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11424 MVT VT = Op.getSimpleValueType();
11425 unsigned VTBits = VT.getSizeInBits();
11427 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11428 SDValue ShOpLo = Op.getOperand(0);
11429 SDValue ShOpHi = Op.getOperand(1);
11430 SDValue ShAmt = Op.getOperand(2);
11431 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11432 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11434 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11435 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11436 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11437 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11438 : DAG.getConstant(0, dl, VT);
11440 SDValue Tmp2, Tmp3;
11441 if (Op.getOpcode() == ISD::SHL_PARTS) {
11442 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11443 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11445 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11446 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11449 // If the shift amount is larger or equal than the width of a part we can't
11450 // rely on the results of shld/shrd. Insert a test and select the appropriate
11451 // values for large shift amounts.
11452 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11453 DAG.getConstant(VTBits, dl, MVT::i8));
11454 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11455 AndNode, DAG.getConstant(0, dl, MVT::i8));
11458 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11459 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11460 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11462 if (Op.getOpcode() == ISD::SHL_PARTS) {
11463 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11464 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11466 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11467 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11470 SDValue Ops[2] = { Lo, Hi };
11471 return DAG.getMergeValues(Ops, dl);
11474 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11475 SelectionDAG &DAG) const {
11476 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11479 if (SrcVT.isVector()) {
11480 if (SrcVT.getVectorElementType() == MVT::i1) {
11481 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11482 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11483 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11484 Op.getOperand(0)));
11489 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11490 "Unknown SINT_TO_FP to lower!");
11492 // These are really Legal; return the operand so the caller accepts it as
11494 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11496 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11497 Subtarget->is64Bit()) {
11501 unsigned Size = SrcVT.getSizeInBits()/8;
11502 MachineFunction &MF = DAG.getMachineFunction();
11503 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11504 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11505 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11507 MachinePointerInfo::getFixedStack(SSFI),
11509 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11512 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11514 SelectionDAG &DAG) const {
11518 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11520 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11522 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11524 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11526 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11527 MachineMemOperand *MMO;
11529 int SSFI = FI->getIndex();
11531 DAG.getMachineFunction()
11532 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11533 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11535 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11536 StackSlot = StackSlot.getOperand(1);
11538 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11539 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11541 Tys, Ops, SrcVT, MMO);
11544 Chain = Result.getValue(1);
11545 SDValue InFlag = Result.getValue(2);
11547 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11548 // shouldn't be necessary except that RFP cannot be live across
11549 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11550 MachineFunction &MF = DAG.getMachineFunction();
11551 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11552 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11553 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11554 Tys = DAG.getVTList(MVT::Other);
11556 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11558 MachineMemOperand *MMO =
11559 DAG.getMachineFunction()
11560 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11561 MachineMemOperand::MOStore, SSFISize, SSFISize);
11563 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11564 Ops, Op.getValueType(), MMO);
11565 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11566 MachinePointerInfo::getFixedStack(SSFI),
11567 false, false, false, 0);
11573 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11574 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11575 SelectionDAG &DAG) const {
11576 // This algorithm is not obvious. Here it is what we're trying to output:
11579 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11580 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11582 haddpd %xmm0, %xmm0
11584 pshufd $0x4e, %xmm0, %xmm1
11590 LLVMContext *Context = DAG.getContext();
11592 // Build some magic constants.
11593 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11594 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11595 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11597 SmallVector<Constant*,2> CV1;
11599 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11600 APInt(64, 0x4330000000000000ULL))));
11602 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11603 APInt(64, 0x4530000000000000ULL))));
11604 Constant *C1 = ConstantVector::get(CV1);
11605 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11607 // Load the 64-bit value into an XMM register.
11608 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11610 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11611 MachinePointerInfo::getConstantPool(),
11612 false, false, false, 16);
11613 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11614 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11617 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11618 MachinePointerInfo::getConstantPool(),
11619 false, false, false, 16);
11620 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11621 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11624 if (Subtarget->hasSSE3()) {
11625 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11626 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11628 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11629 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11631 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11632 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11636 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11637 DAG.getIntPtrConstant(0, dl));
11640 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11641 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11642 SelectionDAG &DAG) const {
11644 // FP constant to bias correct the final result.
11645 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11648 // Load the 32-bit value into an XMM register.
11649 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11652 // Zero out the upper parts of the register.
11653 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11655 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11656 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11657 DAG.getIntPtrConstant(0, dl));
11659 // Or the load with the bias.
11660 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11661 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11662 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11663 MVT::v2f64, Load)),
11664 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11665 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11666 MVT::v2f64, Bias)));
11667 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11668 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11669 DAG.getIntPtrConstant(0, dl));
11671 // Subtract the bias.
11672 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11674 // Handle final rounding.
11675 EVT DestVT = Op.getValueType();
11677 if (DestVT.bitsLT(MVT::f64))
11678 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11679 DAG.getIntPtrConstant(0, dl));
11680 if (DestVT.bitsGT(MVT::f64))
11681 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11683 // Handle final rounding.
11687 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11688 const X86Subtarget &Subtarget) {
11689 // The algorithm is the following:
11690 // #ifdef __SSE4_1__
11691 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11692 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11693 // (uint4) 0x53000000, 0xaa);
11695 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11696 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11698 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11699 // return (float4) lo + fhi;
11702 SDValue V = Op->getOperand(0);
11703 EVT VecIntVT = V.getValueType();
11704 bool Is128 = VecIntVT == MVT::v4i32;
11705 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11706 // If we convert to something else than the supported type, e.g., to v4f64,
11708 if (VecFloatVT != Op->getValueType(0))
11711 unsigned NumElts = VecIntVT.getVectorNumElements();
11712 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11713 "Unsupported custom type");
11714 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11716 // In the #idef/#else code, we have in common:
11717 // - The vector of constants:
11723 // Create the splat vector for 0x4b000000.
11724 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11725 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11726 CstLow, CstLow, CstLow, CstLow};
11727 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11728 makeArrayRef(&CstLowArray[0], NumElts));
11729 // Create the splat vector for 0x53000000.
11730 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11731 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11732 CstHigh, CstHigh, CstHigh, CstHigh};
11733 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11734 makeArrayRef(&CstHighArray[0], NumElts));
11736 // Create the right shift.
11737 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11738 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11739 CstShift, CstShift, CstShift, CstShift};
11740 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11741 makeArrayRef(&CstShiftArray[0], NumElts));
11742 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11745 if (Subtarget.hasSSE41()) {
11746 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11747 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11748 SDValue VecCstLowBitcast =
11749 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11750 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11751 // Low will be bitcasted right away, so do not bother bitcasting back to its
11753 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11754 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11755 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11756 // (uint4) 0x53000000, 0xaa);
11757 SDValue VecCstHighBitcast =
11758 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11759 SDValue VecShiftBitcast =
11760 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11761 // High will be bitcasted right away, so do not bother bitcasting back to
11762 // its original type.
11763 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11764 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11766 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11767 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11768 CstMask, CstMask, CstMask);
11769 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11770 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11771 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11773 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11774 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11777 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11778 SDValue CstFAdd = DAG.getConstantFP(
11779 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11780 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11781 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11782 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11783 makeArrayRef(&CstFAddArray[0], NumElts));
11785 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11786 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11788 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11789 // return (float4) lo + fhi;
11790 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11791 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11794 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11795 SelectionDAG &DAG) const {
11796 SDValue N0 = Op.getOperand(0);
11797 MVT SVT = N0.getSimpleValueType();
11800 switch (SVT.SimpleTy) {
11802 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11807 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11808 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11809 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11813 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11816 if (Subtarget->hasAVX512())
11817 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11818 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11820 llvm_unreachable(nullptr);
11823 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11824 SelectionDAG &DAG) const {
11825 SDValue N0 = Op.getOperand(0);
11828 if (Op.getValueType().isVector())
11829 return lowerUINT_TO_FP_vec(Op, DAG);
11831 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11832 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11833 // the optimization here.
11834 if (DAG.SignBitIsZero(N0))
11835 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11837 MVT SrcVT = N0.getSimpleValueType();
11838 MVT DstVT = Op.getSimpleValueType();
11839 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11840 return LowerUINT_TO_FP_i64(Op, DAG);
11841 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11842 return LowerUINT_TO_FP_i32(Op, DAG);
11843 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11846 // Make a 64-bit buffer, and use it to build an FILD.
11847 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11848 if (SrcVT == MVT::i32) {
11849 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11850 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11851 getPointerTy(), StackSlot, WordOff);
11852 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11853 StackSlot, MachinePointerInfo(),
11855 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11856 OffsetSlot, MachinePointerInfo(),
11858 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11862 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11863 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11864 StackSlot, MachinePointerInfo(),
11866 // For i64 source, we need to add the appropriate power of 2 if the input
11867 // was negative. This is the same as the optimization in
11868 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11869 // we must be careful to do the computation in x87 extended precision, not
11870 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11871 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11872 MachineMemOperand *MMO =
11873 DAG.getMachineFunction()
11874 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11875 MachineMemOperand::MOLoad, 8, 8);
11877 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11878 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11879 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11882 APInt FF(32, 0x5F800000ULL);
11884 // Check whether the sign bit is set.
11885 SDValue SignSet = DAG.getSetCC(dl,
11886 getSetCCResultType(*DAG.getContext(), MVT::i64),
11888 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11890 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11891 SDValue FudgePtr = DAG.getConstantPool(
11892 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11895 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11896 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11897 SDValue Four = DAG.getIntPtrConstant(4, dl);
11898 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11900 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11902 // Load the value out, extending it from f32 to f80.
11903 // FIXME: Avoid the extend by constructing the right constant pool?
11904 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11905 FudgePtr, MachinePointerInfo::getConstantPool(),
11906 MVT::f32, false, false, false, 4);
11907 // Extend everything to 80 bits to force it to be done on x87.
11908 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11909 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11910 DAG.getIntPtrConstant(0, dl));
11913 std::pair<SDValue,SDValue>
11914 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11915 bool IsSigned, bool IsReplace) const {
11918 EVT DstTy = Op.getValueType();
11920 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11921 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11925 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11926 DstTy.getSimpleVT() >= MVT::i16 &&
11927 "Unknown FP_TO_INT to lower!");
11929 // These are really Legal.
11930 if (DstTy == MVT::i32 &&
11931 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11932 return std::make_pair(SDValue(), SDValue());
11933 if (Subtarget->is64Bit() &&
11934 DstTy == MVT::i64 &&
11935 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11936 return std::make_pair(SDValue(), SDValue());
11938 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11939 // stack slot, or into the FTOL runtime function.
11940 MachineFunction &MF = DAG.getMachineFunction();
11941 unsigned MemSize = DstTy.getSizeInBits()/8;
11942 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11943 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11946 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11947 Opc = X86ISD::WIN_FTOL;
11949 switch (DstTy.getSimpleVT().SimpleTy) {
11950 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11951 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11952 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11953 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11956 SDValue Chain = DAG.getEntryNode();
11957 SDValue Value = Op.getOperand(0);
11958 EVT TheVT = Op.getOperand(0).getValueType();
11959 // FIXME This causes a redundant load/store if the SSE-class value is already
11960 // in memory, such as if it is on the callstack.
11961 if (isScalarFPTypeInSSEReg(TheVT)) {
11962 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11963 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11964 MachinePointerInfo::getFixedStack(SSFI),
11966 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11968 Chain, StackSlot, DAG.getValueType(TheVT)
11971 MachineMemOperand *MMO =
11972 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11973 MachineMemOperand::MOLoad, MemSize, MemSize);
11974 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11975 Chain = Value.getValue(1);
11976 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11977 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11980 MachineMemOperand *MMO =
11981 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11982 MachineMemOperand::MOStore, MemSize, MemSize);
11984 if (Opc != X86ISD::WIN_FTOL) {
11985 // Build the FP_TO_INT*_IN_MEM
11986 SDValue Ops[] = { Chain, Value, StackSlot };
11987 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11989 return std::make_pair(FIST, StackSlot);
11991 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11992 DAG.getVTList(MVT::Other, MVT::Glue),
11994 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11995 MVT::i32, ftol.getValue(1));
11996 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11997 MVT::i32, eax.getValue(2));
11998 SDValue Ops[] = { eax, edx };
11999 SDValue pair = IsReplace
12000 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12001 : DAG.getMergeValues(Ops, DL);
12002 return std::make_pair(pair, SDValue());
12006 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12007 const X86Subtarget *Subtarget) {
12008 MVT VT = Op->getSimpleValueType(0);
12009 SDValue In = Op->getOperand(0);
12010 MVT InVT = In.getSimpleValueType();
12013 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12014 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12016 // Optimize vectors in AVX mode:
12019 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12020 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12021 // Concat upper and lower parts.
12024 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12025 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12026 // Concat upper and lower parts.
12029 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12030 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12031 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12034 if (Subtarget->hasInt256())
12035 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12037 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12038 SDValue Undef = DAG.getUNDEF(InVT);
12039 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12040 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12041 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12043 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12044 VT.getVectorNumElements()/2);
12046 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12047 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12049 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12052 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12053 SelectionDAG &DAG) {
12054 MVT VT = Op->getSimpleValueType(0);
12055 SDValue In = Op->getOperand(0);
12056 MVT InVT = In.getSimpleValueType();
12058 unsigned int NumElts = VT.getVectorNumElements();
12059 if (NumElts != 8 && NumElts != 16)
12062 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12063 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12065 assert(InVT.getVectorElementType() == MVT::i1);
12066 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12068 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12070 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12072 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12073 if (VT.is512BitVector())
12075 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12078 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12079 SelectionDAG &DAG) {
12080 if (Subtarget->hasFp256()) {
12081 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12089 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12090 SelectionDAG &DAG) {
12092 MVT VT = Op.getSimpleValueType();
12093 SDValue In = Op.getOperand(0);
12094 MVT SVT = In.getSimpleValueType();
12096 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12097 return LowerZERO_EXTEND_AVX512(Op, DAG);
12099 if (Subtarget->hasFp256()) {
12100 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12105 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12106 VT.getVectorNumElements() != SVT.getVectorNumElements());
12110 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12112 MVT VT = Op.getSimpleValueType();
12113 SDValue In = Op.getOperand(0);
12114 MVT InVT = In.getSimpleValueType();
12116 if (VT == MVT::i1) {
12117 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12118 "Invalid scalar TRUNCATE operation");
12119 if (InVT.getSizeInBits() >= 32)
12121 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12122 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12124 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12125 "Invalid TRUNCATE operation");
12127 // move vector to mask - truncate solution for SKX
12128 if (VT.getVectorElementType() == MVT::i1) {
12129 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12130 Subtarget->hasBWI())
12131 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12132 if ((InVT.is256BitVector() || InVT.is128BitVector())
12133 && InVT.getScalarSizeInBits() <= 16 &&
12134 Subtarget->hasBWI() && Subtarget->hasVLX())
12135 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12136 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12137 Subtarget->hasDQI())
12138 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12139 if ((InVT.is256BitVector() || InVT.is128BitVector())
12140 && InVT.getScalarSizeInBits() >= 32 &&
12141 Subtarget->hasDQI() && Subtarget->hasVLX())
12142 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12144 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12145 if (VT.getVectorElementType().getSizeInBits() >=8)
12146 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12148 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12149 unsigned NumElts = InVT.getVectorNumElements();
12150 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12151 if (InVT.getSizeInBits() < 512) {
12152 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12153 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12158 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12159 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12160 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12163 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12164 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12165 if (Subtarget->hasInt256()) {
12166 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12167 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12168 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12170 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12171 DAG.getIntPtrConstant(0, DL));
12174 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12175 DAG.getIntPtrConstant(0, DL));
12176 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12177 DAG.getIntPtrConstant(2, DL));
12178 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12179 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12180 static const int ShufMask[] = {0, 2, 4, 6};
12181 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12184 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12185 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12186 if (Subtarget->hasInt256()) {
12187 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12189 SmallVector<SDValue,32> pshufbMask;
12190 for (unsigned i = 0; i < 2; ++i) {
12191 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12192 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12193 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12194 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12195 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12196 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12197 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12198 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12199 for (unsigned j = 0; j < 8; ++j)
12200 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12202 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12203 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12204 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12206 static const int ShufMask[] = {0, 2, -1, -1};
12207 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12209 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12210 DAG.getIntPtrConstant(0, DL));
12211 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12214 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12215 DAG.getIntPtrConstant(0, DL));
12217 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12218 DAG.getIntPtrConstant(4, DL));
12220 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12221 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12223 // The PSHUFB mask:
12224 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12225 -1, -1, -1, -1, -1, -1, -1, -1};
12227 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12228 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12229 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12231 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12232 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12234 // The MOVLHPS Mask:
12235 static const int ShufMask2[] = {0, 1, 4, 5};
12236 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12237 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12240 // Handle truncation of V256 to V128 using shuffles.
12241 if (!VT.is128BitVector() || !InVT.is256BitVector())
12244 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12246 unsigned NumElems = VT.getVectorNumElements();
12247 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12249 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12250 // Prepare truncation shuffle mask
12251 for (unsigned i = 0; i != NumElems; ++i)
12252 MaskVec[i] = i * 2;
12253 SDValue V = DAG.getVectorShuffle(NVT, DL,
12254 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12255 DAG.getUNDEF(NVT), &MaskVec[0]);
12256 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12257 DAG.getIntPtrConstant(0, DL));
12260 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12261 SelectionDAG &DAG) const {
12262 assert(!Op.getSimpleValueType().isVector());
12264 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12265 /*IsSigned=*/ true, /*IsReplace=*/ false);
12266 SDValue FIST = Vals.first, StackSlot = Vals.second;
12267 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12268 if (!FIST.getNode()) return Op;
12270 if (StackSlot.getNode())
12271 // Load the result.
12272 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12273 FIST, StackSlot, MachinePointerInfo(),
12274 false, false, false, 0);
12276 // The node is the result.
12280 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12281 SelectionDAG &DAG) const {
12282 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12283 /*IsSigned=*/ false, /*IsReplace=*/ false);
12284 SDValue FIST = Vals.first, StackSlot = Vals.second;
12285 assert(FIST.getNode() && "Unexpected failure");
12287 if (StackSlot.getNode())
12288 // Load the result.
12289 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12290 FIST, StackSlot, MachinePointerInfo(),
12291 false, false, false, 0);
12293 // The node is the result.
12297 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12299 MVT VT = Op.getSimpleValueType();
12300 SDValue In = Op.getOperand(0);
12301 MVT SVT = In.getSimpleValueType();
12303 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12305 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12306 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12307 In, DAG.getUNDEF(SVT)));
12310 /// The only differences between FABS and FNEG are the mask and the logic op.
12311 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12312 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12313 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12314 "Wrong opcode for lowering FABS or FNEG.");
12316 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12318 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12319 // into an FNABS. We'll lower the FABS after that if it is still in use.
12321 for (SDNode *User : Op->uses())
12322 if (User->getOpcode() == ISD::FNEG)
12325 SDValue Op0 = Op.getOperand(0);
12326 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12329 MVT VT = Op.getSimpleValueType();
12330 // Assume scalar op for initialization; update for vector if needed.
12331 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12332 // generate a 16-byte vector constant and logic op even for the scalar case.
12333 // Using a 16-byte mask allows folding the load of the mask with
12334 // the logic op, so it can save (~4 bytes) on code size.
12336 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12337 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12338 // decide if we should generate a 16-byte constant mask when we only need 4 or
12339 // 8 bytes for the scalar case.
12340 if (VT.isVector()) {
12341 EltVT = VT.getVectorElementType();
12342 NumElts = VT.getVectorNumElements();
12345 unsigned EltBits = EltVT.getSizeInBits();
12346 LLVMContext *Context = DAG.getContext();
12347 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12349 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12350 Constant *C = ConstantInt::get(*Context, MaskElt);
12351 C = ConstantVector::getSplat(NumElts, C);
12352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12353 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12354 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12355 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12356 MachinePointerInfo::getConstantPool(),
12357 false, false, false, Alignment);
12359 if (VT.isVector()) {
12360 // For a vector, cast operands to a vector type, perform the logic op,
12361 // and cast the result back to the original value type.
12362 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12363 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12364 SDValue Operand = IsFNABS ?
12365 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12366 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12367 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12368 return DAG.getNode(ISD::BITCAST, dl, VT,
12369 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12372 // If not vector, then scalar.
12373 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12374 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12375 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12378 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12379 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12380 LLVMContext *Context = DAG.getContext();
12381 SDValue Op0 = Op.getOperand(0);
12382 SDValue Op1 = Op.getOperand(1);
12384 MVT VT = Op.getSimpleValueType();
12385 MVT SrcVT = Op1.getSimpleValueType();
12387 // If second operand is smaller, extend it first.
12388 if (SrcVT.bitsLT(VT)) {
12389 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12392 // And if it is bigger, shrink it first.
12393 if (SrcVT.bitsGT(VT)) {
12394 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12398 // At this point the operands and the result should have the same
12399 // type, and that won't be f80 since that is not custom lowered.
12401 const fltSemantics &Sem =
12402 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12403 const unsigned SizeInBits = VT.getSizeInBits();
12405 SmallVector<Constant *, 4> CV(
12406 VT == MVT::f64 ? 2 : 4,
12407 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12409 // First, clear all bits but the sign bit from the second operand (sign).
12410 CV[0] = ConstantFP::get(*Context,
12411 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12412 Constant *C = ConstantVector::get(CV);
12413 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12414 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12415 MachinePointerInfo::getConstantPool(),
12416 false, false, false, 16);
12417 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12419 // Next, clear the sign bit from the first operand (magnitude).
12420 // If it's a constant, we can clear it here.
12421 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12422 APFloat APF = Op0CN->getValueAPF();
12423 // If the magnitude is a positive zero, the sign bit alone is enough.
12424 if (APF.isPosZero())
12427 CV[0] = ConstantFP::get(*Context, APF);
12429 CV[0] = ConstantFP::get(
12431 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12433 C = ConstantVector::get(CV);
12434 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12435 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12436 MachinePointerInfo::getConstantPool(),
12437 false, false, false, 16);
12438 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12439 if (!isa<ConstantFPSDNode>(Op0))
12440 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12442 // OR the magnitude value with the sign bit.
12443 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12446 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12447 SDValue N0 = Op.getOperand(0);
12449 MVT VT = Op.getSimpleValueType();
12451 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12452 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12453 DAG.getConstant(1, dl, VT));
12454 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12457 // Check whether an OR'd tree is PTEST-able.
12458 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12459 SelectionDAG &DAG) {
12460 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12462 if (!Subtarget->hasSSE41())
12465 if (!Op->hasOneUse())
12468 SDNode *N = Op.getNode();
12471 SmallVector<SDValue, 8> Opnds;
12472 DenseMap<SDValue, unsigned> VecInMap;
12473 SmallVector<SDValue, 8> VecIns;
12474 EVT VT = MVT::Other;
12476 // Recognize a special case where a vector is casted into wide integer to
12478 Opnds.push_back(N->getOperand(0));
12479 Opnds.push_back(N->getOperand(1));
12481 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12482 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12483 // BFS traverse all OR'd operands.
12484 if (I->getOpcode() == ISD::OR) {
12485 Opnds.push_back(I->getOperand(0));
12486 Opnds.push_back(I->getOperand(1));
12487 // Re-evaluate the number of nodes to be traversed.
12488 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12492 // Quit if a non-EXTRACT_VECTOR_ELT
12493 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12496 // Quit if without a constant index.
12497 SDValue Idx = I->getOperand(1);
12498 if (!isa<ConstantSDNode>(Idx))
12501 SDValue ExtractedFromVec = I->getOperand(0);
12502 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12503 if (M == VecInMap.end()) {
12504 VT = ExtractedFromVec.getValueType();
12505 // Quit if not 128/256-bit vector.
12506 if (!VT.is128BitVector() && !VT.is256BitVector())
12508 // Quit if not the same type.
12509 if (VecInMap.begin() != VecInMap.end() &&
12510 VT != VecInMap.begin()->first.getValueType())
12512 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12513 VecIns.push_back(ExtractedFromVec);
12515 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12518 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12519 "Not extracted from 128-/256-bit vector.");
12521 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12523 for (DenseMap<SDValue, unsigned>::const_iterator
12524 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12525 // Quit if not all elements are used.
12526 if (I->second != FullMask)
12530 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12532 // Cast all vectors into TestVT for PTEST.
12533 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12534 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12536 // If more than one full vectors are evaluated, OR them first before PTEST.
12537 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12538 // Each iteration will OR 2 nodes and append the result until there is only
12539 // 1 node left, i.e. the final OR'd value of all vectors.
12540 SDValue LHS = VecIns[Slot];
12541 SDValue RHS = VecIns[Slot + 1];
12542 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12545 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12546 VecIns.back(), VecIns.back());
12549 /// \brief return true if \c Op has a use that doesn't just read flags.
12550 static bool hasNonFlagsUse(SDValue Op) {
12551 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12553 SDNode *User = *UI;
12554 unsigned UOpNo = UI.getOperandNo();
12555 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12556 // Look pass truncate.
12557 UOpNo = User->use_begin().getOperandNo();
12558 User = *User->use_begin();
12561 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12562 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12568 /// Emit nodes that will be selected as "test Op0,Op0", or something
12570 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12571 SelectionDAG &DAG) const {
12572 if (Op.getValueType() == MVT::i1) {
12573 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12574 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12575 DAG.getConstant(0, dl, MVT::i8));
12577 // CF and OF aren't always set the way we want. Determine which
12578 // of these we need.
12579 bool NeedCF = false;
12580 bool NeedOF = false;
12583 case X86::COND_A: case X86::COND_AE:
12584 case X86::COND_B: case X86::COND_BE:
12587 case X86::COND_G: case X86::COND_GE:
12588 case X86::COND_L: case X86::COND_LE:
12589 case X86::COND_O: case X86::COND_NO: {
12590 // Check if we really need to set the
12591 // Overflow flag. If NoSignedWrap is present
12592 // that is not actually needed.
12593 switch (Op->getOpcode()) {
12598 const BinaryWithFlagsSDNode *BinNode =
12599 cast<BinaryWithFlagsSDNode>(Op.getNode());
12600 if (BinNode->Flags.hasNoSignedWrap())
12610 // See if we can use the EFLAGS value from the operand instead of
12611 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12612 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12613 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12614 // Emit a CMP with 0, which is the TEST pattern.
12615 //if (Op.getValueType() == MVT::i1)
12616 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12617 // DAG.getConstant(0, MVT::i1));
12618 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12619 DAG.getConstant(0, dl, Op.getValueType()));
12621 unsigned Opcode = 0;
12622 unsigned NumOperands = 0;
12624 // Truncate operations may prevent the merge of the SETCC instruction
12625 // and the arithmetic instruction before it. Attempt to truncate the operands
12626 // of the arithmetic instruction and use a reduced bit-width instruction.
12627 bool NeedTruncation = false;
12628 SDValue ArithOp = Op;
12629 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12630 SDValue Arith = Op->getOperand(0);
12631 // Both the trunc and the arithmetic op need to have one user each.
12632 if (Arith->hasOneUse())
12633 switch (Arith.getOpcode()) {
12640 NeedTruncation = true;
12646 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12647 // which may be the result of a CAST. We use the variable 'Op', which is the
12648 // non-casted variable when we check for possible users.
12649 switch (ArithOp.getOpcode()) {
12651 // Due to an isel shortcoming, be conservative if this add is likely to be
12652 // selected as part of a load-modify-store instruction. When the root node
12653 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12654 // uses of other nodes in the match, such as the ADD in this case. This
12655 // leads to the ADD being left around and reselected, with the result being
12656 // two adds in the output. Alas, even if none our users are stores, that
12657 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12658 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12659 // climbing the DAG back to the root, and it doesn't seem to be worth the
12661 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12662 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12663 if (UI->getOpcode() != ISD::CopyToReg &&
12664 UI->getOpcode() != ISD::SETCC &&
12665 UI->getOpcode() != ISD::STORE)
12668 if (ConstantSDNode *C =
12669 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12670 // An add of one will be selected as an INC.
12671 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12672 Opcode = X86ISD::INC;
12677 // An add of negative one (subtract of one) will be selected as a DEC.
12678 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12679 Opcode = X86ISD::DEC;
12685 // Otherwise use a regular EFLAGS-setting add.
12686 Opcode = X86ISD::ADD;
12691 // If we have a constant logical shift that's only used in a comparison
12692 // against zero turn it into an equivalent AND. This allows turning it into
12693 // a TEST instruction later.
12694 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12695 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12696 EVT VT = Op.getValueType();
12697 unsigned BitWidth = VT.getSizeInBits();
12698 unsigned ShAmt = Op->getConstantOperandVal(1);
12699 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12701 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12702 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12703 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12704 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12706 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12707 DAG.getConstant(Mask, dl, VT));
12708 DAG.ReplaceAllUsesWith(Op, New);
12714 // If the primary and result isn't used, don't bother using X86ISD::AND,
12715 // because a TEST instruction will be better.
12716 if (!hasNonFlagsUse(Op))
12722 // Due to the ISEL shortcoming noted above, be conservative if this op is
12723 // likely to be selected as part of a load-modify-store instruction.
12724 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12725 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12726 if (UI->getOpcode() == ISD::STORE)
12729 // Otherwise use a regular EFLAGS-setting instruction.
12730 switch (ArithOp.getOpcode()) {
12731 default: llvm_unreachable("unexpected operator!");
12732 case ISD::SUB: Opcode = X86ISD::SUB; break;
12733 case ISD::XOR: Opcode = X86ISD::XOR; break;
12734 case ISD::AND: Opcode = X86ISD::AND; break;
12736 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12737 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12738 if (EFLAGS.getNode())
12741 Opcode = X86ISD::OR;
12755 return SDValue(Op.getNode(), 1);
12761 // If we found that truncation is beneficial, perform the truncation and
12763 if (NeedTruncation) {
12764 EVT VT = Op.getValueType();
12765 SDValue WideVal = Op->getOperand(0);
12766 EVT WideVT = WideVal.getValueType();
12767 unsigned ConvertedOp = 0;
12768 // Use a target machine opcode to prevent further DAGCombine
12769 // optimizations that may separate the arithmetic operations
12770 // from the setcc node.
12771 switch (WideVal.getOpcode()) {
12773 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12774 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12775 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12776 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12777 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12781 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12782 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12783 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12784 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12785 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12791 // Emit a CMP with 0, which is the TEST pattern.
12792 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12793 DAG.getConstant(0, dl, Op.getValueType()));
12795 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12796 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12798 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12799 DAG.ReplaceAllUsesWith(Op, New);
12800 return SDValue(New.getNode(), 1);
12803 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12805 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12806 SDLoc dl, SelectionDAG &DAG) const {
12807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12808 if (C->getAPIntValue() == 0)
12809 return EmitTest(Op0, X86CC, dl, DAG);
12811 if (Op0.getValueType() == MVT::i1)
12812 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12815 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12816 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12817 // Do the comparison at i32 if it's smaller, besides the Atom case.
12818 // This avoids subregister aliasing issues. Keep the smaller reference
12819 // if we're optimizing for size, however, as that'll allow better folding
12820 // of memory operations.
12821 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12822 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12823 Attribute::MinSize) &&
12824 !Subtarget->isAtom()) {
12825 unsigned ExtendOp =
12826 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12827 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12828 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12830 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12831 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12832 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12834 return SDValue(Sub.getNode(), 1);
12836 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12839 /// Convert a comparison if required by the subtarget.
12840 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12841 SelectionDAG &DAG) const {
12842 // If the subtarget does not support the FUCOMI instruction, floating-point
12843 // comparisons have to be converted.
12844 if (Subtarget->hasCMov() ||
12845 Cmp.getOpcode() != X86ISD::CMP ||
12846 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12847 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12850 // The instruction selector will select an FUCOM instruction instead of
12851 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12852 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12853 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12855 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12856 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12857 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12858 DAG.getConstant(8, dl, MVT::i8));
12859 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12860 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12863 /// The minimum architected relative accuracy is 2^-12. We need one
12864 /// Newton-Raphson step to have a good float result (24 bits of precision).
12865 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12866 DAGCombinerInfo &DCI,
12867 unsigned &RefinementSteps,
12868 bool &UseOneConstNR) const {
12869 // FIXME: We should use instruction latency models to calculate the cost of
12870 // each potential sequence, but this is very hard to do reliably because
12871 // at least Intel's Core* chips have variable timing based on the number of
12872 // significant digits in the divisor and/or sqrt operand.
12873 if (!Subtarget->useSqrtEst())
12876 EVT VT = Op.getValueType();
12878 // SSE1 has rsqrtss and rsqrtps.
12879 // TODO: Add support for AVX512 (v16f32).
12880 // It is likely not profitable to do this for f64 because a double-precision
12881 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12882 // instructions: convert to single, rsqrtss, convert back to double, refine
12883 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12884 // along with FMA, this could be a throughput win.
12885 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12886 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12887 RefinementSteps = 1;
12888 UseOneConstNR = false;
12889 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12894 /// The minimum architected relative accuracy is 2^-12. We need one
12895 /// Newton-Raphson step to have a good float result (24 bits of precision).
12896 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12897 DAGCombinerInfo &DCI,
12898 unsigned &RefinementSteps) const {
12899 // FIXME: We should use instruction latency models to calculate the cost of
12900 // each potential sequence, but this is very hard to do reliably because
12901 // at least Intel's Core* chips have variable timing based on the number of
12902 // significant digits in the divisor.
12903 if (!Subtarget->useReciprocalEst())
12906 EVT VT = Op.getValueType();
12908 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12909 // TODO: Add support for AVX512 (v16f32).
12910 // It is likely not profitable to do this for f64 because a double-precision
12911 // reciprocal estimate with refinement on x86 prior to FMA requires
12912 // 15 instructions: convert to single, rcpss, convert back to double, refine
12913 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12914 // along with FMA, this could be a throughput win.
12915 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12916 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12917 RefinementSteps = ReciprocalEstimateRefinementSteps;
12918 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12923 /// If we have at least two divisions that use the same divisor, convert to
12924 /// multplication by a reciprocal. This may need to be adjusted for a given
12925 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12926 /// This is because we still need one division to calculate the reciprocal and
12927 /// then we need two multiplies by that reciprocal as replacements for the
12928 /// original divisions.
12929 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12930 return NumUsers > 1;
12933 static bool isAllOnes(SDValue V) {
12934 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12935 return C && C->isAllOnesValue();
12938 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12939 /// if it's possible.
12940 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12941 SDLoc dl, SelectionDAG &DAG) const {
12942 SDValue Op0 = And.getOperand(0);
12943 SDValue Op1 = And.getOperand(1);
12944 if (Op0.getOpcode() == ISD::TRUNCATE)
12945 Op0 = Op0.getOperand(0);
12946 if (Op1.getOpcode() == ISD::TRUNCATE)
12947 Op1 = Op1.getOperand(0);
12950 if (Op1.getOpcode() == ISD::SHL)
12951 std::swap(Op0, Op1);
12952 if (Op0.getOpcode() == ISD::SHL) {
12953 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12954 if (And00C->getZExtValue() == 1) {
12955 // If we looked past a truncate, check that it's only truncating away
12957 unsigned BitWidth = Op0.getValueSizeInBits();
12958 unsigned AndBitWidth = And.getValueSizeInBits();
12959 if (BitWidth > AndBitWidth) {
12961 DAG.computeKnownBits(Op0, Zeros, Ones);
12962 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12966 RHS = Op0.getOperand(1);
12968 } else if (Op1.getOpcode() == ISD::Constant) {
12969 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12970 uint64_t AndRHSVal = AndRHS->getZExtValue();
12971 SDValue AndLHS = Op0;
12973 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12974 LHS = AndLHS.getOperand(0);
12975 RHS = AndLHS.getOperand(1);
12978 // Use BT if the immediate can't be encoded in a TEST instruction.
12979 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12981 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
12985 if (LHS.getNode()) {
12986 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12987 // instruction. Since the shift amount is in-range-or-undefined, we know
12988 // that doing a bittest on the i32 value is ok. We extend to i32 because
12989 // the encoding for the i16 version is larger than the i32 version.
12990 // Also promote i16 to i32 for performance / code size reason.
12991 if (LHS.getValueType() == MVT::i8 ||
12992 LHS.getValueType() == MVT::i16)
12993 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12995 // If the operand types disagree, extend the shift amount to match. Since
12996 // BT ignores high bits (like shifts) we can use anyextend.
12997 if (LHS.getValueType() != RHS.getValueType())
12998 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13000 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13001 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13002 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13003 DAG.getConstant(Cond, dl, MVT::i8), BT);
13009 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13011 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13016 // SSE Condition code mapping:
13025 switch (SetCCOpcode) {
13026 default: llvm_unreachable("Unexpected SETCC condition");
13028 case ISD::SETEQ: SSECC = 0; break;
13030 case ISD::SETGT: Swap = true; // Fallthrough
13032 case ISD::SETOLT: SSECC = 1; break;
13034 case ISD::SETGE: Swap = true; // Fallthrough
13036 case ISD::SETOLE: SSECC = 2; break;
13037 case ISD::SETUO: SSECC = 3; break;
13039 case ISD::SETNE: SSECC = 4; break;
13040 case ISD::SETULE: Swap = true; // Fallthrough
13041 case ISD::SETUGE: SSECC = 5; break;
13042 case ISD::SETULT: Swap = true; // Fallthrough
13043 case ISD::SETUGT: SSECC = 6; break;
13044 case ISD::SETO: SSECC = 7; break;
13046 case ISD::SETONE: SSECC = 8; break;
13049 std::swap(Op0, Op1);
13054 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13055 // ones, and then concatenate the result back.
13056 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13057 MVT VT = Op.getSimpleValueType();
13059 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13060 "Unsupported value type for operation");
13062 unsigned NumElems = VT.getVectorNumElements();
13064 SDValue CC = Op.getOperand(2);
13066 // Extract the LHS vectors
13067 SDValue LHS = Op.getOperand(0);
13068 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13069 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13071 // Extract the RHS vectors
13072 SDValue RHS = Op.getOperand(1);
13073 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13074 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13076 // Issue the operation on the smaller types and concatenate the result back
13077 MVT EltVT = VT.getVectorElementType();
13078 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13079 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13080 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13081 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13084 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13085 SDValue Op0 = Op.getOperand(0);
13086 SDValue Op1 = Op.getOperand(1);
13087 SDValue CC = Op.getOperand(2);
13088 MVT VT = Op.getSimpleValueType();
13091 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13092 "Unexpected type for boolean compare operation");
13093 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13094 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13095 DAG.getConstant(-1, dl, VT));
13096 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13097 DAG.getConstant(-1, dl, VT));
13098 switch (SetCCOpcode) {
13099 default: llvm_unreachable("Unexpected SETCC condition");
13101 // (x != y) -> ~(x ^ y)
13102 return DAG.getNode(ISD::XOR, dl, VT,
13103 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13104 DAG.getConstant(-1, dl, VT));
13106 // (x == y) -> (x ^ y)
13107 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13110 // (x > y) -> (x & ~y)
13111 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13114 // (x < y) -> (~x & y)
13115 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13118 // (x <= y) -> (~x | y)
13119 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13122 // (x >=y) -> (x | ~y)
13123 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13127 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13128 const X86Subtarget *Subtarget) {
13129 SDValue Op0 = Op.getOperand(0);
13130 SDValue Op1 = Op.getOperand(1);
13131 SDValue CC = Op.getOperand(2);
13132 MVT VT = Op.getSimpleValueType();
13135 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13136 Op.getValueType().getScalarType() == MVT::i1 &&
13137 "Cannot set masked compare for this operation");
13139 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13141 bool Unsigned = false;
13144 switch (SetCCOpcode) {
13145 default: llvm_unreachable("Unexpected SETCC condition");
13146 case ISD::SETNE: SSECC = 4; break;
13147 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13148 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13149 case ISD::SETLT: Swap = true; //fall-through
13150 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13151 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13152 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13153 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13154 case ISD::SETULE: Unsigned = true; //fall-through
13155 case ISD::SETLE: SSECC = 2; break;
13159 std::swap(Op0, Op1);
13161 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13162 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13163 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13164 DAG.getConstant(SSECC, dl, MVT::i8));
13167 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13168 /// operand \p Op1. If non-trivial (for example because it's not constant)
13169 /// return an empty value.
13170 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13172 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13176 MVT VT = Op1.getSimpleValueType();
13177 MVT EVT = VT.getVectorElementType();
13178 unsigned n = VT.getVectorNumElements();
13179 SmallVector<SDValue, 8> ULTOp1;
13181 for (unsigned i = 0; i < n; ++i) {
13182 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13183 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13186 // Avoid underflow.
13187 APInt Val = Elt->getAPIntValue();
13191 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13194 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13197 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13198 SelectionDAG &DAG) {
13199 SDValue Op0 = Op.getOperand(0);
13200 SDValue Op1 = Op.getOperand(1);
13201 SDValue CC = Op.getOperand(2);
13202 MVT VT = Op.getSimpleValueType();
13203 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13204 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13209 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13210 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13213 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13214 unsigned Opc = X86ISD::CMPP;
13215 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13216 assert(VT.getVectorNumElements() <= 16);
13217 Opc = X86ISD::CMPM;
13219 // In the two special cases we can't handle, emit two comparisons.
13222 unsigned CombineOpc;
13223 if (SetCCOpcode == ISD::SETUEQ) {
13224 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13226 assert(SetCCOpcode == ISD::SETONE);
13227 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13230 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13231 DAG.getConstant(CC0, dl, MVT::i8));
13232 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13233 DAG.getConstant(CC1, dl, MVT::i8));
13234 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13236 // Handle all other FP comparisons here.
13237 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13238 DAG.getConstant(SSECC, dl, MVT::i8));
13241 // Break 256-bit integer vector compare into smaller ones.
13242 if (VT.is256BitVector() && !Subtarget->hasInt256())
13243 return Lower256IntVSETCC(Op, DAG);
13245 EVT OpVT = Op1.getValueType();
13246 if (OpVT.getVectorElementType() == MVT::i1)
13247 return LowerBoolVSETCC_AVX512(Op, DAG);
13249 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13250 if (Subtarget->hasAVX512()) {
13251 if (Op1.getValueType().is512BitVector() ||
13252 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13253 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13254 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13256 // In AVX-512 architecture setcc returns mask with i1 elements,
13257 // But there is no compare instruction for i8 and i16 elements in KNL.
13258 // We are not talking about 512-bit operands in this case, these
13259 // types are illegal.
13261 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13262 OpVT.getVectorElementType().getSizeInBits() >= 8))
13263 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13264 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13267 // We are handling one of the integer comparisons here. Since SSE only has
13268 // GT and EQ comparisons for integer, swapping operands and multiple
13269 // operations may be required for some comparisons.
13271 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13272 bool Subus = false;
13274 switch (SetCCOpcode) {
13275 default: llvm_unreachable("Unexpected SETCC condition");
13276 case ISD::SETNE: Invert = true;
13277 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13278 case ISD::SETLT: Swap = true;
13279 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13280 case ISD::SETGE: Swap = true;
13281 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13282 Invert = true; break;
13283 case ISD::SETULT: Swap = true;
13284 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13285 FlipSigns = true; break;
13286 case ISD::SETUGE: Swap = true;
13287 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13288 FlipSigns = true; Invert = true; break;
13291 // Special case: Use min/max operations for SETULE/SETUGE
13292 MVT VET = VT.getVectorElementType();
13294 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13295 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13298 switch (SetCCOpcode) {
13300 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13301 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13304 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13307 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13308 if (!MinMax && hasSubus) {
13309 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13311 // t = psubus Op0, Op1
13312 // pcmpeq t, <0..0>
13313 switch (SetCCOpcode) {
13315 case ISD::SETULT: {
13316 // If the comparison is against a constant we can turn this into a
13317 // setule. With psubus, setule does not require a swap. This is
13318 // beneficial because the constant in the register is no longer
13319 // destructed as the destination so it can be hoisted out of a loop.
13320 // Only do this pre-AVX since vpcmp* is no longer destructive.
13321 if (Subtarget->hasAVX())
13323 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13324 if (ULEOp1.getNode()) {
13326 Subus = true; Invert = false; Swap = false;
13330 // Psubus is better than flip-sign because it requires no inversion.
13331 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13332 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13336 Opc = X86ISD::SUBUS;
13342 std::swap(Op0, Op1);
13344 // Check that the operation in question is available (most are plain SSE2,
13345 // but PCMPGTQ and PCMPEQQ have different requirements).
13346 if (VT == MVT::v2i64) {
13347 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13348 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13350 // First cast everything to the right type.
13351 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13352 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13354 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13355 // bits of the inputs before performing those operations. The lower
13356 // compare is always unsigned.
13359 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13361 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13362 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13363 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13364 Sign, Zero, Sign, Zero);
13366 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13367 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13369 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13370 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13371 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13373 // Create masks for only the low parts/high parts of the 64 bit integers.
13374 static const int MaskHi[] = { 1, 1, 3, 3 };
13375 static const int MaskLo[] = { 0, 0, 2, 2 };
13376 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13377 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13378 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13380 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13381 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13384 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13386 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13389 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13390 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13391 // pcmpeqd + pshufd + pand.
13392 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13394 // First cast everything to the right type.
13395 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13396 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13399 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13401 // Make sure the lower and upper halves are both all-ones.
13402 static const int Mask[] = { 1, 0, 3, 2 };
13403 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13404 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13407 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13409 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13413 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13414 // bits of the inputs before performing those operations.
13416 EVT EltVT = VT.getVectorElementType();
13417 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13419 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13420 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13423 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13425 // If the logical-not of the result is required, perform that now.
13427 Result = DAG.getNOT(dl, Result, VT);
13430 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13433 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13434 getZeroVector(VT, Subtarget, DAG, dl));
13439 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13441 MVT VT = Op.getSimpleValueType();
13443 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13445 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13446 && "SetCC type must be 8-bit or 1-bit integer");
13447 SDValue Op0 = Op.getOperand(0);
13448 SDValue Op1 = Op.getOperand(1);
13450 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13452 // Optimize to BT if possible.
13453 // Lower (X & (1 << N)) == 0 to BT(X, N).
13454 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13455 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13456 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13457 Op1.getOpcode() == ISD::Constant &&
13458 cast<ConstantSDNode>(Op1)->isNullValue() &&
13459 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13460 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13461 if (NewSetCC.getNode()) {
13463 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13468 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13470 if (Op1.getOpcode() == ISD::Constant &&
13471 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13472 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13473 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13475 // If the input is a setcc, then reuse the input setcc or use a new one with
13476 // the inverted condition.
13477 if (Op0.getOpcode() == X86ISD::SETCC) {
13478 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13479 bool Invert = (CC == ISD::SETNE) ^
13480 cast<ConstantSDNode>(Op1)->isNullValue();
13484 CCode = X86::GetOppositeBranchCondition(CCode);
13485 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13486 DAG.getConstant(CCode, dl, MVT::i8),
13487 Op0.getOperand(1));
13489 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13493 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13494 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13495 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13497 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13498 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13501 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13502 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13503 if (X86CC == X86::COND_INVALID)
13506 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13507 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13508 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13509 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13511 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13515 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13516 static bool isX86LogicalCmp(SDValue Op) {
13517 unsigned Opc = Op.getNode()->getOpcode();
13518 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13519 Opc == X86ISD::SAHF)
13521 if (Op.getResNo() == 1 &&
13522 (Opc == X86ISD::ADD ||
13523 Opc == X86ISD::SUB ||
13524 Opc == X86ISD::ADC ||
13525 Opc == X86ISD::SBB ||
13526 Opc == X86ISD::SMUL ||
13527 Opc == X86ISD::UMUL ||
13528 Opc == X86ISD::INC ||
13529 Opc == X86ISD::DEC ||
13530 Opc == X86ISD::OR ||
13531 Opc == X86ISD::XOR ||
13532 Opc == X86ISD::AND))
13535 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13541 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13542 if (V.getOpcode() != ISD::TRUNCATE)
13545 SDValue VOp0 = V.getOperand(0);
13546 unsigned InBits = VOp0.getValueSizeInBits();
13547 unsigned Bits = V.getValueSizeInBits();
13548 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13551 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13552 bool addTest = true;
13553 SDValue Cond = Op.getOperand(0);
13554 SDValue Op1 = Op.getOperand(1);
13555 SDValue Op2 = Op.getOperand(2);
13557 EVT VT = Op1.getValueType();
13560 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13561 // are available or VBLENDV if AVX is available.
13562 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13563 if (Cond.getOpcode() == ISD::SETCC &&
13564 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13565 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13566 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13567 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13568 int SSECC = translateX86FSETCC(
13569 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13572 if (Subtarget->hasAVX512()) {
13573 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13574 DAG.getConstant(SSECC, DL, MVT::i8));
13575 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13578 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13579 DAG.getConstant(SSECC, DL, MVT::i8));
13581 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13582 // of 3 logic instructions for size savings and potentially speed.
13583 // Unfortunately, there is no scalar form of VBLENDV.
13585 // If either operand is a constant, don't try this. We can expect to
13586 // optimize away at least one of the logic instructions later in that
13587 // case, so that sequence would be faster than a variable blend.
13589 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13590 // uses XMM0 as the selection register. That may need just as many
13591 // instructions as the AND/ANDN/OR sequence due to register moves, so
13594 if (Subtarget->hasAVX() &&
13595 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13597 // Convert to vectors, do a VSELECT, and convert back to scalar.
13598 // All of the conversions should be optimized away.
13600 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13601 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13602 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13603 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13605 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13606 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13608 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13610 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13611 VSel, DAG.getIntPtrConstant(0, DL));
13613 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13614 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13615 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13619 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13620 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13621 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13622 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13623 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13624 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13625 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13627 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13630 if (Cond.getOpcode() == ISD::SETCC) {
13631 SDValue NewCond = LowerSETCC(Cond, DAG);
13632 if (NewCond.getNode())
13636 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13637 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13638 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13639 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13640 if (Cond.getOpcode() == X86ISD::SETCC &&
13641 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13642 isZero(Cond.getOperand(1).getOperand(1))) {
13643 SDValue Cmp = Cond.getOperand(1);
13645 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13647 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13648 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13649 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13651 SDValue CmpOp0 = Cmp.getOperand(0);
13652 // Apply further optimizations for special cases
13653 // (select (x != 0), -1, 0) -> neg & sbb
13654 // (select (x == 0), 0, -1) -> neg & sbb
13655 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13656 if (YC->isNullValue() &&
13657 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13658 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13659 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13660 DAG.getConstant(0, DL,
13661 CmpOp0.getValueType()),
13663 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13664 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13665 SDValue(Neg.getNode(), 1));
13669 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13670 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13671 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13673 SDValue Res = // Res = 0 or -1.
13674 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13675 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13677 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13678 Res = DAG.getNOT(DL, Res, Res.getValueType());
13680 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13681 if (!N2C || !N2C->isNullValue())
13682 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13687 // Look past (and (setcc_carry (cmp ...)), 1).
13688 if (Cond.getOpcode() == ISD::AND &&
13689 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13690 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13691 if (C && C->getAPIntValue() == 1)
13692 Cond = Cond.getOperand(0);
13695 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13696 // setting operand in place of the X86ISD::SETCC.
13697 unsigned CondOpcode = Cond.getOpcode();
13698 if (CondOpcode == X86ISD::SETCC ||
13699 CondOpcode == X86ISD::SETCC_CARRY) {
13700 CC = Cond.getOperand(0);
13702 SDValue Cmp = Cond.getOperand(1);
13703 unsigned Opc = Cmp.getOpcode();
13704 MVT VT = Op.getSimpleValueType();
13706 bool IllegalFPCMov = false;
13707 if (VT.isFloatingPoint() && !VT.isVector() &&
13708 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13709 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13711 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13712 Opc == X86ISD::BT) { // FIXME
13716 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13717 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13718 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13719 Cond.getOperand(0).getValueType() != MVT::i8)) {
13720 SDValue LHS = Cond.getOperand(0);
13721 SDValue RHS = Cond.getOperand(1);
13722 unsigned X86Opcode;
13725 switch (CondOpcode) {
13726 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13727 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13728 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13729 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13730 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13731 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13732 default: llvm_unreachable("unexpected overflowing operator");
13734 if (CondOpcode == ISD::UMULO)
13735 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13738 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13740 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13742 if (CondOpcode == ISD::UMULO)
13743 Cond = X86Op.getValue(2);
13745 Cond = X86Op.getValue(1);
13747 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13752 // Look pass the truncate if the high bits are known zero.
13753 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13754 Cond = Cond.getOperand(0);
13756 // We know the result of AND is compared against zero. Try to match
13758 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13759 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13760 if (NewSetCC.getNode()) {
13761 CC = NewSetCC.getOperand(0);
13762 Cond = NewSetCC.getOperand(1);
13769 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13770 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13773 // a < b ? -1 : 0 -> RES = ~setcc_carry
13774 // a < b ? 0 : -1 -> RES = setcc_carry
13775 // a >= b ? -1 : 0 -> RES = setcc_carry
13776 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13777 if (Cond.getOpcode() == X86ISD::SUB) {
13778 Cond = ConvertCmpIfNecessary(Cond, DAG);
13779 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13781 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13782 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13783 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13784 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13786 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13787 return DAG.getNOT(DL, Res, Res.getValueType());
13792 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13793 // widen the cmov and push the truncate through. This avoids introducing a new
13794 // branch during isel and doesn't add any extensions.
13795 if (Op.getValueType() == MVT::i8 &&
13796 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13797 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13798 if (T1.getValueType() == T2.getValueType() &&
13799 // Blacklist CopyFromReg to avoid partial register stalls.
13800 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13801 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13802 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13803 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13807 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13808 // condition is true.
13809 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13810 SDValue Ops[] = { Op2, Op1, CC, Cond };
13811 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13814 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13815 SelectionDAG &DAG) {
13816 MVT VT = Op->getSimpleValueType(0);
13817 SDValue In = Op->getOperand(0);
13818 MVT InVT = In.getSimpleValueType();
13819 MVT VTElt = VT.getVectorElementType();
13820 MVT InVTElt = InVT.getVectorElementType();
13824 if ((InVTElt == MVT::i1) &&
13825 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13826 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13828 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13829 VTElt.getSizeInBits() <= 16)) ||
13831 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13832 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13834 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13835 VTElt.getSizeInBits() >= 32))))
13836 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13838 unsigned int NumElts = VT.getVectorNumElements();
13840 if (NumElts != 8 && NumElts != 16)
13843 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13844 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13845 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13846 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13849 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13850 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13852 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
13855 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
13857 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
13858 if (VT.is512BitVector())
13860 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
13863 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13864 SelectionDAG &DAG) {
13865 MVT VT = Op->getSimpleValueType(0);
13866 SDValue In = Op->getOperand(0);
13867 MVT InVT = In.getSimpleValueType();
13870 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13871 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13873 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13874 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13875 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13878 if (Subtarget->hasInt256())
13879 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13881 // Optimize vectors in AVX mode
13882 // Sign extend v8i16 to v8i32 and
13885 // Divide input vector into two parts
13886 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13887 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13888 // concat the vectors to original VT
13890 unsigned NumElems = InVT.getVectorNumElements();
13891 SDValue Undef = DAG.getUNDEF(InVT);
13893 SmallVector<int,8> ShufMask1(NumElems, -1);
13894 for (unsigned i = 0; i != NumElems/2; ++i)
13897 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13899 SmallVector<int,8> ShufMask2(NumElems, -1);
13900 for (unsigned i = 0; i != NumElems/2; ++i)
13901 ShufMask2[i] = i + NumElems/2;
13903 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13905 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13906 VT.getVectorNumElements()/2);
13908 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13909 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13911 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13914 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13915 // may emit an illegal shuffle but the expansion is still better than scalar
13916 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13917 // we'll emit a shuffle and a arithmetic shift.
13918 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13919 // TODO: It is possible to support ZExt by zeroing the undef values during
13920 // the shuffle phase or after the shuffle.
13921 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13922 SelectionDAG &DAG) {
13923 MVT RegVT = Op.getSimpleValueType();
13924 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13925 assert(RegVT.isInteger() &&
13926 "We only custom lower integer vector sext loads.");
13928 // Nothing useful we can do without SSE2 shuffles.
13929 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13931 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13933 EVT MemVT = Ld->getMemoryVT();
13934 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13935 unsigned RegSz = RegVT.getSizeInBits();
13937 ISD::LoadExtType Ext = Ld->getExtensionType();
13939 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13940 && "Only anyext and sext are currently implemented.");
13941 assert(MemVT != RegVT && "Cannot extend to the same type");
13942 assert(MemVT.isVector() && "Must load a vector from memory");
13944 unsigned NumElems = RegVT.getVectorNumElements();
13945 unsigned MemSz = MemVT.getSizeInBits();
13946 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13948 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13949 // The only way in which we have a legal 256-bit vector result but not the
13950 // integer 256-bit operations needed to directly lower a sextload is if we
13951 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13952 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13953 // correctly legalized. We do this late to allow the canonical form of
13954 // sextload to persist throughout the rest of the DAG combiner -- it wants
13955 // to fold together any extensions it can, and so will fuse a sign_extend
13956 // of an sextload into a sextload targeting a wider value.
13958 if (MemSz == 128) {
13959 // Just switch this to a normal load.
13960 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13961 "it must be a legal 128-bit vector "
13963 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13964 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13965 Ld->isInvariant(), Ld->getAlignment());
13967 assert(MemSz < 128 &&
13968 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13969 // Do an sext load to a 128-bit vector type. We want to use the same
13970 // number of elements, but elements half as wide. This will end up being
13971 // recursively lowered by this routine, but will succeed as we definitely
13972 // have all the necessary features if we're using AVX1.
13974 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13975 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13977 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13978 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13979 Ld->isNonTemporal(), Ld->isInvariant(),
13980 Ld->getAlignment());
13983 // Replace chain users with the new chain.
13984 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13985 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13987 // Finally, do a normal sign-extend to the desired register.
13988 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13991 // All sizes must be a power of two.
13992 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13993 "Non-power-of-two elements are not custom lowered!");
13995 // Attempt to load the original value using scalar loads.
13996 // Find the largest scalar type that divides the total loaded size.
13997 MVT SclrLoadTy = MVT::i8;
13998 for (MVT Tp : MVT::integer_valuetypes()) {
13999 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14004 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14005 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14007 SclrLoadTy = MVT::f64;
14009 // Calculate the number of scalar loads that we need to perform
14010 // in order to load our vector from memory.
14011 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14013 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14014 "Can only lower sext loads with a single scalar load!");
14016 unsigned loadRegZize = RegSz;
14017 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14020 // Represent our vector as a sequence of elements which are the
14021 // largest scalar that we can load.
14022 EVT LoadUnitVecVT = EVT::getVectorVT(
14023 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14025 // Represent the data using the same element type that is stored in
14026 // memory. In practice, we ''widen'' MemVT.
14028 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14029 loadRegZize / MemVT.getScalarType().getSizeInBits());
14031 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14032 "Invalid vector type");
14034 // We can't shuffle using an illegal type.
14035 assert(TLI.isTypeLegal(WideVecVT) &&
14036 "We only lower types that form legal widened vector types");
14038 SmallVector<SDValue, 8> Chains;
14039 SDValue Ptr = Ld->getBasePtr();
14040 SDValue Increment =
14041 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14042 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14044 for (unsigned i = 0; i < NumLoads; ++i) {
14045 // Perform a single load.
14046 SDValue ScalarLoad =
14047 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14048 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14049 Ld->getAlignment());
14050 Chains.push_back(ScalarLoad.getValue(1));
14051 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14052 // another round of DAGCombining.
14054 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14056 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14057 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14059 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14062 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14064 // Bitcast the loaded value to a vector of the original element type, in
14065 // the size of the target vector type.
14066 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14067 unsigned SizeRatio = RegSz / MemSz;
14069 if (Ext == ISD::SEXTLOAD) {
14070 // If we have SSE4.1, we can directly emit a VSEXT node.
14071 if (Subtarget->hasSSE41()) {
14072 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14073 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14077 // Otherwise we'll shuffle the small elements in the high bits of the
14078 // larger type and perform an arithmetic shift. If the shift is not legal
14079 // it's better to scalarize.
14080 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14081 "We can't implement a sext load without an arithmetic right shift!");
14083 // Redistribute the loaded elements into the different locations.
14084 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14085 for (unsigned i = 0; i != NumElems; ++i)
14086 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14088 SDValue Shuff = DAG.getVectorShuffle(
14089 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14091 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14093 // Build the arithmetic shift.
14094 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14095 MemVT.getVectorElementType().getSizeInBits();
14097 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14098 DAG.getConstant(Amt, dl, RegVT));
14100 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14104 // Redistribute the loaded elements into the different locations.
14105 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14106 for (unsigned i = 0; i != NumElems; ++i)
14107 ShuffleVec[i * SizeRatio] = i;
14109 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14110 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14112 // Bitcast to the requested type.
14113 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14114 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14118 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14119 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14120 // from the AND / OR.
14121 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14122 Opc = Op.getOpcode();
14123 if (Opc != ISD::OR && Opc != ISD::AND)
14125 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14126 Op.getOperand(0).hasOneUse() &&
14127 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14128 Op.getOperand(1).hasOneUse());
14131 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14132 // 1 and that the SETCC node has a single use.
14133 static bool isXor1OfSetCC(SDValue Op) {
14134 if (Op.getOpcode() != ISD::XOR)
14136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14137 if (N1C && N1C->getAPIntValue() == 1) {
14138 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14139 Op.getOperand(0).hasOneUse();
14144 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14145 bool addTest = true;
14146 SDValue Chain = Op.getOperand(0);
14147 SDValue Cond = Op.getOperand(1);
14148 SDValue Dest = Op.getOperand(2);
14151 bool Inverted = false;
14153 if (Cond.getOpcode() == ISD::SETCC) {
14154 // Check for setcc([su]{add,sub,mul}o == 0).
14155 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14156 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14157 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14158 Cond.getOperand(0).getResNo() == 1 &&
14159 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14160 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14161 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14162 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14163 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14164 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14166 Cond = Cond.getOperand(0);
14168 SDValue NewCond = LowerSETCC(Cond, DAG);
14169 if (NewCond.getNode())
14174 // FIXME: LowerXALUO doesn't handle these!!
14175 else if (Cond.getOpcode() == X86ISD::ADD ||
14176 Cond.getOpcode() == X86ISD::SUB ||
14177 Cond.getOpcode() == X86ISD::SMUL ||
14178 Cond.getOpcode() == X86ISD::UMUL)
14179 Cond = LowerXALUO(Cond, DAG);
14182 // Look pass (and (setcc_carry (cmp ...)), 1).
14183 if (Cond.getOpcode() == ISD::AND &&
14184 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14185 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14186 if (C && C->getAPIntValue() == 1)
14187 Cond = Cond.getOperand(0);
14190 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14191 // setting operand in place of the X86ISD::SETCC.
14192 unsigned CondOpcode = Cond.getOpcode();
14193 if (CondOpcode == X86ISD::SETCC ||
14194 CondOpcode == X86ISD::SETCC_CARRY) {
14195 CC = Cond.getOperand(0);
14197 SDValue Cmp = Cond.getOperand(1);
14198 unsigned Opc = Cmp.getOpcode();
14199 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14200 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14204 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14208 // These can only come from an arithmetic instruction with overflow,
14209 // e.g. SADDO, UADDO.
14210 Cond = Cond.getNode()->getOperand(1);
14216 CondOpcode = Cond.getOpcode();
14217 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14218 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14219 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14220 Cond.getOperand(0).getValueType() != MVT::i8)) {
14221 SDValue LHS = Cond.getOperand(0);
14222 SDValue RHS = Cond.getOperand(1);
14223 unsigned X86Opcode;
14226 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14227 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14229 switch (CondOpcode) {
14230 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14232 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14234 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14237 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14238 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14240 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14242 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14245 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14246 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14247 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14248 default: llvm_unreachable("unexpected overflowing operator");
14251 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14252 if (CondOpcode == ISD::UMULO)
14253 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14256 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14258 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14260 if (CondOpcode == ISD::UMULO)
14261 Cond = X86Op.getValue(2);
14263 Cond = X86Op.getValue(1);
14265 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14269 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14270 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14271 if (CondOpc == ISD::OR) {
14272 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14273 // two branches instead of an explicit OR instruction with a
14275 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14276 isX86LogicalCmp(Cmp)) {
14277 CC = Cond.getOperand(0).getOperand(0);
14278 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14279 Chain, Dest, CC, Cmp);
14280 CC = Cond.getOperand(1).getOperand(0);
14284 } else { // ISD::AND
14285 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14286 // two branches instead of an explicit AND instruction with a
14287 // separate test. However, we only do this if this block doesn't
14288 // have a fall-through edge, because this requires an explicit
14289 // jmp when the condition is false.
14290 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14291 isX86LogicalCmp(Cmp) &&
14292 Op.getNode()->hasOneUse()) {
14293 X86::CondCode CCode =
14294 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14295 CCode = X86::GetOppositeBranchCondition(CCode);
14296 CC = DAG.getConstant(CCode, dl, MVT::i8);
14297 SDNode *User = *Op.getNode()->use_begin();
14298 // Look for an unconditional branch following this conditional branch.
14299 // We need this because we need to reverse the successors in order
14300 // to implement FCMP_OEQ.
14301 if (User->getOpcode() == ISD::BR) {
14302 SDValue FalseBB = User->getOperand(1);
14304 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14305 assert(NewBR == User);
14309 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14310 Chain, Dest, CC, Cmp);
14311 X86::CondCode CCode =
14312 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14313 CCode = X86::GetOppositeBranchCondition(CCode);
14314 CC = DAG.getConstant(CCode, dl, MVT::i8);
14320 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14321 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14322 // It should be transformed during dag combiner except when the condition
14323 // is set by a arithmetics with overflow node.
14324 X86::CondCode CCode =
14325 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14326 CCode = X86::GetOppositeBranchCondition(CCode);
14327 CC = DAG.getConstant(CCode, dl, MVT::i8);
14328 Cond = Cond.getOperand(0).getOperand(1);
14330 } else if (Cond.getOpcode() == ISD::SETCC &&
14331 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14332 // For FCMP_OEQ, we can emit
14333 // two branches instead of an explicit AND instruction with a
14334 // separate test. However, we only do this if this block doesn't
14335 // have a fall-through edge, because this requires an explicit
14336 // jmp when the condition is false.
14337 if (Op.getNode()->hasOneUse()) {
14338 SDNode *User = *Op.getNode()->use_begin();
14339 // Look for an unconditional branch following this conditional branch.
14340 // We need this because we need to reverse the successors in order
14341 // to implement FCMP_OEQ.
14342 if (User->getOpcode() == ISD::BR) {
14343 SDValue FalseBB = User->getOperand(1);
14345 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14346 assert(NewBR == User);
14350 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14351 Cond.getOperand(0), Cond.getOperand(1));
14352 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14353 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14354 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14355 Chain, Dest, CC, Cmp);
14356 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14361 } else if (Cond.getOpcode() == ISD::SETCC &&
14362 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14363 // For FCMP_UNE, we can emit
14364 // two branches instead of an explicit AND instruction with a
14365 // separate test. However, we only do this if this block doesn't
14366 // have a fall-through edge, because this requires an explicit
14367 // jmp when the condition is false.
14368 if (Op.getNode()->hasOneUse()) {
14369 SDNode *User = *Op.getNode()->use_begin();
14370 // Look for an unconditional branch following this conditional branch.
14371 // We need this because we need to reverse the successors in order
14372 // to implement FCMP_UNE.
14373 if (User->getOpcode() == ISD::BR) {
14374 SDValue FalseBB = User->getOperand(1);
14376 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14377 assert(NewBR == User);
14380 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14381 Cond.getOperand(0), Cond.getOperand(1));
14382 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14383 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14384 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14385 Chain, Dest, CC, Cmp);
14386 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14396 // Look pass the truncate if the high bits are known zero.
14397 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14398 Cond = Cond.getOperand(0);
14400 // We know the result of AND is compared against zero. Try to match
14402 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14403 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14404 if (NewSetCC.getNode()) {
14405 CC = NewSetCC.getOperand(0);
14406 Cond = NewSetCC.getOperand(1);
14413 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14414 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14415 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14417 Cond = ConvertCmpIfNecessary(Cond, DAG);
14418 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14419 Chain, Dest, CC, Cond);
14422 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14423 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14424 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14425 // that the guard pages used by the OS virtual memory manager are allocated in
14426 // correct sequence.
14428 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14429 SelectionDAG &DAG) const {
14430 MachineFunction &MF = DAG.getMachineFunction();
14431 bool SplitStack = MF.shouldSplitStack();
14432 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14437 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14438 SDNode* Node = Op.getNode();
14440 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14441 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14442 " not tell us which reg is the stack pointer!");
14443 EVT VT = Node->getValueType(0);
14444 SDValue Tmp1 = SDValue(Node, 0);
14445 SDValue Tmp2 = SDValue(Node, 1);
14446 SDValue Tmp3 = Node->getOperand(2);
14447 SDValue Chain = Tmp1.getOperand(0);
14449 // Chain the dynamic stack allocation so that it doesn't modify the stack
14450 // pointer when other instructions are using the stack.
14451 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14454 SDValue Size = Tmp2.getOperand(1);
14455 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14456 Chain = SP.getValue(1);
14457 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14458 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14459 unsigned StackAlign = TFI.getStackAlignment();
14460 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14461 if (Align > StackAlign)
14462 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14463 DAG.getConstant(-(uint64_t)Align, dl, VT));
14464 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14466 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14467 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14470 SDValue Ops[2] = { Tmp1, Tmp2 };
14471 return DAG.getMergeValues(Ops, dl);
14475 SDValue Chain = Op.getOperand(0);
14476 SDValue Size = Op.getOperand(1);
14477 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14478 EVT VT = Op.getNode()->getValueType(0);
14480 bool Is64Bit = Subtarget->is64Bit();
14481 EVT SPTy = getPointerTy();
14484 MachineRegisterInfo &MRI = MF.getRegInfo();
14487 // The 64 bit implementation of segmented stacks needs to clobber both r10
14488 // r11. This makes it impossible to use it along with nested parameters.
14489 const Function *F = MF.getFunction();
14491 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14493 if (I->hasNestAttr())
14494 report_fatal_error("Cannot use segmented stacks with functions that "
14495 "have nested arguments.");
14498 const TargetRegisterClass *AddrRegClass =
14499 getRegClassFor(getPointerTy());
14500 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14501 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14502 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14503 DAG.getRegister(Vreg, SPTy));
14504 SDValue Ops1[2] = { Value, Chain };
14505 return DAG.getMergeValues(Ops1, dl);
14508 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14510 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14511 Flag = Chain.getValue(1);
14512 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14514 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14516 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14517 unsigned SPReg = RegInfo->getStackRegister();
14518 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14519 Chain = SP.getValue(1);
14522 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14523 DAG.getConstant(-(uint64_t)Align, dl, VT));
14524 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14527 SDValue Ops1[2] = { SP, Chain };
14528 return DAG.getMergeValues(Ops1, dl);
14532 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14533 MachineFunction &MF = DAG.getMachineFunction();
14534 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14536 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14539 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14540 // vastart just stores the address of the VarArgsFrameIndex slot into the
14541 // memory location argument.
14542 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14544 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14545 MachinePointerInfo(SV), false, false, 0);
14549 // gp_offset (0 - 6 * 8)
14550 // fp_offset (48 - 48 + 8 * 16)
14551 // overflow_arg_area (point to parameters coming in memory).
14553 SmallVector<SDValue, 8> MemOps;
14554 SDValue FIN = Op.getOperand(1);
14556 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14557 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14559 FIN, MachinePointerInfo(SV), false, false, 0);
14560 MemOps.push_back(Store);
14563 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14564 FIN, DAG.getIntPtrConstant(4, DL));
14565 Store = DAG.getStore(Op.getOperand(0), DL,
14566 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14568 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14569 MemOps.push_back(Store);
14571 // Store ptr to overflow_arg_area
14572 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14573 FIN, DAG.getIntPtrConstant(4, DL));
14574 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14576 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14577 MachinePointerInfo(SV, 8),
14579 MemOps.push_back(Store);
14581 // Store ptr to reg_save_area.
14582 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14583 FIN, DAG.getIntPtrConstant(8, DL));
14584 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14586 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14587 MachinePointerInfo(SV, 16), false, false, 0);
14588 MemOps.push_back(Store);
14589 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14592 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14593 assert(Subtarget->is64Bit() &&
14594 "LowerVAARG only handles 64-bit va_arg!");
14595 assert((Subtarget->isTargetLinux() ||
14596 Subtarget->isTargetDarwin()) &&
14597 "Unhandled target in LowerVAARG");
14598 assert(Op.getNode()->getNumOperands() == 4);
14599 SDValue Chain = Op.getOperand(0);
14600 SDValue SrcPtr = Op.getOperand(1);
14601 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14602 unsigned Align = Op.getConstantOperandVal(3);
14605 EVT ArgVT = Op.getNode()->getValueType(0);
14606 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14607 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14610 // Decide which area this value should be read from.
14611 // TODO: Implement the AMD64 ABI in its entirety. This simple
14612 // selection mechanism works only for the basic types.
14613 if (ArgVT == MVT::f80) {
14614 llvm_unreachable("va_arg for f80 not yet implemented");
14615 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14616 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14617 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14618 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14620 llvm_unreachable("Unhandled argument type in LowerVAARG");
14623 if (ArgMode == 2) {
14624 // Sanity Check: Make sure using fp_offset makes sense.
14625 assert(!Subtarget->useSoftFloat() &&
14626 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14627 Attribute::NoImplicitFloat)) &&
14628 Subtarget->hasSSE1());
14631 // Insert VAARG_64 node into the DAG
14632 // VAARG_64 returns two values: Variable Argument Address, Chain
14633 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14634 DAG.getConstant(ArgMode, dl, MVT::i8),
14635 DAG.getConstant(Align, dl, MVT::i32)};
14636 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14637 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14638 VTs, InstOps, MVT::i64,
14639 MachinePointerInfo(SV),
14641 /*Volatile=*/false,
14643 /*WriteMem=*/true);
14644 Chain = VAARG.getValue(1);
14646 // Load the next argument and return it
14647 return DAG.getLoad(ArgVT, dl,
14650 MachinePointerInfo(),
14651 false, false, false, 0);
14654 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14655 SelectionDAG &DAG) {
14656 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14657 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14658 SDValue Chain = Op.getOperand(0);
14659 SDValue DstPtr = Op.getOperand(1);
14660 SDValue SrcPtr = Op.getOperand(2);
14661 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14662 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14665 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14666 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14668 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14671 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14672 // amount is a constant. Takes immediate version of shift as input.
14673 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14674 SDValue SrcOp, uint64_t ShiftAmt,
14675 SelectionDAG &DAG) {
14676 MVT ElementType = VT.getVectorElementType();
14678 // Fold this packed shift into its first operand if ShiftAmt is 0.
14682 // Check for ShiftAmt >= element width
14683 if (ShiftAmt >= ElementType.getSizeInBits()) {
14684 if (Opc == X86ISD::VSRAI)
14685 ShiftAmt = ElementType.getSizeInBits() - 1;
14687 return DAG.getConstant(0, dl, VT);
14690 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14691 && "Unknown target vector shift-by-constant node");
14693 // Fold this packed vector shift into a build vector if SrcOp is a
14694 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14695 if (VT == SrcOp.getSimpleValueType() &&
14696 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14697 SmallVector<SDValue, 8> Elts;
14698 unsigned NumElts = SrcOp->getNumOperands();
14699 ConstantSDNode *ND;
14702 default: llvm_unreachable(nullptr);
14703 case X86ISD::VSHLI:
14704 for (unsigned i=0; i!=NumElts; ++i) {
14705 SDValue CurrentOp = SrcOp->getOperand(i);
14706 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14707 Elts.push_back(CurrentOp);
14710 ND = cast<ConstantSDNode>(CurrentOp);
14711 const APInt &C = ND->getAPIntValue();
14712 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14715 case X86ISD::VSRLI:
14716 for (unsigned i=0; i!=NumElts; ++i) {
14717 SDValue CurrentOp = SrcOp->getOperand(i);
14718 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14719 Elts.push_back(CurrentOp);
14722 ND = cast<ConstantSDNode>(CurrentOp);
14723 const APInt &C = ND->getAPIntValue();
14724 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14727 case X86ISD::VSRAI:
14728 for (unsigned i=0; i!=NumElts; ++i) {
14729 SDValue CurrentOp = SrcOp->getOperand(i);
14730 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14731 Elts.push_back(CurrentOp);
14734 ND = cast<ConstantSDNode>(CurrentOp);
14735 const APInt &C = ND->getAPIntValue();
14736 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14741 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14744 return DAG.getNode(Opc, dl, VT, SrcOp,
14745 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14748 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14749 // may or may not be a constant. Takes immediate version of shift as input.
14750 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14751 SDValue SrcOp, SDValue ShAmt,
14752 SelectionDAG &DAG) {
14753 MVT SVT = ShAmt.getSimpleValueType();
14754 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14756 // Catch shift-by-constant.
14757 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14758 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14759 CShAmt->getZExtValue(), DAG);
14761 // Change opcode to non-immediate version
14763 default: llvm_unreachable("Unknown target vector shift node");
14764 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14765 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14766 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14769 const X86Subtarget &Subtarget =
14770 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14771 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14772 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14773 // Let the shuffle legalizer expand this shift amount node.
14774 SDValue Op0 = ShAmt.getOperand(0);
14775 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14776 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14778 // Need to build a vector containing shift amount.
14779 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14780 SmallVector<SDValue, 4> ShOps;
14781 ShOps.push_back(ShAmt);
14782 if (SVT == MVT::i32) {
14783 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14784 ShOps.push_back(DAG.getUNDEF(SVT));
14786 ShOps.push_back(DAG.getUNDEF(SVT));
14788 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14789 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14792 // The return type has to be a 128-bit type with the same element
14793 // type as the input type.
14794 MVT EltVT = VT.getVectorElementType();
14795 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14797 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14798 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14801 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14802 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14803 /// necessary casting for \p Mask when lowering masking intrinsics.
14804 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14805 SDValue PreservedSrc,
14806 const X86Subtarget *Subtarget,
14807 SelectionDAG &DAG) {
14808 EVT VT = Op.getValueType();
14809 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14810 MVT::i1, VT.getVectorNumElements());
14811 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14812 Mask.getValueType().getSizeInBits());
14815 assert(MaskVT.isSimple() && "invalid mask type");
14817 if (isAllOnes(Mask))
14820 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14821 // are extracted by EXTRACT_SUBVECTOR.
14822 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14823 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14824 DAG.getIntPtrConstant(0, dl));
14826 switch (Op.getOpcode()) {
14828 case X86ISD::PCMPEQM:
14829 case X86ISD::PCMPGTM:
14831 case X86ISD::CMPMU:
14832 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14834 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14835 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14836 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14839 /// \brief Creates an SDNode for a predicated scalar operation.
14840 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14841 /// The mask is comming as MVT::i8 and it should be truncated
14842 /// to MVT::i1 while lowering masking intrinsics.
14843 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14844 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14845 /// a scalar instruction.
14846 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14847 SDValue PreservedSrc,
14848 const X86Subtarget *Subtarget,
14849 SelectionDAG &DAG) {
14850 if (isAllOnes(Mask))
14853 EVT VT = Op.getValueType();
14855 // The mask should be of type MVT::i1
14856 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14858 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14859 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14860 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14863 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14864 SelectionDAG &DAG) {
14866 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14867 EVT VT = Op.getValueType();
14868 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14870 switch(IntrData->Type) {
14871 case INTR_TYPE_1OP:
14872 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14873 case INTR_TYPE_2OP:
14874 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14876 case INTR_TYPE_3OP:
14877 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14878 Op.getOperand(2), Op.getOperand(3));
14879 case INTR_TYPE_1OP_MASK_RM: {
14880 SDValue Src = Op.getOperand(1);
14881 SDValue Src0 = Op.getOperand(2);
14882 SDValue Mask = Op.getOperand(3);
14883 SDValue RoundingMode = Op.getOperand(4);
14884 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14886 Mask, Src0, Subtarget, DAG);
14888 case INTR_TYPE_SCALAR_MASK_RM: {
14889 SDValue Src1 = Op.getOperand(1);
14890 SDValue Src2 = Op.getOperand(2);
14891 SDValue Src0 = Op.getOperand(3);
14892 SDValue Mask = Op.getOperand(4);
14893 // There are 2 kinds of intrinsics in this group:
14894 // (1) With supress-all-exceptions (sae) - 6 operands
14895 // (2) With rounding mode and sae - 7 operands.
14896 if (Op.getNumOperands() == 6) {
14897 SDValue Sae = Op.getOperand(5);
14898 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14900 Mask, Src0, Subtarget, DAG);
14902 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
14903 SDValue RoundingMode = Op.getOperand(5);
14904 SDValue Sae = Op.getOperand(6);
14905 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14906 RoundingMode, Sae),
14907 Mask, Src0, Subtarget, DAG);
14909 case INTR_TYPE_2OP_MASK: {
14910 SDValue Src1 = Op.getOperand(1);
14911 SDValue Src2 = Op.getOperand(2);
14912 SDValue PassThru = Op.getOperand(3);
14913 SDValue Mask = Op.getOperand(4);
14914 // We specify 2 possible opcodes for intrinsics with rounding modes.
14915 // First, we check if the intrinsic may have non-default rounding mode,
14916 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14917 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14918 if (IntrWithRoundingModeOpcode != 0) {
14919 SDValue Rnd = Op.getOperand(5);
14920 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14921 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14922 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14923 dl, Op.getValueType(),
14925 Mask, PassThru, Subtarget, DAG);
14928 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14930 Mask, PassThru, Subtarget, DAG);
14932 case FMA_OP_MASK: {
14933 SDValue Src1 = Op.getOperand(1);
14934 SDValue Src2 = Op.getOperand(2);
14935 SDValue Src3 = Op.getOperand(3);
14936 SDValue Mask = Op.getOperand(4);
14937 // We specify 2 possible opcodes for intrinsics with rounding modes.
14938 // First, we check if the intrinsic may have non-default rounding mode,
14939 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14940 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14941 if (IntrWithRoundingModeOpcode != 0) {
14942 SDValue Rnd = Op.getOperand(5);
14943 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14944 X86::STATIC_ROUNDING::CUR_DIRECTION)
14945 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14946 dl, Op.getValueType(),
14947 Src1, Src2, Src3, Rnd),
14948 Mask, Src1, Subtarget, DAG);
14950 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14951 dl, Op.getValueType(),
14953 Mask, Src1, Subtarget, DAG);
14956 case CMP_MASK_CC: {
14957 // Comparison intrinsics with masks.
14958 // Example of transformation:
14959 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14960 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14962 // (v8i1 (insert_subvector undef,
14963 // (v2i1 (and (PCMPEQM %a, %b),
14964 // (extract_subvector
14965 // (v8i1 (bitcast %mask)), 0))), 0))))
14966 EVT VT = Op.getOperand(1).getValueType();
14967 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14968 VT.getVectorNumElements());
14969 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14970 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14971 Mask.getValueType().getSizeInBits());
14973 if (IntrData->Type == CMP_MASK_CC) {
14974 SDValue CC = Op.getOperand(3);
14975 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
14976 // We specify 2 possible opcodes for intrinsics with rounding modes.
14977 // First, we check if the intrinsic may have non-default rounding mode,
14978 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14979 if (IntrData->Opc1 != 0) {
14980 SDValue Rnd = Op.getOperand(5);
14981 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14982 X86::STATIC_ROUNDING::CUR_DIRECTION)
14983 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
14984 Op.getOperand(2), CC, Rnd);
14986 //default rounding mode
14988 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14989 Op.getOperand(2), CC);
14992 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14993 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14996 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
14997 DAG.getTargetConstant(0, dl,
15000 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15001 DAG.getUNDEF(BitcastVT), CmpMask,
15002 DAG.getIntPtrConstant(0, dl));
15003 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
15005 case COMI: { // Comparison intrinsics
15006 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15007 SDValue LHS = Op.getOperand(1);
15008 SDValue RHS = Op.getOperand(2);
15009 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15010 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15011 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15012 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15013 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15014 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15017 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15018 Op.getOperand(1), Op.getOperand(2), DAG);
15020 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15021 Op.getSimpleValueType(),
15023 Op.getOperand(2), DAG),
15024 Op.getOperand(4), Op.getOperand(3), Subtarget,
15026 case COMPRESS_EXPAND_IN_REG: {
15027 SDValue Mask = Op.getOperand(3);
15028 SDValue DataToCompress = Op.getOperand(1);
15029 SDValue PassThru = Op.getOperand(2);
15030 if (isAllOnes(Mask)) // return data as is
15031 return Op.getOperand(1);
15032 EVT VT = Op.getValueType();
15033 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15034 VT.getVectorNumElements());
15035 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15036 Mask.getValueType().getSizeInBits());
15038 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15039 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15040 DAG.getIntPtrConstant(0, dl));
15042 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15046 SDValue Mask = Op.getOperand(3);
15047 EVT VT = Op.getValueType();
15048 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15049 VT.getVectorNumElements());
15050 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15051 Mask.getValueType().getSizeInBits());
15053 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15054 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15055 DAG.getIntPtrConstant(0, dl));
15056 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15065 default: return SDValue(); // Don't custom lower most intrinsics.
15067 case Intrinsic::x86_avx2_permd:
15068 case Intrinsic::x86_avx2_permps:
15069 // Operands intentionally swapped. Mask is last operand to intrinsic,
15070 // but second operand for node/instruction.
15071 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15072 Op.getOperand(2), Op.getOperand(1));
15074 case Intrinsic::x86_avx512_mask_valign_q_512:
15075 case Intrinsic::x86_avx512_mask_valign_d_512:
15076 // Vector source operands are swapped.
15077 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15078 Op.getValueType(), Op.getOperand(2),
15081 Op.getOperand(5), Op.getOperand(4),
15084 // ptest and testp intrinsics. The intrinsic these come from are designed to
15085 // return an integer value, not just an instruction so lower it to the ptest
15086 // or testp pattern and a setcc for the result.
15087 case Intrinsic::x86_sse41_ptestz:
15088 case Intrinsic::x86_sse41_ptestc:
15089 case Intrinsic::x86_sse41_ptestnzc:
15090 case Intrinsic::x86_avx_ptestz_256:
15091 case Intrinsic::x86_avx_ptestc_256:
15092 case Intrinsic::x86_avx_ptestnzc_256:
15093 case Intrinsic::x86_avx_vtestz_ps:
15094 case Intrinsic::x86_avx_vtestc_ps:
15095 case Intrinsic::x86_avx_vtestnzc_ps:
15096 case Intrinsic::x86_avx_vtestz_pd:
15097 case Intrinsic::x86_avx_vtestc_pd:
15098 case Intrinsic::x86_avx_vtestnzc_pd:
15099 case Intrinsic::x86_avx_vtestz_ps_256:
15100 case Intrinsic::x86_avx_vtestc_ps_256:
15101 case Intrinsic::x86_avx_vtestnzc_ps_256:
15102 case Intrinsic::x86_avx_vtestz_pd_256:
15103 case Intrinsic::x86_avx_vtestc_pd_256:
15104 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15105 bool IsTestPacked = false;
15108 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15109 case Intrinsic::x86_avx_vtestz_ps:
15110 case Intrinsic::x86_avx_vtestz_pd:
15111 case Intrinsic::x86_avx_vtestz_ps_256:
15112 case Intrinsic::x86_avx_vtestz_pd_256:
15113 IsTestPacked = true; // Fallthrough
15114 case Intrinsic::x86_sse41_ptestz:
15115 case Intrinsic::x86_avx_ptestz_256:
15117 X86CC = X86::COND_E;
15119 case Intrinsic::x86_avx_vtestc_ps:
15120 case Intrinsic::x86_avx_vtestc_pd:
15121 case Intrinsic::x86_avx_vtestc_ps_256:
15122 case Intrinsic::x86_avx_vtestc_pd_256:
15123 IsTestPacked = true; // Fallthrough
15124 case Intrinsic::x86_sse41_ptestc:
15125 case Intrinsic::x86_avx_ptestc_256:
15127 X86CC = X86::COND_B;
15129 case Intrinsic::x86_avx_vtestnzc_ps:
15130 case Intrinsic::x86_avx_vtestnzc_pd:
15131 case Intrinsic::x86_avx_vtestnzc_ps_256:
15132 case Intrinsic::x86_avx_vtestnzc_pd_256:
15133 IsTestPacked = true; // Fallthrough
15134 case Intrinsic::x86_sse41_ptestnzc:
15135 case Intrinsic::x86_avx_ptestnzc_256:
15137 X86CC = X86::COND_A;
15141 SDValue LHS = Op.getOperand(1);
15142 SDValue RHS = Op.getOperand(2);
15143 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15144 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15145 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15146 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15147 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15149 case Intrinsic::x86_avx512_kortestz_w:
15150 case Intrinsic::x86_avx512_kortestc_w: {
15151 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15152 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15153 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15154 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15155 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15156 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15157 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15160 case Intrinsic::x86_sse42_pcmpistria128:
15161 case Intrinsic::x86_sse42_pcmpestria128:
15162 case Intrinsic::x86_sse42_pcmpistric128:
15163 case Intrinsic::x86_sse42_pcmpestric128:
15164 case Intrinsic::x86_sse42_pcmpistrio128:
15165 case Intrinsic::x86_sse42_pcmpestrio128:
15166 case Intrinsic::x86_sse42_pcmpistris128:
15167 case Intrinsic::x86_sse42_pcmpestris128:
15168 case Intrinsic::x86_sse42_pcmpistriz128:
15169 case Intrinsic::x86_sse42_pcmpestriz128: {
15173 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15174 case Intrinsic::x86_sse42_pcmpistria128:
15175 Opcode = X86ISD::PCMPISTRI;
15176 X86CC = X86::COND_A;
15178 case Intrinsic::x86_sse42_pcmpestria128:
15179 Opcode = X86ISD::PCMPESTRI;
15180 X86CC = X86::COND_A;
15182 case Intrinsic::x86_sse42_pcmpistric128:
15183 Opcode = X86ISD::PCMPISTRI;
15184 X86CC = X86::COND_B;
15186 case Intrinsic::x86_sse42_pcmpestric128:
15187 Opcode = X86ISD::PCMPESTRI;
15188 X86CC = X86::COND_B;
15190 case Intrinsic::x86_sse42_pcmpistrio128:
15191 Opcode = X86ISD::PCMPISTRI;
15192 X86CC = X86::COND_O;
15194 case Intrinsic::x86_sse42_pcmpestrio128:
15195 Opcode = X86ISD::PCMPESTRI;
15196 X86CC = X86::COND_O;
15198 case Intrinsic::x86_sse42_pcmpistris128:
15199 Opcode = X86ISD::PCMPISTRI;
15200 X86CC = X86::COND_S;
15202 case Intrinsic::x86_sse42_pcmpestris128:
15203 Opcode = X86ISD::PCMPESTRI;
15204 X86CC = X86::COND_S;
15206 case Intrinsic::x86_sse42_pcmpistriz128:
15207 Opcode = X86ISD::PCMPISTRI;
15208 X86CC = X86::COND_E;
15210 case Intrinsic::x86_sse42_pcmpestriz128:
15211 Opcode = X86ISD::PCMPESTRI;
15212 X86CC = X86::COND_E;
15215 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15216 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15217 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15218 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15219 DAG.getConstant(X86CC, dl, MVT::i8),
15220 SDValue(PCMP.getNode(), 1));
15221 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15224 case Intrinsic::x86_sse42_pcmpistri128:
15225 case Intrinsic::x86_sse42_pcmpestri128: {
15227 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15228 Opcode = X86ISD::PCMPISTRI;
15230 Opcode = X86ISD::PCMPESTRI;
15232 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15233 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15234 return DAG.getNode(Opcode, dl, VTs, NewOps);
15239 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15240 SDValue Src, SDValue Mask, SDValue Base,
15241 SDValue Index, SDValue ScaleOp, SDValue Chain,
15242 const X86Subtarget * Subtarget) {
15244 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15245 assert(C && "Invalid scale type");
15246 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15247 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15248 Index.getSimpleValueType().getVectorNumElements());
15250 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15252 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15254 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15255 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15256 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15257 SDValue Segment = DAG.getRegister(0, MVT::i32);
15258 if (Src.getOpcode() == ISD::UNDEF)
15259 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15260 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15261 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15262 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15263 return DAG.getMergeValues(RetOps, dl);
15266 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15267 SDValue Src, SDValue Mask, SDValue Base,
15268 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15270 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15271 assert(C && "Invalid scale type");
15272 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15273 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15274 SDValue Segment = DAG.getRegister(0, MVT::i32);
15275 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15276 Index.getSimpleValueType().getVectorNumElements());
15278 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15280 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15282 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15283 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15284 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15285 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15286 return SDValue(Res, 1);
15289 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15290 SDValue Mask, SDValue Base, SDValue Index,
15291 SDValue ScaleOp, SDValue Chain) {
15293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15294 assert(C && "Invalid scale type");
15295 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15296 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15297 SDValue Segment = DAG.getRegister(0, MVT::i32);
15299 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15301 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15303 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15305 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15306 //SDVTList VTs = DAG.getVTList(MVT::Other);
15307 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15308 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15309 return SDValue(Res, 0);
15312 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15313 // read performance monitor counters (x86_rdpmc).
15314 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15315 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15316 SmallVectorImpl<SDValue> &Results) {
15317 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15318 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15321 // The ECX register is used to select the index of the performance counter
15323 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15325 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15327 // Reads the content of a 64-bit performance counter and returns it in the
15328 // registers EDX:EAX.
15329 if (Subtarget->is64Bit()) {
15330 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15331 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15334 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15335 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15338 Chain = HI.getValue(1);
15340 if (Subtarget->is64Bit()) {
15341 // The EAX register is loaded with the low-order 32 bits. The EDX register
15342 // is loaded with the supported high-order bits of the counter.
15343 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15344 DAG.getConstant(32, DL, MVT::i8));
15345 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15346 Results.push_back(Chain);
15350 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15351 SDValue Ops[] = { LO, HI };
15352 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15353 Results.push_back(Pair);
15354 Results.push_back(Chain);
15357 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15358 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15359 // also used to custom lower READCYCLECOUNTER nodes.
15360 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15361 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15362 SmallVectorImpl<SDValue> &Results) {
15363 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15364 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15367 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15368 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15369 // and the EAX register is loaded with the low-order 32 bits.
15370 if (Subtarget->is64Bit()) {
15371 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15372 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15375 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15376 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15379 SDValue Chain = HI.getValue(1);
15381 if (Opcode == X86ISD::RDTSCP_DAG) {
15382 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15384 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15385 // the ECX register. Add 'ecx' explicitly to the chain.
15386 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15388 // Explicitly store the content of ECX at the location passed in input
15389 // to the 'rdtscp' intrinsic.
15390 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15391 MachinePointerInfo(), false, false, 0);
15394 if (Subtarget->is64Bit()) {
15395 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15396 // the EAX register is loaded with the low-order 32 bits.
15397 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15398 DAG.getConstant(32, DL, MVT::i8));
15399 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15400 Results.push_back(Chain);
15404 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15405 SDValue Ops[] = { LO, HI };
15406 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15407 Results.push_back(Pair);
15408 Results.push_back(Chain);
15411 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15412 SelectionDAG &DAG) {
15413 SmallVector<SDValue, 2> Results;
15415 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15417 return DAG.getMergeValues(Results, DL);
15421 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15422 SelectionDAG &DAG) {
15423 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15425 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15430 switch(IntrData->Type) {
15432 llvm_unreachable("Unknown Intrinsic Type");
15436 // Emit the node with the right value type.
15437 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15438 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15440 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15441 // Otherwise return the value from Rand, which is always 0, casted to i32.
15442 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15443 DAG.getConstant(1, dl, Op->getValueType(1)),
15444 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15445 SDValue(Result.getNode(), 1) };
15446 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15447 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15450 // Return { result, isValid, chain }.
15451 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15452 SDValue(Result.getNode(), 2));
15455 //gather(v1, mask, index, base, scale);
15456 SDValue Chain = Op.getOperand(0);
15457 SDValue Src = Op.getOperand(2);
15458 SDValue Base = Op.getOperand(3);
15459 SDValue Index = Op.getOperand(4);
15460 SDValue Mask = Op.getOperand(5);
15461 SDValue Scale = Op.getOperand(6);
15462 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15466 //scatter(base, mask, index, v1, scale);
15467 SDValue Chain = Op.getOperand(0);
15468 SDValue Base = Op.getOperand(2);
15469 SDValue Mask = Op.getOperand(3);
15470 SDValue Index = Op.getOperand(4);
15471 SDValue Src = Op.getOperand(5);
15472 SDValue Scale = Op.getOperand(6);
15473 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15477 SDValue Hint = Op.getOperand(6);
15478 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15479 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15480 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15481 SDValue Chain = Op.getOperand(0);
15482 SDValue Mask = Op.getOperand(2);
15483 SDValue Index = Op.getOperand(3);
15484 SDValue Base = Op.getOperand(4);
15485 SDValue Scale = Op.getOperand(5);
15486 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15488 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15490 SmallVector<SDValue, 2> Results;
15491 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15493 return DAG.getMergeValues(Results, dl);
15495 // Read Performance Monitoring Counters.
15497 SmallVector<SDValue, 2> Results;
15498 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15499 return DAG.getMergeValues(Results, dl);
15501 // XTEST intrinsics.
15503 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15504 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15505 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15506 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15508 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15509 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15510 Ret, SDValue(InTrans.getNode(), 1));
15514 SmallVector<SDValue, 2> Results;
15515 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15516 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15517 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15518 DAG.getConstant(-1, dl, MVT::i8));
15519 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15520 Op.getOperand(4), GenCF.getValue(1));
15521 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15522 Op.getOperand(5), MachinePointerInfo(),
15524 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15525 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15527 Results.push_back(SetCC);
15528 Results.push_back(Store);
15529 return DAG.getMergeValues(Results, dl);
15531 case COMPRESS_TO_MEM: {
15533 SDValue Mask = Op.getOperand(4);
15534 SDValue DataToCompress = Op.getOperand(3);
15535 SDValue Addr = Op.getOperand(2);
15536 SDValue Chain = Op.getOperand(0);
15538 if (isAllOnes(Mask)) // return just a store
15539 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15540 MachinePointerInfo(), false, false, 0);
15542 EVT VT = DataToCompress.getValueType();
15543 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15544 VT.getVectorNumElements());
15545 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15546 Mask.getValueType().getSizeInBits());
15547 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15548 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15549 DAG.getIntPtrConstant(0, dl));
15551 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15552 DataToCompress, DAG.getUNDEF(VT));
15553 return DAG.getStore(Chain, dl, Compressed, Addr,
15554 MachinePointerInfo(), false, false, 0);
15556 case EXPAND_FROM_MEM: {
15558 SDValue Mask = Op.getOperand(4);
15559 SDValue PathThru = Op.getOperand(3);
15560 SDValue Addr = Op.getOperand(2);
15561 SDValue Chain = Op.getOperand(0);
15562 EVT VT = Op.getValueType();
15564 if (isAllOnes(Mask)) // return just a load
15565 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15567 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15568 VT.getVectorNumElements());
15569 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15570 Mask.getValueType().getSizeInBits());
15571 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15572 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15573 DAG.getIntPtrConstant(0, dl));
15575 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15576 false, false, false, 0);
15578 SDValue Results[] = {
15579 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15581 return DAG.getMergeValues(Results, dl);
15586 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15587 SelectionDAG &DAG) const {
15588 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15589 MFI->setReturnAddressIsTaken(true);
15591 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15594 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15596 EVT PtrVT = getPointerTy();
15599 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15600 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15601 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15602 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15603 DAG.getNode(ISD::ADD, dl, PtrVT,
15604 FrameAddr, Offset),
15605 MachinePointerInfo(), false, false, false, 0);
15608 // Just load the return address.
15609 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15610 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15611 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15614 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15615 MachineFunction &MF = DAG.getMachineFunction();
15616 MachineFrameInfo *MFI = MF.getFrameInfo();
15617 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15618 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15619 EVT VT = Op.getValueType();
15621 MFI->setFrameAddressIsTaken(true);
15623 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15624 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15625 // is not possible to crawl up the stack without looking at the unwind codes
15627 int FrameAddrIndex = FuncInfo->getFAIndex();
15628 if (!FrameAddrIndex) {
15629 // Set up a frame object for the return address.
15630 unsigned SlotSize = RegInfo->getSlotSize();
15631 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15632 SlotSize, /*Offset=*/INT64_MIN, /*IsImmutable=*/false);
15633 FuncInfo->setFAIndex(FrameAddrIndex);
15635 return DAG.getFrameIndex(FrameAddrIndex, VT);
15638 unsigned FrameReg =
15639 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15640 SDLoc dl(Op); // FIXME probably not meaningful
15641 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15642 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15643 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15644 "Invalid Frame Register!");
15645 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15647 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15648 MachinePointerInfo(),
15649 false, false, false, 0);
15653 // FIXME? Maybe this could be a TableGen attribute on some registers and
15654 // this table could be generated automatically from RegInfo.
15655 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15657 unsigned Reg = StringSwitch<unsigned>(RegName)
15658 .Case("esp", X86::ESP)
15659 .Case("rsp", X86::RSP)
15663 report_fatal_error("Invalid register name global variable");
15666 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15667 SelectionDAG &DAG) const {
15668 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15669 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15672 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15673 SDValue Chain = Op.getOperand(0);
15674 SDValue Offset = Op.getOperand(1);
15675 SDValue Handler = Op.getOperand(2);
15678 EVT PtrVT = getPointerTy();
15679 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15680 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15681 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15682 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15683 "Invalid Frame Register!");
15684 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15685 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15687 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15688 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15690 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15691 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15693 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15695 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15696 DAG.getRegister(StoreAddrReg, PtrVT));
15699 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15700 SelectionDAG &DAG) const {
15702 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15703 DAG.getVTList(MVT::i32, MVT::Other),
15704 Op.getOperand(0), Op.getOperand(1));
15707 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15708 SelectionDAG &DAG) const {
15710 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15711 Op.getOperand(0), Op.getOperand(1));
15714 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15715 return Op.getOperand(0);
15718 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15719 SelectionDAG &DAG) const {
15720 SDValue Root = Op.getOperand(0);
15721 SDValue Trmp = Op.getOperand(1); // trampoline
15722 SDValue FPtr = Op.getOperand(2); // nested function
15723 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15726 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15727 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15729 if (Subtarget->is64Bit()) {
15730 SDValue OutChains[6];
15732 // Large code-model.
15733 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15734 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15736 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15737 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15739 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15741 // Load the pointer to the nested function into R11.
15742 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15743 SDValue Addr = Trmp;
15744 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15745 Addr, MachinePointerInfo(TrmpAddr),
15748 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15749 DAG.getConstant(2, dl, MVT::i64));
15750 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15751 MachinePointerInfo(TrmpAddr, 2),
15754 // Load the 'nest' parameter value into R10.
15755 // R10 is specified in X86CallingConv.td
15756 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15757 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15758 DAG.getConstant(10, dl, MVT::i64));
15759 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15760 Addr, MachinePointerInfo(TrmpAddr, 10),
15763 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15764 DAG.getConstant(12, dl, MVT::i64));
15765 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15766 MachinePointerInfo(TrmpAddr, 12),
15769 // Jump to the nested function.
15770 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15771 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15772 DAG.getConstant(20, dl, MVT::i64));
15773 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15774 Addr, MachinePointerInfo(TrmpAddr, 20),
15777 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15778 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15779 DAG.getConstant(22, dl, MVT::i64));
15780 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
15781 Addr, MachinePointerInfo(TrmpAddr, 22),
15784 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15786 const Function *Func =
15787 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15788 CallingConv::ID CC = Func->getCallingConv();
15793 llvm_unreachable("Unsupported calling convention");
15794 case CallingConv::C:
15795 case CallingConv::X86_StdCall: {
15796 // Pass 'nest' parameter in ECX.
15797 // Must be kept in sync with X86CallingConv.td
15798 NestReg = X86::ECX;
15800 // Check that ECX wasn't needed by an 'inreg' parameter.
15801 FunctionType *FTy = Func->getFunctionType();
15802 const AttributeSet &Attrs = Func->getAttributes();
15804 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15805 unsigned InRegCount = 0;
15808 for (FunctionType::param_iterator I = FTy->param_begin(),
15809 E = FTy->param_end(); I != E; ++I, ++Idx)
15810 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15811 // FIXME: should only count parameters that are lowered to integers.
15812 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15814 if (InRegCount > 2) {
15815 report_fatal_error("Nest register in use - reduce number of inreg"
15821 case CallingConv::X86_FastCall:
15822 case CallingConv::X86_ThisCall:
15823 case CallingConv::Fast:
15824 // Pass 'nest' parameter in EAX.
15825 // Must be kept in sync with X86CallingConv.td
15826 NestReg = X86::EAX;
15830 SDValue OutChains[4];
15831 SDValue Addr, Disp;
15833 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15834 DAG.getConstant(10, dl, MVT::i32));
15835 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15837 // This is storing the opcode for MOV32ri.
15838 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15839 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15840 OutChains[0] = DAG.getStore(Root, dl,
15841 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
15842 Trmp, MachinePointerInfo(TrmpAddr),
15845 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15846 DAG.getConstant(1, dl, MVT::i32));
15847 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15848 MachinePointerInfo(TrmpAddr, 1),
15851 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15852 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15853 DAG.getConstant(5, dl, MVT::i32));
15854 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
15855 Addr, MachinePointerInfo(TrmpAddr, 5),
15858 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15859 DAG.getConstant(6, dl, MVT::i32));
15860 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15861 MachinePointerInfo(TrmpAddr, 6),
15864 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15868 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15869 SelectionDAG &DAG) const {
15871 The rounding mode is in bits 11:10 of FPSR, and has the following
15873 00 Round to nearest
15878 FLT_ROUNDS, on the other hand, expects the following:
15885 To perform the conversion, we do:
15886 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15889 MachineFunction &MF = DAG.getMachineFunction();
15890 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15891 unsigned StackAlignment = TFI.getStackAlignment();
15892 MVT VT = Op.getSimpleValueType();
15895 // Save FP Control Word to stack slot
15896 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15897 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15899 MachineMemOperand *MMO =
15900 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15901 MachineMemOperand::MOStore, 2, 2);
15903 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15904 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15905 DAG.getVTList(MVT::Other),
15906 Ops, MVT::i16, MMO);
15908 // Load FP Control Word from stack slot
15909 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15910 MachinePointerInfo(), false, false, false, 0);
15912 // Transform as necessary
15914 DAG.getNode(ISD::SRL, DL, MVT::i16,
15915 DAG.getNode(ISD::AND, DL, MVT::i16,
15916 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
15917 DAG.getConstant(11, DL, MVT::i8));
15919 DAG.getNode(ISD::SRL, DL, MVT::i16,
15920 DAG.getNode(ISD::AND, DL, MVT::i16,
15921 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
15922 DAG.getConstant(9, DL, MVT::i8));
15925 DAG.getNode(ISD::AND, DL, MVT::i16,
15926 DAG.getNode(ISD::ADD, DL, MVT::i16,
15927 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15928 DAG.getConstant(1, DL, MVT::i16)),
15929 DAG.getConstant(3, DL, MVT::i16));
15931 return DAG.getNode((VT.getSizeInBits() < 16 ?
15932 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15935 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15936 MVT VT = Op.getSimpleValueType();
15938 unsigned NumBits = VT.getSizeInBits();
15941 Op = Op.getOperand(0);
15942 if (VT == MVT::i8) {
15943 // Zero extend to i32 since there is not an i8 bsr.
15945 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15948 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15949 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15950 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15952 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15955 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
15956 DAG.getConstant(X86::COND_E, dl, MVT::i8),
15959 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15961 // Finally xor with NumBits-1.
15962 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
15963 DAG.getConstant(NumBits - 1, dl, OpVT));
15966 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15970 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15971 MVT VT = Op.getSimpleValueType();
15973 unsigned NumBits = VT.getSizeInBits();
15976 Op = Op.getOperand(0);
15977 if (VT == MVT::i8) {
15978 // Zero extend to i32 since there is not an i8 bsr.
15980 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15983 // Issue a bsr (scan bits in reverse).
15984 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15985 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15987 // And xor with NumBits-1.
15988 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
15989 DAG.getConstant(NumBits - 1, dl, OpVT));
15992 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15996 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15997 MVT VT = Op.getSimpleValueType();
15998 unsigned NumBits = VT.getSizeInBits();
16000 Op = Op.getOperand(0);
16002 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16003 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16004 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16006 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16009 DAG.getConstant(NumBits, dl, VT),
16010 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16013 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16016 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16017 // ones, and then concatenate the result back.
16018 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16019 MVT VT = Op.getSimpleValueType();
16021 assert(VT.is256BitVector() && VT.isInteger() &&
16022 "Unsupported value type for operation");
16024 unsigned NumElems = VT.getVectorNumElements();
16027 // Extract the LHS vectors
16028 SDValue LHS = Op.getOperand(0);
16029 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16030 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16032 // Extract the RHS vectors
16033 SDValue RHS = Op.getOperand(1);
16034 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16035 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16037 MVT EltVT = VT.getVectorElementType();
16038 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16040 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16041 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16042 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16045 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16046 assert(Op.getSimpleValueType().is256BitVector() &&
16047 Op.getSimpleValueType().isInteger() &&
16048 "Only handle AVX 256-bit vector integer operation");
16049 return Lower256IntArith(Op, DAG);
16052 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16053 assert(Op.getSimpleValueType().is256BitVector() &&
16054 Op.getSimpleValueType().isInteger() &&
16055 "Only handle AVX 256-bit vector integer operation");
16056 return Lower256IntArith(Op, DAG);
16059 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16060 SelectionDAG &DAG) {
16062 MVT VT = Op.getSimpleValueType();
16064 // Decompose 256-bit ops into smaller 128-bit ops.
16065 if (VT.is256BitVector() && !Subtarget->hasInt256())
16066 return Lower256IntArith(Op, DAG);
16068 SDValue A = Op.getOperand(0);
16069 SDValue B = Op.getOperand(1);
16071 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16072 // pairs, multiply and truncate.
16073 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16074 if (Subtarget->hasInt256()) {
16075 if (VT == MVT::v32i8) {
16076 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16077 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16078 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16079 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16080 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16081 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16082 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16083 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16084 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16085 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16088 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16089 return DAG.getNode(
16090 ISD::TRUNCATE, dl, VT,
16091 DAG.getNode(ISD::MUL, dl, ExVT,
16092 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16093 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16096 assert(VT == MVT::v16i8 &&
16097 "Pre-AVX2 support only supports v16i8 multiplication");
16098 MVT ExVT = MVT::v8i16;
16100 // Extract the lo parts and sign extend to i16
16102 if (Subtarget->hasSSE41()) {
16103 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16104 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16106 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16107 -1, 4, -1, 5, -1, 6, -1, 7};
16108 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16109 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16110 ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);
16111 BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);
16112 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16113 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16116 // Extract the hi parts and sign extend to i16
16118 if (Subtarget->hasSSE41()) {
16119 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16120 -1, -1, -1, -1, -1, -1, -1, -1};
16121 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16122 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16123 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16124 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16126 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16127 -1, 12, -1, 13, -1, 14, -1, 15};
16128 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16129 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16130 AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);
16131 BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);
16132 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16133 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16136 // Multiply, mask the lower 8bits of the lo/hi results and pack
16137 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16138 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16139 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16140 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16141 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16144 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16145 if (VT == MVT::v4i32) {
16146 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16147 "Should not custom lower when pmuldq is available!");
16149 // Extract the odd parts.
16150 static const int UnpackMask[] = { 1, -1, 3, -1 };
16151 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16152 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16154 // Multiply the even parts.
16155 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16156 // Now multiply odd parts.
16157 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16159 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16160 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16162 // Merge the two vectors back together with a shuffle. This expands into 2
16164 static const int ShufMask[] = { 0, 4, 2, 6 };
16165 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16168 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16169 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16171 // Ahi = psrlqi(a, 32);
16172 // Bhi = psrlqi(b, 32);
16174 // AloBlo = pmuludq(a, b);
16175 // AloBhi = pmuludq(a, Bhi);
16176 // AhiBlo = pmuludq(Ahi, b);
16178 // AloBhi = psllqi(AloBhi, 32);
16179 // AhiBlo = psllqi(AhiBlo, 32);
16180 // return AloBlo + AloBhi + AhiBlo;
16182 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16183 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16185 // Bit cast to 32-bit vectors for MULUDQ
16186 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16187 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16188 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16189 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16190 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16191 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16193 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16194 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16195 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16197 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16198 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16200 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16201 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16204 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16205 assert(Subtarget->isTargetWin64() && "Unexpected target");
16206 EVT VT = Op.getValueType();
16207 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16208 "Unexpected return type for lowering");
16212 switch (Op->getOpcode()) {
16213 default: llvm_unreachable("Unexpected request for libcall!");
16214 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16215 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16216 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16217 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16218 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16219 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16223 SDValue InChain = DAG.getEntryNode();
16225 TargetLowering::ArgListTy Args;
16226 TargetLowering::ArgListEntry Entry;
16227 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16228 EVT ArgVT = Op->getOperand(i).getValueType();
16229 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16230 "Unexpected argument type for lowering");
16231 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16232 Entry.Node = StackPtr;
16233 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16235 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16236 Entry.Ty = PointerType::get(ArgTy,0);
16237 Entry.isSExt = false;
16238 Entry.isZExt = false;
16239 Args.push_back(Entry);
16242 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16245 TargetLowering::CallLoweringInfo CLI(DAG);
16246 CLI.setDebugLoc(dl).setChain(InChain)
16247 .setCallee(getLibcallCallingConv(LC),
16248 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16249 Callee, std::move(Args), 0)
16250 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16252 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16253 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16256 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16257 SelectionDAG &DAG) {
16258 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16259 EVT VT = Op0.getValueType();
16262 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16263 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16265 // PMULxD operations multiply each even value (starting at 0) of LHS with
16266 // the related value of RHS and produce a widen result.
16267 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16268 // => <2 x i64> <ae|cg>
16270 // In other word, to have all the results, we need to perform two PMULxD:
16271 // 1. one with the even values.
16272 // 2. one with the odd values.
16273 // To achieve #2, with need to place the odd values at an even position.
16275 // Place the odd value at an even position (basically, shift all values 1
16276 // step to the left):
16277 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16278 // <a|b|c|d> => <b|undef|d|undef>
16279 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16280 // <e|f|g|h> => <f|undef|h|undef>
16281 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16283 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16285 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16286 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16288 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16289 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16290 // => <2 x i64> <ae|cg>
16291 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16292 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16293 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16294 // => <2 x i64> <bf|dh>
16295 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16296 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16298 // Shuffle it back into the right order.
16299 SDValue Highs, Lows;
16300 if (VT == MVT::v8i32) {
16301 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16302 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16303 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16304 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16306 const int HighMask[] = {1, 5, 3, 7};
16307 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16308 const int LowMask[] = {0, 4, 2, 6};
16309 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16312 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16313 // unsigned multiply.
16314 if (IsSigned && !Subtarget->hasSSE41()) {
16316 DAG.getConstant(31, dl,
16317 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16318 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16319 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16320 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16321 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16323 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16324 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16327 // The first result of MUL_LOHI is actually the low value, followed by the
16329 SDValue Ops[] = {Lows, Highs};
16330 return DAG.getMergeValues(Ops, dl);
16333 // Return true if the requred (according to Opcode) shift-imm form is natively
16334 // supported by the Subtarget
16335 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16337 if (VT.getScalarSizeInBits() < 16)
16340 if (VT.is512BitVector() &&
16341 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16344 bool LShift = VT.is128BitVector() ||
16345 (VT.is256BitVector() && Subtarget->hasInt256());
16347 bool AShift = LShift && (Subtarget->hasVLX() ||
16348 (VT != MVT::v2i64 && VT != MVT::v4i64));
16349 return (Opcode == ISD::SRA) ? AShift : LShift;
16352 // The shift amount is a variable, but it is the same for all vector lanes.
16353 // These instrcutions are defined together with shift-immediate.
16355 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16357 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16360 // Return true if the requred (according to Opcode) variable-shift form is
16361 // natively supported by the Subtarget
16362 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16365 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16368 // vXi16 supported only on AVX-512, BWI
16369 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16372 if (VT.is512BitVector() || Subtarget->hasVLX())
16375 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16376 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16377 return (Opcode == ISD::SRA) ? AShift : LShift;
16380 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16381 const X86Subtarget *Subtarget) {
16382 MVT VT = Op.getSimpleValueType();
16384 SDValue R = Op.getOperand(0);
16385 SDValue Amt = Op.getOperand(1);
16387 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16388 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16390 // Optimize shl/srl/sra with constant shift amount.
16391 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16392 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16393 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16395 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16396 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16398 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16399 unsigned NumElts = VT.getVectorNumElements();
16400 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16402 if (Op.getOpcode() == ISD::SHL) {
16403 // Make a large shift.
16404 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16406 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16407 // Zero out the rightmost bits.
16408 SmallVector<SDValue, 32> V(
16409 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16410 return DAG.getNode(ISD::AND, dl, VT, SHL,
16411 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16413 if (Op.getOpcode() == ISD::SRL) {
16414 // Make a large shift.
16415 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16417 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16418 // Zero out the leftmost bits.
16419 SmallVector<SDValue, 32> V(
16420 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16421 return DAG.getNode(ISD::AND, dl, VT, SRL,
16422 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16424 if (Op.getOpcode() == ISD::SRA) {
16425 if (ShiftAmt == 7) {
16426 // R s>> 7 === R s< 0
16427 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16428 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16431 // R s>> a === ((R u>> a) ^ m) - m
16432 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16433 SmallVector<SDValue, 32> V(NumElts,
16434 DAG.getConstant(128 >> ShiftAmt, dl,
16436 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16437 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16438 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16441 llvm_unreachable("Unknown shift opcode.");
16446 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16447 if (!Subtarget->is64Bit() &&
16448 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16449 Amt.getOpcode() == ISD::BITCAST &&
16450 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16451 Amt = Amt.getOperand(0);
16452 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16453 VT.getVectorNumElements();
16454 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16455 uint64_t ShiftAmt = 0;
16456 for (unsigned i = 0; i != Ratio; ++i) {
16457 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16461 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16463 // Check remaining shift amounts.
16464 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16465 uint64_t ShAmt = 0;
16466 for (unsigned j = 0; j != Ratio; ++j) {
16467 ConstantSDNode *C =
16468 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16472 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16474 if (ShAmt != ShiftAmt)
16477 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16483 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16484 const X86Subtarget* Subtarget) {
16485 MVT VT = Op.getSimpleValueType();
16487 SDValue R = Op.getOperand(0);
16488 SDValue Amt = Op.getOperand(1);
16490 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16491 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16493 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16494 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16496 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16498 EVT EltVT = VT.getVectorElementType();
16500 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16501 // Check if this build_vector node is doing a splat.
16502 // If so, then set BaseShAmt equal to the splat value.
16503 BaseShAmt = BV->getSplatValue();
16504 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16505 BaseShAmt = SDValue();
16507 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16508 Amt = Amt.getOperand(0);
16510 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16511 if (SVN && SVN->isSplat()) {
16512 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16513 SDValue InVec = Amt.getOperand(0);
16514 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16515 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16516 "Unexpected shuffle index found!");
16517 BaseShAmt = InVec.getOperand(SplatIdx);
16518 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16519 if (ConstantSDNode *C =
16520 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16521 if (C->getZExtValue() == SplatIdx)
16522 BaseShAmt = InVec.getOperand(1);
16527 // Avoid introducing an extract element from a shuffle.
16528 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16529 DAG.getIntPtrConstant(SplatIdx, dl));
16533 if (BaseShAmt.getNode()) {
16534 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16535 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16536 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16537 else if (EltVT.bitsLT(MVT::i32))
16538 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16540 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16544 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16545 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16546 Amt.getOpcode() == ISD::BITCAST &&
16547 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16548 Amt = Amt.getOperand(0);
16549 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16550 VT.getVectorNumElements();
16551 std::vector<SDValue> Vals(Ratio);
16552 for (unsigned i = 0; i != Ratio; ++i)
16553 Vals[i] = Amt.getOperand(i);
16554 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16555 for (unsigned j = 0; j != Ratio; ++j)
16556 if (Vals[j] != Amt.getOperand(i + j))
16559 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16564 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16565 SelectionDAG &DAG) {
16566 MVT VT = Op.getSimpleValueType();
16568 SDValue R = Op.getOperand(0);
16569 SDValue Amt = Op.getOperand(1);
16571 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16572 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16574 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16577 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16580 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16583 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16584 // shifts per-lane and then shuffle the partial results back together.
16585 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16586 // Splat the shift amounts so the scalar shifts above will catch it.
16587 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16588 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16589 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16590 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16591 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16594 // If possible, lower this packed shift into a vector multiply instead of
16595 // expanding it into a sequence of scalar shifts.
16596 // Do this only if the vector shift count is a constant build_vector.
16597 if (Op.getOpcode() == ISD::SHL &&
16598 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16599 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16600 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16601 SmallVector<SDValue, 8> Elts;
16602 EVT SVT = VT.getScalarType();
16603 unsigned SVTBits = SVT.getSizeInBits();
16604 const APInt &One = APInt(SVTBits, 1);
16605 unsigned NumElems = VT.getVectorNumElements();
16607 for (unsigned i=0; i !=NumElems; ++i) {
16608 SDValue Op = Amt->getOperand(i);
16609 if (Op->getOpcode() == ISD::UNDEF) {
16610 Elts.push_back(Op);
16614 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16615 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16616 uint64_t ShAmt = C.getZExtValue();
16617 if (ShAmt >= SVTBits) {
16618 Elts.push_back(DAG.getUNDEF(SVT));
16621 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16623 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16624 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16627 // Lower SHL with variable shift amount.
16628 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16629 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16631 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16632 DAG.getConstant(0x3f800000U, dl, VT));
16633 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16634 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16635 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16638 // If possible, lower this shift as a sequence of two shifts by
16639 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16641 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16643 // Could be rewritten as:
16644 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16646 // The advantage is that the two shifts from the example would be
16647 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16648 // the vector shift into four scalar shifts plus four pairs of vector
16650 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16651 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16652 unsigned TargetOpcode = X86ISD::MOVSS;
16653 bool CanBeSimplified;
16654 // The splat value for the first packed shift (the 'X' from the example).
16655 SDValue Amt1 = Amt->getOperand(0);
16656 // The splat value for the second packed shift (the 'Y' from the example).
16657 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16658 Amt->getOperand(2);
16660 // See if it is possible to replace this node with a sequence of
16661 // two shifts followed by a MOVSS/MOVSD
16662 if (VT == MVT::v4i32) {
16663 // Check if it is legal to use a MOVSS.
16664 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16665 Amt2 == Amt->getOperand(3);
16666 if (!CanBeSimplified) {
16667 // Otherwise, check if we can still simplify this node using a MOVSD.
16668 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16669 Amt->getOperand(2) == Amt->getOperand(3);
16670 TargetOpcode = X86ISD::MOVSD;
16671 Amt2 = Amt->getOperand(2);
16674 // Do similar checks for the case where the machine value type
16676 CanBeSimplified = Amt1 == Amt->getOperand(1);
16677 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16678 CanBeSimplified = Amt2 == Amt->getOperand(i);
16680 if (!CanBeSimplified) {
16681 TargetOpcode = X86ISD::MOVSD;
16682 CanBeSimplified = true;
16683 Amt2 = Amt->getOperand(4);
16684 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16685 CanBeSimplified = Amt1 == Amt->getOperand(i);
16686 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16687 CanBeSimplified = Amt2 == Amt->getOperand(j);
16691 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16692 isa<ConstantSDNode>(Amt2)) {
16693 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16694 EVT CastVT = MVT::v4i32;
16696 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16697 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16699 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16700 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16701 if (TargetOpcode == X86ISD::MOVSD)
16702 CastVT = MVT::v2i64;
16703 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16704 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16705 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16707 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16711 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16712 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
16713 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
16715 SDValue VSelM = DAG.getConstant(0x80, dl, VT);
16716 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16717 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16719 // r = VSELECT(r, shl(r, 4), a);
16720 SDValue M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(4, dl, VT));
16721 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16724 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16725 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16726 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16728 // r = VSELECT(r, shl(r, 2), a);
16729 M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(2, dl, VT));
16730 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16733 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16734 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16735 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16737 // return VSELECT(r, r+r, a);
16738 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16739 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16743 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16744 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16745 // solution better.
16746 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16747 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16749 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16750 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16751 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16752 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16753 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16756 // Decompose 256-bit shifts into smaller 128-bit shifts.
16757 if (VT.is256BitVector()) {
16758 unsigned NumElems = VT.getVectorNumElements();
16759 MVT EltVT = VT.getVectorElementType();
16760 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16762 // Extract the two vectors
16763 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16764 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16766 // Recreate the shift amount vectors
16767 SDValue Amt1, Amt2;
16768 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16769 // Constant shift amount
16770 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16771 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16772 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16774 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16775 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16777 // Variable shift amount
16778 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16779 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16782 // Issue new vector shifts for the smaller types
16783 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16784 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16786 // Concatenate the result back
16787 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16793 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16794 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16795 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16796 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16797 // has only one use.
16798 SDNode *N = Op.getNode();
16799 SDValue LHS = N->getOperand(0);
16800 SDValue RHS = N->getOperand(1);
16801 unsigned BaseOp = 0;
16804 switch (Op.getOpcode()) {
16805 default: llvm_unreachable("Unknown ovf instruction!");
16807 // A subtract of one will be selected as a INC. Note that INC doesn't
16808 // set CF, so we can't do this for UADDO.
16809 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16811 BaseOp = X86ISD::INC;
16812 Cond = X86::COND_O;
16815 BaseOp = X86ISD::ADD;
16816 Cond = X86::COND_O;
16819 BaseOp = X86ISD::ADD;
16820 Cond = X86::COND_B;
16823 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16824 // set CF, so we can't do this for USUBO.
16825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16827 BaseOp = X86ISD::DEC;
16828 Cond = X86::COND_O;
16831 BaseOp = X86ISD::SUB;
16832 Cond = X86::COND_O;
16835 BaseOp = X86ISD::SUB;
16836 Cond = X86::COND_B;
16839 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16840 Cond = X86::COND_O;
16842 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16843 if (N->getValueType(0) == MVT::i8) {
16844 BaseOp = X86ISD::UMUL8;
16845 Cond = X86::COND_O;
16848 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16850 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16853 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16854 DAG.getConstant(X86::COND_O, DL, MVT::i32),
16855 SDValue(Sum.getNode(), 2));
16857 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16861 // Also sets EFLAGS.
16862 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16863 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16866 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16867 DAG.getConstant(Cond, DL, MVT::i32),
16868 SDValue(Sum.getNode(), 1));
16870 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16873 /// Returns true if the operand type is exactly twice the native width, and
16874 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16875 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16876 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16877 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16878 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16881 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16882 else if (OpWidth == 128)
16883 return Subtarget->hasCmpxchg16b();
16888 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16889 return needsCmpXchgNb(SI->getValueOperand()->getType());
16892 // Note: this turns large loads into lock cmpxchg8b/16b.
16893 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16894 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16895 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16896 return needsCmpXchgNb(PTy->getElementType());
16899 TargetLoweringBase::AtomicRMWExpansionKind
16900 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16901 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16902 const Type *MemType = AI->getType();
16904 // If the operand is too big, we must see if cmpxchg8/16b is available
16905 // and default to library calls otherwise.
16906 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
16907 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
16908 : AtomicRMWExpansionKind::None;
16911 AtomicRMWInst::BinOp Op = AI->getOperation();
16914 llvm_unreachable("Unknown atomic operation");
16915 case AtomicRMWInst::Xchg:
16916 case AtomicRMWInst::Add:
16917 case AtomicRMWInst::Sub:
16918 // It's better to use xadd, xsub or xchg for these in all cases.
16919 return AtomicRMWExpansionKind::None;
16920 case AtomicRMWInst::Or:
16921 case AtomicRMWInst::And:
16922 case AtomicRMWInst::Xor:
16923 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16924 // prefix to a normal instruction for these operations.
16925 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
16926 : AtomicRMWExpansionKind::None;
16927 case AtomicRMWInst::Nand:
16928 case AtomicRMWInst::Max:
16929 case AtomicRMWInst::Min:
16930 case AtomicRMWInst::UMax:
16931 case AtomicRMWInst::UMin:
16932 // These always require a non-trivial set of data operations on x86. We must
16933 // use a cmpxchg loop.
16934 return AtomicRMWExpansionKind::CmpXChg;
16938 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16939 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16940 // no-sse2). There isn't any reason to disable it if the target processor
16942 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16946 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16947 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16948 const Type *MemType = AI->getType();
16949 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16950 // there is no benefit in turning such RMWs into loads, and it is actually
16951 // harmful as it introduces a mfence.
16952 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16955 auto Builder = IRBuilder<>(AI);
16956 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16957 auto SynchScope = AI->getSynchScope();
16958 // We must restrict the ordering to avoid generating loads with Release or
16959 // ReleaseAcquire orderings.
16960 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16961 auto Ptr = AI->getPointerOperand();
16963 // Before the load we need a fence. Here is an example lifted from
16964 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16967 // x.store(1, relaxed);
16968 // r1 = y.fetch_add(0, release);
16970 // y.fetch_add(42, acquire);
16971 // r2 = x.load(relaxed);
16972 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16973 // lowered to just a load without a fence. A mfence flushes the store buffer,
16974 // making the optimization clearly correct.
16975 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16976 // otherwise, we might be able to be more agressive on relaxed idempotent
16977 // rmw. In practice, they do not look useful, so we don't try to be
16978 // especially clever.
16979 if (SynchScope == SingleThread) {
16980 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16981 // the IR level, so we must wrap it in an intrinsic.
16983 } else if (hasMFENCE(*Subtarget)) {
16984 Function *MFence = llvm::Intrinsic::getDeclaration(M,
16985 Intrinsic::x86_sse2_mfence);
16986 Builder.CreateCall(MFence);
16988 // FIXME: it might make sense to use a locked operation here but on a
16989 // different cache-line to prevent cache-line bouncing. In practice it
16990 // is probably a small win, and x86 processors without mfence are rare
16991 // enough that we do not bother.
16995 // Finally we can emit the atomic load.
16996 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
16997 AI->getType()->getPrimitiveSizeInBits());
16998 Loaded->setAtomic(Order, SynchScope);
16999 AI->replaceAllUsesWith(Loaded);
17000 AI->eraseFromParent();
17004 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17005 SelectionDAG &DAG) {
17007 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17008 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17009 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17010 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17012 // The only fence that needs an instruction is a sequentially-consistent
17013 // cross-thread fence.
17014 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17015 if (hasMFENCE(*Subtarget))
17016 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17018 SDValue Chain = Op.getOperand(0);
17019 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17021 DAG.getRegister(X86::ESP, MVT::i32), // Base
17022 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17023 DAG.getRegister(0, MVT::i32), // Index
17024 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17025 DAG.getRegister(0, MVT::i32), // Segment.
17029 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17030 return SDValue(Res, 0);
17033 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17034 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17037 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17038 SelectionDAG &DAG) {
17039 MVT T = Op.getSimpleValueType();
17043 switch(T.SimpleTy) {
17044 default: llvm_unreachable("Invalid value type!");
17045 case MVT::i8: Reg = X86::AL; size = 1; break;
17046 case MVT::i16: Reg = X86::AX; size = 2; break;
17047 case MVT::i32: Reg = X86::EAX; size = 4; break;
17049 assert(Subtarget->is64Bit() && "Node not type legal!");
17050 Reg = X86::RAX; size = 8;
17053 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17054 Op.getOperand(2), SDValue());
17055 SDValue Ops[] = { cpIn.getValue(0),
17058 DAG.getTargetConstant(size, DL, MVT::i8),
17059 cpIn.getValue(1) };
17060 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17061 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17062 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17066 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17067 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17068 MVT::i32, cpOut.getValue(2));
17069 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17070 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17073 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17074 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17075 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17079 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17080 SelectionDAG &DAG) {
17081 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17082 MVT DstVT = Op.getSimpleValueType();
17084 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17085 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17086 if (DstVT != MVT::f64)
17087 // This conversion needs to be expanded.
17090 SDValue InVec = Op->getOperand(0);
17092 unsigned NumElts = SrcVT.getVectorNumElements();
17093 EVT SVT = SrcVT.getVectorElementType();
17095 // Widen the vector in input in the case of MVT::v2i32.
17096 // Example: from MVT::v2i32 to MVT::v4i32.
17097 SmallVector<SDValue, 16> Elts;
17098 for (unsigned i = 0, e = NumElts; i != e; ++i)
17099 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17100 DAG.getIntPtrConstant(i, dl)));
17102 // Explicitly mark the extra elements as Undef.
17103 Elts.append(NumElts, DAG.getUNDEF(SVT));
17105 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17106 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17107 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17108 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17109 DAG.getIntPtrConstant(0, dl));
17112 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17113 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17114 assert((DstVT == MVT::i64 ||
17115 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17116 "Unexpected custom BITCAST");
17117 // i64 <=> MMX conversions are Legal.
17118 if (SrcVT==MVT::i64 && DstVT.isVector())
17120 if (DstVT==MVT::i64 && SrcVT.isVector())
17122 // MMX <=> MMX conversions are Legal.
17123 if (SrcVT.isVector() && DstVT.isVector())
17125 // All other conversions need to be expanded.
17129 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17130 SelectionDAG &DAG) {
17131 SDNode *Node = Op.getNode();
17134 Op = Op.getOperand(0);
17135 EVT VT = Op.getValueType();
17136 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17137 "CTPOP lowering only implemented for 128/256-bit wide vector types");
17139 unsigned NumElts = VT.getVectorNumElements();
17140 EVT EltVT = VT.getVectorElementType();
17141 unsigned Len = EltVT.getSizeInBits();
17143 // This is the vectorized version of the "best" algorithm from
17144 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17145 // with a minor tweak to use a series of adds + shifts instead of vector
17146 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
17148 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
17149 // v8i32 => Always profitable
17151 // FIXME: There a couple of possible improvements:
17153 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
17154 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
17156 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
17157 "CTPOP not implemented for this vector element type.");
17159 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
17160 // extra legalization.
17161 bool NeedsBitcast = EltVT == MVT::i32;
17162 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
17164 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl,
17166 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl,
17168 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl,
17171 // v = v - ((v >> 1) & 0x55555555...)
17172 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, dl, EltVT));
17173 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
17174 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
17176 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17178 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
17179 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
17181 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
17183 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
17184 if (VT != And.getValueType())
17185 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17186 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
17188 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17189 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
17190 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
17191 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, dl, EltVT));
17192 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
17194 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
17195 if (NeedsBitcast) {
17196 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17197 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
17198 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
17201 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
17202 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
17203 if (VT != AndRHS.getValueType()) {
17204 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
17205 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
17207 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
17209 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17210 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, dl, EltVT));
17211 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
17212 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
17213 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17215 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
17216 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
17217 if (NeedsBitcast) {
17218 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17219 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
17221 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
17222 if (VT != And.getValueType())
17223 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17225 // The algorithm mentioned above uses:
17226 // v = (v * 0x01010101...) >> (Len - 8)
17228 // Change it to use vector adds + vector shifts which yield faster results on
17229 // Haswell than using vector integer multiplication.
17231 // For i32 elements:
17232 // v = v + (v >> 8)
17233 // v = v + (v >> 16)
17235 // For i64 elements:
17236 // v = v + (v >> 8)
17237 // v = v + (v >> 16)
17238 // v = v + (v >> 32)
17241 SmallVector<SDValue, 8> Csts;
17242 for (unsigned i = 8; i <= Len/2; i *= 2) {
17243 Csts.assign(NumElts, DAG.getConstant(i, dl, EltVT));
17244 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
17245 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
17246 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17250 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
17251 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), dl,
17253 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
17254 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
17255 if (NeedsBitcast) {
17256 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17257 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
17259 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
17260 if (VT != And.getValueType())
17261 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17266 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17267 SDNode *Node = Op.getNode();
17269 EVT T = Node->getValueType(0);
17270 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17271 DAG.getConstant(0, dl, T), Node->getOperand(2));
17272 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17273 cast<AtomicSDNode>(Node)->getMemoryVT(),
17274 Node->getOperand(0),
17275 Node->getOperand(1), negOp,
17276 cast<AtomicSDNode>(Node)->getMemOperand(),
17277 cast<AtomicSDNode>(Node)->getOrdering(),
17278 cast<AtomicSDNode>(Node)->getSynchScope());
17281 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17282 SDNode *Node = Op.getNode();
17284 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17286 // Convert seq_cst store -> xchg
17287 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17288 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17289 // (The only way to get a 16-byte store is cmpxchg16b)
17290 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17291 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17292 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17293 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17294 cast<AtomicSDNode>(Node)->getMemoryVT(),
17295 Node->getOperand(0),
17296 Node->getOperand(1), Node->getOperand(2),
17297 cast<AtomicSDNode>(Node)->getMemOperand(),
17298 cast<AtomicSDNode>(Node)->getOrdering(),
17299 cast<AtomicSDNode>(Node)->getSynchScope());
17300 return Swap.getValue(1);
17302 // Other atomic stores have a simple pattern.
17306 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17307 EVT VT = Op.getNode()->getSimpleValueType(0);
17309 // Let legalize expand this if it isn't a legal type yet.
17310 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17313 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17316 bool ExtraOp = false;
17317 switch (Op.getOpcode()) {
17318 default: llvm_unreachable("Invalid code");
17319 case ISD::ADDC: Opc = X86ISD::ADD; break;
17320 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17321 case ISD::SUBC: Opc = X86ISD::SUB; break;
17322 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17326 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17328 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17329 Op.getOperand(1), Op.getOperand(2));
17332 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17333 SelectionDAG &DAG) {
17334 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17336 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17337 // which returns the values as { float, float } (in XMM0) or
17338 // { double, double } (which is returned in XMM0, XMM1).
17340 SDValue Arg = Op.getOperand(0);
17341 EVT ArgVT = Arg.getValueType();
17342 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17344 TargetLowering::ArgListTy Args;
17345 TargetLowering::ArgListEntry Entry;
17349 Entry.isSExt = false;
17350 Entry.isZExt = false;
17351 Args.push_back(Entry);
17353 bool isF64 = ArgVT == MVT::f64;
17354 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17355 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17356 // the results are returned via SRet in memory.
17357 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17359 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17361 Type *RetTy = isF64
17362 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17363 : (Type*)VectorType::get(ArgTy, 4);
17365 TargetLowering::CallLoweringInfo CLI(DAG);
17366 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17367 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17369 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17372 // Returned in xmm0 and xmm1.
17373 return CallResult.first;
17375 // Returned in bits 0:31 and 32:64 xmm0.
17376 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17377 CallResult.first, DAG.getIntPtrConstant(0, dl));
17378 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17379 CallResult.first, DAG.getIntPtrConstant(1, dl));
17380 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17381 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17384 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17385 SelectionDAG &DAG) {
17386 assert(Subtarget->hasAVX512() &&
17387 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17389 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17390 EVT VT = N->getValue().getValueType();
17391 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17394 // X86 scatter kills mask register, so its type should be added to
17395 // the list of return values
17396 if (N->getNumValues() == 1) {
17397 SDValue Index = N->getIndex();
17398 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17399 !Index.getValueType().is512BitVector())
17400 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17402 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17403 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17404 N->getOperand(3), Index };
17406 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17407 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17408 return SDValue(NewScatter.getNode(), 0);
17413 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17414 SelectionDAG &DAG) {
17415 assert(Subtarget->hasAVX512() &&
17416 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17418 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17419 EVT VT = Op.getValueType();
17420 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17423 SDValue Index = N->getIndex();
17424 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17425 !Index.getValueType().is512BitVector()) {
17426 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17427 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17428 N->getOperand(3), Index };
17429 DAG.UpdateNodeOperands(N, Ops);
17434 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
17435 SelectionDAG &DAG) const {
17436 // TODO: Eventually, the lowering of these nodes should be informed by or
17437 // deferred to the GC strategy for the function in which they appear. For
17438 // now, however, they must be lowered to something. Since they are logically
17439 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17440 // require special handling for these nodes), lower them as literal NOOPs for
17442 SmallVector<SDValue, 2> Ops;
17444 Ops.push_back(Op.getOperand(0));
17445 if (Op->getGluedNode())
17446 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17449 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17450 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17455 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
17456 SelectionDAG &DAG) const {
17457 // TODO: Eventually, the lowering of these nodes should be informed by or
17458 // deferred to the GC strategy for the function in which they appear. For
17459 // now, however, they must be lowered to something. Since they are logically
17460 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17461 // require special handling for these nodes), lower them as literal NOOPs for
17463 SmallVector<SDValue, 2> Ops;
17465 Ops.push_back(Op.getOperand(0));
17466 if (Op->getGluedNode())
17467 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17470 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17471 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17476 /// LowerOperation - Provide custom lowering hooks for some operations.
17478 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17479 switch (Op.getOpcode()) {
17480 default: llvm_unreachable("Should not custom lower this!");
17481 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17482 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17483 return LowerCMP_SWAP(Op, Subtarget, DAG);
17484 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17485 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17486 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17487 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17488 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17489 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17490 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17491 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17492 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17493 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17494 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17495 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17496 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17497 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17498 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17499 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17500 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17501 case ISD::SHL_PARTS:
17502 case ISD::SRA_PARTS:
17503 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17504 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17505 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17506 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17507 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17508 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17509 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17510 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17511 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17512 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17513 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17515 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17516 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17517 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17518 case ISD::SETCC: return LowerSETCC(Op, DAG);
17519 case ISD::SELECT: return LowerSELECT(Op, DAG);
17520 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17521 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17522 case ISD::VASTART: return LowerVASTART(Op, DAG);
17523 case ISD::VAARG: return LowerVAARG(Op, DAG);
17524 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17525 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17526 case ISD::INTRINSIC_VOID:
17527 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17528 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17529 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17530 case ISD::FRAME_TO_ARGS_OFFSET:
17531 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17532 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17533 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17534 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17535 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17536 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17537 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17538 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17539 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17540 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17541 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17542 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17543 case ISD::UMUL_LOHI:
17544 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17547 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17553 case ISD::UMULO: return LowerXALUO(Op, DAG);
17554 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17555 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17559 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17560 case ISD::ADD: return LowerADD(Op, DAG);
17561 case ISD::SUB: return LowerSUB(Op, DAG);
17562 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17563 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
17564 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
17565 case ISD::GC_TRANSITION_START:
17566 return LowerGC_TRANSITION_START(Op, DAG);
17567 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
17571 /// ReplaceNodeResults - Replace a node with an illegal result type
17572 /// with a new node built out of custom code.
17573 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17574 SmallVectorImpl<SDValue>&Results,
17575 SelectionDAG &DAG) const {
17577 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17578 switch (N->getOpcode()) {
17580 llvm_unreachable("Do not know how to custom type legalize this operation!");
17581 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17582 case X86ISD::FMINC:
17584 case X86ISD::FMAXC:
17585 case X86ISD::FMAX: {
17586 EVT VT = N->getValueType(0);
17587 if (VT != MVT::v2f32)
17588 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17589 SDValue UNDEF = DAG.getUNDEF(VT);
17590 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17591 N->getOperand(0), UNDEF);
17592 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17593 N->getOperand(1), UNDEF);
17594 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17597 case ISD::SIGN_EXTEND_INREG:
17602 // We don't want to expand or promote these.
17609 case ISD::UDIVREM: {
17610 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17611 Results.push_back(V);
17614 case ISD::FP_TO_SINT:
17615 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
17616 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
17617 if (N->getOperand(0).getValueType() == MVT::f16)
17620 case ISD::FP_TO_UINT: {
17621 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17623 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17626 std::pair<SDValue,SDValue> Vals =
17627 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17628 SDValue FIST = Vals.first, StackSlot = Vals.second;
17629 if (FIST.getNode()) {
17630 EVT VT = N->getValueType(0);
17631 // Return a load from the stack slot.
17632 if (StackSlot.getNode())
17633 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17634 MachinePointerInfo(),
17635 false, false, false, 0));
17637 Results.push_back(FIST);
17641 case ISD::UINT_TO_FP: {
17642 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17643 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17644 N->getValueType(0) != MVT::v2f32)
17646 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17648 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
17650 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17651 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17652 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17653 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17654 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17655 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17658 case ISD::FP_ROUND: {
17659 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17661 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17662 Results.push_back(V);
17665 case ISD::FP_EXTEND: {
17666 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
17667 // No other ValueType for FP_EXTEND should reach this point.
17668 assert(N->getValueType(0) == MVT::v2f32 &&
17669 "Do not know how to legalize this Node");
17672 case ISD::INTRINSIC_W_CHAIN: {
17673 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17675 default : llvm_unreachable("Do not know how to custom type "
17676 "legalize this intrinsic operation!");
17677 case Intrinsic::x86_rdtsc:
17678 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17680 case Intrinsic::x86_rdtscp:
17681 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17683 case Intrinsic::x86_rdpmc:
17684 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17687 case ISD::READCYCLECOUNTER: {
17688 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17691 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17692 EVT T = N->getValueType(0);
17693 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17694 bool Regs64bit = T == MVT::i128;
17695 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17696 SDValue cpInL, cpInH;
17697 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17698 DAG.getConstant(0, dl, HalfT));
17699 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17700 DAG.getConstant(1, dl, HalfT));
17701 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17702 Regs64bit ? X86::RAX : X86::EAX,
17704 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17705 Regs64bit ? X86::RDX : X86::EDX,
17706 cpInH, cpInL.getValue(1));
17707 SDValue swapInL, swapInH;
17708 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17709 DAG.getConstant(0, dl, HalfT));
17710 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17711 DAG.getConstant(1, dl, HalfT));
17712 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17713 Regs64bit ? X86::RBX : X86::EBX,
17714 swapInL, cpInH.getValue(1));
17715 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17716 Regs64bit ? X86::RCX : X86::ECX,
17717 swapInH, swapInL.getValue(1));
17718 SDValue Ops[] = { swapInH.getValue(0),
17720 swapInH.getValue(1) };
17721 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17722 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17723 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17724 X86ISD::LCMPXCHG8_DAG;
17725 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17726 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17727 Regs64bit ? X86::RAX : X86::EAX,
17728 HalfT, Result.getValue(1));
17729 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17730 Regs64bit ? X86::RDX : X86::EDX,
17731 HalfT, cpOutL.getValue(2));
17732 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17734 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17735 MVT::i32, cpOutH.getValue(2));
17737 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17738 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
17739 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17741 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17742 Results.push_back(Success);
17743 Results.push_back(EFLAGS.getValue(1));
17746 case ISD::ATOMIC_SWAP:
17747 case ISD::ATOMIC_LOAD_ADD:
17748 case ISD::ATOMIC_LOAD_SUB:
17749 case ISD::ATOMIC_LOAD_AND:
17750 case ISD::ATOMIC_LOAD_OR:
17751 case ISD::ATOMIC_LOAD_XOR:
17752 case ISD::ATOMIC_LOAD_NAND:
17753 case ISD::ATOMIC_LOAD_MIN:
17754 case ISD::ATOMIC_LOAD_MAX:
17755 case ISD::ATOMIC_LOAD_UMIN:
17756 case ISD::ATOMIC_LOAD_UMAX:
17757 case ISD::ATOMIC_LOAD: {
17758 // Delegate to generic TypeLegalization. Situations we can really handle
17759 // should have already been dealt with by AtomicExpandPass.cpp.
17762 case ISD::BITCAST: {
17763 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17764 EVT DstVT = N->getValueType(0);
17765 EVT SrcVT = N->getOperand(0)->getValueType(0);
17767 if (SrcVT != MVT::f64 ||
17768 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17771 unsigned NumElts = DstVT.getVectorNumElements();
17772 EVT SVT = DstVT.getVectorElementType();
17773 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17774 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17775 MVT::v2f64, N->getOperand(0));
17776 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17778 if (ExperimentalVectorWideningLegalization) {
17779 // If we are legalizing vectors by widening, we already have the desired
17780 // legal vector type, just return it.
17781 Results.push_back(ToVecInt);
17785 SmallVector<SDValue, 8> Elts;
17786 for (unsigned i = 0, e = NumElts; i != e; ++i)
17787 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17788 ToVecInt, DAG.getIntPtrConstant(i, dl)));
17790 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17795 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17796 switch ((X86ISD::NodeType)Opcode) {
17797 case X86ISD::FIRST_NUMBER: break;
17798 case X86ISD::BSF: return "X86ISD::BSF";
17799 case X86ISD::BSR: return "X86ISD::BSR";
17800 case X86ISD::SHLD: return "X86ISD::SHLD";
17801 case X86ISD::SHRD: return "X86ISD::SHRD";
17802 case X86ISD::FAND: return "X86ISD::FAND";
17803 case X86ISD::FANDN: return "X86ISD::FANDN";
17804 case X86ISD::FOR: return "X86ISD::FOR";
17805 case X86ISD::FXOR: return "X86ISD::FXOR";
17806 case X86ISD::FSRL: return "X86ISD::FSRL";
17807 case X86ISD::FILD: return "X86ISD::FILD";
17808 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17809 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17810 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17811 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17812 case X86ISD::FLD: return "X86ISD::FLD";
17813 case X86ISD::FST: return "X86ISD::FST";
17814 case X86ISD::CALL: return "X86ISD::CALL";
17815 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17816 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17817 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17818 case X86ISD::BT: return "X86ISD::BT";
17819 case X86ISD::CMP: return "X86ISD::CMP";
17820 case X86ISD::COMI: return "X86ISD::COMI";
17821 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17822 case X86ISD::CMPM: return "X86ISD::CMPM";
17823 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17824 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
17825 case X86ISD::SETCC: return "X86ISD::SETCC";
17826 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17827 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17828 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
17829 case X86ISD::CMOV: return "X86ISD::CMOV";
17830 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17831 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17832 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17833 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17834 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17835 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17836 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17837 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
17838 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
17839 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
17840 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17841 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17842 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17843 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17844 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17845 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
17846 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17847 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17848 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17849 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17850 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17851 case X86ISD::ADDUS: return "X86ISD::ADDUS";
17852 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17853 case X86ISD::HADD: return "X86ISD::HADD";
17854 case X86ISD::HSUB: return "X86ISD::HSUB";
17855 case X86ISD::FHADD: return "X86ISD::FHADD";
17856 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17857 case X86ISD::UMAX: return "X86ISD::UMAX";
17858 case X86ISD::UMIN: return "X86ISD::UMIN";
17859 case X86ISD::SMAX: return "X86ISD::SMAX";
17860 case X86ISD::SMIN: return "X86ISD::SMIN";
17861 case X86ISD::FMAX: return "X86ISD::FMAX";
17862 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
17863 case X86ISD::FMIN: return "X86ISD::FMIN";
17864 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
17865 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17866 case X86ISD::FMINC: return "X86ISD::FMINC";
17867 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17868 case X86ISD::FRCP: return "X86ISD::FRCP";
17869 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17870 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17871 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17872 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17873 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17874 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17875 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17876 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17877 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17878 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17879 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17880 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17881 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17882 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17883 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17884 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17885 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17886 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17887 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17888 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17889 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17890 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17891 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17892 case X86ISD::VSHL: return "X86ISD::VSHL";
17893 case X86ISD::VSRL: return "X86ISD::VSRL";
17894 case X86ISD::VSRA: return "X86ISD::VSRA";
17895 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17896 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17897 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17898 case X86ISD::CMPP: return "X86ISD::CMPP";
17899 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17900 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17901 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17902 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17903 case X86ISD::ADD: return "X86ISD::ADD";
17904 case X86ISD::SUB: return "X86ISD::SUB";
17905 case X86ISD::ADC: return "X86ISD::ADC";
17906 case X86ISD::SBB: return "X86ISD::SBB";
17907 case X86ISD::SMUL: return "X86ISD::SMUL";
17908 case X86ISD::UMUL: return "X86ISD::UMUL";
17909 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17910 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17911 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17912 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17913 case X86ISD::INC: return "X86ISD::INC";
17914 case X86ISD::DEC: return "X86ISD::DEC";
17915 case X86ISD::OR: return "X86ISD::OR";
17916 case X86ISD::XOR: return "X86ISD::XOR";
17917 case X86ISD::AND: return "X86ISD::AND";
17918 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17919 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17920 case X86ISD::PTEST: return "X86ISD::PTEST";
17921 case X86ISD::TESTP: return "X86ISD::TESTP";
17922 case X86ISD::TESTM: return "X86ISD::TESTM";
17923 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17924 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17925 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17926 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17927 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17928 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17929 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17930 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17931 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17932 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17933 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17934 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17935 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17936 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17937 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17938 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17939 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17940 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17941 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17942 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17943 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17944 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17945 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17946 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17947 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
17948 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17949 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17950 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17951 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17952 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17953 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17954 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17955 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17956 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17957 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17958 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17959 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17960 case X86ISD::MFENCE: return "X86ISD::MFENCE";
17961 case X86ISD::SFENCE: return "X86ISD::SFENCE";
17962 case X86ISD::LFENCE: return "X86ISD::LFENCE";
17963 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17964 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17965 case X86ISD::SAHF: return "X86ISD::SAHF";
17966 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17967 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17968 case X86ISD::FMADD: return "X86ISD::FMADD";
17969 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17970 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17971 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17972 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17973 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17974 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
17975 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
17976 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
17977 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
17978 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
17979 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
17980 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
17981 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17982 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17983 case X86ISD::XTEST: return "X86ISD::XTEST";
17984 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17985 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17986 case X86ISD::SELECT: return "X86ISD::SELECT";
17987 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17988 case X86ISD::RCP28: return "X86ISD::RCP28";
17989 case X86ISD::EXP2: return "X86ISD::EXP2";
17990 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17991 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17992 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17993 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17994 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17995 case X86ISD::ADDS: return "X86ISD::ADDS";
17996 case X86ISD::SUBS: return "X86ISD::SUBS";
18001 // isLegalAddressingMode - Return true if the addressing mode represented
18002 // by AM is legal for this target, for a load/store of the specified type.
18003 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18005 // X86 supports extremely general addressing modes.
18006 CodeModel::Model M = getTargetMachine().getCodeModel();
18007 Reloc::Model R = getTargetMachine().getRelocationModel();
18009 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18010 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18015 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18017 // If a reference to this global requires an extra load, we can't fold it.
18018 if (isGlobalStubReference(GVFlags))
18021 // If BaseGV requires a register for the PIC base, we cannot also have a
18022 // BaseReg specified.
18023 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18026 // If lower 4G is not available, then we must use rip-relative addressing.
18027 if ((M != CodeModel::Small || R != Reloc::Static) &&
18028 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18032 switch (AM.Scale) {
18038 // These scales always work.
18043 // These scales are formed with basereg+scalereg. Only accept if there is
18048 default: // Other stuff never works.
18055 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18056 unsigned Bits = Ty->getScalarSizeInBits();
18058 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18059 // particularly cheaper than those without.
18063 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18064 // variable shifts just as cheap as scalar ones.
18065 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18068 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18069 // fully general vector.
18073 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18074 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18076 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18077 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18078 return NumBits1 > NumBits2;
18081 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18082 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18085 if (!isTypeLegal(EVT::getEVT(Ty1)))
18088 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18090 // Assuming the caller doesn't have a zeroext or signext return parameter,
18091 // truncation all the way down to i1 is valid.
18095 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18096 return isInt<32>(Imm);
18099 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18100 // Can also use sub to handle negated immediates.
18101 return isInt<32>(Imm);
18104 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18105 if (!VT1.isInteger() || !VT2.isInteger())
18107 unsigned NumBits1 = VT1.getSizeInBits();
18108 unsigned NumBits2 = VT2.getSizeInBits();
18109 return NumBits1 > NumBits2;
18112 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18113 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18114 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18117 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18118 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18119 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18122 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18123 EVT VT1 = Val.getValueType();
18124 if (isZExtFree(VT1, VT2))
18127 if (Val.getOpcode() != ISD::LOAD)
18130 if (!VT1.isSimple() || !VT1.isInteger() ||
18131 !VT2.isSimple() || !VT2.isInteger())
18134 switch (VT1.getSimpleVT().SimpleTy) {
18139 // X86 has 8, 16, and 32-bit zero-extending loads.
18146 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18149 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18150 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18153 VT = VT.getScalarType();
18155 if (!VT.isSimple())
18158 switch (VT.getSimpleVT().SimpleTy) {
18169 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18170 // i16 instructions are longer (0x66 prefix) and potentially slower.
18171 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18174 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18175 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18176 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18177 /// are assumed to be legal.
18179 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18181 if (!VT.isSimple())
18184 // Not for i1 vectors
18185 if (VT.getScalarType() == MVT::i1)
18188 // Very little shuffling can be done for 64-bit vectors right now.
18189 if (VT.getSizeInBits() == 64)
18192 // We only care that the types being shuffled are legal. The lowering can
18193 // handle any possible shuffle mask that results.
18194 return isTypeLegal(VT.getSimpleVT());
18198 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18200 // Just delegate to the generic legality, clear masks aren't special.
18201 return isShuffleMaskLegal(Mask, VT);
18204 //===----------------------------------------------------------------------===//
18205 // X86 Scheduler Hooks
18206 //===----------------------------------------------------------------------===//
18208 /// Utility function to emit xbegin specifying the start of an RTM region.
18209 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18210 const TargetInstrInfo *TII) {
18211 DebugLoc DL = MI->getDebugLoc();
18213 const BasicBlock *BB = MBB->getBasicBlock();
18214 MachineFunction::iterator I = MBB;
18217 // For the v = xbegin(), we generate
18228 MachineBasicBlock *thisMBB = MBB;
18229 MachineFunction *MF = MBB->getParent();
18230 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18231 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18232 MF->insert(I, mainMBB);
18233 MF->insert(I, sinkMBB);
18235 // Transfer the remainder of BB and its successor edges to sinkMBB.
18236 sinkMBB->splice(sinkMBB->begin(), MBB,
18237 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18238 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18242 // # fallthrough to mainMBB
18243 // # abortion to sinkMBB
18244 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18245 thisMBB->addSuccessor(mainMBB);
18246 thisMBB->addSuccessor(sinkMBB);
18250 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18251 mainMBB->addSuccessor(sinkMBB);
18254 // EAX is live into the sinkMBB
18255 sinkMBB->addLiveIn(X86::EAX);
18256 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18257 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18260 MI->eraseFromParent();
18264 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18265 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18266 // in the .td file.
18267 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18268 const TargetInstrInfo *TII) {
18270 switch (MI->getOpcode()) {
18271 default: llvm_unreachable("illegal opcode!");
18272 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18273 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18274 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18275 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18276 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18277 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18278 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18279 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18282 DebugLoc dl = MI->getDebugLoc();
18283 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18285 unsigned NumArgs = MI->getNumOperands();
18286 for (unsigned i = 1; i < NumArgs; ++i) {
18287 MachineOperand &Op = MI->getOperand(i);
18288 if (!(Op.isReg() && Op.isImplicit()))
18289 MIB.addOperand(Op);
18291 if (MI->hasOneMemOperand())
18292 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18294 BuildMI(*BB, MI, dl,
18295 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18296 .addReg(X86::XMM0);
18298 MI->eraseFromParent();
18302 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18303 // defs in an instruction pattern
18304 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18305 const TargetInstrInfo *TII) {
18307 switch (MI->getOpcode()) {
18308 default: llvm_unreachable("illegal opcode!");
18309 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18310 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18311 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18312 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18313 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18314 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18315 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18316 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18319 DebugLoc dl = MI->getDebugLoc();
18320 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18322 unsigned NumArgs = MI->getNumOperands(); // remove the results
18323 for (unsigned i = 1; i < NumArgs; ++i) {
18324 MachineOperand &Op = MI->getOperand(i);
18325 if (!(Op.isReg() && Op.isImplicit()))
18326 MIB.addOperand(Op);
18328 if (MI->hasOneMemOperand())
18329 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18331 BuildMI(*BB, MI, dl,
18332 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18335 MI->eraseFromParent();
18339 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18340 const X86Subtarget *Subtarget) {
18341 DebugLoc dl = MI->getDebugLoc();
18342 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18343 // Address into RAX/EAX, other two args into ECX, EDX.
18344 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18345 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18346 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18347 for (int i = 0; i < X86::AddrNumOperands; ++i)
18348 MIB.addOperand(MI->getOperand(i));
18350 unsigned ValOps = X86::AddrNumOperands;
18351 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18352 .addReg(MI->getOperand(ValOps).getReg());
18353 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18354 .addReg(MI->getOperand(ValOps+1).getReg());
18356 // The instruction doesn't actually take any operands though.
18357 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18359 MI->eraseFromParent(); // The pseudo is gone now.
18363 MachineBasicBlock *
18364 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18365 MachineBasicBlock *MBB) const {
18366 // Emit va_arg instruction on X86-64.
18368 // Operands to this pseudo-instruction:
18369 // 0 ) Output : destination address (reg)
18370 // 1-5) Input : va_list address (addr, i64mem)
18371 // 6 ) ArgSize : Size (in bytes) of vararg type
18372 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18373 // 8 ) Align : Alignment of type
18374 // 9 ) EFLAGS (implicit-def)
18376 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18377 static_assert(X86::AddrNumOperands == 5,
18378 "VAARG_64 assumes 5 address operands");
18380 unsigned DestReg = MI->getOperand(0).getReg();
18381 MachineOperand &Base = MI->getOperand(1);
18382 MachineOperand &Scale = MI->getOperand(2);
18383 MachineOperand &Index = MI->getOperand(3);
18384 MachineOperand &Disp = MI->getOperand(4);
18385 MachineOperand &Segment = MI->getOperand(5);
18386 unsigned ArgSize = MI->getOperand(6).getImm();
18387 unsigned ArgMode = MI->getOperand(7).getImm();
18388 unsigned Align = MI->getOperand(8).getImm();
18390 // Memory Reference
18391 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18392 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18393 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18395 // Machine Information
18396 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18397 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18398 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18399 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18400 DebugLoc DL = MI->getDebugLoc();
18402 // struct va_list {
18405 // i64 overflow_area (address)
18406 // i64 reg_save_area (address)
18408 // sizeof(va_list) = 24
18409 // alignment(va_list) = 8
18411 unsigned TotalNumIntRegs = 6;
18412 unsigned TotalNumXMMRegs = 8;
18413 bool UseGPOffset = (ArgMode == 1);
18414 bool UseFPOffset = (ArgMode == 2);
18415 unsigned MaxOffset = TotalNumIntRegs * 8 +
18416 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18418 /* Align ArgSize to a multiple of 8 */
18419 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18420 bool NeedsAlign = (Align > 8);
18422 MachineBasicBlock *thisMBB = MBB;
18423 MachineBasicBlock *overflowMBB;
18424 MachineBasicBlock *offsetMBB;
18425 MachineBasicBlock *endMBB;
18427 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18428 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18429 unsigned OffsetReg = 0;
18431 if (!UseGPOffset && !UseFPOffset) {
18432 // If we only pull from the overflow region, we don't create a branch.
18433 // We don't need to alter control flow.
18434 OffsetDestReg = 0; // unused
18435 OverflowDestReg = DestReg;
18437 offsetMBB = nullptr;
18438 overflowMBB = thisMBB;
18441 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18442 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18443 // If not, pull from overflow_area. (branch to overflowMBB)
18448 // offsetMBB overflowMBB
18453 // Registers for the PHI in endMBB
18454 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18455 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18457 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18458 MachineFunction *MF = MBB->getParent();
18459 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18460 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18461 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18463 MachineFunction::iterator MBBIter = MBB;
18466 // Insert the new basic blocks
18467 MF->insert(MBBIter, offsetMBB);
18468 MF->insert(MBBIter, overflowMBB);
18469 MF->insert(MBBIter, endMBB);
18471 // Transfer the remainder of MBB and its successor edges to endMBB.
18472 endMBB->splice(endMBB->begin(), thisMBB,
18473 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18474 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18476 // Make offsetMBB and overflowMBB successors of thisMBB
18477 thisMBB->addSuccessor(offsetMBB);
18478 thisMBB->addSuccessor(overflowMBB);
18480 // endMBB is a successor of both offsetMBB and overflowMBB
18481 offsetMBB->addSuccessor(endMBB);
18482 overflowMBB->addSuccessor(endMBB);
18484 // Load the offset value into a register
18485 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18486 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18490 .addDisp(Disp, UseFPOffset ? 4 : 0)
18491 .addOperand(Segment)
18492 .setMemRefs(MMOBegin, MMOEnd);
18494 // Check if there is enough room left to pull this argument.
18495 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18497 .addImm(MaxOffset + 8 - ArgSizeA8);
18499 // Branch to "overflowMBB" if offset >= max
18500 // Fall through to "offsetMBB" otherwise
18501 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18502 .addMBB(overflowMBB);
18505 // In offsetMBB, emit code to use the reg_save_area.
18507 assert(OffsetReg != 0);
18509 // Read the reg_save_area address.
18510 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18511 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18516 .addOperand(Segment)
18517 .setMemRefs(MMOBegin, MMOEnd);
18519 // Zero-extend the offset
18520 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18521 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18524 .addImm(X86::sub_32bit);
18526 // Add the offset to the reg_save_area to get the final address.
18527 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18528 .addReg(OffsetReg64)
18529 .addReg(RegSaveReg);
18531 // Compute the offset for the next argument
18532 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18533 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18535 .addImm(UseFPOffset ? 16 : 8);
18537 // Store it back into the va_list.
18538 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18542 .addDisp(Disp, UseFPOffset ? 4 : 0)
18543 .addOperand(Segment)
18544 .addReg(NextOffsetReg)
18545 .setMemRefs(MMOBegin, MMOEnd);
18548 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18553 // Emit code to use overflow area
18556 // Load the overflow_area address into a register.
18557 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18558 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18563 .addOperand(Segment)
18564 .setMemRefs(MMOBegin, MMOEnd);
18566 // If we need to align it, do so. Otherwise, just copy the address
18567 // to OverflowDestReg.
18569 // Align the overflow address
18570 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18571 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18573 // aligned_addr = (addr + (align-1)) & ~(align-1)
18574 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18575 .addReg(OverflowAddrReg)
18578 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18580 .addImm(~(uint64_t)(Align-1));
18582 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18583 .addReg(OverflowAddrReg);
18586 // Compute the next overflow address after this argument.
18587 // (the overflow address should be kept 8-byte aligned)
18588 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18589 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18590 .addReg(OverflowDestReg)
18591 .addImm(ArgSizeA8);
18593 // Store the new overflow address.
18594 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18599 .addOperand(Segment)
18600 .addReg(NextAddrReg)
18601 .setMemRefs(MMOBegin, MMOEnd);
18603 // If we branched, emit the PHI to the front of endMBB.
18605 BuildMI(*endMBB, endMBB->begin(), DL,
18606 TII->get(X86::PHI), DestReg)
18607 .addReg(OffsetDestReg).addMBB(offsetMBB)
18608 .addReg(OverflowDestReg).addMBB(overflowMBB);
18611 // Erase the pseudo instruction
18612 MI->eraseFromParent();
18617 MachineBasicBlock *
18618 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18620 MachineBasicBlock *MBB) const {
18621 // Emit code to save XMM registers to the stack. The ABI says that the
18622 // number of registers to save is given in %al, so it's theoretically
18623 // possible to do an indirect jump trick to avoid saving all of them,
18624 // however this code takes a simpler approach and just executes all
18625 // of the stores if %al is non-zero. It's less code, and it's probably
18626 // easier on the hardware branch predictor, and stores aren't all that
18627 // expensive anyway.
18629 // Create the new basic blocks. One block contains all the XMM stores,
18630 // and one block is the final destination regardless of whether any
18631 // stores were performed.
18632 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18633 MachineFunction *F = MBB->getParent();
18634 MachineFunction::iterator MBBIter = MBB;
18636 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18637 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18638 F->insert(MBBIter, XMMSaveMBB);
18639 F->insert(MBBIter, EndMBB);
18641 // Transfer the remainder of MBB and its successor edges to EndMBB.
18642 EndMBB->splice(EndMBB->begin(), MBB,
18643 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18644 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18646 // The original block will now fall through to the XMM save block.
18647 MBB->addSuccessor(XMMSaveMBB);
18648 // The XMMSaveMBB will fall through to the end block.
18649 XMMSaveMBB->addSuccessor(EndMBB);
18651 // Now add the instructions.
18652 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18653 DebugLoc DL = MI->getDebugLoc();
18655 unsigned CountReg = MI->getOperand(0).getReg();
18656 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18657 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18659 if (!Subtarget->isTargetWin64()) {
18660 // If %al is 0, branch around the XMM save block.
18661 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18662 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18663 MBB->addSuccessor(EndMBB);
18666 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18667 // that was just emitted, but clearly shouldn't be "saved".
18668 assert((MI->getNumOperands() <= 3 ||
18669 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18670 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18671 && "Expected last argument to be EFLAGS");
18672 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18673 // In the XMM save block, save all the XMM argument registers.
18674 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18675 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18676 MachineMemOperand *MMO =
18677 F->getMachineMemOperand(
18678 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18679 MachineMemOperand::MOStore,
18680 /*Size=*/16, /*Align=*/16);
18681 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18682 .addFrameIndex(RegSaveFrameIndex)
18683 .addImm(/*Scale=*/1)
18684 .addReg(/*IndexReg=*/0)
18685 .addImm(/*Disp=*/Offset)
18686 .addReg(/*Segment=*/0)
18687 .addReg(MI->getOperand(i).getReg())
18688 .addMemOperand(MMO);
18691 MI->eraseFromParent(); // The pseudo instruction is gone now.
18696 // The EFLAGS operand of SelectItr might be missing a kill marker
18697 // because there were multiple uses of EFLAGS, and ISel didn't know
18698 // which to mark. Figure out whether SelectItr should have had a
18699 // kill marker, and set it if it should. Returns the correct kill
18701 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18702 MachineBasicBlock* BB,
18703 const TargetRegisterInfo* TRI) {
18704 // Scan forward through BB for a use/def of EFLAGS.
18705 MachineBasicBlock::iterator miI(std::next(SelectItr));
18706 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18707 const MachineInstr& mi = *miI;
18708 if (mi.readsRegister(X86::EFLAGS))
18710 if (mi.definesRegister(X86::EFLAGS))
18711 break; // Should have kill-flag - update below.
18714 // If we hit the end of the block, check whether EFLAGS is live into a
18716 if (miI == BB->end()) {
18717 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18718 sEnd = BB->succ_end();
18719 sItr != sEnd; ++sItr) {
18720 MachineBasicBlock* succ = *sItr;
18721 if (succ->isLiveIn(X86::EFLAGS))
18726 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18727 // out. SelectMI should have a kill flag on EFLAGS.
18728 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18732 MachineBasicBlock *
18733 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18734 MachineBasicBlock *BB) const {
18735 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18736 DebugLoc DL = MI->getDebugLoc();
18738 // To "insert" a SELECT_CC instruction, we actually have to insert the
18739 // diamond control-flow pattern. The incoming instruction knows the
18740 // destination vreg to set, the condition code register to branch on, the
18741 // true/false values to select between, and a branch opcode to use.
18742 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18743 MachineFunction::iterator It = BB;
18749 // cmpTY ccX, r1, r2
18751 // fallthrough --> copy0MBB
18752 MachineBasicBlock *thisMBB = BB;
18753 MachineFunction *F = BB->getParent();
18755 // We also lower double CMOVs:
18756 // (CMOV (CMOV F, T, cc1), T, cc2)
18757 // to two successives branches. For that, we look for another CMOV as the
18758 // following instruction.
18760 // Without this, we would add a PHI between the two jumps, which ends up
18761 // creating a few copies all around. For instance, for
18763 // (sitofp (zext (fcmp une)))
18765 // we would generate:
18767 // ucomiss %xmm1, %xmm0
18768 // movss <1.0f>, %xmm0
18769 // movaps %xmm0, %xmm1
18771 // xorps %xmm1, %xmm1
18774 // movaps %xmm1, %xmm0
18778 // because this custom-inserter would have generated:
18790 // A: X = ...; Y = ...
18792 // C: Z = PHI [X, A], [Y, B]
18794 // E: PHI [X, C], [Z, D]
18796 // If we lower both CMOVs in a single step, we can instead generate:
18808 // A: X = ...; Y = ...
18810 // E: PHI [X, A], [X, C], [Y, D]
18812 // Which, in our sitofp/fcmp example, gives us something like:
18814 // ucomiss %xmm1, %xmm0
18815 // movss <1.0f>, %xmm0
18818 // xorps %xmm0, %xmm0
18822 MachineInstr *NextCMOV = nullptr;
18823 MachineBasicBlock::iterator NextMIIt =
18824 std::next(MachineBasicBlock::iterator(MI));
18825 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
18826 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
18827 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
18828 NextCMOV = &*NextMIIt;
18830 MachineBasicBlock *jcc1MBB = nullptr;
18832 // If we have a double CMOV, we lower it to two successive branches to
18833 // the same block. EFLAGS is used by both, so mark it as live in the second.
18835 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
18836 F->insert(It, jcc1MBB);
18837 jcc1MBB->addLiveIn(X86::EFLAGS);
18840 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18841 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18842 F->insert(It, copy0MBB);
18843 F->insert(It, sinkMBB);
18845 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18846 // live into the sink and copy blocks.
18847 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18849 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
18850 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
18851 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
18852 copy0MBB->addLiveIn(X86::EFLAGS);
18853 sinkMBB->addLiveIn(X86::EFLAGS);
18856 // Transfer the remainder of BB and its successor edges to sinkMBB.
18857 sinkMBB->splice(sinkMBB->begin(), BB,
18858 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18859 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18861 // Add the true and fallthrough blocks as its successors.
18863 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
18864 BB->addSuccessor(jcc1MBB);
18866 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
18867 // jump to the sinkMBB.
18868 jcc1MBB->addSuccessor(copy0MBB);
18869 jcc1MBB->addSuccessor(sinkMBB);
18871 BB->addSuccessor(copy0MBB);
18874 // The true block target of the first (or only) branch is always sinkMBB.
18875 BB->addSuccessor(sinkMBB);
18877 // Create the conditional branch instruction.
18879 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18880 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18883 unsigned Opc2 = X86::GetCondBranchFromCond(
18884 (X86::CondCode)NextCMOV->getOperand(3).getImm());
18885 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
18889 // %FalseValue = ...
18890 // # fallthrough to sinkMBB
18891 copy0MBB->addSuccessor(sinkMBB);
18894 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18896 MachineInstrBuilder MIB =
18897 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
18898 MI->getOperand(0).getReg())
18899 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18900 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18902 // If we have a double CMOV, the second Jcc provides the same incoming
18903 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
18905 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
18906 // Copy the PHI result to the register defined by the second CMOV.
18907 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
18908 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
18909 .addReg(MI->getOperand(0).getReg());
18910 NextCMOV->eraseFromParent();
18913 MI->eraseFromParent(); // The pseudo instruction is gone now.
18917 MachineBasicBlock *
18918 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18919 MachineBasicBlock *BB) const {
18920 MachineFunction *MF = BB->getParent();
18921 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18922 DebugLoc DL = MI->getDebugLoc();
18923 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18925 assert(MF->shouldSplitStack());
18927 const bool Is64Bit = Subtarget->is64Bit();
18928 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18930 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18931 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18934 // ... [Till the alloca]
18935 // If stacklet is not large enough, jump to mallocMBB
18938 // Allocate by subtracting from RSP
18939 // Jump to continueMBB
18942 // Allocate by call to runtime
18946 // [rest of original BB]
18949 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18950 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18951 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18953 MachineRegisterInfo &MRI = MF->getRegInfo();
18954 const TargetRegisterClass *AddrRegClass =
18955 getRegClassFor(getPointerTy());
18957 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18958 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18959 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18960 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18961 sizeVReg = MI->getOperand(1).getReg(),
18962 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18964 MachineFunction::iterator MBBIter = BB;
18967 MF->insert(MBBIter, bumpMBB);
18968 MF->insert(MBBIter, mallocMBB);
18969 MF->insert(MBBIter, continueMBB);
18971 continueMBB->splice(continueMBB->begin(), BB,
18972 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18973 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18975 // Add code to the main basic block to check if the stack limit has been hit,
18976 // and if so, jump to mallocMBB otherwise to bumpMBB.
18977 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18978 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18979 .addReg(tmpSPVReg).addReg(sizeVReg);
18980 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18981 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18982 .addReg(SPLimitVReg);
18983 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18985 // bumpMBB simply decreases the stack pointer, since we know the current
18986 // stacklet has enough space.
18987 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18988 .addReg(SPLimitVReg);
18989 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18990 .addReg(SPLimitVReg);
18991 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18993 // Calls into a routine in libgcc to allocate more space from the heap.
18994 const uint32_t *RegMask =
18995 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
18997 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18999 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19000 .addExternalSymbol("__morestack_allocate_stack_space")
19001 .addRegMask(RegMask)
19002 .addReg(X86::RDI, RegState::Implicit)
19003 .addReg(X86::RAX, RegState::ImplicitDefine);
19004 } else if (Is64Bit) {
19005 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19007 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19008 .addExternalSymbol("__morestack_allocate_stack_space")
19009 .addRegMask(RegMask)
19010 .addReg(X86::EDI, RegState::Implicit)
19011 .addReg(X86::EAX, RegState::ImplicitDefine);
19013 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19015 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19016 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19017 .addExternalSymbol("__morestack_allocate_stack_space")
19018 .addRegMask(RegMask)
19019 .addReg(X86::EAX, RegState::ImplicitDefine);
19023 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19026 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19027 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19028 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19030 // Set up the CFG correctly.
19031 BB->addSuccessor(bumpMBB);
19032 BB->addSuccessor(mallocMBB);
19033 mallocMBB->addSuccessor(continueMBB);
19034 bumpMBB->addSuccessor(continueMBB);
19036 // Take care of the PHI nodes.
19037 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19038 MI->getOperand(0).getReg())
19039 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19040 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19042 // Delete the original pseudo instruction.
19043 MI->eraseFromParent();
19046 return continueMBB;
19049 MachineBasicBlock *
19050 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19051 MachineBasicBlock *BB) const {
19052 DebugLoc DL = MI->getDebugLoc();
19054 assert(!Subtarget->isTargetMachO());
19056 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19058 MI->eraseFromParent(); // The pseudo instruction is gone now.
19062 MachineBasicBlock *
19063 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19064 MachineBasicBlock *BB) const {
19065 // This is pretty easy. We're taking the value that we received from
19066 // our load from the relocation, sticking it in either RDI (x86-64)
19067 // or EAX and doing an indirect call. The return value will then
19068 // be in the normal return register.
19069 MachineFunction *F = BB->getParent();
19070 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19071 DebugLoc DL = MI->getDebugLoc();
19073 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19074 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19076 // Get a register mask for the lowered call.
19077 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19078 // proper register mask.
19079 const uint32_t *RegMask =
19080 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19081 if (Subtarget->is64Bit()) {
19082 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19083 TII->get(X86::MOV64rm), X86::RDI)
19085 .addImm(0).addReg(0)
19086 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19087 MI->getOperand(3).getTargetFlags())
19089 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19090 addDirectMem(MIB, X86::RDI);
19091 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19092 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19093 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19094 TII->get(X86::MOV32rm), X86::EAX)
19096 .addImm(0).addReg(0)
19097 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19098 MI->getOperand(3).getTargetFlags())
19100 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19101 addDirectMem(MIB, X86::EAX);
19102 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19104 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19105 TII->get(X86::MOV32rm), X86::EAX)
19106 .addReg(TII->getGlobalBaseReg(F))
19107 .addImm(0).addReg(0)
19108 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19109 MI->getOperand(3).getTargetFlags())
19111 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19112 addDirectMem(MIB, X86::EAX);
19113 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19116 MI->eraseFromParent(); // The pseudo instruction is gone now.
19120 MachineBasicBlock *
19121 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19122 MachineBasicBlock *MBB) const {
19123 DebugLoc DL = MI->getDebugLoc();
19124 MachineFunction *MF = MBB->getParent();
19125 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19126 MachineRegisterInfo &MRI = MF->getRegInfo();
19128 const BasicBlock *BB = MBB->getBasicBlock();
19129 MachineFunction::iterator I = MBB;
19132 // Memory Reference
19133 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19134 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19137 unsigned MemOpndSlot = 0;
19139 unsigned CurOp = 0;
19141 DstReg = MI->getOperand(CurOp++).getReg();
19142 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19143 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19144 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19145 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19147 MemOpndSlot = CurOp;
19149 MVT PVT = getPointerTy();
19150 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19151 "Invalid Pointer Size!");
19153 // For v = setjmp(buf), we generate
19156 // buf[LabelOffset] = restoreMBB
19157 // SjLjSetup restoreMBB
19163 // v = phi(main, restore)
19166 // if base pointer being used, load it from frame
19169 MachineBasicBlock *thisMBB = MBB;
19170 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19171 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19172 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19173 MF->insert(I, mainMBB);
19174 MF->insert(I, sinkMBB);
19175 MF->push_back(restoreMBB);
19177 MachineInstrBuilder MIB;
19179 // Transfer the remainder of BB and its successor edges to sinkMBB.
19180 sinkMBB->splice(sinkMBB->begin(), MBB,
19181 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19182 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19185 unsigned PtrStoreOpc = 0;
19186 unsigned LabelReg = 0;
19187 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19188 Reloc::Model RM = MF->getTarget().getRelocationModel();
19189 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19190 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19192 // Prepare IP either in reg or imm.
19193 if (!UseImmLabel) {
19194 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19195 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19196 LabelReg = MRI.createVirtualRegister(PtrRC);
19197 if (Subtarget->is64Bit()) {
19198 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19202 .addMBB(restoreMBB)
19205 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19206 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19207 .addReg(XII->getGlobalBaseReg(MF))
19210 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19214 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19216 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19217 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19218 if (i == X86::AddrDisp)
19219 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19221 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19224 MIB.addReg(LabelReg);
19226 MIB.addMBB(restoreMBB);
19227 MIB.setMemRefs(MMOBegin, MMOEnd);
19229 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19230 .addMBB(restoreMBB);
19232 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19233 MIB.addRegMask(RegInfo->getNoPreservedMask());
19234 thisMBB->addSuccessor(mainMBB);
19235 thisMBB->addSuccessor(restoreMBB);
19239 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19240 mainMBB->addSuccessor(sinkMBB);
19243 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19244 TII->get(X86::PHI), DstReg)
19245 .addReg(mainDstReg).addMBB(mainMBB)
19246 .addReg(restoreDstReg).addMBB(restoreMBB);
19249 if (RegInfo->hasBasePointer(*MF)) {
19250 const bool Uses64BitFramePtr =
19251 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19252 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19253 X86FI->setRestoreBasePointer(MF);
19254 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19255 unsigned BasePtr = RegInfo->getBaseRegister();
19256 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19257 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19258 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19259 .setMIFlag(MachineInstr::FrameSetup);
19261 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19262 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19263 restoreMBB->addSuccessor(sinkMBB);
19265 MI->eraseFromParent();
19269 MachineBasicBlock *
19270 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19271 MachineBasicBlock *MBB) const {
19272 DebugLoc DL = MI->getDebugLoc();
19273 MachineFunction *MF = MBB->getParent();
19274 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19275 MachineRegisterInfo &MRI = MF->getRegInfo();
19277 // Memory Reference
19278 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19279 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19281 MVT PVT = getPointerTy();
19282 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19283 "Invalid Pointer Size!");
19285 const TargetRegisterClass *RC =
19286 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19287 unsigned Tmp = MRI.createVirtualRegister(RC);
19288 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19289 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19290 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19291 unsigned SP = RegInfo->getStackRegister();
19293 MachineInstrBuilder MIB;
19295 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19296 const int64_t SPOffset = 2 * PVT.getStoreSize();
19298 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19299 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19302 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19303 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19304 MIB.addOperand(MI->getOperand(i));
19305 MIB.setMemRefs(MMOBegin, MMOEnd);
19307 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19308 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19309 if (i == X86::AddrDisp)
19310 MIB.addDisp(MI->getOperand(i), LabelOffset);
19312 MIB.addOperand(MI->getOperand(i));
19314 MIB.setMemRefs(MMOBegin, MMOEnd);
19316 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19317 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19318 if (i == X86::AddrDisp)
19319 MIB.addDisp(MI->getOperand(i), SPOffset);
19321 MIB.addOperand(MI->getOperand(i));
19323 MIB.setMemRefs(MMOBegin, MMOEnd);
19325 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19327 MI->eraseFromParent();
19331 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19332 // accumulator loops. Writing back to the accumulator allows the coalescer
19333 // to remove extra copies in the loop.
19334 MachineBasicBlock *
19335 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19336 MachineBasicBlock *MBB) const {
19337 MachineOperand &AddendOp = MI->getOperand(3);
19339 // Bail out early if the addend isn't a register - we can't switch these.
19340 if (!AddendOp.isReg())
19343 MachineFunction &MF = *MBB->getParent();
19344 MachineRegisterInfo &MRI = MF.getRegInfo();
19346 // Check whether the addend is defined by a PHI:
19347 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19348 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19349 if (!AddendDef.isPHI())
19352 // Look for the following pattern:
19354 // %addend = phi [%entry, 0], [%loop, %result]
19356 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19360 // %addend = phi [%entry, 0], [%loop, %result]
19362 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19364 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19365 assert(AddendDef.getOperand(i).isReg());
19366 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19367 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19368 if (&PHISrcInst == MI) {
19369 // Found a matching instruction.
19370 unsigned NewFMAOpc = 0;
19371 switch (MI->getOpcode()) {
19372 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19373 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19374 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19375 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19376 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19377 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19378 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19379 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19380 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19381 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19382 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19383 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19384 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19385 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19386 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19387 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19388 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19389 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19390 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19391 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19393 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19394 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19395 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19396 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19397 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19398 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19399 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19400 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19401 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19402 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19403 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19404 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19405 default: llvm_unreachable("Unrecognized FMA variant.");
19408 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19409 MachineInstrBuilder MIB =
19410 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19411 .addOperand(MI->getOperand(0))
19412 .addOperand(MI->getOperand(3))
19413 .addOperand(MI->getOperand(2))
19414 .addOperand(MI->getOperand(1));
19415 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19416 MI->eraseFromParent();
19423 MachineBasicBlock *
19424 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19425 MachineBasicBlock *BB) const {
19426 switch (MI->getOpcode()) {
19427 default: llvm_unreachable("Unexpected instr type to insert");
19428 case X86::TAILJMPd64:
19429 case X86::TAILJMPr64:
19430 case X86::TAILJMPm64:
19431 case X86::TAILJMPd64_REX:
19432 case X86::TAILJMPr64_REX:
19433 case X86::TAILJMPm64_REX:
19434 llvm_unreachable("TAILJMP64 would not be touched here.");
19435 case X86::TCRETURNdi64:
19436 case X86::TCRETURNri64:
19437 case X86::TCRETURNmi64:
19439 case X86::WIN_ALLOCA:
19440 return EmitLoweredWinAlloca(MI, BB);
19441 case X86::SEG_ALLOCA_32:
19442 case X86::SEG_ALLOCA_64:
19443 return EmitLoweredSegAlloca(MI, BB);
19444 case X86::TLSCall_32:
19445 case X86::TLSCall_64:
19446 return EmitLoweredTLSCall(MI, BB);
19447 case X86::CMOV_GR8:
19448 case X86::CMOV_FR32:
19449 case X86::CMOV_FR64:
19450 case X86::CMOV_V4F32:
19451 case X86::CMOV_V2F64:
19452 case X86::CMOV_V2I64:
19453 case X86::CMOV_V8F32:
19454 case X86::CMOV_V4F64:
19455 case X86::CMOV_V4I64:
19456 case X86::CMOV_V16F32:
19457 case X86::CMOV_V8F64:
19458 case X86::CMOV_V8I64:
19459 case X86::CMOV_GR16:
19460 case X86::CMOV_GR32:
19461 case X86::CMOV_RFP32:
19462 case X86::CMOV_RFP64:
19463 case X86::CMOV_RFP80:
19464 case X86::CMOV_V8I1:
19465 case X86::CMOV_V16I1:
19466 case X86::CMOV_V32I1:
19467 case X86::CMOV_V64I1:
19468 return EmitLoweredSelect(MI, BB);
19470 case X86::FP32_TO_INT16_IN_MEM:
19471 case X86::FP32_TO_INT32_IN_MEM:
19472 case X86::FP32_TO_INT64_IN_MEM:
19473 case X86::FP64_TO_INT16_IN_MEM:
19474 case X86::FP64_TO_INT32_IN_MEM:
19475 case X86::FP64_TO_INT64_IN_MEM:
19476 case X86::FP80_TO_INT16_IN_MEM:
19477 case X86::FP80_TO_INT32_IN_MEM:
19478 case X86::FP80_TO_INT64_IN_MEM: {
19479 MachineFunction *F = BB->getParent();
19480 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19481 DebugLoc DL = MI->getDebugLoc();
19483 // Change the floating point control register to use "round towards zero"
19484 // mode when truncating to an integer value.
19485 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19486 addFrameReference(BuildMI(*BB, MI, DL,
19487 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19489 // Load the old value of the high byte of the control word...
19491 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19492 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19495 // Set the high part to be round to zero...
19496 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19499 // Reload the modified control word now...
19500 addFrameReference(BuildMI(*BB, MI, DL,
19501 TII->get(X86::FLDCW16m)), CWFrameIdx);
19503 // Restore the memory image of control word to original value
19504 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19507 // Get the X86 opcode to use.
19509 switch (MI->getOpcode()) {
19510 default: llvm_unreachable("illegal opcode!");
19511 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19512 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19513 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19514 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19515 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19516 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19517 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19518 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19519 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19523 MachineOperand &Op = MI->getOperand(0);
19525 AM.BaseType = X86AddressMode::RegBase;
19526 AM.Base.Reg = Op.getReg();
19528 AM.BaseType = X86AddressMode::FrameIndexBase;
19529 AM.Base.FrameIndex = Op.getIndex();
19531 Op = MI->getOperand(1);
19533 AM.Scale = Op.getImm();
19534 Op = MI->getOperand(2);
19536 AM.IndexReg = Op.getImm();
19537 Op = MI->getOperand(3);
19538 if (Op.isGlobal()) {
19539 AM.GV = Op.getGlobal();
19541 AM.Disp = Op.getImm();
19543 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19544 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19546 // Reload the original control word now.
19547 addFrameReference(BuildMI(*BB, MI, DL,
19548 TII->get(X86::FLDCW16m)), CWFrameIdx);
19550 MI->eraseFromParent(); // The pseudo instruction is gone now.
19553 // String/text processing lowering.
19554 case X86::PCMPISTRM128REG:
19555 case X86::VPCMPISTRM128REG:
19556 case X86::PCMPISTRM128MEM:
19557 case X86::VPCMPISTRM128MEM:
19558 case X86::PCMPESTRM128REG:
19559 case X86::VPCMPESTRM128REG:
19560 case X86::PCMPESTRM128MEM:
19561 case X86::VPCMPESTRM128MEM:
19562 assert(Subtarget->hasSSE42() &&
19563 "Target must have SSE4.2 or AVX features enabled");
19564 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19566 // String/text processing lowering.
19567 case X86::PCMPISTRIREG:
19568 case X86::VPCMPISTRIREG:
19569 case X86::PCMPISTRIMEM:
19570 case X86::VPCMPISTRIMEM:
19571 case X86::PCMPESTRIREG:
19572 case X86::VPCMPESTRIREG:
19573 case X86::PCMPESTRIMEM:
19574 case X86::VPCMPESTRIMEM:
19575 assert(Subtarget->hasSSE42() &&
19576 "Target must have SSE4.2 or AVX features enabled");
19577 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19579 // Thread synchronization.
19581 return EmitMonitor(MI, BB, Subtarget);
19585 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19587 case X86::VASTART_SAVE_XMM_REGS:
19588 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19590 case X86::VAARG_64:
19591 return EmitVAARG64WithCustomInserter(MI, BB);
19593 case X86::EH_SjLj_SetJmp32:
19594 case X86::EH_SjLj_SetJmp64:
19595 return emitEHSjLjSetJmp(MI, BB);
19597 case X86::EH_SjLj_LongJmp32:
19598 case X86::EH_SjLj_LongJmp64:
19599 return emitEHSjLjLongJmp(MI, BB);
19601 case TargetOpcode::STATEPOINT:
19602 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19603 // this point in the process. We diverge later.
19604 return emitPatchPoint(MI, BB);
19606 case TargetOpcode::STACKMAP:
19607 case TargetOpcode::PATCHPOINT:
19608 return emitPatchPoint(MI, BB);
19610 case X86::VFMADDPDr213r:
19611 case X86::VFMADDPSr213r:
19612 case X86::VFMADDSDr213r:
19613 case X86::VFMADDSSr213r:
19614 case X86::VFMSUBPDr213r:
19615 case X86::VFMSUBPSr213r:
19616 case X86::VFMSUBSDr213r:
19617 case X86::VFMSUBSSr213r:
19618 case X86::VFNMADDPDr213r:
19619 case X86::VFNMADDPSr213r:
19620 case X86::VFNMADDSDr213r:
19621 case X86::VFNMADDSSr213r:
19622 case X86::VFNMSUBPDr213r:
19623 case X86::VFNMSUBPSr213r:
19624 case X86::VFNMSUBSDr213r:
19625 case X86::VFNMSUBSSr213r:
19626 case X86::VFMADDSUBPDr213r:
19627 case X86::VFMADDSUBPSr213r:
19628 case X86::VFMSUBADDPDr213r:
19629 case X86::VFMSUBADDPSr213r:
19630 case X86::VFMADDPDr213rY:
19631 case X86::VFMADDPSr213rY:
19632 case X86::VFMSUBPDr213rY:
19633 case X86::VFMSUBPSr213rY:
19634 case X86::VFNMADDPDr213rY:
19635 case X86::VFNMADDPSr213rY:
19636 case X86::VFNMSUBPDr213rY:
19637 case X86::VFNMSUBPSr213rY:
19638 case X86::VFMADDSUBPDr213rY:
19639 case X86::VFMADDSUBPSr213rY:
19640 case X86::VFMSUBADDPDr213rY:
19641 case X86::VFMSUBADDPSr213rY:
19642 return emitFMA3Instr(MI, BB);
19646 //===----------------------------------------------------------------------===//
19647 // X86 Optimization Hooks
19648 //===----------------------------------------------------------------------===//
19650 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19653 const SelectionDAG &DAG,
19654 unsigned Depth) const {
19655 unsigned BitWidth = KnownZero.getBitWidth();
19656 unsigned Opc = Op.getOpcode();
19657 assert((Opc >= ISD::BUILTIN_OP_END ||
19658 Opc == ISD::INTRINSIC_WO_CHAIN ||
19659 Opc == ISD::INTRINSIC_W_CHAIN ||
19660 Opc == ISD::INTRINSIC_VOID) &&
19661 "Should use MaskedValueIsZero if you don't know whether Op"
19662 " is a target node!");
19664 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19678 // These nodes' second result is a boolean.
19679 if (Op.getResNo() == 0)
19682 case X86ISD::SETCC:
19683 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19685 case ISD::INTRINSIC_WO_CHAIN: {
19686 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19687 unsigned NumLoBits = 0;
19690 case Intrinsic::x86_sse_movmsk_ps:
19691 case Intrinsic::x86_avx_movmsk_ps_256:
19692 case Intrinsic::x86_sse2_movmsk_pd:
19693 case Intrinsic::x86_avx_movmsk_pd_256:
19694 case Intrinsic::x86_mmx_pmovmskb:
19695 case Intrinsic::x86_sse2_pmovmskb_128:
19696 case Intrinsic::x86_avx2_pmovmskb: {
19697 // High bits of movmskp{s|d}, pmovmskb are known zero.
19699 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19700 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19701 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19702 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19703 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19704 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19705 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19706 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19708 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19717 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19719 const SelectionDAG &,
19720 unsigned Depth) const {
19721 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19722 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19723 return Op.getValueType().getScalarType().getSizeInBits();
19729 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19730 /// node is a GlobalAddress + offset.
19731 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19732 const GlobalValue* &GA,
19733 int64_t &Offset) const {
19734 if (N->getOpcode() == X86ISD::Wrapper) {
19735 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19736 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19737 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19741 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19744 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19745 /// same as extracting the high 128-bit part of 256-bit vector and then
19746 /// inserting the result into the low part of a new 256-bit vector
19747 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19748 EVT VT = SVOp->getValueType(0);
19749 unsigned NumElems = VT.getVectorNumElements();
19751 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19752 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19753 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19754 SVOp->getMaskElt(j) >= 0)
19760 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19761 /// same as extracting the low 128-bit part of 256-bit vector and then
19762 /// inserting the result into the high part of a new 256-bit vector
19763 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19764 EVT VT = SVOp->getValueType(0);
19765 unsigned NumElems = VT.getVectorNumElements();
19767 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19768 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19769 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19770 SVOp->getMaskElt(j) >= 0)
19776 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19777 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19778 TargetLowering::DAGCombinerInfo &DCI,
19779 const X86Subtarget* Subtarget) {
19781 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19782 SDValue V1 = SVOp->getOperand(0);
19783 SDValue V2 = SVOp->getOperand(1);
19784 EVT VT = SVOp->getValueType(0);
19785 unsigned NumElems = VT.getVectorNumElements();
19787 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19788 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19792 // V UNDEF BUILD_VECTOR UNDEF
19794 // CONCAT_VECTOR CONCAT_VECTOR
19797 // RESULT: V + zero extended
19799 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19800 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19801 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19804 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19807 // To match the shuffle mask, the first half of the mask should
19808 // be exactly the first vector, and all the rest a splat with the
19809 // first element of the second one.
19810 for (unsigned i = 0; i != NumElems/2; ++i)
19811 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19812 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19815 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19816 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19817 if (Ld->hasNUsesOfValue(1, 0)) {
19818 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19819 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19821 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19823 Ld->getPointerInfo(),
19824 Ld->getAlignment(),
19825 false/*isVolatile*/, true/*ReadMem*/,
19826 false/*WriteMem*/);
19828 // Make sure the newly-created LOAD is in the same position as Ld in
19829 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19830 // and update uses of Ld's output chain to use the TokenFactor.
19831 if (Ld->hasAnyUseOfValue(1)) {
19832 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19833 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19834 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19835 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19836 SDValue(ResNode.getNode(), 1));
19839 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19843 // Emit a zeroed vector and insert the desired subvector on its
19845 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19846 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19847 return DCI.CombineTo(N, InsV);
19850 //===--------------------------------------------------------------------===//
19851 // Combine some shuffles into subvector extracts and inserts:
19854 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19855 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19856 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19857 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19858 return DCI.CombineTo(N, InsV);
19861 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19862 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19863 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19864 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19865 return DCI.CombineTo(N, InsV);
19871 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19874 /// This is the leaf of the recursive combinine below. When we have found some
19875 /// chain of single-use x86 shuffle instructions and accumulated the combined
19876 /// shuffle mask represented by them, this will try to pattern match that mask
19877 /// into either a single instruction if there is a special purpose instruction
19878 /// for this operation, or into a PSHUFB instruction which is a fully general
19879 /// instruction but should only be used to replace chains over a certain depth.
19880 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19881 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19882 TargetLowering::DAGCombinerInfo &DCI,
19883 const X86Subtarget *Subtarget) {
19884 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19886 // Find the operand that enters the chain. Note that multiple uses are OK
19887 // here, we're not going to remove the operand we find.
19888 SDValue Input = Op.getOperand(0);
19889 while (Input.getOpcode() == ISD::BITCAST)
19890 Input = Input.getOperand(0);
19892 MVT VT = Input.getSimpleValueType();
19893 MVT RootVT = Root.getSimpleValueType();
19896 // Just remove no-op shuffle masks.
19897 if (Mask.size() == 1) {
19898 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19903 // Use the float domain if the operand type is a floating point type.
19904 bool FloatDomain = VT.isFloatingPoint();
19906 // For floating point shuffles, we don't have free copies in the shuffle
19907 // instructions or the ability to load as part of the instruction, so
19908 // canonicalize their shuffles to UNPCK or MOV variants.
19910 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19911 // vectors because it can have a load folded into it that UNPCK cannot. This
19912 // doesn't preclude something switching to the shorter encoding post-RA.
19914 // FIXME: Should teach these routines about AVX vector widths.
19915 if (FloatDomain && VT.getSizeInBits() == 128) {
19916 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
19917 bool Lo = Mask.equals({0, 0});
19920 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19921 // is no slower than UNPCKLPD but has the option to fold the input operand
19922 // into even an unaligned memory load.
19923 if (Lo && Subtarget->hasSSE3()) {
19924 Shuffle = X86ISD::MOVDDUP;
19925 ShuffleVT = MVT::v2f64;
19927 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19928 // than the UNPCK variants.
19929 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19930 ShuffleVT = MVT::v4f32;
19932 if (Depth == 1 && Root->getOpcode() == Shuffle)
19933 return false; // Nothing to do!
19934 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19935 DCI.AddToWorklist(Op.getNode());
19936 if (Shuffle == X86ISD::MOVDDUP)
19937 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19939 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19940 DCI.AddToWorklist(Op.getNode());
19941 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19945 if (Subtarget->hasSSE3() &&
19946 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
19947 bool Lo = Mask.equals({0, 0, 2, 2});
19948 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19949 MVT ShuffleVT = MVT::v4f32;
19950 if (Depth == 1 && Root->getOpcode() == Shuffle)
19951 return false; // Nothing to do!
19952 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19953 DCI.AddToWorklist(Op.getNode());
19954 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19955 DCI.AddToWorklist(Op.getNode());
19956 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19960 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
19961 bool Lo = Mask.equals({0, 0, 1, 1});
19962 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19963 MVT ShuffleVT = MVT::v4f32;
19964 if (Depth == 1 && Root->getOpcode() == Shuffle)
19965 return false; // Nothing to do!
19966 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19967 DCI.AddToWorklist(Op.getNode());
19968 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19969 DCI.AddToWorklist(Op.getNode());
19970 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19976 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19977 // variants as none of these have single-instruction variants that are
19978 // superior to the UNPCK formulation.
19979 if (!FloatDomain && VT.getSizeInBits() == 128 &&
19980 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
19981 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
19982 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
19984 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
19985 bool Lo = Mask[0] == 0;
19986 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19987 if (Depth == 1 && Root->getOpcode() == Shuffle)
19988 return false; // Nothing to do!
19990 switch (Mask.size()) {
19992 ShuffleVT = MVT::v8i16;
19995 ShuffleVT = MVT::v16i8;
19998 llvm_unreachable("Impossible mask size!");
20000 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20001 DCI.AddToWorklist(Op.getNode());
20002 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20003 DCI.AddToWorklist(Op.getNode());
20004 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20009 // Don't try to re-form single instruction chains under any circumstances now
20010 // that we've done encoding canonicalization for them.
20014 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20015 // can replace them with a single PSHUFB instruction profitably. Intel's
20016 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20017 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20018 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20019 SmallVector<SDValue, 16> PSHUFBMask;
20020 int NumBytes = VT.getSizeInBits() / 8;
20021 int Ratio = NumBytes / Mask.size();
20022 for (int i = 0; i < NumBytes; ++i) {
20023 if (Mask[i / Ratio] == SM_SentinelUndef) {
20024 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20027 int M = Mask[i / Ratio] != SM_SentinelZero
20028 ? Ratio * Mask[i / Ratio] + i % Ratio
20030 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20032 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20033 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
20034 DCI.AddToWorklist(Op.getNode());
20035 SDValue PSHUFBMaskOp =
20036 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20037 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20038 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20039 DCI.AddToWorklist(Op.getNode());
20040 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20045 // Failed to find any combines.
20049 /// \brief Fully generic combining of x86 shuffle instructions.
20051 /// This should be the last combine run over the x86 shuffle instructions. Once
20052 /// they have been fully optimized, this will recursively consider all chains
20053 /// of single-use shuffle instructions, build a generic model of the cumulative
20054 /// shuffle operation, and check for simpler instructions which implement this
20055 /// operation. We use this primarily for two purposes:
20057 /// 1) Collapse generic shuffles to specialized single instructions when
20058 /// equivalent. In most cases, this is just an encoding size win, but
20059 /// sometimes we will collapse multiple generic shuffles into a single
20060 /// special-purpose shuffle.
20061 /// 2) Look for sequences of shuffle instructions with 3 or more total
20062 /// instructions, and replace them with the slightly more expensive SSSE3
20063 /// PSHUFB instruction if available. We do this as the last combining step
20064 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20065 /// a suitable short sequence of other instructions. The PHUFB will either
20066 /// use a register or have to read from memory and so is slightly (but only
20067 /// slightly) more expensive than the other shuffle instructions.
20069 /// Because this is inherently a quadratic operation (for each shuffle in
20070 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20071 /// This should never be an issue in practice as the shuffle lowering doesn't
20072 /// produce sequences of more than 8 instructions.
20074 /// FIXME: We will currently miss some cases where the redundant shuffling
20075 /// would simplify under the threshold for PSHUFB formation because of
20076 /// combine-ordering. To fix this, we should do the redundant instruction
20077 /// combining in this recursive walk.
20078 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20079 ArrayRef<int> RootMask,
20080 int Depth, bool HasPSHUFB,
20082 TargetLowering::DAGCombinerInfo &DCI,
20083 const X86Subtarget *Subtarget) {
20084 // Bound the depth of our recursive combine because this is ultimately
20085 // quadratic in nature.
20089 // Directly rip through bitcasts to find the underlying operand.
20090 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20091 Op = Op.getOperand(0);
20093 MVT VT = Op.getSimpleValueType();
20094 if (!VT.isVector())
20095 return false; // Bail if we hit a non-vector.
20097 assert(Root.getSimpleValueType().isVector() &&
20098 "Shuffles operate on vector types!");
20099 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20100 "Can only combine shuffles of the same vector register size.");
20102 if (!isTargetShuffle(Op.getOpcode()))
20104 SmallVector<int, 16> OpMask;
20106 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20107 // We only can combine unary shuffles which we can decode the mask for.
20108 if (!HaveMask || !IsUnary)
20111 assert(VT.getVectorNumElements() == OpMask.size() &&
20112 "Different mask size from vector size!");
20113 assert(((RootMask.size() > OpMask.size() &&
20114 RootMask.size() % OpMask.size() == 0) ||
20115 (OpMask.size() > RootMask.size() &&
20116 OpMask.size() % RootMask.size() == 0) ||
20117 OpMask.size() == RootMask.size()) &&
20118 "The smaller number of elements must divide the larger.");
20119 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20120 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20121 assert(((RootRatio == 1 && OpRatio == 1) ||
20122 (RootRatio == 1) != (OpRatio == 1)) &&
20123 "Must not have a ratio for both incoming and op masks!");
20125 SmallVector<int, 16> Mask;
20126 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20128 // Merge this shuffle operation's mask into our accumulated mask. Note that
20129 // this shuffle's mask will be the first applied to the input, followed by the
20130 // root mask to get us all the way to the root value arrangement. The reason
20131 // for this order is that we are recursing up the operation chain.
20132 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20133 int RootIdx = i / RootRatio;
20134 if (RootMask[RootIdx] < 0) {
20135 // This is a zero or undef lane, we're done.
20136 Mask.push_back(RootMask[RootIdx]);
20140 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20141 int OpIdx = RootMaskedIdx / OpRatio;
20142 if (OpMask[OpIdx] < 0) {
20143 // The incoming lanes are zero or undef, it doesn't matter which ones we
20145 Mask.push_back(OpMask[OpIdx]);
20149 // Ok, we have non-zero lanes, map them through.
20150 Mask.push_back(OpMask[OpIdx] * OpRatio +
20151 RootMaskedIdx % OpRatio);
20154 // See if we can recurse into the operand to combine more things.
20155 switch (Op.getOpcode()) {
20156 case X86ISD::PSHUFB:
20158 case X86ISD::PSHUFD:
20159 case X86ISD::PSHUFHW:
20160 case X86ISD::PSHUFLW:
20161 if (Op.getOperand(0).hasOneUse() &&
20162 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20163 HasPSHUFB, DAG, DCI, Subtarget))
20167 case X86ISD::UNPCKL:
20168 case X86ISD::UNPCKH:
20169 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20170 // We can't check for single use, we have to check that this shuffle is the only user.
20171 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20172 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20173 HasPSHUFB, DAG, DCI, Subtarget))
20178 // Minor canonicalization of the accumulated shuffle mask to make it easier
20179 // to match below. All this does is detect masks with squential pairs of
20180 // elements, and shrink them to the half-width mask. It does this in a loop
20181 // so it will reduce the size of the mask to the minimal width mask which
20182 // performs an equivalent shuffle.
20183 SmallVector<int, 16> WidenedMask;
20184 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20185 Mask = std::move(WidenedMask);
20186 WidenedMask.clear();
20189 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20193 /// \brief Get the PSHUF-style mask from PSHUF node.
20195 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20196 /// PSHUF-style masks that can be reused with such instructions.
20197 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20198 MVT VT = N.getSimpleValueType();
20199 SmallVector<int, 4> Mask;
20201 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20205 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20206 // matter. Check that the upper masks are repeats and remove them.
20207 if (VT.getSizeInBits() > 128) {
20208 int LaneElts = 128 / VT.getScalarSizeInBits();
20210 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20211 for (int j = 0; j < LaneElts; ++j)
20212 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
20213 "Mask doesn't repeat in high 128-bit lanes!");
20215 Mask.resize(LaneElts);
20218 switch (N.getOpcode()) {
20219 case X86ISD::PSHUFD:
20221 case X86ISD::PSHUFLW:
20224 case X86ISD::PSHUFHW:
20225 Mask.erase(Mask.begin(), Mask.begin() + 4);
20226 for (int &M : Mask)
20230 llvm_unreachable("No valid shuffle instruction found!");
20234 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20236 /// We walk up the chain and look for a combinable shuffle, skipping over
20237 /// shuffles that we could hoist this shuffle's transformation past without
20238 /// altering anything.
20240 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20242 TargetLowering::DAGCombinerInfo &DCI) {
20243 assert(N.getOpcode() == X86ISD::PSHUFD &&
20244 "Called with something other than an x86 128-bit half shuffle!");
20247 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20248 // of the shuffles in the chain so that we can form a fresh chain to replace
20250 SmallVector<SDValue, 8> Chain;
20251 SDValue V = N.getOperand(0);
20252 for (; V.hasOneUse(); V = V.getOperand(0)) {
20253 switch (V.getOpcode()) {
20255 return SDValue(); // Nothing combined!
20258 // Skip bitcasts as we always know the type for the target specific
20262 case X86ISD::PSHUFD:
20263 // Found another dword shuffle.
20266 case X86ISD::PSHUFLW:
20267 // Check that the low words (being shuffled) are the identity in the
20268 // dword shuffle, and the high words are self-contained.
20269 if (Mask[0] != 0 || Mask[1] != 1 ||
20270 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20273 Chain.push_back(V);
20276 case X86ISD::PSHUFHW:
20277 // Check that the high words (being shuffled) are the identity in the
20278 // dword shuffle, and the low words are self-contained.
20279 if (Mask[2] != 2 || Mask[3] != 3 ||
20280 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20283 Chain.push_back(V);
20286 case X86ISD::UNPCKL:
20287 case X86ISD::UNPCKH:
20288 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20289 // shuffle into a preceding word shuffle.
20290 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20291 V.getSimpleValueType().getScalarType() != MVT::i16)
20294 // Search for a half-shuffle which we can combine with.
20295 unsigned CombineOp =
20296 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20297 if (V.getOperand(0) != V.getOperand(1) ||
20298 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20300 Chain.push_back(V);
20301 V = V.getOperand(0);
20303 switch (V.getOpcode()) {
20305 return SDValue(); // Nothing to combine.
20307 case X86ISD::PSHUFLW:
20308 case X86ISD::PSHUFHW:
20309 if (V.getOpcode() == CombineOp)
20312 Chain.push_back(V);
20316 V = V.getOperand(0);
20320 } while (V.hasOneUse());
20323 // Break out of the loop if we break out of the switch.
20327 if (!V.hasOneUse())
20328 // We fell out of the loop without finding a viable combining instruction.
20331 // Merge this node's mask and our incoming mask.
20332 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20333 for (int &M : Mask)
20335 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20336 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20338 // Rebuild the chain around this new shuffle.
20339 while (!Chain.empty()) {
20340 SDValue W = Chain.pop_back_val();
20342 if (V.getValueType() != W.getOperand(0).getValueType())
20343 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20345 switch (W.getOpcode()) {
20347 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20349 case X86ISD::UNPCKL:
20350 case X86ISD::UNPCKH:
20351 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20354 case X86ISD::PSHUFD:
20355 case X86ISD::PSHUFLW:
20356 case X86ISD::PSHUFHW:
20357 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20361 if (V.getValueType() != N.getValueType())
20362 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20364 // Return the new chain to replace N.
20368 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20370 /// We walk up the chain, skipping shuffles of the other half and looking
20371 /// through shuffles which switch halves trying to find a shuffle of the same
20372 /// pair of dwords.
20373 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20375 TargetLowering::DAGCombinerInfo &DCI) {
20377 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20378 "Called with something other than an x86 128-bit half shuffle!");
20380 unsigned CombineOpcode = N.getOpcode();
20382 // Walk up a single-use chain looking for a combinable shuffle.
20383 SDValue V = N.getOperand(0);
20384 for (; V.hasOneUse(); V = V.getOperand(0)) {
20385 switch (V.getOpcode()) {
20387 return false; // Nothing combined!
20390 // Skip bitcasts as we always know the type for the target specific
20394 case X86ISD::PSHUFLW:
20395 case X86ISD::PSHUFHW:
20396 if (V.getOpcode() == CombineOpcode)
20399 // Other-half shuffles are no-ops.
20402 // Break out of the loop if we break out of the switch.
20406 if (!V.hasOneUse())
20407 // We fell out of the loop without finding a viable combining instruction.
20410 // Combine away the bottom node as its shuffle will be accumulated into
20411 // a preceding shuffle.
20412 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20414 // Record the old value.
20417 // Merge this node's mask and our incoming mask (adjusted to account for all
20418 // the pshufd instructions encountered).
20419 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20420 for (int &M : Mask)
20422 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20423 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20425 // Check that the shuffles didn't cancel each other out. If not, we need to
20426 // combine to the new one.
20428 // Replace the combinable shuffle with the combined one, updating all users
20429 // so that we re-evaluate the chain here.
20430 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20435 /// \brief Try to combine x86 target specific shuffles.
20436 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20437 TargetLowering::DAGCombinerInfo &DCI,
20438 const X86Subtarget *Subtarget) {
20440 MVT VT = N.getSimpleValueType();
20441 SmallVector<int, 4> Mask;
20443 switch (N.getOpcode()) {
20444 case X86ISD::PSHUFD:
20445 case X86ISD::PSHUFLW:
20446 case X86ISD::PSHUFHW:
20447 Mask = getPSHUFShuffleMask(N);
20448 assert(Mask.size() == 4);
20454 // Nuke no-op shuffles that show up after combining.
20455 if (isNoopShuffleMask(Mask))
20456 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20458 // Look for simplifications involving one or two shuffle instructions.
20459 SDValue V = N.getOperand(0);
20460 switch (N.getOpcode()) {
20463 case X86ISD::PSHUFLW:
20464 case X86ISD::PSHUFHW:
20465 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20467 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20468 return SDValue(); // We combined away this shuffle, so we're done.
20470 // See if this reduces to a PSHUFD which is no more expensive and can
20471 // combine with more operations. Note that it has to at least flip the
20472 // dwords as otherwise it would have been removed as a no-op.
20473 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20474 int DMask[] = {0, 1, 2, 3};
20475 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20476 DMask[DOffset + 0] = DOffset + 1;
20477 DMask[DOffset + 1] = DOffset + 0;
20478 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20479 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20480 DCI.AddToWorklist(V.getNode());
20481 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20482 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20483 DCI.AddToWorklist(V.getNode());
20484 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20487 // Look for shuffle patterns which can be implemented as a single unpack.
20488 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20489 // only works when we have a PSHUFD followed by two half-shuffles.
20490 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20491 (V.getOpcode() == X86ISD::PSHUFLW ||
20492 V.getOpcode() == X86ISD::PSHUFHW) &&
20493 V.getOpcode() != N.getOpcode() &&
20495 SDValue D = V.getOperand(0);
20496 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20497 D = D.getOperand(0);
20498 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20499 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20500 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20501 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20502 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20504 for (int i = 0; i < 4; ++i) {
20505 WordMask[i + NOffset] = Mask[i] + NOffset;
20506 WordMask[i + VOffset] = VMask[i] + VOffset;
20508 // Map the word mask through the DWord mask.
20510 for (int i = 0; i < 8; ++i)
20511 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20512 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20513 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20514 // We can replace all three shuffles with an unpack.
20515 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20516 DCI.AddToWorklist(V.getNode());
20517 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20526 case X86ISD::PSHUFD:
20527 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20536 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20538 /// We combine this directly on the abstract vector shuffle nodes so it is
20539 /// easier to generically match. We also insert dummy vector shuffle nodes for
20540 /// the operands which explicitly discard the lanes which are unused by this
20541 /// operation to try to flow through the rest of the combiner the fact that
20542 /// they're unused.
20543 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20545 EVT VT = N->getValueType(0);
20547 // We only handle target-independent shuffles.
20548 // FIXME: It would be easy and harmless to use the target shuffle mask
20549 // extraction tool to support more.
20550 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20553 auto *SVN = cast<ShuffleVectorSDNode>(N);
20554 ArrayRef<int> Mask = SVN->getMask();
20555 SDValue V1 = N->getOperand(0);
20556 SDValue V2 = N->getOperand(1);
20558 // We require the first shuffle operand to be the SUB node, and the second to
20559 // be the ADD node.
20560 // FIXME: We should support the commuted patterns.
20561 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20564 // If there are other uses of these operations we can't fold them.
20565 if (!V1->hasOneUse() || !V2->hasOneUse())
20568 // Ensure that both operations have the same operands. Note that we can
20569 // commute the FADD operands.
20570 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20571 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20572 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20575 // We're looking for blends between FADD and FSUB nodes. We insist on these
20576 // nodes being lined up in a specific expected pattern.
20577 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20578 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20579 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20582 // Only specific types are legal at this point, assert so we notice if and
20583 // when these change.
20584 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20585 VT == MVT::v4f64) &&
20586 "Unknown vector type encountered!");
20588 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20591 /// PerformShuffleCombine - Performs several different shuffle combines.
20592 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20593 TargetLowering::DAGCombinerInfo &DCI,
20594 const X86Subtarget *Subtarget) {
20596 SDValue N0 = N->getOperand(0);
20597 SDValue N1 = N->getOperand(1);
20598 EVT VT = N->getValueType(0);
20600 // Don't create instructions with illegal types after legalize types has run.
20601 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20602 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20605 // If we have legalized the vector types, look for blends of FADD and FSUB
20606 // nodes that we can fuse into an ADDSUB node.
20607 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20608 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20611 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20612 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20613 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20614 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20616 // During Type Legalization, when promoting illegal vector types,
20617 // the backend might introduce new shuffle dag nodes and bitcasts.
20619 // This code performs the following transformation:
20620 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20621 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20623 // We do this only if both the bitcast and the BINOP dag nodes have
20624 // one use. Also, perform this transformation only if the new binary
20625 // operation is legal. This is to avoid introducing dag nodes that
20626 // potentially need to be further expanded (or custom lowered) into a
20627 // less optimal sequence of dag nodes.
20628 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20629 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20630 N0.getOpcode() == ISD::BITCAST) {
20631 SDValue BC0 = N0.getOperand(0);
20632 EVT SVT = BC0.getValueType();
20633 unsigned Opcode = BC0.getOpcode();
20634 unsigned NumElts = VT.getVectorNumElements();
20636 if (BC0.hasOneUse() && SVT.isVector() &&
20637 SVT.getVectorNumElements() * 2 == NumElts &&
20638 TLI.isOperationLegal(Opcode, VT)) {
20639 bool CanFold = false;
20651 unsigned SVTNumElts = SVT.getVectorNumElements();
20652 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20653 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20654 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20655 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20656 CanFold = SVOp->getMaskElt(i) < 0;
20659 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20660 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20661 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20662 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20667 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20668 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20669 // consecutive, non-overlapping, and in the right order.
20670 SmallVector<SDValue, 16> Elts;
20671 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20672 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20674 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20678 if (isTargetShuffle(N->getOpcode())) {
20680 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20681 if (Shuffle.getNode())
20684 // Try recursively combining arbitrary sequences of x86 shuffle
20685 // instructions into higher-order shuffles. We do this after combining
20686 // specific PSHUF instruction sequences into their minimal form so that we
20687 // can evaluate how many specialized shuffle instructions are involved in
20688 // a particular chain.
20689 SmallVector<int, 1> NonceMask; // Just a placeholder.
20690 NonceMask.push_back(0);
20691 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20692 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20694 return SDValue(); // This routine will use CombineTo to replace N.
20700 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20701 /// specific shuffle of a load can be folded into a single element load.
20702 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20703 /// shuffles have been custom lowered so we need to handle those here.
20704 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20705 TargetLowering::DAGCombinerInfo &DCI) {
20706 if (DCI.isBeforeLegalizeOps())
20709 SDValue InVec = N->getOperand(0);
20710 SDValue EltNo = N->getOperand(1);
20712 if (!isa<ConstantSDNode>(EltNo))
20715 EVT OriginalVT = InVec.getValueType();
20717 if (InVec.getOpcode() == ISD::BITCAST) {
20718 // Don't duplicate a load with other uses.
20719 if (!InVec.hasOneUse())
20721 EVT BCVT = InVec.getOperand(0).getValueType();
20722 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20724 InVec = InVec.getOperand(0);
20727 EVT CurrentVT = InVec.getValueType();
20729 if (!isTargetShuffle(InVec.getOpcode()))
20732 // Don't duplicate a load with other uses.
20733 if (!InVec.hasOneUse())
20736 SmallVector<int, 16> ShuffleMask;
20738 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20739 ShuffleMask, UnaryShuffle))
20742 // Select the input vector, guarding against out of range extract vector.
20743 unsigned NumElems = CurrentVT.getVectorNumElements();
20744 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20745 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20746 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20747 : InVec.getOperand(1);
20749 // If inputs to shuffle are the same for both ops, then allow 2 uses
20750 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20751 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20753 if (LdNode.getOpcode() == ISD::BITCAST) {
20754 // Don't duplicate a load with other uses.
20755 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20758 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20759 LdNode = LdNode.getOperand(0);
20762 if (!ISD::isNormalLoad(LdNode.getNode()))
20765 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20767 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20770 EVT EltVT = N->getValueType(0);
20771 // If there's a bitcast before the shuffle, check if the load type and
20772 // alignment is valid.
20773 unsigned Align = LN0->getAlignment();
20774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20775 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20776 EltVT.getTypeForEVT(*DAG.getContext()));
20778 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20781 // All checks match so transform back to vector_shuffle so that DAG combiner
20782 // can finish the job
20785 // Create shuffle node taking into account the case that its a unary shuffle
20786 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20787 : InVec.getOperand(1);
20788 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20789 InVec.getOperand(0), Shuffle,
20791 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20792 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20796 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20797 /// special and don't usually play with other vector types, it's better to
20798 /// handle them early to be sure we emit efficient code by avoiding
20799 /// store-load conversions.
20800 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20801 if (N->getValueType(0) != MVT::x86mmx ||
20802 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
20803 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20806 SDValue V = N->getOperand(0);
20807 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20808 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20809 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20810 N->getValueType(0), V.getOperand(0));
20815 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20816 /// generation and convert it from being a bunch of shuffles and extracts
20817 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20818 /// storing the value and loading scalars back, while for x64 we should
20819 /// use 64-bit extracts and shifts.
20820 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20821 TargetLowering::DAGCombinerInfo &DCI) {
20822 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20823 if (NewOp.getNode())
20826 SDValue InputVector = N->getOperand(0);
20828 // Detect mmx to i32 conversion through a v2i32 elt extract.
20829 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20830 N->getValueType(0) == MVT::i32 &&
20831 InputVector.getValueType() == MVT::v2i32) {
20833 // The bitcast source is a direct mmx result.
20834 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20835 if (MMXSrc.getValueType() == MVT::x86mmx)
20836 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20837 N->getValueType(0),
20838 InputVector.getNode()->getOperand(0));
20840 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20841 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20842 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20843 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20844 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20845 MMXSrcOp.getValueType() == MVT::v1i64 &&
20846 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20847 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20848 N->getValueType(0),
20849 MMXSrcOp.getOperand(0));
20852 // Only operate on vectors of 4 elements, where the alternative shuffling
20853 // gets to be more expensive.
20854 if (InputVector.getValueType() != MVT::v4i32)
20857 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20858 // single use which is a sign-extend or zero-extend, and all elements are
20860 SmallVector<SDNode *, 4> Uses;
20861 unsigned ExtractedElements = 0;
20862 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20863 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20864 if (UI.getUse().getResNo() != InputVector.getResNo())
20867 SDNode *Extract = *UI;
20868 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20871 if (Extract->getValueType(0) != MVT::i32)
20873 if (!Extract->hasOneUse())
20875 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20876 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20878 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20881 // Record which element was extracted.
20882 ExtractedElements |=
20883 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20885 Uses.push_back(Extract);
20888 // If not all the elements were used, this may not be worthwhile.
20889 if (ExtractedElements != 15)
20892 // Ok, we've now decided to do the transformation.
20893 // If 64-bit shifts are legal, use the extract-shift sequence,
20894 // otherwise bounce the vector off the cache.
20895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20897 SDLoc dl(InputVector);
20899 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20900 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20901 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20902 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20903 DAG.getConstant(0, dl, VecIdxTy));
20904 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20905 DAG.getConstant(1, dl, VecIdxTy));
20907 SDValue ShAmt = DAG.getConstant(32, dl,
20908 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20909 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20910 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20911 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20912 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20913 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20914 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20916 // Store the value to a temporary stack slot.
20917 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20918 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20919 MachinePointerInfo(), false, false, 0);
20921 EVT ElementType = InputVector.getValueType().getVectorElementType();
20922 unsigned EltSize = ElementType.getSizeInBits() / 8;
20924 // Replace each use (extract) with a load of the appropriate element.
20925 for (unsigned i = 0; i < 4; ++i) {
20926 uint64_t Offset = EltSize * i;
20927 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
20929 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20930 StackPtr, OffsetVal);
20932 // Load the scalar.
20933 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20934 ScalarAddr, MachinePointerInfo(),
20935 false, false, false, 0);
20940 // Replace the extracts
20941 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20942 UE = Uses.end(); UI != UE; ++UI) {
20943 SDNode *Extract = *UI;
20945 SDValue Idx = Extract->getOperand(1);
20946 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20947 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20950 // The replacement was made in place; don't return anything.
20954 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20955 static std::pair<unsigned, bool>
20956 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20957 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20958 if (!VT.isVector())
20959 return std::make_pair(0, false);
20961 bool NeedSplit = false;
20962 switch (VT.getSimpleVT().SimpleTy) {
20963 default: return std::make_pair(0, false);
20966 if (!Subtarget->hasVLX())
20967 return std::make_pair(0, false);
20971 if (!Subtarget->hasBWI())
20972 return std::make_pair(0, false);
20976 if (!Subtarget->hasAVX512())
20977 return std::make_pair(0, false);
20982 if (!Subtarget->hasAVX2())
20984 if (!Subtarget->hasAVX())
20985 return std::make_pair(0, false);
20990 if (!Subtarget->hasSSE2())
20991 return std::make_pair(0, false);
20994 // SSE2 has only a small subset of the operations.
20995 bool hasUnsigned = Subtarget->hasSSE41() ||
20996 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20997 bool hasSigned = Subtarget->hasSSE41() ||
20998 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21000 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21003 // Check for x CC y ? x : y.
21004 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21005 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21010 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21013 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21016 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21019 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21021 // Check for x CC y ? y : x -- a min/max with reversed arms.
21022 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21023 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21028 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21031 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21034 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21037 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21041 return std::make_pair(Opc, NeedSplit);
21045 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21046 const X86Subtarget *Subtarget) {
21048 SDValue Cond = N->getOperand(0);
21049 SDValue LHS = N->getOperand(1);
21050 SDValue RHS = N->getOperand(2);
21052 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21053 SDValue CondSrc = Cond->getOperand(0);
21054 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21055 Cond = CondSrc->getOperand(0);
21058 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21061 // A vselect where all conditions and data are constants can be optimized into
21062 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21063 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21064 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21067 unsigned MaskValue = 0;
21068 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21071 MVT VT = N->getSimpleValueType(0);
21072 unsigned NumElems = VT.getVectorNumElements();
21073 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21074 for (unsigned i = 0; i < NumElems; ++i) {
21075 // Be sure we emit undef where we can.
21076 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21077 ShuffleMask[i] = -1;
21079 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21083 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21085 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21088 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21090 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21091 TargetLowering::DAGCombinerInfo &DCI,
21092 const X86Subtarget *Subtarget) {
21094 SDValue Cond = N->getOperand(0);
21095 // Get the LHS/RHS of the select.
21096 SDValue LHS = N->getOperand(1);
21097 SDValue RHS = N->getOperand(2);
21098 EVT VT = LHS.getValueType();
21099 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21101 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21102 // instructions match the semantics of the common C idiom x<y?x:y but not
21103 // x<=y?x:y, because of how they handle negative zero (which can be
21104 // ignored in unsafe-math mode).
21105 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21106 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21107 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21108 (Subtarget->hasSSE2() ||
21109 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21110 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21112 unsigned Opcode = 0;
21113 // Check for x CC y ? x : y.
21114 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21115 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21119 // Converting this to a min would handle NaNs incorrectly, and swapping
21120 // the operands would cause it to handle comparisons between positive
21121 // and negative zero incorrectly.
21122 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21123 if (!DAG.getTarget().Options.UnsafeFPMath &&
21124 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21126 std::swap(LHS, RHS);
21128 Opcode = X86ISD::FMIN;
21131 // Converting this to a min would handle comparisons between positive
21132 // and negative zero incorrectly.
21133 if (!DAG.getTarget().Options.UnsafeFPMath &&
21134 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21136 Opcode = X86ISD::FMIN;
21139 // Converting this to a min would handle both negative zeros and NaNs
21140 // incorrectly, but we can swap the operands to fix both.
21141 std::swap(LHS, RHS);
21145 Opcode = X86ISD::FMIN;
21149 // Converting this to a max would handle comparisons between positive
21150 // and negative zero incorrectly.
21151 if (!DAG.getTarget().Options.UnsafeFPMath &&
21152 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21154 Opcode = X86ISD::FMAX;
21157 // Converting this to a max would handle NaNs incorrectly, and swapping
21158 // the operands would cause it to handle comparisons between positive
21159 // and negative zero incorrectly.
21160 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21161 if (!DAG.getTarget().Options.UnsafeFPMath &&
21162 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21164 std::swap(LHS, RHS);
21166 Opcode = X86ISD::FMAX;
21169 // Converting this to a max would handle both negative zeros and NaNs
21170 // incorrectly, but we can swap the operands to fix both.
21171 std::swap(LHS, RHS);
21175 Opcode = X86ISD::FMAX;
21178 // Check for x CC y ? y : x -- a min/max with reversed arms.
21179 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21180 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21184 // Converting this to a min would handle comparisons between positive
21185 // and negative zero incorrectly, and swapping the operands would
21186 // cause it to handle NaNs incorrectly.
21187 if (!DAG.getTarget().Options.UnsafeFPMath &&
21188 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21189 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21191 std::swap(LHS, RHS);
21193 Opcode = X86ISD::FMIN;
21196 // Converting this to a min would handle NaNs incorrectly.
21197 if (!DAG.getTarget().Options.UnsafeFPMath &&
21198 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21200 Opcode = X86ISD::FMIN;
21203 // Converting this to a min would handle both negative zeros and NaNs
21204 // incorrectly, but we can swap the operands to fix both.
21205 std::swap(LHS, RHS);
21209 Opcode = X86ISD::FMIN;
21213 // Converting this to a max would handle NaNs incorrectly.
21214 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21216 Opcode = X86ISD::FMAX;
21219 // Converting this to a max would handle comparisons between positive
21220 // and negative zero incorrectly, and swapping the operands would
21221 // cause it to handle NaNs incorrectly.
21222 if (!DAG.getTarget().Options.UnsafeFPMath &&
21223 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21224 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21226 std::swap(LHS, RHS);
21228 Opcode = X86ISD::FMAX;
21231 // Converting this to a max would handle both negative zeros and NaNs
21232 // incorrectly, but we can swap the operands to fix both.
21233 std::swap(LHS, RHS);
21237 Opcode = X86ISD::FMAX;
21243 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21246 EVT CondVT = Cond.getValueType();
21247 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21248 CondVT.getVectorElementType() == MVT::i1) {
21249 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21250 // lowering on KNL. In this case we convert it to
21251 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21252 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21253 // Since SKX these selects have a proper lowering.
21254 EVT OpVT = LHS.getValueType();
21255 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21256 (OpVT.getVectorElementType() == MVT::i8 ||
21257 OpVT.getVectorElementType() == MVT::i16) &&
21258 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21259 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21260 DCI.AddToWorklist(Cond.getNode());
21261 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21264 // If this is a select between two integer constants, try to do some
21266 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21267 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21268 // Don't do this for crazy integer types.
21269 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21270 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21271 // so that TrueC (the true value) is larger than FalseC.
21272 bool NeedsCondInvert = false;
21274 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21275 // Efficiently invertible.
21276 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21277 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21278 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21279 NeedsCondInvert = true;
21280 std::swap(TrueC, FalseC);
21283 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21284 if (FalseC->getAPIntValue() == 0 &&
21285 TrueC->getAPIntValue().isPowerOf2()) {
21286 if (NeedsCondInvert) // Invert the condition if needed.
21287 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21288 DAG.getConstant(1, DL, Cond.getValueType()));
21290 // Zero extend the condition if needed.
21291 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21293 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21294 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21295 DAG.getConstant(ShAmt, DL, MVT::i8));
21298 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21299 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21300 if (NeedsCondInvert) // Invert the condition if needed.
21301 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21302 DAG.getConstant(1, DL, Cond.getValueType()));
21304 // Zero extend the condition if needed.
21305 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21306 FalseC->getValueType(0), Cond);
21307 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21308 SDValue(FalseC, 0));
21311 // Optimize cases that will turn into an LEA instruction. This requires
21312 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21313 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21314 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21315 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21317 bool isFastMultiplier = false;
21319 switch ((unsigned char)Diff) {
21321 case 1: // result = add base, cond
21322 case 2: // result = lea base( , cond*2)
21323 case 3: // result = lea base(cond, cond*2)
21324 case 4: // result = lea base( , cond*4)
21325 case 5: // result = lea base(cond, cond*4)
21326 case 8: // result = lea base( , cond*8)
21327 case 9: // result = lea base(cond, cond*8)
21328 isFastMultiplier = true;
21333 if (isFastMultiplier) {
21334 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21335 if (NeedsCondInvert) // Invert the condition if needed.
21336 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21337 DAG.getConstant(1, DL, Cond.getValueType()));
21339 // Zero extend the condition if needed.
21340 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21342 // Scale the condition by the difference.
21344 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21345 DAG.getConstant(Diff, DL,
21346 Cond.getValueType()));
21348 // Add the base if non-zero.
21349 if (FalseC->getAPIntValue() != 0)
21350 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21351 SDValue(FalseC, 0));
21358 // Canonicalize max and min:
21359 // (x > y) ? x : y -> (x >= y) ? x : y
21360 // (x < y) ? x : y -> (x <= y) ? x : y
21361 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21362 // the need for an extra compare
21363 // against zero. e.g.
21364 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21366 // testl %edi, %edi
21368 // cmovgl %edi, %eax
21372 // cmovsl %eax, %edi
21373 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21374 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21375 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21376 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21381 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21382 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21383 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21384 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21389 // Early exit check
21390 if (!TLI.isTypeLegal(VT))
21393 // Match VSELECTs into subs with unsigned saturation.
21394 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21395 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21396 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21397 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21398 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21400 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21401 // left side invert the predicate to simplify logic below.
21403 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21405 CC = ISD::getSetCCInverse(CC, true);
21406 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21410 if (Other.getNode() && Other->getNumOperands() == 2 &&
21411 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21412 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21413 SDValue CondRHS = Cond->getOperand(1);
21415 // Look for a general sub with unsigned saturation first.
21416 // x >= y ? x-y : 0 --> subus x, y
21417 // x > y ? x-y : 0 --> subus x, y
21418 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21419 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21420 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21422 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21423 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21424 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21425 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21426 // If the RHS is a constant we have to reverse the const
21427 // canonicalization.
21428 // x > C-1 ? x+-C : 0 --> subus x, C
21429 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21430 CondRHSConst->getAPIntValue() ==
21431 (-OpRHSConst->getAPIntValue() - 1))
21432 return DAG.getNode(
21433 X86ISD::SUBUS, DL, VT, OpLHS,
21434 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21436 // Another special case: If C was a sign bit, the sub has been
21437 // canonicalized into a xor.
21438 // FIXME: Would it be better to use computeKnownBits to determine
21439 // whether it's safe to decanonicalize the xor?
21440 // x s< 0 ? x^C : 0 --> subus x, C
21441 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21442 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21443 OpRHSConst->getAPIntValue().isSignBit())
21444 // Note that we have to rebuild the RHS constant here to ensure we
21445 // don't rely on particular values of undef lanes.
21446 return DAG.getNode(
21447 X86ISD::SUBUS, DL, VT, OpLHS,
21448 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21453 // Try to match a min/max vector operation.
21454 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21455 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21456 unsigned Opc = ret.first;
21457 bool NeedSplit = ret.second;
21459 if (Opc && NeedSplit) {
21460 unsigned NumElems = VT.getVectorNumElements();
21461 // Extract the LHS vectors
21462 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21463 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21465 // Extract the RHS vectors
21466 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21467 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21469 // Create min/max for each subvector
21470 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21471 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21473 // Merge the result
21474 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21476 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21479 // Simplify vector selection if condition value type matches vselect
21481 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21482 assert(Cond.getValueType().isVector() &&
21483 "vector select expects a vector selector!");
21485 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21486 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21488 // Try invert the condition if true value is not all 1s and false value
21490 if (!TValIsAllOnes && !FValIsAllZeros &&
21491 // Check if the selector will be produced by CMPP*/PCMP*
21492 Cond.getOpcode() == ISD::SETCC &&
21493 // Check if SETCC has already been promoted
21494 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21495 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21496 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21498 if (TValIsAllZeros || FValIsAllOnes) {
21499 SDValue CC = Cond.getOperand(2);
21500 ISD::CondCode NewCC =
21501 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21502 Cond.getOperand(0).getValueType().isInteger());
21503 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21504 std::swap(LHS, RHS);
21505 TValIsAllOnes = FValIsAllOnes;
21506 FValIsAllZeros = TValIsAllZeros;
21510 if (TValIsAllOnes || FValIsAllZeros) {
21513 if (TValIsAllOnes && FValIsAllZeros)
21515 else if (TValIsAllOnes)
21516 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21517 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21518 else if (FValIsAllZeros)
21519 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21520 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21522 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21526 // We should generate an X86ISD::BLENDI from a vselect if its argument
21527 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21528 // constants. This specific pattern gets generated when we split a
21529 // selector for a 512 bit vector in a machine without AVX512 (but with
21530 // 256-bit vectors), during legalization:
21532 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21534 // Iff we find this pattern and the build_vectors are built from
21535 // constants, we translate the vselect into a shuffle_vector that we
21536 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21537 if ((N->getOpcode() == ISD::VSELECT ||
21538 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21539 !DCI.isBeforeLegalize()) {
21540 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21541 if (Shuffle.getNode())
21545 // If this is a *dynamic* select (non-constant condition) and we can match
21546 // this node with one of the variable blend instructions, restructure the
21547 // condition so that the blends can use the high bit of each element and use
21548 // SimplifyDemandedBits to simplify the condition operand.
21549 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21550 !DCI.isBeforeLegalize() &&
21551 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21552 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21554 // Don't optimize vector selects that map to mask-registers.
21558 // We can only handle the cases where VSELECT is directly legal on the
21559 // subtarget. We custom lower VSELECT nodes with constant conditions and
21560 // this makes it hard to see whether a dynamic VSELECT will correctly
21561 // lower, so we both check the operation's status and explicitly handle the
21562 // cases where a *dynamic* blend will fail even though a constant-condition
21563 // blend could be custom lowered.
21564 // FIXME: We should find a better way to handle this class of problems.
21565 // Potentially, we should combine constant-condition vselect nodes
21566 // pre-legalization into shuffles and not mark as many types as custom
21568 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21570 // FIXME: We don't support i16-element blends currently. We could and
21571 // should support them by making *all* the bits in the condition be set
21572 // rather than just the high bit and using an i8-element blend.
21573 if (VT.getScalarType() == MVT::i16)
21575 // Dynamic blending was only available from SSE4.1 onward.
21576 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21578 // Byte blends are only available in AVX2
21579 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21580 !Subtarget->hasAVX2())
21583 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21584 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21586 APInt KnownZero, KnownOne;
21587 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21588 DCI.isBeforeLegalizeOps());
21589 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21590 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21592 // If we changed the computation somewhere in the DAG, this change
21593 // will affect all users of Cond.
21594 // Make sure it is fine and update all the nodes so that we do not
21595 // use the generic VSELECT anymore. Otherwise, we may perform
21596 // wrong optimizations as we messed up with the actual expectation
21597 // for the vector boolean values.
21598 if (Cond != TLO.Old) {
21599 // Check all uses of that condition operand to check whether it will be
21600 // consumed by non-BLEND instructions, which may depend on all bits are
21602 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21604 if (I->getOpcode() != ISD::VSELECT)
21605 // TODO: Add other opcodes eventually lowered into BLEND.
21608 // Update all the users of the condition, before committing the change,
21609 // so that the VSELECT optimizations that expect the correct vector
21610 // boolean value will not be triggered.
21611 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21613 DAG.ReplaceAllUsesOfValueWith(
21615 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21616 Cond, I->getOperand(1), I->getOperand(2)));
21617 DCI.CommitTargetLoweringOpt(TLO);
21620 // At this point, only Cond is changed. Change the condition
21621 // just for N to keep the opportunity to optimize all other
21622 // users their own way.
21623 DAG.ReplaceAllUsesOfValueWith(
21625 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21626 TLO.New, N->getOperand(1), N->getOperand(2)));
21634 // Check whether a boolean test is testing a boolean value generated by
21635 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21638 // Simplify the following patterns:
21639 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21640 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21641 // to (Op EFLAGS Cond)
21643 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21644 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21645 // to (Op EFLAGS !Cond)
21647 // where Op could be BRCOND or CMOV.
21649 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21650 // Quit if not CMP and SUB with its value result used.
21651 if (Cmp.getOpcode() != X86ISD::CMP &&
21652 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21655 // Quit if not used as a boolean value.
21656 if (CC != X86::COND_E && CC != X86::COND_NE)
21659 // Check CMP operands. One of them should be 0 or 1 and the other should be
21660 // an SetCC or extended from it.
21661 SDValue Op1 = Cmp.getOperand(0);
21662 SDValue Op2 = Cmp.getOperand(1);
21665 const ConstantSDNode* C = nullptr;
21666 bool needOppositeCond = (CC == X86::COND_E);
21667 bool checkAgainstTrue = false; // Is it a comparison against 1?
21669 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21671 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21673 else // Quit if all operands are not constants.
21676 if (C->getZExtValue() == 1) {
21677 needOppositeCond = !needOppositeCond;
21678 checkAgainstTrue = true;
21679 } else if (C->getZExtValue() != 0)
21680 // Quit if the constant is neither 0 or 1.
21683 bool truncatedToBoolWithAnd = false;
21684 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21685 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21686 SetCC.getOpcode() == ISD::TRUNCATE ||
21687 SetCC.getOpcode() == ISD::AND) {
21688 if (SetCC.getOpcode() == ISD::AND) {
21690 ConstantSDNode *CS;
21691 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21692 CS->getZExtValue() == 1)
21694 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21695 CS->getZExtValue() == 1)
21699 SetCC = SetCC.getOperand(OpIdx);
21700 truncatedToBoolWithAnd = true;
21702 SetCC = SetCC.getOperand(0);
21705 switch (SetCC.getOpcode()) {
21706 case X86ISD::SETCC_CARRY:
21707 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21708 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21709 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21710 // truncated to i1 using 'and'.
21711 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21713 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21714 "Invalid use of SETCC_CARRY!");
21716 case X86ISD::SETCC:
21717 // Set the condition code or opposite one if necessary.
21718 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21719 if (needOppositeCond)
21720 CC = X86::GetOppositeBranchCondition(CC);
21721 return SetCC.getOperand(1);
21722 case X86ISD::CMOV: {
21723 // Check whether false/true value has canonical one, i.e. 0 or 1.
21724 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21725 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21726 // Quit if true value is not a constant.
21729 // Quit if false value is not a constant.
21731 SDValue Op = SetCC.getOperand(0);
21732 // Skip 'zext' or 'trunc' node.
21733 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21734 Op.getOpcode() == ISD::TRUNCATE)
21735 Op = Op.getOperand(0);
21736 // A special case for rdrand/rdseed, where 0 is set if false cond is
21738 if ((Op.getOpcode() != X86ISD::RDRAND &&
21739 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21742 // Quit if false value is not the constant 0 or 1.
21743 bool FValIsFalse = true;
21744 if (FVal && FVal->getZExtValue() != 0) {
21745 if (FVal->getZExtValue() != 1)
21747 // If FVal is 1, opposite cond is needed.
21748 needOppositeCond = !needOppositeCond;
21749 FValIsFalse = false;
21751 // Quit if TVal is not the constant opposite of FVal.
21752 if (FValIsFalse && TVal->getZExtValue() != 1)
21754 if (!FValIsFalse && TVal->getZExtValue() != 0)
21756 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21757 if (needOppositeCond)
21758 CC = X86::GetOppositeBranchCondition(CC);
21759 return SetCC.getOperand(3);
21766 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21768 /// (X86or (X86setcc) (X86setcc))
21769 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21770 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21771 X86::CondCode &CC1, SDValue &Flags,
21773 if (Cond->getOpcode() == X86ISD::CMP) {
21774 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21775 if (!CondOp1C || !CondOp1C->isNullValue())
21778 Cond = Cond->getOperand(0);
21783 SDValue SetCC0, SetCC1;
21784 switch (Cond->getOpcode()) {
21785 default: return false;
21792 SetCC0 = Cond->getOperand(0);
21793 SetCC1 = Cond->getOperand(1);
21797 // Make sure we have SETCC nodes, using the same flags value.
21798 if (SetCC0.getOpcode() != X86ISD::SETCC ||
21799 SetCC1.getOpcode() != X86ISD::SETCC ||
21800 SetCC0->getOperand(1) != SetCC1->getOperand(1))
21803 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
21804 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
21805 Flags = SetCC0->getOperand(1);
21809 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21810 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21811 TargetLowering::DAGCombinerInfo &DCI,
21812 const X86Subtarget *Subtarget) {
21815 // If the flag operand isn't dead, don't touch this CMOV.
21816 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21819 SDValue FalseOp = N->getOperand(0);
21820 SDValue TrueOp = N->getOperand(1);
21821 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21822 SDValue Cond = N->getOperand(3);
21824 if (CC == X86::COND_E || CC == X86::COND_NE) {
21825 switch (Cond.getOpcode()) {
21829 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21830 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21831 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21837 Flags = checkBoolTestSetCCCombine(Cond, CC);
21838 if (Flags.getNode() &&
21839 // Extra check as FCMOV only supports a subset of X86 cond.
21840 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21841 SDValue Ops[] = { FalseOp, TrueOp,
21842 DAG.getConstant(CC, DL, MVT::i8), Flags };
21843 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21846 // If this is a select between two integer constants, try to do some
21847 // optimizations. Note that the operands are ordered the opposite of SELECT
21849 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21850 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21851 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21852 // larger than FalseC (the false value).
21853 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21854 CC = X86::GetOppositeBranchCondition(CC);
21855 std::swap(TrueC, FalseC);
21856 std::swap(TrueOp, FalseOp);
21859 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21860 // This is efficient for any integer data type (including i8/i16) and
21862 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21863 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21864 DAG.getConstant(CC, DL, MVT::i8), Cond);
21866 // Zero extend the condition if needed.
21867 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21869 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21870 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21871 DAG.getConstant(ShAmt, DL, MVT::i8));
21872 if (N->getNumValues() == 2) // Dead flag value?
21873 return DCI.CombineTo(N, Cond, SDValue());
21877 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21878 // for any integer data type, including i8/i16.
21879 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21880 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21881 DAG.getConstant(CC, DL, MVT::i8), Cond);
21883 // Zero extend the condition if needed.
21884 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21885 FalseC->getValueType(0), Cond);
21886 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21887 SDValue(FalseC, 0));
21889 if (N->getNumValues() == 2) // Dead flag value?
21890 return DCI.CombineTo(N, Cond, SDValue());
21894 // Optimize cases that will turn into an LEA instruction. This requires
21895 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21896 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21897 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21898 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21900 bool isFastMultiplier = false;
21902 switch ((unsigned char)Diff) {
21904 case 1: // result = add base, cond
21905 case 2: // result = lea base( , cond*2)
21906 case 3: // result = lea base(cond, cond*2)
21907 case 4: // result = lea base( , cond*4)
21908 case 5: // result = lea base(cond, cond*4)
21909 case 8: // result = lea base( , cond*8)
21910 case 9: // result = lea base(cond, cond*8)
21911 isFastMultiplier = true;
21916 if (isFastMultiplier) {
21917 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21918 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21919 DAG.getConstant(CC, DL, MVT::i8), Cond);
21920 // Zero extend the condition if needed.
21921 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21923 // Scale the condition by the difference.
21925 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21926 DAG.getConstant(Diff, DL, Cond.getValueType()));
21928 // Add the base if non-zero.
21929 if (FalseC->getAPIntValue() != 0)
21930 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21931 SDValue(FalseC, 0));
21932 if (N->getNumValues() == 2) // Dead flag value?
21933 return DCI.CombineTo(N, Cond, SDValue());
21940 // Handle these cases:
21941 // (select (x != c), e, c) -> select (x != c), e, x),
21942 // (select (x == c), c, e) -> select (x == c), x, e)
21943 // where the c is an integer constant, and the "select" is the combination
21944 // of CMOV and CMP.
21946 // The rationale for this change is that the conditional-move from a constant
21947 // needs two instructions, however, conditional-move from a register needs
21948 // only one instruction.
21950 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21951 // some instruction-combining opportunities. This opt needs to be
21952 // postponed as late as possible.
21954 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21955 // the DCI.xxxx conditions are provided to postpone the optimization as
21956 // late as possible.
21958 ConstantSDNode *CmpAgainst = nullptr;
21959 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21960 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21961 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21963 if (CC == X86::COND_NE &&
21964 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21965 CC = X86::GetOppositeBranchCondition(CC);
21966 std::swap(TrueOp, FalseOp);
21969 if (CC == X86::COND_E &&
21970 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21971 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21972 DAG.getConstant(CC, DL, MVT::i8), Cond };
21973 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21978 // Fold and/or of setcc's to double CMOV:
21979 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
21980 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
21982 // This combine lets us generate:
21983 // cmovcc1 (jcc1 if we don't have CMOV)
21989 // cmovne (jne if we don't have CMOV)
21990 // When we can't use the CMOV instruction, it might increase branch
21992 // When we can use CMOV, or when there is no mispredict, this improves
21993 // throughput and reduces register pressure.
21995 if (CC == X86::COND_NE) {
21997 X86::CondCode CC0, CC1;
21999 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22001 std::swap(FalseOp, TrueOp);
22002 CC0 = X86::GetOppositeBranchCondition(CC0);
22003 CC1 = X86::GetOppositeBranchCondition(CC1);
22006 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22008 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22009 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22010 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22011 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22019 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22020 const X86Subtarget *Subtarget) {
22021 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22023 default: return SDValue();
22024 // SSE/AVX/AVX2 blend intrinsics.
22025 case Intrinsic::x86_avx2_pblendvb:
22026 // Don't try to simplify this intrinsic if we don't have AVX2.
22027 if (!Subtarget->hasAVX2())
22030 case Intrinsic::x86_avx_blendv_pd_256:
22031 case Intrinsic::x86_avx_blendv_ps_256:
22032 // Don't try to simplify this intrinsic if we don't have AVX.
22033 if (!Subtarget->hasAVX())
22036 case Intrinsic::x86_sse41_blendvps:
22037 case Intrinsic::x86_sse41_blendvpd:
22038 case Intrinsic::x86_sse41_pblendvb: {
22039 SDValue Op0 = N->getOperand(1);
22040 SDValue Op1 = N->getOperand(2);
22041 SDValue Mask = N->getOperand(3);
22043 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22044 if (!Subtarget->hasSSE41())
22047 // fold (blend A, A, Mask) -> A
22050 // fold (blend A, B, allZeros) -> A
22051 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22053 // fold (blend A, B, allOnes) -> B
22054 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22057 // Simplify the case where the mask is a constant i32 value.
22058 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22059 if (C->isNullValue())
22061 if (C->isAllOnesValue())
22068 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22069 case Intrinsic::x86_sse2_psrai_w:
22070 case Intrinsic::x86_sse2_psrai_d:
22071 case Intrinsic::x86_avx2_psrai_w:
22072 case Intrinsic::x86_avx2_psrai_d:
22073 case Intrinsic::x86_sse2_psra_w:
22074 case Intrinsic::x86_sse2_psra_d:
22075 case Intrinsic::x86_avx2_psra_w:
22076 case Intrinsic::x86_avx2_psra_d: {
22077 SDValue Op0 = N->getOperand(1);
22078 SDValue Op1 = N->getOperand(2);
22079 EVT VT = Op0.getValueType();
22080 assert(VT.isVector() && "Expected a vector type!");
22082 if (isa<BuildVectorSDNode>(Op1))
22083 Op1 = Op1.getOperand(0);
22085 if (!isa<ConstantSDNode>(Op1))
22088 EVT SVT = VT.getVectorElementType();
22089 unsigned SVTBits = SVT.getSizeInBits();
22091 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22092 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22093 uint64_t ShAmt = C.getZExtValue();
22095 // Don't try to convert this shift into a ISD::SRA if the shift
22096 // count is bigger than or equal to the element size.
22097 if (ShAmt >= SVTBits)
22100 // Trivial case: if the shift count is zero, then fold this
22101 // into the first operand.
22105 // Replace this packed shift intrinsic with a target independent
22108 SDValue Splat = DAG.getConstant(C, DL, VT);
22109 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22114 /// PerformMulCombine - Optimize a single multiply with constant into two
22115 /// in order to implement it with two cheaper instructions, e.g.
22116 /// LEA + SHL, LEA + LEA.
22117 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22118 TargetLowering::DAGCombinerInfo &DCI) {
22119 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22122 EVT VT = N->getValueType(0);
22123 if (VT != MVT::i64 && VT != MVT::i32)
22126 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22129 uint64_t MulAmt = C->getZExtValue();
22130 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22133 uint64_t MulAmt1 = 0;
22134 uint64_t MulAmt2 = 0;
22135 if ((MulAmt % 9) == 0) {
22137 MulAmt2 = MulAmt / 9;
22138 } else if ((MulAmt % 5) == 0) {
22140 MulAmt2 = MulAmt / 5;
22141 } else if ((MulAmt % 3) == 0) {
22143 MulAmt2 = MulAmt / 3;
22146 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22149 if (isPowerOf2_64(MulAmt2) &&
22150 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22151 // If second multiplifer is pow2, issue it first. We want the multiply by
22152 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22154 std::swap(MulAmt1, MulAmt2);
22157 if (isPowerOf2_64(MulAmt1))
22158 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22159 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22161 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22162 DAG.getConstant(MulAmt1, DL, VT));
22164 if (isPowerOf2_64(MulAmt2))
22165 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22166 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22168 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22169 DAG.getConstant(MulAmt2, DL, VT));
22171 // Do not add new nodes to DAG combiner worklist.
22172 DCI.CombineTo(N, NewMul, false);
22177 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22178 SDValue N0 = N->getOperand(0);
22179 SDValue N1 = N->getOperand(1);
22180 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22181 EVT VT = N0.getValueType();
22183 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22184 // since the result of setcc_c is all zero's or all ones.
22185 if (VT.isInteger() && !VT.isVector() &&
22186 N1C && N0.getOpcode() == ISD::AND &&
22187 N0.getOperand(1).getOpcode() == ISD::Constant) {
22188 SDValue N00 = N0.getOperand(0);
22189 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22190 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22191 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22192 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22193 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22194 APInt ShAmt = N1C->getAPIntValue();
22195 Mask = Mask.shl(ShAmt);
22198 return DAG.getNode(ISD::AND, DL, VT,
22199 N00, DAG.getConstant(Mask, DL, VT));
22204 // Hardware support for vector shifts is sparse which makes us scalarize the
22205 // vector operations in many cases. Also, on sandybridge ADD is faster than
22207 // (shl V, 1) -> add V,V
22208 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22209 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22210 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22211 // We shift all of the values by one. In many cases we do not have
22212 // hardware support for this operation. This is better expressed as an ADD
22214 if (N1SplatC->getZExtValue() == 1)
22215 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22221 /// \brief Returns a vector of 0s if the node in input is a vector logical
22222 /// shift by a constant amount which is known to be bigger than or equal
22223 /// to the vector element size in bits.
22224 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22225 const X86Subtarget *Subtarget) {
22226 EVT VT = N->getValueType(0);
22228 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22229 (!Subtarget->hasInt256() ||
22230 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22233 SDValue Amt = N->getOperand(1);
22235 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22236 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22237 APInt ShiftAmt = AmtSplat->getAPIntValue();
22238 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22240 // SSE2/AVX2 logical shifts always return a vector of 0s
22241 // if the shift amount is bigger than or equal to
22242 // the element size. The constant shift amount will be
22243 // encoded as a 8-bit immediate.
22244 if (ShiftAmt.trunc(8).uge(MaxAmount))
22245 return getZeroVector(VT, Subtarget, DAG, DL);
22251 /// PerformShiftCombine - Combine shifts.
22252 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22253 TargetLowering::DAGCombinerInfo &DCI,
22254 const X86Subtarget *Subtarget) {
22255 if (N->getOpcode() == ISD::SHL) {
22256 SDValue V = PerformSHLCombine(N, DAG);
22257 if (V.getNode()) return V;
22260 if (N->getOpcode() != ISD::SRA) {
22261 // Try to fold this logical shift into a zero vector.
22262 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22263 if (V.getNode()) return V;
22269 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22270 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22271 // and friends. Likewise for OR -> CMPNEQSS.
22272 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22273 TargetLowering::DAGCombinerInfo &DCI,
22274 const X86Subtarget *Subtarget) {
22277 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22278 // we're requiring SSE2 for both.
22279 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22280 SDValue N0 = N->getOperand(0);
22281 SDValue N1 = N->getOperand(1);
22282 SDValue CMP0 = N0->getOperand(1);
22283 SDValue CMP1 = N1->getOperand(1);
22286 // The SETCCs should both refer to the same CMP.
22287 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22290 SDValue CMP00 = CMP0->getOperand(0);
22291 SDValue CMP01 = CMP0->getOperand(1);
22292 EVT VT = CMP00.getValueType();
22294 if (VT == MVT::f32 || VT == MVT::f64) {
22295 bool ExpectingFlags = false;
22296 // Check for any users that want flags:
22297 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22298 !ExpectingFlags && UI != UE; ++UI)
22299 switch (UI->getOpcode()) {
22304 ExpectingFlags = true;
22306 case ISD::CopyToReg:
22307 case ISD::SIGN_EXTEND:
22308 case ISD::ZERO_EXTEND:
22309 case ISD::ANY_EXTEND:
22313 if (!ExpectingFlags) {
22314 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22315 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22317 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22318 X86::CondCode tmp = cc0;
22323 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22324 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22325 // FIXME: need symbolic constants for these magic numbers.
22326 // See X86ATTInstPrinter.cpp:printSSECC().
22327 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22328 if (Subtarget->hasAVX512()) {
22329 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22331 DAG.getConstant(x86cc, DL, MVT::i8));
22332 if (N->getValueType(0) != MVT::i1)
22333 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22337 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22338 CMP00.getValueType(), CMP00, CMP01,
22339 DAG.getConstant(x86cc, DL,
22342 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22343 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22345 if (is64BitFP && !Subtarget->is64Bit()) {
22346 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22347 // 64-bit integer, since that's not a legal type. Since
22348 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22349 // bits, but can do this little dance to extract the lowest 32 bits
22350 // and work with those going forward.
22351 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22353 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22355 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22356 Vector32, DAG.getIntPtrConstant(0, DL));
22360 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
22362 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22363 DAG.getConstant(1, DL, IntVT));
22364 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22366 return OneBitOfTruth;
22374 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22375 /// so it can be folded inside ANDNP.
22376 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22377 EVT VT = N->getValueType(0);
22379 // Match direct AllOnes for 128 and 256-bit vectors
22380 if (ISD::isBuildVectorAllOnes(N))
22383 // Look through a bit convert.
22384 if (N->getOpcode() == ISD::BITCAST)
22385 N = N->getOperand(0).getNode();
22387 // Sometimes the operand may come from a insert_subvector building a 256-bit
22389 if (VT.is256BitVector() &&
22390 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22391 SDValue V1 = N->getOperand(0);
22392 SDValue V2 = N->getOperand(1);
22394 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22395 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22396 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22397 ISD::isBuildVectorAllOnes(V2.getNode()))
22404 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22405 // register. In most cases we actually compare or select YMM-sized registers
22406 // and mixing the two types creates horrible code. This method optimizes
22407 // some of the transition sequences.
22408 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22409 TargetLowering::DAGCombinerInfo &DCI,
22410 const X86Subtarget *Subtarget) {
22411 EVT VT = N->getValueType(0);
22412 if (!VT.is256BitVector())
22415 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22416 N->getOpcode() == ISD::ZERO_EXTEND ||
22417 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22419 SDValue Narrow = N->getOperand(0);
22420 EVT NarrowVT = Narrow->getValueType(0);
22421 if (!NarrowVT.is128BitVector())
22424 if (Narrow->getOpcode() != ISD::XOR &&
22425 Narrow->getOpcode() != ISD::AND &&
22426 Narrow->getOpcode() != ISD::OR)
22429 SDValue N0 = Narrow->getOperand(0);
22430 SDValue N1 = Narrow->getOperand(1);
22433 // The Left side has to be a trunc.
22434 if (N0.getOpcode() != ISD::TRUNCATE)
22437 // The type of the truncated inputs.
22438 EVT WideVT = N0->getOperand(0)->getValueType(0);
22442 // The right side has to be a 'trunc' or a constant vector.
22443 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22444 ConstantSDNode *RHSConstSplat = nullptr;
22445 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22446 RHSConstSplat = RHSBV->getConstantSplatNode();
22447 if (!RHSTrunc && !RHSConstSplat)
22450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22452 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22455 // Set N0 and N1 to hold the inputs to the new wide operation.
22456 N0 = N0->getOperand(0);
22457 if (RHSConstSplat) {
22458 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22459 SDValue(RHSConstSplat, 0));
22460 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22461 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22462 } else if (RHSTrunc) {
22463 N1 = N1->getOperand(0);
22466 // Generate the wide operation.
22467 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22468 unsigned Opcode = N->getOpcode();
22470 case ISD::ANY_EXTEND:
22472 case ISD::ZERO_EXTEND: {
22473 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22474 APInt Mask = APInt::getAllOnesValue(InBits);
22475 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22476 return DAG.getNode(ISD::AND, DL, VT,
22477 Op, DAG.getConstant(Mask, DL, VT));
22479 case ISD::SIGN_EXTEND:
22480 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22481 Op, DAG.getValueType(NarrowVT));
22483 llvm_unreachable("Unexpected opcode");
22487 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22488 TargetLowering::DAGCombinerInfo &DCI,
22489 const X86Subtarget *Subtarget) {
22490 SDValue N0 = N->getOperand(0);
22491 SDValue N1 = N->getOperand(1);
22494 // A vector zext_in_reg may be represented as a shuffle,
22495 // feeding into a bitcast (this represents anyext) feeding into
22496 // an and with a mask.
22497 // We'd like to try to combine that into a shuffle with zero
22498 // plus a bitcast, removing the and.
22499 if (N0.getOpcode() != ISD::BITCAST ||
22500 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22503 // The other side of the AND should be a splat of 2^C, where C
22504 // is the number of bits in the source type.
22505 if (N1.getOpcode() == ISD::BITCAST)
22506 N1 = N1.getOperand(0);
22507 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22509 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22511 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22512 EVT SrcType = Shuffle->getValueType(0);
22514 // We expect a single-source shuffle
22515 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22518 unsigned SrcSize = SrcType.getScalarSizeInBits();
22520 APInt SplatValue, SplatUndef;
22521 unsigned SplatBitSize;
22523 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22524 SplatBitSize, HasAnyUndefs))
22527 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22528 // Make sure the splat matches the mask we expect
22529 if (SplatBitSize > ResSize ||
22530 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22533 // Make sure the input and output size make sense
22534 if (SrcSize >= ResSize || ResSize % SrcSize)
22537 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22538 // The number of u's between each two values depends on the ratio between
22539 // the source and dest type.
22540 unsigned ZextRatio = ResSize / SrcSize;
22541 bool IsZext = true;
22542 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22543 if (i % ZextRatio) {
22544 if (Shuffle->getMaskElt(i) > 0) {
22550 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22551 // Expected element number
22561 // Ok, perform the transformation - replace the shuffle with
22562 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22563 // (instead of undef) where the k elements come from the zero vector.
22564 SmallVector<int, 8> Mask;
22565 unsigned NumElems = SrcType.getVectorNumElements();
22566 for (unsigned i = 0; i < NumElems; ++i)
22568 Mask.push_back(NumElems);
22570 Mask.push_back(i / ZextRatio);
22572 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22573 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
22574 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22577 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22578 TargetLowering::DAGCombinerInfo &DCI,
22579 const X86Subtarget *Subtarget) {
22580 if (DCI.isBeforeLegalizeOps())
22583 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22586 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22589 EVT VT = N->getValueType(0);
22590 SDValue N0 = N->getOperand(0);
22591 SDValue N1 = N->getOperand(1);
22594 // Create BEXTR instructions
22595 // BEXTR is ((X >> imm) & (2**size-1))
22596 if (VT == MVT::i32 || VT == MVT::i64) {
22597 // Check for BEXTR.
22598 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22599 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22600 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22601 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22602 if (MaskNode && ShiftNode) {
22603 uint64_t Mask = MaskNode->getZExtValue();
22604 uint64_t Shift = ShiftNode->getZExtValue();
22605 if (isMask_64(Mask)) {
22606 uint64_t MaskSize = countPopulation(Mask);
22607 if (Shift + MaskSize <= VT.getSizeInBits())
22608 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22609 DAG.getConstant(Shift | (MaskSize << 8), DL,
22618 // Want to form ANDNP nodes:
22619 // 1) In the hopes of then easily combining them with OR and AND nodes
22620 // to form PBLEND/PSIGN.
22621 // 2) To match ANDN packed intrinsics
22622 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22625 // Check LHS for vnot
22626 if (N0.getOpcode() == ISD::XOR &&
22627 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22628 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22629 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22631 // Check RHS for vnot
22632 if (N1.getOpcode() == ISD::XOR &&
22633 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22634 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22635 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22640 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22641 TargetLowering::DAGCombinerInfo &DCI,
22642 const X86Subtarget *Subtarget) {
22643 if (DCI.isBeforeLegalizeOps())
22646 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22650 SDValue N0 = N->getOperand(0);
22651 SDValue N1 = N->getOperand(1);
22652 EVT VT = N->getValueType(0);
22654 // look for psign/blend
22655 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22656 if (!Subtarget->hasSSSE3() ||
22657 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22660 // Canonicalize pandn to RHS
22661 if (N0.getOpcode() == X86ISD::ANDNP)
22663 // or (and (m, y), (pandn m, x))
22664 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22665 SDValue Mask = N1.getOperand(0);
22666 SDValue X = N1.getOperand(1);
22668 if (N0.getOperand(0) == Mask)
22669 Y = N0.getOperand(1);
22670 if (N0.getOperand(1) == Mask)
22671 Y = N0.getOperand(0);
22673 // Check to see if the mask appeared in both the AND and ANDNP and
22677 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22678 // Look through mask bitcast.
22679 if (Mask.getOpcode() == ISD::BITCAST)
22680 Mask = Mask.getOperand(0);
22681 if (X.getOpcode() == ISD::BITCAST)
22682 X = X.getOperand(0);
22683 if (Y.getOpcode() == ISD::BITCAST)
22684 Y = Y.getOperand(0);
22686 EVT MaskVT = Mask.getValueType();
22688 // Validate that the Mask operand is a vector sra node.
22689 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22690 // there is no psrai.b
22691 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22692 unsigned SraAmt = ~0;
22693 if (Mask.getOpcode() == ISD::SRA) {
22694 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22695 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22696 SraAmt = AmtConst->getZExtValue();
22697 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22698 SDValue SraC = Mask.getOperand(1);
22699 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22701 if ((SraAmt + 1) != EltBits)
22706 // Now we know we at least have a plendvb with the mask val. See if
22707 // we can form a psignb/w/d.
22708 // psign = x.type == y.type == mask.type && y = sub(0, x);
22709 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22710 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22711 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22712 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22713 "Unsupported VT for PSIGN");
22714 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22715 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22717 // PBLENDVB only available on SSE 4.1
22718 if (!Subtarget->hasSSE41())
22721 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22723 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22724 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22725 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22726 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22727 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22731 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22734 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22735 MachineFunction &MF = DAG.getMachineFunction();
22737 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22739 // SHLD/SHRD instructions have lower register pressure, but on some
22740 // platforms they have higher latency than the equivalent
22741 // series of shifts/or that would otherwise be generated.
22742 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22743 // have higher latencies and we are not optimizing for size.
22744 if (!OptForSize && Subtarget->isSHLDSlow())
22747 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22749 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22751 if (!N0.hasOneUse() || !N1.hasOneUse())
22754 SDValue ShAmt0 = N0.getOperand(1);
22755 if (ShAmt0.getValueType() != MVT::i8)
22757 SDValue ShAmt1 = N1.getOperand(1);
22758 if (ShAmt1.getValueType() != MVT::i8)
22760 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22761 ShAmt0 = ShAmt0.getOperand(0);
22762 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22763 ShAmt1 = ShAmt1.getOperand(0);
22766 unsigned Opc = X86ISD::SHLD;
22767 SDValue Op0 = N0.getOperand(0);
22768 SDValue Op1 = N1.getOperand(0);
22769 if (ShAmt0.getOpcode() == ISD::SUB) {
22770 Opc = X86ISD::SHRD;
22771 std::swap(Op0, Op1);
22772 std::swap(ShAmt0, ShAmt1);
22775 unsigned Bits = VT.getSizeInBits();
22776 if (ShAmt1.getOpcode() == ISD::SUB) {
22777 SDValue Sum = ShAmt1.getOperand(0);
22778 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22779 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22780 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22781 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22782 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22783 return DAG.getNode(Opc, DL, VT,
22785 DAG.getNode(ISD::TRUNCATE, DL,
22788 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22789 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22791 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22792 return DAG.getNode(Opc, DL, VT,
22793 N0.getOperand(0), N1.getOperand(0),
22794 DAG.getNode(ISD::TRUNCATE, DL,
22801 // Generate NEG and CMOV for integer abs.
22802 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22803 EVT VT = N->getValueType(0);
22805 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22806 // 8-bit integer abs to NEG and CMOV.
22807 if (VT.isInteger() && VT.getSizeInBits() == 8)
22810 SDValue N0 = N->getOperand(0);
22811 SDValue N1 = N->getOperand(1);
22814 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22815 // and change it to SUB and CMOV.
22816 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22817 N0.getOpcode() == ISD::ADD &&
22818 N0.getOperand(1) == N1 &&
22819 N1.getOpcode() == ISD::SRA &&
22820 N1.getOperand(0) == N0.getOperand(0))
22821 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22822 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22823 // Generate SUB & CMOV.
22824 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22825 DAG.getConstant(0, DL, VT), N0.getOperand(0));
22827 SDValue Ops[] = { N0.getOperand(0), Neg,
22828 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
22829 SDValue(Neg.getNode(), 1) };
22830 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22835 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22836 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22837 TargetLowering::DAGCombinerInfo &DCI,
22838 const X86Subtarget *Subtarget) {
22839 if (DCI.isBeforeLegalizeOps())
22842 if (Subtarget->hasCMov()) {
22843 SDValue RV = performIntegerAbsCombine(N, DAG);
22851 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22852 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22853 TargetLowering::DAGCombinerInfo &DCI,
22854 const X86Subtarget *Subtarget) {
22855 LoadSDNode *Ld = cast<LoadSDNode>(N);
22856 EVT RegVT = Ld->getValueType(0);
22857 EVT MemVT = Ld->getMemoryVT();
22859 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22861 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
22862 // into two 16-byte operations.
22863 ISD::LoadExtType Ext = Ld->getExtensionType();
22864 unsigned Alignment = Ld->getAlignment();
22865 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22866 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22867 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22868 unsigned NumElems = RegVT.getVectorNumElements();
22872 SDValue Ptr = Ld->getBasePtr();
22873 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
22875 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22877 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22878 Ld->getPointerInfo(), Ld->isVolatile(),
22879 Ld->isNonTemporal(), Ld->isInvariant(),
22881 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22882 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22883 Ld->getPointerInfo(), Ld->isVolatile(),
22884 Ld->isNonTemporal(), Ld->isInvariant(),
22885 std::min(16U, Alignment));
22886 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22888 Load2.getValue(1));
22890 SDValue NewVec = DAG.getUNDEF(RegVT);
22891 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22892 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22893 return DCI.CombineTo(N, NewVec, TF, true);
22899 /// PerformMLOADCombine - Resolve extending loads
22900 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22901 TargetLowering::DAGCombinerInfo &DCI,
22902 const X86Subtarget *Subtarget) {
22903 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22904 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22907 EVT VT = Mld->getValueType(0);
22908 unsigned NumElems = VT.getVectorNumElements();
22909 EVT LdVT = Mld->getMemoryVT();
22912 assert(LdVT != VT && "Cannot extend to the same type");
22913 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22914 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22915 // From, To sizes and ElemCount must be pow of two
22916 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22917 "Unexpected size for extending masked load");
22919 unsigned SizeRatio = ToSz / FromSz;
22920 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22922 // Create a type on which we perform the shuffle
22923 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22924 LdVT.getScalarType(), NumElems*SizeRatio);
22925 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22927 // Convert Src0 value
22928 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22929 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22930 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22931 for (unsigned i = 0; i != NumElems; ++i)
22932 ShuffleVec[i] = i * SizeRatio;
22934 // Can't shuffle using an illegal type.
22935 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22936 && "WideVecVT should be legal");
22937 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22938 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22940 // Prepare the new mask
22942 SDValue Mask = Mld->getMask();
22943 if (Mask.getValueType() == VT) {
22944 // Mask and original value have the same type
22945 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22946 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22947 for (unsigned i = 0; i != NumElems; ++i)
22948 ShuffleVec[i] = i * SizeRatio;
22949 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22950 ShuffleVec[i] = NumElems*SizeRatio;
22951 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22952 DAG.getConstant(0, dl, WideVecVT),
22956 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22957 unsigned WidenNumElts = NumElems*SizeRatio;
22958 unsigned MaskNumElts = VT.getVectorNumElements();
22959 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22962 unsigned NumConcat = WidenNumElts / MaskNumElts;
22963 SmallVector<SDValue, 16> Ops(NumConcat);
22964 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
22966 for (unsigned i = 1; i != NumConcat; ++i)
22969 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22972 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22973 Mld->getBasePtr(), NewMask, WideSrc0,
22974 Mld->getMemoryVT(), Mld->getMemOperand(),
22976 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22977 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22980 /// PerformMSTORECombine - Resolve truncating stores
22981 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22982 const X86Subtarget *Subtarget) {
22983 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22984 if (!Mst->isTruncatingStore())
22987 EVT VT = Mst->getValue().getValueType();
22988 unsigned NumElems = VT.getVectorNumElements();
22989 EVT StVT = Mst->getMemoryVT();
22992 assert(StVT != VT && "Cannot truncate to the same type");
22993 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22994 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22996 // From, To sizes and ElemCount must be pow of two
22997 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22998 "Unexpected size for truncating masked store");
22999 // We are going to use the original vector elt for storing.
23000 // Accumulated smaller vector elements must be a multiple of the store size.
23001 assert (((NumElems * FromSz) % ToSz) == 0 &&
23002 "Unexpected ratio for truncating masked store");
23004 unsigned SizeRatio = FromSz / ToSz;
23005 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23007 // Create a type on which we perform the shuffle
23008 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23009 StVT.getScalarType(), NumElems*SizeRatio);
23011 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23013 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
23014 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23015 for (unsigned i = 0; i != NumElems; ++i)
23016 ShuffleVec[i] = i * SizeRatio;
23018 // Can't shuffle using an illegal type.
23019 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23020 && "WideVecVT should be legal");
23022 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23023 DAG.getUNDEF(WideVecVT),
23027 SDValue Mask = Mst->getMask();
23028 if (Mask.getValueType() == VT) {
23029 // Mask and original value have the same type
23030 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23031 for (unsigned i = 0; i != NumElems; ++i)
23032 ShuffleVec[i] = i * SizeRatio;
23033 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23034 ShuffleVec[i] = NumElems*SizeRatio;
23035 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23036 DAG.getConstant(0, dl, WideVecVT),
23040 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23041 unsigned WidenNumElts = NumElems*SizeRatio;
23042 unsigned MaskNumElts = VT.getVectorNumElements();
23043 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23046 unsigned NumConcat = WidenNumElts / MaskNumElts;
23047 SmallVector<SDValue, 16> Ops(NumConcat);
23048 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23050 for (unsigned i = 1; i != NumConcat; ++i)
23053 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23056 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23057 NewMask, StVT, Mst->getMemOperand(), false);
23059 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23060 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23061 const X86Subtarget *Subtarget) {
23062 StoreSDNode *St = cast<StoreSDNode>(N);
23063 EVT VT = St->getValue().getValueType();
23064 EVT StVT = St->getMemoryVT();
23066 SDValue StoredVal = St->getOperand(1);
23067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23069 // If we are saving a concatenation of two XMM registers and 32-byte stores
23070 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23071 unsigned Alignment = St->getAlignment();
23072 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23073 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23074 StVT == VT && !IsAligned) {
23075 unsigned NumElems = VT.getVectorNumElements();
23079 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23080 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23082 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23083 SDValue Ptr0 = St->getBasePtr();
23084 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23086 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23087 St->getPointerInfo(), St->isVolatile(),
23088 St->isNonTemporal(), Alignment);
23089 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23090 St->getPointerInfo(), St->isVolatile(),
23091 St->isNonTemporal(),
23092 std::min(16U, Alignment));
23093 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23096 // Optimize trunc store (of multiple scalars) to shuffle and store.
23097 // First, pack all of the elements in one place. Next, store to memory
23098 // in fewer chunks.
23099 if (St->isTruncatingStore() && VT.isVector()) {
23100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23101 unsigned NumElems = VT.getVectorNumElements();
23102 assert(StVT != VT && "Cannot truncate to the same type");
23103 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23104 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23106 // From, To sizes and ElemCount must be pow of two
23107 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23108 // We are going to use the original vector elt for storing.
23109 // Accumulated smaller vector elements must be a multiple of the store size.
23110 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23112 unsigned SizeRatio = FromSz / ToSz;
23114 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23116 // Create a type on which we perform the shuffle
23117 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23118 StVT.getScalarType(), NumElems*SizeRatio);
23120 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23122 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23123 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23124 for (unsigned i = 0; i != NumElems; ++i)
23125 ShuffleVec[i] = i * SizeRatio;
23127 // Can't shuffle using an illegal type.
23128 if (!TLI.isTypeLegal(WideVecVT))
23131 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23132 DAG.getUNDEF(WideVecVT),
23134 // At this point all of the data is stored at the bottom of the
23135 // register. We now need to save it to mem.
23137 // Find the largest store unit
23138 MVT StoreType = MVT::i8;
23139 for (MVT Tp : MVT::integer_valuetypes()) {
23140 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23144 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23145 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23146 (64 <= NumElems * ToSz))
23147 StoreType = MVT::f64;
23149 // Bitcast the original vector into a vector of store-size units
23150 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23151 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23152 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23153 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23154 SmallVector<SDValue, 8> Chains;
23155 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23156 TLI.getPointerTy());
23157 SDValue Ptr = St->getBasePtr();
23159 // Perform one or more big stores into memory.
23160 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23161 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23162 StoreType, ShuffWide,
23163 DAG.getIntPtrConstant(i, dl));
23164 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23165 St->getPointerInfo(), St->isVolatile(),
23166 St->isNonTemporal(), St->getAlignment());
23167 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23168 Chains.push_back(Ch);
23171 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23174 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23175 // the FP state in cases where an emms may be missing.
23176 // A preferable solution to the general problem is to figure out the right
23177 // places to insert EMMS. This qualifies as a quick hack.
23179 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23180 if (VT.getSizeInBits() != 64)
23183 const Function *F = DAG.getMachineFunction().getFunction();
23184 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23186 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23187 if ((VT.isVector() ||
23188 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23189 isa<LoadSDNode>(St->getValue()) &&
23190 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23191 St->getChain().hasOneUse() && !St->isVolatile()) {
23192 SDNode* LdVal = St->getValue().getNode();
23193 LoadSDNode *Ld = nullptr;
23194 int TokenFactorIndex = -1;
23195 SmallVector<SDValue, 8> Ops;
23196 SDNode* ChainVal = St->getChain().getNode();
23197 // Must be a store of a load. We currently handle two cases: the load
23198 // is a direct child, and it's under an intervening TokenFactor. It is
23199 // possible to dig deeper under nested TokenFactors.
23200 if (ChainVal == LdVal)
23201 Ld = cast<LoadSDNode>(St->getChain());
23202 else if (St->getValue().hasOneUse() &&
23203 ChainVal->getOpcode() == ISD::TokenFactor) {
23204 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23205 if (ChainVal->getOperand(i).getNode() == LdVal) {
23206 TokenFactorIndex = i;
23207 Ld = cast<LoadSDNode>(St->getValue());
23209 Ops.push_back(ChainVal->getOperand(i));
23213 if (!Ld || !ISD::isNormalLoad(Ld))
23216 // If this is not the MMX case, i.e. we are just turning i64 load/store
23217 // into f64 load/store, avoid the transformation if there are multiple
23218 // uses of the loaded value.
23219 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23224 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23225 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23227 if (Subtarget->is64Bit() || F64IsLegal) {
23228 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23229 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23230 Ld->getPointerInfo(), Ld->isVolatile(),
23231 Ld->isNonTemporal(), Ld->isInvariant(),
23232 Ld->getAlignment());
23233 SDValue NewChain = NewLd.getValue(1);
23234 if (TokenFactorIndex != -1) {
23235 Ops.push_back(NewChain);
23236 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23238 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23239 St->getPointerInfo(),
23240 St->isVolatile(), St->isNonTemporal(),
23241 St->getAlignment());
23244 // Otherwise, lower to two pairs of 32-bit loads / stores.
23245 SDValue LoAddr = Ld->getBasePtr();
23246 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23247 DAG.getConstant(4, LdDL, MVT::i32));
23249 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23250 Ld->getPointerInfo(),
23251 Ld->isVolatile(), Ld->isNonTemporal(),
23252 Ld->isInvariant(), Ld->getAlignment());
23253 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23254 Ld->getPointerInfo().getWithOffset(4),
23255 Ld->isVolatile(), Ld->isNonTemporal(),
23257 MinAlign(Ld->getAlignment(), 4));
23259 SDValue NewChain = LoLd.getValue(1);
23260 if (TokenFactorIndex != -1) {
23261 Ops.push_back(LoLd);
23262 Ops.push_back(HiLd);
23263 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23266 LoAddr = St->getBasePtr();
23267 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23268 DAG.getConstant(4, StDL, MVT::i32));
23270 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23271 St->getPointerInfo(),
23272 St->isVolatile(), St->isNonTemporal(),
23273 St->getAlignment());
23274 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23275 St->getPointerInfo().getWithOffset(4),
23277 St->isNonTemporal(),
23278 MinAlign(St->getAlignment(), 4));
23279 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23282 // This is similar to the above case, but here we handle a scalar 64-bit
23283 // integer store that is extracted from a vector on a 32-bit target.
23284 // If we have SSE2, then we can treat it like a floating-point double
23285 // to get past legalization. The execution dependencies fixup pass will
23286 // choose the optimal machine instruction for the store if this really is
23287 // an integer or v2f32 rather than an f64.
23288 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23289 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23290 SDValue OldExtract = St->getOperand(1);
23291 SDValue ExtOp0 = OldExtract.getOperand(0);
23292 unsigned VecSize = ExtOp0.getValueSizeInBits();
23293 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23294 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
23295 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23296 BitCast, OldExtract.getOperand(1));
23297 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23298 St->getPointerInfo(), St->isVolatile(),
23299 St->isNonTemporal(), St->getAlignment());
23305 /// Return 'true' if this vector operation is "horizontal"
23306 /// and return the operands for the horizontal operation in LHS and RHS. A
23307 /// horizontal operation performs the binary operation on successive elements
23308 /// of its first operand, then on successive elements of its second operand,
23309 /// returning the resulting values in a vector. For example, if
23310 /// A = < float a0, float a1, float a2, float a3 >
23312 /// B = < float b0, float b1, float b2, float b3 >
23313 /// then the result of doing a horizontal operation on A and B is
23314 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23315 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23316 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23317 /// set to A, RHS to B, and the routine returns 'true'.
23318 /// Note that the binary operation should have the property that if one of the
23319 /// operands is UNDEF then the result is UNDEF.
23320 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23321 // Look for the following pattern: if
23322 // A = < float a0, float a1, float a2, float a3 >
23323 // B = < float b0, float b1, float b2, float b3 >
23325 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23326 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23327 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23328 // which is A horizontal-op B.
23330 // At least one of the operands should be a vector shuffle.
23331 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23332 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23335 MVT VT = LHS.getSimpleValueType();
23337 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23338 "Unsupported vector type for horizontal add/sub");
23340 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23341 // operate independently on 128-bit lanes.
23342 unsigned NumElts = VT.getVectorNumElements();
23343 unsigned NumLanes = VT.getSizeInBits()/128;
23344 unsigned NumLaneElts = NumElts / NumLanes;
23345 assert((NumLaneElts % 2 == 0) &&
23346 "Vector type should have an even number of elements in each lane");
23347 unsigned HalfLaneElts = NumLaneElts/2;
23349 // View LHS in the form
23350 // LHS = VECTOR_SHUFFLE A, B, LMask
23351 // If LHS is not a shuffle then pretend it is the shuffle
23352 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23353 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23356 SmallVector<int, 16> LMask(NumElts);
23357 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23358 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23359 A = LHS.getOperand(0);
23360 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23361 B = LHS.getOperand(1);
23362 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23363 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23365 if (LHS.getOpcode() != ISD::UNDEF)
23367 for (unsigned i = 0; i != NumElts; ++i)
23371 // Likewise, view RHS in the form
23372 // RHS = VECTOR_SHUFFLE C, D, RMask
23374 SmallVector<int, 16> RMask(NumElts);
23375 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23376 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23377 C = RHS.getOperand(0);
23378 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23379 D = RHS.getOperand(1);
23380 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23381 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23383 if (RHS.getOpcode() != ISD::UNDEF)
23385 for (unsigned i = 0; i != NumElts; ++i)
23389 // Check that the shuffles are both shuffling the same vectors.
23390 if (!(A == C && B == D) && !(A == D && B == C))
23393 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23394 if (!A.getNode() && !B.getNode())
23397 // If A and B occur in reverse order in RHS, then "swap" them (which means
23398 // rewriting the mask).
23400 ShuffleVectorSDNode::commuteMask(RMask);
23402 // At this point LHS and RHS are equivalent to
23403 // LHS = VECTOR_SHUFFLE A, B, LMask
23404 // RHS = VECTOR_SHUFFLE A, B, RMask
23405 // Check that the masks correspond to performing a horizontal operation.
23406 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23407 for (unsigned i = 0; i != NumLaneElts; ++i) {
23408 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23410 // Ignore any UNDEF components.
23411 if (LIdx < 0 || RIdx < 0 ||
23412 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23413 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23416 // Check that successive elements are being operated on. If not, this is
23417 // not a horizontal operation.
23418 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23419 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23420 if (!(LIdx == Index && RIdx == Index + 1) &&
23421 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23426 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23427 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23431 /// Do target-specific dag combines on floating point adds.
23432 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23433 const X86Subtarget *Subtarget) {
23434 EVT VT = N->getValueType(0);
23435 SDValue LHS = N->getOperand(0);
23436 SDValue RHS = N->getOperand(1);
23438 // Try to synthesize horizontal adds from adds of shuffles.
23439 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23440 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23441 isHorizontalBinOp(LHS, RHS, true))
23442 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23446 /// Do target-specific dag combines on floating point subs.
23447 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23448 const X86Subtarget *Subtarget) {
23449 EVT VT = N->getValueType(0);
23450 SDValue LHS = N->getOperand(0);
23451 SDValue RHS = N->getOperand(1);
23453 // Try to synthesize horizontal subs from subs of shuffles.
23454 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23455 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23456 isHorizontalBinOp(LHS, RHS, false))
23457 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23461 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23462 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23463 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23465 // F[X]OR(0.0, x) -> x
23466 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23467 if (C->getValueAPF().isPosZero())
23468 return N->getOperand(1);
23470 // F[X]OR(x, 0.0) -> x
23471 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23472 if (C->getValueAPF().isPosZero())
23473 return N->getOperand(0);
23477 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23478 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23479 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23481 // Only perform optimizations if UnsafeMath is used.
23482 if (!DAG.getTarget().Options.UnsafeFPMath)
23485 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23486 // into FMINC and FMAXC, which are Commutative operations.
23487 unsigned NewOp = 0;
23488 switch (N->getOpcode()) {
23489 default: llvm_unreachable("unknown opcode");
23490 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23491 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23494 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23495 N->getOperand(0), N->getOperand(1));
23498 /// Do target-specific dag combines on X86ISD::FAND nodes.
23499 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23500 // FAND(0.0, x) -> 0.0
23501 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23502 if (C->getValueAPF().isPosZero())
23503 return N->getOperand(0);
23505 // FAND(x, 0.0) -> 0.0
23506 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23507 if (C->getValueAPF().isPosZero())
23508 return N->getOperand(1);
23513 /// Do target-specific dag combines on X86ISD::FANDN nodes
23514 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23515 // FANDN(0.0, x) -> x
23516 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23517 if (C->getValueAPF().isPosZero())
23518 return N->getOperand(1);
23520 // FANDN(x, 0.0) -> 0.0
23521 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23522 if (C->getValueAPF().isPosZero())
23523 return N->getOperand(1);
23528 static SDValue PerformBTCombine(SDNode *N,
23530 TargetLowering::DAGCombinerInfo &DCI) {
23531 // BT ignores high bits in the bit index operand.
23532 SDValue Op1 = N->getOperand(1);
23533 if (Op1.hasOneUse()) {
23534 unsigned BitWidth = Op1.getValueSizeInBits();
23535 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23536 APInt KnownZero, KnownOne;
23537 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23538 !DCI.isBeforeLegalizeOps());
23539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23540 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23541 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23542 DCI.CommitTargetLoweringOpt(TLO);
23547 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23548 SDValue Op = N->getOperand(0);
23549 if (Op.getOpcode() == ISD::BITCAST)
23550 Op = Op.getOperand(0);
23551 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23552 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23553 VT.getVectorElementType().getSizeInBits() ==
23554 OpVT.getVectorElementType().getSizeInBits()) {
23555 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23560 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23561 const X86Subtarget *Subtarget) {
23562 EVT VT = N->getValueType(0);
23563 if (!VT.isVector())
23566 SDValue N0 = N->getOperand(0);
23567 SDValue N1 = N->getOperand(1);
23568 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23571 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23572 // both SSE and AVX2 since there is no sign-extended shift right
23573 // operation on a vector with 64-bit elements.
23574 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23575 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23576 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23577 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23578 SDValue N00 = N0.getOperand(0);
23580 // EXTLOAD has a better solution on AVX2,
23581 // it may be replaced with X86ISD::VSEXT node.
23582 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23583 if (!ISD::isNormalLoad(N00.getNode()))
23586 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23587 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23589 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23595 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23596 TargetLowering::DAGCombinerInfo &DCI,
23597 const X86Subtarget *Subtarget) {
23598 SDValue N0 = N->getOperand(0);
23599 EVT VT = N->getValueType(0);
23601 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23602 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23603 // This exposes the sext to the sdivrem lowering, so that it directly extends
23604 // from AH (which we otherwise need to do contortions to access).
23605 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23606 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
23608 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23609 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
23610 N0.getOperand(0), N0.getOperand(1));
23611 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23612 return R.getValue(1);
23615 if (!DCI.isBeforeLegalizeOps())
23618 if (!Subtarget->hasFp256())
23621 if (VT.isVector() && VT.getSizeInBits() == 256) {
23622 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23630 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23631 const X86Subtarget* Subtarget) {
23633 EVT VT = N->getValueType(0);
23635 // Let legalize expand this if it isn't a legal type yet.
23636 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23639 EVT ScalarVT = VT.getScalarType();
23640 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23641 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23644 SDValue A = N->getOperand(0);
23645 SDValue B = N->getOperand(1);
23646 SDValue C = N->getOperand(2);
23648 bool NegA = (A.getOpcode() == ISD::FNEG);
23649 bool NegB = (B.getOpcode() == ISD::FNEG);
23650 bool NegC = (C.getOpcode() == ISD::FNEG);
23652 // Negative multiplication when NegA xor NegB
23653 bool NegMul = (NegA != NegB);
23655 A = A.getOperand(0);
23657 B = B.getOperand(0);
23659 C = C.getOperand(0);
23663 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23665 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23667 return DAG.getNode(Opcode, dl, VT, A, B, C);
23670 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23671 TargetLowering::DAGCombinerInfo &DCI,
23672 const X86Subtarget *Subtarget) {
23673 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23674 // (and (i32 x86isd::setcc_carry), 1)
23675 // This eliminates the zext. This transformation is necessary because
23676 // ISD::SETCC is always legalized to i8.
23678 SDValue N0 = N->getOperand(0);
23679 EVT VT = N->getValueType(0);
23681 if (N0.getOpcode() == ISD::AND &&
23683 N0.getOperand(0).hasOneUse()) {
23684 SDValue N00 = N0.getOperand(0);
23685 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23686 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23687 if (!C || C->getZExtValue() != 1)
23689 return DAG.getNode(ISD::AND, dl, VT,
23690 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23691 N00.getOperand(0), N00.getOperand(1)),
23692 DAG.getConstant(1, dl, VT));
23696 if (N0.getOpcode() == ISD::TRUNCATE &&
23698 N0.getOperand(0).hasOneUse()) {
23699 SDValue N00 = N0.getOperand(0);
23700 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23701 return DAG.getNode(ISD::AND, dl, VT,
23702 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23703 N00.getOperand(0), N00.getOperand(1)),
23704 DAG.getConstant(1, dl, VT));
23707 if (VT.is256BitVector()) {
23708 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23713 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23714 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23715 // This exposes the zext to the udivrem lowering, so that it directly extends
23716 // from AH (which we otherwise need to do contortions to access).
23717 if (N0.getOpcode() == ISD::UDIVREM &&
23718 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23719 (VT == MVT::i32 || VT == MVT::i64)) {
23720 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23721 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23722 N0.getOperand(0), N0.getOperand(1));
23723 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23724 return R.getValue(1);
23730 // Optimize x == -y --> x+y == 0
23731 // x != -y --> x+y != 0
23732 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23733 const X86Subtarget* Subtarget) {
23734 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23735 SDValue LHS = N->getOperand(0);
23736 SDValue RHS = N->getOperand(1);
23737 EVT VT = N->getValueType(0);
23740 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23741 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23742 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23743 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
23744 LHS.getOperand(1));
23745 return DAG.getSetCC(DL, N->getValueType(0), addV,
23746 DAG.getConstant(0, DL, addV.getValueType()), CC);
23748 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23749 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23750 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23751 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
23752 RHS.getOperand(1));
23753 return DAG.getSetCC(DL, N->getValueType(0), addV,
23754 DAG.getConstant(0, DL, addV.getValueType()), CC);
23757 if (VT.getScalarType() == MVT::i1 &&
23758 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
23760 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23761 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23762 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23764 if (!IsSEXT0 || !IsVZero1) {
23765 // Swap the operands and update the condition code.
23766 std::swap(LHS, RHS);
23767 CC = ISD::getSetCCSwappedOperands(CC);
23769 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23770 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23771 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23774 if (IsSEXT0 && IsVZero1) {
23775 assert(VT == LHS.getOperand(0).getValueType() &&
23776 "Uexpected operand type");
23777 if (CC == ISD::SETGT)
23778 return DAG.getConstant(0, DL, VT);
23779 if (CC == ISD::SETLE)
23780 return DAG.getConstant(1, DL, VT);
23781 if (CC == ISD::SETEQ || CC == ISD::SETGE)
23782 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23784 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
23785 "Unexpected condition code!");
23786 return LHS.getOperand(0);
23793 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
23794 SelectionDAG &DAG) {
23796 MVT VT = Load->getSimpleValueType(0);
23797 MVT EVT = VT.getVectorElementType();
23798 SDValue Addr = Load->getOperand(1);
23799 SDValue NewAddr = DAG.getNode(
23800 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
23801 DAG.getConstant(Index * EVT.getStoreSize(), dl,
23802 Addr.getSimpleValueType()));
23805 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
23806 DAG.getMachineFunction().getMachineMemOperand(
23807 Load->getMemOperand(), 0, EVT.getStoreSize()));
23811 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23812 const X86Subtarget *Subtarget) {
23814 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23815 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23816 "X86insertps is only defined for v4x32");
23818 SDValue Ld = N->getOperand(1);
23819 if (MayFoldLoad(Ld)) {
23820 // Extract the countS bits from the immediate so we can get the proper
23821 // address when narrowing the vector load to a specific element.
23822 // When the second source op is a memory address, insertps doesn't use
23823 // countS and just gets an f32 from that address.
23824 unsigned DestIndex =
23825 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23827 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23829 // Create this as a scalar to vector to match the instruction pattern.
23830 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23831 // countS bits are ignored when loading from memory on insertps, which
23832 // means we don't need to explicitly set them to 0.
23833 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23834 LoadScalarToVector, N->getOperand(2));
23839 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
23840 SDValue V0 = N->getOperand(0);
23841 SDValue V1 = N->getOperand(1);
23843 EVT VT = N->getValueType(0);
23845 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23846 // operands and changing the mask to 1. This saves us a bunch of
23847 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23848 // x86InstrInfo knows how to commute this back after instruction selection
23849 // if it would help register allocation.
23851 // TODO: If optimizing for size or a processor that doesn't suffer from
23852 // partial register update stalls, this should be transformed into a MOVSD
23853 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23855 if (VT == MVT::v2f64)
23856 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23857 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23858 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
23859 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23865 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23866 // as "sbb reg,reg", since it can be extended without zext and produces
23867 // an all-ones bit which is more useful than 0/1 in some cases.
23868 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23871 return DAG.getNode(ISD::AND, DL, VT,
23872 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23873 DAG.getConstant(X86::COND_B, DL, MVT::i8),
23875 DAG.getConstant(1, DL, VT));
23876 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23877 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23878 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23879 DAG.getConstant(X86::COND_B, DL, MVT::i8),
23883 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23884 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23885 TargetLowering::DAGCombinerInfo &DCI,
23886 const X86Subtarget *Subtarget) {
23888 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23889 SDValue EFLAGS = N->getOperand(1);
23891 if (CC == X86::COND_A) {
23892 // Try to convert COND_A into COND_B in an attempt to facilitate
23893 // materializing "setb reg".
23895 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23896 // cannot take an immediate as its first operand.
23898 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23899 EFLAGS.getValueType().isInteger() &&
23900 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23901 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23902 EFLAGS.getNode()->getVTList(),
23903 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23904 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23905 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23909 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23910 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23912 if (CC == X86::COND_B)
23913 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23917 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23918 if (Flags.getNode()) {
23919 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
23920 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23926 // Optimize branch condition evaluation.
23928 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23929 TargetLowering::DAGCombinerInfo &DCI,
23930 const X86Subtarget *Subtarget) {
23932 SDValue Chain = N->getOperand(0);
23933 SDValue Dest = N->getOperand(1);
23934 SDValue EFLAGS = N->getOperand(3);
23935 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23939 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23940 if (Flags.getNode()) {
23941 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
23942 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23949 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23950 SelectionDAG &DAG) {
23951 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23952 // optimize away operation when it's from a constant.
23954 // The general transformation is:
23955 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23956 // AND(VECTOR_CMP(x,y), constant2)
23957 // constant2 = UNARYOP(constant)
23959 // Early exit if this isn't a vector operation, the operand of the
23960 // unary operation isn't a bitwise AND, or if the sizes of the operations
23961 // aren't the same.
23962 EVT VT = N->getValueType(0);
23963 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23964 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23965 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23968 // Now check that the other operand of the AND is a constant. We could
23969 // make the transformation for non-constant splats as well, but it's unclear
23970 // that would be a benefit as it would not eliminate any operations, just
23971 // perform one more step in scalar code before moving to the vector unit.
23972 if (BuildVectorSDNode *BV =
23973 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23974 // Bail out if the vector isn't a constant.
23975 if (!BV->isConstant())
23978 // Everything checks out. Build up the new and improved node.
23980 EVT IntVT = BV->getValueType(0);
23981 // Create a new constant of the appropriate type for the transformed
23983 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23984 // The AND node needs bitcasts to/from an integer vector type around it.
23985 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23986 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23987 N->getOperand(0)->getOperand(0), MaskConst);
23988 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23995 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23996 const X86Subtarget *Subtarget) {
23997 // First try to optimize away the conversion entirely when it's
23998 // conditionally from a constant. Vectors only.
23999 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24000 if (Res != SDValue())
24003 // Now move on to more general possibilities.
24004 SDValue Op0 = N->getOperand(0);
24005 EVT InVT = Op0->getValueType(0);
24007 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24008 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24010 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24011 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24012 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24015 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24016 // a 32-bit target where SSE doesn't support i64->FP operations.
24017 if (Op0.getOpcode() == ISD::LOAD) {
24018 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24019 EVT VT = Ld->getValueType(0);
24021 // This transformation is not supported if the result type is f16
24022 if (N->getValueType(0) == MVT::f16)
24025 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24026 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24027 !Subtarget->is64Bit() && VT == MVT::i64) {
24028 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24029 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24030 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24037 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24038 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24039 X86TargetLowering::DAGCombinerInfo &DCI) {
24040 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24041 // the result is either zero or one (depending on the input carry bit).
24042 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24043 if (X86::isZeroNode(N->getOperand(0)) &&
24044 X86::isZeroNode(N->getOperand(1)) &&
24045 // We don't have a good way to replace an EFLAGS use, so only do this when
24047 SDValue(N, 1).use_empty()) {
24049 EVT VT = N->getValueType(0);
24050 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24051 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24052 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24053 DAG.getConstant(X86::COND_B, DL,
24056 DAG.getConstant(1, DL, VT));
24057 return DCI.CombineTo(N, Res1, CarryOut);
24063 // fold (add Y, (sete X, 0)) -> adc 0, Y
24064 // (add Y, (setne X, 0)) -> sbb -1, Y
24065 // (sub (sete X, 0), Y) -> sbb 0, Y
24066 // (sub (setne X, 0), Y) -> adc -1, Y
24067 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24070 // Look through ZExts.
24071 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24072 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24075 SDValue SetCC = Ext.getOperand(0);
24076 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24079 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24080 if (CC != X86::COND_E && CC != X86::COND_NE)
24083 SDValue Cmp = SetCC.getOperand(1);
24084 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24085 !X86::isZeroNode(Cmp.getOperand(1)) ||
24086 !Cmp.getOperand(0).getValueType().isInteger())
24089 SDValue CmpOp0 = Cmp.getOperand(0);
24090 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24091 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24093 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24094 if (CC == X86::COND_NE)
24095 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24096 DL, OtherVal.getValueType(), OtherVal,
24097 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24099 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24100 DL, OtherVal.getValueType(), OtherVal,
24101 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24104 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24105 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24106 const X86Subtarget *Subtarget) {
24107 EVT VT = N->getValueType(0);
24108 SDValue Op0 = N->getOperand(0);
24109 SDValue Op1 = N->getOperand(1);
24111 // Try to synthesize horizontal adds from adds of shuffles.
24112 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24113 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24114 isHorizontalBinOp(Op0, Op1, true))
24115 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24117 return OptimizeConditionalInDecrement(N, DAG);
24120 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24121 const X86Subtarget *Subtarget) {
24122 SDValue Op0 = N->getOperand(0);
24123 SDValue Op1 = N->getOperand(1);
24125 // X86 can't encode an immediate LHS of a sub. See if we can push the
24126 // negation into a preceding instruction.
24127 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24128 // If the RHS of the sub is a XOR with one use and a constant, invert the
24129 // immediate. Then add one to the LHS of the sub so we can turn
24130 // X-Y -> X+~Y+1, saving one register.
24131 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24132 isa<ConstantSDNode>(Op1.getOperand(1))) {
24133 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24134 EVT VT = Op0.getValueType();
24135 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24137 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24138 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24139 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24143 // Try to synthesize horizontal adds from adds of shuffles.
24144 EVT VT = N->getValueType(0);
24145 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24146 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24147 isHorizontalBinOp(Op0, Op1, true))
24148 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24150 return OptimizeConditionalInDecrement(N, DAG);
24153 /// performVZEXTCombine - Performs build vector combines
24154 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24155 TargetLowering::DAGCombinerInfo &DCI,
24156 const X86Subtarget *Subtarget) {
24158 MVT VT = N->getSimpleValueType(0);
24159 SDValue Op = N->getOperand(0);
24160 MVT OpVT = Op.getSimpleValueType();
24161 MVT OpEltVT = OpVT.getVectorElementType();
24162 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24164 // (vzext (bitcast (vzext (x)) -> (vzext x)
24166 while (V.getOpcode() == ISD::BITCAST)
24167 V = V.getOperand(0);
24169 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24170 MVT InnerVT = V.getSimpleValueType();
24171 MVT InnerEltVT = InnerVT.getVectorElementType();
24173 // If the element sizes match exactly, we can just do one larger vzext. This
24174 // is always an exact type match as vzext operates on integer types.
24175 if (OpEltVT == InnerEltVT) {
24176 assert(OpVT == InnerVT && "Types must match for vzext!");
24177 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24180 // The only other way we can combine them is if only a single element of the
24181 // inner vzext is used in the input to the outer vzext.
24182 if (InnerEltVT.getSizeInBits() < InputBits)
24185 // In this case, the inner vzext is completely dead because we're going to
24186 // only look at bits inside of the low element. Just do the outer vzext on
24187 // a bitcast of the input to the inner.
24188 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24189 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24192 // Check if we can bypass extracting and re-inserting an element of an input
24193 // vector. Essentialy:
24194 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24195 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24196 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24197 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24198 SDValue ExtractedV = V.getOperand(0);
24199 SDValue OrigV = ExtractedV.getOperand(0);
24200 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24201 if (ExtractIdx->getZExtValue() == 0) {
24202 MVT OrigVT = OrigV.getSimpleValueType();
24203 // Extract a subvector if necessary...
24204 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24205 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24206 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24207 OrigVT.getVectorNumElements() / Ratio);
24208 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24209 DAG.getIntPtrConstant(0, DL));
24211 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24212 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24219 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24220 DAGCombinerInfo &DCI) const {
24221 SelectionDAG &DAG = DCI.DAG;
24222 switch (N->getOpcode()) {
24224 case ISD::EXTRACT_VECTOR_ELT:
24225 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24228 case X86ISD::SHRUNKBLEND:
24229 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24230 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24231 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24232 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24233 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24234 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24235 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24238 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24239 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24240 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24241 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24242 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24243 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24244 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24245 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24246 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24247 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24248 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24250 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24252 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24253 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24254 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24255 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24256 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24257 case ISD::ANY_EXTEND:
24258 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24259 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24260 case ISD::SIGN_EXTEND_INREG:
24261 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24262 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24263 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24264 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24265 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24266 case X86ISD::SHUFP: // Handle all target specific shuffles
24267 case X86ISD::PALIGNR:
24268 case X86ISD::UNPCKH:
24269 case X86ISD::UNPCKL:
24270 case X86ISD::MOVHLPS:
24271 case X86ISD::MOVLHPS:
24272 case X86ISD::PSHUFB:
24273 case X86ISD::PSHUFD:
24274 case X86ISD::PSHUFHW:
24275 case X86ISD::PSHUFLW:
24276 case X86ISD::MOVSS:
24277 case X86ISD::MOVSD:
24278 case X86ISD::VPERMILPI:
24279 case X86ISD::VPERM2X128:
24280 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24281 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24282 case ISD::INTRINSIC_WO_CHAIN:
24283 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24284 case X86ISD::INSERTPS: {
24285 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24286 return PerformINSERTPSCombine(N, DAG, Subtarget);
24289 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24295 /// isTypeDesirableForOp - Return true if the target has native support for
24296 /// the specified value type and it is 'desirable' to use the type for the
24297 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24298 /// instruction encodings are longer and some i16 instructions are slow.
24299 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24300 if (!isTypeLegal(VT))
24302 if (VT != MVT::i16)
24309 case ISD::SIGN_EXTEND:
24310 case ISD::ZERO_EXTEND:
24311 case ISD::ANY_EXTEND:
24324 /// IsDesirableToPromoteOp - This method query the target whether it is
24325 /// beneficial for dag combiner to promote the specified node. If true, it
24326 /// should return the desired promotion type by reference.
24327 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24328 EVT VT = Op.getValueType();
24329 if (VT != MVT::i16)
24332 bool Promote = false;
24333 bool Commute = false;
24334 switch (Op.getOpcode()) {
24337 LoadSDNode *LD = cast<LoadSDNode>(Op);
24338 // If the non-extending load has a single use and it's not live out, then it
24339 // might be folded.
24340 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24341 Op.hasOneUse()*/) {
24342 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24343 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24344 // The only case where we'd want to promote LOAD (rather then it being
24345 // promoted as an operand is when it's only use is liveout.
24346 if (UI->getOpcode() != ISD::CopyToReg)
24353 case ISD::SIGN_EXTEND:
24354 case ISD::ZERO_EXTEND:
24355 case ISD::ANY_EXTEND:
24360 SDValue N0 = Op.getOperand(0);
24361 // Look out for (store (shl (load), x)).
24362 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24375 SDValue N0 = Op.getOperand(0);
24376 SDValue N1 = Op.getOperand(1);
24377 if (!Commute && MayFoldLoad(N1))
24379 // Avoid disabling potential load folding opportunities.
24380 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24382 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24392 //===----------------------------------------------------------------------===//
24393 // X86 Inline Assembly Support
24394 //===----------------------------------------------------------------------===//
24396 // Helper to match a string separated by whitespace.
24397 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24398 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24400 for (StringRef Piece : Pieces) {
24401 if (!S.startswith(Piece)) // Check if the piece matches.
24404 S = S.substr(Piece.size());
24405 StringRef::size_type Pos = S.find_first_not_of(" \t");
24406 if (Pos == 0) // We matched a prefix.
24415 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24417 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24418 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24419 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24420 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24422 if (AsmPieces.size() == 3)
24424 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24431 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24432 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24434 std::string AsmStr = IA->getAsmString();
24436 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24437 if (!Ty || Ty->getBitWidth() % 16 != 0)
24440 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24441 SmallVector<StringRef, 4> AsmPieces;
24442 SplitString(AsmStr, AsmPieces, ";\n");
24444 switch (AsmPieces.size()) {
24445 default: return false;
24447 // FIXME: this should verify that we are targeting a 486 or better. If not,
24448 // we will turn this bswap into something that will be lowered to logical
24449 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24450 // lower so don't worry about this.
24452 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24453 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24454 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24455 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24456 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24457 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24458 // No need to check constraints, nothing other than the equivalent of
24459 // "=r,0" would be valid here.
24460 return IntrinsicLowering::LowerToByteSwap(CI);
24463 // rorw $$8, ${0:w} --> llvm.bswap.i16
24464 if (CI->getType()->isIntegerTy(16) &&
24465 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24466 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24467 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24469 const std::string &ConstraintsStr = IA->getConstraintString();
24470 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24471 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24472 if (clobbersFlagRegisters(AsmPieces))
24473 return IntrinsicLowering::LowerToByteSwap(CI);
24477 if (CI->getType()->isIntegerTy(32) &&
24478 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24479 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24480 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24481 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24483 const std::string &ConstraintsStr = IA->getConstraintString();
24484 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24485 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24486 if (clobbersFlagRegisters(AsmPieces))
24487 return IntrinsicLowering::LowerToByteSwap(CI);
24490 if (CI->getType()->isIntegerTy(64)) {
24491 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24492 if (Constraints.size() >= 2 &&
24493 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24494 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24495 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24496 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24497 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24498 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24499 return IntrinsicLowering::LowerToByteSwap(CI);
24507 /// getConstraintType - Given a constraint letter, return the type of
24508 /// constraint it is for this target.
24509 X86TargetLowering::ConstraintType
24510 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24511 if (Constraint.size() == 1) {
24512 switch (Constraint[0]) {
24523 return C_RegisterClass;
24547 return TargetLowering::getConstraintType(Constraint);
24550 /// Examine constraint type and operand type and determine a weight value.
24551 /// This object must already have been set up with the operand type
24552 /// and the current alternative constraint selected.
24553 TargetLowering::ConstraintWeight
24554 X86TargetLowering::getSingleConstraintMatchWeight(
24555 AsmOperandInfo &info, const char *constraint) const {
24556 ConstraintWeight weight = CW_Invalid;
24557 Value *CallOperandVal = info.CallOperandVal;
24558 // If we don't have a value, we can't do a match,
24559 // but allow it at the lowest weight.
24560 if (!CallOperandVal)
24562 Type *type = CallOperandVal->getType();
24563 // Look at the constraint type.
24564 switch (*constraint) {
24566 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24577 if (CallOperandVal->getType()->isIntegerTy())
24578 weight = CW_SpecificReg;
24583 if (type->isFloatingPointTy())
24584 weight = CW_SpecificReg;
24587 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24588 weight = CW_SpecificReg;
24592 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24593 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24594 weight = CW_Register;
24597 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24598 if (C->getZExtValue() <= 31)
24599 weight = CW_Constant;
24603 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24604 if (C->getZExtValue() <= 63)
24605 weight = CW_Constant;
24609 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24610 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24611 weight = CW_Constant;
24615 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24616 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24617 weight = CW_Constant;
24621 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24622 if (C->getZExtValue() <= 3)
24623 weight = CW_Constant;
24627 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24628 if (C->getZExtValue() <= 0xff)
24629 weight = CW_Constant;
24634 if (isa<ConstantFP>(CallOperandVal)) {
24635 weight = CW_Constant;
24639 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24640 if ((C->getSExtValue() >= -0x80000000LL) &&
24641 (C->getSExtValue() <= 0x7fffffffLL))
24642 weight = CW_Constant;
24646 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24647 if (C->getZExtValue() <= 0xffffffff)
24648 weight = CW_Constant;
24655 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24656 /// with another that has more specific requirements based on the type of the
24657 /// corresponding operand.
24658 const char *X86TargetLowering::
24659 LowerXConstraint(EVT ConstraintVT) const {
24660 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24661 // 'f' like normal targets.
24662 if (ConstraintVT.isFloatingPoint()) {
24663 if (Subtarget->hasSSE2())
24665 if (Subtarget->hasSSE1())
24669 return TargetLowering::LowerXConstraint(ConstraintVT);
24672 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24673 /// vector. If it is invalid, don't add anything to Ops.
24674 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24675 std::string &Constraint,
24676 std::vector<SDValue>&Ops,
24677 SelectionDAG &DAG) const {
24680 // Only support length 1 constraints for now.
24681 if (Constraint.length() > 1) return;
24683 char ConstraintLetter = Constraint[0];
24684 switch (ConstraintLetter) {
24687 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24688 if (C->getZExtValue() <= 31) {
24689 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24690 Op.getValueType());
24696 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24697 if (C->getZExtValue() <= 63) {
24698 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24699 Op.getValueType());
24705 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24706 if (isInt<8>(C->getSExtValue())) {
24707 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24708 Op.getValueType());
24714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24715 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24716 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24717 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
24718 Op.getValueType());
24724 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24725 if (C->getZExtValue() <= 3) {
24726 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24727 Op.getValueType());
24733 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24734 if (C->getZExtValue() <= 255) {
24735 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24736 Op.getValueType());
24742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24743 if (C->getZExtValue() <= 127) {
24744 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24745 Op.getValueType());
24751 // 32-bit signed value
24752 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24753 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24754 C->getSExtValue())) {
24755 // Widen to 64 bits here to get it sign extended.
24756 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
24759 // FIXME gcc accepts some relocatable values here too, but only in certain
24760 // memory models; it's complicated.
24765 // 32-bit unsigned value
24766 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24767 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24768 C->getZExtValue())) {
24769 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24770 Op.getValueType());
24774 // FIXME gcc accepts some relocatable values here too, but only in certain
24775 // memory models; it's complicated.
24779 // Literal immediates are always ok.
24780 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24781 // Widen to 64 bits here to get it sign extended.
24782 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
24786 // In any sort of PIC mode addresses need to be computed at runtime by
24787 // adding in a register or some sort of table lookup. These can't
24788 // be used as immediates.
24789 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24792 // If we are in non-pic codegen mode, we allow the address of a global (with
24793 // an optional displacement) to be used with 'i'.
24794 GlobalAddressSDNode *GA = nullptr;
24795 int64_t Offset = 0;
24797 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24799 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24800 Offset += GA->getOffset();
24802 } else if (Op.getOpcode() == ISD::ADD) {
24803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24804 Offset += C->getZExtValue();
24805 Op = Op.getOperand(0);
24808 } else if (Op.getOpcode() == ISD::SUB) {
24809 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24810 Offset += -C->getZExtValue();
24811 Op = Op.getOperand(0);
24816 // Otherwise, this isn't something we can handle, reject it.
24820 const GlobalValue *GV = GA->getGlobal();
24821 // If we require an extra load to get this address, as in PIC mode, we
24822 // can't accept it.
24823 if (isGlobalStubReference(
24824 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24827 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24828 GA->getValueType(0), Offset);
24833 if (Result.getNode()) {
24834 Ops.push_back(Result);
24837 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24840 std::pair<unsigned, const TargetRegisterClass *>
24841 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
24842 const std::string &Constraint,
24844 // First, see if this is a constraint that directly corresponds to an LLVM
24846 if (Constraint.size() == 1) {
24847 // GCC Constraint Letters
24848 switch (Constraint[0]) {
24850 // TODO: Slight differences here in allocation order and leaving
24851 // RIP in the class. Do they matter any more here than they do
24852 // in the normal allocation?
24853 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24854 if (Subtarget->is64Bit()) {
24855 if (VT == MVT::i32 || VT == MVT::f32)
24856 return std::make_pair(0U, &X86::GR32RegClass);
24857 if (VT == MVT::i16)
24858 return std::make_pair(0U, &X86::GR16RegClass);
24859 if (VT == MVT::i8 || VT == MVT::i1)
24860 return std::make_pair(0U, &X86::GR8RegClass);
24861 if (VT == MVT::i64 || VT == MVT::f64)
24862 return std::make_pair(0U, &X86::GR64RegClass);
24865 // 32-bit fallthrough
24866 case 'Q': // Q_REGS
24867 if (VT == MVT::i32 || VT == MVT::f32)
24868 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24869 if (VT == MVT::i16)
24870 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24871 if (VT == MVT::i8 || VT == MVT::i1)
24872 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24873 if (VT == MVT::i64)
24874 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24876 case 'r': // GENERAL_REGS
24877 case 'l': // INDEX_REGS
24878 if (VT == MVT::i8 || VT == MVT::i1)
24879 return std::make_pair(0U, &X86::GR8RegClass);
24880 if (VT == MVT::i16)
24881 return std::make_pair(0U, &X86::GR16RegClass);
24882 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24883 return std::make_pair(0U, &X86::GR32RegClass);
24884 return std::make_pair(0U, &X86::GR64RegClass);
24885 case 'R': // LEGACY_REGS
24886 if (VT == MVT::i8 || VT == MVT::i1)
24887 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24888 if (VT == MVT::i16)
24889 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24890 if (VT == MVT::i32 || !Subtarget->is64Bit())
24891 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24892 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24893 case 'f': // FP Stack registers.
24894 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24895 // value to the correct fpstack register class.
24896 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24897 return std::make_pair(0U, &X86::RFP32RegClass);
24898 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24899 return std::make_pair(0U, &X86::RFP64RegClass);
24900 return std::make_pair(0U, &X86::RFP80RegClass);
24901 case 'y': // MMX_REGS if MMX allowed.
24902 if (!Subtarget->hasMMX()) break;
24903 return std::make_pair(0U, &X86::VR64RegClass);
24904 case 'Y': // SSE_REGS if SSE2 allowed
24905 if (!Subtarget->hasSSE2()) break;
24907 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24908 if (!Subtarget->hasSSE1()) break;
24910 switch (VT.SimpleTy) {
24912 // Scalar SSE types.
24915 return std::make_pair(0U, &X86::FR32RegClass);
24918 return std::make_pair(0U, &X86::FR64RegClass);
24926 return std::make_pair(0U, &X86::VR128RegClass);
24934 return std::make_pair(0U, &X86::VR256RegClass);
24939 return std::make_pair(0U, &X86::VR512RegClass);
24945 // Use the default implementation in TargetLowering to convert the register
24946 // constraint into a member of a register class.
24947 std::pair<unsigned, const TargetRegisterClass*> Res;
24948 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
24950 // Not found as a standard register?
24952 // Map st(0) -> st(7) -> ST0
24953 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24954 tolower(Constraint[1]) == 's' &&
24955 tolower(Constraint[2]) == 't' &&
24956 Constraint[3] == '(' &&
24957 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24958 Constraint[5] == ')' &&
24959 Constraint[6] == '}') {
24961 Res.first = X86::FP0+Constraint[4]-'0';
24962 Res.second = &X86::RFP80RegClass;
24966 // GCC allows "st(0)" to be called just plain "st".
24967 if (StringRef("{st}").equals_lower(Constraint)) {
24968 Res.first = X86::FP0;
24969 Res.second = &X86::RFP80RegClass;
24974 if (StringRef("{flags}").equals_lower(Constraint)) {
24975 Res.first = X86::EFLAGS;
24976 Res.second = &X86::CCRRegClass;
24980 // 'A' means EAX + EDX.
24981 if (Constraint == "A") {
24982 Res.first = X86::EAX;
24983 Res.second = &X86::GR32_ADRegClass;
24989 // Otherwise, check to see if this is a register class of the wrong value
24990 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24991 // turn into {ax},{dx}.
24992 if (Res.second->hasType(VT))
24993 return Res; // Correct type already, nothing to do.
24995 // All of the single-register GCC register classes map their values onto
24996 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24997 // really want an 8-bit or 32-bit register, map to the appropriate register
24998 // class and return the appropriate register.
24999 if (Res.second == &X86::GR16RegClass) {
25000 if (VT == MVT::i8 || VT == MVT::i1) {
25001 unsigned DestReg = 0;
25002 switch (Res.first) {
25004 case X86::AX: DestReg = X86::AL; break;
25005 case X86::DX: DestReg = X86::DL; break;
25006 case X86::CX: DestReg = X86::CL; break;
25007 case X86::BX: DestReg = X86::BL; break;
25010 Res.first = DestReg;
25011 Res.second = &X86::GR8RegClass;
25013 } else if (VT == MVT::i32 || VT == MVT::f32) {
25014 unsigned DestReg = 0;
25015 switch (Res.first) {
25017 case X86::AX: DestReg = X86::EAX; break;
25018 case X86::DX: DestReg = X86::EDX; break;
25019 case X86::CX: DestReg = X86::ECX; break;
25020 case X86::BX: DestReg = X86::EBX; break;
25021 case X86::SI: DestReg = X86::ESI; break;
25022 case X86::DI: DestReg = X86::EDI; break;
25023 case X86::BP: DestReg = X86::EBP; break;
25024 case X86::SP: DestReg = X86::ESP; break;
25027 Res.first = DestReg;
25028 Res.second = &X86::GR32RegClass;
25030 } else if (VT == MVT::i64 || VT == MVT::f64) {
25031 unsigned DestReg = 0;
25032 switch (Res.first) {
25034 case X86::AX: DestReg = X86::RAX; break;
25035 case X86::DX: DestReg = X86::RDX; break;
25036 case X86::CX: DestReg = X86::RCX; break;
25037 case X86::BX: DestReg = X86::RBX; break;
25038 case X86::SI: DestReg = X86::RSI; break;
25039 case X86::DI: DestReg = X86::RDI; break;
25040 case X86::BP: DestReg = X86::RBP; break;
25041 case X86::SP: DestReg = X86::RSP; break;
25044 Res.first = DestReg;
25045 Res.second = &X86::GR64RegClass;
25048 } else if (Res.second == &X86::FR32RegClass ||
25049 Res.second == &X86::FR64RegClass ||
25050 Res.second == &X86::VR128RegClass ||
25051 Res.second == &X86::VR256RegClass ||
25052 Res.second == &X86::FR32XRegClass ||
25053 Res.second == &X86::FR64XRegClass ||
25054 Res.second == &X86::VR128XRegClass ||
25055 Res.second == &X86::VR256XRegClass ||
25056 Res.second == &X86::VR512RegClass) {
25057 // Handle references to XMM physical registers that got mapped into the
25058 // wrong class. This can happen with constraints like {xmm0} where the
25059 // target independent register mapper will just pick the first match it can
25060 // find, ignoring the required type.
25062 if (VT == MVT::f32 || VT == MVT::i32)
25063 Res.second = &X86::FR32RegClass;
25064 else if (VT == MVT::f64 || VT == MVT::i64)
25065 Res.second = &X86::FR64RegClass;
25066 else if (X86::VR128RegClass.hasType(VT))
25067 Res.second = &X86::VR128RegClass;
25068 else if (X86::VR256RegClass.hasType(VT))
25069 Res.second = &X86::VR256RegClass;
25070 else if (X86::VR512RegClass.hasType(VT))
25071 Res.second = &X86::VR512RegClass;
25077 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25079 // Scaling factors are not free at all.
25080 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25081 // will take 2 allocations in the out of order engine instead of 1
25082 // for plain addressing mode, i.e. inst (reg1).
25084 // vaddps (%rsi,%drx), %ymm0, %ymm1
25085 // Requires two allocations (one for the load, one for the computation)
25087 // vaddps (%rsi), %ymm0, %ymm1
25088 // Requires just 1 allocation, i.e., freeing allocations for other operations
25089 // and having less micro operations to execute.
25091 // For some X86 architectures, this is even worse because for instance for
25092 // stores, the complex addressing mode forces the instruction to use the
25093 // "load" ports instead of the dedicated "store" port.
25094 // E.g., on Haswell:
25095 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25096 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25097 if (isLegalAddressingMode(AM, Ty))
25098 // Scale represents reg2 * scale, thus account for 1
25099 // as soon as we use a second register.
25100 return AM.Scale != 0;
25104 bool X86TargetLowering::isTargetFTOL() const {
25105 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();