1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
62 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
63 SelectionDAG &DAG, SDLoc dl,
64 unsigned vectorWidth) {
65 assert((vectorWidth == 128 || vectorWidth == 256) &&
66 "Unsupported vector width");
67 EVT VT = Vec.getValueType();
68 EVT ElVT = VT.getVectorElementType();
69 unsigned Factor = VT.getSizeInBits()/vectorWidth;
70 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
71 VT.getVectorNumElements()/Factor);
73 // Extract from UNDEF is UNDEF.
74 if (Vec.getOpcode() == ISD::UNDEF)
75 return DAG.getUNDEF(ResultVT);
77 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
78 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
80 // This is the index of the first element of the vectorWidth-bit chunk
82 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
85 // If the input is a buildvector just emit a smaller one.
86 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
88 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
90 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
97 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
98 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
99 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
100 /// instructions or a simple subregister reference. Idx is an index in the
101 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
102 /// lowering EXTRACT_VECTOR_ELT operations easier.
103 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
104 SelectionDAG &DAG, SDLoc dl) {
105 assert((Vec.getValueType().is256BitVector() ||
106 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
107 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
110 /// Generate a DAG to grab 256-bits from a 512-bit vector.
111 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
112 SelectionDAG &DAG, SDLoc dl) {
113 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
114 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
117 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
118 unsigned IdxVal, SelectionDAG &DAG,
119 SDLoc dl, unsigned vectorWidth) {
120 assert((vectorWidth == 128 || vectorWidth == 256) &&
121 "Unsupported vector width");
122 // Inserting UNDEF is Result
123 if (Vec.getOpcode() == ISD::UNDEF)
125 EVT VT = Vec.getValueType();
126 EVT ElVT = VT.getVectorElementType();
127 EVT ResultVT = Result.getValueType();
129 // Insert the relevant vectorWidth bits.
130 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
132 // This is the index of the first element of the vectorWidth-bit chunk
134 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
137 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
141 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
142 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
143 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
144 /// simple superregister reference. Idx is an index in the 128 bits
145 /// we want. It need not be aligned to a 128-bit bounday. That makes
146 /// lowering INSERT_VECTOR_ELT operations easier.
147 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
148 unsigned IdxVal, SelectionDAG &DAG,
150 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
151 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
154 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
155 unsigned IdxVal, SelectionDAG &DAG,
157 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
158 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
161 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
162 /// instructions. This is used because creating CONCAT_VECTOR nodes of
163 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
164 /// large BUILD_VECTORS.
165 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
166 unsigned NumElems, SelectionDAG &DAG,
168 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
169 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
172 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
173 unsigned NumElems, SelectionDAG &DAG,
175 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
176 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
179 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
180 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
181 bool is64Bit = Subtarget->is64Bit();
183 if (Subtarget->isTargetMacho()) {
185 return new X86_64MachoTargetObjectFile();
186 return new TargetLoweringObjectFileMachO();
189 if (Subtarget->isTargetLinux())
190 return new X86LinuxTargetObjectFile();
191 if (Subtarget->isTargetELF())
192 return new TargetLoweringObjectFileELF();
193 if (Subtarget->isTargetCOFF())
194 return new TargetLoweringObjectFileCOFF();
195 llvm_unreachable("unknown subtarget type");
198 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
199 : TargetLowering(TM, createTLOF(TM)) {
200 Subtarget = &TM.getSubtarget<X86Subtarget>();
201 X86ScalarSSEf64 = Subtarget->hasSSE2();
202 X86ScalarSSEf32 = Subtarget->hasSSE1();
203 TD = getDataLayout();
205 resetOperationActions();
208 void X86TargetLowering::resetOperationActions() {
209 const TargetMachine &TM = getTargetMachine();
210 static bool FirstTimeThrough = true;
212 // If none of the target options have changed, then we don't need to reset the
213 // operation actions.
214 if (!FirstTimeThrough && TO == TM.Options) return;
216 if (!FirstTimeThrough) {
217 // Reinitialize the actions.
219 FirstTimeThrough = false;
224 // Set up the TargetLowering object.
225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
227 // X86 is weird, it always uses i8 for shift amounts and setcc results.
228 setBooleanContents(ZeroOrOneBooleanContent);
229 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // For 64-bit since we have so many registers use the ILP scheduler, for
233 // 32-bit code use the register pressure specific scheduling.
234 // For Atom, always use ILP scheduling.
235 if (Subtarget->isAtom())
236 setSchedulingPreference(Sched::ILP);
237 else if (Subtarget->is64Bit())
238 setSchedulingPreference(Sched::ILP);
240 setSchedulingPreference(Sched::RegPressure);
241 const X86RegisterInfo *RegInfo =
242 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
243 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
245 // Bypass expensive divides on Atom when compiling with O2
246 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
247 addBypassSlowDiv(32, 8);
248 if (Subtarget->is64Bit())
249 addBypassSlowDiv(64, 16);
252 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
253 // Setup Windows compiler runtime calls.
254 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
255 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
256 setLibcallName(RTLIB::SREM_I64, "_allrem");
257 setLibcallName(RTLIB::UREM_I64, "_aullrem");
258 setLibcallName(RTLIB::MUL_I64, "_allmul");
259 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
265 // The _ftol2 runtime function has an unusual calling conv, which
266 // is modeled by a special pseudo-instruction.
267 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
270 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
273 if (Subtarget->isTargetDarwin()) {
274 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
275 setUseUnderscoreSetJmp(false);
276 setUseUnderscoreLongJmp(false);
277 } else if (Subtarget->isTargetMingw()) {
278 // MS runtime is weird: it exports _setjmp, but longjmp!
279 setUseUnderscoreSetJmp(true);
280 setUseUnderscoreLongJmp(false);
282 setUseUnderscoreSetJmp(true);
283 setUseUnderscoreLongJmp(true);
286 // Set up the register classes.
287 addRegisterClass(MVT::i8, &X86::GR8RegClass);
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
289 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 if (Subtarget->is64Bit())
291 addRegisterClass(MVT::i64, &X86::GR64RegClass);
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
295 // We don't accept any truncstore of integer registers.
296 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
303 // SETOEQ and SETUNE require checking two conditions.
304 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
311 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
313 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
320 } else if (!TM.Options.UseSoftFloat) {
321 // We have an algorithm for SSE2->double, and we turn this into a
322 // 64-bit FILD followed by conditional FADD for other targets.
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 // We have an algorithm for SSE2, and we turn this into a 64-bit
325 // FILD for other targets.
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
329 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
331 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
332 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
334 if (!TM.Options.UseSoftFloat) {
335 // SSE has no i16 to fp conversion, only i32
336 if (X86ScalarSSEf32) {
337 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
338 // f32 and f64 cases are Legal, f80 case is not
339 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
349 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
350 // are Legal, f80 is custom lowered.
351 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
354 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
356 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
357 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
359 if (X86ScalarSSEf32) {
360 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
361 // f32 and f64 cases are Legal, f80 case is not
362 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 // Handle FP_TO_UINT by promoting the destination to a larger signed
370 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
374 if (Subtarget->is64Bit()) {
375 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
377 } else if (!TM.Options.UseSoftFloat) {
378 // Since AVX is a superset of SSE3, only check for SSE here.
379 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
380 // Expand FP_TO_UINT into a select.
381 // FIXME: We would like to use a Custom expander here eventually to do
382 // the optimal thing for SSE vs. the default expansion in the legalizer.
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
385 // With SSE3 we can use fisttpll to convert to a signed i64; without
386 // SSE, we're stuck with a fistpll.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
390 if (isTargetFTOL()) {
391 // Use the _ftol2 runtime function, which has a pseudo-instruction
392 // to handle its weird calling convention.
393 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
396 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
397 if (!X86ScalarSSEf64) {
398 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
399 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
402 // Without SSE, i64->f64 goes through memory.
403 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
407 // Scalar integer divide and remainder are lowered to use operations that
408 // produce two results, to match the available instructions. This exposes
409 // the two-result form to trivial CSE, which is able to combine x/y and x%y
410 // into a single instruction.
412 // Scalar integer multiply-high is also lowered to use two-result
413 // operations, to match the available instructions. However, plain multiply
414 // (low) operations are left as Legal, as there are single-result
415 // instructions for this in x86. Using the two-result multiply instructions
416 // when both high and low results are needed must be arranged by dagcombine.
417 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
419 setOperationAction(ISD::MULHS, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::SDIV, VT, Expand);
422 setOperationAction(ISD::UDIV, VT, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
424 setOperationAction(ISD::UREM, VT, Expand);
426 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
427 setOperationAction(ISD::ADDC, VT, Custom);
428 setOperationAction(ISD::ADDE, VT, Custom);
429 setOperationAction(ISD::SUBC, VT, Custom);
430 setOperationAction(ISD::SUBE, VT, Custom);
433 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
434 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
435 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
448 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f64 , Expand);
451 setOperationAction(ISD::FREM , MVT::f80 , Expand);
452 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
454 // Promote the i8 variants and force them on up to i32 which has a shorter
456 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
457 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
458 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
459 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
460 if (Subtarget->hasBMI()) {
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
463 if (Subtarget->is64Bit())
464 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
466 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
467 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
468 if (Subtarget->is64Bit())
469 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
472 if (Subtarget->hasLZCNT()) {
473 // When promoting the i8 variants, force them to i32 for a shorter
475 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
476 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
478 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
490 if (Subtarget->is64Bit()) {
491 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
496 if (Subtarget->hasPOPCNT()) {
497 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
499 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
502 if (Subtarget->is64Bit())
503 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
506 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
507 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
509 // These should be promoted to a larger select which is supported.
510 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
511 // X86 wants to expand cmov itself.
512 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
524 if (Subtarget->is64Bit()) {
525 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
528 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
529 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
530 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
531 // support continuation, user-level threading, and etc.. As a result, no
532 // other SjLj exception interfaces are implemented and please don't build
533 // your own exception handling based on them.
534 // LLVM/Clang supports zero-cost DWARF exception handling.
535 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
536 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
539 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
540 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
545 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
546 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
549 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
550 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
551 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
554 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
555 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
564 if (Subtarget->hasSSE1())
565 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
567 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
569 // Expand certain atomics
570 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
572 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
574 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
577 if (!Subtarget->is64Bit()) {
578 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
592 if (Subtarget->hasCmpxchg16b()) {
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
596 // FIXME - use subtarget debug flags
597 if (!Subtarget->isTargetDarwin() &&
598 !Subtarget->isTargetELF() &&
599 !Subtarget->isTargetCygMing()) {
600 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
603 if (Subtarget->is64Bit()) {
604 setExceptionPointerRegister(X86::RAX);
605 setExceptionSelectorRegister(X86::RDX);
607 setExceptionPointerRegister(X86::EAX);
608 setExceptionSelectorRegister(X86::EDX);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
613 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
614 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
616 setOperationAction(ISD::TRAP, MVT::Other, Legal);
617 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
619 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
620 setOperationAction(ISD::VASTART , MVT::Other, Custom);
621 setOperationAction(ISD::VAEND , MVT::Other, Expand);
622 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
623 // TargetInfo::X86_64ABIBuiltinVaList
624 setOperationAction(ISD::VAARG , MVT::Other, Custom);
625 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
627 // TargetInfo::CharPtrBuiltinVaList
628 setOperationAction(ISD::VAARG , MVT::Other, Expand);
629 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
632 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
633 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
635 if (Subtarget->isOSWindows() && !Subtarget->isTargetMacho())
636 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
637 MVT::i64 : MVT::i32, Custom);
638 else if (TM.Options.EnableSegmentedStacks)
639 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
640 MVT::i64 : MVT::i32, Custom);
642 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
643 MVT::i64 : MVT::i32, Expand);
645 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
646 // f32 and f64 use SSE.
647 // Set up the FP register classes.
648 addRegisterClass(MVT::f32, &X86::FR32RegClass);
649 addRegisterClass(MVT::f64, &X86::FR64RegClass);
651 // Use ANDPD to simulate FABS.
652 setOperationAction(ISD::FABS , MVT::f64, Custom);
653 setOperationAction(ISD::FABS , MVT::f32, Custom);
655 // Use XORP to simulate FNEG.
656 setOperationAction(ISD::FNEG , MVT::f64, Custom);
657 setOperationAction(ISD::FNEG , MVT::f32, Custom);
659 // Use ANDPD and ORPD to simulate FCOPYSIGN.
660 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
663 // Lower this to FGETSIGNx86 plus an AND.
664 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
665 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
667 // We don't support sin/cos/fmod
668 setOperationAction(ISD::FSIN , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f64, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSIN , MVT::f32, Expand);
672 setOperationAction(ISD::FCOS , MVT::f32, Expand);
673 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
675 // Expand FP immediates into loads from the stack, except for the special
677 addLegalFPImmediate(APFloat(+0.0)); // xorpd
678 addLegalFPImmediate(APFloat(+0.0f)); // xorps
679 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
680 // Use SSE for f32, x87 for f64.
681 // Set up the FP register classes.
682 addRegisterClass(MVT::f32, &X86::FR32RegClass);
683 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
685 // Use ANDPS to simulate FABS.
686 setOperationAction(ISD::FABS , MVT::f32, Custom);
688 // Use XORP to simulate FNEG.
689 setOperationAction(ISD::FNEG , MVT::f32, Custom);
691 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
693 // Use ANDPS and ORPS to simulate FCOPYSIGN.
694 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
695 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
697 // We don't support sin/cos/fmod
698 setOperationAction(ISD::FSIN , MVT::f32, Expand);
699 setOperationAction(ISD::FCOS , MVT::f32, Expand);
700 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
702 // Special cases we handle for FP constants.
703 addLegalFPImmediate(APFloat(+0.0f)); // xorps
704 addLegalFPImmediate(APFloat(+0.0)); // FLD0
705 addLegalFPImmediate(APFloat(+1.0)); // FLD1
706 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
707 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FCOS , MVT::f64, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
714 } else if (!TM.Options.UseSoftFloat) {
715 // f32 and f64 in x87.
716 // Set up the FP register classes.
717 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
718 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
720 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
721 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
725 if (!TM.Options.UnsafeFPMath) {
726 setOperationAction(ISD::FSIN , MVT::f64, Expand);
727 setOperationAction(ISD::FSIN , MVT::f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FCOS , MVT::f32, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
733 addLegalFPImmediate(APFloat(+0.0)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
737 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
738 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
739 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
740 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
743 // We don't support FMA.
744 setOperationAction(ISD::FMA, MVT::f64, Expand);
745 setOperationAction(ISD::FMA, MVT::f32, Expand);
747 // Long double always uses X87.
748 if (!TM.Options.UseSoftFloat) {
749 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
750 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
751 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
753 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
754 addLegalFPImmediate(TmpFlt); // FLD0
756 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
759 APFloat TmpFlt2(+1.0);
760 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
762 addLegalFPImmediate(TmpFlt2); // FLD1
763 TmpFlt2.changeSign();
764 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
767 if (!TM.Options.UnsafeFPMath) {
768 setOperationAction(ISD::FSIN , MVT::f80, Expand);
769 setOperationAction(ISD::FCOS , MVT::f80, Expand);
770 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
773 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
774 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
775 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
776 setOperationAction(ISD::FRINT, MVT::f80, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
778 setOperationAction(ISD::FMA, MVT::f80, Expand);
781 // Always use a library call for pow.
782 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
786 setOperationAction(ISD::FLOG, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
792 // First set operation action for all vector types to either promote
793 // (for widening) or expand (for scalarization). Then we will selectively
794 // turn on ones that can be effectively codegen'd.
795 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
796 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
797 MVT VT = (MVT::SimpleValueType)i;
798 setOperationAction(ISD::ADD , VT, Expand);
799 setOperationAction(ISD::SUB , VT, Expand);
800 setOperationAction(ISD::FADD, VT, Expand);
801 setOperationAction(ISD::FNEG, VT, Expand);
802 setOperationAction(ISD::FSUB, VT, Expand);
803 setOperationAction(ISD::MUL , VT, Expand);
804 setOperationAction(ISD::FMUL, VT, Expand);
805 setOperationAction(ISD::SDIV, VT, Expand);
806 setOperationAction(ISD::UDIV, VT, Expand);
807 setOperationAction(ISD::FDIV, VT, Expand);
808 setOperationAction(ISD::SREM, VT, Expand);
809 setOperationAction(ISD::UREM, VT, Expand);
810 setOperationAction(ISD::LOAD, VT, Expand);
811 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
814 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::FABS, VT, Expand);
817 setOperationAction(ISD::FSIN, VT, Expand);
818 setOperationAction(ISD::FSINCOS, VT, Expand);
819 setOperationAction(ISD::FCOS, VT, Expand);
820 setOperationAction(ISD::FSINCOS, VT, Expand);
821 setOperationAction(ISD::FREM, VT, Expand);
822 setOperationAction(ISD::FMA, VT, Expand);
823 setOperationAction(ISD::FPOWI, VT, Expand);
824 setOperationAction(ISD::FSQRT, VT, Expand);
825 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
826 setOperationAction(ISD::FFLOOR, VT, Expand);
827 setOperationAction(ISD::FCEIL, VT, Expand);
828 setOperationAction(ISD::FTRUNC, VT, Expand);
829 setOperationAction(ISD::FRINT, VT, Expand);
830 setOperationAction(ISD::FNEARBYINT, VT, Expand);
831 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::SDIVREM, VT, Expand);
834 setOperationAction(ISD::UDIVREM, VT, Expand);
835 setOperationAction(ISD::FPOW, VT, Expand);
836 setOperationAction(ISD::CTPOP, VT, Expand);
837 setOperationAction(ISD::CTTZ, VT, Expand);
838 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
839 setOperationAction(ISD::CTLZ, VT, Expand);
840 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
841 setOperationAction(ISD::SHL, VT, Expand);
842 setOperationAction(ISD::SRA, VT, Expand);
843 setOperationAction(ISD::SRL, VT, Expand);
844 setOperationAction(ISD::ROTL, VT, Expand);
845 setOperationAction(ISD::ROTR, VT, Expand);
846 setOperationAction(ISD::BSWAP, VT, Expand);
847 setOperationAction(ISD::SETCC, VT, Expand);
848 setOperationAction(ISD::FLOG, VT, Expand);
849 setOperationAction(ISD::FLOG2, VT, Expand);
850 setOperationAction(ISD::FLOG10, VT, Expand);
851 setOperationAction(ISD::FEXP, VT, Expand);
852 setOperationAction(ISD::FEXP2, VT, Expand);
853 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
854 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
855 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
858 setOperationAction(ISD::TRUNCATE, VT, Expand);
859 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
860 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
861 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
862 setOperationAction(ISD::VSELECT, VT, Expand);
863 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
864 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
865 setTruncStoreAction(VT,
866 (MVT::SimpleValueType)InnerVT, Expand);
867 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
872 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
873 // with -msoft-float, disable use of MMX as well.
874 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
875 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
876 // No operations on x86mmx supported, everything uses intrinsics.
879 // MMX-sized vectors (other than x86mmx) are expected to be expanded
880 // into smaller operations.
881 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
882 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
883 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
884 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
885 setOperationAction(ISD::AND, MVT::v8i8, Expand);
886 setOperationAction(ISD::AND, MVT::v4i16, Expand);
887 setOperationAction(ISD::AND, MVT::v2i32, Expand);
888 setOperationAction(ISD::AND, MVT::v1i64, Expand);
889 setOperationAction(ISD::OR, MVT::v8i8, Expand);
890 setOperationAction(ISD::OR, MVT::v4i16, Expand);
891 setOperationAction(ISD::OR, MVT::v2i32, Expand);
892 setOperationAction(ISD::OR, MVT::v1i64, Expand);
893 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
894 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
895 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
896 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
902 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
903 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
904 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
905 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
911 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
912 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
914 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
915 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
916 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
917 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
918 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
919 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
920 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
921 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
929 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
931 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
932 // registers cannot be used even for integer operations.
933 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
934 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
935 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
936 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
938 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
939 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
940 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
941 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
945 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
946 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
947 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
948 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
949 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
950 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
951 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
952 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
954 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
955 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
959 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
960 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
969 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
970 MVT VT = (MVT::SimpleValueType)i;
971 // Do not attempt to custom lower non-power-of-2 vectors
972 if (!isPowerOf2_32(VT.getVectorNumElements()))
974 // Do not attempt to custom lower non-128-bit vectors
975 if (!VT.is128BitVector())
977 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
978 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to promote non-128-bit vectors
999 if (!VT.is128BitVector())
1002 setOperationAction(ISD::AND, VT, Promote);
1003 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1004 setOperationAction(ISD::OR, VT, Promote);
1005 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1006 setOperationAction(ISD::XOR, VT, Promote);
1007 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1008 setOperationAction(ISD::LOAD, VT, Promote);
1009 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1010 setOperationAction(ISD::SELECT, VT, Promote);
1011 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1014 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1016 // Custom lower v2i64 and v2f64 selects.
1017 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1019 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1027 // As there is no 64-bit GPR available, we need build a special custom
1028 // sequence to convert from v2i32 to v2f32.
1029 if (!Subtarget->is64Bit())
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1035 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1038 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1039 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1047 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1061 // FIXME: Do we need to handle scalar-to-vector here?
1062 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1070 // i8 and i16 vectors are custom , because the source register and source
1071 // source memory operand types are not the same width. f32 vectors are
1072 // custom since the immediate controlling the insert encodes additional
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1084 // FIXME: these should be Legal but thats only for the case where
1085 // the index is constant. For now custom expand to deal with that.
1086 if (Subtarget->is64Bit()) {
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1088 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1092 if (Subtarget->hasSSE2()) {
1093 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1102 // In the customized shift lowering, the legal cases in AVX2 will be
1104 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1105 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1107 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1110 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1116 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1117 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1124 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1128 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1139 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1141 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1152 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1154 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1159 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1164 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1166 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1167 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1169 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1186 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1204 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1205 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1208 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1209 setOperationAction(ISD::FMA, MVT::f32, Legal);
1210 setOperationAction(ISD::FMA, MVT::f64, Legal);
1213 if (Subtarget->hasInt256()) {
1214 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1227 // Don't lower v32i8 because there is no 128-bit byte mul
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1231 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1234 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1235 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1236 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1241 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1243 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1245 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1246 // Don't lower v32i8 because there is no 128-bit byte mul
1249 // In the customized shift lowering, the legal cases in AVX2 will be
1251 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1255 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1257 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1259 // Custom lower several nodes for 256-bit types.
1260 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1261 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1262 MVT VT = (MVT::SimpleValueType)i;
1264 // Extract subvector is special because the value type
1265 // (result) is 128-bit but the source is 256-bit wide.
1266 if (VT.is128BitVector())
1267 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1269 // Do not attempt to custom lower other non-256-bit vectors
1270 if (!VT.is256BitVector())
1273 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1275 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1278 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1279 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1314 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1315 setOperationAction(ISD::XOR, MVT::i1, Legal);
1316 setOperationAction(ISD::OR, MVT::i1, Legal);
1317 setOperationAction(ISD::AND, MVT::i1, Legal);
1318 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1319 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1322 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1323 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1325 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1326 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1330 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1332 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1338 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1339 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1340 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1342 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1343 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1344 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1345 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1346 if (Subtarget->is64Bit()) {
1347 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1348 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1349 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1350 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1352 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1353 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1355 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1356 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1358 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1359 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1361 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1362 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1364 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1365 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1366 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1367 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1368 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1369 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1374 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1375 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1377 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1378 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1379 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1381 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1382 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1384 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1387 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1388 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1389 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1390 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1391 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1392 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1394 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1395 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1397 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1398 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1400 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1402 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1403 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1405 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1406 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1408 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1409 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1411 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1412 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1413 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1414 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1415 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1416 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1418 // Custom lower several nodes.
1419 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1420 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1421 MVT VT = (MVT::SimpleValueType)i;
1423 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1424 // Extract subvector is special because the value type
1425 // (result) is 256/128-bit but the source is 512-bit wide.
1426 if (VT.is128BitVector() || VT.is256BitVector())
1427 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1429 if (VT.getVectorElementType() == MVT::i1)
1430 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1432 // Do not attempt to custom lower other non-512-bit vectors
1433 if (!VT.is512BitVector())
1436 if ( EltSize >= 32) {
1437 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1438 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1439 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1440 setOperationAction(ISD::VSELECT, VT, Legal);
1441 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1442 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1443 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1446 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1447 MVT VT = (MVT::SimpleValueType)i;
1449 // Do not attempt to promote non-256-bit vectors
1450 if (!VT.is512BitVector())
1453 setOperationAction(ISD::SELECT, VT, Promote);
1454 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1458 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1459 // of this type with custom code.
1460 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1461 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1462 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1466 // We want to custom lower some of our intrinsics.
1467 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1468 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1469 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1471 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1472 // handle type legalization for these operations here.
1474 // FIXME: We really should do custom legalization for addition and
1475 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1476 // than generic legalization for 64-bit multiplication-with-overflow, though.
1477 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1478 // Add/Sub/Mul with overflow operations are custom lowered.
1480 setOperationAction(ISD::SADDO, VT, Custom);
1481 setOperationAction(ISD::UADDO, VT, Custom);
1482 setOperationAction(ISD::SSUBO, VT, Custom);
1483 setOperationAction(ISD::USUBO, VT, Custom);
1484 setOperationAction(ISD::SMULO, VT, Custom);
1485 setOperationAction(ISD::UMULO, VT, Custom);
1488 // There are no 8-bit 3-address imul/mul instructions
1489 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1490 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1492 if (!Subtarget->is64Bit()) {
1493 // These libcalls are not available in 32-bit.
1494 setLibcallName(RTLIB::SHL_I128, 0);
1495 setLibcallName(RTLIB::SRL_I128, 0);
1496 setLibcallName(RTLIB::SRA_I128, 0);
1499 // Combine sin / cos into one node or libcall if possible.
1500 if (Subtarget->hasSinCos()) {
1501 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1502 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1503 if (Subtarget->isTargetDarwin()) {
1504 // For MacOSX, we don't want to the normal expansion of a libcall to
1505 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1507 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1508 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1512 // We have target-specific dag combine patterns for the following nodes:
1513 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1514 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1515 setTargetDAGCombine(ISD::VSELECT);
1516 setTargetDAGCombine(ISD::SELECT);
1517 setTargetDAGCombine(ISD::SHL);
1518 setTargetDAGCombine(ISD::SRA);
1519 setTargetDAGCombine(ISD::SRL);
1520 setTargetDAGCombine(ISD::OR);
1521 setTargetDAGCombine(ISD::AND);
1522 setTargetDAGCombine(ISD::ADD);
1523 setTargetDAGCombine(ISD::FADD);
1524 setTargetDAGCombine(ISD::FSUB);
1525 setTargetDAGCombine(ISD::FMA);
1526 setTargetDAGCombine(ISD::SUB);
1527 setTargetDAGCombine(ISD::LOAD);
1528 setTargetDAGCombine(ISD::STORE);
1529 setTargetDAGCombine(ISD::ZERO_EXTEND);
1530 setTargetDAGCombine(ISD::ANY_EXTEND);
1531 setTargetDAGCombine(ISD::SIGN_EXTEND);
1532 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1533 setTargetDAGCombine(ISD::TRUNCATE);
1534 setTargetDAGCombine(ISD::SINT_TO_FP);
1535 setTargetDAGCombine(ISD::SETCC);
1536 if (Subtarget->is64Bit())
1537 setTargetDAGCombine(ISD::MUL);
1538 setTargetDAGCombine(ISD::XOR);
1540 computeRegisterProperties();
1542 // On Darwin, -Os means optimize for size without hurting performance,
1543 // do not reduce the limit.
1544 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1545 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1546 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1547 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1548 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1549 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1550 setPrefLoopAlignment(4); // 2^4 bytes.
1552 // Predictable cmov don't hurt on atom because it's in-order.
1553 PredictableSelectIsExpensive = !Subtarget->isAtom();
1555 setPrefFunctionAlignment(4); // 2^4 bytes.
1558 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1560 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1562 if (Subtarget->hasAVX512())
1563 switch(VT.getVectorNumElements()) {
1564 case 8: return MVT::v8i1;
1565 case 16: return MVT::v16i1;
1568 return VT.changeVectorElementTypeToInteger();
1571 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1572 /// the desired ByVal argument alignment.
1573 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1576 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1577 if (VTy->getBitWidth() == 128)
1579 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1580 unsigned EltAlign = 0;
1581 getMaxByValAlign(ATy->getElementType(), EltAlign);
1582 if (EltAlign > MaxAlign)
1583 MaxAlign = EltAlign;
1584 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1585 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1586 unsigned EltAlign = 0;
1587 getMaxByValAlign(STy->getElementType(i), EltAlign);
1588 if (EltAlign > MaxAlign)
1589 MaxAlign = EltAlign;
1596 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1597 /// function arguments in the caller parameter area. For X86, aggregates
1598 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1599 /// are at 4-byte boundaries.
1600 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1601 if (Subtarget->is64Bit()) {
1602 // Max of 8 and alignment of type.
1603 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1610 if (Subtarget->hasSSE1())
1611 getMaxByValAlign(Ty, Align);
1615 /// getOptimalMemOpType - Returns the target specific optimal type for load
1616 /// and store operations as a result of memset, memcpy, and memmove
1617 /// lowering. If DstAlign is zero that means it's safe to destination
1618 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1619 /// means there isn't a need to check it against alignment requirement,
1620 /// probably because the source does not need to be loaded. If 'IsMemset' is
1621 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1622 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1623 /// source is constant so it does not need to be loaded.
1624 /// It returns EVT::Other if the type should be determined using generic
1625 /// target-independent logic.
1627 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1628 unsigned DstAlign, unsigned SrcAlign,
1629 bool IsMemset, bool ZeroMemset,
1631 MachineFunction &MF) const {
1632 const Function *F = MF.getFunction();
1633 if ((!IsMemset || ZeroMemset) &&
1634 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1635 Attribute::NoImplicitFloat)) {
1637 (Subtarget->isUnalignedMemAccessFast() ||
1638 ((DstAlign == 0 || DstAlign >= 16) &&
1639 (SrcAlign == 0 || SrcAlign >= 16)))) {
1641 if (Subtarget->hasInt256())
1643 if (Subtarget->hasFp256())
1646 if (Subtarget->hasSSE2())
1648 if (Subtarget->hasSSE1())
1650 } else if (!MemcpyStrSrc && Size >= 8 &&
1651 !Subtarget->is64Bit() &&
1652 Subtarget->hasSSE2()) {
1653 // Do not use f64 to lower memcpy if source is string constant. It's
1654 // better to use i32 to avoid the loads.
1658 if (Subtarget->is64Bit() && Size >= 8)
1663 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1665 return X86ScalarSSEf32;
1666 else if (VT == MVT::f64)
1667 return X86ScalarSSEf64;
1672 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1674 *Fast = Subtarget->isUnalignedMemAccessFast();
1678 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1679 /// current function. The returned value is a member of the
1680 /// MachineJumpTableInfo::JTEntryKind enum.
1681 unsigned X86TargetLowering::getJumpTableEncoding() const {
1682 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1684 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1685 Subtarget->isPICStyleGOT())
1686 return MachineJumpTableInfo::EK_Custom32;
1688 // Otherwise, use the normal jump table encoding heuristics.
1689 return TargetLowering::getJumpTableEncoding();
1693 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1694 const MachineBasicBlock *MBB,
1695 unsigned uid,MCContext &Ctx) const{
1696 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1697 Subtarget->isPICStyleGOT());
1698 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1700 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1701 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1704 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1706 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1707 SelectionDAG &DAG) const {
1708 if (!Subtarget->is64Bit())
1709 // This doesn't have SDLoc associated with it, but is not really the
1710 // same as a Register.
1711 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1715 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1716 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1718 const MCExpr *X86TargetLowering::
1719 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1720 MCContext &Ctx) const {
1721 // X86-64 uses RIP relative addressing based on the jump table label.
1722 if (Subtarget->isPICStyleRIPRel())
1723 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1725 // Otherwise, the reference is relative to the PIC base.
1726 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1729 // FIXME: Why this routine is here? Move to RegInfo!
1730 std::pair<const TargetRegisterClass*, uint8_t>
1731 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1732 const TargetRegisterClass *RRC = 0;
1734 switch (VT.SimpleTy) {
1736 return TargetLowering::findRepresentativeClass(VT);
1737 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1738 RRC = Subtarget->is64Bit() ?
1739 (const TargetRegisterClass*)&X86::GR64RegClass :
1740 (const TargetRegisterClass*)&X86::GR32RegClass;
1743 RRC = &X86::VR64RegClass;
1745 case MVT::f32: case MVT::f64:
1746 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1747 case MVT::v4f32: case MVT::v2f64:
1748 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1750 RRC = &X86::VR128RegClass;
1753 return std::make_pair(RRC, Cost);
1756 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1757 unsigned &Offset) const {
1758 if (!Subtarget->isTargetLinux())
1761 if (Subtarget->is64Bit()) {
1762 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1764 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1776 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1777 unsigned DestAS) const {
1778 assert(SrcAS != DestAS && "Expected different address spaces!");
1780 return SrcAS < 256 && DestAS < 256;
1783 //===----------------------------------------------------------------------===//
1784 // Return Value Calling Convention Implementation
1785 //===----------------------------------------------------------------------===//
1787 #include "X86GenCallingConv.inc"
1790 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1791 MachineFunction &MF, bool isVarArg,
1792 const SmallVectorImpl<ISD::OutputArg> &Outs,
1793 LLVMContext &Context) const {
1794 SmallVector<CCValAssign, 16> RVLocs;
1795 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1797 return CCInfo.CheckReturn(Outs, RetCC_X86);
1800 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1801 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1806 X86TargetLowering::LowerReturn(SDValue Chain,
1807 CallingConv::ID CallConv, bool isVarArg,
1808 const SmallVectorImpl<ISD::OutputArg> &Outs,
1809 const SmallVectorImpl<SDValue> &OutVals,
1810 SDLoc dl, SelectionDAG &DAG) const {
1811 MachineFunction &MF = DAG.getMachineFunction();
1812 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1814 SmallVector<CCValAssign, 16> RVLocs;
1815 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1816 RVLocs, *DAG.getContext());
1817 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1820 SmallVector<SDValue, 6> RetOps;
1821 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1822 // Operand #1 = Bytes To Pop
1823 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1826 // Copy the result values into the output registers.
1827 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1828 CCValAssign &VA = RVLocs[i];
1829 assert(VA.isRegLoc() && "Can only return in registers!");
1830 SDValue ValToCopy = OutVals[i];
1831 EVT ValVT = ValToCopy.getValueType();
1833 // Promote values to the appropriate types
1834 if (VA.getLocInfo() == CCValAssign::SExt)
1835 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1836 else if (VA.getLocInfo() == CCValAssign::ZExt)
1837 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1838 else if (VA.getLocInfo() == CCValAssign::AExt)
1839 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1840 else if (VA.getLocInfo() == CCValAssign::BCvt)
1841 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1843 // If this is x86-64, and we disabled SSE, we can't return FP values,
1844 // or SSE or MMX vectors.
1845 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1846 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1847 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1848 report_fatal_error("SSE register return with SSE disabled");
1850 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1851 // llvm-gcc has never done it right and no one has noticed, so this
1852 // should be OK for now.
1853 if (ValVT == MVT::f64 &&
1854 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1855 report_fatal_error("SSE2 register return with SSE2 disabled");
1857 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1858 // the RET instruction and handled by the FP Stackifier.
1859 if (VA.getLocReg() == X86::ST0 ||
1860 VA.getLocReg() == X86::ST1) {
1861 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1862 // change the value to the FP stack register class.
1863 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1864 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1865 RetOps.push_back(ValToCopy);
1866 // Don't emit a copytoreg.
1870 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1871 // which is returned in RAX / RDX.
1872 if (Subtarget->is64Bit()) {
1873 if (ValVT == MVT::x86mmx) {
1874 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1875 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1876 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1878 // If we don't have SSE2 available, convert to v4f32 so the generated
1879 // register is legal.
1880 if (!Subtarget->hasSSE2())
1881 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1886 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1887 Flag = Chain.getValue(1);
1888 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1891 // The x86-64 ABIs require that for returning structs by value we copy
1892 // the sret argument into %rax/%eax (depending on ABI) for the return.
1893 // Win32 requires us to put the sret argument to %eax as well.
1894 // We saved the argument into a virtual register in the entry block,
1895 // so now we copy the value out and into %rax/%eax.
1896 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1897 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1898 MachineFunction &MF = DAG.getMachineFunction();
1899 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1900 unsigned Reg = FuncInfo->getSRetReturnReg();
1902 "SRetReturnReg should have been set in LowerFormalArguments().");
1903 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1906 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1907 X86::RAX : X86::EAX;
1908 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1909 Flag = Chain.getValue(1);
1911 // RAX/EAX now acts like a return value.
1912 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1915 RetOps[0] = Chain; // Update chain.
1917 // Add the flag if we have it.
1919 RetOps.push_back(Flag);
1921 return DAG.getNode(X86ISD::RET_FLAG, dl,
1922 MVT::Other, &RetOps[0], RetOps.size());
1925 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1926 if (N->getNumValues() != 1)
1928 if (!N->hasNUsesOfValue(1, 0))
1931 SDValue TCChain = Chain;
1932 SDNode *Copy = *N->use_begin();
1933 if (Copy->getOpcode() == ISD::CopyToReg) {
1934 // If the copy has a glue operand, we conservatively assume it isn't safe to
1935 // perform a tail call.
1936 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1938 TCChain = Copy->getOperand(0);
1939 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1942 bool HasRet = false;
1943 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1945 if (UI->getOpcode() != X86ISD::RET_FLAG)
1958 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1959 ISD::NodeType ExtendKind) const {
1961 // TODO: Is this also valid on 32-bit?
1962 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1963 ReturnMVT = MVT::i8;
1965 ReturnMVT = MVT::i32;
1967 MVT MinVT = getRegisterType(ReturnMVT);
1968 return VT.bitsLT(MinVT) ? MinVT : VT;
1971 /// LowerCallResult - Lower the result values of a call into the
1972 /// appropriate copies out of appropriate physical registers.
1975 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1976 CallingConv::ID CallConv, bool isVarArg,
1977 const SmallVectorImpl<ISD::InputArg> &Ins,
1978 SDLoc dl, SelectionDAG &DAG,
1979 SmallVectorImpl<SDValue> &InVals) const {
1981 // Assign locations to each value returned by this call.
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 bool Is64Bit = Subtarget->is64Bit();
1984 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1985 getTargetMachine(), RVLocs, *DAG.getContext());
1986 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1988 // Copy all of the result registers out of their specified physreg.
1989 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1990 CCValAssign &VA = RVLocs[i];
1991 EVT CopyVT = VA.getValVT();
1993 // If this is x86-64, and we disabled SSE, we can't return FP values
1994 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1995 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1996 report_fatal_error("SSE register return with SSE disabled");
2001 // If this is a call to a function that returns an fp value on the floating
2002 // point stack, we must guarantee the value is popped from the stack, so
2003 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2004 // if the return value is not used. We use the FpPOP_RETVAL instruction
2006 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2007 // If we prefer to use the value in xmm registers, copy it out as f80 and
2008 // use a truncate to move it from fp stack reg to xmm reg.
2009 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2010 SDValue Ops[] = { Chain, InFlag };
2011 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2012 MVT::Other, MVT::Glue, Ops), 1);
2013 Val = Chain.getValue(0);
2015 // Round the f80 to the right size, which also moves it to the appropriate
2017 if (CopyVT != VA.getValVT())
2018 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2019 // This truncation won't change the value.
2020 DAG.getIntPtrConstant(1));
2022 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2023 CopyVT, InFlag).getValue(1);
2024 Val = Chain.getValue(0);
2026 InFlag = Chain.getValue(2);
2027 InVals.push_back(Val);
2033 //===----------------------------------------------------------------------===//
2034 // C & StdCall & Fast Calling Convention implementation
2035 //===----------------------------------------------------------------------===//
2036 // StdCall calling convention seems to be standard for many Windows' API
2037 // routines and around. It differs from C calling convention just a little:
2038 // callee should clean up the stack, not caller. Symbols should be also
2039 // decorated in some fancy way :) It doesn't support any vector arguments.
2040 // For info on fast calling convention see Fast Calling Convention (tail call)
2041 // implementation LowerX86_32FastCCCallTo.
2043 /// CallIsStructReturn - Determines whether a call uses struct return
2045 enum StructReturnType {
2050 static StructReturnType
2051 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2053 return NotStructReturn;
2055 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2056 if (!Flags.isSRet())
2057 return NotStructReturn;
2058 if (Flags.isInReg())
2059 return RegStructReturn;
2060 return StackStructReturn;
2063 /// ArgsAreStructReturn - Determines whether a function uses struct
2064 /// return semantics.
2065 static StructReturnType
2066 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2068 return NotStructReturn;
2070 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2071 if (!Flags.isSRet())
2072 return NotStructReturn;
2073 if (Flags.isInReg())
2074 return RegStructReturn;
2075 return StackStructReturn;
2078 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2079 /// by "Src" to address "Dst" with size and alignment information specified by
2080 /// the specific parameter attribute. The copy will be passed as a byval
2081 /// function parameter.
2083 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2084 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2086 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2088 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2089 /*isVolatile*/false, /*AlwaysInline=*/true,
2090 MachinePointerInfo(), MachinePointerInfo());
2093 /// IsTailCallConvention - Return true if the calling convention is one that
2094 /// supports tail call optimization.
2095 static bool IsTailCallConvention(CallingConv::ID CC) {
2096 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2097 CC == CallingConv::HiPE);
2100 /// \brief Return true if the calling convention is a C calling convention.
2101 static bool IsCCallConvention(CallingConv::ID CC) {
2102 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2103 CC == CallingConv::X86_64_SysV);
2106 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2107 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2111 CallingConv::ID CalleeCC = CS.getCallingConv();
2112 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2118 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2119 /// a tailcall target by changing its ABI.
2120 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2121 bool GuaranteedTailCallOpt) {
2122 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2126 X86TargetLowering::LowerMemArgument(SDValue Chain,
2127 CallingConv::ID CallConv,
2128 const SmallVectorImpl<ISD::InputArg> &Ins,
2129 SDLoc dl, SelectionDAG &DAG,
2130 const CCValAssign &VA,
2131 MachineFrameInfo *MFI,
2133 // Create the nodes corresponding to a load from this parameter slot.
2134 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2135 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2136 getTargetMachine().Options.GuaranteedTailCallOpt);
2137 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2140 // If value is passed by pointer we have address passed instead of the value
2142 if (VA.getLocInfo() == CCValAssign::Indirect)
2143 ValVT = VA.getLocVT();
2145 ValVT = VA.getValVT();
2147 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2148 // changed with more analysis.
2149 // In case of tail call optimization mark all arguments mutable. Since they
2150 // could be overwritten by lowering of arguments in case of a tail call.
2151 if (Flags.isByVal()) {
2152 unsigned Bytes = Flags.getByValSize();
2153 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2154 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2155 return DAG.getFrameIndex(FI, getPointerTy());
2157 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2158 VA.getLocMemOffset(), isImmutable);
2159 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2160 return DAG.getLoad(ValVT, dl, Chain, FIN,
2161 MachinePointerInfo::getFixedStack(FI),
2162 false, false, false, 0);
2167 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2168 CallingConv::ID CallConv,
2170 const SmallVectorImpl<ISD::InputArg> &Ins,
2173 SmallVectorImpl<SDValue> &InVals)
2175 MachineFunction &MF = DAG.getMachineFunction();
2176 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2178 const Function* Fn = MF.getFunction();
2179 if (Fn->hasExternalLinkage() &&
2180 Subtarget->isTargetCygMing() &&
2181 Fn->getName() == "main")
2182 FuncInfo->setForceFramePointer(true);
2184 MachineFrameInfo *MFI = MF.getFrameInfo();
2185 bool Is64Bit = Subtarget->is64Bit();
2186 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2188 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2189 "Var args not supported with calling convention fastcc, ghc or hipe");
2191 // Assign locations to all of the incoming arguments.
2192 SmallVector<CCValAssign, 16> ArgLocs;
2193 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2194 ArgLocs, *DAG.getContext());
2196 // Allocate shadow area for Win64
2198 CCInfo.AllocateStack(32, 8);
2200 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2202 unsigned LastVal = ~0U;
2204 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2205 CCValAssign &VA = ArgLocs[i];
2206 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2208 assert(VA.getValNo() != LastVal &&
2209 "Don't support value assigned to multiple locs yet");
2211 LastVal = VA.getValNo();
2213 if (VA.isRegLoc()) {
2214 EVT RegVT = VA.getLocVT();
2215 const TargetRegisterClass *RC;
2216 if (RegVT == MVT::i32)
2217 RC = &X86::GR32RegClass;
2218 else if (Is64Bit && RegVT == MVT::i64)
2219 RC = &X86::GR64RegClass;
2220 else if (RegVT == MVT::f32)
2221 RC = &X86::FR32RegClass;
2222 else if (RegVT == MVT::f64)
2223 RC = &X86::FR64RegClass;
2224 else if (RegVT.is512BitVector())
2225 RC = &X86::VR512RegClass;
2226 else if (RegVT.is256BitVector())
2227 RC = &X86::VR256RegClass;
2228 else if (RegVT.is128BitVector())
2229 RC = &X86::VR128RegClass;
2230 else if (RegVT == MVT::x86mmx)
2231 RC = &X86::VR64RegClass;
2232 else if (RegVT == MVT::i1)
2233 RC = &X86::VK1RegClass;
2234 else if (RegVT == MVT::v8i1)
2235 RC = &X86::VK8RegClass;
2236 else if (RegVT == MVT::v16i1)
2237 RC = &X86::VK16RegClass;
2239 llvm_unreachable("Unknown argument type!");
2241 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2242 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2244 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2245 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2247 if (VA.getLocInfo() == CCValAssign::SExt)
2248 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2249 DAG.getValueType(VA.getValVT()));
2250 else if (VA.getLocInfo() == CCValAssign::ZExt)
2251 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2252 DAG.getValueType(VA.getValVT()));
2253 else if (VA.getLocInfo() == CCValAssign::BCvt)
2254 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2256 if (VA.isExtInLoc()) {
2257 // Handle MMX values passed in XMM regs.
2258 if (RegVT.isVector())
2259 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2261 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2264 assert(VA.isMemLoc());
2265 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2268 // If value is passed via pointer - do a load.
2269 if (VA.getLocInfo() == CCValAssign::Indirect)
2270 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2271 MachinePointerInfo(), false, false, false, 0);
2273 InVals.push_back(ArgValue);
2276 // The x86-64 ABIs require that for returning structs by value we copy
2277 // the sret argument into %rax/%eax (depending on ABI) for the return.
2278 // Win32 requires us to put the sret argument to %eax as well.
2279 // Save the argument into a virtual register so that we can access it
2280 // from the return points.
2281 if (MF.getFunction()->hasStructRetAttr() &&
2282 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2283 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2284 unsigned Reg = FuncInfo->getSRetReturnReg();
2286 MVT PtrTy = getPointerTy();
2287 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2288 FuncInfo->setSRetReturnReg(Reg);
2290 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2291 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2294 unsigned StackSize = CCInfo.getNextStackOffset();
2295 // Align stack specially for tail calls.
2296 if (FuncIsMadeTailCallSafe(CallConv,
2297 MF.getTarget().Options.GuaranteedTailCallOpt))
2298 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2300 // If the function takes variable number of arguments, make a frame index for
2301 // the start of the first vararg value... for expansion of llvm.va_start.
2303 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2304 CallConv != CallingConv::X86_ThisCall)) {
2305 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2308 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2310 // FIXME: We should really autogenerate these arrays
2311 static const uint16_t GPR64ArgRegsWin64[] = {
2312 X86::RCX, X86::RDX, X86::R8, X86::R9
2314 static const uint16_t GPR64ArgRegs64Bit[] = {
2315 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2317 static const uint16_t XMMArgRegs64Bit[] = {
2318 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2319 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2321 const uint16_t *GPR64ArgRegs;
2322 unsigned NumXMMRegs = 0;
2325 // The XMM registers which might contain var arg parameters are shadowed
2326 // in their paired GPR. So we only need to save the GPR to their home
2328 TotalNumIntRegs = 4;
2329 GPR64ArgRegs = GPR64ArgRegsWin64;
2331 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2332 GPR64ArgRegs = GPR64ArgRegs64Bit;
2334 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2337 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2340 bool NoImplicitFloatOps = Fn->getAttributes().
2341 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2342 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2343 "SSE register cannot be used when SSE is disabled!");
2344 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2345 NoImplicitFloatOps) &&
2346 "SSE register cannot be used when SSE is disabled!");
2347 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2348 !Subtarget->hasSSE1())
2349 // Kernel mode asks for SSE to be disabled, so don't push them
2351 TotalNumXMMRegs = 0;
2354 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2355 // Get to the caller-allocated home save location. Add 8 to account
2356 // for the return address.
2357 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2358 FuncInfo->setRegSaveFrameIndex(
2359 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2360 // Fixup to set vararg frame on shadow area (4 x i64).
2362 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2364 // For X86-64, if there are vararg parameters that are passed via
2365 // registers, then we must store them to their spots on the stack so
2366 // they may be loaded by deferencing the result of va_next.
2367 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2368 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2369 FuncInfo->setRegSaveFrameIndex(
2370 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2374 // Store the integer parameter registers.
2375 SmallVector<SDValue, 8> MemOps;
2376 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2378 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2379 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2380 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2381 DAG.getIntPtrConstant(Offset));
2382 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2383 &X86::GR64RegClass);
2384 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2386 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2387 MachinePointerInfo::getFixedStack(
2388 FuncInfo->getRegSaveFrameIndex(), Offset),
2390 MemOps.push_back(Store);
2394 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2395 // Now store the XMM (fp + vector) parameter registers.
2396 SmallVector<SDValue, 11> SaveXMMOps;
2397 SaveXMMOps.push_back(Chain);
2399 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2400 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2401 SaveXMMOps.push_back(ALVal);
2403 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2404 FuncInfo->getRegSaveFrameIndex()));
2405 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2406 FuncInfo->getVarArgsFPOffset()));
2408 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2409 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2410 &X86::VR128RegClass);
2411 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2412 SaveXMMOps.push_back(Val);
2414 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2416 &SaveXMMOps[0], SaveXMMOps.size()));
2419 if (!MemOps.empty())
2420 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2421 &MemOps[0], MemOps.size());
2425 // Some CCs need callee pop.
2426 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2427 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2428 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2430 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2431 // If this is an sret function, the return should pop the hidden pointer.
2432 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2433 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2434 argsAreStructReturn(Ins) == StackStructReturn)
2435 FuncInfo->setBytesToPopOnReturn(4);
2439 // RegSaveFrameIndex is X86-64 only.
2440 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2441 if (CallConv == CallingConv::X86_FastCall ||
2442 CallConv == CallingConv::X86_ThisCall)
2443 // fastcc functions can't have varargs.
2444 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2447 FuncInfo->setArgumentStackSize(StackSize);
2453 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2454 SDValue StackPtr, SDValue Arg,
2455 SDLoc dl, SelectionDAG &DAG,
2456 const CCValAssign &VA,
2457 ISD::ArgFlagsTy Flags) const {
2458 unsigned LocMemOffset = VA.getLocMemOffset();
2459 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2460 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2461 if (Flags.isByVal())
2462 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2464 return DAG.getStore(Chain, dl, Arg, PtrOff,
2465 MachinePointerInfo::getStack(LocMemOffset),
2469 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2470 /// optimization is performed and it is required.
2472 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2473 SDValue &OutRetAddr, SDValue Chain,
2474 bool IsTailCall, bool Is64Bit,
2475 int FPDiff, SDLoc dl) const {
2476 // Adjust the Return address stack slot.
2477 EVT VT = getPointerTy();
2478 OutRetAddr = getReturnAddressFrameIndex(DAG);
2480 // Load the "old" Return address.
2481 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2482 false, false, false, 0);
2483 return SDValue(OutRetAddr.getNode(), 1);
2486 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2487 /// optimization is performed and it is required (FPDiff!=0).
2489 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2490 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2491 unsigned SlotSize, int FPDiff, SDLoc dl) {
2492 // Store the return address to the appropriate stack slot.
2493 if (!FPDiff) return Chain;
2494 // Calculate the new stack slot for the return address.
2495 int NewReturnAddrFI =
2496 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2498 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2499 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2500 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2506 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2507 SmallVectorImpl<SDValue> &InVals) const {
2508 SelectionDAG &DAG = CLI.DAG;
2510 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2511 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2512 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2513 SDValue Chain = CLI.Chain;
2514 SDValue Callee = CLI.Callee;
2515 CallingConv::ID CallConv = CLI.CallConv;
2516 bool &isTailCall = CLI.IsTailCall;
2517 bool isVarArg = CLI.IsVarArg;
2519 MachineFunction &MF = DAG.getMachineFunction();
2520 bool Is64Bit = Subtarget->is64Bit();
2521 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2522 StructReturnType SR = callIsStructReturn(Outs);
2523 bool IsSibcall = false;
2525 if (MF.getTarget().Options.DisableTailCalls)
2529 // Check if it's really possible to do a tail call.
2530 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2531 isVarArg, SR != NotStructReturn,
2532 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2533 Outs, OutVals, Ins, DAG);
2535 // Sibcalls are automatically detected tailcalls which do not require
2537 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2544 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2545 "Var args not supported with calling convention fastcc, ghc or hipe");
2547 // Analyze operands of the call, assigning locations to each operand.
2548 SmallVector<CCValAssign, 16> ArgLocs;
2549 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2550 ArgLocs, *DAG.getContext());
2552 // Allocate shadow area for Win64
2554 CCInfo.AllocateStack(32, 8);
2556 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2558 // Get a count of how many bytes are to be pushed on the stack.
2559 unsigned NumBytes = CCInfo.getNextStackOffset();
2561 // This is a sibcall. The memory operands are available in caller's
2562 // own caller's stack.
2564 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2565 IsTailCallConvention(CallConv))
2566 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2569 if (isTailCall && !IsSibcall) {
2570 // Lower arguments at fp - stackoffset + fpdiff.
2571 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2572 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2574 FPDiff = NumBytesCallerPushed - NumBytes;
2576 // Set the delta of movement of the returnaddr stackslot.
2577 // But only set if delta is greater than previous delta.
2578 if (FPDiff < X86Info->getTCReturnAddrDelta())
2579 X86Info->setTCReturnAddrDelta(FPDiff);
2583 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2586 SDValue RetAddrFrIdx;
2587 // Load return address for tail calls.
2588 if (isTailCall && FPDiff)
2589 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2590 Is64Bit, FPDiff, dl);
2592 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2593 SmallVector<SDValue, 8> MemOpChains;
2596 // Walk the register/memloc assignments, inserting copies/loads. In the case
2597 // of tail call optimization arguments are handle later.
2598 const X86RegisterInfo *RegInfo =
2599 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2600 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2601 CCValAssign &VA = ArgLocs[i];
2602 EVT RegVT = VA.getLocVT();
2603 SDValue Arg = OutVals[i];
2604 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2605 bool isByVal = Flags.isByVal();
2607 // Promote the value if needed.
2608 switch (VA.getLocInfo()) {
2609 default: llvm_unreachable("Unknown loc info!");
2610 case CCValAssign::Full: break;
2611 case CCValAssign::SExt:
2612 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2614 case CCValAssign::ZExt:
2615 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2617 case CCValAssign::AExt:
2618 if (RegVT.is128BitVector()) {
2619 // Special case: passing MMX values in XMM registers.
2620 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2621 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2622 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2624 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2626 case CCValAssign::BCvt:
2627 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2629 case CCValAssign::Indirect: {
2630 // Store the argument.
2631 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2632 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2633 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2634 MachinePointerInfo::getFixedStack(FI),
2641 if (VA.isRegLoc()) {
2642 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2643 if (isVarArg && IsWin64) {
2644 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2645 // shadow reg if callee is a varargs function.
2646 unsigned ShadowReg = 0;
2647 switch (VA.getLocReg()) {
2648 case X86::XMM0: ShadowReg = X86::RCX; break;
2649 case X86::XMM1: ShadowReg = X86::RDX; break;
2650 case X86::XMM2: ShadowReg = X86::R8; break;
2651 case X86::XMM3: ShadowReg = X86::R9; break;
2654 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2656 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2657 assert(VA.isMemLoc());
2658 if (StackPtr.getNode() == 0)
2659 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2661 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2662 dl, DAG, VA, Flags));
2666 if (!MemOpChains.empty())
2667 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2668 &MemOpChains[0], MemOpChains.size());
2670 if (Subtarget->isPICStyleGOT()) {
2671 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2674 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2675 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2677 // If we are tail calling and generating PIC/GOT style code load the
2678 // address of the callee into ECX. The value in ecx is used as target of
2679 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2680 // for tail calls on PIC/GOT architectures. Normally we would just put the
2681 // address of GOT into ebx and then call target@PLT. But for tail calls
2682 // ebx would be restored (since ebx is callee saved) before jumping to the
2685 // Note: The actual moving to ECX is done further down.
2686 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2687 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2688 !G->getGlobal()->hasProtectedVisibility())
2689 Callee = LowerGlobalAddress(Callee, DAG);
2690 else if (isa<ExternalSymbolSDNode>(Callee))
2691 Callee = LowerExternalSymbol(Callee, DAG);
2695 if (Is64Bit && isVarArg && !IsWin64) {
2696 // From AMD64 ABI document:
2697 // For calls that may call functions that use varargs or stdargs
2698 // (prototype-less calls or calls to functions containing ellipsis (...) in
2699 // the declaration) %al is used as hidden argument to specify the number
2700 // of SSE registers used. The contents of %al do not need to match exactly
2701 // the number of registers, but must be an ubound on the number of SSE
2702 // registers used and is in the range 0 - 8 inclusive.
2704 // Count the number of XMM registers allocated.
2705 static const uint16_t XMMArgRegs[] = {
2706 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2707 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2709 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2710 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2711 && "SSE registers cannot be used when SSE is disabled");
2713 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2714 DAG.getConstant(NumXMMRegs, MVT::i8)));
2717 // For tail calls lower the arguments to the 'real' stack slot.
2719 // Force all the incoming stack arguments to be loaded from the stack
2720 // before any new outgoing arguments are stored to the stack, because the
2721 // outgoing stack slots may alias the incoming argument stack slots, and
2722 // the alias isn't otherwise explicit. This is slightly more conservative
2723 // than necessary, because it means that each store effectively depends
2724 // on every argument instead of just those arguments it would clobber.
2725 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2727 SmallVector<SDValue, 8> MemOpChains2;
2730 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2731 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2732 CCValAssign &VA = ArgLocs[i];
2735 assert(VA.isMemLoc());
2736 SDValue Arg = OutVals[i];
2737 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2738 // Create frame index.
2739 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2740 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2741 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2742 FIN = DAG.getFrameIndex(FI, getPointerTy());
2744 if (Flags.isByVal()) {
2745 // Copy relative to framepointer.
2746 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2747 if (StackPtr.getNode() == 0)
2748 StackPtr = DAG.getCopyFromReg(Chain, dl,
2749 RegInfo->getStackRegister(),
2751 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2753 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2757 // Store relative to framepointer.
2758 MemOpChains2.push_back(
2759 DAG.getStore(ArgChain, dl, Arg, FIN,
2760 MachinePointerInfo::getFixedStack(FI),
2766 if (!MemOpChains2.empty())
2767 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2768 &MemOpChains2[0], MemOpChains2.size());
2770 // Store the return address to the appropriate stack slot.
2771 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2772 getPointerTy(), RegInfo->getSlotSize(),
2776 // Build a sequence of copy-to-reg nodes chained together with token chain
2777 // and flag operands which copy the outgoing args into registers.
2779 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2780 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2781 RegsToPass[i].second, InFlag);
2782 InFlag = Chain.getValue(1);
2785 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2786 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2787 // In the 64-bit large code model, we have to make all calls
2788 // through a register, since the call instruction's 32-bit
2789 // pc-relative offset may not be large enough to hold the whole
2791 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2792 // If the callee is a GlobalAddress node (quite common, every direct call
2793 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2796 // We should use extra load for direct calls to dllimported functions in
2798 const GlobalValue *GV = G->getGlobal();
2799 if (!GV->hasDLLImportLinkage()) {
2800 unsigned char OpFlags = 0;
2801 bool ExtraLoad = false;
2802 unsigned WrapperKind = ISD::DELETED_NODE;
2804 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2805 // external symbols most go through the PLT in PIC mode. If the symbol
2806 // has hidden or protected visibility, or if it is static or local, then
2807 // we don't need to use the PLT - we can directly call it.
2808 if (Subtarget->isTargetELF() &&
2809 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2810 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2811 OpFlags = X86II::MO_PLT;
2812 } else if (Subtarget->isPICStyleStubAny() &&
2813 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2814 (!Subtarget->getTargetTriple().isMacOSX() ||
2815 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2816 // PC-relative references to external symbols should go through $stub,
2817 // unless we're building with the leopard linker or later, which
2818 // automatically synthesizes these stubs.
2819 OpFlags = X86II::MO_DARWIN_STUB;
2820 } else if (Subtarget->isPICStyleRIPRel() &&
2821 isa<Function>(GV) &&
2822 cast<Function>(GV)->getAttributes().
2823 hasAttribute(AttributeSet::FunctionIndex,
2824 Attribute::NonLazyBind)) {
2825 // If the function is marked as non-lazy, generate an indirect call
2826 // which loads from the GOT directly. This avoids runtime overhead
2827 // at the cost of eager binding (and one extra byte of encoding).
2828 OpFlags = X86II::MO_GOTPCREL;
2829 WrapperKind = X86ISD::WrapperRIP;
2833 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2834 G->getOffset(), OpFlags);
2836 // Add a wrapper if needed.
2837 if (WrapperKind != ISD::DELETED_NODE)
2838 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2839 // Add extra indirection if needed.
2841 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2842 MachinePointerInfo::getGOT(),
2843 false, false, false, 0);
2845 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2846 unsigned char OpFlags = 0;
2848 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2849 // external symbols should go through the PLT.
2850 if (Subtarget->isTargetELF() &&
2851 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2852 OpFlags = X86II::MO_PLT;
2853 } else if (Subtarget->isPICStyleStubAny() &&
2854 (!Subtarget->getTargetTriple().isMacOSX() ||
2855 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2856 // PC-relative references to external symbols should go through $stub,
2857 // unless we're building with the leopard linker or later, which
2858 // automatically synthesizes these stubs.
2859 OpFlags = X86II::MO_DARWIN_STUB;
2862 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2866 // Returns a chain & a flag for retval copy to use.
2867 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2868 SmallVector<SDValue, 8> Ops;
2870 if (!IsSibcall && isTailCall) {
2871 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2872 DAG.getIntPtrConstant(0, true), InFlag, dl);
2873 InFlag = Chain.getValue(1);
2876 Ops.push_back(Chain);
2877 Ops.push_back(Callee);
2880 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2882 // Add argument registers to the end of the list so that they are known live
2884 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2885 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2886 RegsToPass[i].second.getValueType()));
2888 // Add a register mask operand representing the call-preserved registers.
2889 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2890 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2891 assert(Mask && "Missing call preserved mask for calling convention");
2892 Ops.push_back(DAG.getRegisterMask(Mask));
2894 if (InFlag.getNode())
2895 Ops.push_back(InFlag);
2899 //// If this is the first return lowered for this function, add the regs
2900 //// to the liveout set for the function.
2901 // This isn't right, although it's probably harmless on x86; liveouts
2902 // should be computed from returns not tail calls. Consider a void
2903 // function making a tail call to a function returning int.
2904 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2907 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2908 InFlag = Chain.getValue(1);
2910 // Create the CALLSEQ_END node.
2911 unsigned NumBytesForCalleeToPush;
2912 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2913 getTargetMachine().Options.GuaranteedTailCallOpt))
2914 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2915 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2916 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2917 SR == StackStructReturn)
2918 // If this is a call to a struct-return function, the callee
2919 // pops the hidden struct pointer, so we have to push it back.
2920 // This is common for Darwin/X86, Linux & Mingw32 targets.
2921 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2922 NumBytesForCalleeToPush = 4;
2924 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2926 // Returns a flag for retval copy to use.
2928 Chain = DAG.getCALLSEQ_END(Chain,
2929 DAG.getIntPtrConstant(NumBytes, true),
2930 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2933 InFlag = Chain.getValue(1);
2936 // Handle result values, copying them out of physregs into vregs that we
2938 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2939 Ins, dl, DAG, InVals);
2942 //===----------------------------------------------------------------------===//
2943 // Fast Calling Convention (tail call) implementation
2944 //===----------------------------------------------------------------------===//
2946 // Like std call, callee cleans arguments, convention except that ECX is
2947 // reserved for storing the tail called function address. Only 2 registers are
2948 // free for argument passing (inreg). Tail call optimization is performed
2950 // * tailcallopt is enabled
2951 // * caller/callee are fastcc
2952 // On X86_64 architecture with GOT-style position independent code only local
2953 // (within module) calls are supported at the moment.
2954 // To keep the stack aligned according to platform abi the function
2955 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2956 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2957 // If a tail called function callee has more arguments than the caller the
2958 // caller needs to make sure that there is room to move the RETADDR to. This is
2959 // achieved by reserving an area the size of the argument delta right after the
2960 // original REtADDR, but before the saved framepointer or the spilled registers
2961 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2973 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2974 /// for a 16 byte align requirement.
2976 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2977 SelectionDAG& DAG) const {
2978 MachineFunction &MF = DAG.getMachineFunction();
2979 const TargetMachine &TM = MF.getTarget();
2980 const X86RegisterInfo *RegInfo =
2981 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2982 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2983 unsigned StackAlignment = TFI.getStackAlignment();
2984 uint64_t AlignMask = StackAlignment - 1;
2985 int64_t Offset = StackSize;
2986 unsigned SlotSize = RegInfo->getSlotSize();
2987 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2988 // Number smaller than 12 so just add the difference.
2989 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2991 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2992 Offset = ((~AlignMask) & Offset) + StackAlignment +
2993 (StackAlignment-SlotSize);
2998 /// MatchingStackOffset - Return true if the given stack call argument is
2999 /// already available in the same position (relatively) of the caller's
3000 /// incoming argument stack.
3002 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3003 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3004 const X86InstrInfo *TII) {
3005 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3007 if (Arg.getOpcode() == ISD::CopyFromReg) {
3008 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3009 if (!TargetRegisterInfo::isVirtualRegister(VR))
3011 MachineInstr *Def = MRI->getVRegDef(VR);
3014 if (!Flags.isByVal()) {
3015 if (!TII->isLoadFromStackSlot(Def, FI))
3018 unsigned Opcode = Def->getOpcode();
3019 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3020 Def->getOperand(1).isFI()) {
3021 FI = Def->getOperand(1).getIndex();
3022 Bytes = Flags.getByValSize();
3026 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3027 if (Flags.isByVal())
3028 // ByVal argument is passed in as a pointer but it's now being
3029 // dereferenced. e.g.
3030 // define @foo(%struct.X* %A) {
3031 // tail call @bar(%struct.X* byval %A)
3034 SDValue Ptr = Ld->getBasePtr();
3035 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3038 FI = FINode->getIndex();
3039 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3040 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3041 FI = FINode->getIndex();
3042 Bytes = Flags.getByValSize();
3046 assert(FI != INT_MAX);
3047 if (!MFI->isFixedObjectIndex(FI))
3049 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3052 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3053 /// for tail call optimization. Targets which want to do tail call
3054 /// optimization should implement this function.
3056 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3057 CallingConv::ID CalleeCC,
3059 bool isCalleeStructRet,
3060 bool isCallerStructRet,
3062 const SmallVectorImpl<ISD::OutputArg> &Outs,
3063 const SmallVectorImpl<SDValue> &OutVals,
3064 const SmallVectorImpl<ISD::InputArg> &Ins,
3065 SelectionDAG &DAG) const {
3066 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3069 // If -tailcallopt is specified, make fastcc functions tail-callable.
3070 const MachineFunction &MF = DAG.getMachineFunction();
3071 const Function *CallerF = MF.getFunction();
3073 // If the function return type is x86_fp80 and the callee return type is not,
3074 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3075 // perform a tailcall optimization here.
3076 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3079 CallingConv::ID CallerCC = CallerF->getCallingConv();
3080 bool CCMatch = CallerCC == CalleeCC;
3081 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3082 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3084 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3085 if (IsTailCallConvention(CalleeCC) && CCMatch)
3090 // Look for obvious safe cases to perform tail call optimization that do not
3091 // require ABI changes. This is what gcc calls sibcall.
3093 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3094 // emit a special epilogue.
3095 const X86RegisterInfo *RegInfo =
3096 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3097 if (RegInfo->needsStackRealignment(MF))
3100 // Also avoid sibcall optimization if either caller or callee uses struct
3101 // return semantics.
3102 if (isCalleeStructRet || isCallerStructRet)
3105 // An stdcall/thiscall caller is expected to clean up its arguments; the
3106 // callee isn't going to do that.
3107 // FIXME: this is more restrictive than needed. We could produce a tailcall
3108 // when the stack adjustment matches. For example, with a thiscall that takes
3109 // only one argument.
3110 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3111 CallerCC == CallingConv::X86_ThisCall))
3114 // Do not sibcall optimize vararg calls unless all arguments are passed via
3116 if (isVarArg && !Outs.empty()) {
3118 // Optimizing for varargs on Win64 is unlikely to be safe without
3119 // additional testing.
3120 if (IsCalleeWin64 || IsCallerWin64)
3123 SmallVector<CCValAssign, 16> ArgLocs;
3124 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3125 getTargetMachine(), ArgLocs, *DAG.getContext());
3127 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3128 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3129 if (!ArgLocs[i].isRegLoc())
3133 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3134 // stack. Therefore, if it's not used by the call it is not safe to optimize
3135 // this into a sibcall.
3136 bool Unused = false;
3137 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3144 SmallVector<CCValAssign, 16> RVLocs;
3145 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3146 getTargetMachine(), RVLocs, *DAG.getContext());
3147 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3148 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3149 CCValAssign &VA = RVLocs[i];
3150 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3155 // If the calling conventions do not match, then we'd better make sure the
3156 // results are returned in the same way as what the caller expects.
3158 SmallVector<CCValAssign, 16> RVLocs1;
3159 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3160 getTargetMachine(), RVLocs1, *DAG.getContext());
3161 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3163 SmallVector<CCValAssign, 16> RVLocs2;
3164 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3165 getTargetMachine(), RVLocs2, *DAG.getContext());
3166 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3168 if (RVLocs1.size() != RVLocs2.size())
3170 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3171 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3173 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3175 if (RVLocs1[i].isRegLoc()) {
3176 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3179 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3185 // If the callee takes no arguments then go on to check the results of the
3187 if (!Outs.empty()) {
3188 // Check if stack adjustment is needed. For now, do not do this if any
3189 // argument is passed on the stack.
3190 SmallVector<CCValAssign, 16> ArgLocs;
3191 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3192 getTargetMachine(), ArgLocs, *DAG.getContext());
3194 // Allocate shadow area for Win64
3196 CCInfo.AllocateStack(32, 8);
3198 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3199 if (CCInfo.getNextStackOffset()) {
3200 MachineFunction &MF = DAG.getMachineFunction();
3201 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3204 // Check if the arguments are already laid out in the right way as
3205 // the caller's fixed stack objects.
3206 MachineFrameInfo *MFI = MF.getFrameInfo();
3207 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3208 const X86InstrInfo *TII =
3209 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3211 CCValAssign &VA = ArgLocs[i];
3212 SDValue Arg = OutVals[i];
3213 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3214 if (VA.getLocInfo() == CCValAssign::Indirect)
3216 if (!VA.isRegLoc()) {
3217 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3224 // If the tailcall address may be in a register, then make sure it's
3225 // possible to register allocate for it. In 32-bit, the call address can
3226 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3227 // callee-saved registers are restored. These happen to be the same
3228 // registers used to pass 'inreg' arguments so watch out for those.
3229 if (!Subtarget->is64Bit() &&
3230 ((!isa<GlobalAddressSDNode>(Callee) &&
3231 !isa<ExternalSymbolSDNode>(Callee)) ||
3232 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3233 unsigned NumInRegs = 0;
3234 // In PIC we need an extra register to formulate the address computation
3236 unsigned MaxInRegs =
3237 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3239 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3240 CCValAssign &VA = ArgLocs[i];
3243 unsigned Reg = VA.getLocReg();
3246 case X86::EAX: case X86::EDX: case X86::ECX:
3247 if (++NumInRegs == MaxInRegs)
3259 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3260 const TargetLibraryInfo *libInfo) const {
3261 return X86::createFastISel(funcInfo, libInfo);
3264 //===----------------------------------------------------------------------===//
3265 // Other Lowering Hooks
3266 //===----------------------------------------------------------------------===//
3268 static bool MayFoldLoad(SDValue Op) {
3269 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3272 static bool MayFoldIntoStore(SDValue Op) {
3273 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3276 static bool isTargetShuffle(unsigned Opcode) {
3278 default: return false;
3279 case X86ISD::PSHUFD:
3280 case X86ISD::PSHUFHW:
3281 case X86ISD::PSHUFLW:
3283 case X86ISD::PALIGNR:
3284 case X86ISD::MOVLHPS:
3285 case X86ISD::MOVLHPD:
3286 case X86ISD::MOVHLPS:
3287 case X86ISD::MOVLPS:
3288 case X86ISD::MOVLPD:
3289 case X86ISD::MOVSHDUP:
3290 case X86ISD::MOVSLDUP:
3291 case X86ISD::MOVDDUP:
3294 case X86ISD::UNPCKL:
3295 case X86ISD::UNPCKH:
3296 case X86ISD::VPERMILP:
3297 case X86ISD::VPERM2X128:
3298 case X86ISD::VPERMI:
3303 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3304 SDValue V1, SelectionDAG &DAG) {
3306 default: llvm_unreachable("Unknown x86 shuffle node");
3307 case X86ISD::MOVSHDUP:
3308 case X86ISD::MOVSLDUP:
3309 case X86ISD::MOVDDUP:
3310 return DAG.getNode(Opc, dl, VT, V1);
3314 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3315 SDValue V1, unsigned TargetMask,
3316 SelectionDAG &DAG) {
3318 default: llvm_unreachable("Unknown x86 shuffle node");
3319 case X86ISD::PSHUFD:
3320 case X86ISD::PSHUFHW:
3321 case X86ISD::PSHUFLW:
3322 case X86ISD::VPERMILP:
3323 case X86ISD::VPERMI:
3324 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3328 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3329 SDValue V1, SDValue V2, unsigned TargetMask,
3330 SelectionDAG &DAG) {
3332 default: llvm_unreachable("Unknown x86 shuffle node");
3333 case X86ISD::PALIGNR:
3335 case X86ISD::VPERM2X128:
3336 return DAG.getNode(Opc, dl, VT, V1, V2,
3337 DAG.getConstant(TargetMask, MVT::i8));
3341 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3342 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3344 default: llvm_unreachable("Unknown x86 shuffle node");
3345 case X86ISD::MOVLHPS:
3346 case X86ISD::MOVLHPD:
3347 case X86ISD::MOVHLPS:
3348 case X86ISD::MOVLPS:
3349 case X86ISD::MOVLPD:
3352 case X86ISD::UNPCKL:
3353 case X86ISD::UNPCKH:
3354 return DAG.getNode(Opc, dl, VT, V1, V2);
3358 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3359 MachineFunction &MF = DAG.getMachineFunction();
3360 const X86RegisterInfo *RegInfo =
3361 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3362 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3363 int ReturnAddrIndex = FuncInfo->getRAIndex();
3365 if (ReturnAddrIndex == 0) {
3366 // Set up a frame object for the return address.
3367 unsigned SlotSize = RegInfo->getSlotSize();
3368 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3371 FuncInfo->setRAIndex(ReturnAddrIndex);
3374 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3377 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3378 bool hasSymbolicDisplacement) {
3379 // Offset should fit into 32 bit immediate field.
3380 if (!isInt<32>(Offset))
3383 // If we don't have a symbolic displacement - we don't have any extra
3385 if (!hasSymbolicDisplacement)
3388 // FIXME: Some tweaks might be needed for medium code model.
3389 if (M != CodeModel::Small && M != CodeModel::Kernel)
3392 // For small code model we assume that latest object is 16MB before end of 31
3393 // bits boundary. We may also accept pretty large negative constants knowing
3394 // that all objects are in the positive half of address space.
3395 if (M == CodeModel::Small && Offset < 16*1024*1024)
3398 // For kernel code model we know that all object resist in the negative half
3399 // of 32bits address space. We may not accept negative offsets, since they may
3400 // be just off and we may accept pretty large positive ones.
3401 if (M == CodeModel::Kernel && Offset > 0)
3407 /// isCalleePop - Determines whether the callee is required to pop its
3408 /// own arguments. Callee pop is necessary to support tail calls.
3409 bool X86::isCalleePop(CallingConv::ID CallingConv,
3410 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3414 switch (CallingConv) {
3417 case CallingConv::X86_StdCall:
3419 case CallingConv::X86_FastCall:
3421 case CallingConv::X86_ThisCall:
3423 case CallingConv::Fast:
3425 case CallingConv::GHC:
3427 case CallingConv::HiPE:
3432 /// \brief Return true if the condition is an unsigned comparison operation.
3433 static bool isX86CCUnsigned(unsigned X86CC) {
3435 default: llvm_unreachable("Invalid integer condition!");
3436 case X86::COND_E: return true;
3437 case X86::COND_G: return false;
3438 case X86::COND_GE: return false;
3439 case X86::COND_L: return false;
3440 case X86::COND_LE: return false;
3441 case X86::COND_NE: return true;
3442 case X86::COND_B: return true;
3443 case X86::COND_A: return true;
3444 case X86::COND_BE: return true;
3445 case X86::COND_AE: return true;
3447 llvm_unreachable("covered switch fell through?!");
3450 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3451 /// specific condition code, returning the condition code and the LHS/RHS of the
3452 /// comparison to make.
3453 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3454 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3456 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3457 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3458 // X > -1 -> X == 0, jump !sign.
3459 RHS = DAG.getConstant(0, RHS.getValueType());
3460 return X86::COND_NS;
3462 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3463 // X < 0 -> X == 0, jump on sign.
3466 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3468 RHS = DAG.getConstant(0, RHS.getValueType());
3469 return X86::COND_LE;
3473 switch (SetCCOpcode) {
3474 default: llvm_unreachable("Invalid integer condition!");
3475 case ISD::SETEQ: return X86::COND_E;
3476 case ISD::SETGT: return X86::COND_G;
3477 case ISD::SETGE: return X86::COND_GE;
3478 case ISD::SETLT: return X86::COND_L;
3479 case ISD::SETLE: return X86::COND_LE;
3480 case ISD::SETNE: return X86::COND_NE;
3481 case ISD::SETULT: return X86::COND_B;
3482 case ISD::SETUGT: return X86::COND_A;
3483 case ISD::SETULE: return X86::COND_BE;
3484 case ISD::SETUGE: return X86::COND_AE;
3488 // First determine if it is required or is profitable to flip the operands.
3490 // If LHS is a foldable load, but RHS is not, flip the condition.
3491 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3492 !ISD::isNON_EXTLoad(RHS.getNode())) {
3493 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3494 std::swap(LHS, RHS);
3497 switch (SetCCOpcode) {
3503 std::swap(LHS, RHS);
3507 // On a floating point condition, the flags are set as follows:
3509 // 0 | 0 | 0 | X > Y
3510 // 0 | 0 | 1 | X < Y
3511 // 1 | 0 | 0 | X == Y
3512 // 1 | 1 | 1 | unordered
3513 switch (SetCCOpcode) {
3514 default: llvm_unreachable("Condcode should be pre-legalized away");
3516 case ISD::SETEQ: return X86::COND_E;
3517 case ISD::SETOLT: // flipped
3519 case ISD::SETGT: return X86::COND_A;
3520 case ISD::SETOLE: // flipped
3522 case ISD::SETGE: return X86::COND_AE;
3523 case ISD::SETUGT: // flipped
3525 case ISD::SETLT: return X86::COND_B;
3526 case ISD::SETUGE: // flipped
3528 case ISD::SETLE: return X86::COND_BE;
3530 case ISD::SETNE: return X86::COND_NE;
3531 case ISD::SETUO: return X86::COND_P;
3532 case ISD::SETO: return X86::COND_NP;
3534 case ISD::SETUNE: return X86::COND_INVALID;
3538 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3539 /// code. Current x86 isa includes the following FP cmov instructions:
3540 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3541 static bool hasFPCMov(unsigned X86CC) {
3557 /// isFPImmLegal - Returns true if the target can instruction select the
3558 /// specified FP immediate natively. If false, the legalizer will
3559 /// materialize the FP immediate as a load from a constant pool.
3560 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3561 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3562 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3568 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3569 /// the specified range (L, H].
3570 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3571 return (Val < 0) || (Val >= Low && Val < Hi);
3574 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3575 /// specified value.
3576 static bool isUndefOrEqual(int Val, int CmpVal) {
3577 return (Val < 0 || Val == CmpVal);
3580 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3581 /// from position Pos and ending in Pos+Size, falls within the specified
3582 /// sequential range (L, L+Pos]. or is undef.
3583 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3584 unsigned Pos, unsigned Size, int Low) {
3585 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3586 if (!isUndefOrEqual(Mask[i], Low))
3591 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3592 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3593 /// the second operand.
3594 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3595 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3596 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3597 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3598 return (Mask[0] < 2 && Mask[1] < 2);
3602 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3603 /// is suitable for input to PSHUFHW.
3604 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3605 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3608 // Lower quadword copied in order or undef.
3609 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3612 // Upper quadword shuffled.
3613 for (unsigned i = 4; i != 8; ++i)
3614 if (!isUndefOrInRange(Mask[i], 4, 8))
3617 if (VT == MVT::v16i16) {
3618 // Lower quadword copied in order or undef.
3619 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3622 // Upper quadword shuffled.
3623 for (unsigned i = 12; i != 16; ++i)
3624 if (!isUndefOrInRange(Mask[i], 12, 16))
3631 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3632 /// is suitable for input to PSHUFLW.
3633 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3634 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3637 // Upper quadword copied in order.
3638 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3641 // Lower quadword shuffled.
3642 for (unsigned i = 0; i != 4; ++i)
3643 if (!isUndefOrInRange(Mask[i], 0, 4))
3646 if (VT == MVT::v16i16) {
3647 // Upper quadword copied in order.
3648 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3651 // Lower quadword shuffled.
3652 for (unsigned i = 8; i != 12; ++i)
3653 if (!isUndefOrInRange(Mask[i], 8, 12))
3660 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3661 /// is suitable for input to PALIGNR.
3662 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3663 const X86Subtarget *Subtarget) {
3664 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3665 (VT.is256BitVector() && !Subtarget->hasInt256()))
3668 unsigned NumElts = VT.getVectorNumElements();
3669 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3670 unsigned NumLaneElts = NumElts/NumLanes;
3672 // Do not handle 64-bit element shuffles with palignr.
3673 if (NumLaneElts == 2)
3676 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3678 for (i = 0; i != NumLaneElts; ++i) {
3683 // Lane is all undef, go to next lane
3684 if (i == NumLaneElts)
3687 int Start = Mask[i+l];
3689 // Make sure its in this lane in one of the sources
3690 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3691 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3694 // If not lane 0, then we must match lane 0
3695 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3698 // Correct second source to be contiguous with first source
3699 if (Start >= (int)NumElts)
3700 Start -= NumElts - NumLaneElts;
3702 // Make sure we're shifting in the right direction.
3703 if (Start <= (int)(i+l))
3708 // Check the rest of the elements to see if they are consecutive.
3709 for (++i; i != NumLaneElts; ++i) {
3710 int Idx = Mask[i+l];
3712 // Make sure its in this lane
3713 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3714 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3717 // If not lane 0, then we must match lane 0
3718 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3721 if (Idx >= (int)NumElts)
3722 Idx -= NumElts - NumLaneElts;
3724 if (!isUndefOrEqual(Idx, Start+i))
3733 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3734 /// the two vector operands have swapped position.
3735 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3736 unsigned NumElems) {
3737 for (unsigned i = 0; i != NumElems; ++i) {
3741 else if (idx < (int)NumElems)
3742 Mask[i] = idx + NumElems;
3744 Mask[i] = idx - NumElems;
3748 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3749 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3750 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3751 /// reverse of what x86 shuffles want.
3752 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3754 unsigned NumElems = VT.getVectorNumElements();
3755 unsigned NumLanes = VT.getSizeInBits()/128;
3756 unsigned NumLaneElems = NumElems/NumLanes;
3758 if (NumLaneElems != 2 && NumLaneElems != 4)
3761 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3762 bool symetricMaskRequired =
3763 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3765 // VSHUFPSY divides the resulting vector into 4 chunks.
3766 // The sources are also splitted into 4 chunks, and each destination
3767 // chunk must come from a different source chunk.
3769 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3770 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3772 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3773 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3775 // VSHUFPDY divides the resulting vector into 4 chunks.
3776 // The sources are also splitted into 4 chunks, and each destination
3777 // chunk must come from a different source chunk.
3779 // SRC1 => X3 X2 X1 X0
3780 // SRC2 => Y3 Y2 Y1 Y0
3782 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3784 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3785 unsigned HalfLaneElems = NumLaneElems/2;
3786 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3787 for (unsigned i = 0; i != NumLaneElems; ++i) {
3788 int Idx = Mask[i+l];
3789 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3790 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3792 // For VSHUFPSY, the mask of the second half must be the same as the
3793 // first but with the appropriate offsets. This works in the same way as
3794 // VPERMILPS works with masks.
3795 if (!symetricMaskRequired || Idx < 0)
3797 if (MaskVal[i] < 0) {
3798 MaskVal[i] = Idx - l;
3801 if ((signed)(Idx - l) != MaskVal[i])
3809 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3810 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3811 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3812 if (!VT.is128BitVector())
3815 unsigned NumElems = VT.getVectorNumElements();
3820 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3821 return isUndefOrEqual(Mask[0], 6) &&
3822 isUndefOrEqual(Mask[1], 7) &&
3823 isUndefOrEqual(Mask[2], 2) &&
3824 isUndefOrEqual(Mask[3], 3);
3827 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3828 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3830 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3831 if (!VT.is128BitVector())
3834 unsigned NumElems = VT.getVectorNumElements();
3839 return isUndefOrEqual(Mask[0], 2) &&
3840 isUndefOrEqual(Mask[1], 3) &&
3841 isUndefOrEqual(Mask[2], 2) &&
3842 isUndefOrEqual(Mask[3], 3);
3845 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3846 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3847 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3848 if (!VT.is128BitVector())
3851 unsigned NumElems = VT.getVectorNumElements();
3853 if (NumElems != 2 && NumElems != 4)
3856 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3857 if (!isUndefOrEqual(Mask[i], i + NumElems))
3860 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3861 if (!isUndefOrEqual(Mask[i], i))
3867 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3868 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3869 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3870 if (!VT.is128BitVector())
3873 unsigned NumElems = VT.getVectorNumElements();
3875 if (NumElems != 2 && NumElems != 4)
3878 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3879 if (!isUndefOrEqual(Mask[i], i))
3882 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3883 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3890 // Some special combinations that can be optimized.
3893 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3894 SelectionDAG &DAG) {
3895 MVT VT = SVOp->getSimpleValueType(0);
3898 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3901 ArrayRef<int> Mask = SVOp->getMask();
3903 // These are the special masks that may be optimized.
3904 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3905 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3906 bool MatchEvenMask = true;
3907 bool MatchOddMask = true;
3908 for (int i=0; i<8; ++i) {
3909 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3910 MatchEvenMask = false;
3911 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3912 MatchOddMask = false;
3915 if (!MatchEvenMask && !MatchOddMask)
3918 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3920 SDValue Op0 = SVOp->getOperand(0);
3921 SDValue Op1 = SVOp->getOperand(1);
3923 if (MatchEvenMask) {
3924 // Shift the second operand right to 32 bits.
3925 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3926 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3928 // Shift the first operand left to 32 bits.
3929 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3930 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3932 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3933 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3936 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3937 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3938 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3939 bool HasInt256, bool V2IsSplat = false) {
3941 assert(VT.getSizeInBits() >= 128 &&
3942 "Unsupported vector type for unpckl");
3944 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3946 unsigned NumOf256BitLanes;
3947 unsigned NumElts = VT.getVectorNumElements();
3948 if (VT.is256BitVector()) {
3949 if (NumElts != 4 && NumElts != 8 &&
3950 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3953 NumOf256BitLanes = 1;
3954 } else if (VT.is512BitVector()) {
3955 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3956 "Unsupported vector type for unpckh");
3958 NumOf256BitLanes = 2;
3961 NumOf256BitLanes = 1;
3964 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3965 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3967 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3968 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3969 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3970 int BitI = Mask[l256*NumEltsInStride+l+i];
3971 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3972 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3974 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3976 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3984 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3985 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3986 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3987 bool HasInt256, bool V2IsSplat = false) {
3988 assert(VT.getSizeInBits() >= 128 &&
3989 "Unsupported vector type for unpckh");
3991 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3993 unsigned NumOf256BitLanes;
3994 unsigned NumElts = VT.getVectorNumElements();
3995 if (VT.is256BitVector()) {
3996 if (NumElts != 4 && NumElts != 8 &&
3997 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4000 NumOf256BitLanes = 1;
4001 } else if (VT.is512BitVector()) {
4002 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4003 "Unsupported vector type for unpckh");
4005 NumOf256BitLanes = 2;
4008 NumOf256BitLanes = 1;
4011 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4012 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4014 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4015 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4016 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4017 int BitI = Mask[l256*NumEltsInStride+l+i];
4018 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4019 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4021 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4023 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4031 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4032 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4034 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4035 unsigned NumElts = VT.getVectorNumElements();
4036 bool Is256BitVec = VT.is256BitVector();
4038 if (VT.is512BitVector())
4040 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4041 "Unsupported vector type for unpckh");
4043 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4044 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4047 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4048 // FIXME: Need a better way to get rid of this, there's no latency difference
4049 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4050 // the former later. We should also remove the "_undef" special mask.
4051 if (NumElts == 4 && Is256BitVec)
4054 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4055 // independently on 128-bit lanes.
4056 unsigned NumLanes = VT.getSizeInBits()/128;
4057 unsigned NumLaneElts = NumElts/NumLanes;
4059 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4060 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4061 int BitI = Mask[l+i];
4062 int BitI1 = Mask[l+i+1];
4064 if (!isUndefOrEqual(BitI, j))
4066 if (!isUndefOrEqual(BitI1, j))
4074 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4075 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4077 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4078 unsigned NumElts = VT.getVectorNumElements();
4080 if (VT.is512BitVector())
4083 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4084 "Unsupported vector type for unpckh");
4086 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4087 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4090 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4091 // independently on 128-bit lanes.
4092 unsigned NumLanes = VT.getSizeInBits()/128;
4093 unsigned NumLaneElts = NumElts/NumLanes;
4095 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4096 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4097 int BitI = Mask[l+i];
4098 int BitI1 = Mask[l+i+1];
4099 if (!isUndefOrEqual(BitI, j))
4101 if (!isUndefOrEqual(BitI1, j))
4108 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4109 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4110 /// MOVSD, and MOVD, i.e. setting the lowest element.
4111 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4112 if (VT.getVectorElementType().getSizeInBits() < 32)
4114 if (!VT.is128BitVector())
4117 unsigned NumElts = VT.getVectorNumElements();
4119 if (!isUndefOrEqual(Mask[0], NumElts))
4122 for (unsigned i = 1; i != NumElts; ++i)
4123 if (!isUndefOrEqual(Mask[i], i))
4129 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4130 /// as permutations between 128-bit chunks or halves. As an example: this
4132 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4133 /// The first half comes from the second half of V1 and the second half from the
4134 /// the second half of V2.
4135 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4136 if (!HasFp256 || !VT.is256BitVector())
4139 // The shuffle result is divided into half A and half B. In total the two
4140 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4141 // B must come from C, D, E or F.
4142 unsigned HalfSize = VT.getVectorNumElements()/2;
4143 bool MatchA = false, MatchB = false;
4145 // Check if A comes from one of C, D, E, F.
4146 for (unsigned Half = 0; Half != 4; ++Half) {
4147 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4153 // Check if B comes from one of C, D, E, F.
4154 for (unsigned Half = 0; Half != 4; ++Half) {
4155 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4161 return MatchA && MatchB;
4164 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4165 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4166 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4167 MVT VT = SVOp->getSimpleValueType(0);
4169 unsigned HalfSize = VT.getVectorNumElements()/2;
4171 unsigned FstHalf = 0, SndHalf = 0;
4172 for (unsigned i = 0; i < HalfSize; ++i) {
4173 if (SVOp->getMaskElt(i) > 0) {
4174 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4178 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4179 if (SVOp->getMaskElt(i) > 0) {
4180 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4185 return (FstHalf | (SndHalf << 4));
4188 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4189 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4190 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4194 unsigned NumElts = VT.getVectorNumElements();
4196 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4197 for (unsigned i = 0; i != NumElts; ++i) {
4200 Imm8 |= Mask[i] << (i*2);
4205 unsigned LaneSize = 4;
4206 SmallVector<int, 4> MaskVal(LaneSize, -1);
4208 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4209 for (unsigned i = 0; i != LaneSize; ++i) {
4210 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4214 if (MaskVal[i] < 0) {
4215 MaskVal[i] = Mask[i+l] - l;
4216 Imm8 |= MaskVal[i] << (i*2);
4219 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4226 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4227 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4228 /// Note that VPERMIL mask matching is different depending whether theunderlying
4229 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4230 /// to the same elements of the low, but to the higher half of the source.
4231 /// In VPERMILPD the two lanes could be shuffled independently of each other
4232 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4233 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4234 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4235 if (VT.getSizeInBits() < 256 || EltSize < 32)
4237 bool symetricMaskRequired = (EltSize == 32);
4238 unsigned NumElts = VT.getVectorNumElements();
4240 unsigned NumLanes = VT.getSizeInBits()/128;
4241 unsigned LaneSize = NumElts/NumLanes;
4242 // 2 or 4 elements in one lane
4244 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4245 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4246 for (unsigned i = 0; i != LaneSize; ++i) {
4247 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4249 if (symetricMaskRequired) {
4250 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4251 ExpectedMaskVal[i] = Mask[i+l] - l;
4254 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4262 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4263 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4264 /// element of vector 2 and the other elements to come from vector 1 in order.
4265 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4266 bool V2IsSplat = false, bool V2IsUndef = false) {
4267 if (!VT.is128BitVector())
4270 unsigned NumOps = VT.getVectorNumElements();
4271 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4274 if (!isUndefOrEqual(Mask[0], 0))
4277 for (unsigned i = 1; i != NumOps; ++i)
4278 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4279 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4280 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4286 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4287 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4288 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4289 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4290 const X86Subtarget *Subtarget) {
4291 if (!Subtarget->hasSSE3())
4294 unsigned NumElems = VT.getVectorNumElements();
4296 if ((VT.is128BitVector() && NumElems != 4) ||
4297 (VT.is256BitVector() && NumElems != 8) ||
4298 (VT.is512BitVector() && NumElems != 16))
4301 // "i+1" is the value the indexed mask element must have
4302 for (unsigned i = 0; i != NumElems; i += 2)
4303 if (!isUndefOrEqual(Mask[i], i+1) ||
4304 !isUndefOrEqual(Mask[i+1], i+1))
4310 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4311 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4312 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4313 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4314 const X86Subtarget *Subtarget) {
4315 if (!Subtarget->hasSSE3())
4318 unsigned NumElems = VT.getVectorNumElements();
4320 if ((VT.is128BitVector() && NumElems != 4) ||
4321 (VT.is256BitVector() && NumElems != 8) ||
4322 (VT.is512BitVector() && NumElems != 16))
4325 // "i" is the value the indexed mask element must have
4326 for (unsigned i = 0; i != NumElems; i += 2)
4327 if (!isUndefOrEqual(Mask[i], i) ||
4328 !isUndefOrEqual(Mask[i+1], i))
4334 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4335 /// specifies a shuffle of elements that is suitable for input to 256-bit
4336 /// version of MOVDDUP.
4337 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4338 if (!HasFp256 || !VT.is256BitVector())
4341 unsigned NumElts = VT.getVectorNumElements();
4345 for (unsigned i = 0; i != NumElts/2; ++i)
4346 if (!isUndefOrEqual(Mask[i], 0))
4348 for (unsigned i = NumElts/2; i != NumElts; ++i)
4349 if (!isUndefOrEqual(Mask[i], NumElts/2))
4354 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4355 /// specifies a shuffle of elements that is suitable for input to 128-bit
4356 /// version of MOVDDUP.
4357 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4358 if (!VT.is128BitVector())
4361 unsigned e = VT.getVectorNumElements() / 2;
4362 for (unsigned i = 0; i != e; ++i)
4363 if (!isUndefOrEqual(Mask[i], i))
4365 for (unsigned i = 0; i != e; ++i)
4366 if (!isUndefOrEqual(Mask[e+i], i))
4371 /// isVEXTRACTIndex - Return true if the specified
4372 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4373 /// suitable for instruction that extract 128 or 256 bit vectors
4374 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4375 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4376 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4379 // The index should be aligned on a vecWidth-bit boundary.
4381 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4383 MVT VT = N->getSimpleValueType(0);
4384 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4385 bool Result = (Index * ElSize) % vecWidth == 0;
4390 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4391 /// operand specifies a subvector insert that is suitable for input to
4392 /// insertion of 128 or 256-bit subvectors
4393 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4394 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4395 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4397 // The index should be aligned on a vecWidth-bit boundary.
4399 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4401 MVT VT = N->getSimpleValueType(0);
4402 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4403 bool Result = (Index * ElSize) % vecWidth == 0;
4408 bool X86::isVINSERT128Index(SDNode *N) {
4409 return isVINSERTIndex(N, 128);
4412 bool X86::isVINSERT256Index(SDNode *N) {
4413 return isVINSERTIndex(N, 256);
4416 bool X86::isVEXTRACT128Index(SDNode *N) {
4417 return isVEXTRACTIndex(N, 128);
4420 bool X86::isVEXTRACT256Index(SDNode *N) {
4421 return isVEXTRACTIndex(N, 256);
4424 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4425 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4426 /// Handles 128-bit and 256-bit.
4427 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4428 MVT VT = N->getSimpleValueType(0);
4430 assert((VT.getSizeInBits() >= 128) &&
4431 "Unsupported vector type for PSHUF/SHUFP");
4433 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4434 // independently on 128-bit lanes.
4435 unsigned NumElts = VT.getVectorNumElements();
4436 unsigned NumLanes = VT.getSizeInBits()/128;
4437 unsigned NumLaneElts = NumElts/NumLanes;
4439 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4440 "Only supports 2, 4 or 8 elements per lane");
4442 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4444 for (unsigned i = 0; i != NumElts; ++i) {
4445 int Elt = N->getMaskElt(i);
4446 if (Elt < 0) continue;
4447 Elt &= NumLaneElts - 1;
4448 unsigned ShAmt = (i << Shift) % 8;
4449 Mask |= Elt << ShAmt;
4455 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4456 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4457 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4458 MVT VT = N->getSimpleValueType(0);
4460 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4461 "Unsupported vector type for PSHUFHW");
4463 unsigned NumElts = VT.getVectorNumElements();
4466 for (unsigned l = 0; l != NumElts; l += 8) {
4467 // 8 nodes per lane, but we only care about the last 4.
4468 for (unsigned i = 0; i < 4; ++i) {
4469 int Elt = N->getMaskElt(l+i+4);
4470 if (Elt < 0) continue;
4471 Elt &= 0x3; // only 2-bits.
4472 Mask |= Elt << (i * 2);
4479 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4480 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4481 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4482 MVT VT = N->getSimpleValueType(0);
4484 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4485 "Unsupported vector type for PSHUFHW");
4487 unsigned NumElts = VT.getVectorNumElements();
4490 for (unsigned l = 0; l != NumElts; l += 8) {
4491 // 8 nodes per lane, but we only care about the first 4.
4492 for (unsigned i = 0; i < 4; ++i) {
4493 int Elt = N->getMaskElt(l+i);
4494 if (Elt < 0) continue;
4495 Elt &= 0x3; // only 2-bits
4496 Mask |= Elt << (i * 2);
4503 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4504 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4505 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4506 MVT VT = SVOp->getSimpleValueType(0);
4507 unsigned EltSize = VT.is512BitVector() ? 1 :
4508 VT.getVectorElementType().getSizeInBits() >> 3;
4510 unsigned NumElts = VT.getVectorNumElements();
4511 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4512 unsigned NumLaneElts = NumElts/NumLanes;
4516 for (i = 0; i != NumElts; ++i) {
4517 Val = SVOp->getMaskElt(i);
4521 if (Val >= (int)NumElts)
4522 Val -= NumElts - NumLaneElts;
4524 assert(Val - i > 0 && "PALIGNR imm should be positive");
4525 return (Val - i) * EltSize;
4528 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4529 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4530 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4531 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4534 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4536 MVT VecVT = N->getOperand(0).getSimpleValueType();
4537 MVT ElVT = VecVT.getVectorElementType();
4539 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4540 return Index / NumElemsPerChunk;
4543 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4544 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4545 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4546 llvm_unreachable("Illegal insert subvector for VINSERT");
4549 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4551 MVT VecVT = N->getSimpleValueType(0);
4552 MVT ElVT = VecVT.getVectorElementType();
4554 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4555 return Index / NumElemsPerChunk;
4558 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4559 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4560 /// and VINSERTI128 instructions.
4561 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4562 return getExtractVEXTRACTImmediate(N, 128);
4565 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4566 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4567 /// and VINSERTI64x4 instructions.
4568 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4569 return getExtractVEXTRACTImmediate(N, 256);
4572 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4573 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4574 /// and VINSERTI128 instructions.
4575 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4576 return getInsertVINSERTImmediate(N, 128);
4579 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4580 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4581 /// and VINSERTI64x4 instructions.
4582 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4583 return getInsertVINSERTImmediate(N, 256);
4586 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4588 bool X86::isZeroNode(SDValue Elt) {
4589 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4590 return CN->isNullValue();
4591 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4592 return CFP->getValueAPF().isPosZero();
4596 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4597 /// their permute mask.
4598 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4599 SelectionDAG &DAG) {
4600 MVT VT = SVOp->getSimpleValueType(0);
4601 unsigned NumElems = VT.getVectorNumElements();
4602 SmallVector<int, 8> MaskVec;
4604 for (unsigned i = 0; i != NumElems; ++i) {
4605 int Idx = SVOp->getMaskElt(i);
4607 if (Idx < (int)NumElems)
4612 MaskVec.push_back(Idx);
4614 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4615 SVOp->getOperand(0), &MaskVec[0]);
4618 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4619 /// match movhlps. The lower half elements should come from upper half of
4620 /// V1 (and in order), and the upper half elements should come from the upper
4621 /// half of V2 (and in order).
4622 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4623 if (!VT.is128BitVector())
4625 if (VT.getVectorNumElements() != 4)
4627 for (unsigned i = 0, e = 2; i != e; ++i)
4628 if (!isUndefOrEqual(Mask[i], i+2))
4630 for (unsigned i = 2; i != 4; ++i)
4631 if (!isUndefOrEqual(Mask[i], i+4))
4636 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4637 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4639 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4640 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4642 N = N->getOperand(0).getNode();
4643 if (!ISD::isNON_EXTLoad(N))
4646 *LD = cast<LoadSDNode>(N);
4650 // Test whether the given value is a vector value which will be legalized
4652 static bool WillBeConstantPoolLoad(SDNode *N) {
4653 if (N->getOpcode() != ISD::BUILD_VECTOR)
4656 // Check for any non-constant elements.
4657 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4658 switch (N->getOperand(i).getNode()->getOpcode()) {
4660 case ISD::ConstantFP:
4667 // Vectors of all-zeros and all-ones are materialized with special
4668 // instructions rather than being loaded.
4669 return !ISD::isBuildVectorAllZeros(N) &&
4670 !ISD::isBuildVectorAllOnes(N);
4673 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4674 /// match movlp{s|d}. The lower half elements should come from lower half of
4675 /// V1 (and in order), and the upper half elements should come from the upper
4676 /// half of V2 (and in order). And since V1 will become the source of the
4677 /// MOVLP, it must be either a vector load or a scalar load to vector.
4678 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4679 ArrayRef<int> Mask, MVT VT) {
4680 if (!VT.is128BitVector())
4683 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4685 // Is V2 is a vector load, don't do this transformation. We will try to use
4686 // load folding shufps op.
4687 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4690 unsigned NumElems = VT.getVectorNumElements();
4692 if (NumElems != 2 && NumElems != 4)
4694 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4695 if (!isUndefOrEqual(Mask[i], i))
4697 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4698 if (!isUndefOrEqual(Mask[i], i+NumElems))
4703 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4705 static bool isSplatVector(SDNode *N) {
4706 if (N->getOpcode() != ISD::BUILD_VECTOR)
4709 SDValue SplatValue = N->getOperand(0);
4710 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4711 if (N->getOperand(i) != SplatValue)
4716 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4717 /// to an zero vector.
4718 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4719 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4720 SDValue V1 = N->getOperand(0);
4721 SDValue V2 = N->getOperand(1);
4722 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4723 for (unsigned i = 0; i != NumElems; ++i) {
4724 int Idx = N->getMaskElt(i);
4725 if (Idx >= (int)NumElems) {
4726 unsigned Opc = V2.getOpcode();
4727 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4729 if (Opc != ISD::BUILD_VECTOR ||
4730 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4732 } else if (Idx >= 0) {
4733 unsigned Opc = V1.getOpcode();
4734 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4736 if (Opc != ISD::BUILD_VECTOR ||
4737 !X86::isZeroNode(V1.getOperand(Idx)))
4744 /// getZeroVector - Returns a vector of specified type with all zero elements.
4746 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4747 SelectionDAG &DAG, SDLoc dl) {
4748 assert(VT.isVector() && "Expected a vector type");
4750 // Always build SSE zero vectors as <4 x i32> bitcasted
4751 // to their dest type. This ensures they get CSE'd.
4753 if (VT.is128BitVector()) { // SSE
4754 if (Subtarget->hasSSE2()) { // SSE2
4755 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4756 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4758 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4759 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4761 } else if (VT.is256BitVector()) { // AVX
4762 if (Subtarget->hasInt256()) { // AVX2
4763 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4764 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4765 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4766 array_lengthof(Ops));
4768 // 256-bit logic and arithmetic instructions in AVX are all
4769 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4770 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4771 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4772 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4773 array_lengthof(Ops));
4775 } else if (VT.is512BitVector()) { // AVX-512
4776 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4777 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4778 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4779 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4781 llvm_unreachable("Unexpected vector type");
4783 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4786 /// getOnesVector - Returns a vector of specified type with all bits set.
4787 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4788 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4789 /// Then bitcast to their original type, ensuring they get CSE'd.
4790 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4792 assert(VT.isVector() && "Expected a vector type");
4794 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4796 if (VT.is256BitVector()) {
4797 if (HasInt256) { // AVX2
4798 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4799 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4800 array_lengthof(Ops));
4802 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4803 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4805 } else if (VT.is128BitVector()) {
4806 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4808 llvm_unreachable("Unexpected vector type");
4810 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4813 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4814 /// that point to V2 points to its first element.
4815 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4816 for (unsigned i = 0; i != NumElems; ++i) {
4817 if (Mask[i] > (int)NumElems) {
4823 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4824 /// operation of specified width.
4825 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4827 unsigned NumElems = VT.getVectorNumElements();
4828 SmallVector<int, 8> Mask;
4829 Mask.push_back(NumElems);
4830 for (unsigned i = 1; i != NumElems; ++i)
4832 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4835 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4836 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4838 unsigned NumElems = VT.getVectorNumElements();
4839 SmallVector<int, 8> Mask;
4840 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4842 Mask.push_back(i + NumElems);
4844 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4847 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4848 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4850 unsigned NumElems = VT.getVectorNumElements();
4851 SmallVector<int, 8> Mask;
4852 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4853 Mask.push_back(i + Half);
4854 Mask.push_back(i + NumElems + Half);
4856 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4859 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4860 // a generic shuffle instruction because the target has no such instructions.
4861 // Generate shuffles which repeat i16 and i8 several times until they can be
4862 // represented by v4f32 and then be manipulated by target suported shuffles.
4863 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4864 MVT VT = V.getSimpleValueType();
4865 int NumElems = VT.getVectorNumElements();
4868 while (NumElems > 4) {
4869 if (EltNo < NumElems/2) {
4870 V = getUnpackl(DAG, dl, VT, V, V);
4872 V = getUnpackh(DAG, dl, VT, V, V);
4873 EltNo -= NumElems/2;
4880 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4881 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4882 MVT VT = V.getSimpleValueType();
4885 if (VT.is128BitVector()) {
4886 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4887 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4888 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4890 } else if (VT.is256BitVector()) {
4891 // To use VPERMILPS to splat scalars, the second half of indicies must
4892 // refer to the higher part, which is a duplication of the lower one,
4893 // because VPERMILPS can only handle in-lane permutations.
4894 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4895 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4897 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4898 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4901 llvm_unreachable("Vector size not supported");
4903 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4906 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4907 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4908 MVT SrcVT = SV->getSimpleValueType(0);
4909 SDValue V1 = SV->getOperand(0);
4912 int EltNo = SV->getSplatIndex();
4913 int NumElems = SrcVT.getVectorNumElements();
4914 bool Is256BitVec = SrcVT.is256BitVector();
4916 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4917 "Unknown how to promote splat for type");
4919 // Extract the 128-bit part containing the splat element and update
4920 // the splat element index when it refers to the higher register.
4922 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4923 if (EltNo >= NumElems/2)
4924 EltNo -= NumElems/2;
4927 // All i16 and i8 vector types can't be used directly by a generic shuffle
4928 // instruction because the target has no such instruction. Generate shuffles
4929 // which repeat i16 and i8 several times until they fit in i32, and then can
4930 // be manipulated by target suported shuffles.
4931 MVT EltVT = SrcVT.getVectorElementType();
4932 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4933 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4935 // Recreate the 256-bit vector and place the same 128-bit vector
4936 // into the low and high part. This is necessary because we want
4937 // to use VPERM* to shuffle the vectors
4939 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4942 return getLegalSplat(DAG, V1, EltNo);
4945 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4946 /// vector of zero or undef vector. This produces a shuffle where the low
4947 /// element of V2 is swizzled into the zero/undef vector, landing at element
4948 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4949 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4951 const X86Subtarget *Subtarget,
4952 SelectionDAG &DAG) {
4953 MVT VT = V2.getSimpleValueType();
4955 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4956 unsigned NumElems = VT.getVectorNumElements();
4957 SmallVector<int, 16> MaskVec;
4958 for (unsigned i = 0; i != NumElems; ++i)
4959 // If this is the insertion idx, put the low elt of V2 here.
4960 MaskVec.push_back(i == Idx ? NumElems : i);
4961 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4964 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4965 /// target specific opcode. Returns true if the Mask could be calculated.
4966 /// Sets IsUnary to true if only uses one source.
4967 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4968 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4969 unsigned NumElems = VT.getVectorNumElements();
4973 switch(N->getOpcode()) {
4975 ImmN = N->getOperand(N->getNumOperands()-1);
4976 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4978 case X86ISD::UNPCKH:
4979 DecodeUNPCKHMask(VT, Mask);
4981 case X86ISD::UNPCKL:
4982 DecodeUNPCKLMask(VT, Mask);
4984 case X86ISD::MOVHLPS:
4985 DecodeMOVHLPSMask(NumElems, Mask);
4987 case X86ISD::MOVLHPS:
4988 DecodeMOVLHPSMask(NumElems, Mask);
4990 case X86ISD::PALIGNR:
4991 ImmN = N->getOperand(N->getNumOperands()-1);
4992 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4994 case X86ISD::PSHUFD:
4995 case X86ISD::VPERMILP:
4996 ImmN = N->getOperand(N->getNumOperands()-1);
4997 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5000 case X86ISD::PSHUFHW:
5001 ImmN = N->getOperand(N->getNumOperands()-1);
5002 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5005 case X86ISD::PSHUFLW:
5006 ImmN = N->getOperand(N->getNumOperands()-1);
5007 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5010 case X86ISD::VPERMI:
5011 ImmN = N->getOperand(N->getNumOperands()-1);
5012 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5016 case X86ISD::MOVSD: {
5017 // The index 0 always comes from the first element of the second source,
5018 // this is why MOVSS and MOVSD are used in the first place. The other
5019 // elements come from the other positions of the first source vector
5020 Mask.push_back(NumElems);
5021 for (unsigned i = 1; i != NumElems; ++i) {
5026 case X86ISD::VPERM2X128:
5027 ImmN = N->getOperand(N->getNumOperands()-1);
5028 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5029 if (Mask.empty()) return false;
5031 case X86ISD::MOVDDUP:
5032 case X86ISD::MOVLHPD:
5033 case X86ISD::MOVLPD:
5034 case X86ISD::MOVLPS:
5035 case X86ISD::MOVSHDUP:
5036 case X86ISD::MOVSLDUP:
5037 // Not yet implemented
5039 default: llvm_unreachable("unknown target shuffle node");
5045 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5046 /// element of the result of the vector shuffle.
5047 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5050 return SDValue(); // Limit search depth.
5052 SDValue V = SDValue(N, 0);
5053 EVT VT = V.getValueType();
5054 unsigned Opcode = V.getOpcode();
5056 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5057 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5058 int Elt = SV->getMaskElt(Index);
5061 return DAG.getUNDEF(VT.getVectorElementType());
5063 unsigned NumElems = VT.getVectorNumElements();
5064 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5065 : SV->getOperand(1);
5066 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5069 // Recurse into target specific vector shuffles to find scalars.
5070 if (isTargetShuffle(Opcode)) {
5071 MVT ShufVT = V.getSimpleValueType();
5072 unsigned NumElems = ShufVT.getVectorNumElements();
5073 SmallVector<int, 16> ShuffleMask;
5076 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5079 int Elt = ShuffleMask[Index];
5081 return DAG.getUNDEF(ShufVT.getVectorElementType());
5083 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5085 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5089 // Actual nodes that may contain scalar elements
5090 if (Opcode == ISD::BITCAST) {
5091 V = V.getOperand(0);
5092 EVT SrcVT = V.getValueType();
5093 unsigned NumElems = VT.getVectorNumElements();
5095 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5099 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5100 return (Index == 0) ? V.getOperand(0)
5101 : DAG.getUNDEF(VT.getVectorElementType());
5103 if (V.getOpcode() == ISD::BUILD_VECTOR)
5104 return V.getOperand(Index);
5109 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5110 /// shuffle operation which come from a consecutively from a zero. The
5111 /// search can start in two different directions, from left or right.
5112 /// We count undefs as zeros until PreferredNum is reached.
5113 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5114 unsigned NumElems, bool ZerosFromLeft,
5116 unsigned PreferredNum = -1U) {
5117 unsigned NumZeros = 0;
5118 for (unsigned i = 0; i != NumElems; ++i) {
5119 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5120 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5124 if (X86::isZeroNode(Elt))
5126 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5127 NumZeros = std::min(NumZeros + 1, PreferredNum);
5135 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5136 /// correspond consecutively to elements from one of the vector operands,
5137 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5139 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5140 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5141 unsigned NumElems, unsigned &OpNum) {
5142 bool SeenV1 = false;
5143 bool SeenV2 = false;
5145 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5146 int Idx = SVOp->getMaskElt(i);
5147 // Ignore undef indicies
5151 if (Idx < (int)NumElems)
5156 // Only accept consecutive elements from the same vector
5157 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5161 OpNum = SeenV1 ? 0 : 1;
5165 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5166 /// logical left shift of a vector.
5167 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5168 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5170 SVOp->getSimpleValueType(0).getVectorNumElements();
5171 unsigned NumZeros = getNumOfConsecutiveZeros(
5172 SVOp, NumElems, false /* check zeros from right */, DAG,
5173 SVOp->getMaskElt(0));
5179 // Considering the elements in the mask that are not consecutive zeros,
5180 // check if they consecutively come from only one of the source vectors.
5182 // V1 = {X, A, B, C} 0
5184 // vector_shuffle V1, V2 <1, 2, 3, X>
5186 if (!isShuffleMaskConsecutive(SVOp,
5187 0, // Mask Start Index
5188 NumElems-NumZeros, // Mask End Index(exclusive)
5189 NumZeros, // Where to start looking in the src vector
5190 NumElems, // Number of elements in vector
5191 OpSrc)) // Which source operand ?
5196 ShVal = SVOp->getOperand(OpSrc);
5200 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5201 /// logical left shift of a vector.
5202 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5203 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5205 SVOp->getSimpleValueType(0).getVectorNumElements();
5206 unsigned NumZeros = getNumOfConsecutiveZeros(
5207 SVOp, NumElems, true /* check zeros from left */, DAG,
5208 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5214 // Considering the elements in the mask that are not consecutive zeros,
5215 // check if they consecutively come from only one of the source vectors.
5217 // 0 { A, B, X, X } = V2
5219 // vector_shuffle V1, V2 <X, X, 4, 5>
5221 if (!isShuffleMaskConsecutive(SVOp,
5222 NumZeros, // Mask Start Index
5223 NumElems, // Mask End Index(exclusive)
5224 0, // Where to start looking in the src vector
5225 NumElems, // Number of elements in vector
5226 OpSrc)) // Which source operand ?
5231 ShVal = SVOp->getOperand(OpSrc);
5235 /// isVectorShift - Returns true if the shuffle can be implemented as a
5236 /// logical left or right shift of a vector.
5237 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5238 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5239 // Although the logic below support any bitwidth size, there are no
5240 // shift instructions which handle more than 128-bit vectors.
5241 if (!SVOp->getSimpleValueType(0).is128BitVector())
5244 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5245 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5251 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5253 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5254 unsigned NumNonZero, unsigned NumZero,
5256 const X86Subtarget* Subtarget,
5257 const TargetLowering &TLI) {
5264 for (unsigned i = 0; i < 16; ++i) {
5265 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5266 if (ThisIsNonZero && First) {
5268 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5270 V = DAG.getUNDEF(MVT::v8i16);
5275 SDValue ThisElt(0, 0), LastElt(0, 0);
5276 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5277 if (LastIsNonZero) {
5278 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5279 MVT::i16, Op.getOperand(i-1));
5281 if (ThisIsNonZero) {
5282 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5283 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5284 ThisElt, DAG.getConstant(8, MVT::i8));
5286 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5290 if (ThisElt.getNode())
5291 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5292 DAG.getIntPtrConstant(i/2));
5296 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5299 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5301 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5302 unsigned NumNonZero, unsigned NumZero,
5304 const X86Subtarget* Subtarget,
5305 const TargetLowering &TLI) {
5312 for (unsigned i = 0; i < 8; ++i) {
5313 bool isNonZero = (NonZeros & (1 << i)) != 0;
5317 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5319 V = DAG.getUNDEF(MVT::v8i16);
5322 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5323 MVT::v8i16, V, Op.getOperand(i),
5324 DAG.getIntPtrConstant(i));
5331 /// getVShift - Return a vector logical shift node.
5333 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5334 unsigned NumBits, SelectionDAG &DAG,
5335 const TargetLowering &TLI, SDLoc dl) {
5336 assert(VT.is128BitVector() && "Unknown type for VShift");
5337 EVT ShVT = MVT::v2i64;
5338 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5339 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5340 return DAG.getNode(ISD::BITCAST, dl, VT,
5341 DAG.getNode(Opc, dl, ShVT, SrcOp,
5342 DAG.getConstant(NumBits,
5343 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5347 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5349 // Check if the scalar load can be widened into a vector load. And if
5350 // the address is "base + cst" see if the cst can be "absorbed" into
5351 // the shuffle mask.
5352 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5353 SDValue Ptr = LD->getBasePtr();
5354 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5356 EVT PVT = LD->getValueType(0);
5357 if (PVT != MVT::i32 && PVT != MVT::f32)
5362 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5363 FI = FINode->getIndex();
5365 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5366 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5367 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5368 Offset = Ptr.getConstantOperandVal(1);
5369 Ptr = Ptr.getOperand(0);
5374 // FIXME: 256-bit vector instructions don't require a strict alignment,
5375 // improve this code to support it better.
5376 unsigned RequiredAlign = VT.getSizeInBits()/8;
5377 SDValue Chain = LD->getChain();
5378 // Make sure the stack object alignment is at least 16 or 32.
5379 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5380 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5381 if (MFI->isFixedObjectIndex(FI)) {
5382 // Can't change the alignment. FIXME: It's possible to compute
5383 // the exact stack offset and reference FI + adjust offset instead.
5384 // If someone *really* cares about this. That's the way to implement it.
5387 MFI->setObjectAlignment(FI, RequiredAlign);
5391 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5392 // Ptr + (Offset & ~15).
5395 if ((Offset % RequiredAlign) & 3)
5397 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5399 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5400 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5402 int EltNo = (Offset - StartOffset) >> 2;
5403 unsigned NumElems = VT.getVectorNumElements();
5405 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5406 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5407 LD->getPointerInfo().getWithOffset(StartOffset),
5408 false, false, false, 0);
5410 SmallVector<int, 8> Mask;
5411 for (unsigned i = 0; i != NumElems; ++i)
5412 Mask.push_back(EltNo);
5414 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5420 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5421 /// vector of type 'VT', see if the elements can be replaced by a single large
5422 /// load which has the same value as a build_vector whose operands are 'elts'.
5424 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5426 /// FIXME: we'd also like to handle the case where the last elements are zero
5427 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5428 /// There's even a handy isZeroNode for that purpose.
5429 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5430 SDLoc &DL, SelectionDAG &DAG,
5431 bool isAfterLegalize) {
5432 EVT EltVT = VT.getVectorElementType();
5433 unsigned NumElems = Elts.size();
5435 LoadSDNode *LDBase = NULL;
5436 unsigned LastLoadedElt = -1U;
5438 // For each element in the initializer, see if we've found a load or an undef.
5439 // If we don't find an initial load element, or later load elements are
5440 // non-consecutive, bail out.
5441 for (unsigned i = 0; i < NumElems; ++i) {
5442 SDValue Elt = Elts[i];
5444 if (!Elt.getNode() ||
5445 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5448 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5450 LDBase = cast<LoadSDNode>(Elt.getNode());
5454 if (Elt.getOpcode() == ISD::UNDEF)
5457 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5458 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5463 // If we have found an entire vector of loads and undefs, then return a large
5464 // load of the entire vector width starting at the base pointer. If we found
5465 // consecutive loads for the low half, generate a vzext_load node.
5466 if (LastLoadedElt == NumElems - 1) {
5468 if (isAfterLegalize &&
5469 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5472 SDValue NewLd = SDValue();
5474 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5475 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5476 LDBase->getPointerInfo(),
5477 LDBase->isVolatile(), LDBase->isNonTemporal(),
5478 LDBase->isInvariant(), 0);
5479 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5480 LDBase->getPointerInfo(),
5481 LDBase->isVolatile(), LDBase->isNonTemporal(),
5482 LDBase->isInvariant(), LDBase->getAlignment());
5484 if (LDBase->hasAnyUseOfValue(1)) {
5485 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5487 SDValue(NewLd.getNode(), 1));
5488 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5489 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5490 SDValue(NewLd.getNode(), 1));
5495 if (NumElems == 4 && LastLoadedElt == 1 &&
5496 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5497 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5498 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5500 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5501 array_lengthof(Ops), MVT::i64,
5502 LDBase->getPointerInfo(),
5503 LDBase->getAlignment(),
5504 false/*isVolatile*/, true/*ReadMem*/,
5507 // Make sure the newly-created LOAD is in the same position as LDBase in
5508 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5509 // update uses of LDBase's output chain to use the TokenFactor.
5510 if (LDBase->hasAnyUseOfValue(1)) {
5511 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5512 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5513 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5514 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5515 SDValue(ResNode.getNode(), 1));
5518 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5523 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5524 /// to generate a splat value for the following cases:
5525 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5526 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5527 /// a scalar load, or a constant.
5528 /// The VBROADCAST node is returned when a pattern is found,
5529 /// or SDValue() otherwise.
5530 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5531 SelectionDAG &DAG) {
5532 if (!Subtarget->hasFp256())
5535 MVT VT = Op.getSimpleValueType();
5538 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5539 "Unsupported vector type for broadcast.");
5544 switch (Op.getOpcode()) {
5546 // Unknown pattern found.
5549 case ISD::BUILD_VECTOR: {
5550 // The BUILD_VECTOR node must be a splat.
5551 if (!isSplatVector(Op.getNode()))
5554 Ld = Op.getOperand(0);
5555 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5556 Ld.getOpcode() == ISD::ConstantFP);
5558 // The suspected load node has several users. Make sure that all
5559 // of its users are from the BUILD_VECTOR node.
5560 // Constants may have multiple users.
5561 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5566 case ISD::VECTOR_SHUFFLE: {
5567 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5569 // Shuffles must have a splat mask where the first element is
5571 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5574 SDValue Sc = Op.getOperand(0);
5575 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5576 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5578 if (!Subtarget->hasInt256())
5581 // Use the register form of the broadcast instruction available on AVX2.
5582 if (VT.getSizeInBits() >= 256)
5583 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5584 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5587 Ld = Sc.getOperand(0);
5588 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5589 Ld.getOpcode() == ISD::ConstantFP);
5591 // The scalar_to_vector node and the suspected
5592 // load node must have exactly one user.
5593 // Constants may have multiple users.
5595 // AVX-512 has register version of the broadcast
5596 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5597 Ld.getValueType().getSizeInBits() >= 32;
5598 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5605 bool IsGE256 = (VT.getSizeInBits() >= 256);
5607 // Handle the broadcasting a single constant scalar from the constant pool
5608 // into a vector. On Sandybridge it is still better to load a constant vector
5609 // from the constant pool and not to broadcast it from a scalar.
5610 if (ConstSplatVal && Subtarget->hasInt256()) {
5611 EVT CVT = Ld.getValueType();
5612 assert(!CVT.isVector() && "Must not broadcast a vector type");
5613 unsigned ScalarSize = CVT.getSizeInBits();
5615 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5616 const Constant *C = 0;
5617 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5618 C = CI->getConstantIntValue();
5619 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5620 C = CF->getConstantFPValue();
5622 assert(C && "Invalid constant type");
5624 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5625 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5626 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5627 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5628 MachinePointerInfo::getConstantPool(),
5629 false, false, false, Alignment);
5631 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5635 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5636 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5638 // Handle AVX2 in-register broadcasts.
5639 if (!IsLoad && Subtarget->hasInt256() &&
5640 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5641 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5643 // The scalar source must be a normal load.
5647 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5648 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5650 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5651 // double since there is no vbroadcastsd xmm
5652 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5653 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5654 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5657 // Unsupported broadcast.
5661 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5662 MVT VT = Op.getSimpleValueType();
5664 // Skip if insert_vec_elt is not supported.
5665 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5666 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5670 unsigned NumElems = Op.getNumOperands();
5674 SmallVector<unsigned, 4> InsertIndices;
5675 SmallVector<int, 8> Mask(NumElems, -1);
5677 for (unsigned i = 0; i != NumElems; ++i) {
5678 unsigned Opc = Op.getOperand(i).getOpcode();
5680 if (Opc == ISD::UNDEF)
5683 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5684 // Quit if more than 1 elements need inserting.
5685 if (InsertIndices.size() > 1)
5688 InsertIndices.push_back(i);
5692 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5693 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5695 // Quit if extracted from vector of different type.
5696 if (ExtractedFromVec.getValueType() != VT)
5699 // Quit if non-constant index.
5700 if (!isa<ConstantSDNode>(ExtIdx))
5703 if (VecIn1.getNode() == 0)
5704 VecIn1 = ExtractedFromVec;
5705 else if (VecIn1 != ExtractedFromVec) {
5706 if (VecIn2.getNode() == 0)
5707 VecIn2 = ExtractedFromVec;
5708 else if (VecIn2 != ExtractedFromVec)
5709 // Quit if more than 2 vectors to shuffle
5713 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5715 if (ExtractedFromVec == VecIn1)
5717 else if (ExtractedFromVec == VecIn2)
5718 Mask[i] = Idx + NumElems;
5721 if (VecIn1.getNode() == 0)
5724 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5725 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5726 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5727 unsigned Idx = InsertIndices[i];
5728 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5729 DAG.getIntPtrConstant(Idx));
5735 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5737 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5739 MVT VT = Op.getSimpleValueType();
5740 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5741 "Unexpected type in LowerBUILD_VECTORvXi1!");
5744 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5745 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5746 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5747 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5748 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5749 Ops, VT.getVectorNumElements());
5752 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5753 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5754 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5755 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5756 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5757 Ops, VT.getVectorNumElements());
5760 bool AllContants = true;
5761 uint64_t Immediate = 0;
5762 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5763 SDValue In = Op.getOperand(idx);
5764 if (In.getOpcode() == ISD::UNDEF)
5766 if (!isa<ConstantSDNode>(In)) {
5767 AllContants = false;
5770 if (cast<ConstantSDNode>(In)->getZExtValue())
5771 Immediate |= (1ULL << idx);
5775 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5776 DAG.getConstant(Immediate, MVT::i16));
5777 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5778 DAG.getIntPtrConstant(0));
5781 // Splat vector (with undefs)
5782 SDValue In = Op.getOperand(0);
5783 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5784 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5785 llvm_unreachable("Unsupported predicate operation");
5788 SDValue EFLAGS, X86CC;
5789 if (In.getOpcode() == ISD::SETCC) {
5790 SDValue Op0 = In.getOperand(0);
5791 SDValue Op1 = In.getOperand(1);
5792 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5793 bool isFP = Op1.getValueType().isFloatingPoint();
5794 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5796 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5798 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5799 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5800 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5801 } else if (In.getOpcode() == X86ISD::SETCC) {
5802 X86CC = In.getOperand(0);
5803 EFLAGS = In.getOperand(1);
5812 // res = allOnes ### CMOVNE -1, %res
5815 MVT InVT = In.getSimpleValueType();
5816 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5817 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5818 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5821 if (VT == MVT::v16i1) {
5822 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5823 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5824 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5825 Cst0, Cst1, X86CC, EFLAGS);
5826 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5829 if (VT == MVT::v8i1) {
5830 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5831 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5832 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5833 Cst0, Cst1, X86CC, EFLAGS);
5834 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5835 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5837 llvm_unreachable("Unsupported predicate operation");
5841 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5844 MVT VT = Op.getSimpleValueType();
5845 MVT ExtVT = VT.getVectorElementType();
5846 unsigned NumElems = Op.getNumOperands();
5848 // Generate vectors for predicate vectors.
5849 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5850 return LowerBUILD_VECTORvXi1(Op, DAG);
5852 // Vectors containing all zeros can be matched by pxor and xorps later
5853 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5854 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5855 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5856 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5859 return getZeroVector(VT, Subtarget, DAG, dl);
5862 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5863 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5864 // vpcmpeqd on 256-bit vectors.
5865 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5866 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5869 if (!VT.is512BitVector())
5870 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5873 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5874 if (Broadcast.getNode())
5877 unsigned EVTBits = ExtVT.getSizeInBits();
5879 unsigned NumZero = 0;
5880 unsigned NumNonZero = 0;
5881 unsigned NonZeros = 0;
5882 bool IsAllConstants = true;
5883 SmallSet<SDValue, 8> Values;
5884 for (unsigned i = 0; i < NumElems; ++i) {
5885 SDValue Elt = Op.getOperand(i);
5886 if (Elt.getOpcode() == ISD::UNDEF)
5889 if (Elt.getOpcode() != ISD::Constant &&
5890 Elt.getOpcode() != ISD::ConstantFP)
5891 IsAllConstants = false;
5892 if (X86::isZeroNode(Elt))
5895 NonZeros |= (1 << i);
5900 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5901 if (NumNonZero == 0)
5902 return DAG.getUNDEF(VT);
5904 // Special case for single non-zero, non-undef, element.
5905 if (NumNonZero == 1) {
5906 unsigned Idx = countTrailingZeros(NonZeros);
5907 SDValue Item = Op.getOperand(Idx);
5909 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5910 // the value are obviously zero, truncate the value to i32 and do the
5911 // insertion that way. Only do this if the value is non-constant or if the
5912 // value is a constant being inserted into element 0. It is cheaper to do
5913 // a constant pool load than it is to do a movd + shuffle.
5914 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5915 (!IsAllConstants || Idx == 0)) {
5916 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5918 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5919 EVT VecVT = MVT::v4i32;
5920 unsigned VecElts = 4;
5922 // Truncate the value (which may itself be a constant) to i32, and
5923 // convert it to a vector with movd (S2V+shuffle to zero extend).
5924 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5925 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5926 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5928 // Now we have our 32-bit value zero extended in the low element of
5929 // a vector. If Idx != 0, swizzle it into place.
5931 SmallVector<int, 4> Mask;
5932 Mask.push_back(Idx);
5933 for (unsigned i = 1; i != VecElts; ++i)
5935 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5938 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5942 // If we have a constant or non-constant insertion into the low element of
5943 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5944 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5945 // depending on what the source datatype is.
5948 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5950 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5951 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5952 if (VT.is256BitVector() || VT.is512BitVector()) {
5953 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5954 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5955 Item, DAG.getIntPtrConstant(0));
5957 assert(VT.is128BitVector() && "Expected an SSE value type!");
5958 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5959 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5960 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5963 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5964 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5965 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5966 if (VT.is256BitVector()) {
5967 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5968 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5970 assert(VT.is128BitVector() && "Expected an SSE value type!");
5971 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5973 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5977 // Is it a vector logical left shift?
5978 if (NumElems == 2 && Idx == 1 &&
5979 X86::isZeroNode(Op.getOperand(0)) &&
5980 !X86::isZeroNode(Op.getOperand(1))) {
5981 unsigned NumBits = VT.getSizeInBits();
5982 return getVShift(true, VT,
5983 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5984 VT, Op.getOperand(1)),
5985 NumBits/2, DAG, *this, dl);
5988 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5991 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5992 // is a non-constant being inserted into an element other than the low one,
5993 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5994 // movd/movss) to move this into the low element, then shuffle it into
5996 if (EVTBits == 32) {
5997 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5999 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6000 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6001 SmallVector<int, 8> MaskVec;
6002 for (unsigned i = 0; i != NumElems; ++i)
6003 MaskVec.push_back(i == Idx ? 0 : 1);
6004 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6008 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6009 if (Values.size() == 1) {
6010 if (EVTBits == 32) {
6011 // Instead of a shuffle like this:
6012 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6013 // Check if it's possible to issue this instead.
6014 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6015 unsigned Idx = countTrailingZeros(NonZeros);
6016 SDValue Item = Op.getOperand(Idx);
6017 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6018 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6023 // A vector full of immediates; various special cases are already
6024 // handled, so this is best done with a single constant-pool load.
6028 // For AVX-length vectors, build the individual 128-bit pieces and use
6029 // shuffles to put them in place.
6030 if (VT.is256BitVector()) {
6031 SmallVector<SDValue, 32> V;
6032 for (unsigned i = 0; i != NumElems; ++i)
6033 V.push_back(Op.getOperand(i));
6035 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6037 // Build both the lower and upper subvector.
6038 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6039 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6042 // Recreate the wider vector with the lower and upper part.
6043 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6046 // Let legalizer expand 2-wide build_vectors.
6047 if (EVTBits == 64) {
6048 if (NumNonZero == 1) {
6049 // One half is zero or undef.
6050 unsigned Idx = countTrailingZeros(NonZeros);
6051 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6052 Op.getOperand(Idx));
6053 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6058 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6059 if (EVTBits == 8 && NumElems == 16) {
6060 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6062 if (V.getNode()) return V;
6065 if (EVTBits == 16 && NumElems == 8) {
6066 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6068 if (V.getNode()) return V;
6071 // If element VT is == 32 bits, turn it into a number of shuffles.
6072 SmallVector<SDValue, 8> V(NumElems);
6073 if (NumElems == 4 && NumZero > 0) {
6074 for (unsigned i = 0; i < 4; ++i) {
6075 bool isZero = !(NonZeros & (1 << i));
6077 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6079 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6082 for (unsigned i = 0; i < 2; ++i) {
6083 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6086 V[i] = V[i*2]; // Must be a zero vector.
6089 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6092 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6095 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6100 bool Reverse1 = (NonZeros & 0x3) == 2;
6101 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6105 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6106 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6108 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6111 if (Values.size() > 1 && VT.is128BitVector()) {
6112 // Check for a build vector of consecutive loads.
6113 for (unsigned i = 0; i < NumElems; ++i)
6114 V[i] = Op.getOperand(i);
6116 // Check for elements which are consecutive loads.
6117 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6121 // Check for a build vector from mostly shuffle plus few inserting.
6122 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6126 // For SSE 4.1, use insertps to put the high elements into the low element.
6127 if (getSubtarget()->hasSSE41()) {
6129 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6130 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6132 Result = DAG.getUNDEF(VT);
6134 for (unsigned i = 1; i < NumElems; ++i) {
6135 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6136 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6137 Op.getOperand(i), DAG.getIntPtrConstant(i));
6142 // Otherwise, expand into a number of unpckl*, start by extending each of
6143 // our (non-undef) elements to the full vector width with the element in the
6144 // bottom slot of the vector (which generates no code for SSE).
6145 for (unsigned i = 0; i < NumElems; ++i) {
6146 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6147 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6149 V[i] = DAG.getUNDEF(VT);
6152 // Next, we iteratively mix elements, e.g. for v4f32:
6153 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6154 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6155 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6156 unsigned EltStride = NumElems >> 1;
6157 while (EltStride != 0) {
6158 for (unsigned i = 0; i < EltStride; ++i) {
6159 // If V[i+EltStride] is undef and this is the first round of mixing,
6160 // then it is safe to just drop this shuffle: V[i] is already in the
6161 // right place, the one element (since it's the first round) being
6162 // inserted as undef can be dropped. This isn't safe for successive
6163 // rounds because they will permute elements within both vectors.
6164 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6165 EltStride == NumElems/2)
6168 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6177 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6178 // to create 256-bit vectors from two other 128-bit ones.
6179 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6181 MVT ResVT = Op.getSimpleValueType();
6183 assert((ResVT.is256BitVector() ||
6184 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6186 SDValue V1 = Op.getOperand(0);
6187 SDValue V2 = Op.getOperand(1);
6188 unsigned NumElems = ResVT.getVectorNumElements();
6189 if(ResVT.is256BitVector())
6190 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6192 if (Op.getNumOperands() == 4) {
6193 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6194 ResVT.getVectorNumElements()/2);
6195 SDValue V3 = Op.getOperand(2);
6196 SDValue V4 = Op.getOperand(3);
6197 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6198 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6200 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6203 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6204 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6205 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6206 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6207 Op.getNumOperands() == 4)));
6209 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6210 // from two other 128-bit ones.
6212 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6213 return LowerAVXCONCAT_VECTORS(Op, DAG);
6216 // Try to lower a shuffle node into a simple blend instruction.
6218 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6219 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6220 SDValue V1 = SVOp->getOperand(0);
6221 SDValue V2 = SVOp->getOperand(1);
6223 MVT VT = SVOp->getSimpleValueType(0);
6224 MVT EltVT = VT.getVectorElementType();
6225 unsigned NumElems = VT.getVectorNumElements();
6227 // There is no blend with immediate in AVX-512.
6228 if (VT.is512BitVector())
6231 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6233 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6236 // Check the mask for BLEND and build the value.
6237 unsigned MaskValue = 0;
6238 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6239 unsigned NumLanes = (NumElems-1)/8 + 1;
6240 unsigned NumElemsInLane = NumElems / NumLanes;
6242 // Blend for v16i16 should be symetric for the both lanes.
6243 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6245 int SndLaneEltIdx = (NumLanes == 2) ?
6246 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6247 int EltIdx = SVOp->getMaskElt(i);
6249 if ((EltIdx < 0 || EltIdx == (int)i) &&
6250 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6253 if (((unsigned)EltIdx == (i + NumElems)) &&
6254 (SndLaneEltIdx < 0 ||
6255 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6256 MaskValue |= (1<<i);
6261 // Convert i32 vectors to floating point if it is not AVX2.
6262 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6264 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6265 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6267 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6268 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6271 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6272 DAG.getConstant(MaskValue, MVT::i32));
6273 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6276 // v8i16 shuffles - Prefer shuffles in the following order:
6277 // 1. [all] pshuflw, pshufhw, optional move
6278 // 2. [ssse3] 1 x pshufb
6279 // 3. [ssse3] 2 x pshufb + 1 x por
6280 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6282 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6283 SelectionDAG &DAG) {
6284 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6285 SDValue V1 = SVOp->getOperand(0);
6286 SDValue V2 = SVOp->getOperand(1);
6288 SmallVector<int, 8> MaskVals;
6290 // Determine if more than 1 of the words in each of the low and high quadwords
6291 // of the result come from the same quadword of one of the two inputs. Undef
6292 // mask values count as coming from any quadword, for better codegen.
6293 unsigned LoQuad[] = { 0, 0, 0, 0 };
6294 unsigned HiQuad[] = { 0, 0, 0, 0 };
6295 std::bitset<4> InputQuads;
6296 for (unsigned i = 0; i < 8; ++i) {
6297 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6298 int EltIdx = SVOp->getMaskElt(i);
6299 MaskVals.push_back(EltIdx);
6308 InputQuads.set(EltIdx / 4);
6311 int BestLoQuad = -1;
6312 unsigned MaxQuad = 1;
6313 for (unsigned i = 0; i < 4; ++i) {
6314 if (LoQuad[i] > MaxQuad) {
6316 MaxQuad = LoQuad[i];
6320 int BestHiQuad = -1;
6322 for (unsigned i = 0; i < 4; ++i) {
6323 if (HiQuad[i] > MaxQuad) {
6325 MaxQuad = HiQuad[i];
6329 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6330 // of the two input vectors, shuffle them into one input vector so only a
6331 // single pshufb instruction is necessary. If There are more than 2 input
6332 // quads, disable the next transformation since it does not help SSSE3.
6333 bool V1Used = InputQuads[0] || InputQuads[1];
6334 bool V2Used = InputQuads[2] || InputQuads[3];
6335 if (Subtarget->hasSSSE3()) {
6336 if (InputQuads.count() == 2 && V1Used && V2Used) {
6337 BestLoQuad = InputQuads[0] ? 0 : 1;
6338 BestHiQuad = InputQuads[2] ? 2 : 3;
6340 if (InputQuads.count() > 2) {
6346 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6347 // the shuffle mask. If a quad is scored as -1, that means that it contains
6348 // words from all 4 input quadwords.
6350 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6352 BestLoQuad < 0 ? 0 : BestLoQuad,
6353 BestHiQuad < 0 ? 1 : BestHiQuad
6355 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6356 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6357 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6358 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6360 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6361 // source words for the shuffle, to aid later transformations.
6362 bool AllWordsInNewV = true;
6363 bool InOrder[2] = { true, true };
6364 for (unsigned i = 0; i != 8; ++i) {
6365 int idx = MaskVals[i];
6367 InOrder[i/4] = false;
6368 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6370 AllWordsInNewV = false;
6374 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6375 if (AllWordsInNewV) {
6376 for (int i = 0; i != 8; ++i) {
6377 int idx = MaskVals[i];
6380 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6381 if ((idx != i) && idx < 4)
6383 if ((idx != i) && idx > 3)
6392 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6393 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6394 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6395 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6396 unsigned TargetMask = 0;
6397 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6398 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6399 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6400 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6401 getShufflePSHUFLWImmediate(SVOp);
6402 V1 = NewV.getOperand(0);
6403 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6407 // Promote splats to a larger type which usually leads to more efficient code.
6408 // FIXME: Is this true if pshufb is available?
6409 if (SVOp->isSplat())
6410 return PromoteSplat(SVOp, DAG);
6412 // If we have SSSE3, and all words of the result are from 1 input vector,
6413 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6414 // is present, fall back to case 4.
6415 if (Subtarget->hasSSSE3()) {
6416 SmallVector<SDValue,16> pshufbMask;
6418 // If we have elements from both input vectors, set the high bit of the
6419 // shuffle mask element to zero out elements that come from V2 in the V1
6420 // mask, and elements that come from V1 in the V2 mask, so that the two
6421 // results can be OR'd together.
6422 bool TwoInputs = V1Used && V2Used;
6423 for (unsigned i = 0; i != 8; ++i) {
6424 int EltIdx = MaskVals[i] * 2;
6425 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6426 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6427 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6428 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6430 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6431 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6432 DAG.getNode(ISD::BUILD_VECTOR, dl,
6433 MVT::v16i8, &pshufbMask[0], 16));
6435 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6437 // Calculate the shuffle mask for the second input, shuffle it, and
6438 // OR it with the first shuffled input.
6440 for (unsigned i = 0; i != 8; ++i) {
6441 int EltIdx = MaskVals[i] * 2;
6442 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6443 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6444 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6445 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6447 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6448 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6449 DAG.getNode(ISD::BUILD_VECTOR, dl,
6450 MVT::v16i8, &pshufbMask[0], 16));
6451 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6452 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6455 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6456 // and update MaskVals with new element order.
6457 std::bitset<8> InOrder;
6458 if (BestLoQuad >= 0) {
6459 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6460 for (int i = 0; i != 4; ++i) {
6461 int idx = MaskVals[i];
6464 } else if ((idx / 4) == BestLoQuad) {
6469 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6472 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6473 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6474 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6476 getShufflePSHUFLWImmediate(SVOp), DAG);
6480 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6481 // and update MaskVals with the new element order.
6482 if (BestHiQuad >= 0) {
6483 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6484 for (unsigned i = 4; i != 8; ++i) {
6485 int idx = MaskVals[i];
6488 } else if ((idx / 4) == BestHiQuad) {
6489 MaskV[i] = (idx & 3) + 4;
6493 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6496 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6498 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6500 getShufflePSHUFHWImmediate(SVOp), DAG);
6504 // In case BestHi & BestLo were both -1, which means each quadword has a word
6505 // from each of the four input quadwords, calculate the InOrder bitvector now
6506 // before falling through to the insert/extract cleanup.
6507 if (BestLoQuad == -1 && BestHiQuad == -1) {
6509 for (int i = 0; i != 8; ++i)
6510 if (MaskVals[i] < 0 || MaskVals[i] == i)
6514 // The other elements are put in the right place using pextrw and pinsrw.
6515 for (unsigned i = 0; i != 8; ++i) {
6518 int EltIdx = MaskVals[i];
6521 SDValue ExtOp = (EltIdx < 8) ?
6522 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6523 DAG.getIntPtrConstant(EltIdx)) :
6524 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6525 DAG.getIntPtrConstant(EltIdx - 8));
6526 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6527 DAG.getIntPtrConstant(i));
6532 // v16i8 shuffles - Prefer shuffles in the following order:
6533 // 1. [ssse3] 1 x pshufb
6534 // 2. [ssse3] 2 x pshufb + 1 x por
6535 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6536 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6537 const X86Subtarget* Subtarget,
6538 SelectionDAG &DAG) {
6539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6540 SDValue V1 = SVOp->getOperand(0);
6541 SDValue V2 = SVOp->getOperand(1);
6543 ArrayRef<int> MaskVals = SVOp->getMask();
6545 // Promote splats to a larger type which usually leads to more efficient code.
6546 // FIXME: Is this true if pshufb is available?
6547 if (SVOp->isSplat())
6548 return PromoteSplat(SVOp, DAG);
6550 // If we have SSSE3, case 1 is generated when all result bytes come from
6551 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6552 // present, fall back to case 3.
6554 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6555 if (Subtarget->hasSSSE3()) {
6556 SmallVector<SDValue,16> pshufbMask;
6558 // If all result elements are from one input vector, then only translate
6559 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6561 // Otherwise, we have elements from both input vectors, and must zero out
6562 // elements that come from V2 in the first mask, and V1 in the second mask
6563 // so that we can OR them together.
6564 for (unsigned i = 0; i != 16; ++i) {
6565 int EltIdx = MaskVals[i];
6566 if (EltIdx < 0 || EltIdx >= 16)
6568 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6570 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6571 DAG.getNode(ISD::BUILD_VECTOR, dl,
6572 MVT::v16i8, &pshufbMask[0], 16));
6574 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6575 // the 2nd operand if it's undefined or zero.
6576 if (V2.getOpcode() == ISD::UNDEF ||
6577 ISD::isBuildVectorAllZeros(V2.getNode()))
6580 // Calculate the shuffle mask for the second input, shuffle it, and
6581 // OR it with the first shuffled input.
6583 for (unsigned i = 0; i != 16; ++i) {
6584 int EltIdx = MaskVals[i];
6585 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6586 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6588 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6589 DAG.getNode(ISD::BUILD_VECTOR, dl,
6590 MVT::v16i8, &pshufbMask[0], 16));
6591 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6594 // No SSSE3 - Calculate in place words and then fix all out of place words
6595 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6596 // the 16 different words that comprise the two doublequadword input vectors.
6597 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6598 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6600 for (int i = 0; i != 8; ++i) {
6601 int Elt0 = MaskVals[i*2];
6602 int Elt1 = MaskVals[i*2+1];
6604 // This word of the result is all undef, skip it.
6605 if (Elt0 < 0 && Elt1 < 0)
6608 // This word of the result is already in the correct place, skip it.
6609 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6612 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6613 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6616 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6617 // using a single extract together, load it and store it.
6618 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6619 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6620 DAG.getIntPtrConstant(Elt1 / 2));
6621 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6622 DAG.getIntPtrConstant(i));
6626 // If Elt1 is defined, extract it from the appropriate source. If the
6627 // source byte is not also odd, shift the extracted word left 8 bits
6628 // otherwise clear the bottom 8 bits if we need to do an or.
6630 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6631 DAG.getIntPtrConstant(Elt1 / 2));
6632 if ((Elt1 & 1) == 0)
6633 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6635 TLI.getShiftAmountTy(InsElt.getValueType())));
6637 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6638 DAG.getConstant(0xFF00, MVT::i16));
6640 // If Elt0 is defined, extract it from the appropriate source. If the
6641 // source byte is not also even, shift the extracted word right 8 bits. If
6642 // Elt1 was also defined, OR the extracted values together before
6643 // inserting them in the result.
6645 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6646 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6647 if ((Elt0 & 1) != 0)
6648 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6650 TLI.getShiftAmountTy(InsElt0.getValueType())));
6652 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6653 DAG.getConstant(0x00FF, MVT::i16));
6654 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6657 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6658 DAG.getIntPtrConstant(i));
6660 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6663 // v32i8 shuffles - Translate to VPSHUFB if possible.
6665 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6666 const X86Subtarget *Subtarget,
6667 SelectionDAG &DAG) {
6668 MVT VT = SVOp->getSimpleValueType(0);
6669 SDValue V1 = SVOp->getOperand(0);
6670 SDValue V2 = SVOp->getOperand(1);
6672 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6674 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6675 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6676 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6678 // VPSHUFB may be generated if
6679 // (1) one of input vector is undefined or zeroinitializer.
6680 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6681 // And (2) the mask indexes don't cross the 128-bit lane.
6682 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6683 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6686 if (V1IsAllZero && !V2IsAllZero) {
6687 CommuteVectorShuffleMask(MaskVals, 32);
6690 SmallVector<SDValue, 32> pshufbMask;
6691 for (unsigned i = 0; i != 32; i++) {
6692 int EltIdx = MaskVals[i];
6693 if (EltIdx < 0 || EltIdx >= 32)
6696 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6697 // Cross lane is not allowed.
6701 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6703 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6704 DAG.getNode(ISD::BUILD_VECTOR, dl,
6705 MVT::v32i8, &pshufbMask[0], 32));
6708 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6709 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6710 /// done when every pair / quad of shuffle mask elements point to elements in
6711 /// the right sequence. e.g.
6712 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6714 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6715 SelectionDAG &DAG) {
6716 MVT VT = SVOp->getSimpleValueType(0);
6718 unsigned NumElems = VT.getVectorNumElements();
6721 switch (VT.SimpleTy) {
6722 default: llvm_unreachable("Unexpected!");
6723 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6724 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6725 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6726 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6727 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6728 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6731 SmallVector<int, 8> MaskVec;
6732 for (unsigned i = 0; i != NumElems; i += Scale) {
6734 for (unsigned j = 0; j != Scale; ++j) {
6735 int EltIdx = SVOp->getMaskElt(i+j);
6739 StartIdx = (EltIdx / Scale);
6740 if (EltIdx != (int)(StartIdx*Scale + j))
6743 MaskVec.push_back(StartIdx);
6746 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6747 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6748 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6751 /// getVZextMovL - Return a zero-extending vector move low node.
6753 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6754 SDValue SrcOp, SelectionDAG &DAG,
6755 const X86Subtarget *Subtarget, SDLoc dl) {
6756 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6757 LoadSDNode *LD = NULL;
6758 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6759 LD = dyn_cast<LoadSDNode>(SrcOp);
6761 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6763 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6764 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6765 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6766 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6767 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6769 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6770 return DAG.getNode(ISD::BITCAST, dl, VT,
6771 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6772 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6780 return DAG.getNode(ISD::BITCAST, dl, VT,
6781 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6782 DAG.getNode(ISD::BITCAST, dl,
6786 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6787 /// which could not be matched by any known target speficic shuffle
6789 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6791 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6792 if (NewOp.getNode())
6795 MVT VT = SVOp->getSimpleValueType(0);
6797 unsigned NumElems = VT.getVectorNumElements();
6798 unsigned NumLaneElems = NumElems / 2;
6801 MVT EltVT = VT.getVectorElementType();
6802 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6805 SmallVector<int, 16> Mask;
6806 for (unsigned l = 0; l < 2; ++l) {
6807 // Build a shuffle mask for the output, discovering on the fly which
6808 // input vectors to use as shuffle operands (recorded in InputUsed).
6809 // If building a suitable shuffle vector proves too hard, then bail
6810 // out with UseBuildVector set.
6811 bool UseBuildVector = false;
6812 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6813 unsigned LaneStart = l * NumLaneElems;
6814 for (unsigned i = 0; i != NumLaneElems; ++i) {
6815 // The mask element. This indexes into the input.
6816 int Idx = SVOp->getMaskElt(i+LaneStart);
6818 // the mask element does not index into any input vector.
6823 // The input vector this mask element indexes into.
6824 int Input = Idx / NumLaneElems;
6826 // Turn the index into an offset from the start of the input vector.
6827 Idx -= Input * NumLaneElems;
6829 // Find or create a shuffle vector operand to hold this input.
6831 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6832 if (InputUsed[OpNo] == Input)
6833 // This input vector is already an operand.
6835 if (InputUsed[OpNo] < 0) {
6836 // Create a new operand for this input vector.
6837 InputUsed[OpNo] = Input;
6842 if (OpNo >= array_lengthof(InputUsed)) {
6843 // More than two input vectors used! Give up on trying to create a
6844 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6845 UseBuildVector = true;
6849 // Add the mask index for the new shuffle vector.
6850 Mask.push_back(Idx + OpNo * NumLaneElems);
6853 if (UseBuildVector) {
6854 SmallVector<SDValue, 16> SVOps;
6855 for (unsigned i = 0; i != NumLaneElems; ++i) {
6856 // The mask element. This indexes into the input.
6857 int Idx = SVOp->getMaskElt(i+LaneStart);
6859 SVOps.push_back(DAG.getUNDEF(EltVT));
6863 // The input vector this mask element indexes into.
6864 int Input = Idx / NumElems;
6866 // Turn the index into an offset from the start of the input vector.
6867 Idx -= Input * NumElems;
6869 // Extract the vector element by hand.
6870 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6871 SVOp->getOperand(Input),
6872 DAG.getIntPtrConstant(Idx)));
6875 // Construct the output using a BUILD_VECTOR.
6876 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6878 } else if (InputUsed[0] < 0) {
6879 // No input vectors were used! The result is undefined.
6880 Output[l] = DAG.getUNDEF(NVT);
6882 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6883 (InputUsed[0] % 2) * NumLaneElems,
6885 // If only one input was used, use an undefined vector for the other.
6886 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6887 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6888 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6889 // At least one input vector was used. Create a new shuffle vector.
6890 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6896 // Concatenate the result back
6897 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6900 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6901 /// 4 elements, and match them with several different shuffle types.
6903 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6904 SDValue V1 = SVOp->getOperand(0);
6905 SDValue V2 = SVOp->getOperand(1);
6907 MVT VT = SVOp->getSimpleValueType(0);
6909 assert(VT.is128BitVector() && "Unsupported vector size");
6911 std::pair<int, int> Locs[4];
6912 int Mask1[] = { -1, -1, -1, -1 };
6913 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6917 for (unsigned i = 0; i != 4; ++i) {
6918 int Idx = PermMask[i];
6920 Locs[i] = std::make_pair(-1, -1);
6922 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6924 Locs[i] = std::make_pair(0, NumLo);
6928 Locs[i] = std::make_pair(1, NumHi);
6930 Mask1[2+NumHi] = Idx;
6936 if (NumLo <= 2 && NumHi <= 2) {
6937 // If no more than two elements come from either vector. This can be
6938 // implemented with two shuffles. First shuffle gather the elements.
6939 // The second shuffle, which takes the first shuffle as both of its
6940 // vector operands, put the elements into the right order.
6941 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6943 int Mask2[] = { -1, -1, -1, -1 };
6945 for (unsigned i = 0; i != 4; ++i)
6946 if (Locs[i].first != -1) {
6947 unsigned Idx = (i < 2) ? 0 : 4;
6948 Idx += Locs[i].first * 2 + Locs[i].second;
6952 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6955 if (NumLo == 3 || NumHi == 3) {
6956 // Otherwise, we must have three elements from one vector, call it X, and
6957 // one element from the other, call it Y. First, use a shufps to build an
6958 // intermediate vector with the one element from Y and the element from X
6959 // that will be in the same half in the final destination (the indexes don't
6960 // matter). Then, use a shufps to build the final vector, taking the half
6961 // containing the element from Y from the intermediate, and the other half
6964 // Normalize it so the 3 elements come from V1.
6965 CommuteVectorShuffleMask(PermMask, 4);
6969 // Find the element from V2.
6971 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6972 int Val = PermMask[HiIndex];
6979 Mask1[0] = PermMask[HiIndex];
6981 Mask1[2] = PermMask[HiIndex^1];
6983 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6986 Mask1[0] = PermMask[0];
6987 Mask1[1] = PermMask[1];
6988 Mask1[2] = HiIndex & 1 ? 6 : 4;
6989 Mask1[3] = HiIndex & 1 ? 4 : 6;
6990 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6993 Mask1[0] = HiIndex & 1 ? 2 : 0;
6994 Mask1[1] = HiIndex & 1 ? 0 : 2;
6995 Mask1[2] = PermMask[2];
6996 Mask1[3] = PermMask[3];
7001 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7004 // Break it into (shuffle shuffle_hi, shuffle_lo).
7005 int LoMask[] = { -1, -1, -1, -1 };
7006 int HiMask[] = { -1, -1, -1, -1 };
7008 int *MaskPtr = LoMask;
7009 unsigned MaskIdx = 0;
7012 for (unsigned i = 0; i != 4; ++i) {
7019 int Idx = PermMask[i];
7021 Locs[i] = std::make_pair(-1, -1);
7022 } else if (Idx < 4) {
7023 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7024 MaskPtr[LoIdx] = Idx;
7027 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7028 MaskPtr[HiIdx] = Idx;
7033 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7034 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7035 int MaskOps[] = { -1, -1, -1, -1 };
7036 for (unsigned i = 0; i != 4; ++i)
7037 if (Locs[i].first != -1)
7038 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7039 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7042 static bool MayFoldVectorLoad(SDValue V) {
7043 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7044 V = V.getOperand(0);
7046 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7047 V = V.getOperand(0);
7048 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7049 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7050 // BUILD_VECTOR (load), undef
7051 V = V.getOperand(0);
7053 return MayFoldLoad(V);
7057 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7058 MVT VT = Op.getSimpleValueType();
7060 // Canonizalize to v2f64.
7061 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7062 return DAG.getNode(ISD::BITCAST, dl, VT,
7063 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7068 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7070 SDValue V1 = Op.getOperand(0);
7071 SDValue V2 = Op.getOperand(1);
7072 MVT VT = Op.getSimpleValueType();
7074 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7076 if (HasSSE2 && VT == MVT::v2f64)
7077 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7079 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7080 return DAG.getNode(ISD::BITCAST, dl, VT,
7081 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7082 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7083 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7087 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7088 SDValue V1 = Op.getOperand(0);
7089 SDValue V2 = Op.getOperand(1);
7090 MVT VT = Op.getSimpleValueType();
7092 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7093 "unsupported shuffle type");
7095 if (V2.getOpcode() == ISD::UNDEF)
7099 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7103 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7104 SDValue V1 = Op.getOperand(0);
7105 SDValue V2 = Op.getOperand(1);
7106 MVT VT = Op.getSimpleValueType();
7107 unsigned NumElems = VT.getVectorNumElements();
7109 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7110 // operand of these instructions is only memory, so check if there's a
7111 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7113 bool CanFoldLoad = false;
7115 // Trivial case, when V2 comes from a load.
7116 if (MayFoldVectorLoad(V2))
7119 // When V1 is a load, it can be folded later into a store in isel, example:
7120 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7122 // (MOVLPSmr addr:$src1, VR128:$src2)
7123 // So, recognize this potential and also use MOVLPS or MOVLPD
7124 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7127 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7129 if (HasSSE2 && NumElems == 2)
7130 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7133 // If we don't care about the second element, proceed to use movss.
7134 if (SVOp->getMaskElt(1) != -1)
7135 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7138 // movl and movlp will both match v2i64, but v2i64 is never matched by
7139 // movl earlier because we make it strict to avoid messing with the movlp load
7140 // folding logic (see the code above getMOVLP call). Match it here then,
7141 // this is horrible, but will stay like this until we move all shuffle
7142 // matching to x86 specific nodes. Note that for the 1st condition all
7143 // types are matched with movsd.
7145 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7146 // as to remove this logic from here, as much as possible
7147 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7148 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7149 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7152 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7154 // Invert the operand order and use SHUFPS to match it.
7155 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7156 getShuffleSHUFImmediate(SVOp), DAG);
7159 // Reduce a vector shuffle to zext.
7160 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7161 SelectionDAG &DAG) {
7162 // PMOVZX is only available from SSE41.
7163 if (!Subtarget->hasSSE41())
7166 MVT VT = Op.getSimpleValueType();
7168 // Only AVX2 support 256-bit vector integer extending.
7169 if (!Subtarget->hasInt256() && VT.is256BitVector())
7172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7174 SDValue V1 = Op.getOperand(0);
7175 SDValue V2 = Op.getOperand(1);
7176 unsigned NumElems = VT.getVectorNumElements();
7178 // Extending is an unary operation and the element type of the source vector
7179 // won't be equal to or larger than i64.
7180 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7181 VT.getVectorElementType() == MVT::i64)
7184 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7185 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7186 while ((1U << Shift) < NumElems) {
7187 if (SVOp->getMaskElt(1U << Shift) == 1)
7190 // The maximal ratio is 8, i.e. from i8 to i64.
7195 // Check the shuffle mask.
7196 unsigned Mask = (1U << Shift) - 1;
7197 for (unsigned i = 0; i != NumElems; ++i) {
7198 int EltIdx = SVOp->getMaskElt(i);
7199 if ((i & Mask) != 0 && EltIdx != -1)
7201 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7205 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7206 MVT NeVT = MVT::getIntegerVT(NBits);
7207 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7209 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7212 // Simplify the operand as it's prepared to be fed into shuffle.
7213 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7214 if (V1.getOpcode() == ISD::BITCAST &&
7215 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7216 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7217 V1.getOperand(0).getOperand(0)
7218 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7219 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7220 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7221 ConstantSDNode *CIdx =
7222 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7223 // If it's foldable, i.e. normal load with single use, we will let code
7224 // selection to fold it. Otherwise, we will short the conversion sequence.
7225 if (CIdx && CIdx->getZExtValue() == 0 &&
7226 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7227 MVT FullVT = V.getSimpleValueType();
7228 MVT V1VT = V1.getSimpleValueType();
7229 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7230 // The "ext_vec_elt" node is wider than the result node.
7231 // In this case we should extract subvector from V.
7232 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7233 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7234 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7235 FullVT.getVectorNumElements()/Ratio);
7236 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7237 DAG.getIntPtrConstant(0));
7239 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7243 return DAG.getNode(ISD::BITCAST, DL, VT,
7244 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7248 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7249 SelectionDAG &DAG) {
7250 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7251 MVT VT = Op.getSimpleValueType();
7253 SDValue V1 = Op.getOperand(0);
7254 SDValue V2 = Op.getOperand(1);
7256 if (isZeroShuffle(SVOp))
7257 return getZeroVector(VT, Subtarget, DAG, dl);
7259 // Handle splat operations
7260 if (SVOp->isSplat()) {
7261 // Use vbroadcast whenever the splat comes from a foldable load
7262 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7263 if (Broadcast.getNode())
7267 // Check integer expanding shuffles.
7268 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7269 if (NewOp.getNode())
7272 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7274 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7275 VT == MVT::v16i16 || VT == MVT::v32i8) {
7276 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7277 if (NewOp.getNode())
7278 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7279 } else if ((VT == MVT::v4i32 ||
7280 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7281 // FIXME: Figure out a cleaner way to do this.
7282 // Try to make use of movq to zero out the top part.
7283 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7284 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7285 if (NewOp.getNode()) {
7286 MVT NewVT = NewOp.getSimpleValueType();
7287 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7288 NewVT, true, false))
7289 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7290 DAG, Subtarget, dl);
7292 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7293 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7294 if (NewOp.getNode()) {
7295 MVT NewVT = NewOp.getSimpleValueType();
7296 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7297 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7298 DAG, Subtarget, dl);
7306 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7307 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7308 SDValue V1 = Op.getOperand(0);
7309 SDValue V2 = Op.getOperand(1);
7310 MVT VT = Op.getSimpleValueType();
7312 unsigned NumElems = VT.getVectorNumElements();
7313 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7314 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7315 bool V1IsSplat = false;
7316 bool V2IsSplat = false;
7317 bool HasSSE2 = Subtarget->hasSSE2();
7318 bool HasFp256 = Subtarget->hasFp256();
7319 bool HasInt256 = Subtarget->hasInt256();
7320 MachineFunction &MF = DAG.getMachineFunction();
7321 bool OptForSize = MF.getFunction()->getAttributes().
7322 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7324 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7326 if (V1IsUndef && V2IsUndef)
7327 return DAG.getUNDEF(VT);
7329 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7331 // Vector shuffle lowering takes 3 steps:
7333 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7334 // narrowing and commutation of operands should be handled.
7335 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7337 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7338 // so the shuffle can be broken into other shuffles and the legalizer can
7339 // try the lowering again.
7341 // The general idea is that no vector_shuffle operation should be left to
7342 // be matched during isel, all of them must be converted to a target specific
7345 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7346 // narrowing and commutation of operands should be handled. The actual code
7347 // doesn't include all of those, work in progress...
7348 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7349 if (NewOp.getNode())
7352 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7354 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7355 // unpckh_undef). Only use pshufd if speed is more important than size.
7356 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7357 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7358 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7359 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7361 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7362 V2IsUndef && MayFoldVectorLoad(V1))
7363 return getMOVDDup(Op, dl, V1, DAG);
7365 if (isMOVHLPS_v_undef_Mask(M, VT))
7366 return getMOVHighToLow(Op, dl, DAG);
7368 // Use to match splats
7369 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7370 (VT == MVT::v2f64 || VT == MVT::v2i64))
7371 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7373 if (isPSHUFDMask(M, VT)) {
7374 // The actual implementation will match the mask in the if above and then
7375 // during isel it can match several different instructions, not only pshufd
7376 // as its name says, sad but true, emulate the behavior for now...
7377 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7378 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7380 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7382 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7383 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7385 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7386 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7389 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7393 if (isPALIGNRMask(M, VT, Subtarget))
7394 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7395 getShufflePALIGNRImmediate(SVOp),
7398 // Check if this can be converted into a logical shift.
7399 bool isLeft = false;
7402 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7403 if (isShift && ShVal.hasOneUse()) {
7404 // If the shifted value has multiple uses, it may be cheaper to use
7405 // v_set0 + movlhps or movhlps, etc.
7406 MVT EltVT = VT.getVectorElementType();
7407 ShAmt *= EltVT.getSizeInBits();
7408 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7411 if (isMOVLMask(M, VT)) {
7412 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7413 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7414 if (!isMOVLPMask(M, VT)) {
7415 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7416 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7418 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7419 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7423 // FIXME: fold these into legal mask.
7424 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7425 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7427 if (isMOVHLPSMask(M, VT))
7428 return getMOVHighToLow(Op, dl, DAG);
7430 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7431 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7433 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7434 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7436 if (isMOVLPMask(M, VT))
7437 return getMOVLP(Op, dl, DAG, HasSSE2);
7439 if (ShouldXformToMOVHLPS(M, VT) ||
7440 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7441 return CommuteVectorShuffle(SVOp, DAG);
7444 // No better options. Use a vshldq / vsrldq.
7445 MVT EltVT = VT.getVectorElementType();
7446 ShAmt *= EltVT.getSizeInBits();
7447 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7450 bool Commuted = false;
7451 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7452 // 1,1,1,1 -> v8i16 though.
7453 V1IsSplat = isSplatVector(V1.getNode());
7454 V2IsSplat = isSplatVector(V2.getNode());
7456 // Canonicalize the splat or undef, if present, to be on the RHS.
7457 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7458 CommuteVectorShuffleMask(M, NumElems);
7460 std::swap(V1IsSplat, V2IsSplat);
7464 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7465 // Shuffling low element of v1 into undef, just return v1.
7468 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7469 // the instruction selector will not match, so get a canonical MOVL with
7470 // swapped operands to undo the commute.
7471 return getMOVL(DAG, dl, VT, V2, V1);
7474 if (isUNPCKLMask(M, VT, HasInt256))
7475 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7477 if (isUNPCKHMask(M, VT, HasInt256))
7478 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7481 // Normalize mask so all entries that point to V2 points to its first
7482 // element then try to match unpck{h|l} again. If match, return a
7483 // new vector_shuffle with the corrected mask.p
7484 SmallVector<int, 8> NewMask(M.begin(), M.end());
7485 NormalizeMask(NewMask, NumElems);
7486 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7487 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7488 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7489 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7493 // Commute is back and try unpck* again.
7494 // FIXME: this seems wrong.
7495 CommuteVectorShuffleMask(M, NumElems);
7497 std::swap(V1IsSplat, V2IsSplat);
7500 if (isUNPCKLMask(M, VT, HasInt256))
7501 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7503 if (isUNPCKHMask(M, VT, HasInt256))
7504 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7507 // Normalize the node to match x86 shuffle ops if needed
7508 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7509 return CommuteVectorShuffle(SVOp, DAG);
7511 // The checks below are all present in isShuffleMaskLegal, but they are
7512 // inlined here right now to enable us to directly emit target specific
7513 // nodes, and remove one by one until they don't return Op anymore.
7515 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7516 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7517 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7518 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7521 if (isPSHUFHWMask(M, VT, HasInt256))
7522 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7523 getShufflePSHUFHWImmediate(SVOp),
7526 if (isPSHUFLWMask(M, VT, HasInt256))
7527 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7528 getShufflePSHUFLWImmediate(SVOp),
7531 if (isSHUFPMask(M, VT))
7532 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7533 getShuffleSHUFImmediate(SVOp), DAG);
7535 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7536 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7537 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7538 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7540 //===--------------------------------------------------------------------===//
7541 // Generate target specific nodes for 128 or 256-bit shuffles only
7542 // supported in the AVX instruction set.
7545 // Handle VMOVDDUPY permutations
7546 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7547 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7549 // Handle VPERMILPS/D* permutations
7550 if (isVPERMILPMask(M, VT)) {
7551 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7552 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7553 getShuffleSHUFImmediate(SVOp), DAG);
7554 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7555 getShuffleSHUFImmediate(SVOp), DAG);
7558 // Handle VPERM2F128/VPERM2I128 permutations
7559 if (isVPERM2X128Mask(M, VT, HasFp256))
7560 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7561 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7563 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7564 if (BlendOp.getNode())
7568 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7569 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7571 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7572 VT.is512BitVector()) {
7573 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7574 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7575 SmallVector<SDValue, 16> permclMask;
7576 for (unsigned i = 0; i != NumElems; ++i) {
7577 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7580 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7581 &permclMask[0], NumElems);
7583 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7584 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7585 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7586 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7587 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7590 //===--------------------------------------------------------------------===//
7591 // Since no target specific shuffle was selected for this generic one,
7592 // lower it into other known shuffles. FIXME: this isn't true yet, but
7593 // this is the plan.
7596 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7597 if (VT == MVT::v8i16) {
7598 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7599 if (NewOp.getNode())
7603 if (VT == MVT::v16i8) {
7604 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7605 if (NewOp.getNode())
7609 if (VT == MVT::v32i8) {
7610 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7611 if (NewOp.getNode())
7615 // Handle all 128-bit wide vectors with 4 elements, and match them with
7616 // several different shuffle types.
7617 if (NumElems == 4 && VT.is128BitVector())
7618 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7620 // Handle general 256-bit shuffles
7621 if (VT.is256BitVector())
7622 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7627 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7628 MVT VT = Op.getSimpleValueType();
7631 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7634 if (VT.getSizeInBits() == 8) {
7635 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7636 Op.getOperand(0), Op.getOperand(1));
7637 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7638 DAG.getValueType(VT));
7639 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7642 if (VT.getSizeInBits() == 16) {
7643 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7644 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7646 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7647 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7648 DAG.getNode(ISD::BITCAST, dl,
7652 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7653 Op.getOperand(0), Op.getOperand(1));
7654 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7655 DAG.getValueType(VT));
7656 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7659 if (VT == MVT::f32) {
7660 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7661 // the result back to FR32 register. It's only worth matching if the
7662 // result has a single use which is a store or a bitcast to i32. And in
7663 // the case of a store, it's not worth it if the index is a constant 0,
7664 // because a MOVSSmr can be used instead, which is smaller and faster.
7665 if (!Op.hasOneUse())
7667 SDNode *User = *Op.getNode()->use_begin();
7668 if ((User->getOpcode() != ISD::STORE ||
7669 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7670 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7671 (User->getOpcode() != ISD::BITCAST ||
7672 User->getValueType(0) != MVT::i32))
7674 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7675 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7678 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7681 if (VT == MVT::i32 || VT == MVT::i64) {
7682 // ExtractPS/pextrq works with constant index.
7683 if (isa<ConstantSDNode>(Op.getOperand(1)))
7689 /// Extract one bit from mask vector, like v16i1 or v8i1.
7690 /// AVX-512 feature.
7691 static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
7692 SDValue Vec = Op.getOperand(0);
7694 MVT VecVT = Vec.getSimpleValueType();
7695 SDValue Idx = Op.getOperand(1);
7696 MVT EltVT = Op.getSimpleValueType();
7698 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7700 // variable index can't be handled in mask registers,
7701 // extend vector to VR512
7702 if (!isa<ConstantSDNode>(Idx)) {
7703 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7704 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7705 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7706 ExtVT.getVectorElementType(), Ext, Idx);
7707 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7710 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7712 unsigned MaxSift = VecVT.getSizeInBits() - 1;
7713 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7714 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7715 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7716 DAG.getConstant(MaxSift, MVT::i8));
7718 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i1, Vec,
7719 DAG.getIntPtrConstant(0));
7723 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7724 SelectionDAG &DAG) const {
7726 SDValue Vec = Op.getOperand(0);
7727 MVT VecVT = Vec.getSimpleValueType();
7728 SDValue Idx = Op.getOperand(1);
7730 if (Op.getSimpleValueType() == MVT::i1)
7731 return ExtractBitFromMaskVector(Op, DAG);
7733 if (!isa<ConstantSDNode>(Idx)) {
7734 if (VecVT.is512BitVector() ||
7735 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7736 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7739 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7740 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7741 MaskEltVT.getSizeInBits());
7743 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7744 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7745 getZeroVector(MaskVT, Subtarget, DAG, dl),
7746 Idx, DAG.getConstant(0, getPointerTy()));
7747 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7748 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7749 Perm, DAG.getConstant(0, getPointerTy()));
7754 // If this is a 256-bit vector result, first extract the 128-bit vector and
7755 // then extract the element from the 128-bit vector.
7756 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7758 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7759 // Get the 128-bit vector.
7760 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7761 MVT EltVT = VecVT.getVectorElementType();
7763 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7765 //if (IdxVal >= NumElems/2)
7766 // IdxVal -= NumElems/2;
7767 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7768 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7769 DAG.getConstant(IdxVal, MVT::i32));
7772 assert(VecVT.is128BitVector() && "Unexpected vector length");
7774 if (Subtarget->hasSSE41()) {
7775 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7780 MVT VT = Op.getSimpleValueType();
7781 // TODO: handle v16i8.
7782 if (VT.getSizeInBits() == 16) {
7783 SDValue Vec = Op.getOperand(0);
7784 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7786 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7787 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7788 DAG.getNode(ISD::BITCAST, dl,
7791 // Transform it so it match pextrw which produces a 32-bit result.
7792 MVT EltVT = MVT::i32;
7793 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7794 Op.getOperand(0), Op.getOperand(1));
7795 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7796 DAG.getValueType(VT));
7797 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7800 if (VT.getSizeInBits() == 32) {
7801 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7805 // SHUFPS the element to the lowest double word, then movss.
7806 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7807 MVT VVT = Op.getOperand(0).getSimpleValueType();
7808 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7809 DAG.getUNDEF(VVT), Mask);
7810 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7811 DAG.getIntPtrConstant(0));
7814 if (VT.getSizeInBits() == 64) {
7815 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7816 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7817 // to match extract_elt for f64.
7818 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7822 // UNPCKHPD the element to the lowest double word, then movsd.
7823 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7824 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7825 int Mask[2] = { 1, -1 };
7826 MVT VVT = Op.getOperand(0).getSimpleValueType();
7827 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7828 DAG.getUNDEF(VVT), Mask);
7829 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7830 DAG.getIntPtrConstant(0));
7836 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7837 MVT VT = Op.getSimpleValueType();
7838 MVT EltVT = VT.getVectorElementType();
7841 SDValue N0 = Op.getOperand(0);
7842 SDValue N1 = Op.getOperand(1);
7843 SDValue N2 = Op.getOperand(2);
7845 if (!VT.is128BitVector())
7848 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7849 isa<ConstantSDNode>(N2)) {
7851 if (VT == MVT::v8i16)
7852 Opc = X86ISD::PINSRW;
7853 else if (VT == MVT::v16i8)
7854 Opc = X86ISD::PINSRB;
7856 Opc = X86ISD::PINSRB;
7858 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7860 if (N1.getValueType() != MVT::i32)
7861 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7862 if (N2.getValueType() != MVT::i32)
7863 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7864 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7867 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7868 // Bits [7:6] of the constant are the source select. This will always be
7869 // zero here. The DAG Combiner may combine an extract_elt index into these
7870 // bits. For example (insert (extract, 3), 2) could be matched by putting
7871 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7872 // Bits [5:4] of the constant are the destination select. This is the
7873 // value of the incoming immediate.
7874 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7875 // combine either bitwise AND or insert of float 0.0 to set these bits.
7876 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7877 // Create this as a scalar to vector..
7878 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7879 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7882 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7883 // PINSR* works with constant index.
7890 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7891 MVT VT = Op.getSimpleValueType();
7892 MVT EltVT = VT.getVectorElementType();
7895 SDValue N0 = Op.getOperand(0);
7896 SDValue N1 = Op.getOperand(1);
7897 SDValue N2 = Op.getOperand(2);
7899 // If this is a 256-bit vector result, first extract the 128-bit vector,
7900 // insert the element into the extracted half and then place it back.
7901 if (VT.is256BitVector() || VT.is512BitVector()) {
7902 if (!isa<ConstantSDNode>(N2))
7905 // Get the desired 128-bit vector half.
7906 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7907 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7909 // Insert the element into the desired half.
7910 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7911 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7913 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7914 DAG.getConstant(IdxIn128, MVT::i32));
7916 // Insert the changed part back to the 256-bit vector
7917 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7920 if (Subtarget->hasSSE41())
7921 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7923 if (EltVT == MVT::i8)
7926 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7927 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7928 // as its second argument.
7929 if (N1.getValueType() != MVT::i32)
7930 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7931 if (N2.getValueType() != MVT::i32)
7932 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7933 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7938 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7940 MVT OpVT = Op.getSimpleValueType();
7942 // If this is a 256-bit vector result, first insert into a 128-bit
7943 // vector and then insert into the 256-bit vector.
7944 if (!OpVT.is128BitVector()) {
7945 // Insert into a 128-bit vector.
7946 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7947 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7948 OpVT.getVectorNumElements() / SizeFactor);
7950 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7952 // Insert the 128-bit vector.
7953 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7956 if (OpVT == MVT::v1i64 &&
7957 Op.getOperand(0).getValueType() == MVT::i64)
7958 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7960 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7961 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7962 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7963 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7966 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7967 // a simple subregister reference or explicit instructions to grab
7968 // upper bits of a vector.
7969 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7970 SelectionDAG &DAG) {
7972 SDValue In = Op.getOperand(0);
7973 SDValue Idx = Op.getOperand(1);
7974 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7975 MVT ResVT = Op.getSimpleValueType();
7976 MVT InVT = In.getSimpleValueType();
7978 if (Subtarget->hasFp256()) {
7979 if (ResVT.is128BitVector() &&
7980 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7981 isa<ConstantSDNode>(Idx)) {
7982 return Extract128BitVector(In, IdxVal, DAG, dl);
7984 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7985 isa<ConstantSDNode>(Idx)) {
7986 return Extract256BitVector(In, IdxVal, DAG, dl);
7992 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7993 // simple superregister reference or explicit instructions to insert
7994 // the upper bits of a vector.
7995 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7996 SelectionDAG &DAG) {
7997 if (Subtarget->hasFp256()) {
7998 SDLoc dl(Op.getNode());
7999 SDValue Vec = Op.getNode()->getOperand(0);
8000 SDValue SubVec = Op.getNode()->getOperand(1);
8001 SDValue Idx = Op.getNode()->getOperand(2);
8003 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8004 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8005 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8006 isa<ConstantSDNode>(Idx)) {
8007 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8008 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8011 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8012 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8013 isa<ConstantSDNode>(Idx)) {
8014 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8015 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8021 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8022 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8023 // one of the above mentioned nodes. It has to be wrapped because otherwise
8024 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8025 // be used to form addressing mode. These wrapped nodes will be selected
8028 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8029 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8031 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8033 unsigned char OpFlag = 0;
8034 unsigned WrapperKind = X86ISD::Wrapper;
8035 CodeModel::Model M = getTargetMachine().getCodeModel();
8037 if (Subtarget->isPICStyleRIPRel() &&
8038 (M == CodeModel::Small || M == CodeModel::Kernel))
8039 WrapperKind = X86ISD::WrapperRIP;
8040 else if (Subtarget->isPICStyleGOT())
8041 OpFlag = X86II::MO_GOTOFF;
8042 else if (Subtarget->isPICStyleStubPIC())
8043 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8045 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8047 CP->getOffset(), OpFlag);
8049 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8050 // With PIC, the address is actually $g + Offset.
8052 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8053 DAG.getNode(X86ISD::GlobalBaseReg,
8054 SDLoc(), getPointerTy()),
8061 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8062 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8064 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8066 unsigned char OpFlag = 0;
8067 unsigned WrapperKind = X86ISD::Wrapper;
8068 CodeModel::Model M = getTargetMachine().getCodeModel();
8070 if (Subtarget->isPICStyleRIPRel() &&
8071 (M == CodeModel::Small || M == CodeModel::Kernel))
8072 WrapperKind = X86ISD::WrapperRIP;
8073 else if (Subtarget->isPICStyleGOT())
8074 OpFlag = X86II::MO_GOTOFF;
8075 else if (Subtarget->isPICStyleStubPIC())
8076 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8078 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8081 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8083 // With PIC, the address is actually $g + Offset.
8085 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8086 DAG.getNode(X86ISD::GlobalBaseReg,
8087 SDLoc(), getPointerTy()),
8094 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8095 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8097 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8099 unsigned char OpFlag = 0;
8100 unsigned WrapperKind = X86ISD::Wrapper;
8101 CodeModel::Model M = getTargetMachine().getCodeModel();
8103 if (Subtarget->isPICStyleRIPRel() &&
8104 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8105 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8106 OpFlag = X86II::MO_GOTPCREL;
8107 WrapperKind = X86ISD::WrapperRIP;
8108 } else if (Subtarget->isPICStyleGOT()) {
8109 OpFlag = X86II::MO_GOT;
8110 } else if (Subtarget->isPICStyleStubPIC()) {
8111 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8112 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8113 OpFlag = X86II::MO_DARWIN_NONLAZY;
8116 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8119 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8121 // With PIC, the address is actually $g + Offset.
8122 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8123 !Subtarget->is64Bit()) {
8124 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8125 DAG.getNode(X86ISD::GlobalBaseReg,
8126 SDLoc(), getPointerTy()),
8130 // For symbols that require a load from a stub to get the address, emit the
8132 if (isGlobalStubReference(OpFlag))
8133 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8134 MachinePointerInfo::getGOT(), false, false, false, 0);
8140 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8141 // Create the TargetBlockAddressAddress node.
8142 unsigned char OpFlags =
8143 Subtarget->ClassifyBlockAddressReference();
8144 CodeModel::Model M = getTargetMachine().getCodeModel();
8145 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8146 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8148 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8151 if (Subtarget->isPICStyleRIPRel() &&
8152 (M == CodeModel::Small || M == CodeModel::Kernel))
8153 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8155 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8157 // With PIC, the address is actually $g + Offset.
8158 if (isGlobalRelativeToPICBase(OpFlags)) {
8159 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8160 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8168 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8169 int64_t Offset, SelectionDAG &DAG) const {
8170 // Create the TargetGlobalAddress node, folding in the constant
8171 // offset if it is legal.
8172 unsigned char OpFlags =
8173 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8174 CodeModel::Model M = getTargetMachine().getCodeModel();
8176 if (OpFlags == X86II::MO_NO_FLAG &&
8177 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8178 // A direct static reference to a global.
8179 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8182 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8185 if (Subtarget->isPICStyleRIPRel() &&
8186 (M == CodeModel::Small || M == CodeModel::Kernel))
8187 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8189 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8191 // With PIC, the address is actually $g + Offset.
8192 if (isGlobalRelativeToPICBase(OpFlags)) {
8193 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8194 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8198 // For globals that require a load from a stub to get the address, emit the
8200 if (isGlobalStubReference(OpFlags))
8201 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8202 MachinePointerInfo::getGOT(), false, false, false, 0);
8204 // If there was a non-zero offset that we didn't fold, create an explicit
8207 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8208 DAG.getConstant(Offset, getPointerTy()));
8214 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8215 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8216 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8217 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8221 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8222 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8223 unsigned char OperandFlags, bool LocalDynamic = false) {
8224 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8225 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8227 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8228 GA->getValueType(0),
8232 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8236 SDValue Ops[] = { Chain, TGA, *InFlag };
8237 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8239 SDValue Ops[] = { Chain, TGA };
8240 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8243 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8244 MFI->setAdjustsStack(true);
8246 SDValue Flag = Chain.getValue(1);
8247 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8250 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8252 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8255 SDLoc dl(GA); // ? function entry point might be better
8256 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8257 DAG.getNode(X86ISD::GlobalBaseReg,
8258 SDLoc(), PtrVT), InFlag);
8259 InFlag = Chain.getValue(1);
8261 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8264 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8266 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8268 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8269 X86::RAX, X86II::MO_TLSGD);
8272 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8278 // Get the start address of the TLS block for this module.
8279 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8280 .getInfo<X86MachineFunctionInfo>();
8281 MFI->incNumLocalDynamicTLSAccesses();
8285 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8286 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8289 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8290 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8291 InFlag = Chain.getValue(1);
8292 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8293 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8296 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8300 unsigned char OperandFlags = X86II::MO_DTPOFF;
8301 unsigned WrapperKind = X86ISD::Wrapper;
8302 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8303 GA->getValueType(0),
8304 GA->getOffset(), OperandFlags);
8305 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8307 // Add x@dtpoff with the base.
8308 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8311 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8312 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8313 const EVT PtrVT, TLSModel::Model model,
8314 bool is64Bit, bool isPIC) {
8317 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8318 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8319 is64Bit ? 257 : 256));
8321 SDValue ThreadPointer =
8322 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8323 MachinePointerInfo(Ptr), false, false, false, 0);
8325 unsigned char OperandFlags = 0;
8326 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8328 unsigned WrapperKind = X86ISD::Wrapper;
8329 if (model == TLSModel::LocalExec) {
8330 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8331 } else if (model == TLSModel::InitialExec) {
8333 OperandFlags = X86II::MO_GOTTPOFF;
8334 WrapperKind = X86ISD::WrapperRIP;
8336 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8339 llvm_unreachable("Unexpected model");
8342 // emit "addl x@ntpoff,%eax" (local exec)
8343 // or "addl x@indntpoff,%eax" (initial exec)
8344 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8346 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8347 GA->getOffset(), OperandFlags);
8348 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8350 if (model == TLSModel::InitialExec) {
8351 if (isPIC && !is64Bit) {
8352 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8353 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8357 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8358 MachinePointerInfo::getGOT(), false, false, false, 0);
8361 // The address of the thread local variable is the add of the thread
8362 // pointer with the offset of the variable.
8363 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8367 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8369 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8370 const GlobalValue *GV = GA->getGlobal();
8372 if (Subtarget->isTargetELF()) {
8373 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8376 case TLSModel::GeneralDynamic:
8377 if (Subtarget->is64Bit())
8378 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8379 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8380 case TLSModel::LocalDynamic:
8381 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8382 Subtarget->is64Bit());
8383 case TLSModel::InitialExec:
8384 case TLSModel::LocalExec:
8385 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8386 Subtarget->is64Bit(),
8387 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8389 llvm_unreachable("Unknown TLS model.");
8392 if (Subtarget->isTargetDarwin()) {
8393 // Darwin only has one model of TLS. Lower to that.
8394 unsigned char OpFlag = 0;
8395 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8396 X86ISD::WrapperRIP : X86ISD::Wrapper;
8398 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8400 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8401 !Subtarget->is64Bit();
8403 OpFlag = X86II::MO_TLVP_PIC_BASE;
8405 OpFlag = X86II::MO_TLVP;
8407 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8408 GA->getValueType(0),
8409 GA->getOffset(), OpFlag);
8410 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8412 // With PIC32, the address is actually $g + Offset.
8414 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8415 DAG.getNode(X86ISD::GlobalBaseReg,
8416 SDLoc(), getPointerTy()),
8419 // Lowering the machine isd will make sure everything is in the right
8421 SDValue Chain = DAG.getEntryNode();
8422 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8423 SDValue Args[] = { Chain, Offset };
8424 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8426 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8427 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8428 MFI->setAdjustsStack(true);
8430 // And our return value (tls address) is in the standard call return value
8432 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8433 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8437 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8438 // Just use the implicit TLS architecture
8439 // Need to generate someting similar to:
8440 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8442 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8443 // mov rcx, qword [rdx+rcx*8]
8444 // mov eax, .tls$:tlsvar
8445 // [rax+rcx] contains the address
8446 // Windows 64bit: gs:0x58
8447 // Windows 32bit: fs:__tls_array
8449 // If GV is an alias then use the aliasee for determining
8450 // thread-localness.
8451 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8452 GV = GA->resolveAliasedGlobal(false);
8454 SDValue Chain = DAG.getEntryNode();
8456 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8457 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8458 // use its literal value of 0x2C.
8459 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8460 ? Type::getInt8PtrTy(*DAG.getContext(),
8462 : Type::getInt32PtrTy(*DAG.getContext(),
8465 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8466 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8467 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8469 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8470 MachinePointerInfo(Ptr),
8471 false, false, false, 0);
8473 // Load the _tls_index variable
8474 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8475 if (Subtarget->is64Bit())
8476 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8477 IDX, MachinePointerInfo(), MVT::i32,
8480 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8481 false, false, false, 0);
8483 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8485 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8487 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8488 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8489 false, false, false, 0);
8491 // Get the offset of start of .tls section
8492 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8493 GA->getValueType(0),
8494 GA->getOffset(), X86II::MO_SECREL);
8495 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8497 // The address of the thread local variable is the add of the thread
8498 // pointer with the offset of the variable.
8499 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8502 llvm_unreachable("TLS not implemented for this target.");
8505 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8506 /// and take a 2 x i32 value to shift plus a shift amount.
8507 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8508 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8509 EVT VT = Op.getValueType();
8510 unsigned VTBits = VT.getSizeInBits();
8512 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8513 SDValue ShOpLo = Op.getOperand(0);
8514 SDValue ShOpHi = Op.getOperand(1);
8515 SDValue ShAmt = Op.getOperand(2);
8516 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8517 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8519 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8520 DAG.getConstant(VTBits - 1, MVT::i8));
8521 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8522 DAG.getConstant(VTBits - 1, MVT::i8))
8523 : DAG.getConstant(0, VT);
8526 if (Op.getOpcode() == ISD::SHL_PARTS) {
8527 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8528 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8530 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8531 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8534 // If the shift amount is larger or equal than the width of a part we can't
8535 // rely on the results of shld/shrd. Insert a test and select the appropriate
8536 // values for large shift amounts.
8537 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8538 DAG.getConstant(VTBits, MVT::i8));
8539 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8540 AndNode, DAG.getConstant(0, MVT::i8));
8543 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8544 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8545 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8547 if (Op.getOpcode() == ISD::SHL_PARTS) {
8548 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8549 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8551 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8552 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8555 SDValue Ops[2] = { Lo, Hi };
8556 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8559 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8560 SelectionDAG &DAG) const {
8561 EVT SrcVT = Op.getOperand(0).getValueType();
8563 if (SrcVT.isVector())
8566 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8567 "Unknown SINT_TO_FP to lower!");
8569 // These are really Legal; return the operand so the caller accepts it as
8571 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8573 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8574 Subtarget->is64Bit()) {
8579 unsigned Size = SrcVT.getSizeInBits()/8;
8580 MachineFunction &MF = DAG.getMachineFunction();
8581 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8582 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8583 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8585 MachinePointerInfo::getFixedStack(SSFI),
8587 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8590 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8592 SelectionDAG &DAG) const {
8596 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8598 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8600 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8602 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8604 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8605 MachineMemOperand *MMO;
8607 int SSFI = FI->getIndex();
8609 DAG.getMachineFunction()
8610 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8611 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8613 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8614 StackSlot = StackSlot.getOperand(1);
8616 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8617 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8619 Tys, Ops, array_lengthof(Ops),
8623 Chain = Result.getValue(1);
8624 SDValue InFlag = Result.getValue(2);
8626 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8627 // shouldn't be necessary except that RFP cannot be live across
8628 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8629 MachineFunction &MF = DAG.getMachineFunction();
8630 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8631 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8632 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8633 Tys = DAG.getVTList(MVT::Other);
8635 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8637 MachineMemOperand *MMO =
8638 DAG.getMachineFunction()
8639 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8640 MachineMemOperand::MOStore, SSFISize, SSFISize);
8642 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8643 Ops, array_lengthof(Ops),
8644 Op.getValueType(), MMO);
8645 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8646 MachinePointerInfo::getFixedStack(SSFI),
8647 false, false, false, 0);
8653 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8654 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8655 SelectionDAG &DAG) const {
8656 // This algorithm is not obvious. Here it is what we're trying to output:
8659 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8660 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8664 pshufd $0x4e, %xmm0, %xmm1
8670 LLVMContext *Context = DAG.getContext();
8672 // Build some magic constants.
8673 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8674 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8675 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8677 SmallVector<Constant*,2> CV1;
8679 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8680 APInt(64, 0x4330000000000000ULL))));
8682 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8683 APInt(64, 0x4530000000000000ULL))));
8684 Constant *C1 = ConstantVector::get(CV1);
8685 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8687 // Load the 64-bit value into an XMM register.
8688 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8690 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8691 MachinePointerInfo::getConstantPool(),
8692 false, false, false, 16);
8693 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8694 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8697 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8698 MachinePointerInfo::getConstantPool(),
8699 false, false, false, 16);
8700 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8701 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8704 if (Subtarget->hasSSE3()) {
8705 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8706 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8708 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8709 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8711 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8712 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8716 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8717 DAG.getIntPtrConstant(0));
8720 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8721 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8722 SelectionDAG &DAG) const {
8724 // FP constant to bias correct the final result.
8725 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8728 // Load the 32-bit value into an XMM register.
8729 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8732 // Zero out the upper parts of the register.
8733 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8735 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8736 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8737 DAG.getIntPtrConstant(0));
8739 // Or the load with the bias.
8740 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8741 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8742 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8744 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8745 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8746 MVT::v2f64, Bias)));
8747 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8748 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8749 DAG.getIntPtrConstant(0));
8751 // Subtract the bias.
8752 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8754 // Handle final rounding.
8755 EVT DestVT = Op.getValueType();
8757 if (DestVT.bitsLT(MVT::f64))
8758 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8759 DAG.getIntPtrConstant(0));
8760 if (DestVT.bitsGT(MVT::f64))
8761 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8763 // Handle final rounding.
8767 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8768 SelectionDAG &DAG) const {
8769 SDValue N0 = Op.getOperand(0);
8770 EVT SVT = N0.getValueType();
8773 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8774 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8775 "Custom UINT_TO_FP is not supported!");
8777 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8778 SVT.getVectorNumElements());
8779 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8780 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8783 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8784 SelectionDAG &DAG) const {
8785 SDValue N0 = Op.getOperand(0);
8788 if (Op.getValueType().isVector())
8789 return lowerUINT_TO_FP_vec(Op, DAG);
8791 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8792 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8793 // the optimization here.
8794 if (DAG.SignBitIsZero(N0))
8795 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8797 EVT SrcVT = N0.getValueType();
8798 EVT DstVT = Op.getValueType();
8799 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8800 return LowerUINT_TO_FP_i64(Op, DAG);
8801 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8802 return LowerUINT_TO_FP_i32(Op, DAG);
8803 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8806 // Make a 64-bit buffer, and use it to build an FILD.
8807 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8808 if (SrcVT == MVT::i32) {
8809 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8810 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8811 getPointerTy(), StackSlot, WordOff);
8812 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8813 StackSlot, MachinePointerInfo(),
8815 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8816 OffsetSlot, MachinePointerInfo(),
8818 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8822 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8823 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8824 StackSlot, MachinePointerInfo(),
8826 // For i64 source, we need to add the appropriate power of 2 if the input
8827 // was negative. This is the same as the optimization in
8828 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8829 // we must be careful to do the computation in x87 extended precision, not
8830 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8831 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8832 MachineMemOperand *MMO =
8833 DAG.getMachineFunction()
8834 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8835 MachineMemOperand::MOLoad, 8, 8);
8837 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8838 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8839 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8840 array_lengthof(Ops), MVT::i64, MMO);
8842 APInt FF(32, 0x5F800000ULL);
8844 // Check whether the sign bit is set.
8845 SDValue SignSet = DAG.getSetCC(dl,
8846 getSetCCResultType(*DAG.getContext(), MVT::i64),
8847 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8850 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8851 SDValue FudgePtr = DAG.getConstantPool(
8852 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8855 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8856 SDValue Zero = DAG.getIntPtrConstant(0);
8857 SDValue Four = DAG.getIntPtrConstant(4);
8858 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8860 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8862 // Load the value out, extending it from f32 to f80.
8863 // FIXME: Avoid the extend by constructing the right constant pool?
8864 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8865 FudgePtr, MachinePointerInfo::getConstantPool(),
8866 MVT::f32, false, false, 4);
8867 // Extend everything to 80 bits to force it to be done on x87.
8868 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8869 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8872 std::pair<SDValue,SDValue>
8873 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8874 bool IsSigned, bool IsReplace) const {
8877 EVT DstTy = Op.getValueType();
8879 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8880 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8884 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8885 DstTy.getSimpleVT() >= MVT::i16 &&
8886 "Unknown FP_TO_INT to lower!");
8888 // These are really Legal.
8889 if (DstTy == MVT::i32 &&
8890 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8891 return std::make_pair(SDValue(), SDValue());
8892 if (Subtarget->is64Bit() &&
8893 DstTy == MVT::i64 &&
8894 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8895 return std::make_pair(SDValue(), SDValue());
8897 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8898 // stack slot, or into the FTOL runtime function.
8899 MachineFunction &MF = DAG.getMachineFunction();
8900 unsigned MemSize = DstTy.getSizeInBits()/8;
8901 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8902 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8905 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8906 Opc = X86ISD::WIN_FTOL;
8908 switch (DstTy.getSimpleVT().SimpleTy) {
8909 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8910 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8911 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8912 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8915 SDValue Chain = DAG.getEntryNode();
8916 SDValue Value = Op.getOperand(0);
8917 EVT TheVT = Op.getOperand(0).getValueType();
8918 // FIXME This causes a redundant load/store if the SSE-class value is already
8919 // in memory, such as if it is on the callstack.
8920 if (isScalarFPTypeInSSEReg(TheVT)) {
8921 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8922 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8923 MachinePointerInfo::getFixedStack(SSFI),
8925 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8927 Chain, StackSlot, DAG.getValueType(TheVT)
8930 MachineMemOperand *MMO =
8931 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8932 MachineMemOperand::MOLoad, MemSize, MemSize);
8933 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8934 array_lengthof(Ops), DstTy, MMO);
8935 Chain = Value.getValue(1);
8936 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8937 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8940 MachineMemOperand *MMO =
8941 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8942 MachineMemOperand::MOStore, MemSize, MemSize);
8944 if (Opc != X86ISD::WIN_FTOL) {
8945 // Build the FP_TO_INT*_IN_MEM
8946 SDValue Ops[] = { Chain, Value, StackSlot };
8947 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8948 Ops, array_lengthof(Ops), DstTy,
8950 return std::make_pair(FIST, StackSlot);
8952 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8953 DAG.getVTList(MVT::Other, MVT::Glue),
8955 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8956 MVT::i32, ftol.getValue(1));
8957 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8958 MVT::i32, eax.getValue(2));
8959 SDValue Ops[] = { eax, edx };
8960 SDValue pair = IsReplace
8961 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8962 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8963 return std::make_pair(pair, SDValue());
8967 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8968 const X86Subtarget *Subtarget) {
8969 MVT VT = Op->getSimpleValueType(0);
8970 SDValue In = Op->getOperand(0);
8971 MVT InVT = In.getSimpleValueType();
8974 // Optimize vectors in AVX mode:
8977 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8978 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8979 // Concat upper and lower parts.
8982 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8983 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8984 // Concat upper and lower parts.
8987 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8988 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8989 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8992 if (Subtarget->hasInt256())
8993 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8995 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8996 SDValue Undef = DAG.getUNDEF(InVT);
8997 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8998 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8999 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9001 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9002 VT.getVectorNumElements()/2);
9004 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9005 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9007 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9010 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9011 SelectionDAG &DAG) {
9012 MVT VT = Op->getValueType(0).getSimpleVT();
9013 SDValue In = Op->getOperand(0);
9014 MVT InVT = In.getValueType().getSimpleVT();
9016 unsigned int NumElts = VT.getVectorNumElements();
9017 if (NumElts != 8 && NumElts != 16)
9020 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9021 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9023 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9024 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9025 // Now we have only mask extension
9026 assert(InVT.getVectorElementType() == MVT::i1);
9027 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9028 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9029 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9030 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9031 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9032 MachinePointerInfo::getConstantPool(),
9033 false, false, false, Alignment);
9035 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9036 if (VT.is512BitVector())
9038 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9041 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9042 SelectionDAG &DAG) {
9043 if (Subtarget->hasFp256()) {
9044 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9052 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9053 SelectionDAG &DAG) {
9055 MVT VT = Op.getSimpleValueType();
9056 SDValue In = Op.getOperand(0);
9057 MVT SVT = In.getSimpleValueType();
9059 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9060 return LowerZERO_EXTEND_AVX512(Op, DAG);
9062 if (Subtarget->hasFp256()) {
9063 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9068 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9069 VT.getVectorNumElements() != SVT.getVectorNumElements());
9073 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9075 MVT VT = Op.getSimpleValueType();
9076 SDValue In = Op.getOperand(0);
9077 MVT InVT = In.getSimpleValueType();
9079 if (VT == MVT::i1) {
9080 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9081 "Invalid scalar TRUNCATE operation");
9082 if (InVT == MVT::i32)
9084 if (InVT.getSizeInBits() == 64)
9085 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9086 else if (InVT.getSizeInBits() < 32)
9087 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9088 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9090 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9091 "Invalid TRUNCATE operation");
9093 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9094 if (VT.getVectorElementType().getSizeInBits() >=8)
9095 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9097 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9098 unsigned NumElts = InVT.getVectorNumElements();
9099 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9100 if (InVT.getSizeInBits() < 512) {
9101 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9102 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9105 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9106 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9107 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9108 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9109 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9110 MachinePointerInfo::getConstantPool(),
9111 false, false, false, Alignment);
9112 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9113 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9114 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9117 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9118 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9119 if (Subtarget->hasInt256()) {
9120 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9121 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9122 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9124 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9125 DAG.getIntPtrConstant(0));
9128 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9129 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9130 DAG.getIntPtrConstant(0));
9131 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9132 DAG.getIntPtrConstant(2));
9134 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9135 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9138 static const int ShufMask1[] = {0, 2, 0, 0};
9139 SDValue Undef = DAG.getUNDEF(VT);
9140 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9141 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9143 // The MOVLHPS mask:
9144 static const int ShufMask2[] = {0, 1, 4, 5};
9145 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9148 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9149 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9150 if (Subtarget->hasInt256()) {
9151 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9153 SmallVector<SDValue,32> pshufbMask;
9154 for (unsigned i = 0; i < 2; ++i) {
9155 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9156 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9157 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9158 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9159 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9160 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9161 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9162 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9163 for (unsigned j = 0; j < 8; ++j)
9164 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9166 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9167 &pshufbMask[0], 32);
9168 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9169 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9171 static const int ShufMask[] = {0, 2, -1, -1};
9172 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9174 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9175 DAG.getIntPtrConstant(0));
9176 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9179 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9180 DAG.getIntPtrConstant(0));
9182 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9183 DAG.getIntPtrConstant(4));
9185 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9186 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9189 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9190 -1, -1, -1, -1, -1, -1, -1, -1};
9192 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9193 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9194 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9196 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9197 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9199 // The MOVLHPS Mask:
9200 static const int ShufMask2[] = {0, 1, 4, 5};
9201 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9202 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9205 // Handle truncation of V256 to V128 using shuffles.
9206 if (!VT.is128BitVector() || !InVT.is256BitVector())
9209 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9211 unsigned NumElems = VT.getVectorNumElements();
9212 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9215 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9216 // Prepare truncation shuffle mask
9217 for (unsigned i = 0; i != NumElems; ++i)
9219 SDValue V = DAG.getVectorShuffle(NVT, DL,
9220 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9221 DAG.getUNDEF(NVT), &MaskVec[0]);
9222 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9223 DAG.getIntPtrConstant(0));
9226 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9227 SelectionDAG &DAG) const {
9228 MVT VT = Op.getSimpleValueType();
9229 if (VT.isVector()) {
9230 if (VT == MVT::v8i16)
9231 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9232 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9233 MVT::v8i32, Op.getOperand(0)));
9237 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9238 /*IsSigned=*/ true, /*IsReplace=*/ false);
9239 SDValue FIST = Vals.first, StackSlot = Vals.second;
9240 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9241 if (FIST.getNode() == 0) return Op;
9243 if (StackSlot.getNode())
9245 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9246 FIST, StackSlot, MachinePointerInfo(),
9247 false, false, false, 0);
9249 // The node is the result.
9253 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9254 SelectionDAG &DAG) const {
9255 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9256 /*IsSigned=*/ false, /*IsReplace=*/ false);
9257 SDValue FIST = Vals.first, StackSlot = Vals.second;
9258 assert(FIST.getNode() && "Unexpected failure");
9260 if (StackSlot.getNode())
9262 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9263 FIST, StackSlot, MachinePointerInfo(),
9264 false, false, false, 0);
9266 // The node is the result.
9270 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9272 MVT VT = Op.getSimpleValueType();
9273 SDValue In = Op.getOperand(0);
9274 MVT SVT = In.getSimpleValueType();
9276 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9278 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9279 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9280 In, DAG.getUNDEF(SVT)));
9283 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9284 LLVMContext *Context = DAG.getContext();
9286 MVT VT = Op.getSimpleValueType();
9288 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9289 if (VT.isVector()) {
9290 EltVT = VT.getVectorElementType();
9291 NumElts = VT.getVectorNumElements();
9294 if (EltVT == MVT::f64)
9295 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9296 APInt(64, ~(1ULL << 63))));
9298 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9299 APInt(32, ~(1U << 31))));
9300 C = ConstantVector::getSplat(NumElts, C);
9301 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9302 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9303 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9304 MachinePointerInfo::getConstantPool(),
9305 false, false, false, Alignment);
9306 if (VT.isVector()) {
9307 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9308 return DAG.getNode(ISD::BITCAST, dl, VT,
9309 DAG.getNode(ISD::AND, dl, ANDVT,
9310 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9312 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9314 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9317 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9318 LLVMContext *Context = DAG.getContext();
9320 MVT VT = Op.getSimpleValueType();
9322 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9323 if (VT.isVector()) {
9324 EltVT = VT.getVectorElementType();
9325 NumElts = VT.getVectorNumElements();
9328 if (EltVT == MVT::f64)
9329 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9330 APInt(64, 1ULL << 63)));
9332 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9333 APInt(32, 1U << 31)));
9334 C = ConstantVector::getSplat(NumElts, C);
9335 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9336 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9337 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9338 MachinePointerInfo::getConstantPool(),
9339 false, false, false, Alignment);
9340 if (VT.isVector()) {
9341 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9342 return DAG.getNode(ISD::BITCAST, dl, VT,
9343 DAG.getNode(ISD::XOR, dl, XORVT,
9344 DAG.getNode(ISD::BITCAST, dl, XORVT,
9346 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9349 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9352 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9353 LLVMContext *Context = DAG.getContext();
9354 SDValue Op0 = Op.getOperand(0);
9355 SDValue Op1 = Op.getOperand(1);
9357 MVT VT = Op.getSimpleValueType();
9358 MVT SrcVT = Op1.getSimpleValueType();
9360 // If second operand is smaller, extend it first.
9361 if (SrcVT.bitsLT(VT)) {
9362 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9365 // And if it is bigger, shrink it first.
9366 if (SrcVT.bitsGT(VT)) {
9367 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9371 // At this point the operands and the result should have the same
9372 // type, and that won't be f80 since that is not custom lowered.
9374 // First get the sign bit of second operand.
9375 SmallVector<Constant*,4> CV;
9376 if (SrcVT == MVT::f64) {
9377 const fltSemantics &Sem = APFloat::IEEEdouble;
9378 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9379 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9381 const fltSemantics &Sem = APFloat::IEEEsingle;
9382 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9383 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9384 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9385 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9387 Constant *C = ConstantVector::get(CV);
9388 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9389 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9390 MachinePointerInfo::getConstantPool(),
9391 false, false, false, 16);
9392 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9394 // Shift sign bit right or left if the two operands have different types.
9395 if (SrcVT.bitsGT(VT)) {
9396 // Op0 is MVT::f32, Op1 is MVT::f64.
9397 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9398 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9399 DAG.getConstant(32, MVT::i32));
9400 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9401 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9402 DAG.getIntPtrConstant(0));
9405 // Clear first operand sign bit.
9407 if (VT == MVT::f64) {
9408 const fltSemantics &Sem = APFloat::IEEEdouble;
9409 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9410 APInt(64, ~(1ULL << 63)))));
9411 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9413 const fltSemantics &Sem = APFloat::IEEEsingle;
9414 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9415 APInt(32, ~(1U << 31)))));
9416 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9417 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9418 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9420 C = ConstantVector::get(CV);
9421 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9422 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9423 MachinePointerInfo::getConstantPool(),
9424 false, false, false, 16);
9425 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9427 // Or the value with the sign bit.
9428 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9431 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9432 SDValue N0 = Op.getOperand(0);
9434 MVT VT = Op.getSimpleValueType();
9436 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9437 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9438 DAG.getConstant(1, VT));
9439 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9442 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9444 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9445 SelectionDAG &DAG) {
9446 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9448 if (!Subtarget->hasSSE41())
9451 if (!Op->hasOneUse())
9454 SDNode *N = Op.getNode();
9457 SmallVector<SDValue, 8> Opnds;
9458 DenseMap<SDValue, unsigned> VecInMap;
9459 EVT VT = MVT::Other;
9461 // Recognize a special case where a vector is casted into wide integer to
9463 Opnds.push_back(N->getOperand(0));
9464 Opnds.push_back(N->getOperand(1));
9466 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9467 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9468 // BFS traverse all OR'd operands.
9469 if (I->getOpcode() == ISD::OR) {
9470 Opnds.push_back(I->getOperand(0));
9471 Opnds.push_back(I->getOperand(1));
9472 // Re-evaluate the number of nodes to be traversed.
9473 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9477 // Quit if a non-EXTRACT_VECTOR_ELT
9478 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9481 // Quit if without a constant index.
9482 SDValue Idx = I->getOperand(1);
9483 if (!isa<ConstantSDNode>(Idx))
9486 SDValue ExtractedFromVec = I->getOperand(0);
9487 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9488 if (M == VecInMap.end()) {
9489 VT = ExtractedFromVec.getValueType();
9490 // Quit if not 128/256-bit vector.
9491 if (!VT.is128BitVector() && !VT.is256BitVector())
9493 // Quit if not the same type.
9494 if (VecInMap.begin() != VecInMap.end() &&
9495 VT != VecInMap.begin()->first.getValueType())
9497 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9499 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9502 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9503 "Not extracted from 128-/256-bit vector.");
9505 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9506 SmallVector<SDValue, 8> VecIns;
9508 for (DenseMap<SDValue, unsigned>::const_iterator
9509 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9510 // Quit if not all elements are used.
9511 if (I->second != FullMask)
9513 VecIns.push_back(I->first);
9516 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9518 // Cast all vectors into TestVT for PTEST.
9519 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9520 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9522 // If more than one full vectors are evaluated, OR them first before PTEST.
9523 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9524 // Each iteration will OR 2 nodes and append the result until there is only
9525 // 1 node left, i.e. the final OR'd value of all vectors.
9526 SDValue LHS = VecIns[Slot];
9527 SDValue RHS = VecIns[Slot + 1];
9528 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9531 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9532 VecIns.back(), VecIns.back());
9535 /// Emit nodes that will be selected as "test Op0,Op0", or something
9537 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9538 SelectionDAG &DAG) const {
9541 // CF and OF aren't always set the way we want. Determine which
9542 // of these we need.
9543 bool NeedCF = false;
9544 bool NeedOF = false;
9547 case X86::COND_A: case X86::COND_AE:
9548 case X86::COND_B: case X86::COND_BE:
9551 case X86::COND_G: case X86::COND_GE:
9552 case X86::COND_L: case X86::COND_LE:
9553 case X86::COND_O: case X86::COND_NO:
9558 // See if we can use the EFLAGS value from the operand instead of
9559 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9560 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9561 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
9562 // Emit a CMP with 0, which is the TEST pattern.
9563 if (Op.getValueType() == MVT::i1)
9564 return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
9565 DAG.getConstant(0, MVT::i1));
9566 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9567 DAG.getConstant(0, Op.getValueType()));
9569 unsigned Opcode = 0;
9570 unsigned NumOperands = 0;
9572 // Truncate operations may prevent the merge of the SETCC instruction
9573 // and the arithmetic instruction before it. Attempt to truncate the operands
9574 // of the arithmetic instruction and use a reduced bit-width instruction.
9575 bool NeedTruncation = false;
9576 SDValue ArithOp = Op;
9577 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9578 SDValue Arith = Op->getOperand(0);
9579 // Both the trunc and the arithmetic op need to have one user each.
9580 if (Arith->hasOneUse())
9581 switch (Arith.getOpcode()) {
9588 NeedTruncation = true;
9594 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9595 // which may be the result of a CAST. We use the variable 'Op', which is the
9596 // non-casted variable when we check for possible users.
9597 switch (ArithOp.getOpcode()) {
9599 // Due to an isel shortcoming, be conservative if this add is likely to be
9600 // selected as part of a load-modify-store instruction. When the root node
9601 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9602 // uses of other nodes in the match, such as the ADD in this case. This
9603 // leads to the ADD being left around and reselected, with the result being
9604 // two adds in the output. Alas, even if none our users are stores, that
9605 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9606 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9607 // climbing the DAG back to the root, and it doesn't seem to be worth the
9609 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9610 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9611 if (UI->getOpcode() != ISD::CopyToReg &&
9612 UI->getOpcode() != ISD::SETCC &&
9613 UI->getOpcode() != ISD::STORE)
9616 if (ConstantSDNode *C =
9617 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9618 // An add of one will be selected as an INC.
9619 if (C->getAPIntValue() == 1) {
9620 Opcode = X86ISD::INC;
9625 // An add of negative one (subtract of one) will be selected as a DEC.
9626 if (C->getAPIntValue().isAllOnesValue()) {
9627 Opcode = X86ISD::DEC;
9633 // Otherwise use a regular EFLAGS-setting add.
9634 Opcode = X86ISD::ADD;
9638 // If the primary and result isn't used, don't bother using X86ISD::AND,
9639 // because a TEST instruction will be better.
9640 bool NonFlagUse = false;
9641 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9642 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9644 unsigned UOpNo = UI.getOperandNo();
9645 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9646 // Look pass truncate.
9647 UOpNo = User->use_begin().getOperandNo();
9648 User = *User->use_begin();
9651 if (User->getOpcode() != ISD::BRCOND &&
9652 User->getOpcode() != ISD::SETCC &&
9653 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9666 // Due to the ISEL shortcoming noted above, be conservative if this op is
9667 // likely to be selected as part of a load-modify-store instruction.
9668 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9669 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9670 if (UI->getOpcode() == ISD::STORE)
9673 // Otherwise use a regular EFLAGS-setting instruction.
9674 switch (ArithOp.getOpcode()) {
9675 default: llvm_unreachable("unexpected operator!");
9676 case ISD::SUB: Opcode = X86ISD::SUB; break;
9677 case ISD::XOR: Opcode = X86ISD::XOR; break;
9678 case ISD::AND: Opcode = X86ISD::AND; break;
9680 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9681 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9682 if (EFLAGS.getNode())
9685 Opcode = X86ISD::OR;
9699 return SDValue(Op.getNode(), 1);
9705 // If we found that truncation is beneficial, perform the truncation and
9707 if (NeedTruncation) {
9708 EVT VT = Op.getValueType();
9709 SDValue WideVal = Op->getOperand(0);
9710 EVT WideVT = WideVal.getValueType();
9711 unsigned ConvertedOp = 0;
9712 // Use a target machine opcode to prevent further DAGCombine
9713 // optimizations that may separate the arithmetic operations
9714 // from the setcc node.
9715 switch (WideVal.getOpcode()) {
9717 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9718 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9719 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9720 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9721 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9726 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9727 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9728 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9729 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9735 // Emit a CMP with 0, which is the TEST pattern.
9736 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9737 DAG.getConstant(0, Op.getValueType()));
9739 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9740 SmallVector<SDValue, 4> Ops;
9741 for (unsigned i = 0; i != NumOperands; ++i)
9742 Ops.push_back(Op.getOperand(i));
9744 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9745 DAG.ReplaceAllUsesWith(Op, New);
9746 return SDValue(New.getNode(), 1);
9749 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9751 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9752 SelectionDAG &DAG) const {
9754 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9755 if (C->getAPIntValue() == 0)
9756 return EmitTest(Op0, X86CC, DAG);
9758 if (Op0.getValueType() == MVT::i1) {
9759 Op0 = DAG.getNode(ISD::XOR, dl, MVT::i1, Op0,
9760 DAG.getConstant(-1, MVT::i1));
9761 return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op0,
9762 DAG.getConstant(0, MVT::i1));
9766 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9767 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9768 // Do the comparison at i32 if it's smaller. This avoids subregister
9769 // aliasing issues. Keep the smaller reference if we're optimizing for
9770 // size, however, as that'll allow better folding of memory operations.
9771 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9772 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9773 AttributeSet::FunctionIndex, Attribute::MinSize)) {
9775 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9776 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9777 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9779 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9780 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9781 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9783 return SDValue(Sub.getNode(), 1);
9785 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9788 /// Convert a comparison if required by the subtarget.
9789 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9790 SelectionDAG &DAG) const {
9791 // If the subtarget does not support the FUCOMI instruction, floating-point
9792 // comparisons have to be converted.
9793 if (Subtarget->hasCMov() ||
9794 Cmp.getOpcode() != X86ISD::CMP ||
9795 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9796 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9799 // The instruction selector will select an FUCOM instruction instead of
9800 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9801 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9802 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9804 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9805 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9806 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9807 DAG.getConstant(8, MVT::i8));
9808 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9809 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9812 static bool isAllOnes(SDValue V) {
9813 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9814 return C && C->isAllOnesValue();
9817 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9818 /// if it's possible.
9819 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9820 SDLoc dl, SelectionDAG &DAG) const {
9821 SDValue Op0 = And.getOperand(0);
9822 SDValue Op1 = And.getOperand(1);
9823 if (Op0.getOpcode() == ISD::TRUNCATE)
9824 Op0 = Op0.getOperand(0);
9825 if (Op1.getOpcode() == ISD::TRUNCATE)
9826 Op1 = Op1.getOperand(0);
9829 if (Op1.getOpcode() == ISD::SHL)
9830 std::swap(Op0, Op1);
9831 if (Op0.getOpcode() == ISD::SHL) {
9832 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9833 if (And00C->getZExtValue() == 1) {
9834 // If we looked past a truncate, check that it's only truncating away
9836 unsigned BitWidth = Op0.getValueSizeInBits();
9837 unsigned AndBitWidth = And.getValueSizeInBits();
9838 if (BitWidth > AndBitWidth) {
9840 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9841 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9845 RHS = Op0.getOperand(1);
9847 } else if (Op1.getOpcode() == ISD::Constant) {
9848 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9849 uint64_t AndRHSVal = AndRHS->getZExtValue();
9850 SDValue AndLHS = Op0;
9852 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9853 LHS = AndLHS.getOperand(0);
9854 RHS = AndLHS.getOperand(1);
9857 // Use BT if the immediate can't be encoded in a TEST instruction.
9858 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9860 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9864 if (LHS.getNode()) {
9865 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9866 // instruction. Since the shift amount is in-range-or-undefined, we know
9867 // that doing a bittest on the i32 value is ok. We extend to i32 because
9868 // the encoding for the i16 version is larger than the i32 version.
9869 // Also promote i16 to i32 for performance / code size reason.
9870 if (LHS.getValueType() == MVT::i8 ||
9871 LHS.getValueType() == MVT::i16)
9872 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9874 // If the operand types disagree, extend the shift amount to match. Since
9875 // BT ignores high bits (like shifts) we can use anyextend.
9876 if (LHS.getValueType() != RHS.getValueType())
9877 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9879 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9880 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9881 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9882 DAG.getConstant(Cond, MVT::i8), BT);
9888 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9890 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9895 // SSE Condition code mapping:
9904 switch (SetCCOpcode) {
9905 default: llvm_unreachable("Unexpected SETCC condition");
9907 case ISD::SETEQ: SSECC = 0; break;
9909 case ISD::SETGT: Swap = true; // Fallthrough
9911 case ISD::SETOLT: SSECC = 1; break;
9913 case ISD::SETGE: Swap = true; // Fallthrough
9915 case ISD::SETOLE: SSECC = 2; break;
9916 case ISD::SETUO: SSECC = 3; break;
9918 case ISD::SETNE: SSECC = 4; break;
9919 case ISD::SETULE: Swap = true; // Fallthrough
9920 case ISD::SETUGE: SSECC = 5; break;
9921 case ISD::SETULT: Swap = true; // Fallthrough
9922 case ISD::SETUGT: SSECC = 6; break;
9923 case ISD::SETO: SSECC = 7; break;
9925 case ISD::SETONE: SSECC = 8; break;
9928 std::swap(Op0, Op1);
9933 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9934 // ones, and then concatenate the result back.
9935 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9936 MVT VT = Op.getSimpleValueType();
9938 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9939 "Unsupported value type for operation");
9941 unsigned NumElems = VT.getVectorNumElements();
9943 SDValue CC = Op.getOperand(2);
9945 // Extract the LHS vectors
9946 SDValue LHS = Op.getOperand(0);
9947 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9948 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9950 // Extract the RHS vectors
9951 SDValue RHS = Op.getOperand(1);
9952 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9953 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9955 // Issue the operation on the smaller types and concatenate the result back
9956 MVT EltVT = VT.getVectorElementType();
9957 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9958 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9959 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9960 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9963 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9964 SDValue Op0 = Op.getOperand(0);
9965 SDValue Op1 = Op.getOperand(1);
9966 SDValue CC = Op.getOperand(2);
9967 MVT VT = Op.getSimpleValueType();
9969 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9970 Op.getValueType().getScalarType() == MVT::i1 &&
9971 "Cannot set masked compare for this operation");
9973 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9976 bool Unsigned = false;
9978 switch (SetCCOpcode) {
9979 default: llvm_unreachable("Unexpected SETCC condition");
9980 case ISD::SETNE: SSECC = 4; break;
9981 case ISD::SETEQ: SSECC = 0; break;
9982 case ISD::SETUGT: Unsigned = true;
9983 case ISD::SETGT: SSECC = 6; break; // NLE
9984 case ISD::SETULT: Unsigned = true;
9985 case ISD::SETLT: SSECC = 1; break;
9986 case ISD::SETUGE: Unsigned = true;
9987 case ISD::SETGE: SSECC = 5; break; // NLT
9988 case ISD::SETULE: Unsigned = true;
9989 case ISD::SETLE: SSECC = 2; break;
9991 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9992 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9993 DAG.getConstant(SSECC, MVT::i8));
9997 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9998 SelectionDAG &DAG) {
9999 SDValue Op0 = Op.getOperand(0);
10000 SDValue Op1 = Op.getOperand(1);
10001 SDValue CC = Op.getOperand(2);
10002 MVT VT = Op.getSimpleValueType();
10003 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10004 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10009 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10010 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10013 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10014 unsigned Opc = X86ISD::CMPP;
10015 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10016 assert(VT.getVectorNumElements() <= 16);
10017 Opc = X86ISD::CMPM;
10019 // In the two special cases we can't handle, emit two comparisons.
10022 unsigned CombineOpc;
10023 if (SetCCOpcode == ISD::SETUEQ) {
10024 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10026 assert(SetCCOpcode == ISD::SETONE);
10027 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10030 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10031 DAG.getConstant(CC0, MVT::i8));
10032 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10033 DAG.getConstant(CC1, MVT::i8));
10034 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10036 // Handle all other FP comparisons here.
10037 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10038 DAG.getConstant(SSECC, MVT::i8));
10041 // Break 256-bit integer vector compare into smaller ones.
10042 if (VT.is256BitVector() && !Subtarget->hasInt256())
10043 return Lower256IntVSETCC(Op, DAG);
10045 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10046 EVT OpVT = Op1.getValueType();
10047 if (Subtarget->hasAVX512()) {
10048 if (Op1.getValueType().is512BitVector() ||
10049 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10050 return LowerIntVSETCC_AVX512(Op, DAG);
10052 // In AVX-512 architecture setcc returns mask with i1 elements,
10053 // But there is no compare instruction for i8 and i16 elements.
10054 // We are not talking about 512-bit operands in this case, these
10055 // types are illegal.
10057 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10058 OpVT.getVectorElementType().getSizeInBits() >= 8))
10059 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10060 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10063 // We are handling one of the integer comparisons here. Since SSE only has
10064 // GT and EQ comparisons for integer, swapping operands and multiple
10065 // operations may be required for some comparisons.
10067 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10069 switch (SetCCOpcode) {
10070 default: llvm_unreachable("Unexpected SETCC condition");
10071 case ISD::SETNE: Invert = true;
10072 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
10073 case ISD::SETLT: Swap = true;
10074 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
10075 case ISD::SETGE: Swap = true;
10076 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10077 Invert = true; break;
10078 case ISD::SETULT: Swap = true;
10079 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10080 FlipSigns = true; break;
10081 case ISD::SETUGE: Swap = true;
10082 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10083 FlipSigns = true; Invert = true; break;
10086 // Special case: Use min/max operations for SETULE/SETUGE
10087 MVT VET = VT.getVectorElementType();
10089 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10090 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10093 switch (SetCCOpcode) {
10095 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10096 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10099 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10103 std::swap(Op0, Op1);
10105 // Check that the operation in question is available (most are plain SSE2,
10106 // but PCMPGTQ and PCMPEQQ have different requirements).
10107 if (VT == MVT::v2i64) {
10108 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10109 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10111 // First cast everything to the right type.
10112 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10113 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10115 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10116 // bits of the inputs before performing those operations. The lower
10117 // compare is always unsigned.
10120 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10122 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10123 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10124 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10125 Sign, Zero, Sign, Zero);
10127 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10128 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10130 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10131 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10132 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10134 // Create masks for only the low parts/high parts of the 64 bit integers.
10135 static const int MaskHi[] = { 1, 1, 3, 3 };
10136 static const int MaskLo[] = { 0, 0, 2, 2 };
10137 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10138 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10139 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10141 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10142 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10145 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10147 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10150 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10151 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10152 // pcmpeqd + pshufd + pand.
10153 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10155 // First cast everything to the right type.
10156 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10157 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10160 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10162 // Make sure the lower and upper halves are both all-ones.
10163 static const int Mask[] = { 1, 0, 3, 2 };
10164 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10165 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10168 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10170 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10174 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10175 // bits of the inputs before performing those operations.
10177 EVT EltVT = VT.getVectorElementType();
10178 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10179 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10180 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10183 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10185 // If the logical-not of the result is required, perform that now.
10187 Result = DAG.getNOT(dl, Result, VT);
10190 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10195 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10197 MVT VT = Op.getSimpleValueType();
10199 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10201 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10202 && "SetCC type must be 8-bit or 1-bit integer");
10203 SDValue Op0 = Op.getOperand(0);
10204 SDValue Op1 = Op.getOperand(1);
10206 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10208 // Optimize to BT if possible.
10209 // Lower (X & (1 << N)) == 0 to BT(X, N).
10210 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10211 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10212 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10213 Op1.getOpcode() == ISD::Constant &&
10214 cast<ConstantSDNode>(Op1)->isNullValue() &&
10215 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10216 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10217 if (NewSetCC.getNode())
10221 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10223 if (Op1.getOpcode() == ISD::Constant &&
10224 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10225 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10226 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10228 // If the input is a setcc, then reuse the input setcc or use a new one with
10229 // the inverted condition.
10230 if (Op0.getOpcode() == X86ISD::SETCC) {
10231 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10232 bool Invert = (CC == ISD::SETNE) ^
10233 cast<ConstantSDNode>(Op1)->isNullValue();
10234 if (!Invert) return Op0;
10236 CCode = X86::GetOppositeBranchCondition(CCode);
10237 return DAG.getNode(X86ISD::SETCC, dl, VT,
10238 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10242 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10243 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10244 if (X86CC == X86::COND_INVALID)
10247 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10248 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10249 return DAG.getNode(X86ISD::SETCC, dl, VT,
10250 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10253 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10254 static bool isX86LogicalCmp(SDValue Op) {
10255 unsigned Opc = Op.getNode()->getOpcode();
10256 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10257 Opc == X86ISD::SAHF)
10259 if (Op.getResNo() == 1 &&
10260 (Opc == X86ISD::ADD ||
10261 Opc == X86ISD::SUB ||
10262 Opc == X86ISD::ADC ||
10263 Opc == X86ISD::SBB ||
10264 Opc == X86ISD::SMUL ||
10265 Opc == X86ISD::UMUL ||
10266 Opc == X86ISD::INC ||
10267 Opc == X86ISD::DEC ||
10268 Opc == X86ISD::OR ||
10269 Opc == X86ISD::XOR ||
10270 Opc == X86ISD::AND))
10273 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10279 static bool isZero(SDValue V) {
10280 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10281 return C && C->isNullValue();
10284 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10285 if (V.getOpcode() != ISD::TRUNCATE)
10288 SDValue VOp0 = V.getOperand(0);
10289 unsigned InBits = VOp0.getValueSizeInBits();
10290 unsigned Bits = V.getValueSizeInBits();
10291 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10294 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10295 bool addTest = true;
10296 SDValue Cond = Op.getOperand(0);
10297 SDValue Op1 = Op.getOperand(1);
10298 SDValue Op2 = Op.getOperand(2);
10300 EVT VT = Op1.getValueType();
10303 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10304 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10305 // sequence later on.
10306 if (Cond.getOpcode() == ISD::SETCC &&
10307 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10308 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10309 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10310 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10311 int SSECC = translateX86FSETCC(
10312 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10315 if (Subtarget->hasAVX512()) {
10316 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10317 DAG.getConstant(SSECC, MVT::i8));
10318 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10320 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10321 DAG.getConstant(SSECC, MVT::i8));
10322 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10323 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10324 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10328 if (Cond.getOpcode() == ISD::SETCC) {
10329 SDValue NewCond = LowerSETCC(Cond, DAG);
10330 if (NewCond.getNode())
10334 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10335 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10336 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10337 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10338 if (Cond.getOpcode() == X86ISD::SETCC &&
10339 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10340 isZero(Cond.getOperand(1).getOperand(1))) {
10341 SDValue Cmp = Cond.getOperand(1);
10343 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10345 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10346 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10347 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10349 SDValue CmpOp0 = Cmp.getOperand(0);
10350 // Apply further optimizations for special cases
10351 // (select (x != 0), -1, 0) -> neg & sbb
10352 // (select (x == 0), 0, -1) -> neg & sbb
10353 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10354 if (YC->isNullValue() &&
10355 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10356 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10357 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10358 DAG.getConstant(0, CmpOp0.getValueType()),
10360 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10361 DAG.getConstant(X86::COND_B, MVT::i8),
10362 SDValue(Neg.getNode(), 1));
10366 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10367 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10368 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10370 SDValue Res = // Res = 0 or -1.
10371 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10372 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10374 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10375 Res = DAG.getNOT(DL, Res, Res.getValueType());
10377 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10378 if (N2C == 0 || !N2C->isNullValue())
10379 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10384 // Look past (and (setcc_carry (cmp ...)), 1).
10385 if (Cond.getOpcode() == ISD::AND &&
10386 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10387 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10388 if (C && C->getAPIntValue() == 1)
10389 Cond = Cond.getOperand(0);
10392 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10393 // setting operand in place of the X86ISD::SETCC.
10394 unsigned CondOpcode = Cond.getOpcode();
10395 if (CondOpcode == X86ISD::SETCC ||
10396 CondOpcode == X86ISD::SETCC_CARRY) {
10397 CC = Cond.getOperand(0);
10399 SDValue Cmp = Cond.getOperand(1);
10400 unsigned Opc = Cmp.getOpcode();
10401 MVT VT = Op.getSimpleValueType();
10403 bool IllegalFPCMov = false;
10404 if (VT.isFloatingPoint() && !VT.isVector() &&
10405 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10406 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10408 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10409 Opc == X86ISD::BT) { // FIXME
10413 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10414 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10415 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10416 Cond.getOperand(0).getValueType() != MVT::i8)) {
10417 SDValue LHS = Cond.getOperand(0);
10418 SDValue RHS = Cond.getOperand(1);
10419 unsigned X86Opcode;
10422 switch (CondOpcode) {
10423 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10424 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10425 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10426 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10427 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10428 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10429 default: llvm_unreachable("unexpected overflowing operator");
10431 if (CondOpcode == ISD::UMULO)
10432 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10435 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10437 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10439 if (CondOpcode == ISD::UMULO)
10440 Cond = X86Op.getValue(2);
10442 Cond = X86Op.getValue(1);
10444 CC = DAG.getConstant(X86Cond, MVT::i8);
10449 // Look pass the truncate if the high bits are known zero.
10450 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10451 Cond = Cond.getOperand(0);
10453 // We know the result of AND is compared against zero. Try to match
10455 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10456 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10457 if (NewSetCC.getNode()) {
10458 CC = NewSetCC.getOperand(0);
10459 Cond = NewSetCC.getOperand(1);
10466 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10467 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10470 // a < b ? -1 : 0 -> RES = ~setcc_carry
10471 // a < b ? 0 : -1 -> RES = setcc_carry
10472 // a >= b ? -1 : 0 -> RES = setcc_carry
10473 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10474 if (Cond.getOpcode() == X86ISD::SUB) {
10475 Cond = ConvertCmpIfNecessary(Cond, DAG);
10476 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10478 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10479 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10480 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10481 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10482 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10483 return DAG.getNOT(DL, Res, Res.getValueType());
10488 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10489 // widen the cmov and push the truncate through. This avoids introducing a new
10490 // branch during isel and doesn't add any extensions.
10491 if (Op.getValueType() == MVT::i8 &&
10492 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10493 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10494 if (T1.getValueType() == T2.getValueType() &&
10495 // Blacklist CopyFromReg to avoid partial register stalls.
10496 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10497 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10498 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10499 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10503 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10504 // condition is true.
10505 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10506 SDValue Ops[] = { Op2, Op1, CC, Cond };
10507 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10510 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10511 MVT VT = Op->getSimpleValueType(0);
10512 SDValue In = Op->getOperand(0);
10513 MVT InVT = In.getSimpleValueType();
10516 unsigned int NumElts = VT.getVectorNumElements();
10517 if (NumElts != 8 && NumElts != 16)
10520 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10521 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10523 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10524 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10526 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10527 Constant *C = ConstantInt::get(*DAG.getContext(),
10528 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10530 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10531 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10532 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10533 MachinePointerInfo::getConstantPool(),
10534 false, false, false, Alignment);
10535 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10536 if (VT.is512BitVector())
10538 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10541 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10542 SelectionDAG &DAG) {
10543 MVT VT = Op->getSimpleValueType(0);
10544 SDValue In = Op->getOperand(0);
10545 MVT InVT = In.getSimpleValueType();
10548 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10549 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10551 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10552 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10553 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10556 if (Subtarget->hasInt256())
10557 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10559 // Optimize vectors in AVX mode
10560 // Sign extend v8i16 to v8i32 and
10563 // Divide input vector into two parts
10564 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10565 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10566 // concat the vectors to original VT
10568 unsigned NumElems = InVT.getVectorNumElements();
10569 SDValue Undef = DAG.getUNDEF(InVT);
10571 SmallVector<int,8> ShufMask1(NumElems, -1);
10572 for (unsigned i = 0; i != NumElems/2; ++i)
10575 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10577 SmallVector<int,8> ShufMask2(NumElems, -1);
10578 for (unsigned i = 0; i != NumElems/2; ++i)
10579 ShufMask2[i] = i + NumElems/2;
10581 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10583 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10584 VT.getVectorNumElements()/2);
10586 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10587 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10589 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10592 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10593 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10594 // from the AND / OR.
10595 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10596 Opc = Op.getOpcode();
10597 if (Opc != ISD::OR && Opc != ISD::AND)
10599 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10600 Op.getOperand(0).hasOneUse() &&
10601 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10602 Op.getOperand(1).hasOneUse());
10605 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10606 // 1 and that the SETCC node has a single use.
10607 static bool isXor1OfSetCC(SDValue Op) {
10608 if (Op.getOpcode() != ISD::XOR)
10610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10611 if (N1C && N1C->getAPIntValue() == 1) {
10612 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10613 Op.getOperand(0).hasOneUse();
10618 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10619 bool addTest = true;
10620 SDValue Chain = Op.getOperand(0);
10621 SDValue Cond = Op.getOperand(1);
10622 SDValue Dest = Op.getOperand(2);
10625 bool Inverted = false;
10627 if (Cond.getOpcode() == ISD::SETCC) {
10628 // Check for setcc([su]{add,sub,mul}o == 0).
10629 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10630 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10631 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10632 Cond.getOperand(0).getResNo() == 1 &&
10633 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10634 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10635 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10636 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10637 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10638 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10640 Cond = Cond.getOperand(0);
10642 SDValue NewCond = LowerSETCC(Cond, DAG);
10643 if (NewCond.getNode())
10648 // FIXME: LowerXALUO doesn't handle these!!
10649 else if (Cond.getOpcode() == X86ISD::ADD ||
10650 Cond.getOpcode() == X86ISD::SUB ||
10651 Cond.getOpcode() == X86ISD::SMUL ||
10652 Cond.getOpcode() == X86ISD::UMUL)
10653 Cond = LowerXALUO(Cond, DAG);
10656 // Look pass (and (setcc_carry (cmp ...)), 1).
10657 if (Cond.getOpcode() == ISD::AND &&
10658 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10659 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10660 if (C && C->getAPIntValue() == 1)
10661 Cond = Cond.getOperand(0);
10664 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10665 // setting operand in place of the X86ISD::SETCC.
10666 unsigned CondOpcode = Cond.getOpcode();
10667 if (CondOpcode == X86ISD::SETCC ||
10668 CondOpcode == X86ISD::SETCC_CARRY) {
10669 CC = Cond.getOperand(0);
10671 SDValue Cmp = Cond.getOperand(1);
10672 unsigned Opc = Cmp.getOpcode();
10673 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10674 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10678 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10682 // These can only come from an arithmetic instruction with overflow,
10683 // e.g. SADDO, UADDO.
10684 Cond = Cond.getNode()->getOperand(1);
10690 CondOpcode = Cond.getOpcode();
10691 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10692 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10693 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10694 Cond.getOperand(0).getValueType() != MVT::i8)) {
10695 SDValue LHS = Cond.getOperand(0);
10696 SDValue RHS = Cond.getOperand(1);
10697 unsigned X86Opcode;
10700 switch (CondOpcode) {
10701 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10702 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10703 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10704 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10705 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10706 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10707 default: llvm_unreachable("unexpected overflowing operator");
10710 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10711 if (CondOpcode == ISD::UMULO)
10712 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10715 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10717 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10719 if (CondOpcode == ISD::UMULO)
10720 Cond = X86Op.getValue(2);
10722 Cond = X86Op.getValue(1);
10724 CC = DAG.getConstant(X86Cond, MVT::i8);
10728 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10729 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10730 if (CondOpc == ISD::OR) {
10731 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10732 // two branches instead of an explicit OR instruction with a
10734 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10735 isX86LogicalCmp(Cmp)) {
10736 CC = Cond.getOperand(0).getOperand(0);
10737 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10738 Chain, Dest, CC, Cmp);
10739 CC = Cond.getOperand(1).getOperand(0);
10743 } else { // ISD::AND
10744 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10745 // two branches instead of an explicit AND instruction with a
10746 // separate test. However, we only do this if this block doesn't
10747 // have a fall-through edge, because this requires an explicit
10748 // jmp when the condition is false.
10749 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10750 isX86LogicalCmp(Cmp) &&
10751 Op.getNode()->hasOneUse()) {
10752 X86::CondCode CCode =
10753 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10754 CCode = X86::GetOppositeBranchCondition(CCode);
10755 CC = DAG.getConstant(CCode, MVT::i8);
10756 SDNode *User = *Op.getNode()->use_begin();
10757 // Look for an unconditional branch following this conditional branch.
10758 // We need this because we need to reverse the successors in order
10759 // to implement FCMP_OEQ.
10760 if (User->getOpcode() == ISD::BR) {
10761 SDValue FalseBB = User->getOperand(1);
10763 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10764 assert(NewBR == User);
10768 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10769 Chain, Dest, CC, Cmp);
10770 X86::CondCode CCode =
10771 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10772 CCode = X86::GetOppositeBranchCondition(CCode);
10773 CC = DAG.getConstant(CCode, MVT::i8);
10779 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10780 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10781 // It should be transformed during dag combiner except when the condition
10782 // is set by a arithmetics with overflow node.
10783 X86::CondCode CCode =
10784 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10785 CCode = X86::GetOppositeBranchCondition(CCode);
10786 CC = DAG.getConstant(CCode, MVT::i8);
10787 Cond = Cond.getOperand(0).getOperand(1);
10789 } else if (Cond.getOpcode() == ISD::SETCC &&
10790 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10791 // For FCMP_OEQ, we can emit
10792 // two branches instead of an explicit AND instruction with a
10793 // separate test. However, we only do this if this block doesn't
10794 // have a fall-through edge, because this requires an explicit
10795 // jmp when the condition is false.
10796 if (Op.getNode()->hasOneUse()) {
10797 SDNode *User = *Op.getNode()->use_begin();
10798 // Look for an unconditional branch following this conditional branch.
10799 // We need this because we need to reverse the successors in order
10800 // to implement FCMP_OEQ.
10801 if (User->getOpcode() == ISD::BR) {
10802 SDValue FalseBB = User->getOperand(1);
10804 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10805 assert(NewBR == User);
10809 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10810 Cond.getOperand(0), Cond.getOperand(1));
10811 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10812 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10813 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10814 Chain, Dest, CC, Cmp);
10815 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10820 } else if (Cond.getOpcode() == ISD::SETCC &&
10821 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10822 // For FCMP_UNE, we can emit
10823 // two branches instead of an explicit AND instruction with a
10824 // separate test. However, we only do this if this block doesn't
10825 // have a fall-through edge, because this requires an explicit
10826 // jmp when the condition is false.
10827 if (Op.getNode()->hasOneUse()) {
10828 SDNode *User = *Op.getNode()->use_begin();
10829 // Look for an unconditional branch following this conditional branch.
10830 // We need this because we need to reverse the successors in order
10831 // to implement FCMP_UNE.
10832 if (User->getOpcode() == ISD::BR) {
10833 SDValue FalseBB = User->getOperand(1);
10835 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10836 assert(NewBR == User);
10839 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10840 Cond.getOperand(0), Cond.getOperand(1));
10841 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10842 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10843 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10844 Chain, Dest, CC, Cmp);
10845 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10855 // Look pass the truncate if the high bits are known zero.
10856 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10857 Cond = Cond.getOperand(0);
10859 // We know the result of AND is compared against zero. Try to match
10861 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10862 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10863 if (NewSetCC.getNode()) {
10864 CC = NewSetCC.getOperand(0);
10865 Cond = NewSetCC.getOperand(1);
10872 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10873 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10875 Cond = ConvertCmpIfNecessary(Cond, DAG);
10876 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10877 Chain, Dest, CC, Cond);
10880 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10881 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10882 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10883 // that the guard pages used by the OS virtual memory manager are allocated in
10884 // correct sequence.
10886 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10887 SelectionDAG &DAG) const {
10888 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10889 getTargetMachine().Options.EnableSegmentedStacks) &&
10890 "This should be used only on Windows targets or when segmented stacks "
10892 assert(!Subtarget->isTargetMacho() && "Not implemented");
10896 SDValue Chain = Op.getOperand(0);
10897 SDValue Size = Op.getOperand(1);
10898 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10899 EVT VT = Op.getNode()->getValueType(0);
10901 bool Is64Bit = Subtarget->is64Bit();
10902 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10904 if (getTargetMachine().Options.EnableSegmentedStacks) {
10905 MachineFunction &MF = DAG.getMachineFunction();
10906 MachineRegisterInfo &MRI = MF.getRegInfo();
10909 // The 64 bit implementation of segmented stacks needs to clobber both r10
10910 // r11. This makes it impossible to use it along with nested parameters.
10911 const Function *F = MF.getFunction();
10913 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10915 if (I->hasNestAttr())
10916 report_fatal_error("Cannot use segmented stacks with functions that "
10917 "have nested arguments.");
10920 const TargetRegisterClass *AddrRegClass =
10921 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10922 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10923 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10924 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10925 DAG.getRegister(Vreg, SPTy));
10926 SDValue Ops1[2] = { Value, Chain };
10927 return DAG.getMergeValues(Ops1, 2, dl);
10930 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10932 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10933 Flag = Chain.getValue(1);
10934 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10936 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10938 const X86RegisterInfo *RegInfo =
10939 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10940 unsigned SPReg = RegInfo->getStackRegister();
10941 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10942 Chain = SP.getValue(1);
10945 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10946 DAG.getConstant(-(uint64_t)Align, VT));
10947 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10950 SDValue Ops1[2] = { SP, Chain };
10951 return DAG.getMergeValues(Ops1, 2, dl);
10955 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10956 MachineFunction &MF = DAG.getMachineFunction();
10957 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10959 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10962 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10963 // vastart just stores the address of the VarArgsFrameIndex slot into the
10964 // memory location argument.
10965 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10967 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10968 MachinePointerInfo(SV), false, false, 0);
10972 // gp_offset (0 - 6 * 8)
10973 // fp_offset (48 - 48 + 8 * 16)
10974 // overflow_arg_area (point to parameters coming in memory).
10976 SmallVector<SDValue, 8> MemOps;
10977 SDValue FIN = Op.getOperand(1);
10979 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10980 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10982 FIN, MachinePointerInfo(SV), false, false, 0);
10983 MemOps.push_back(Store);
10986 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10987 FIN, DAG.getIntPtrConstant(4));
10988 Store = DAG.getStore(Op.getOperand(0), DL,
10989 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10991 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10992 MemOps.push_back(Store);
10994 // Store ptr to overflow_arg_area
10995 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10996 FIN, DAG.getIntPtrConstant(4));
10997 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10999 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11000 MachinePointerInfo(SV, 8),
11002 MemOps.push_back(Store);
11004 // Store ptr to reg_save_area.
11005 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11006 FIN, DAG.getIntPtrConstant(8));
11007 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11009 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11010 MachinePointerInfo(SV, 16), false, false, 0);
11011 MemOps.push_back(Store);
11012 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11013 &MemOps[0], MemOps.size());
11016 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11017 assert(Subtarget->is64Bit() &&
11018 "LowerVAARG only handles 64-bit va_arg!");
11019 assert((Subtarget->isTargetLinux() ||
11020 Subtarget->isTargetDarwin()) &&
11021 "Unhandled target in LowerVAARG");
11022 assert(Op.getNode()->getNumOperands() == 4);
11023 SDValue Chain = Op.getOperand(0);
11024 SDValue SrcPtr = Op.getOperand(1);
11025 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11026 unsigned Align = Op.getConstantOperandVal(3);
11029 EVT ArgVT = Op.getNode()->getValueType(0);
11030 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11031 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11034 // Decide which area this value should be read from.
11035 // TODO: Implement the AMD64 ABI in its entirety. This simple
11036 // selection mechanism works only for the basic types.
11037 if (ArgVT == MVT::f80) {
11038 llvm_unreachable("va_arg for f80 not yet implemented");
11039 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11040 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11041 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11042 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11044 llvm_unreachable("Unhandled argument type in LowerVAARG");
11047 if (ArgMode == 2) {
11048 // Sanity Check: Make sure using fp_offset makes sense.
11049 assert(!getTargetMachine().Options.UseSoftFloat &&
11050 !(DAG.getMachineFunction()
11051 .getFunction()->getAttributes()
11052 .hasAttribute(AttributeSet::FunctionIndex,
11053 Attribute::NoImplicitFloat)) &&
11054 Subtarget->hasSSE1());
11057 // Insert VAARG_64 node into the DAG
11058 // VAARG_64 returns two values: Variable Argument Address, Chain
11059 SmallVector<SDValue, 11> InstOps;
11060 InstOps.push_back(Chain);
11061 InstOps.push_back(SrcPtr);
11062 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11063 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11064 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11065 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11066 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11067 VTs, &InstOps[0], InstOps.size(),
11069 MachinePointerInfo(SV),
11071 /*Volatile=*/false,
11073 /*WriteMem=*/true);
11074 Chain = VAARG.getValue(1);
11076 // Load the next argument and return it
11077 return DAG.getLoad(ArgVT, dl,
11080 MachinePointerInfo(),
11081 false, false, false, 0);
11084 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11085 SelectionDAG &DAG) {
11086 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11087 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11088 SDValue Chain = Op.getOperand(0);
11089 SDValue DstPtr = Op.getOperand(1);
11090 SDValue SrcPtr = Op.getOperand(2);
11091 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11092 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11095 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11096 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11098 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11101 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11102 // amount is a constant. Takes immediate version of shift as input.
11103 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
11104 SDValue SrcOp, uint64_t ShiftAmt,
11105 SelectionDAG &DAG) {
11106 EVT ElementType = VT.getVectorElementType();
11108 // Check for ShiftAmt >= element width
11109 if (ShiftAmt >= ElementType.getSizeInBits()) {
11110 if (Opc == X86ISD::VSRAI)
11111 ShiftAmt = ElementType.getSizeInBits() - 1;
11113 return DAG.getConstant(0, VT);
11116 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11117 && "Unknown target vector shift-by-constant node");
11119 // Fold this packed vector shift into a build vector if SrcOp is a
11120 // vector of ConstantSDNodes or UNDEFs.
11121 if (ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11122 SmallVector<SDValue, 8> Elts;
11123 unsigned NumElts = SrcOp->getNumOperands();
11124 ConstantSDNode *ND;
11127 default: llvm_unreachable(0);
11128 case X86ISD::VSHLI:
11129 for (unsigned i=0; i!=NumElts; ++i) {
11130 SDValue CurrentOp = SrcOp->getOperand(i);
11131 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11132 Elts.push_back(CurrentOp);
11135 ND = cast<ConstantSDNode>(CurrentOp);
11136 const APInt &C = ND->getAPIntValue();
11137 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11140 case X86ISD::VSRLI:
11141 for (unsigned i=0; i!=NumElts; ++i) {
11142 SDValue CurrentOp = SrcOp->getOperand(i);
11143 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11144 Elts.push_back(CurrentOp);
11147 ND = cast<ConstantSDNode>(CurrentOp);
11148 const APInt &C = ND->getAPIntValue();
11149 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11152 case X86ISD::VSRAI:
11153 for (unsigned i=0; i!=NumElts; ++i) {
11154 SDValue CurrentOp = SrcOp->getOperand(i);
11155 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11156 Elts.push_back(CurrentOp);
11159 ND = cast<ConstantSDNode>(CurrentOp);
11160 const APInt &C = ND->getAPIntValue();
11161 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11166 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
11169 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11172 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11173 // may or may not be a constant. Takes immediate version of shift as input.
11174 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
11175 SDValue SrcOp, SDValue ShAmt,
11176 SelectionDAG &DAG) {
11177 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11179 // Catch shift-by-constant.
11180 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11181 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11182 CShAmt->getZExtValue(), DAG);
11184 // Change opcode to non-immediate version
11186 default: llvm_unreachable("Unknown target vector shift node");
11187 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11188 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11189 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11192 // Need to build a vector containing shift amount
11193 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11196 ShOps[1] = DAG.getConstant(0, MVT::i32);
11197 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11198 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11200 // The return type has to be a 128-bit type with the same element
11201 // type as the input type.
11202 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11203 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11205 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11206 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11209 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11211 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11213 default: return SDValue(); // Don't custom lower most intrinsics.
11214 // Comparison intrinsics.
11215 case Intrinsic::x86_sse_comieq_ss:
11216 case Intrinsic::x86_sse_comilt_ss:
11217 case Intrinsic::x86_sse_comile_ss:
11218 case Intrinsic::x86_sse_comigt_ss:
11219 case Intrinsic::x86_sse_comige_ss:
11220 case Intrinsic::x86_sse_comineq_ss:
11221 case Intrinsic::x86_sse_ucomieq_ss:
11222 case Intrinsic::x86_sse_ucomilt_ss:
11223 case Intrinsic::x86_sse_ucomile_ss:
11224 case Intrinsic::x86_sse_ucomigt_ss:
11225 case Intrinsic::x86_sse_ucomige_ss:
11226 case Intrinsic::x86_sse_ucomineq_ss:
11227 case Intrinsic::x86_sse2_comieq_sd:
11228 case Intrinsic::x86_sse2_comilt_sd:
11229 case Intrinsic::x86_sse2_comile_sd:
11230 case Intrinsic::x86_sse2_comigt_sd:
11231 case Intrinsic::x86_sse2_comige_sd:
11232 case Intrinsic::x86_sse2_comineq_sd:
11233 case Intrinsic::x86_sse2_ucomieq_sd:
11234 case Intrinsic::x86_sse2_ucomilt_sd:
11235 case Intrinsic::x86_sse2_ucomile_sd:
11236 case Intrinsic::x86_sse2_ucomigt_sd:
11237 case Intrinsic::x86_sse2_ucomige_sd:
11238 case Intrinsic::x86_sse2_ucomineq_sd: {
11242 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11243 case Intrinsic::x86_sse_comieq_ss:
11244 case Intrinsic::x86_sse2_comieq_sd:
11245 Opc = X86ISD::COMI;
11248 case Intrinsic::x86_sse_comilt_ss:
11249 case Intrinsic::x86_sse2_comilt_sd:
11250 Opc = X86ISD::COMI;
11253 case Intrinsic::x86_sse_comile_ss:
11254 case Intrinsic::x86_sse2_comile_sd:
11255 Opc = X86ISD::COMI;
11258 case Intrinsic::x86_sse_comigt_ss:
11259 case Intrinsic::x86_sse2_comigt_sd:
11260 Opc = X86ISD::COMI;
11263 case Intrinsic::x86_sse_comige_ss:
11264 case Intrinsic::x86_sse2_comige_sd:
11265 Opc = X86ISD::COMI;
11268 case Intrinsic::x86_sse_comineq_ss:
11269 case Intrinsic::x86_sse2_comineq_sd:
11270 Opc = X86ISD::COMI;
11273 case Intrinsic::x86_sse_ucomieq_ss:
11274 case Intrinsic::x86_sse2_ucomieq_sd:
11275 Opc = X86ISD::UCOMI;
11278 case Intrinsic::x86_sse_ucomilt_ss:
11279 case Intrinsic::x86_sse2_ucomilt_sd:
11280 Opc = X86ISD::UCOMI;
11283 case Intrinsic::x86_sse_ucomile_ss:
11284 case Intrinsic::x86_sse2_ucomile_sd:
11285 Opc = X86ISD::UCOMI;
11288 case Intrinsic::x86_sse_ucomigt_ss:
11289 case Intrinsic::x86_sse2_ucomigt_sd:
11290 Opc = X86ISD::UCOMI;
11293 case Intrinsic::x86_sse_ucomige_ss:
11294 case Intrinsic::x86_sse2_ucomige_sd:
11295 Opc = X86ISD::UCOMI;
11298 case Intrinsic::x86_sse_ucomineq_ss:
11299 case Intrinsic::x86_sse2_ucomineq_sd:
11300 Opc = X86ISD::UCOMI;
11305 SDValue LHS = Op.getOperand(1);
11306 SDValue RHS = Op.getOperand(2);
11307 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11308 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11309 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11310 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11311 DAG.getConstant(X86CC, MVT::i8), Cond);
11312 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11315 // Arithmetic intrinsics.
11316 case Intrinsic::x86_sse2_pmulu_dq:
11317 case Intrinsic::x86_avx2_pmulu_dq:
11318 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11319 Op.getOperand(1), Op.getOperand(2));
11321 // SSE2/AVX2 sub with unsigned saturation intrinsics
11322 case Intrinsic::x86_sse2_psubus_b:
11323 case Intrinsic::x86_sse2_psubus_w:
11324 case Intrinsic::x86_avx2_psubus_b:
11325 case Intrinsic::x86_avx2_psubus_w:
11326 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11327 Op.getOperand(1), Op.getOperand(2));
11329 // SSE3/AVX horizontal add/sub intrinsics
11330 case Intrinsic::x86_sse3_hadd_ps:
11331 case Intrinsic::x86_sse3_hadd_pd:
11332 case Intrinsic::x86_avx_hadd_ps_256:
11333 case Intrinsic::x86_avx_hadd_pd_256:
11334 case Intrinsic::x86_sse3_hsub_ps:
11335 case Intrinsic::x86_sse3_hsub_pd:
11336 case Intrinsic::x86_avx_hsub_ps_256:
11337 case Intrinsic::x86_avx_hsub_pd_256:
11338 case Intrinsic::x86_ssse3_phadd_w_128:
11339 case Intrinsic::x86_ssse3_phadd_d_128:
11340 case Intrinsic::x86_avx2_phadd_w:
11341 case Intrinsic::x86_avx2_phadd_d:
11342 case Intrinsic::x86_ssse3_phsub_w_128:
11343 case Intrinsic::x86_ssse3_phsub_d_128:
11344 case Intrinsic::x86_avx2_phsub_w:
11345 case Intrinsic::x86_avx2_phsub_d: {
11348 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11349 case Intrinsic::x86_sse3_hadd_ps:
11350 case Intrinsic::x86_sse3_hadd_pd:
11351 case Intrinsic::x86_avx_hadd_ps_256:
11352 case Intrinsic::x86_avx_hadd_pd_256:
11353 Opcode = X86ISD::FHADD;
11355 case Intrinsic::x86_sse3_hsub_ps:
11356 case Intrinsic::x86_sse3_hsub_pd:
11357 case Intrinsic::x86_avx_hsub_ps_256:
11358 case Intrinsic::x86_avx_hsub_pd_256:
11359 Opcode = X86ISD::FHSUB;
11361 case Intrinsic::x86_ssse3_phadd_w_128:
11362 case Intrinsic::x86_ssse3_phadd_d_128:
11363 case Intrinsic::x86_avx2_phadd_w:
11364 case Intrinsic::x86_avx2_phadd_d:
11365 Opcode = X86ISD::HADD;
11367 case Intrinsic::x86_ssse3_phsub_w_128:
11368 case Intrinsic::x86_ssse3_phsub_d_128:
11369 case Intrinsic::x86_avx2_phsub_w:
11370 case Intrinsic::x86_avx2_phsub_d:
11371 Opcode = X86ISD::HSUB;
11374 return DAG.getNode(Opcode, dl, Op.getValueType(),
11375 Op.getOperand(1), Op.getOperand(2));
11378 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11379 case Intrinsic::x86_sse2_pmaxu_b:
11380 case Intrinsic::x86_sse41_pmaxuw:
11381 case Intrinsic::x86_sse41_pmaxud:
11382 case Intrinsic::x86_avx2_pmaxu_b:
11383 case Intrinsic::x86_avx2_pmaxu_w:
11384 case Intrinsic::x86_avx2_pmaxu_d:
11385 case Intrinsic::x86_avx512_pmaxu_d:
11386 case Intrinsic::x86_avx512_pmaxu_q:
11387 case Intrinsic::x86_sse2_pminu_b:
11388 case Intrinsic::x86_sse41_pminuw:
11389 case Intrinsic::x86_sse41_pminud:
11390 case Intrinsic::x86_avx2_pminu_b:
11391 case Intrinsic::x86_avx2_pminu_w:
11392 case Intrinsic::x86_avx2_pminu_d:
11393 case Intrinsic::x86_avx512_pminu_d:
11394 case Intrinsic::x86_avx512_pminu_q:
11395 case Intrinsic::x86_sse41_pmaxsb:
11396 case Intrinsic::x86_sse2_pmaxs_w:
11397 case Intrinsic::x86_sse41_pmaxsd:
11398 case Intrinsic::x86_avx2_pmaxs_b:
11399 case Intrinsic::x86_avx2_pmaxs_w:
11400 case Intrinsic::x86_avx2_pmaxs_d:
11401 case Intrinsic::x86_avx512_pmaxs_d:
11402 case Intrinsic::x86_avx512_pmaxs_q:
11403 case Intrinsic::x86_sse41_pminsb:
11404 case Intrinsic::x86_sse2_pmins_w:
11405 case Intrinsic::x86_sse41_pminsd:
11406 case Intrinsic::x86_avx2_pmins_b:
11407 case Intrinsic::x86_avx2_pmins_w:
11408 case Intrinsic::x86_avx2_pmins_d:
11409 case Intrinsic::x86_avx512_pmins_d:
11410 case Intrinsic::x86_avx512_pmins_q: {
11413 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11414 case Intrinsic::x86_sse2_pmaxu_b:
11415 case Intrinsic::x86_sse41_pmaxuw:
11416 case Intrinsic::x86_sse41_pmaxud:
11417 case Intrinsic::x86_avx2_pmaxu_b:
11418 case Intrinsic::x86_avx2_pmaxu_w:
11419 case Intrinsic::x86_avx2_pmaxu_d:
11420 case Intrinsic::x86_avx512_pmaxu_d:
11421 case Intrinsic::x86_avx512_pmaxu_q:
11422 Opcode = X86ISD::UMAX;
11424 case Intrinsic::x86_sse2_pminu_b:
11425 case Intrinsic::x86_sse41_pminuw:
11426 case Intrinsic::x86_sse41_pminud:
11427 case Intrinsic::x86_avx2_pminu_b:
11428 case Intrinsic::x86_avx2_pminu_w:
11429 case Intrinsic::x86_avx2_pminu_d:
11430 case Intrinsic::x86_avx512_pminu_d:
11431 case Intrinsic::x86_avx512_pminu_q:
11432 Opcode = X86ISD::UMIN;
11434 case Intrinsic::x86_sse41_pmaxsb:
11435 case Intrinsic::x86_sse2_pmaxs_w:
11436 case Intrinsic::x86_sse41_pmaxsd:
11437 case Intrinsic::x86_avx2_pmaxs_b:
11438 case Intrinsic::x86_avx2_pmaxs_w:
11439 case Intrinsic::x86_avx2_pmaxs_d:
11440 case Intrinsic::x86_avx512_pmaxs_d:
11441 case Intrinsic::x86_avx512_pmaxs_q:
11442 Opcode = X86ISD::SMAX;
11444 case Intrinsic::x86_sse41_pminsb:
11445 case Intrinsic::x86_sse2_pmins_w:
11446 case Intrinsic::x86_sse41_pminsd:
11447 case Intrinsic::x86_avx2_pmins_b:
11448 case Intrinsic::x86_avx2_pmins_w:
11449 case Intrinsic::x86_avx2_pmins_d:
11450 case Intrinsic::x86_avx512_pmins_d:
11451 case Intrinsic::x86_avx512_pmins_q:
11452 Opcode = X86ISD::SMIN;
11455 return DAG.getNode(Opcode, dl, Op.getValueType(),
11456 Op.getOperand(1), Op.getOperand(2));
11459 // SSE/SSE2/AVX floating point max/min intrinsics.
11460 case Intrinsic::x86_sse_max_ps:
11461 case Intrinsic::x86_sse2_max_pd:
11462 case Intrinsic::x86_avx_max_ps_256:
11463 case Intrinsic::x86_avx_max_pd_256:
11464 case Intrinsic::x86_avx512_max_ps_512:
11465 case Intrinsic::x86_avx512_max_pd_512:
11466 case Intrinsic::x86_sse_min_ps:
11467 case Intrinsic::x86_sse2_min_pd:
11468 case Intrinsic::x86_avx_min_ps_256:
11469 case Intrinsic::x86_avx_min_pd_256:
11470 case Intrinsic::x86_avx512_min_ps_512:
11471 case Intrinsic::x86_avx512_min_pd_512: {
11474 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11475 case Intrinsic::x86_sse_max_ps:
11476 case Intrinsic::x86_sse2_max_pd:
11477 case Intrinsic::x86_avx_max_ps_256:
11478 case Intrinsic::x86_avx_max_pd_256:
11479 case Intrinsic::x86_avx512_max_ps_512:
11480 case Intrinsic::x86_avx512_max_pd_512:
11481 Opcode = X86ISD::FMAX;
11483 case Intrinsic::x86_sse_min_ps:
11484 case Intrinsic::x86_sse2_min_pd:
11485 case Intrinsic::x86_avx_min_ps_256:
11486 case Intrinsic::x86_avx_min_pd_256:
11487 case Intrinsic::x86_avx512_min_ps_512:
11488 case Intrinsic::x86_avx512_min_pd_512:
11489 Opcode = X86ISD::FMIN;
11492 return DAG.getNode(Opcode, dl, Op.getValueType(),
11493 Op.getOperand(1), Op.getOperand(2));
11496 // AVX2 variable shift intrinsics
11497 case Intrinsic::x86_avx2_psllv_d:
11498 case Intrinsic::x86_avx2_psllv_q:
11499 case Intrinsic::x86_avx2_psllv_d_256:
11500 case Intrinsic::x86_avx2_psllv_q_256:
11501 case Intrinsic::x86_avx2_psrlv_d:
11502 case Intrinsic::x86_avx2_psrlv_q:
11503 case Intrinsic::x86_avx2_psrlv_d_256:
11504 case Intrinsic::x86_avx2_psrlv_q_256:
11505 case Intrinsic::x86_avx2_psrav_d:
11506 case Intrinsic::x86_avx2_psrav_d_256: {
11509 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11510 case Intrinsic::x86_avx2_psllv_d:
11511 case Intrinsic::x86_avx2_psllv_q:
11512 case Intrinsic::x86_avx2_psllv_d_256:
11513 case Intrinsic::x86_avx2_psllv_q_256:
11516 case Intrinsic::x86_avx2_psrlv_d:
11517 case Intrinsic::x86_avx2_psrlv_q:
11518 case Intrinsic::x86_avx2_psrlv_d_256:
11519 case Intrinsic::x86_avx2_psrlv_q_256:
11522 case Intrinsic::x86_avx2_psrav_d:
11523 case Intrinsic::x86_avx2_psrav_d_256:
11527 return DAG.getNode(Opcode, dl, Op.getValueType(),
11528 Op.getOperand(1), Op.getOperand(2));
11531 case Intrinsic::x86_ssse3_pshuf_b_128:
11532 case Intrinsic::x86_avx2_pshuf_b:
11533 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11534 Op.getOperand(1), Op.getOperand(2));
11536 case Intrinsic::x86_ssse3_psign_b_128:
11537 case Intrinsic::x86_ssse3_psign_w_128:
11538 case Intrinsic::x86_ssse3_psign_d_128:
11539 case Intrinsic::x86_avx2_psign_b:
11540 case Intrinsic::x86_avx2_psign_w:
11541 case Intrinsic::x86_avx2_psign_d:
11542 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11543 Op.getOperand(1), Op.getOperand(2));
11545 case Intrinsic::x86_sse41_insertps:
11546 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11547 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11549 case Intrinsic::x86_avx_vperm2f128_ps_256:
11550 case Intrinsic::x86_avx_vperm2f128_pd_256:
11551 case Intrinsic::x86_avx_vperm2f128_si_256:
11552 case Intrinsic::x86_avx2_vperm2i128:
11553 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11554 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11556 case Intrinsic::x86_avx2_permd:
11557 case Intrinsic::x86_avx2_permps:
11558 // Operands intentionally swapped. Mask is last operand to intrinsic,
11559 // but second operand for node/instruction.
11560 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11561 Op.getOperand(2), Op.getOperand(1));
11563 case Intrinsic::x86_sse_sqrt_ps:
11564 case Intrinsic::x86_sse2_sqrt_pd:
11565 case Intrinsic::x86_avx_sqrt_ps_256:
11566 case Intrinsic::x86_avx_sqrt_pd_256:
11567 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11569 // ptest and testp intrinsics. The intrinsic these come from are designed to
11570 // return an integer value, not just an instruction so lower it to the ptest
11571 // or testp pattern and a setcc for the result.
11572 case Intrinsic::x86_sse41_ptestz:
11573 case Intrinsic::x86_sse41_ptestc:
11574 case Intrinsic::x86_sse41_ptestnzc:
11575 case Intrinsic::x86_avx_ptestz_256:
11576 case Intrinsic::x86_avx_ptestc_256:
11577 case Intrinsic::x86_avx_ptestnzc_256:
11578 case Intrinsic::x86_avx_vtestz_ps:
11579 case Intrinsic::x86_avx_vtestc_ps:
11580 case Intrinsic::x86_avx_vtestnzc_ps:
11581 case Intrinsic::x86_avx_vtestz_pd:
11582 case Intrinsic::x86_avx_vtestc_pd:
11583 case Intrinsic::x86_avx_vtestnzc_pd:
11584 case Intrinsic::x86_avx_vtestz_ps_256:
11585 case Intrinsic::x86_avx_vtestc_ps_256:
11586 case Intrinsic::x86_avx_vtestnzc_ps_256:
11587 case Intrinsic::x86_avx_vtestz_pd_256:
11588 case Intrinsic::x86_avx_vtestc_pd_256:
11589 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11590 bool IsTestPacked = false;
11593 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11594 case Intrinsic::x86_avx_vtestz_ps:
11595 case Intrinsic::x86_avx_vtestz_pd:
11596 case Intrinsic::x86_avx_vtestz_ps_256:
11597 case Intrinsic::x86_avx_vtestz_pd_256:
11598 IsTestPacked = true; // Fallthrough
11599 case Intrinsic::x86_sse41_ptestz:
11600 case Intrinsic::x86_avx_ptestz_256:
11602 X86CC = X86::COND_E;
11604 case Intrinsic::x86_avx_vtestc_ps:
11605 case Intrinsic::x86_avx_vtestc_pd:
11606 case Intrinsic::x86_avx_vtestc_ps_256:
11607 case Intrinsic::x86_avx_vtestc_pd_256:
11608 IsTestPacked = true; // Fallthrough
11609 case Intrinsic::x86_sse41_ptestc:
11610 case Intrinsic::x86_avx_ptestc_256:
11612 X86CC = X86::COND_B;
11614 case Intrinsic::x86_avx_vtestnzc_ps:
11615 case Intrinsic::x86_avx_vtestnzc_pd:
11616 case Intrinsic::x86_avx_vtestnzc_ps_256:
11617 case Intrinsic::x86_avx_vtestnzc_pd_256:
11618 IsTestPacked = true; // Fallthrough
11619 case Intrinsic::x86_sse41_ptestnzc:
11620 case Intrinsic::x86_avx_ptestnzc_256:
11622 X86CC = X86::COND_A;
11626 SDValue LHS = Op.getOperand(1);
11627 SDValue RHS = Op.getOperand(2);
11628 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11629 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11630 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11631 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11632 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11634 case Intrinsic::x86_avx512_kortestz_w:
11635 case Intrinsic::x86_avx512_kortestc_w: {
11636 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11637 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11638 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11639 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11640 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11641 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
11642 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11645 // SSE/AVX shift intrinsics
11646 case Intrinsic::x86_sse2_psll_w:
11647 case Intrinsic::x86_sse2_psll_d:
11648 case Intrinsic::x86_sse2_psll_q:
11649 case Intrinsic::x86_avx2_psll_w:
11650 case Intrinsic::x86_avx2_psll_d:
11651 case Intrinsic::x86_avx2_psll_q:
11652 case Intrinsic::x86_sse2_psrl_w:
11653 case Intrinsic::x86_sse2_psrl_d:
11654 case Intrinsic::x86_sse2_psrl_q:
11655 case Intrinsic::x86_avx2_psrl_w:
11656 case Intrinsic::x86_avx2_psrl_d:
11657 case Intrinsic::x86_avx2_psrl_q:
11658 case Intrinsic::x86_sse2_psra_w:
11659 case Intrinsic::x86_sse2_psra_d:
11660 case Intrinsic::x86_avx2_psra_w:
11661 case Intrinsic::x86_avx2_psra_d: {
11664 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11665 case Intrinsic::x86_sse2_psll_w:
11666 case Intrinsic::x86_sse2_psll_d:
11667 case Intrinsic::x86_sse2_psll_q:
11668 case Intrinsic::x86_avx2_psll_w:
11669 case Intrinsic::x86_avx2_psll_d:
11670 case Intrinsic::x86_avx2_psll_q:
11671 Opcode = X86ISD::VSHL;
11673 case Intrinsic::x86_sse2_psrl_w:
11674 case Intrinsic::x86_sse2_psrl_d:
11675 case Intrinsic::x86_sse2_psrl_q:
11676 case Intrinsic::x86_avx2_psrl_w:
11677 case Intrinsic::x86_avx2_psrl_d:
11678 case Intrinsic::x86_avx2_psrl_q:
11679 Opcode = X86ISD::VSRL;
11681 case Intrinsic::x86_sse2_psra_w:
11682 case Intrinsic::x86_sse2_psra_d:
11683 case Intrinsic::x86_avx2_psra_w:
11684 case Intrinsic::x86_avx2_psra_d:
11685 Opcode = X86ISD::VSRA;
11688 return DAG.getNode(Opcode, dl, Op.getValueType(),
11689 Op.getOperand(1), Op.getOperand(2));
11692 // SSE/AVX immediate shift intrinsics
11693 case Intrinsic::x86_sse2_pslli_w:
11694 case Intrinsic::x86_sse2_pslli_d:
11695 case Intrinsic::x86_sse2_pslli_q:
11696 case Intrinsic::x86_avx2_pslli_w:
11697 case Intrinsic::x86_avx2_pslli_d:
11698 case Intrinsic::x86_avx2_pslli_q:
11699 case Intrinsic::x86_sse2_psrli_w:
11700 case Intrinsic::x86_sse2_psrli_d:
11701 case Intrinsic::x86_sse2_psrli_q:
11702 case Intrinsic::x86_avx2_psrli_w:
11703 case Intrinsic::x86_avx2_psrli_d:
11704 case Intrinsic::x86_avx2_psrli_q:
11705 case Intrinsic::x86_sse2_psrai_w:
11706 case Intrinsic::x86_sse2_psrai_d:
11707 case Intrinsic::x86_avx2_psrai_w:
11708 case Intrinsic::x86_avx2_psrai_d: {
11711 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11712 case Intrinsic::x86_sse2_pslli_w:
11713 case Intrinsic::x86_sse2_pslli_d:
11714 case Intrinsic::x86_sse2_pslli_q:
11715 case Intrinsic::x86_avx2_pslli_w:
11716 case Intrinsic::x86_avx2_pslli_d:
11717 case Intrinsic::x86_avx2_pslli_q:
11718 Opcode = X86ISD::VSHLI;
11720 case Intrinsic::x86_sse2_psrli_w:
11721 case Intrinsic::x86_sse2_psrli_d:
11722 case Intrinsic::x86_sse2_psrli_q:
11723 case Intrinsic::x86_avx2_psrli_w:
11724 case Intrinsic::x86_avx2_psrli_d:
11725 case Intrinsic::x86_avx2_psrli_q:
11726 Opcode = X86ISD::VSRLI;
11728 case Intrinsic::x86_sse2_psrai_w:
11729 case Intrinsic::x86_sse2_psrai_d:
11730 case Intrinsic::x86_avx2_psrai_w:
11731 case Intrinsic::x86_avx2_psrai_d:
11732 Opcode = X86ISD::VSRAI;
11735 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11736 Op.getOperand(1), Op.getOperand(2), DAG);
11739 case Intrinsic::x86_sse42_pcmpistria128:
11740 case Intrinsic::x86_sse42_pcmpestria128:
11741 case Intrinsic::x86_sse42_pcmpistric128:
11742 case Intrinsic::x86_sse42_pcmpestric128:
11743 case Intrinsic::x86_sse42_pcmpistrio128:
11744 case Intrinsic::x86_sse42_pcmpestrio128:
11745 case Intrinsic::x86_sse42_pcmpistris128:
11746 case Intrinsic::x86_sse42_pcmpestris128:
11747 case Intrinsic::x86_sse42_pcmpistriz128:
11748 case Intrinsic::x86_sse42_pcmpestriz128: {
11752 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11753 case Intrinsic::x86_sse42_pcmpistria128:
11754 Opcode = X86ISD::PCMPISTRI;
11755 X86CC = X86::COND_A;
11757 case Intrinsic::x86_sse42_pcmpestria128:
11758 Opcode = X86ISD::PCMPESTRI;
11759 X86CC = X86::COND_A;
11761 case Intrinsic::x86_sse42_pcmpistric128:
11762 Opcode = X86ISD::PCMPISTRI;
11763 X86CC = X86::COND_B;
11765 case Intrinsic::x86_sse42_pcmpestric128:
11766 Opcode = X86ISD::PCMPESTRI;
11767 X86CC = X86::COND_B;
11769 case Intrinsic::x86_sse42_pcmpistrio128:
11770 Opcode = X86ISD::PCMPISTRI;
11771 X86CC = X86::COND_O;
11773 case Intrinsic::x86_sse42_pcmpestrio128:
11774 Opcode = X86ISD::PCMPESTRI;
11775 X86CC = X86::COND_O;
11777 case Intrinsic::x86_sse42_pcmpistris128:
11778 Opcode = X86ISD::PCMPISTRI;
11779 X86CC = X86::COND_S;
11781 case Intrinsic::x86_sse42_pcmpestris128:
11782 Opcode = X86ISD::PCMPESTRI;
11783 X86CC = X86::COND_S;
11785 case Intrinsic::x86_sse42_pcmpistriz128:
11786 Opcode = X86ISD::PCMPISTRI;
11787 X86CC = X86::COND_E;
11789 case Intrinsic::x86_sse42_pcmpestriz128:
11790 Opcode = X86ISD::PCMPESTRI;
11791 X86CC = X86::COND_E;
11794 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11795 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11796 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11797 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11798 DAG.getConstant(X86CC, MVT::i8),
11799 SDValue(PCMP.getNode(), 1));
11800 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11803 case Intrinsic::x86_sse42_pcmpistri128:
11804 case Intrinsic::x86_sse42_pcmpestri128: {
11806 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11807 Opcode = X86ISD::PCMPISTRI;
11809 Opcode = X86ISD::PCMPESTRI;
11811 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11812 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11813 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11815 case Intrinsic::x86_fma_vfmadd_ps:
11816 case Intrinsic::x86_fma_vfmadd_pd:
11817 case Intrinsic::x86_fma_vfmsub_ps:
11818 case Intrinsic::x86_fma_vfmsub_pd:
11819 case Intrinsic::x86_fma_vfnmadd_ps:
11820 case Intrinsic::x86_fma_vfnmadd_pd:
11821 case Intrinsic::x86_fma_vfnmsub_ps:
11822 case Intrinsic::x86_fma_vfnmsub_pd:
11823 case Intrinsic::x86_fma_vfmaddsub_ps:
11824 case Intrinsic::x86_fma_vfmaddsub_pd:
11825 case Intrinsic::x86_fma_vfmsubadd_ps:
11826 case Intrinsic::x86_fma_vfmsubadd_pd:
11827 case Intrinsic::x86_fma_vfmadd_ps_256:
11828 case Intrinsic::x86_fma_vfmadd_pd_256:
11829 case Intrinsic::x86_fma_vfmsub_ps_256:
11830 case Intrinsic::x86_fma_vfmsub_pd_256:
11831 case Intrinsic::x86_fma_vfnmadd_ps_256:
11832 case Intrinsic::x86_fma_vfnmadd_pd_256:
11833 case Intrinsic::x86_fma_vfnmsub_ps_256:
11834 case Intrinsic::x86_fma_vfnmsub_pd_256:
11835 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11836 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11837 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11838 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11839 case Intrinsic::x86_fma_vfmadd_ps_512:
11840 case Intrinsic::x86_fma_vfmadd_pd_512:
11841 case Intrinsic::x86_fma_vfmsub_ps_512:
11842 case Intrinsic::x86_fma_vfmsub_pd_512:
11843 case Intrinsic::x86_fma_vfnmadd_ps_512:
11844 case Intrinsic::x86_fma_vfnmadd_pd_512:
11845 case Intrinsic::x86_fma_vfnmsub_ps_512:
11846 case Intrinsic::x86_fma_vfnmsub_pd_512:
11847 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11848 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11849 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11850 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11853 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11854 case Intrinsic::x86_fma_vfmadd_ps:
11855 case Intrinsic::x86_fma_vfmadd_pd:
11856 case Intrinsic::x86_fma_vfmadd_ps_256:
11857 case Intrinsic::x86_fma_vfmadd_pd_256:
11858 case Intrinsic::x86_fma_vfmadd_ps_512:
11859 case Intrinsic::x86_fma_vfmadd_pd_512:
11860 Opc = X86ISD::FMADD;
11862 case Intrinsic::x86_fma_vfmsub_ps:
11863 case Intrinsic::x86_fma_vfmsub_pd:
11864 case Intrinsic::x86_fma_vfmsub_ps_256:
11865 case Intrinsic::x86_fma_vfmsub_pd_256:
11866 case Intrinsic::x86_fma_vfmsub_ps_512:
11867 case Intrinsic::x86_fma_vfmsub_pd_512:
11868 Opc = X86ISD::FMSUB;
11870 case Intrinsic::x86_fma_vfnmadd_ps:
11871 case Intrinsic::x86_fma_vfnmadd_pd:
11872 case Intrinsic::x86_fma_vfnmadd_ps_256:
11873 case Intrinsic::x86_fma_vfnmadd_pd_256:
11874 case Intrinsic::x86_fma_vfnmadd_ps_512:
11875 case Intrinsic::x86_fma_vfnmadd_pd_512:
11876 Opc = X86ISD::FNMADD;
11878 case Intrinsic::x86_fma_vfnmsub_ps:
11879 case Intrinsic::x86_fma_vfnmsub_pd:
11880 case Intrinsic::x86_fma_vfnmsub_ps_256:
11881 case Intrinsic::x86_fma_vfnmsub_pd_256:
11882 case Intrinsic::x86_fma_vfnmsub_ps_512:
11883 case Intrinsic::x86_fma_vfnmsub_pd_512:
11884 Opc = X86ISD::FNMSUB;
11886 case Intrinsic::x86_fma_vfmaddsub_ps:
11887 case Intrinsic::x86_fma_vfmaddsub_pd:
11888 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11889 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11890 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11891 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11892 Opc = X86ISD::FMADDSUB;
11894 case Intrinsic::x86_fma_vfmsubadd_ps:
11895 case Intrinsic::x86_fma_vfmsubadd_pd:
11896 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11897 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11898 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11899 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11900 Opc = X86ISD::FMSUBADD;
11904 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11905 Op.getOperand(2), Op.getOperand(3));
11910 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11911 SDValue Base, SDValue Index,
11912 SDValue ScaleOp, SDValue Chain,
11913 const X86Subtarget * Subtarget) {
11915 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11916 assert(C && "Invalid scale type");
11917 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11918 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11919 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11920 Index.getValueType().getVectorNumElements());
11921 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11922 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11923 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11924 SDValue Segment = DAG.getRegister(0, MVT::i32);
11925 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11926 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11927 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11928 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11931 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11932 SDValue Src, SDValue Mask, SDValue Base,
11933 SDValue Index, SDValue ScaleOp, SDValue Chain,
11934 const X86Subtarget * Subtarget) {
11936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11937 assert(C && "Invalid scale type");
11938 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11939 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11940 Index.getValueType().getVectorNumElements());
11941 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11942 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11943 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11944 SDValue Segment = DAG.getRegister(0, MVT::i32);
11945 if (Src.getOpcode() == ISD::UNDEF)
11946 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11947 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11948 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11949 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11950 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11953 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11954 SDValue Src, SDValue Base, SDValue Index,
11955 SDValue ScaleOp, SDValue Chain) {
11957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11958 assert(C && "Invalid scale type");
11959 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11960 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11961 SDValue Segment = DAG.getRegister(0, MVT::i32);
11962 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11963 Index.getValueType().getVectorNumElements());
11964 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11965 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11966 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11967 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11968 return SDValue(Res, 1);
11971 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11972 SDValue Src, SDValue Mask, SDValue Base,
11973 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11975 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11976 assert(C && "Invalid scale type");
11977 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11978 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11979 SDValue Segment = DAG.getRegister(0, MVT::i32);
11980 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11981 Index.getValueType().getVectorNumElements());
11982 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11983 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11984 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11985 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11986 return SDValue(Res, 1);
11989 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11990 SelectionDAG &DAG) {
11992 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11994 default: return SDValue(); // Don't custom lower most intrinsics.
11996 // RDRAND/RDSEED intrinsics.
11997 case Intrinsic::x86_rdrand_16:
11998 case Intrinsic::x86_rdrand_32:
11999 case Intrinsic::x86_rdrand_64:
12000 case Intrinsic::x86_rdseed_16:
12001 case Intrinsic::x86_rdseed_32:
12002 case Intrinsic::x86_rdseed_64: {
12003 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
12004 IntNo == Intrinsic::x86_rdseed_32 ||
12005 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
12007 // Emit the node with the right value type.
12008 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12009 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
12011 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12012 // Otherwise return the value from Rand, which is always 0, casted to i32.
12013 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12014 DAG.getConstant(1, Op->getValueType(1)),
12015 DAG.getConstant(X86::COND_B, MVT::i32),
12016 SDValue(Result.getNode(), 1) };
12017 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12018 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12019 Ops, array_lengthof(Ops));
12021 // Return { result, isValid, chain }.
12022 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12023 SDValue(Result.getNode(), 2));
12025 //int_gather(index, base, scale);
12026 case Intrinsic::x86_avx512_gather_qpd_512:
12027 case Intrinsic::x86_avx512_gather_qps_512:
12028 case Intrinsic::x86_avx512_gather_dpd_512:
12029 case Intrinsic::x86_avx512_gather_qpi_512:
12030 case Intrinsic::x86_avx512_gather_qpq_512:
12031 case Intrinsic::x86_avx512_gather_dpq_512:
12032 case Intrinsic::x86_avx512_gather_dps_512:
12033 case Intrinsic::x86_avx512_gather_dpi_512: {
12036 default: llvm_unreachable("Unexpected intrinsic!");
12037 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
12038 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
12039 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
12040 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
12041 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
12042 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
12043 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
12044 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
12046 SDValue Chain = Op.getOperand(0);
12047 SDValue Index = Op.getOperand(2);
12048 SDValue Base = Op.getOperand(3);
12049 SDValue Scale = Op.getOperand(4);
12050 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
12052 //int_gather_mask(v1, mask, index, base, scale);
12053 case Intrinsic::x86_avx512_gather_qps_mask_512:
12054 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12055 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12056 case Intrinsic::x86_avx512_gather_dps_mask_512:
12057 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12058 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12059 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12060 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
12063 default: llvm_unreachable("Unexpected intrinsic!");
12064 case Intrinsic::x86_avx512_gather_qps_mask_512:
12065 Opc = X86::VGATHERQPSZrm; break;
12066 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12067 Opc = X86::VGATHERQPDZrm; break;
12068 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12069 Opc = X86::VGATHERDPDZrm; break;
12070 case Intrinsic::x86_avx512_gather_dps_mask_512:
12071 Opc = X86::VGATHERDPSZrm; break;
12072 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12073 Opc = X86::VPGATHERQDZrm; break;
12074 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12075 Opc = X86::VPGATHERQQZrm; break;
12076 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12077 Opc = X86::VPGATHERDDZrm; break;
12078 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12079 Opc = X86::VPGATHERDQZrm; break;
12081 SDValue Chain = Op.getOperand(0);
12082 SDValue Src = Op.getOperand(2);
12083 SDValue Mask = Op.getOperand(3);
12084 SDValue Index = Op.getOperand(4);
12085 SDValue Base = Op.getOperand(5);
12086 SDValue Scale = Op.getOperand(6);
12087 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12090 //int_scatter(base, index, v1, scale);
12091 case Intrinsic::x86_avx512_scatter_qpd_512:
12092 case Intrinsic::x86_avx512_scatter_qps_512:
12093 case Intrinsic::x86_avx512_scatter_dpd_512:
12094 case Intrinsic::x86_avx512_scatter_qpi_512:
12095 case Intrinsic::x86_avx512_scatter_qpq_512:
12096 case Intrinsic::x86_avx512_scatter_dpq_512:
12097 case Intrinsic::x86_avx512_scatter_dps_512:
12098 case Intrinsic::x86_avx512_scatter_dpi_512: {
12101 default: llvm_unreachable("Unexpected intrinsic!");
12102 case Intrinsic::x86_avx512_scatter_qpd_512:
12103 Opc = X86::VSCATTERQPDZmr; break;
12104 case Intrinsic::x86_avx512_scatter_qps_512:
12105 Opc = X86::VSCATTERQPSZmr; break;
12106 case Intrinsic::x86_avx512_scatter_dpd_512:
12107 Opc = X86::VSCATTERDPDZmr; break;
12108 case Intrinsic::x86_avx512_scatter_dps_512:
12109 Opc = X86::VSCATTERDPSZmr; break;
12110 case Intrinsic::x86_avx512_scatter_qpi_512:
12111 Opc = X86::VPSCATTERQDZmr; break;
12112 case Intrinsic::x86_avx512_scatter_qpq_512:
12113 Opc = X86::VPSCATTERQQZmr; break;
12114 case Intrinsic::x86_avx512_scatter_dpq_512:
12115 Opc = X86::VPSCATTERDQZmr; break;
12116 case Intrinsic::x86_avx512_scatter_dpi_512:
12117 Opc = X86::VPSCATTERDDZmr; break;
12119 SDValue Chain = Op.getOperand(0);
12120 SDValue Base = Op.getOperand(2);
12121 SDValue Index = Op.getOperand(3);
12122 SDValue Src = Op.getOperand(4);
12123 SDValue Scale = Op.getOperand(5);
12124 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12126 //int_scatter_mask(base, mask, index, v1, scale);
12127 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12128 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12129 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12130 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12131 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12132 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12133 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12134 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12137 default: llvm_unreachable("Unexpected intrinsic!");
12138 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12139 Opc = X86::VSCATTERQPDZmr; break;
12140 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12141 Opc = X86::VSCATTERQPSZmr; break;
12142 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12143 Opc = X86::VSCATTERDPDZmr; break;
12144 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12145 Opc = X86::VSCATTERDPSZmr; break;
12146 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12147 Opc = X86::VPSCATTERQDZmr; break;
12148 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12149 Opc = X86::VPSCATTERQQZmr; break;
12150 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12151 Opc = X86::VPSCATTERDQZmr; break;
12152 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12153 Opc = X86::VPSCATTERDDZmr; break;
12155 SDValue Chain = Op.getOperand(0);
12156 SDValue Base = Op.getOperand(2);
12157 SDValue Mask = Op.getOperand(3);
12158 SDValue Index = Op.getOperand(4);
12159 SDValue Src = Op.getOperand(5);
12160 SDValue Scale = Op.getOperand(6);
12161 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12163 // XTEST intrinsics.
12164 case Intrinsic::x86_xtest: {
12165 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12166 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12167 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12168 DAG.getConstant(X86::COND_NE, MVT::i8),
12170 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12171 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12172 Ret, SDValue(InTrans.getNode(), 1));
12177 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12178 SelectionDAG &DAG) const {
12179 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12180 MFI->setReturnAddressIsTaken(true);
12182 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12184 EVT PtrVT = getPointerTy();
12187 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12188 const X86RegisterInfo *RegInfo =
12189 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12190 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12191 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12192 DAG.getNode(ISD::ADD, dl, PtrVT,
12193 FrameAddr, Offset),
12194 MachinePointerInfo(), false, false, false, 0);
12197 // Just load the return address.
12198 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12199 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12200 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12203 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12204 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12205 MFI->setFrameAddressIsTaken(true);
12207 EVT VT = Op.getValueType();
12208 SDLoc dl(Op); // FIXME probably not meaningful
12209 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12210 const X86RegisterInfo *RegInfo =
12211 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12212 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12213 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12214 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12215 "Invalid Frame Register!");
12216 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12218 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12219 MachinePointerInfo(),
12220 false, false, false, 0);
12224 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12225 SelectionDAG &DAG) const {
12226 const X86RegisterInfo *RegInfo =
12227 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12228 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12231 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12232 SDValue Chain = Op.getOperand(0);
12233 SDValue Offset = Op.getOperand(1);
12234 SDValue Handler = Op.getOperand(2);
12237 EVT PtrVT = getPointerTy();
12238 const X86RegisterInfo *RegInfo =
12239 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12240 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12241 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12242 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12243 "Invalid Frame Register!");
12244 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12245 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12247 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12248 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12249 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12250 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12252 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12254 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12255 DAG.getRegister(StoreAddrReg, PtrVT));
12258 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12259 SelectionDAG &DAG) const {
12261 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12262 DAG.getVTList(MVT::i32, MVT::Other),
12263 Op.getOperand(0), Op.getOperand(1));
12266 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12267 SelectionDAG &DAG) const {
12269 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12270 Op.getOperand(0), Op.getOperand(1));
12273 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12274 return Op.getOperand(0);
12277 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12278 SelectionDAG &DAG) const {
12279 SDValue Root = Op.getOperand(0);
12280 SDValue Trmp = Op.getOperand(1); // trampoline
12281 SDValue FPtr = Op.getOperand(2); // nested function
12282 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12285 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12286 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12288 if (Subtarget->is64Bit()) {
12289 SDValue OutChains[6];
12291 // Large code-model.
12292 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12293 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12295 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12296 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12298 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12300 // Load the pointer to the nested function into R11.
12301 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12302 SDValue Addr = Trmp;
12303 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12304 Addr, MachinePointerInfo(TrmpAddr),
12307 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12308 DAG.getConstant(2, MVT::i64));
12309 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12310 MachinePointerInfo(TrmpAddr, 2),
12313 // Load the 'nest' parameter value into R10.
12314 // R10 is specified in X86CallingConv.td
12315 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12316 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12317 DAG.getConstant(10, MVT::i64));
12318 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12319 Addr, MachinePointerInfo(TrmpAddr, 10),
12322 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12323 DAG.getConstant(12, MVT::i64));
12324 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12325 MachinePointerInfo(TrmpAddr, 12),
12328 // Jump to the nested function.
12329 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12330 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12331 DAG.getConstant(20, MVT::i64));
12332 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12333 Addr, MachinePointerInfo(TrmpAddr, 20),
12336 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12337 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12338 DAG.getConstant(22, MVT::i64));
12339 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12340 MachinePointerInfo(TrmpAddr, 22),
12343 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12345 const Function *Func =
12346 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12347 CallingConv::ID CC = Func->getCallingConv();
12352 llvm_unreachable("Unsupported calling convention");
12353 case CallingConv::C:
12354 case CallingConv::X86_StdCall: {
12355 // Pass 'nest' parameter in ECX.
12356 // Must be kept in sync with X86CallingConv.td
12357 NestReg = X86::ECX;
12359 // Check that ECX wasn't needed by an 'inreg' parameter.
12360 FunctionType *FTy = Func->getFunctionType();
12361 const AttributeSet &Attrs = Func->getAttributes();
12363 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12364 unsigned InRegCount = 0;
12367 for (FunctionType::param_iterator I = FTy->param_begin(),
12368 E = FTy->param_end(); I != E; ++I, ++Idx)
12369 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12370 // FIXME: should only count parameters that are lowered to integers.
12371 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12373 if (InRegCount > 2) {
12374 report_fatal_error("Nest register in use - reduce number of inreg"
12380 case CallingConv::X86_FastCall:
12381 case CallingConv::X86_ThisCall:
12382 case CallingConv::Fast:
12383 // Pass 'nest' parameter in EAX.
12384 // Must be kept in sync with X86CallingConv.td
12385 NestReg = X86::EAX;
12389 SDValue OutChains[4];
12390 SDValue Addr, Disp;
12392 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12393 DAG.getConstant(10, MVT::i32));
12394 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12396 // This is storing the opcode for MOV32ri.
12397 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12398 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12399 OutChains[0] = DAG.getStore(Root, dl,
12400 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12401 Trmp, MachinePointerInfo(TrmpAddr),
12404 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12405 DAG.getConstant(1, MVT::i32));
12406 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12407 MachinePointerInfo(TrmpAddr, 1),
12410 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12411 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12412 DAG.getConstant(5, MVT::i32));
12413 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12414 MachinePointerInfo(TrmpAddr, 5),
12417 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12418 DAG.getConstant(6, MVT::i32));
12419 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12420 MachinePointerInfo(TrmpAddr, 6),
12423 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12427 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12428 SelectionDAG &DAG) const {
12430 The rounding mode is in bits 11:10 of FPSR, and has the following
12432 00 Round to nearest
12437 FLT_ROUNDS, on the other hand, expects the following:
12444 To perform the conversion, we do:
12445 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12448 MachineFunction &MF = DAG.getMachineFunction();
12449 const TargetMachine &TM = MF.getTarget();
12450 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12451 unsigned StackAlignment = TFI.getStackAlignment();
12452 EVT VT = Op.getValueType();
12455 // Save FP Control Word to stack slot
12456 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12457 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12459 MachineMemOperand *MMO =
12460 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12461 MachineMemOperand::MOStore, 2, 2);
12463 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12464 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12465 DAG.getVTList(MVT::Other),
12466 Ops, array_lengthof(Ops), MVT::i16,
12469 // Load FP Control Word from stack slot
12470 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12471 MachinePointerInfo(), false, false, false, 0);
12473 // Transform as necessary
12475 DAG.getNode(ISD::SRL, DL, MVT::i16,
12476 DAG.getNode(ISD::AND, DL, MVT::i16,
12477 CWD, DAG.getConstant(0x800, MVT::i16)),
12478 DAG.getConstant(11, MVT::i8));
12480 DAG.getNode(ISD::SRL, DL, MVT::i16,
12481 DAG.getNode(ISD::AND, DL, MVT::i16,
12482 CWD, DAG.getConstant(0x400, MVT::i16)),
12483 DAG.getConstant(9, MVT::i8));
12486 DAG.getNode(ISD::AND, DL, MVT::i16,
12487 DAG.getNode(ISD::ADD, DL, MVT::i16,
12488 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12489 DAG.getConstant(1, MVT::i16)),
12490 DAG.getConstant(3, MVT::i16));
12492 return DAG.getNode((VT.getSizeInBits() < 16 ?
12493 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12496 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12497 EVT VT = Op.getValueType();
12499 unsigned NumBits = VT.getSizeInBits();
12502 Op = Op.getOperand(0);
12503 if (VT == MVT::i8) {
12504 // Zero extend to i32 since there is not an i8 bsr.
12506 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12509 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12510 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12511 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12513 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12516 DAG.getConstant(NumBits+NumBits-1, OpVT),
12517 DAG.getConstant(X86::COND_E, MVT::i8),
12520 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12522 // Finally xor with NumBits-1.
12523 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12526 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12530 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12531 EVT VT = Op.getValueType();
12533 unsigned NumBits = VT.getSizeInBits();
12536 Op = Op.getOperand(0);
12537 if (VT == MVT::i8) {
12538 // Zero extend to i32 since there is not an i8 bsr.
12540 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12543 // Issue a bsr (scan bits in reverse).
12544 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12545 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12547 // And xor with NumBits-1.
12548 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12551 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12555 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12556 EVT VT = Op.getValueType();
12557 unsigned NumBits = VT.getSizeInBits();
12559 Op = Op.getOperand(0);
12561 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12562 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12563 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12565 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12568 DAG.getConstant(NumBits, VT),
12569 DAG.getConstant(X86::COND_E, MVT::i8),
12572 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12575 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12576 // ones, and then concatenate the result back.
12577 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12578 EVT VT = Op.getValueType();
12580 assert(VT.is256BitVector() && VT.isInteger() &&
12581 "Unsupported value type for operation");
12583 unsigned NumElems = VT.getVectorNumElements();
12586 // Extract the LHS vectors
12587 SDValue LHS = Op.getOperand(0);
12588 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12589 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12591 // Extract the RHS vectors
12592 SDValue RHS = Op.getOperand(1);
12593 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12594 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12596 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12597 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12599 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12600 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12601 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12604 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12605 assert(Op.getValueType().is256BitVector() &&
12606 Op.getValueType().isInteger() &&
12607 "Only handle AVX 256-bit vector integer operation");
12608 return Lower256IntArith(Op, DAG);
12611 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12612 assert(Op.getValueType().is256BitVector() &&
12613 Op.getValueType().isInteger() &&
12614 "Only handle AVX 256-bit vector integer operation");
12615 return Lower256IntArith(Op, DAG);
12618 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12619 SelectionDAG &DAG) {
12621 EVT VT = Op.getValueType();
12623 // Decompose 256-bit ops into smaller 128-bit ops.
12624 if (VT.is256BitVector() && !Subtarget->hasInt256())
12625 return Lower256IntArith(Op, DAG);
12627 SDValue A = Op.getOperand(0);
12628 SDValue B = Op.getOperand(1);
12630 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12631 if (VT == MVT::v4i32) {
12632 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12633 "Should not custom lower when pmuldq is available!");
12635 // Extract the odd parts.
12636 static const int UnpackMask[] = { 1, -1, 3, -1 };
12637 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12638 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12640 // Multiply the even parts.
12641 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12642 // Now multiply odd parts.
12643 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12645 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12646 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12648 // Merge the two vectors back together with a shuffle. This expands into 2
12650 static const int ShufMask[] = { 0, 4, 2, 6 };
12651 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12654 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12655 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12657 // Ahi = psrlqi(a, 32);
12658 // Bhi = psrlqi(b, 32);
12660 // AloBlo = pmuludq(a, b);
12661 // AloBhi = pmuludq(a, Bhi);
12662 // AhiBlo = pmuludq(Ahi, b);
12664 // AloBhi = psllqi(AloBhi, 32);
12665 // AhiBlo = psllqi(AhiBlo, 32);
12666 // return AloBlo + AloBhi + AhiBlo;
12668 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12669 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12671 // Bit cast to 32-bit vectors for MULUDQ
12672 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12673 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12674 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12675 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12676 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12677 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12679 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12680 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12681 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12683 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12684 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12686 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12687 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12690 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12691 EVT VT = Op.getValueType();
12692 EVT EltTy = VT.getVectorElementType();
12693 unsigned NumElts = VT.getVectorNumElements();
12694 SDValue N0 = Op.getOperand(0);
12697 // Lower sdiv X, pow2-const.
12698 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12702 APInt SplatValue, SplatUndef;
12703 unsigned SplatBitSize;
12705 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12707 EltTy.getSizeInBits() < SplatBitSize)
12710 if ((SplatValue != 0) &&
12711 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12712 unsigned Lg2 = SplatValue.countTrailingZeros();
12713 // Splat the sign bit.
12714 SmallVector<SDValue, 16> Sz(NumElts,
12715 DAG.getConstant(EltTy.getSizeInBits() - 1,
12717 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12718 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12720 // Add (N0 < 0) ? abs2 - 1 : 0;
12721 SmallVector<SDValue, 16> Amt(NumElts,
12722 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12724 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12725 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12727 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12728 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12729 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12730 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12733 // If we're dividing by a positive value, we're done. Otherwise, we must
12734 // negate the result.
12735 if (SplatValue.isNonNegative())
12738 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12739 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12740 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12745 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12746 const X86Subtarget *Subtarget) {
12747 EVT VT = Op.getValueType();
12749 SDValue R = Op.getOperand(0);
12750 SDValue Amt = Op.getOperand(1);
12752 // Optimize shl/srl/sra with constant shift amount.
12753 if (isSplatVector(Amt.getNode())) {
12754 SDValue SclrAmt = Amt->getOperand(0);
12755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12756 uint64_t ShiftAmt = C->getZExtValue();
12758 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12759 (Subtarget->hasInt256() &&
12760 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12761 (Subtarget->hasAVX512() &&
12762 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12763 if (Op.getOpcode() == ISD::SHL)
12764 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12766 if (Op.getOpcode() == ISD::SRL)
12767 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12769 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12770 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12774 if (VT == MVT::v16i8) {
12775 if (Op.getOpcode() == ISD::SHL) {
12776 // Make a large shift.
12777 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12778 MVT::v8i16, R, ShiftAmt,
12780 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12781 // Zero out the rightmost bits.
12782 SmallVector<SDValue, 16> V(16,
12783 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12785 return DAG.getNode(ISD::AND, dl, VT, SHL,
12786 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12788 if (Op.getOpcode() == ISD::SRL) {
12789 // Make a large shift.
12790 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12791 MVT::v8i16, R, ShiftAmt,
12793 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12794 // Zero out the leftmost bits.
12795 SmallVector<SDValue, 16> V(16,
12796 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12798 return DAG.getNode(ISD::AND, dl, VT, SRL,
12799 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12801 if (Op.getOpcode() == ISD::SRA) {
12802 if (ShiftAmt == 7) {
12803 // R s>> 7 === R s< 0
12804 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12805 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12808 // R s>> a === ((R u>> a) ^ m) - m
12809 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12810 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12812 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12813 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12814 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12817 llvm_unreachable("Unknown shift opcode.");
12820 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12821 if (Op.getOpcode() == ISD::SHL) {
12822 // Make a large shift.
12823 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12824 MVT::v16i16, R, ShiftAmt,
12826 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12827 // Zero out the rightmost bits.
12828 SmallVector<SDValue, 32> V(32,
12829 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12831 return DAG.getNode(ISD::AND, dl, VT, SHL,
12832 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12834 if (Op.getOpcode() == ISD::SRL) {
12835 // Make a large shift.
12836 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12837 MVT::v16i16, R, ShiftAmt,
12839 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12840 // Zero out the leftmost bits.
12841 SmallVector<SDValue, 32> V(32,
12842 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12844 return DAG.getNode(ISD::AND, dl, VT, SRL,
12845 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12847 if (Op.getOpcode() == ISD::SRA) {
12848 if (ShiftAmt == 7) {
12849 // R s>> 7 === R s< 0
12850 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12851 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12854 // R s>> a === ((R u>> a) ^ m) - m
12855 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12856 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12858 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12859 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12860 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12863 llvm_unreachable("Unknown shift opcode.");
12868 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12869 if (!Subtarget->is64Bit() &&
12870 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12871 Amt.getOpcode() == ISD::BITCAST &&
12872 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12873 Amt = Amt.getOperand(0);
12874 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12875 VT.getVectorNumElements();
12876 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12877 uint64_t ShiftAmt = 0;
12878 for (unsigned i = 0; i != Ratio; ++i) {
12879 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12883 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12885 // Check remaining shift amounts.
12886 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12887 uint64_t ShAmt = 0;
12888 for (unsigned j = 0; j != Ratio; ++j) {
12889 ConstantSDNode *C =
12890 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12894 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12896 if (ShAmt != ShiftAmt)
12899 switch (Op.getOpcode()) {
12901 llvm_unreachable("Unknown shift opcode!");
12903 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12906 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12909 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12917 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12918 const X86Subtarget* Subtarget) {
12919 EVT VT = Op.getValueType();
12921 SDValue R = Op.getOperand(0);
12922 SDValue Amt = Op.getOperand(1);
12924 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12925 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12926 (Subtarget->hasInt256() &&
12927 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12928 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12929 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12931 EVT EltVT = VT.getVectorElementType();
12933 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12934 unsigned NumElts = VT.getVectorNumElements();
12936 for (i = 0; i != NumElts; ++i) {
12937 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12941 for (j = i; j != NumElts; ++j) {
12942 SDValue Arg = Amt.getOperand(j);
12943 if (Arg.getOpcode() == ISD::UNDEF) continue;
12944 if (Arg != Amt.getOperand(i))
12947 if (i != NumElts && j == NumElts)
12948 BaseShAmt = Amt.getOperand(i);
12950 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12951 Amt = Amt.getOperand(0);
12952 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12953 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12954 SDValue InVec = Amt.getOperand(0);
12955 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12956 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12958 for (; i != NumElts; ++i) {
12959 SDValue Arg = InVec.getOperand(i);
12960 if (Arg.getOpcode() == ISD::UNDEF) continue;
12964 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12965 if (ConstantSDNode *C =
12966 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12967 unsigned SplatIdx =
12968 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12969 if (C->getZExtValue() == SplatIdx)
12970 BaseShAmt = InVec.getOperand(1);
12973 if (BaseShAmt.getNode() == 0)
12974 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12975 DAG.getIntPtrConstant(0));
12979 if (BaseShAmt.getNode()) {
12980 if (EltVT.bitsGT(MVT::i32))
12981 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12982 else if (EltVT.bitsLT(MVT::i32))
12983 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12985 switch (Op.getOpcode()) {
12987 llvm_unreachable("Unknown shift opcode!");
12989 switch (VT.getSimpleVT().SimpleTy) {
12990 default: return SDValue();
12999 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13002 switch (VT.getSimpleVT().SimpleTy) {
13003 default: return SDValue();
13010 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13013 switch (VT.getSimpleVT().SimpleTy) {
13014 default: return SDValue();
13023 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13029 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13030 if (!Subtarget->is64Bit() &&
13031 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13032 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13033 Amt.getOpcode() == ISD::BITCAST &&
13034 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13035 Amt = Amt.getOperand(0);
13036 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
13037 VT.getVectorNumElements();
13038 std::vector<SDValue> Vals(Ratio);
13039 for (unsigned i = 0; i != Ratio; ++i)
13040 Vals[i] = Amt.getOperand(i);
13041 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13042 for (unsigned j = 0; j != Ratio; ++j)
13043 if (Vals[j] != Amt.getOperand(i + j))
13046 switch (Op.getOpcode()) {
13048 llvm_unreachable("Unknown shift opcode!");
13050 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13052 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13054 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13061 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13062 SelectionDAG &DAG) {
13064 EVT VT = Op.getValueType();
13066 SDValue R = Op.getOperand(0);
13067 SDValue Amt = Op.getOperand(1);
13070 if (!Subtarget->hasSSE2())
13073 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13077 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13081 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13083 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13084 if (Subtarget->hasInt256()) {
13085 if (Op.getOpcode() == ISD::SRL &&
13086 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13087 VT == MVT::v4i64 || VT == MVT::v8i32))
13089 if (Op.getOpcode() == ISD::SHL &&
13090 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13091 VT == MVT::v4i64 || VT == MVT::v8i32))
13093 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13097 // Lower SHL with variable shift amount.
13098 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13099 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13101 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13102 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13103 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13104 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13106 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13107 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13110 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13111 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13113 // Turn 'a' into a mask suitable for VSELECT
13114 SDValue VSelM = DAG.getConstant(0x80, VT);
13115 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13116 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13118 SDValue CM1 = DAG.getConstant(0x0f, VT);
13119 SDValue CM2 = DAG.getConstant(0x3f, VT);
13121 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13122 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13123 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13124 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13125 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13128 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13129 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13130 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13132 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13133 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13134 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13135 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13136 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13139 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13140 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13141 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13143 // return VSELECT(r, r+r, a);
13144 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13145 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13149 // Decompose 256-bit shifts into smaller 128-bit shifts.
13150 if (VT.is256BitVector()) {
13151 unsigned NumElems = VT.getVectorNumElements();
13152 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13153 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13155 // Extract the two vectors
13156 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13157 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13159 // Recreate the shift amount vectors
13160 SDValue Amt1, Amt2;
13161 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13162 // Constant shift amount
13163 SmallVector<SDValue, 4> Amt1Csts;
13164 SmallVector<SDValue, 4> Amt2Csts;
13165 for (unsigned i = 0; i != NumElems/2; ++i)
13166 Amt1Csts.push_back(Amt->getOperand(i));
13167 for (unsigned i = NumElems/2; i != NumElems; ++i)
13168 Amt2Csts.push_back(Amt->getOperand(i));
13170 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13171 &Amt1Csts[0], NumElems/2);
13172 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13173 &Amt2Csts[0], NumElems/2);
13175 // Variable shift amount
13176 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13177 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13180 // Issue new vector shifts for the smaller types
13181 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13182 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13184 // Concatenate the result back
13185 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13191 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13192 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13193 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13194 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13195 // has only one use.
13196 SDNode *N = Op.getNode();
13197 SDValue LHS = N->getOperand(0);
13198 SDValue RHS = N->getOperand(1);
13199 unsigned BaseOp = 0;
13202 switch (Op.getOpcode()) {
13203 default: llvm_unreachable("Unknown ovf instruction!");
13205 // A subtract of one will be selected as a INC. Note that INC doesn't
13206 // set CF, so we can't do this for UADDO.
13207 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13209 BaseOp = X86ISD::INC;
13210 Cond = X86::COND_O;
13213 BaseOp = X86ISD::ADD;
13214 Cond = X86::COND_O;
13217 BaseOp = X86ISD::ADD;
13218 Cond = X86::COND_B;
13221 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13222 // set CF, so we can't do this for USUBO.
13223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13225 BaseOp = X86ISD::DEC;
13226 Cond = X86::COND_O;
13229 BaseOp = X86ISD::SUB;
13230 Cond = X86::COND_O;
13233 BaseOp = X86ISD::SUB;
13234 Cond = X86::COND_B;
13237 BaseOp = X86ISD::SMUL;
13238 Cond = X86::COND_O;
13240 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13241 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13243 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13246 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13247 DAG.getConstant(X86::COND_O, MVT::i32),
13248 SDValue(Sum.getNode(), 2));
13250 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13254 // Also sets EFLAGS.
13255 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13256 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13259 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13260 DAG.getConstant(Cond, MVT::i32),
13261 SDValue(Sum.getNode(), 1));
13263 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13266 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13267 SelectionDAG &DAG) const {
13269 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13270 EVT VT = Op.getValueType();
13272 if (!Subtarget->hasSSE2() || !VT.isVector())
13275 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13276 ExtraVT.getScalarType().getSizeInBits();
13278 switch (VT.getSimpleVT().SimpleTy) {
13279 default: return SDValue();
13282 if (!Subtarget->hasFp256())
13284 if (!Subtarget->hasInt256()) {
13285 // needs to be split
13286 unsigned NumElems = VT.getVectorNumElements();
13288 // Extract the LHS vectors
13289 SDValue LHS = Op.getOperand(0);
13290 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13291 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13293 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13294 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13296 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13297 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13298 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13300 SDValue Extra = DAG.getValueType(ExtraVT);
13302 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13303 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13305 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13310 SDValue Op0 = Op.getOperand(0);
13311 SDValue Op00 = Op0.getOperand(0);
13313 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13314 if (Op0.getOpcode() == ISD::BITCAST &&
13315 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13316 // (sext (vzext x)) -> (vsext x)
13317 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13318 if (Tmp1.getNode()) {
13319 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13320 // This folding is only valid when the in-reg type is a vector of i8,
13322 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13323 ExtraEltVT == MVT::i32) {
13324 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13325 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13326 "This optimization is invalid without a VZEXT.");
13327 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13333 // If the above didn't work, then just use Shift-Left + Shift-Right.
13334 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13336 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13342 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13343 SelectionDAG &DAG) {
13345 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13346 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13347 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13348 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13350 // The only fence that needs an instruction is a sequentially-consistent
13351 // cross-thread fence.
13352 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13353 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13354 // no-sse2). There isn't any reason to disable it if the target processor
13356 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13357 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13359 SDValue Chain = Op.getOperand(0);
13360 SDValue Zero = DAG.getConstant(0, MVT::i32);
13362 DAG.getRegister(X86::ESP, MVT::i32), // Base
13363 DAG.getTargetConstant(1, MVT::i8), // Scale
13364 DAG.getRegister(0, MVT::i32), // Index
13365 DAG.getTargetConstant(0, MVT::i32), // Disp
13366 DAG.getRegister(0, MVT::i32), // Segment.
13370 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13371 return SDValue(Res, 0);
13374 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13375 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13378 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13379 SelectionDAG &DAG) {
13380 EVT T = Op.getValueType();
13384 switch(T.getSimpleVT().SimpleTy) {
13385 default: llvm_unreachable("Invalid value type!");
13386 case MVT::i8: Reg = X86::AL; size = 1; break;
13387 case MVT::i16: Reg = X86::AX; size = 2; break;
13388 case MVT::i32: Reg = X86::EAX; size = 4; break;
13390 assert(Subtarget->is64Bit() && "Node not type legal!");
13391 Reg = X86::RAX; size = 8;
13394 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13395 Op.getOperand(2), SDValue());
13396 SDValue Ops[] = { cpIn.getValue(0),
13399 DAG.getTargetConstant(size, MVT::i8),
13400 cpIn.getValue(1) };
13401 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13402 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13403 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13404 Ops, array_lengthof(Ops), T, MMO);
13406 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13410 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13411 SelectionDAG &DAG) {
13412 assert(Subtarget->is64Bit() && "Result not type legalized?");
13413 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13414 SDValue TheChain = Op.getOperand(0);
13416 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13417 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13418 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13420 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13421 DAG.getConstant(32, MVT::i8));
13423 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13426 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13429 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13430 SelectionDAG &DAG) {
13431 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13432 MVT DstVT = Op.getSimpleValueType();
13433 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13434 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13435 assert((DstVT == MVT::i64 ||
13436 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13437 "Unexpected custom BITCAST");
13438 // i64 <=> MMX conversions are Legal.
13439 if (SrcVT==MVT::i64 && DstVT.isVector())
13441 if (DstVT==MVT::i64 && SrcVT.isVector())
13443 // MMX <=> MMX conversions are Legal.
13444 if (SrcVT.isVector() && DstVT.isVector())
13446 // All other conversions need to be expanded.
13450 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13451 SDNode *Node = Op.getNode();
13453 EVT T = Node->getValueType(0);
13454 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13455 DAG.getConstant(0, T), Node->getOperand(2));
13456 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13457 cast<AtomicSDNode>(Node)->getMemoryVT(),
13458 Node->getOperand(0),
13459 Node->getOperand(1), negOp,
13460 cast<AtomicSDNode>(Node)->getSrcValue(),
13461 cast<AtomicSDNode>(Node)->getAlignment(),
13462 cast<AtomicSDNode>(Node)->getOrdering(),
13463 cast<AtomicSDNode>(Node)->getSynchScope());
13466 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13467 SDNode *Node = Op.getNode();
13469 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13471 // Convert seq_cst store -> xchg
13472 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13473 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13474 // (The only way to get a 16-byte store is cmpxchg16b)
13475 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13476 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13477 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13478 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13479 cast<AtomicSDNode>(Node)->getMemoryVT(),
13480 Node->getOperand(0),
13481 Node->getOperand(1), Node->getOperand(2),
13482 cast<AtomicSDNode>(Node)->getMemOperand(),
13483 cast<AtomicSDNode>(Node)->getOrdering(),
13484 cast<AtomicSDNode>(Node)->getSynchScope());
13485 return Swap.getValue(1);
13487 // Other atomic stores have a simple pattern.
13491 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13492 EVT VT = Op.getNode()->getValueType(0);
13494 // Let legalize expand this if it isn't a legal type yet.
13495 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13498 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13501 bool ExtraOp = false;
13502 switch (Op.getOpcode()) {
13503 default: llvm_unreachable("Invalid code");
13504 case ISD::ADDC: Opc = X86ISD::ADD; break;
13505 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13506 case ISD::SUBC: Opc = X86ISD::SUB; break;
13507 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13511 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13513 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13514 Op.getOperand(1), Op.getOperand(2));
13517 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13518 SelectionDAG &DAG) {
13519 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13521 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13522 // which returns the values as { float, float } (in XMM0) or
13523 // { double, double } (which is returned in XMM0, XMM1).
13525 SDValue Arg = Op.getOperand(0);
13526 EVT ArgVT = Arg.getValueType();
13527 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13529 TargetLowering::ArgListTy Args;
13530 TargetLowering::ArgListEntry Entry;
13534 Entry.isSExt = false;
13535 Entry.isZExt = false;
13536 Args.push_back(Entry);
13538 bool isF64 = ArgVT == MVT::f64;
13539 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13540 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13541 // the results are returned via SRet in memory.
13542 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13543 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13544 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13546 Type *RetTy = isF64
13547 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13548 : (Type*)VectorType::get(ArgTy, 4);
13550 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13551 false, false, false, false, 0,
13552 CallingConv::C, /*isTaillCall=*/false,
13553 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13554 Callee, Args, DAG, dl);
13555 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13558 // Returned in xmm0 and xmm1.
13559 return CallResult.first;
13561 // Returned in bits 0:31 and 32:64 xmm0.
13562 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13563 CallResult.first, DAG.getIntPtrConstant(0));
13564 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13565 CallResult.first, DAG.getIntPtrConstant(1));
13566 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13567 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13570 /// LowerOperation - Provide custom lowering hooks for some operations.
13572 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13573 switch (Op.getOpcode()) {
13574 default: llvm_unreachable("Should not custom lower this!");
13575 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13576 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13577 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13578 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13579 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13580 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13581 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13582 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13583 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13584 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13585 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13586 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13587 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13588 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13589 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13590 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13591 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13592 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13593 case ISD::SHL_PARTS:
13594 case ISD::SRA_PARTS:
13595 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13596 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13597 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13598 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13599 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13600 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13601 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13602 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13603 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13604 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13605 case ISD::FABS: return LowerFABS(Op, DAG);
13606 case ISD::FNEG: return LowerFNEG(Op, DAG);
13607 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13608 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13609 case ISD::SETCC: return LowerSETCC(Op, DAG);
13610 case ISD::SELECT: return LowerSELECT(Op, DAG);
13611 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13612 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13613 case ISD::VASTART: return LowerVASTART(Op, DAG);
13614 case ISD::VAARG: return LowerVAARG(Op, DAG);
13615 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13616 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13617 case ISD::INTRINSIC_VOID:
13618 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13619 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13620 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13621 case ISD::FRAME_TO_ARGS_OFFSET:
13622 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13623 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13624 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13625 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13626 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13627 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13628 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13629 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13630 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13631 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13632 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13633 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13636 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13642 case ISD::UMULO: return LowerXALUO(Op, DAG);
13643 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13644 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13648 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13649 case ISD::ADD: return LowerADD(Op, DAG);
13650 case ISD::SUB: return LowerSUB(Op, DAG);
13651 case ISD::SDIV: return LowerSDIV(Op, DAG);
13652 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13656 static void ReplaceATOMIC_LOAD(SDNode *Node,
13657 SmallVectorImpl<SDValue> &Results,
13658 SelectionDAG &DAG) {
13660 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13662 // Convert wide load -> cmpxchg8b/cmpxchg16b
13663 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13664 // (The only way to get a 16-byte load is cmpxchg16b)
13665 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13666 SDValue Zero = DAG.getConstant(0, VT);
13667 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13668 Node->getOperand(0),
13669 Node->getOperand(1), Zero, Zero,
13670 cast<AtomicSDNode>(Node)->getMemOperand(),
13671 cast<AtomicSDNode>(Node)->getOrdering(),
13672 cast<AtomicSDNode>(Node)->getSynchScope());
13673 Results.push_back(Swap.getValue(0));
13674 Results.push_back(Swap.getValue(1));
13678 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13679 SelectionDAG &DAG, unsigned NewOp) {
13681 assert (Node->getValueType(0) == MVT::i64 &&
13682 "Only know how to expand i64 atomics");
13684 SDValue Chain = Node->getOperand(0);
13685 SDValue In1 = Node->getOperand(1);
13686 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13687 Node->getOperand(2), DAG.getIntPtrConstant(0));
13688 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13689 Node->getOperand(2), DAG.getIntPtrConstant(1));
13690 SDValue Ops[] = { Chain, In1, In2L, In2H };
13691 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13693 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13694 cast<MemSDNode>(Node)->getMemOperand());
13695 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13696 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13697 Results.push_back(Result.getValue(2));
13700 /// ReplaceNodeResults - Replace a node with an illegal result type
13701 /// with a new node built out of custom code.
13702 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13703 SmallVectorImpl<SDValue>&Results,
13704 SelectionDAG &DAG) const {
13706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13707 switch (N->getOpcode()) {
13709 llvm_unreachable("Do not know how to custom type legalize this operation!");
13710 case ISD::SIGN_EXTEND_INREG:
13715 // We don't want to expand or promote these.
13717 case ISD::FP_TO_SINT:
13718 case ISD::FP_TO_UINT: {
13719 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13721 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13724 std::pair<SDValue,SDValue> Vals =
13725 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13726 SDValue FIST = Vals.first, StackSlot = Vals.second;
13727 if (FIST.getNode() != 0) {
13728 EVT VT = N->getValueType(0);
13729 // Return a load from the stack slot.
13730 if (StackSlot.getNode() != 0)
13731 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13732 MachinePointerInfo(),
13733 false, false, false, 0));
13735 Results.push_back(FIST);
13739 case ISD::UINT_TO_FP: {
13740 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13741 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13742 N->getValueType(0) != MVT::v2f32)
13744 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13746 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13748 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13749 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13750 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13751 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13752 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13753 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13756 case ISD::FP_ROUND: {
13757 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13759 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13760 Results.push_back(V);
13763 case ISD::READCYCLECOUNTER: {
13764 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13765 SDValue TheChain = N->getOperand(0);
13766 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13767 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13769 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13771 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13772 SDValue Ops[] = { eax, edx };
13773 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13774 array_lengthof(Ops)));
13775 Results.push_back(edx.getValue(1));
13778 case ISD::ATOMIC_CMP_SWAP: {
13779 EVT T = N->getValueType(0);
13780 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13781 bool Regs64bit = T == MVT::i128;
13782 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13783 SDValue cpInL, cpInH;
13784 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13785 DAG.getConstant(0, HalfT));
13786 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13787 DAG.getConstant(1, HalfT));
13788 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13789 Regs64bit ? X86::RAX : X86::EAX,
13791 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13792 Regs64bit ? X86::RDX : X86::EDX,
13793 cpInH, cpInL.getValue(1));
13794 SDValue swapInL, swapInH;
13795 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13796 DAG.getConstant(0, HalfT));
13797 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13798 DAG.getConstant(1, HalfT));
13799 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13800 Regs64bit ? X86::RBX : X86::EBX,
13801 swapInL, cpInH.getValue(1));
13802 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13803 Regs64bit ? X86::RCX : X86::ECX,
13804 swapInH, swapInL.getValue(1));
13805 SDValue Ops[] = { swapInH.getValue(0),
13807 swapInH.getValue(1) };
13808 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13809 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13810 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13811 X86ISD::LCMPXCHG8_DAG;
13812 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13813 Ops, array_lengthof(Ops), T, MMO);
13814 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13815 Regs64bit ? X86::RAX : X86::EAX,
13816 HalfT, Result.getValue(1));
13817 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13818 Regs64bit ? X86::RDX : X86::EDX,
13819 HalfT, cpOutL.getValue(2));
13820 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13821 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13822 Results.push_back(cpOutH.getValue(1));
13825 case ISD::ATOMIC_LOAD_ADD:
13826 case ISD::ATOMIC_LOAD_AND:
13827 case ISD::ATOMIC_LOAD_NAND:
13828 case ISD::ATOMIC_LOAD_OR:
13829 case ISD::ATOMIC_LOAD_SUB:
13830 case ISD::ATOMIC_LOAD_XOR:
13831 case ISD::ATOMIC_LOAD_MAX:
13832 case ISD::ATOMIC_LOAD_MIN:
13833 case ISD::ATOMIC_LOAD_UMAX:
13834 case ISD::ATOMIC_LOAD_UMIN:
13835 case ISD::ATOMIC_SWAP: {
13837 switch (N->getOpcode()) {
13838 default: llvm_unreachable("Unexpected opcode");
13839 case ISD::ATOMIC_LOAD_ADD:
13840 Opc = X86ISD::ATOMADD64_DAG;
13842 case ISD::ATOMIC_LOAD_AND:
13843 Opc = X86ISD::ATOMAND64_DAG;
13845 case ISD::ATOMIC_LOAD_NAND:
13846 Opc = X86ISD::ATOMNAND64_DAG;
13848 case ISD::ATOMIC_LOAD_OR:
13849 Opc = X86ISD::ATOMOR64_DAG;
13851 case ISD::ATOMIC_LOAD_SUB:
13852 Opc = X86ISD::ATOMSUB64_DAG;
13854 case ISD::ATOMIC_LOAD_XOR:
13855 Opc = X86ISD::ATOMXOR64_DAG;
13857 case ISD::ATOMIC_LOAD_MAX:
13858 Opc = X86ISD::ATOMMAX64_DAG;
13860 case ISD::ATOMIC_LOAD_MIN:
13861 Opc = X86ISD::ATOMMIN64_DAG;
13863 case ISD::ATOMIC_LOAD_UMAX:
13864 Opc = X86ISD::ATOMUMAX64_DAG;
13866 case ISD::ATOMIC_LOAD_UMIN:
13867 Opc = X86ISD::ATOMUMIN64_DAG;
13869 case ISD::ATOMIC_SWAP:
13870 Opc = X86ISD::ATOMSWAP64_DAG;
13873 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13876 case ISD::ATOMIC_LOAD:
13877 ReplaceATOMIC_LOAD(N, Results, DAG);
13881 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13883 default: return NULL;
13884 case X86ISD::BSF: return "X86ISD::BSF";
13885 case X86ISD::BSR: return "X86ISD::BSR";
13886 case X86ISD::SHLD: return "X86ISD::SHLD";
13887 case X86ISD::SHRD: return "X86ISD::SHRD";
13888 case X86ISD::FAND: return "X86ISD::FAND";
13889 case X86ISD::FANDN: return "X86ISD::FANDN";
13890 case X86ISD::FOR: return "X86ISD::FOR";
13891 case X86ISD::FXOR: return "X86ISD::FXOR";
13892 case X86ISD::FSRL: return "X86ISD::FSRL";
13893 case X86ISD::FILD: return "X86ISD::FILD";
13894 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13895 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13896 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13897 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13898 case X86ISD::FLD: return "X86ISD::FLD";
13899 case X86ISD::FST: return "X86ISD::FST";
13900 case X86ISD::CALL: return "X86ISD::CALL";
13901 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13902 case X86ISD::BT: return "X86ISD::BT";
13903 case X86ISD::CMP: return "X86ISD::CMP";
13904 case X86ISD::COMI: return "X86ISD::COMI";
13905 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13906 case X86ISD::CMPM: return "X86ISD::CMPM";
13907 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13908 case X86ISD::SETCC: return "X86ISD::SETCC";
13909 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13910 case X86ISD::FSETCC: return "X86ISD::FSETCC";
13911 case X86ISD::CMOV: return "X86ISD::CMOV";
13912 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13913 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13914 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13915 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13916 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13917 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13918 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13919 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13920 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13921 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13922 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13923 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13924 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13925 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13926 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13927 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13928 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13929 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13930 case X86ISD::HADD: return "X86ISD::HADD";
13931 case X86ISD::HSUB: return "X86ISD::HSUB";
13932 case X86ISD::FHADD: return "X86ISD::FHADD";
13933 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13934 case X86ISD::UMAX: return "X86ISD::UMAX";
13935 case X86ISD::UMIN: return "X86ISD::UMIN";
13936 case X86ISD::SMAX: return "X86ISD::SMAX";
13937 case X86ISD::SMIN: return "X86ISD::SMIN";
13938 case X86ISD::FMAX: return "X86ISD::FMAX";
13939 case X86ISD::FMIN: return "X86ISD::FMIN";
13940 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13941 case X86ISD::FMINC: return "X86ISD::FMINC";
13942 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13943 case X86ISD::FRCP: return "X86ISD::FRCP";
13944 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13945 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13946 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13947 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13948 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13949 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13950 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13951 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13952 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13953 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13954 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13955 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13956 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13957 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13958 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13959 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13960 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13961 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13962 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13963 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13964 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13965 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13966 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13967 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13968 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13969 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13970 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13971 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13972 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13973 case X86ISD::VSHL: return "X86ISD::VSHL";
13974 case X86ISD::VSRL: return "X86ISD::VSRL";
13975 case X86ISD::VSRA: return "X86ISD::VSRA";
13976 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13977 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13978 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13979 case X86ISD::CMPP: return "X86ISD::CMPP";
13980 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13981 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13982 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13983 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13984 case X86ISD::ADD: return "X86ISD::ADD";
13985 case X86ISD::SUB: return "X86ISD::SUB";
13986 case X86ISD::ADC: return "X86ISD::ADC";
13987 case X86ISD::SBB: return "X86ISD::SBB";
13988 case X86ISD::SMUL: return "X86ISD::SMUL";
13989 case X86ISD::UMUL: return "X86ISD::UMUL";
13990 case X86ISD::INC: return "X86ISD::INC";
13991 case X86ISD::DEC: return "X86ISD::DEC";
13992 case X86ISD::OR: return "X86ISD::OR";
13993 case X86ISD::XOR: return "X86ISD::XOR";
13994 case X86ISD::AND: return "X86ISD::AND";
13995 case X86ISD::BLSI: return "X86ISD::BLSI";
13996 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13997 case X86ISD::BLSR: return "X86ISD::BLSR";
13998 case X86ISD::BZHI: return "X86ISD::BZHI";
13999 case X86ISD::BEXTR: return "X86ISD::BEXTR";
14000 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
14001 case X86ISD::PTEST: return "X86ISD::PTEST";
14002 case X86ISD::TESTP: return "X86ISD::TESTP";
14003 case X86ISD::TESTM: return "X86ISD::TESTM";
14004 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14005 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14006 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14007 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14008 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14009 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14010 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14011 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14012 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14013 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14014 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14015 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14016 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14017 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14018 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14019 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14020 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14021 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14022 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14023 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14024 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14025 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14026 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14027 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14028 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14029 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14030 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14031 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14032 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14033 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14034 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14035 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14036 case X86ISD::SAHF: return "X86ISD::SAHF";
14037 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14038 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14039 case X86ISD::FMADD: return "X86ISD::FMADD";
14040 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14041 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14042 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14043 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14044 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14045 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14046 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14047 case X86ISD::XTEST: return "X86ISD::XTEST";
14051 // isLegalAddressingMode - Return true if the addressing mode represented
14052 // by AM is legal for this target, for a load/store of the specified type.
14053 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14055 // X86 supports extremely general addressing modes.
14056 CodeModel::Model M = getTargetMachine().getCodeModel();
14057 Reloc::Model R = getTargetMachine().getRelocationModel();
14059 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14060 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
14065 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14067 // If a reference to this global requires an extra load, we can't fold it.
14068 if (isGlobalStubReference(GVFlags))
14071 // If BaseGV requires a register for the PIC base, we cannot also have a
14072 // BaseReg specified.
14073 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14076 // If lower 4G is not available, then we must use rip-relative addressing.
14077 if ((M != CodeModel::Small || R != Reloc::Static) &&
14078 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14082 switch (AM.Scale) {
14088 // These scales always work.
14093 // These scales are formed with basereg+scalereg. Only accept if there is
14098 default: // Other stuff never works.
14105 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14106 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14108 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14109 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14110 return NumBits1 > NumBits2;
14113 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14114 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14117 if (!isTypeLegal(EVT::getEVT(Ty1)))
14120 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14122 // Assuming the caller doesn't have a zeroext or signext return parameter,
14123 // truncation all the way down to i1 is valid.
14127 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14128 return isInt<32>(Imm);
14131 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14132 // Can also use sub to handle negated immediates.
14133 return isInt<32>(Imm);
14136 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14137 if (!VT1.isInteger() || !VT2.isInteger())
14139 unsigned NumBits1 = VT1.getSizeInBits();
14140 unsigned NumBits2 = VT2.getSizeInBits();
14141 return NumBits1 > NumBits2;
14144 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14145 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14146 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14149 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14150 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14151 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14154 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14155 EVT VT1 = Val.getValueType();
14156 if (isZExtFree(VT1, VT2))
14159 if (Val.getOpcode() != ISD::LOAD)
14162 if (!VT1.isSimple() || !VT1.isInteger() ||
14163 !VT2.isSimple() || !VT2.isInteger())
14166 switch (VT1.getSimpleVT().SimpleTy) {
14171 // X86 has 8, 16, and 32-bit zero-extending loads.
14179 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14180 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14183 VT = VT.getScalarType();
14185 if (!VT.isSimple())
14188 switch (VT.getSimpleVT().SimpleTy) {
14199 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14200 // i16 instructions are longer (0x66 prefix) and potentially slower.
14201 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14204 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14205 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14206 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14207 /// are assumed to be legal.
14209 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14211 if (!VT.isSimple())
14214 MVT SVT = VT.getSimpleVT();
14216 // Very little shuffling can be done for 64-bit vectors right now.
14217 if (VT.getSizeInBits() == 64)
14220 // FIXME: pshufb, blends, shifts.
14221 return (SVT.getVectorNumElements() == 2 ||
14222 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14223 isMOVLMask(M, SVT) ||
14224 isSHUFPMask(M, SVT) ||
14225 isPSHUFDMask(M, SVT) ||
14226 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14227 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14228 isPALIGNRMask(M, SVT, Subtarget) ||
14229 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14230 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14231 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14232 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14236 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14238 if (!VT.isSimple())
14241 MVT SVT = VT.getSimpleVT();
14242 unsigned NumElts = SVT.getVectorNumElements();
14243 // FIXME: This collection of masks seems suspect.
14246 if (NumElts == 4 && SVT.is128BitVector()) {
14247 return (isMOVLMask(Mask, SVT) ||
14248 isCommutedMOVLMask(Mask, SVT, true) ||
14249 isSHUFPMask(Mask, SVT) ||
14250 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14255 //===----------------------------------------------------------------------===//
14256 // X86 Scheduler Hooks
14257 //===----------------------------------------------------------------------===//
14259 /// Utility function to emit xbegin specifying the start of an RTM region.
14260 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14261 const TargetInstrInfo *TII) {
14262 DebugLoc DL = MI->getDebugLoc();
14264 const BasicBlock *BB = MBB->getBasicBlock();
14265 MachineFunction::iterator I = MBB;
14268 // For the v = xbegin(), we generate
14279 MachineBasicBlock *thisMBB = MBB;
14280 MachineFunction *MF = MBB->getParent();
14281 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14282 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14283 MF->insert(I, mainMBB);
14284 MF->insert(I, sinkMBB);
14286 // Transfer the remainder of BB and its successor edges to sinkMBB.
14287 sinkMBB->splice(sinkMBB->begin(), MBB,
14288 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14289 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14293 // # fallthrough to mainMBB
14294 // # abortion to sinkMBB
14295 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14296 thisMBB->addSuccessor(mainMBB);
14297 thisMBB->addSuccessor(sinkMBB);
14301 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14302 mainMBB->addSuccessor(sinkMBB);
14305 // EAX is live into the sinkMBB
14306 sinkMBB->addLiveIn(X86::EAX);
14307 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14308 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14311 MI->eraseFromParent();
14315 // Get CMPXCHG opcode for the specified data type.
14316 static unsigned getCmpXChgOpcode(EVT VT) {
14317 switch (VT.getSimpleVT().SimpleTy) {
14318 case MVT::i8: return X86::LCMPXCHG8;
14319 case MVT::i16: return X86::LCMPXCHG16;
14320 case MVT::i32: return X86::LCMPXCHG32;
14321 case MVT::i64: return X86::LCMPXCHG64;
14325 llvm_unreachable("Invalid operand size!");
14328 // Get LOAD opcode for the specified data type.
14329 static unsigned getLoadOpcode(EVT VT) {
14330 switch (VT.getSimpleVT().SimpleTy) {
14331 case MVT::i8: return X86::MOV8rm;
14332 case MVT::i16: return X86::MOV16rm;
14333 case MVT::i32: return X86::MOV32rm;
14334 case MVT::i64: return X86::MOV64rm;
14338 llvm_unreachable("Invalid operand size!");
14341 // Get opcode of the non-atomic one from the specified atomic instruction.
14342 static unsigned getNonAtomicOpcode(unsigned Opc) {
14344 case X86::ATOMAND8: return X86::AND8rr;
14345 case X86::ATOMAND16: return X86::AND16rr;
14346 case X86::ATOMAND32: return X86::AND32rr;
14347 case X86::ATOMAND64: return X86::AND64rr;
14348 case X86::ATOMOR8: return X86::OR8rr;
14349 case X86::ATOMOR16: return X86::OR16rr;
14350 case X86::ATOMOR32: return X86::OR32rr;
14351 case X86::ATOMOR64: return X86::OR64rr;
14352 case X86::ATOMXOR8: return X86::XOR8rr;
14353 case X86::ATOMXOR16: return X86::XOR16rr;
14354 case X86::ATOMXOR32: return X86::XOR32rr;
14355 case X86::ATOMXOR64: return X86::XOR64rr;
14357 llvm_unreachable("Unhandled atomic-load-op opcode!");
14360 // Get opcode of the non-atomic one from the specified atomic instruction with
14362 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14363 unsigned &ExtraOpc) {
14365 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14366 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14367 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14368 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14369 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14370 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14371 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14372 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14373 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14374 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14375 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14376 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14377 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14378 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14379 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14380 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14381 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14382 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14383 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14384 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14386 llvm_unreachable("Unhandled atomic-load-op opcode!");
14389 // Get opcode of the non-atomic one from the specified atomic instruction for
14390 // 64-bit data type on 32-bit target.
14391 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14393 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14394 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14395 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14396 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14397 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14398 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14399 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14400 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14401 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14402 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14404 llvm_unreachable("Unhandled atomic-load-op opcode!");
14407 // Get opcode of the non-atomic one from the specified atomic instruction for
14408 // 64-bit data type on 32-bit target with extra opcode.
14409 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14411 unsigned &ExtraOpc) {
14413 case X86::ATOMNAND6432:
14414 ExtraOpc = X86::NOT32r;
14415 HiOpc = X86::AND32rr;
14416 return X86::AND32rr;
14418 llvm_unreachable("Unhandled atomic-load-op opcode!");
14421 // Get pseudo CMOV opcode from the specified data type.
14422 static unsigned getPseudoCMOVOpc(EVT VT) {
14423 switch (VT.getSimpleVT().SimpleTy) {
14424 case MVT::i8: return X86::CMOV_GR8;
14425 case MVT::i16: return X86::CMOV_GR16;
14426 case MVT::i32: return X86::CMOV_GR32;
14430 llvm_unreachable("Unknown CMOV opcode!");
14433 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14434 // They will be translated into a spin-loop or compare-exchange loop from
14437 // dst = atomic-fetch-op MI.addr, MI.val
14443 // t1 = LOAD MI.addr
14445 // t4 = phi(t1, t3 / loop)
14446 // t2 = OP MI.val, t4
14448 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14454 MachineBasicBlock *
14455 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14456 MachineBasicBlock *MBB) const {
14457 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14458 DebugLoc DL = MI->getDebugLoc();
14460 MachineFunction *MF = MBB->getParent();
14461 MachineRegisterInfo &MRI = MF->getRegInfo();
14463 const BasicBlock *BB = MBB->getBasicBlock();
14464 MachineFunction::iterator I = MBB;
14467 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14468 "Unexpected number of operands");
14470 assert(MI->hasOneMemOperand() &&
14471 "Expected atomic-load-op to have one memoperand");
14473 // Memory Reference
14474 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14475 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14477 unsigned DstReg, SrcReg;
14478 unsigned MemOpndSlot;
14480 unsigned CurOp = 0;
14482 DstReg = MI->getOperand(CurOp++).getReg();
14483 MemOpndSlot = CurOp;
14484 CurOp += X86::AddrNumOperands;
14485 SrcReg = MI->getOperand(CurOp++).getReg();
14487 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14488 MVT::SimpleValueType VT = *RC->vt_begin();
14489 unsigned t1 = MRI.createVirtualRegister(RC);
14490 unsigned t2 = MRI.createVirtualRegister(RC);
14491 unsigned t3 = MRI.createVirtualRegister(RC);
14492 unsigned t4 = MRI.createVirtualRegister(RC);
14493 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14495 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14496 unsigned LOADOpc = getLoadOpcode(VT);
14498 // For the atomic load-arith operator, we generate
14501 // t1 = LOAD [MI.addr]
14503 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14504 // t1 = OP MI.val, EAX
14506 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14512 MachineBasicBlock *thisMBB = MBB;
14513 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14514 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14515 MF->insert(I, mainMBB);
14516 MF->insert(I, sinkMBB);
14518 MachineInstrBuilder MIB;
14520 // Transfer the remainder of BB and its successor edges to sinkMBB.
14521 sinkMBB->splice(sinkMBB->begin(), MBB,
14522 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14523 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14526 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14527 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14528 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14530 NewMO.setIsKill(false);
14531 MIB.addOperand(NewMO);
14533 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14534 unsigned flags = (*MMOI)->getFlags();
14535 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14536 MachineMemOperand *MMO =
14537 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14538 (*MMOI)->getSize(),
14539 (*MMOI)->getBaseAlignment(),
14540 (*MMOI)->getTBAAInfo(),
14541 (*MMOI)->getRanges());
14542 MIB.addMemOperand(MMO);
14545 thisMBB->addSuccessor(mainMBB);
14548 MachineBasicBlock *origMainMBB = mainMBB;
14551 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14552 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14554 unsigned Opc = MI->getOpcode();
14557 llvm_unreachable("Unhandled atomic-load-op opcode!");
14558 case X86::ATOMAND8:
14559 case X86::ATOMAND16:
14560 case X86::ATOMAND32:
14561 case X86::ATOMAND64:
14563 case X86::ATOMOR16:
14564 case X86::ATOMOR32:
14565 case X86::ATOMOR64:
14566 case X86::ATOMXOR8:
14567 case X86::ATOMXOR16:
14568 case X86::ATOMXOR32:
14569 case X86::ATOMXOR64: {
14570 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14571 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14575 case X86::ATOMNAND8:
14576 case X86::ATOMNAND16:
14577 case X86::ATOMNAND32:
14578 case X86::ATOMNAND64: {
14579 unsigned Tmp = MRI.createVirtualRegister(RC);
14581 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14582 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14584 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14587 case X86::ATOMMAX8:
14588 case X86::ATOMMAX16:
14589 case X86::ATOMMAX32:
14590 case X86::ATOMMAX64:
14591 case X86::ATOMMIN8:
14592 case X86::ATOMMIN16:
14593 case X86::ATOMMIN32:
14594 case X86::ATOMMIN64:
14595 case X86::ATOMUMAX8:
14596 case X86::ATOMUMAX16:
14597 case X86::ATOMUMAX32:
14598 case X86::ATOMUMAX64:
14599 case X86::ATOMUMIN8:
14600 case X86::ATOMUMIN16:
14601 case X86::ATOMUMIN32:
14602 case X86::ATOMUMIN64: {
14604 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14606 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14610 if (Subtarget->hasCMov()) {
14611 if (VT != MVT::i8) {
14613 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14617 // Promote i8 to i32 to use CMOV32
14618 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14619 const TargetRegisterClass *RC32 =
14620 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14621 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14622 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14623 unsigned Tmp = MRI.createVirtualRegister(RC32);
14625 unsigned Undef = MRI.createVirtualRegister(RC32);
14626 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14628 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14631 .addImm(X86::sub_8bit);
14632 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14635 .addImm(X86::sub_8bit);
14637 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14641 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14642 .addReg(Tmp, 0, X86::sub_8bit);
14645 // Use pseudo select and lower them.
14646 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14647 "Invalid atomic-load-op transformation!");
14648 unsigned SelOpc = getPseudoCMOVOpc(VT);
14649 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14650 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14651 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14652 .addReg(SrcReg).addReg(t4)
14654 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14655 // Replace the original PHI node as mainMBB is changed after CMOV
14657 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14658 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14659 Phi->eraseFromParent();
14665 // Copy PhyReg back from virtual register.
14666 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14669 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14670 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14671 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14673 NewMO.setIsKill(false);
14674 MIB.addOperand(NewMO);
14677 MIB.setMemRefs(MMOBegin, MMOEnd);
14679 // Copy PhyReg back to virtual register.
14680 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14683 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14685 mainMBB->addSuccessor(origMainMBB);
14686 mainMBB->addSuccessor(sinkMBB);
14689 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14690 TII->get(TargetOpcode::COPY), DstReg)
14693 MI->eraseFromParent();
14697 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14698 // instructions. They will be translated into a spin-loop or compare-exchange
14702 // dst = atomic-fetch-op MI.addr, MI.val
14708 // t1L = LOAD [MI.addr + 0]
14709 // t1H = LOAD [MI.addr + 4]
14711 // t4L = phi(t1L, t3L / loop)
14712 // t4H = phi(t1H, t3H / loop)
14713 // t2L = OP MI.val.lo, t4L
14714 // t2H = OP MI.val.hi, t4H
14719 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14727 MachineBasicBlock *
14728 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14729 MachineBasicBlock *MBB) const {
14730 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14731 DebugLoc DL = MI->getDebugLoc();
14733 MachineFunction *MF = MBB->getParent();
14734 MachineRegisterInfo &MRI = MF->getRegInfo();
14736 const BasicBlock *BB = MBB->getBasicBlock();
14737 MachineFunction::iterator I = MBB;
14740 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14741 "Unexpected number of operands");
14743 assert(MI->hasOneMemOperand() &&
14744 "Expected atomic-load-op32 to have one memoperand");
14746 // Memory Reference
14747 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14748 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14750 unsigned DstLoReg, DstHiReg;
14751 unsigned SrcLoReg, SrcHiReg;
14752 unsigned MemOpndSlot;
14754 unsigned CurOp = 0;
14756 DstLoReg = MI->getOperand(CurOp++).getReg();
14757 DstHiReg = MI->getOperand(CurOp++).getReg();
14758 MemOpndSlot = CurOp;
14759 CurOp += X86::AddrNumOperands;
14760 SrcLoReg = MI->getOperand(CurOp++).getReg();
14761 SrcHiReg = MI->getOperand(CurOp++).getReg();
14763 const TargetRegisterClass *RC = &X86::GR32RegClass;
14764 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14766 unsigned t1L = MRI.createVirtualRegister(RC);
14767 unsigned t1H = MRI.createVirtualRegister(RC);
14768 unsigned t2L = MRI.createVirtualRegister(RC);
14769 unsigned t2H = MRI.createVirtualRegister(RC);
14770 unsigned t3L = MRI.createVirtualRegister(RC);
14771 unsigned t3H = MRI.createVirtualRegister(RC);
14772 unsigned t4L = MRI.createVirtualRegister(RC);
14773 unsigned t4H = MRI.createVirtualRegister(RC);
14775 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14776 unsigned LOADOpc = X86::MOV32rm;
14778 // For the atomic load-arith operator, we generate
14781 // t1L = LOAD [MI.addr + 0]
14782 // t1H = LOAD [MI.addr + 4]
14784 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14785 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14786 // t2L = OP MI.val.lo, t4L
14787 // t2H = OP MI.val.hi, t4H
14790 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14798 MachineBasicBlock *thisMBB = MBB;
14799 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14800 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14801 MF->insert(I, mainMBB);
14802 MF->insert(I, sinkMBB);
14804 MachineInstrBuilder MIB;
14806 // Transfer the remainder of BB and its successor edges to sinkMBB.
14807 sinkMBB->splice(sinkMBB->begin(), MBB,
14808 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14809 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14813 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14814 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14815 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14817 NewMO.setIsKill(false);
14818 MIB.addOperand(NewMO);
14820 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14821 unsigned flags = (*MMOI)->getFlags();
14822 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14823 MachineMemOperand *MMO =
14824 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14825 (*MMOI)->getSize(),
14826 (*MMOI)->getBaseAlignment(),
14827 (*MMOI)->getTBAAInfo(),
14828 (*MMOI)->getRanges());
14829 MIB.addMemOperand(MMO);
14831 MachineInstr *LowMI = MIB;
14834 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14835 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14836 if (i == X86::AddrDisp) {
14837 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14839 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14841 NewMO.setIsKill(false);
14842 MIB.addOperand(NewMO);
14845 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14847 thisMBB->addSuccessor(mainMBB);
14850 MachineBasicBlock *origMainMBB = mainMBB;
14853 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14854 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14855 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14856 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14858 unsigned Opc = MI->getOpcode();
14861 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14862 case X86::ATOMAND6432:
14863 case X86::ATOMOR6432:
14864 case X86::ATOMXOR6432:
14865 case X86::ATOMADD6432:
14866 case X86::ATOMSUB6432: {
14868 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14869 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14871 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14875 case X86::ATOMNAND6432: {
14876 unsigned HiOpc, NOTOpc;
14877 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14878 unsigned TmpL = MRI.createVirtualRegister(RC);
14879 unsigned TmpH = MRI.createVirtualRegister(RC);
14880 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14882 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14884 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14885 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14888 case X86::ATOMMAX6432:
14889 case X86::ATOMMIN6432:
14890 case X86::ATOMUMAX6432:
14891 case X86::ATOMUMIN6432: {
14893 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14894 unsigned cL = MRI.createVirtualRegister(RC8);
14895 unsigned cH = MRI.createVirtualRegister(RC8);
14896 unsigned cL32 = MRI.createVirtualRegister(RC);
14897 unsigned cH32 = MRI.createVirtualRegister(RC);
14898 unsigned cc = MRI.createVirtualRegister(RC);
14899 // cl := cmp src_lo, lo
14900 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14901 .addReg(SrcLoReg).addReg(t4L);
14902 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14903 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14904 // ch := cmp src_hi, hi
14905 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14906 .addReg(SrcHiReg).addReg(t4H);
14907 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14908 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14909 // cc := if (src_hi == hi) ? cl : ch;
14910 if (Subtarget->hasCMov()) {
14911 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14912 .addReg(cH32).addReg(cL32);
14914 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14915 .addReg(cH32).addReg(cL32)
14916 .addImm(X86::COND_E);
14917 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14919 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14920 if (Subtarget->hasCMov()) {
14921 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14922 .addReg(SrcLoReg).addReg(t4L);
14923 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14924 .addReg(SrcHiReg).addReg(t4H);
14926 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14927 .addReg(SrcLoReg).addReg(t4L)
14928 .addImm(X86::COND_NE);
14929 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14930 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14931 // 2nd CMOV lowering.
14932 mainMBB->addLiveIn(X86::EFLAGS);
14933 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14934 .addReg(SrcHiReg).addReg(t4H)
14935 .addImm(X86::COND_NE);
14936 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14937 // Replace the original PHI node as mainMBB is changed after CMOV
14939 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14940 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14941 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14942 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14943 PhiL->eraseFromParent();
14944 PhiH->eraseFromParent();
14948 case X86::ATOMSWAP6432: {
14950 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14951 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14952 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14957 // Copy EDX:EAX back from HiReg:LoReg
14958 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14959 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14960 // Copy ECX:EBX from t1H:t1L
14961 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14962 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14964 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14965 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14966 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14968 NewMO.setIsKill(false);
14969 MIB.addOperand(NewMO);
14971 MIB.setMemRefs(MMOBegin, MMOEnd);
14973 // Copy EDX:EAX back to t3H:t3L
14974 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14975 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14977 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14979 mainMBB->addSuccessor(origMainMBB);
14980 mainMBB->addSuccessor(sinkMBB);
14983 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14984 TII->get(TargetOpcode::COPY), DstLoReg)
14986 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14987 TII->get(TargetOpcode::COPY), DstHiReg)
14990 MI->eraseFromParent();
14994 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14995 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14996 // in the .td file.
14997 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14998 const TargetInstrInfo *TII) {
15000 switch (MI->getOpcode()) {
15001 default: llvm_unreachable("illegal opcode!");
15002 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15003 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15004 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15005 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15006 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15007 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15008 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15009 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15012 DebugLoc dl = MI->getDebugLoc();
15013 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15015 unsigned NumArgs = MI->getNumOperands();
15016 for (unsigned i = 1; i < NumArgs; ++i) {
15017 MachineOperand &Op = MI->getOperand(i);
15018 if (!(Op.isReg() && Op.isImplicit()))
15019 MIB.addOperand(Op);
15021 if (MI->hasOneMemOperand())
15022 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15024 BuildMI(*BB, MI, dl,
15025 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15026 .addReg(X86::XMM0);
15028 MI->eraseFromParent();
15032 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15033 // defs in an instruction pattern
15034 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15035 const TargetInstrInfo *TII) {
15037 switch (MI->getOpcode()) {
15038 default: llvm_unreachable("illegal opcode!");
15039 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15040 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15041 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15042 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15043 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15044 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15045 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15046 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15049 DebugLoc dl = MI->getDebugLoc();
15050 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15052 unsigned NumArgs = MI->getNumOperands(); // remove the results
15053 for (unsigned i = 1; i < NumArgs; ++i) {
15054 MachineOperand &Op = MI->getOperand(i);
15055 if (!(Op.isReg() && Op.isImplicit()))
15056 MIB.addOperand(Op);
15058 if (MI->hasOneMemOperand())
15059 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15061 BuildMI(*BB, MI, dl,
15062 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15065 MI->eraseFromParent();
15069 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15070 const TargetInstrInfo *TII,
15071 const X86Subtarget* Subtarget) {
15072 DebugLoc dl = MI->getDebugLoc();
15074 // Address into RAX/EAX, other two args into ECX, EDX.
15075 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
15076 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15077 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15078 for (int i = 0; i < X86::AddrNumOperands; ++i)
15079 MIB.addOperand(MI->getOperand(i));
15081 unsigned ValOps = X86::AddrNumOperands;
15082 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15083 .addReg(MI->getOperand(ValOps).getReg());
15084 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15085 .addReg(MI->getOperand(ValOps+1).getReg());
15087 // The instruction doesn't actually take any operands though.
15088 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15090 MI->eraseFromParent(); // The pseudo is gone now.
15094 MachineBasicBlock *
15095 X86TargetLowering::EmitVAARG64WithCustomInserter(
15097 MachineBasicBlock *MBB) const {
15098 // Emit va_arg instruction on X86-64.
15100 // Operands to this pseudo-instruction:
15101 // 0 ) Output : destination address (reg)
15102 // 1-5) Input : va_list address (addr, i64mem)
15103 // 6 ) ArgSize : Size (in bytes) of vararg type
15104 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15105 // 8 ) Align : Alignment of type
15106 // 9 ) EFLAGS (implicit-def)
15108 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15109 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15111 unsigned DestReg = MI->getOperand(0).getReg();
15112 MachineOperand &Base = MI->getOperand(1);
15113 MachineOperand &Scale = MI->getOperand(2);
15114 MachineOperand &Index = MI->getOperand(3);
15115 MachineOperand &Disp = MI->getOperand(4);
15116 MachineOperand &Segment = MI->getOperand(5);
15117 unsigned ArgSize = MI->getOperand(6).getImm();
15118 unsigned ArgMode = MI->getOperand(7).getImm();
15119 unsigned Align = MI->getOperand(8).getImm();
15121 // Memory Reference
15122 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15123 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15124 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15126 // Machine Information
15127 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15128 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15129 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15130 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15131 DebugLoc DL = MI->getDebugLoc();
15133 // struct va_list {
15136 // i64 overflow_area (address)
15137 // i64 reg_save_area (address)
15139 // sizeof(va_list) = 24
15140 // alignment(va_list) = 8
15142 unsigned TotalNumIntRegs = 6;
15143 unsigned TotalNumXMMRegs = 8;
15144 bool UseGPOffset = (ArgMode == 1);
15145 bool UseFPOffset = (ArgMode == 2);
15146 unsigned MaxOffset = TotalNumIntRegs * 8 +
15147 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15149 /* Align ArgSize to a multiple of 8 */
15150 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15151 bool NeedsAlign = (Align > 8);
15153 MachineBasicBlock *thisMBB = MBB;
15154 MachineBasicBlock *overflowMBB;
15155 MachineBasicBlock *offsetMBB;
15156 MachineBasicBlock *endMBB;
15158 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15159 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15160 unsigned OffsetReg = 0;
15162 if (!UseGPOffset && !UseFPOffset) {
15163 // If we only pull from the overflow region, we don't create a branch.
15164 // We don't need to alter control flow.
15165 OffsetDestReg = 0; // unused
15166 OverflowDestReg = DestReg;
15169 overflowMBB = thisMBB;
15172 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15173 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15174 // If not, pull from overflow_area. (branch to overflowMBB)
15179 // offsetMBB overflowMBB
15184 // Registers for the PHI in endMBB
15185 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15186 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15188 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15189 MachineFunction *MF = MBB->getParent();
15190 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15191 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15192 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15194 MachineFunction::iterator MBBIter = MBB;
15197 // Insert the new basic blocks
15198 MF->insert(MBBIter, offsetMBB);
15199 MF->insert(MBBIter, overflowMBB);
15200 MF->insert(MBBIter, endMBB);
15202 // Transfer the remainder of MBB and its successor edges to endMBB.
15203 endMBB->splice(endMBB->begin(), thisMBB,
15204 llvm::next(MachineBasicBlock::iterator(MI)),
15206 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15208 // Make offsetMBB and overflowMBB successors of thisMBB
15209 thisMBB->addSuccessor(offsetMBB);
15210 thisMBB->addSuccessor(overflowMBB);
15212 // endMBB is a successor of both offsetMBB and overflowMBB
15213 offsetMBB->addSuccessor(endMBB);
15214 overflowMBB->addSuccessor(endMBB);
15216 // Load the offset value into a register
15217 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15218 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15222 .addDisp(Disp, UseFPOffset ? 4 : 0)
15223 .addOperand(Segment)
15224 .setMemRefs(MMOBegin, MMOEnd);
15226 // Check if there is enough room left to pull this argument.
15227 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15229 .addImm(MaxOffset + 8 - ArgSizeA8);
15231 // Branch to "overflowMBB" if offset >= max
15232 // Fall through to "offsetMBB" otherwise
15233 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15234 .addMBB(overflowMBB);
15237 // In offsetMBB, emit code to use the reg_save_area.
15239 assert(OffsetReg != 0);
15241 // Read the reg_save_area address.
15242 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15243 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15248 .addOperand(Segment)
15249 .setMemRefs(MMOBegin, MMOEnd);
15251 // Zero-extend the offset
15252 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15253 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15256 .addImm(X86::sub_32bit);
15258 // Add the offset to the reg_save_area to get the final address.
15259 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15260 .addReg(OffsetReg64)
15261 .addReg(RegSaveReg);
15263 // Compute the offset for the next argument
15264 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15265 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15267 .addImm(UseFPOffset ? 16 : 8);
15269 // Store it back into the va_list.
15270 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15274 .addDisp(Disp, UseFPOffset ? 4 : 0)
15275 .addOperand(Segment)
15276 .addReg(NextOffsetReg)
15277 .setMemRefs(MMOBegin, MMOEnd);
15280 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15285 // Emit code to use overflow area
15288 // Load the overflow_area address into a register.
15289 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15290 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15295 .addOperand(Segment)
15296 .setMemRefs(MMOBegin, MMOEnd);
15298 // If we need to align it, do so. Otherwise, just copy the address
15299 // to OverflowDestReg.
15301 // Align the overflow address
15302 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15303 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15305 // aligned_addr = (addr + (align-1)) & ~(align-1)
15306 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15307 .addReg(OverflowAddrReg)
15310 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15312 .addImm(~(uint64_t)(Align-1));
15314 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15315 .addReg(OverflowAddrReg);
15318 // Compute the next overflow address after this argument.
15319 // (the overflow address should be kept 8-byte aligned)
15320 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15321 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15322 .addReg(OverflowDestReg)
15323 .addImm(ArgSizeA8);
15325 // Store the new overflow address.
15326 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15331 .addOperand(Segment)
15332 .addReg(NextAddrReg)
15333 .setMemRefs(MMOBegin, MMOEnd);
15335 // If we branched, emit the PHI to the front of endMBB.
15337 BuildMI(*endMBB, endMBB->begin(), DL,
15338 TII->get(X86::PHI), DestReg)
15339 .addReg(OffsetDestReg).addMBB(offsetMBB)
15340 .addReg(OverflowDestReg).addMBB(overflowMBB);
15343 // Erase the pseudo instruction
15344 MI->eraseFromParent();
15349 MachineBasicBlock *
15350 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15352 MachineBasicBlock *MBB) const {
15353 // Emit code to save XMM registers to the stack. The ABI says that the
15354 // number of registers to save is given in %al, so it's theoretically
15355 // possible to do an indirect jump trick to avoid saving all of them,
15356 // however this code takes a simpler approach and just executes all
15357 // of the stores if %al is non-zero. It's less code, and it's probably
15358 // easier on the hardware branch predictor, and stores aren't all that
15359 // expensive anyway.
15361 // Create the new basic blocks. One block contains all the XMM stores,
15362 // and one block is the final destination regardless of whether any
15363 // stores were performed.
15364 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15365 MachineFunction *F = MBB->getParent();
15366 MachineFunction::iterator MBBIter = MBB;
15368 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15369 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15370 F->insert(MBBIter, XMMSaveMBB);
15371 F->insert(MBBIter, EndMBB);
15373 // Transfer the remainder of MBB and its successor edges to EndMBB.
15374 EndMBB->splice(EndMBB->begin(), MBB,
15375 llvm::next(MachineBasicBlock::iterator(MI)),
15377 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15379 // The original block will now fall through to the XMM save block.
15380 MBB->addSuccessor(XMMSaveMBB);
15381 // The XMMSaveMBB will fall through to the end block.
15382 XMMSaveMBB->addSuccessor(EndMBB);
15384 // Now add the instructions.
15385 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15386 DebugLoc DL = MI->getDebugLoc();
15388 unsigned CountReg = MI->getOperand(0).getReg();
15389 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15390 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15392 if (!Subtarget->isTargetWin64()) {
15393 // If %al is 0, branch around the XMM save block.
15394 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15395 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15396 MBB->addSuccessor(EndMBB);
15399 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
15400 // that was just emitted, but clearly shouldn't be "saved".
15401 assert((MI->getNumOperands() <= 3 ||
15402 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
15403 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
15404 && "Expected last argument to be EFLAGS");
15405 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15406 // In the XMM save block, save all the XMM argument registers.
15407 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
15408 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15409 MachineMemOperand *MMO =
15410 F->getMachineMemOperand(
15411 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15412 MachineMemOperand::MOStore,
15413 /*Size=*/16, /*Align=*/16);
15414 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15415 .addFrameIndex(RegSaveFrameIndex)
15416 .addImm(/*Scale=*/1)
15417 .addReg(/*IndexReg=*/0)
15418 .addImm(/*Disp=*/Offset)
15419 .addReg(/*Segment=*/0)
15420 .addReg(MI->getOperand(i).getReg())
15421 .addMemOperand(MMO);
15424 MI->eraseFromParent(); // The pseudo instruction is gone now.
15429 // The EFLAGS operand of SelectItr might be missing a kill marker
15430 // because there were multiple uses of EFLAGS, and ISel didn't know
15431 // which to mark. Figure out whether SelectItr should have had a
15432 // kill marker, and set it if it should. Returns the correct kill
15434 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15435 MachineBasicBlock* BB,
15436 const TargetRegisterInfo* TRI) {
15437 // Scan forward through BB for a use/def of EFLAGS.
15438 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15439 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15440 const MachineInstr& mi = *miI;
15441 if (mi.readsRegister(X86::EFLAGS))
15443 if (mi.definesRegister(X86::EFLAGS))
15444 break; // Should have kill-flag - update below.
15447 // If we hit the end of the block, check whether EFLAGS is live into a
15449 if (miI == BB->end()) {
15450 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15451 sEnd = BB->succ_end();
15452 sItr != sEnd; ++sItr) {
15453 MachineBasicBlock* succ = *sItr;
15454 if (succ->isLiveIn(X86::EFLAGS))
15459 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15460 // out. SelectMI should have a kill flag on EFLAGS.
15461 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15465 MachineBasicBlock *
15466 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15467 MachineBasicBlock *BB) const {
15468 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15469 DebugLoc DL = MI->getDebugLoc();
15471 // To "insert" a SELECT_CC instruction, we actually have to insert the
15472 // diamond control-flow pattern. The incoming instruction knows the
15473 // destination vreg to set, the condition code register to branch on, the
15474 // true/false values to select between, and a branch opcode to use.
15475 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15476 MachineFunction::iterator It = BB;
15482 // cmpTY ccX, r1, r2
15484 // fallthrough --> copy0MBB
15485 MachineBasicBlock *thisMBB = BB;
15486 MachineFunction *F = BB->getParent();
15487 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15488 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15489 F->insert(It, copy0MBB);
15490 F->insert(It, sinkMBB);
15492 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15493 // live into the sink and copy blocks.
15494 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15495 if (!MI->killsRegister(X86::EFLAGS) &&
15496 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15497 copy0MBB->addLiveIn(X86::EFLAGS);
15498 sinkMBB->addLiveIn(X86::EFLAGS);
15501 // Transfer the remainder of BB and its successor edges to sinkMBB.
15502 sinkMBB->splice(sinkMBB->begin(), BB,
15503 llvm::next(MachineBasicBlock::iterator(MI)),
15505 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15507 // Add the true and fallthrough blocks as its successors.
15508 BB->addSuccessor(copy0MBB);
15509 BB->addSuccessor(sinkMBB);
15511 // Create the conditional branch instruction.
15513 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15514 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15517 // %FalseValue = ...
15518 // # fallthrough to sinkMBB
15519 copy0MBB->addSuccessor(sinkMBB);
15522 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15524 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15525 TII->get(X86::PHI), MI->getOperand(0).getReg())
15526 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15527 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15529 MI->eraseFromParent(); // The pseudo instruction is gone now.
15533 MachineBasicBlock *
15534 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15535 bool Is64Bit) const {
15536 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15537 DebugLoc DL = MI->getDebugLoc();
15538 MachineFunction *MF = BB->getParent();
15539 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15541 assert(getTargetMachine().Options.EnableSegmentedStacks);
15543 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15544 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15547 // ... [Till the alloca]
15548 // If stacklet is not large enough, jump to mallocMBB
15551 // Allocate by subtracting from RSP
15552 // Jump to continueMBB
15555 // Allocate by call to runtime
15559 // [rest of original BB]
15562 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15563 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15564 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15566 MachineRegisterInfo &MRI = MF->getRegInfo();
15567 const TargetRegisterClass *AddrRegClass =
15568 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15570 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15571 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15572 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15573 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15574 sizeVReg = MI->getOperand(1).getReg(),
15575 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15577 MachineFunction::iterator MBBIter = BB;
15580 MF->insert(MBBIter, bumpMBB);
15581 MF->insert(MBBIter, mallocMBB);
15582 MF->insert(MBBIter, continueMBB);
15584 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15585 (MachineBasicBlock::iterator(MI)), BB->end());
15586 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15588 // Add code to the main basic block to check if the stack limit has been hit,
15589 // and if so, jump to mallocMBB otherwise to bumpMBB.
15590 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15591 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15592 .addReg(tmpSPVReg).addReg(sizeVReg);
15593 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15594 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15595 .addReg(SPLimitVReg);
15596 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15598 // bumpMBB simply decreases the stack pointer, since we know the current
15599 // stacklet has enough space.
15600 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15601 .addReg(SPLimitVReg);
15602 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15603 .addReg(SPLimitVReg);
15604 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15606 // Calls into a routine in libgcc to allocate more space from the heap.
15607 const uint32_t *RegMask =
15608 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15610 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15612 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15613 .addExternalSymbol("__morestack_allocate_stack_space")
15614 .addRegMask(RegMask)
15615 .addReg(X86::RDI, RegState::Implicit)
15616 .addReg(X86::RAX, RegState::ImplicitDefine);
15618 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15620 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15621 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15622 .addExternalSymbol("__morestack_allocate_stack_space")
15623 .addRegMask(RegMask)
15624 .addReg(X86::EAX, RegState::ImplicitDefine);
15628 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15631 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15632 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15633 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15635 // Set up the CFG correctly.
15636 BB->addSuccessor(bumpMBB);
15637 BB->addSuccessor(mallocMBB);
15638 mallocMBB->addSuccessor(continueMBB);
15639 bumpMBB->addSuccessor(continueMBB);
15641 // Take care of the PHI nodes.
15642 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15643 MI->getOperand(0).getReg())
15644 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15645 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15647 // Delete the original pseudo instruction.
15648 MI->eraseFromParent();
15651 return continueMBB;
15654 MachineBasicBlock *
15655 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15656 MachineBasicBlock *BB) const {
15657 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15658 DebugLoc DL = MI->getDebugLoc();
15660 assert(!Subtarget->isTargetMacho());
15662 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15663 // non-trivial part is impdef of ESP.
15665 if (Subtarget->isTargetWin64()) {
15666 if (Subtarget->isTargetCygMing()) {
15667 // ___chkstk(Mingw64):
15668 // Clobbers R10, R11, RAX and EFLAGS.
15670 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15671 .addExternalSymbol("___chkstk")
15672 .addReg(X86::RAX, RegState::Implicit)
15673 .addReg(X86::RSP, RegState::Implicit)
15674 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15675 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15676 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15678 // __chkstk(MSVCRT): does not update stack pointer.
15679 // Clobbers R10, R11 and EFLAGS.
15680 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15681 .addExternalSymbol("__chkstk")
15682 .addReg(X86::RAX, RegState::Implicit)
15683 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15684 // RAX has the offset to be subtracted from RSP.
15685 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15690 const char *StackProbeSymbol =
15691 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15693 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15694 .addExternalSymbol(StackProbeSymbol)
15695 .addReg(X86::EAX, RegState::Implicit)
15696 .addReg(X86::ESP, RegState::Implicit)
15697 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15698 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15699 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15702 MI->eraseFromParent(); // The pseudo instruction is gone now.
15706 MachineBasicBlock *
15707 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15708 MachineBasicBlock *BB) const {
15709 // This is pretty easy. We're taking the value that we received from
15710 // our load from the relocation, sticking it in either RDI (x86-64)
15711 // or EAX and doing an indirect call. The return value will then
15712 // be in the normal return register.
15713 const X86InstrInfo *TII
15714 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15715 DebugLoc DL = MI->getDebugLoc();
15716 MachineFunction *F = BB->getParent();
15718 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15719 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15721 // Get a register mask for the lowered call.
15722 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15723 // proper register mask.
15724 const uint32_t *RegMask =
15725 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15726 if (Subtarget->is64Bit()) {
15727 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15728 TII->get(X86::MOV64rm), X86::RDI)
15730 .addImm(0).addReg(0)
15731 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15732 MI->getOperand(3).getTargetFlags())
15734 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15735 addDirectMem(MIB, X86::RDI);
15736 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15737 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15738 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15739 TII->get(X86::MOV32rm), X86::EAX)
15741 .addImm(0).addReg(0)
15742 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15743 MI->getOperand(3).getTargetFlags())
15745 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15746 addDirectMem(MIB, X86::EAX);
15747 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15749 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15750 TII->get(X86::MOV32rm), X86::EAX)
15751 .addReg(TII->getGlobalBaseReg(F))
15752 .addImm(0).addReg(0)
15753 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15754 MI->getOperand(3).getTargetFlags())
15756 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15757 addDirectMem(MIB, X86::EAX);
15758 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15761 MI->eraseFromParent(); // The pseudo instruction is gone now.
15765 MachineBasicBlock *
15766 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15767 MachineBasicBlock *MBB) const {
15768 DebugLoc DL = MI->getDebugLoc();
15769 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15771 MachineFunction *MF = MBB->getParent();
15772 MachineRegisterInfo &MRI = MF->getRegInfo();
15774 const BasicBlock *BB = MBB->getBasicBlock();
15775 MachineFunction::iterator I = MBB;
15778 // Memory Reference
15779 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15780 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15783 unsigned MemOpndSlot = 0;
15785 unsigned CurOp = 0;
15787 DstReg = MI->getOperand(CurOp++).getReg();
15788 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15789 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15790 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15791 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15793 MemOpndSlot = CurOp;
15795 MVT PVT = getPointerTy();
15796 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15797 "Invalid Pointer Size!");
15799 // For v = setjmp(buf), we generate
15802 // buf[LabelOffset] = restoreMBB
15803 // SjLjSetup restoreMBB
15809 // v = phi(main, restore)
15814 MachineBasicBlock *thisMBB = MBB;
15815 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15816 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15817 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15818 MF->insert(I, mainMBB);
15819 MF->insert(I, sinkMBB);
15820 MF->push_back(restoreMBB);
15822 MachineInstrBuilder MIB;
15824 // Transfer the remainder of BB and its successor edges to sinkMBB.
15825 sinkMBB->splice(sinkMBB->begin(), MBB,
15826 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15827 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15830 unsigned PtrStoreOpc = 0;
15831 unsigned LabelReg = 0;
15832 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15833 Reloc::Model RM = getTargetMachine().getRelocationModel();
15834 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15835 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15837 // Prepare IP either in reg or imm.
15838 if (!UseImmLabel) {
15839 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15840 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15841 LabelReg = MRI.createVirtualRegister(PtrRC);
15842 if (Subtarget->is64Bit()) {
15843 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15847 .addMBB(restoreMBB)
15850 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15851 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15852 .addReg(XII->getGlobalBaseReg(MF))
15855 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15859 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15861 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15862 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15863 if (i == X86::AddrDisp)
15864 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15866 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15869 MIB.addReg(LabelReg);
15871 MIB.addMBB(restoreMBB);
15872 MIB.setMemRefs(MMOBegin, MMOEnd);
15874 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15875 .addMBB(restoreMBB);
15877 const X86RegisterInfo *RegInfo =
15878 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15879 MIB.addRegMask(RegInfo->getNoPreservedMask());
15880 thisMBB->addSuccessor(mainMBB);
15881 thisMBB->addSuccessor(restoreMBB);
15885 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15886 mainMBB->addSuccessor(sinkMBB);
15889 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15890 TII->get(X86::PHI), DstReg)
15891 .addReg(mainDstReg).addMBB(mainMBB)
15892 .addReg(restoreDstReg).addMBB(restoreMBB);
15895 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15896 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15897 restoreMBB->addSuccessor(sinkMBB);
15899 MI->eraseFromParent();
15903 MachineBasicBlock *
15904 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15905 MachineBasicBlock *MBB) const {
15906 DebugLoc DL = MI->getDebugLoc();
15907 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15909 MachineFunction *MF = MBB->getParent();
15910 MachineRegisterInfo &MRI = MF->getRegInfo();
15912 // Memory Reference
15913 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15914 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15916 MVT PVT = getPointerTy();
15917 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15918 "Invalid Pointer Size!");
15920 const TargetRegisterClass *RC =
15921 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15922 unsigned Tmp = MRI.createVirtualRegister(RC);
15923 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15924 const X86RegisterInfo *RegInfo =
15925 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15926 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15927 unsigned SP = RegInfo->getStackRegister();
15929 MachineInstrBuilder MIB;
15931 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15932 const int64_t SPOffset = 2 * PVT.getStoreSize();
15934 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15935 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15938 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15939 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15940 MIB.addOperand(MI->getOperand(i));
15941 MIB.setMemRefs(MMOBegin, MMOEnd);
15943 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15944 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15945 if (i == X86::AddrDisp)
15946 MIB.addDisp(MI->getOperand(i), LabelOffset);
15948 MIB.addOperand(MI->getOperand(i));
15950 MIB.setMemRefs(MMOBegin, MMOEnd);
15952 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15953 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15954 if (i == X86::AddrDisp)
15955 MIB.addDisp(MI->getOperand(i), SPOffset);
15957 MIB.addOperand(MI->getOperand(i));
15959 MIB.setMemRefs(MMOBegin, MMOEnd);
15961 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15963 MI->eraseFromParent();
15967 MachineBasicBlock *
15968 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15969 MachineBasicBlock *BB) const {
15970 switch (MI->getOpcode()) {
15971 default: llvm_unreachable("Unexpected instr type to insert");
15972 case X86::TAILJMPd64:
15973 case X86::TAILJMPr64:
15974 case X86::TAILJMPm64:
15975 llvm_unreachable("TAILJMP64 would not be touched here.");
15976 case X86::TCRETURNdi64:
15977 case X86::TCRETURNri64:
15978 case X86::TCRETURNmi64:
15980 case X86::WIN_ALLOCA:
15981 return EmitLoweredWinAlloca(MI, BB);
15982 case X86::SEG_ALLOCA_32:
15983 return EmitLoweredSegAlloca(MI, BB, false);
15984 case X86::SEG_ALLOCA_64:
15985 return EmitLoweredSegAlloca(MI, BB, true);
15986 case X86::TLSCall_32:
15987 case X86::TLSCall_64:
15988 return EmitLoweredTLSCall(MI, BB);
15989 case X86::CMOV_GR8:
15990 case X86::CMOV_FR32:
15991 case X86::CMOV_FR64:
15992 case X86::CMOV_V4F32:
15993 case X86::CMOV_V2F64:
15994 case X86::CMOV_V2I64:
15995 case X86::CMOV_V8F32:
15996 case X86::CMOV_V4F64:
15997 case X86::CMOV_V4I64:
15998 case X86::CMOV_V16F32:
15999 case X86::CMOV_V8F64:
16000 case X86::CMOV_V8I64:
16001 case X86::CMOV_GR16:
16002 case X86::CMOV_GR32:
16003 case X86::CMOV_RFP32:
16004 case X86::CMOV_RFP64:
16005 case X86::CMOV_RFP80:
16006 return EmitLoweredSelect(MI, BB);
16008 case X86::FP32_TO_INT16_IN_MEM:
16009 case X86::FP32_TO_INT32_IN_MEM:
16010 case X86::FP32_TO_INT64_IN_MEM:
16011 case X86::FP64_TO_INT16_IN_MEM:
16012 case X86::FP64_TO_INT32_IN_MEM:
16013 case X86::FP64_TO_INT64_IN_MEM:
16014 case X86::FP80_TO_INT16_IN_MEM:
16015 case X86::FP80_TO_INT32_IN_MEM:
16016 case X86::FP80_TO_INT64_IN_MEM: {
16017 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16018 DebugLoc DL = MI->getDebugLoc();
16020 // Change the floating point control register to use "round towards zero"
16021 // mode when truncating to an integer value.
16022 MachineFunction *F = BB->getParent();
16023 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
16024 addFrameReference(BuildMI(*BB, MI, DL,
16025 TII->get(X86::FNSTCW16m)), CWFrameIdx);
16027 // Load the old value of the high byte of the control word...
16029 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
16030 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
16033 // Set the high part to be round to zero...
16034 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
16037 // Reload the modified control word now...
16038 addFrameReference(BuildMI(*BB, MI, DL,
16039 TII->get(X86::FLDCW16m)), CWFrameIdx);
16041 // Restore the memory image of control word to original value
16042 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
16045 // Get the X86 opcode to use.
16047 switch (MI->getOpcode()) {
16048 default: llvm_unreachable("illegal opcode!");
16049 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
16050 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
16051 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
16052 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
16053 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
16054 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
16055 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
16056 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
16057 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
16061 MachineOperand &Op = MI->getOperand(0);
16063 AM.BaseType = X86AddressMode::RegBase;
16064 AM.Base.Reg = Op.getReg();
16066 AM.BaseType = X86AddressMode::FrameIndexBase;
16067 AM.Base.FrameIndex = Op.getIndex();
16069 Op = MI->getOperand(1);
16071 AM.Scale = Op.getImm();
16072 Op = MI->getOperand(2);
16074 AM.IndexReg = Op.getImm();
16075 Op = MI->getOperand(3);
16076 if (Op.isGlobal()) {
16077 AM.GV = Op.getGlobal();
16079 AM.Disp = Op.getImm();
16081 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
16082 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16084 // Reload the original control word now.
16085 addFrameReference(BuildMI(*BB, MI, DL,
16086 TII->get(X86::FLDCW16m)), CWFrameIdx);
16088 MI->eraseFromParent(); // The pseudo instruction is gone now.
16091 // String/text processing lowering.
16092 case X86::PCMPISTRM128REG:
16093 case X86::VPCMPISTRM128REG:
16094 case X86::PCMPISTRM128MEM:
16095 case X86::VPCMPISTRM128MEM:
16096 case X86::PCMPESTRM128REG:
16097 case X86::VPCMPESTRM128REG:
16098 case X86::PCMPESTRM128MEM:
16099 case X86::VPCMPESTRM128MEM:
16100 assert(Subtarget->hasSSE42() &&
16101 "Target must have SSE4.2 or AVX features enabled");
16102 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16104 // String/text processing lowering.
16105 case X86::PCMPISTRIREG:
16106 case X86::VPCMPISTRIREG:
16107 case X86::PCMPISTRIMEM:
16108 case X86::VPCMPISTRIMEM:
16109 case X86::PCMPESTRIREG:
16110 case X86::VPCMPESTRIREG:
16111 case X86::PCMPESTRIMEM:
16112 case X86::VPCMPESTRIMEM:
16113 assert(Subtarget->hasSSE42() &&
16114 "Target must have SSE4.2 or AVX features enabled");
16115 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16117 // Thread synchronization.
16119 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16123 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16125 // Atomic Lowering.
16126 case X86::ATOMAND8:
16127 case X86::ATOMAND16:
16128 case X86::ATOMAND32:
16129 case X86::ATOMAND64:
16132 case X86::ATOMOR16:
16133 case X86::ATOMOR32:
16134 case X86::ATOMOR64:
16136 case X86::ATOMXOR16:
16137 case X86::ATOMXOR8:
16138 case X86::ATOMXOR32:
16139 case X86::ATOMXOR64:
16141 case X86::ATOMNAND8:
16142 case X86::ATOMNAND16:
16143 case X86::ATOMNAND32:
16144 case X86::ATOMNAND64:
16146 case X86::ATOMMAX8:
16147 case X86::ATOMMAX16:
16148 case X86::ATOMMAX32:
16149 case X86::ATOMMAX64:
16151 case X86::ATOMMIN8:
16152 case X86::ATOMMIN16:
16153 case X86::ATOMMIN32:
16154 case X86::ATOMMIN64:
16156 case X86::ATOMUMAX8:
16157 case X86::ATOMUMAX16:
16158 case X86::ATOMUMAX32:
16159 case X86::ATOMUMAX64:
16161 case X86::ATOMUMIN8:
16162 case X86::ATOMUMIN16:
16163 case X86::ATOMUMIN32:
16164 case X86::ATOMUMIN64:
16165 return EmitAtomicLoadArith(MI, BB);
16167 // This group does 64-bit operations on a 32-bit host.
16168 case X86::ATOMAND6432:
16169 case X86::ATOMOR6432:
16170 case X86::ATOMXOR6432:
16171 case X86::ATOMNAND6432:
16172 case X86::ATOMADD6432:
16173 case X86::ATOMSUB6432:
16174 case X86::ATOMMAX6432:
16175 case X86::ATOMMIN6432:
16176 case X86::ATOMUMAX6432:
16177 case X86::ATOMUMIN6432:
16178 case X86::ATOMSWAP6432:
16179 return EmitAtomicLoadArith6432(MI, BB);
16181 case X86::VASTART_SAVE_XMM_REGS:
16182 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16184 case X86::VAARG_64:
16185 return EmitVAARG64WithCustomInserter(MI, BB);
16187 case X86::EH_SjLj_SetJmp32:
16188 case X86::EH_SjLj_SetJmp64:
16189 return emitEHSjLjSetJmp(MI, BB);
16191 case X86::EH_SjLj_LongJmp32:
16192 case X86::EH_SjLj_LongJmp64:
16193 return emitEHSjLjLongJmp(MI, BB);
16195 case TargetOpcode::STACKMAP:
16196 case TargetOpcode::PATCHPOINT:
16197 return emitPatchPoint(MI, BB);
16201 //===----------------------------------------------------------------------===//
16202 // X86 Optimization Hooks
16203 //===----------------------------------------------------------------------===//
16205 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16208 const SelectionDAG &DAG,
16209 unsigned Depth) const {
16210 unsigned BitWidth = KnownZero.getBitWidth();
16211 unsigned Opc = Op.getOpcode();
16212 assert((Opc >= ISD::BUILTIN_OP_END ||
16213 Opc == ISD::INTRINSIC_WO_CHAIN ||
16214 Opc == ISD::INTRINSIC_W_CHAIN ||
16215 Opc == ISD::INTRINSIC_VOID) &&
16216 "Should use MaskedValueIsZero if you don't know whether Op"
16217 " is a target node!");
16219 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16233 // These nodes' second result is a boolean.
16234 if (Op.getResNo() == 0)
16237 case X86ISD::SETCC:
16238 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16240 case ISD::INTRINSIC_WO_CHAIN: {
16241 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16242 unsigned NumLoBits = 0;
16245 case Intrinsic::x86_sse_movmsk_ps:
16246 case Intrinsic::x86_avx_movmsk_ps_256:
16247 case Intrinsic::x86_sse2_movmsk_pd:
16248 case Intrinsic::x86_avx_movmsk_pd_256:
16249 case Intrinsic::x86_mmx_pmovmskb:
16250 case Intrinsic::x86_sse2_pmovmskb_128:
16251 case Intrinsic::x86_avx2_pmovmskb: {
16252 // High bits of movmskp{s|d}, pmovmskb are known zero.
16254 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16255 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16256 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16257 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16258 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16259 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16260 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16261 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16263 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16272 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16273 unsigned Depth) const {
16274 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16275 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16276 return Op.getValueType().getScalarType().getSizeInBits();
16282 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16283 /// node is a GlobalAddress + offset.
16284 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16285 const GlobalValue* &GA,
16286 int64_t &Offset) const {
16287 if (N->getOpcode() == X86ISD::Wrapper) {
16288 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16289 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16290 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16294 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16297 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16298 /// same as extracting the high 128-bit part of 256-bit vector and then
16299 /// inserting the result into the low part of a new 256-bit vector
16300 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16301 EVT VT = SVOp->getValueType(0);
16302 unsigned NumElems = VT.getVectorNumElements();
16304 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16305 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16306 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16307 SVOp->getMaskElt(j) >= 0)
16313 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16314 /// same as extracting the low 128-bit part of 256-bit vector and then
16315 /// inserting the result into the high part of a new 256-bit vector
16316 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16317 EVT VT = SVOp->getValueType(0);
16318 unsigned NumElems = VT.getVectorNumElements();
16320 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16321 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16322 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16323 SVOp->getMaskElt(j) >= 0)
16329 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16330 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16331 TargetLowering::DAGCombinerInfo &DCI,
16332 const X86Subtarget* Subtarget) {
16334 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16335 SDValue V1 = SVOp->getOperand(0);
16336 SDValue V2 = SVOp->getOperand(1);
16337 EVT VT = SVOp->getValueType(0);
16338 unsigned NumElems = VT.getVectorNumElements();
16340 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16341 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16345 // V UNDEF BUILD_VECTOR UNDEF
16347 // CONCAT_VECTOR CONCAT_VECTOR
16350 // RESULT: V + zero extended
16352 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16353 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16354 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16357 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16360 // To match the shuffle mask, the first half of the mask should
16361 // be exactly the first vector, and all the rest a splat with the
16362 // first element of the second one.
16363 for (unsigned i = 0; i != NumElems/2; ++i)
16364 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16365 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16368 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16369 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16370 if (Ld->hasNUsesOfValue(1, 0)) {
16371 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16372 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16374 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16375 array_lengthof(Ops),
16377 Ld->getPointerInfo(),
16378 Ld->getAlignment(),
16379 false/*isVolatile*/, true/*ReadMem*/,
16380 false/*WriteMem*/);
16382 // Make sure the newly-created LOAD is in the same position as Ld in
16383 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16384 // and update uses of Ld's output chain to use the TokenFactor.
16385 if (Ld->hasAnyUseOfValue(1)) {
16386 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16387 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16388 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16389 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16390 SDValue(ResNode.getNode(), 1));
16393 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16397 // Emit a zeroed vector and insert the desired subvector on its
16399 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16400 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16401 return DCI.CombineTo(N, InsV);
16404 //===--------------------------------------------------------------------===//
16405 // Combine some shuffles into subvector extracts and inserts:
16408 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16409 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16410 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16411 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16412 return DCI.CombineTo(N, InsV);
16415 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16416 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16417 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16418 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16419 return DCI.CombineTo(N, InsV);
16425 /// PerformShuffleCombine - Performs several different shuffle combines.
16426 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16427 TargetLowering::DAGCombinerInfo &DCI,
16428 const X86Subtarget *Subtarget) {
16430 EVT VT = N->getValueType(0);
16432 // Don't create instructions with illegal types after legalize types has run.
16433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16434 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16437 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16438 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16439 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16440 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16442 // Only handle 128 wide vector from here on.
16443 if (!VT.is128BitVector())
16446 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16447 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16448 // consecutive, non-overlapping, and in the right order.
16449 SmallVector<SDValue, 16> Elts;
16450 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16451 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16453 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
16456 /// PerformTruncateCombine - Converts truncate operation to
16457 /// a sequence of vector shuffle operations.
16458 /// It is possible when we truncate 256-bit vector to 128-bit vector
16459 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16460 TargetLowering::DAGCombinerInfo &DCI,
16461 const X86Subtarget *Subtarget) {
16465 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16466 /// specific shuffle of a load can be folded into a single element load.
16467 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16468 /// shuffles have been customed lowered so we need to handle those here.
16469 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16470 TargetLowering::DAGCombinerInfo &DCI) {
16471 if (DCI.isBeforeLegalizeOps())
16474 SDValue InVec = N->getOperand(0);
16475 SDValue EltNo = N->getOperand(1);
16477 if (!isa<ConstantSDNode>(EltNo))
16480 EVT VT = InVec.getValueType();
16482 bool HasShuffleIntoBitcast = false;
16483 if (InVec.getOpcode() == ISD::BITCAST) {
16484 // Don't duplicate a load with other uses.
16485 if (!InVec.hasOneUse())
16487 EVT BCVT = InVec.getOperand(0).getValueType();
16488 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16490 InVec = InVec.getOperand(0);
16491 HasShuffleIntoBitcast = true;
16494 if (!isTargetShuffle(InVec.getOpcode()))
16497 // Don't duplicate a load with other uses.
16498 if (!InVec.hasOneUse())
16501 SmallVector<int, 16> ShuffleMask;
16503 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16507 // Select the input vector, guarding against out of range extract vector.
16508 unsigned NumElems = VT.getVectorNumElements();
16509 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16510 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16511 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16512 : InVec.getOperand(1);
16514 // If inputs to shuffle are the same for both ops, then allow 2 uses
16515 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16517 if (LdNode.getOpcode() == ISD::BITCAST) {
16518 // Don't duplicate a load with other uses.
16519 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16522 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16523 LdNode = LdNode.getOperand(0);
16526 if (!ISD::isNormalLoad(LdNode.getNode()))
16529 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16531 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16534 if (HasShuffleIntoBitcast) {
16535 // If there's a bitcast before the shuffle, check if the load type and
16536 // alignment is valid.
16537 unsigned Align = LN0->getAlignment();
16538 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16539 unsigned NewAlign = TLI.getDataLayout()->
16540 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16542 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16546 // All checks match so transform back to vector_shuffle so that DAG combiner
16547 // can finish the job
16550 // Create shuffle node taking into account the case that its a unary shuffle
16551 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16552 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16553 InVec.getOperand(0), Shuffle,
16555 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16556 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16560 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16561 /// generation and convert it from being a bunch of shuffles and extracts
16562 /// to a simple store and scalar loads to extract the elements.
16563 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16564 TargetLowering::DAGCombinerInfo &DCI) {
16565 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16566 if (NewOp.getNode())
16569 SDValue InputVector = N->getOperand(0);
16571 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16572 // from mmx to v2i32 has a single usage.
16573 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16574 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16575 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16576 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16577 N->getValueType(0),
16578 InputVector.getNode()->getOperand(0));
16580 // Only operate on vectors of 4 elements, where the alternative shuffling
16581 // gets to be more expensive.
16582 if (InputVector.getValueType() != MVT::v4i32)
16585 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16586 // single use which is a sign-extend or zero-extend, and all elements are
16588 SmallVector<SDNode *, 4> Uses;
16589 unsigned ExtractedElements = 0;
16590 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16591 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16592 if (UI.getUse().getResNo() != InputVector.getResNo())
16595 SDNode *Extract = *UI;
16596 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16599 if (Extract->getValueType(0) != MVT::i32)
16601 if (!Extract->hasOneUse())
16603 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16604 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16606 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16609 // Record which element was extracted.
16610 ExtractedElements |=
16611 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16613 Uses.push_back(Extract);
16616 // If not all the elements were used, this may not be worthwhile.
16617 if (ExtractedElements != 15)
16620 // Ok, we've now decided to do the transformation.
16621 SDLoc dl(InputVector);
16623 // Store the value to a temporary stack slot.
16624 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16625 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16626 MachinePointerInfo(), false, false, 0);
16628 // Replace each use (extract) with a load of the appropriate element.
16629 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16630 UE = Uses.end(); UI != UE; ++UI) {
16631 SDNode *Extract = *UI;
16633 // cOMpute the element's address.
16634 SDValue Idx = Extract->getOperand(1);
16636 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16637 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16638 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16639 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16641 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16642 StackPtr, OffsetVal);
16644 // Load the scalar.
16645 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16646 ScalarAddr, MachinePointerInfo(),
16647 false, false, false, 0);
16649 // Replace the exact with the load.
16650 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16653 // The replacement was made in place; don't return anything.
16657 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16658 static std::pair<unsigned, bool>
16659 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16660 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16661 if (!VT.isVector())
16662 return std::make_pair(0, false);
16664 bool NeedSplit = false;
16665 switch (VT.getSimpleVT().SimpleTy) {
16666 default: return std::make_pair(0, false);
16670 if (!Subtarget->hasAVX2())
16672 if (!Subtarget->hasAVX())
16673 return std::make_pair(0, false);
16678 if (!Subtarget->hasSSE2())
16679 return std::make_pair(0, false);
16682 // SSE2 has only a small subset of the operations.
16683 bool hasUnsigned = Subtarget->hasSSE41() ||
16684 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16685 bool hasSigned = Subtarget->hasSSE41() ||
16686 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16688 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16691 // Check for x CC y ? x : y.
16692 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16693 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16698 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16701 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16704 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16707 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16709 // Check for x CC y ? y : x -- a min/max with reversed arms.
16710 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16711 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16716 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16719 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16722 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16725 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16729 return std::make_pair(Opc, NeedSplit);
16732 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16734 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16735 TargetLowering::DAGCombinerInfo &DCI,
16736 const X86Subtarget *Subtarget) {
16738 SDValue Cond = N->getOperand(0);
16739 // Get the LHS/RHS of the select.
16740 SDValue LHS = N->getOperand(1);
16741 SDValue RHS = N->getOperand(2);
16742 EVT VT = LHS.getValueType();
16743 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16745 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16746 // instructions match the semantics of the common C idiom x<y?x:y but not
16747 // x<=y?x:y, because of how they handle negative zero (which can be
16748 // ignored in unsafe-math mode).
16749 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16750 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16751 (Subtarget->hasSSE2() ||
16752 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16753 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16755 unsigned Opcode = 0;
16756 // Check for x CC y ? x : y.
16757 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16758 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16762 // Converting this to a min would handle NaNs incorrectly, and swapping
16763 // the operands would cause it to handle comparisons between positive
16764 // and negative zero incorrectly.
16765 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16766 if (!DAG.getTarget().Options.UnsafeFPMath &&
16767 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16769 std::swap(LHS, RHS);
16771 Opcode = X86ISD::FMIN;
16774 // Converting this to a min would handle comparisons between positive
16775 // and negative zero incorrectly.
16776 if (!DAG.getTarget().Options.UnsafeFPMath &&
16777 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16779 Opcode = X86ISD::FMIN;
16782 // Converting this to a min would handle both negative zeros and NaNs
16783 // incorrectly, but we can swap the operands to fix both.
16784 std::swap(LHS, RHS);
16788 Opcode = X86ISD::FMIN;
16792 // Converting this to a max would handle comparisons between positive
16793 // and negative zero incorrectly.
16794 if (!DAG.getTarget().Options.UnsafeFPMath &&
16795 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16797 Opcode = X86ISD::FMAX;
16800 // Converting this to a max would handle NaNs incorrectly, and swapping
16801 // the operands would cause it to handle comparisons between positive
16802 // and negative zero incorrectly.
16803 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16804 if (!DAG.getTarget().Options.UnsafeFPMath &&
16805 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16807 std::swap(LHS, RHS);
16809 Opcode = X86ISD::FMAX;
16812 // Converting this to a max would handle both negative zeros and NaNs
16813 // incorrectly, but we can swap the operands to fix both.
16814 std::swap(LHS, RHS);
16818 Opcode = X86ISD::FMAX;
16821 // Check for x CC y ? y : x -- a min/max with reversed arms.
16822 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16823 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16827 // Converting this to a min would handle comparisons between positive
16828 // and negative zero incorrectly, and swapping the operands would
16829 // cause it to handle NaNs incorrectly.
16830 if (!DAG.getTarget().Options.UnsafeFPMath &&
16831 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16832 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16834 std::swap(LHS, RHS);
16836 Opcode = X86ISD::FMIN;
16839 // Converting this to a min would handle NaNs incorrectly.
16840 if (!DAG.getTarget().Options.UnsafeFPMath &&
16841 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16843 Opcode = X86ISD::FMIN;
16846 // Converting this to a min would handle both negative zeros and NaNs
16847 // incorrectly, but we can swap the operands to fix both.
16848 std::swap(LHS, RHS);
16852 Opcode = X86ISD::FMIN;
16856 // Converting this to a max would handle NaNs incorrectly.
16857 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16859 Opcode = X86ISD::FMAX;
16862 // Converting this to a max would handle comparisons between positive
16863 // and negative zero incorrectly, and swapping the operands would
16864 // cause it to handle NaNs incorrectly.
16865 if (!DAG.getTarget().Options.UnsafeFPMath &&
16866 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16867 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16869 std::swap(LHS, RHS);
16871 Opcode = X86ISD::FMAX;
16874 // Converting this to a max would handle both negative zeros and NaNs
16875 // incorrectly, but we can swap the operands to fix both.
16876 std::swap(LHS, RHS);
16880 Opcode = X86ISD::FMAX;
16886 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16889 EVT CondVT = Cond.getValueType();
16890 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
16891 CondVT.getVectorElementType() == MVT::i1) {
16892 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16893 // lowering on AVX-512. In this case we convert it to
16894 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16895 // The same situation for all 128 and 256-bit vectors of i8 and i16
16896 EVT OpVT = LHS.getValueType();
16897 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16898 (OpVT.getVectorElementType() == MVT::i8 ||
16899 OpVT.getVectorElementType() == MVT::i16)) {
16900 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16901 DCI.AddToWorklist(Cond.getNode());
16902 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16905 // If this is a select between two integer constants, try to do some
16907 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16908 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16909 // Don't do this for crazy integer types.
16910 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16911 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16912 // so that TrueC (the true value) is larger than FalseC.
16913 bool NeedsCondInvert = false;
16915 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16916 // Efficiently invertible.
16917 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16918 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16919 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16920 NeedsCondInvert = true;
16921 std::swap(TrueC, FalseC);
16924 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16925 if (FalseC->getAPIntValue() == 0 &&
16926 TrueC->getAPIntValue().isPowerOf2()) {
16927 if (NeedsCondInvert) // Invert the condition if needed.
16928 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16929 DAG.getConstant(1, Cond.getValueType()));
16931 // Zero extend the condition if needed.
16932 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16934 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16935 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16936 DAG.getConstant(ShAmt, MVT::i8));
16939 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16940 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16941 if (NeedsCondInvert) // Invert the condition if needed.
16942 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16943 DAG.getConstant(1, Cond.getValueType()));
16945 // Zero extend the condition if needed.
16946 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16947 FalseC->getValueType(0), Cond);
16948 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16949 SDValue(FalseC, 0));
16952 // Optimize cases that will turn into an LEA instruction. This requires
16953 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16954 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16955 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16956 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16958 bool isFastMultiplier = false;
16960 switch ((unsigned char)Diff) {
16962 case 1: // result = add base, cond
16963 case 2: // result = lea base( , cond*2)
16964 case 3: // result = lea base(cond, cond*2)
16965 case 4: // result = lea base( , cond*4)
16966 case 5: // result = lea base(cond, cond*4)
16967 case 8: // result = lea base( , cond*8)
16968 case 9: // result = lea base(cond, cond*8)
16969 isFastMultiplier = true;
16974 if (isFastMultiplier) {
16975 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16976 if (NeedsCondInvert) // Invert the condition if needed.
16977 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16978 DAG.getConstant(1, Cond.getValueType()));
16980 // Zero extend the condition if needed.
16981 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16983 // Scale the condition by the difference.
16985 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16986 DAG.getConstant(Diff, Cond.getValueType()));
16988 // Add the base if non-zero.
16989 if (FalseC->getAPIntValue() != 0)
16990 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16991 SDValue(FalseC, 0));
16998 // Canonicalize max and min:
16999 // (x > y) ? x : y -> (x >= y) ? x : y
17000 // (x < y) ? x : y -> (x <= y) ? x : y
17001 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
17002 // the need for an extra compare
17003 // against zero. e.g.
17004 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
17006 // testl %edi, %edi
17008 // cmovgl %edi, %eax
17012 // cmovsl %eax, %edi
17013 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
17014 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17015 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17016 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17021 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
17022 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
17023 Cond.getOperand(0), Cond.getOperand(1), NewCC);
17024 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
17029 // Early exit check
17030 if (!TLI.isTypeLegal(VT))
17033 // Match VSELECTs into subs with unsigned saturation.
17034 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17035 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
17036 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
17037 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
17038 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17040 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
17041 // left side invert the predicate to simplify logic below.
17043 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
17045 CC = ISD::getSetCCInverse(CC, true);
17046 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
17050 if (Other.getNode() && Other->getNumOperands() == 2 &&
17051 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
17052 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
17053 SDValue CondRHS = Cond->getOperand(1);
17055 // Look for a general sub with unsigned saturation first.
17056 // x >= y ? x-y : 0 --> subus x, y
17057 // x > y ? x-y : 0 --> subus x, y
17058 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
17059 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
17060 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17062 // If the RHS is a constant we have to reverse the const canonicalization.
17063 // x > C-1 ? x+-C : 0 --> subus x, C
17064 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
17065 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
17066 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17067 if (CondRHS.getConstantOperandVal(0) == -A-1)
17068 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
17069 DAG.getConstant(-A, VT));
17072 // Another special case: If C was a sign bit, the sub has been
17073 // canonicalized into a xor.
17074 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
17075 // it's safe to decanonicalize the xor?
17076 // x s< 0 ? x^C : 0 --> subus x, C
17077 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
17078 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
17079 isSplatVector(OpRHS.getNode())) {
17080 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17082 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17087 // Try to match a min/max vector operation.
17088 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17089 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17090 unsigned Opc = ret.first;
17091 bool NeedSplit = ret.second;
17093 if (Opc && NeedSplit) {
17094 unsigned NumElems = VT.getVectorNumElements();
17095 // Extract the LHS vectors
17096 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17097 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17099 // Extract the RHS vectors
17100 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17101 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17103 // Create min/max for each subvector
17104 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17105 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17107 // Merge the result
17108 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17110 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17113 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17114 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17115 // Check if SETCC has already been promoted
17116 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17117 // Check that condition value type matches vselect operand type
17120 assert(Cond.getValueType().isVector() &&
17121 "vector select expects a vector selector!");
17123 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17124 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17126 if (!TValIsAllOnes && !FValIsAllZeros) {
17127 // Try invert the condition if true value is not all 1s and false value
17129 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17130 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17132 if (TValIsAllZeros || FValIsAllOnes) {
17133 SDValue CC = Cond.getOperand(2);
17134 ISD::CondCode NewCC =
17135 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17136 Cond.getOperand(0).getValueType().isInteger());
17137 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17138 std::swap(LHS, RHS);
17139 TValIsAllOnes = FValIsAllOnes;
17140 FValIsAllZeros = TValIsAllZeros;
17144 if (TValIsAllOnes || FValIsAllZeros) {
17147 if (TValIsAllOnes && FValIsAllZeros)
17149 else if (TValIsAllOnes)
17150 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17151 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17152 else if (FValIsAllZeros)
17153 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17154 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17156 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17160 // If we know that this node is legal then we know that it is going to be
17161 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17162 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17163 // to simplify previous instructions.
17164 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17165 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17166 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17168 // Don't optimize vector selects that map to mask-registers.
17172 // Check all uses of that condition operand to check whether it will be
17173 // consumed by non-BLEND instructions, which may depend on all bits are set
17175 for (SDNode::use_iterator I = Cond->use_begin(),
17176 E = Cond->use_end(); I != E; ++I)
17177 if (I->getOpcode() != ISD::VSELECT)
17178 // TODO: Add other opcodes eventually lowered into BLEND.
17181 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17182 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17184 APInt KnownZero, KnownOne;
17185 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17186 DCI.isBeforeLegalizeOps());
17187 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17188 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17189 DCI.CommitTargetLoweringOpt(TLO);
17195 // Check whether a boolean test is testing a boolean value generated by
17196 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17199 // Simplify the following patterns:
17200 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17201 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17202 // to (Op EFLAGS Cond)
17204 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17205 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17206 // to (Op EFLAGS !Cond)
17208 // where Op could be BRCOND or CMOV.
17210 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17211 // Quit if not CMP and SUB with its value result used.
17212 if (Cmp.getOpcode() != X86ISD::CMP &&
17213 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17216 // Quit if not used as a boolean value.
17217 if (CC != X86::COND_E && CC != X86::COND_NE)
17220 // Check CMP operands. One of them should be 0 or 1 and the other should be
17221 // an SetCC or extended from it.
17222 SDValue Op1 = Cmp.getOperand(0);
17223 SDValue Op2 = Cmp.getOperand(1);
17226 const ConstantSDNode* C = 0;
17227 bool needOppositeCond = (CC == X86::COND_E);
17228 bool checkAgainstTrue = false; // Is it a comparison against 1?
17230 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17232 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17234 else // Quit if all operands are not constants.
17237 if (C->getZExtValue() == 1) {
17238 needOppositeCond = !needOppositeCond;
17239 checkAgainstTrue = true;
17240 } else if (C->getZExtValue() != 0)
17241 // Quit if the constant is neither 0 or 1.
17244 bool truncatedToBoolWithAnd = false;
17245 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17246 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17247 SetCC.getOpcode() == ISD::TRUNCATE ||
17248 SetCC.getOpcode() == ISD::AND) {
17249 if (SetCC.getOpcode() == ISD::AND) {
17251 ConstantSDNode *CS;
17252 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17253 CS->getZExtValue() == 1)
17255 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17256 CS->getZExtValue() == 1)
17260 SetCC = SetCC.getOperand(OpIdx);
17261 truncatedToBoolWithAnd = true;
17263 SetCC = SetCC.getOperand(0);
17266 switch (SetCC.getOpcode()) {
17267 case X86ISD::SETCC_CARRY:
17268 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17269 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17270 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17271 // truncated to i1 using 'and'.
17272 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17274 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17275 "Invalid use of SETCC_CARRY!");
17277 case X86ISD::SETCC:
17278 // Set the condition code or opposite one if necessary.
17279 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17280 if (needOppositeCond)
17281 CC = X86::GetOppositeBranchCondition(CC);
17282 return SetCC.getOperand(1);
17283 case X86ISD::CMOV: {
17284 // Check whether false/true value has canonical one, i.e. 0 or 1.
17285 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17286 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17287 // Quit if true value is not a constant.
17290 // Quit if false value is not a constant.
17292 SDValue Op = SetCC.getOperand(0);
17293 // Skip 'zext' or 'trunc' node.
17294 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17295 Op.getOpcode() == ISD::TRUNCATE)
17296 Op = Op.getOperand(0);
17297 // A special case for rdrand/rdseed, where 0 is set if false cond is
17299 if ((Op.getOpcode() != X86ISD::RDRAND &&
17300 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17303 // Quit if false value is not the constant 0 or 1.
17304 bool FValIsFalse = true;
17305 if (FVal && FVal->getZExtValue() != 0) {
17306 if (FVal->getZExtValue() != 1)
17308 // If FVal is 1, opposite cond is needed.
17309 needOppositeCond = !needOppositeCond;
17310 FValIsFalse = false;
17312 // Quit if TVal is not the constant opposite of FVal.
17313 if (FValIsFalse && TVal->getZExtValue() != 1)
17315 if (!FValIsFalse && TVal->getZExtValue() != 0)
17317 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17318 if (needOppositeCond)
17319 CC = X86::GetOppositeBranchCondition(CC);
17320 return SetCC.getOperand(3);
17327 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17328 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17329 TargetLowering::DAGCombinerInfo &DCI,
17330 const X86Subtarget *Subtarget) {
17333 // If the flag operand isn't dead, don't touch this CMOV.
17334 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17337 SDValue FalseOp = N->getOperand(0);
17338 SDValue TrueOp = N->getOperand(1);
17339 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17340 SDValue Cond = N->getOperand(3);
17342 if (CC == X86::COND_E || CC == X86::COND_NE) {
17343 switch (Cond.getOpcode()) {
17347 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17348 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17349 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17355 Flags = checkBoolTestSetCCCombine(Cond, CC);
17356 if (Flags.getNode() &&
17357 // Extra check as FCMOV only supports a subset of X86 cond.
17358 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17359 SDValue Ops[] = { FalseOp, TrueOp,
17360 DAG.getConstant(CC, MVT::i8), Flags };
17361 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17362 Ops, array_lengthof(Ops));
17365 // If this is a select between two integer constants, try to do some
17366 // optimizations. Note that the operands are ordered the opposite of SELECT
17368 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17369 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17370 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17371 // larger than FalseC (the false value).
17372 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17373 CC = X86::GetOppositeBranchCondition(CC);
17374 std::swap(TrueC, FalseC);
17375 std::swap(TrueOp, FalseOp);
17378 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17379 // This is efficient for any integer data type (including i8/i16) and
17381 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17382 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17383 DAG.getConstant(CC, MVT::i8), Cond);
17385 // Zero extend the condition if needed.
17386 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17388 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17389 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17390 DAG.getConstant(ShAmt, MVT::i8));
17391 if (N->getNumValues() == 2) // Dead flag value?
17392 return DCI.CombineTo(N, Cond, SDValue());
17396 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17397 // for any integer data type, including i8/i16.
17398 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17399 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17400 DAG.getConstant(CC, MVT::i8), Cond);
17402 // Zero extend the condition if needed.
17403 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17404 FalseC->getValueType(0), Cond);
17405 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17406 SDValue(FalseC, 0));
17408 if (N->getNumValues() == 2) // Dead flag value?
17409 return DCI.CombineTo(N, Cond, SDValue());
17413 // Optimize cases that will turn into an LEA instruction. This requires
17414 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17415 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17416 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17417 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17419 bool isFastMultiplier = false;
17421 switch ((unsigned char)Diff) {
17423 case 1: // result = add base, cond
17424 case 2: // result = lea base( , cond*2)
17425 case 3: // result = lea base(cond, cond*2)
17426 case 4: // result = lea base( , cond*4)
17427 case 5: // result = lea base(cond, cond*4)
17428 case 8: // result = lea base( , cond*8)
17429 case 9: // result = lea base(cond, cond*8)
17430 isFastMultiplier = true;
17435 if (isFastMultiplier) {
17436 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17437 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17438 DAG.getConstant(CC, MVT::i8), Cond);
17439 // Zero extend the condition if needed.
17440 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17442 // Scale the condition by the difference.
17444 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17445 DAG.getConstant(Diff, Cond.getValueType()));
17447 // Add the base if non-zero.
17448 if (FalseC->getAPIntValue() != 0)
17449 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17450 SDValue(FalseC, 0));
17451 if (N->getNumValues() == 2) // Dead flag value?
17452 return DCI.CombineTo(N, Cond, SDValue());
17459 // Handle these cases:
17460 // (select (x != c), e, c) -> select (x != c), e, x),
17461 // (select (x == c), c, e) -> select (x == c), x, e)
17462 // where the c is an integer constant, and the "select" is the combination
17463 // of CMOV and CMP.
17465 // The rationale for this change is that the conditional-move from a constant
17466 // needs two instructions, however, conditional-move from a register needs
17467 // only one instruction.
17469 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17470 // some instruction-combining opportunities. This opt needs to be
17471 // postponed as late as possible.
17473 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17474 // the DCI.xxxx conditions are provided to postpone the optimization as
17475 // late as possible.
17477 ConstantSDNode *CmpAgainst = 0;
17478 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17479 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17480 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17482 if (CC == X86::COND_NE &&
17483 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17484 CC = X86::GetOppositeBranchCondition(CC);
17485 std::swap(TrueOp, FalseOp);
17488 if (CC == X86::COND_E &&
17489 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17490 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17491 DAG.getConstant(CC, MVT::i8), Cond };
17492 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17493 array_lengthof(Ops));
17501 /// PerformMulCombine - Optimize a single multiply with constant into two
17502 /// in order to implement it with two cheaper instructions, e.g.
17503 /// LEA + SHL, LEA + LEA.
17504 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17505 TargetLowering::DAGCombinerInfo &DCI) {
17506 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17509 EVT VT = N->getValueType(0);
17510 if (VT != MVT::i64)
17513 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17516 uint64_t MulAmt = C->getZExtValue();
17517 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17520 uint64_t MulAmt1 = 0;
17521 uint64_t MulAmt2 = 0;
17522 if ((MulAmt % 9) == 0) {
17524 MulAmt2 = MulAmt / 9;
17525 } else if ((MulAmt % 5) == 0) {
17527 MulAmt2 = MulAmt / 5;
17528 } else if ((MulAmt % 3) == 0) {
17530 MulAmt2 = MulAmt / 3;
17533 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17536 if (isPowerOf2_64(MulAmt2) &&
17537 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17538 // If second multiplifer is pow2, issue it first. We want the multiply by
17539 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17541 std::swap(MulAmt1, MulAmt2);
17544 if (isPowerOf2_64(MulAmt1))
17545 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17546 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17548 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17549 DAG.getConstant(MulAmt1, VT));
17551 if (isPowerOf2_64(MulAmt2))
17552 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17553 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17555 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17556 DAG.getConstant(MulAmt2, VT));
17558 // Do not add new nodes to DAG combiner worklist.
17559 DCI.CombineTo(N, NewMul, false);
17564 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17565 SDValue N0 = N->getOperand(0);
17566 SDValue N1 = N->getOperand(1);
17567 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17568 EVT VT = N0.getValueType();
17570 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17571 // since the result of setcc_c is all zero's or all ones.
17572 if (VT.isInteger() && !VT.isVector() &&
17573 N1C && N0.getOpcode() == ISD::AND &&
17574 N0.getOperand(1).getOpcode() == ISD::Constant) {
17575 SDValue N00 = N0.getOperand(0);
17576 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17577 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17578 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17579 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17580 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17581 APInt ShAmt = N1C->getAPIntValue();
17582 Mask = Mask.shl(ShAmt);
17584 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17585 N00, DAG.getConstant(Mask, VT));
17589 // Hardware support for vector shifts is sparse which makes us scalarize the
17590 // vector operations in many cases. Also, on sandybridge ADD is faster than
17592 // (shl V, 1) -> add V,V
17593 if (isSplatVector(N1.getNode())) {
17594 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17595 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17596 // We shift all of the values by one. In many cases we do not have
17597 // hardware support for this operation. This is better expressed as an ADD
17599 if (N1C && (1 == N1C->getZExtValue())) {
17600 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17607 /// \brief Returns a vector of 0s if the node in input is a vector logical
17608 /// shift by a constant amount which is known to be bigger than or equal
17609 /// to the vector element size in bits.
17610 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17611 const X86Subtarget *Subtarget) {
17612 EVT VT = N->getValueType(0);
17614 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17615 (!Subtarget->hasInt256() ||
17616 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17619 SDValue Amt = N->getOperand(1);
17621 if (isSplatVector(Amt.getNode())) {
17622 SDValue SclrAmt = Amt->getOperand(0);
17623 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17624 APInt ShiftAmt = C->getAPIntValue();
17625 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17627 // SSE2/AVX2 logical shifts always return a vector of 0s
17628 // if the shift amount is bigger than or equal to
17629 // the element size. The constant shift amount will be
17630 // encoded as a 8-bit immediate.
17631 if (ShiftAmt.trunc(8).uge(MaxAmount))
17632 return getZeroVector(VT, Subtarget, DAG, DL);
17639 /// PerformShiftCombine - Combine shifts.
17640 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17641 TargetLowering::DAGCombinerInfo &DCI,
17642 const X86Subtarget *Subtarget) {
17643 if (N->getOpcode() == ISD::SHL) {
17644 SDValue V = PerformSHLCombine(N, DAG);
17645 if (V.getNode()) return V;
17648 if (N->getOpcode() != ISD::SRA) {
17649 // Try to fold this logical shift into a zero vector.
17650 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17651 if (V.getNode()) return V;
17657 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17658 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17659 // and friends. Likewise for OR -> CMPNEQSS.
17660 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17661 TargetLowering::DAGCombinerInfo &DCI,
17662 const X86Subtarget *Subtarget) {
17665 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17666 // we're requiring SSE2 for both.
17667 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17668 SDValue N0 = N->getOperand(0);
17669 SDValue N1 = N->getOperand(1);
17670 SDValue CMP0 = N0->getOperand(1);
17671 SDValue CMP1 = N1->getOperand(1);
17674 // The SETCCs should both refer to the same CMP.
17675 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17678 SDValue CMP00 = CMP0->getOperand(0);
17679 SDValue CMP01 = CMP0->getOperand(1);
17680 EVT VT = CMP00.getValueType();
17682 if (VT == MVT::f32 || VT == MVT::f64) {
17683 bool ExpectingFlags = false;
17684 // Check for any users that want flags:
17685 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17686 !ExpectingFlags && UI != UE; ++UI)
17687 switch (UI->getOpcode()) {
17692 ExpectingFlags = true;
17694 case ISD::CopyToReg:
17695 case ISD::SIGN_EXTEND:
17696 case ISD::ZERO_EXTEND:
17697 case ISD::ANY_EXTEND:
17701 if (!ExpectingFlags) {
17702 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17703 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17705 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17706 X86::CondCode tmp = cc0;
17711 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17712 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17713 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17714 // FIXME: need symbolic constants for these magic numbers.
17715 // See X86ATTInstPrinter.cpp:printSSECC().
17716 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17717 if (Subtarget->hasAVX512()) {
17718 // SETCC type in AVX-512 is MVT::i1
17719 assert(N->getValueType(0) == MVT::i1 && "Unexpected AND node type");
17720 return DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00, CMP01,
17721 DAG.getConstant(x86cc, MVT::i8));
17723 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL, CMP00.getValueType(), CMP00, CMP01,
17724 DAG.getConstant(x86cc, MVT::i8));
17725 MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
17726 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
17728 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
17729 DAG.getConstant(1, IntVT));
17730 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17731 return OneBitOfTruth;
17739 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17740 /// so it can be folded inside ANDNP.
17741 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17742 EVT VT = N->getValueType(0);
17744 // Match direct AllOnes for 128 and 256-bit vectors
17745 if (ISD::isBuildVectorAllOnes(N))
17748 // Look through a bit convert.
17749 if (N->getOpcode() == ISD::BITCAST)
17750 N = N->getOperand(0).getNode();
17752 // Sometimes the operand may come from a insert_subvector building a 256-bit
17754 if (VT.is256BitVector() &&
17755 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17756 SDValue V1 = N->getOperand(0);
17757 SDValue V2 = N->getOperand(1);
17759 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17760 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17761 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17762 ISD::isBuildVectorAllOnes(V2.getNode()))
17769 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17770 // register. In most cases we actually compare or select YMM-sized registers
17771 // and mixing the two types creates horrible code. This method optimizes
17772 // some of the transition sequences.
17773 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17774 TargetLowering::DAGCombinerInfo &DCI,
17775 const X86Subtarget *Subtarget) {
17776 EVT VT = N->getValueType(0);
17777 if (!VT.is256BitVector())
17780 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17781 N->getOpcode() == ISD::ZERO_EXTEND ||
17782 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17784 SDValue Narrow = N->getOperand(0);
17785 EVT NarrowVT = Narrow->getValueType(0);
17786 if (!NarrowVT.is128BitVector())
17789 if (Narrow->getOpcode() != ISD::XOR &&
17790 Narrow->getOpcode() != ISD::AND &&
17791 Narrow->getOpcode() != ISD::OR)
17794 SDValue N0 = Narrow->getOperand(0);
17795 SDValue N1 = Narrow->getOperand(1);
17798 // The Left side has to be a trunc.
17799 if (N0.getOpcode() != ISD::TRUNCATE)
17802 // The type of the truncated inputs.
17803 EVT WideVT = N0->getOperand(0)->getValueType(0);
17807 // The right side has to be a 'trunc' or a constant vector.
17808 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17809 bool RHSConst = (isSplatVector(N1.getNode()) &&
17810 isa<ConstantSDNode>(N1->getOperand(0)));
17811 if (!RHSTrunc && !RHSConst)
17814 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17816 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17819 // Set N0 and N1 to hold the inputs to the new wide operation.
17820 N0 = N0->getOperand(0);
17822 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17823 N1->getOperand(0));
17824 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17825 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17826 } else if (RHSTrunc) {
17827 N1 = N1->getOperand(0);
17830 // Generate the wide operation.
17831 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17832 unsigned Opcode = N->getOpcode();
17834 case ISD::ANY_EXTEND:
17836 case ISD::ZERO_EXTEND: {
17837 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17838 APInt Mask = APInt::getAllOnesValue(InBits);
17839 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17840 return DAG.getNode(ISD::AND, DL, VT,
17841 Op, DAG.getConstant(Mask, VT));
17843 case ISD::SIGN_EXTEND:
17844 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17845 Op, DAG.getValueType(NarrowVT));
17847 llvm_unreachable("Unexpected opcode");
17851 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17852 TargetLowering::DAGCombinerInfo &DCI,
17853 const X86Subtarget *Subtarget) {
17854 EVT VT = N->getValueType(0);
17855 if (DCI.isBeforeLegalizeOps())
17858 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17862 // Create BLSI, BLSR, and BZHI instructions
17863 // BLSI is X & (-X)
17864 // BLSR is X & (X-1)
17865 // BZHI is X & ((1 << Y) - 1)
17866 // BEXTR is ((X >> imm) & (2**size-1))
17867 if (VT == MVT::i32 || VT == MVT::i64) {
17868 SDValue N0 = N->getOperand(0);
17869 SDValue N1 = N->getOperand(1);
17872 if (Subtarget->hasBMI()) {
17873 // Check LHS for neg
17874 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17875 isZero(N0.getOperand(0)))
17876 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17878 // Check RHS for neg
17879 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17880 isZero(N1.getOperand(0)))
17881 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17883 // Check LHS for X-1
17884 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17885 isAllOnes(N0.getOperand(1)))
17886 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17888 // Check RHS for X-1
17889 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17890 isAllOnes(N1.getOperand(1)))
17891 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17894 if (Subtarget->hasBMI2()) {
17895 // Check for (and (add (shl 1, Y), -1), X)
17896 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17897 SDValue N00 = N0.getOperand(0);
17898 if (N00.getOpcode() == ISD::SHL) {
17899 SDValue N001 = N00.getOperand(1);
17900 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17901 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17902 if (C && C->getZExtValue() == 1)
17903 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17907 // Check for (and X, (add (shl 1, Y), -1))
17908 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17909 SDValue N10 = N1.getOperand(0);
17910 if (N10.getOpcode() == ISD::SHL) {
17911 SDValue N101 = N10.getOperand(1);
17912 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17913 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17914 if (C && C->getZExtValue() == 1)
17915 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17920 // Check for BEXTR.
17921 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17922 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17923 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17924 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17925 if (MaskNode && ShiftNode) {
17926 uint64_t Mask = MaskNode->getZExtValue();
17927 uint64_t Shift = ShiftNode->getZExtValue();
17928 if (isMask_64(Mask)) {
17929 uint64_t MaskSize = CountPopulation_64(Mask);
17930 if (Shift + MaskSize <= VT.getSizeInBits())
17931 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17932 DAG.getConstant(Shift | (MaskSize << 8), VT));
17940 // Want to form ANDNP nodes:
17941 // 1) In the hopes of then easily combining them with OR and AND nodes
17942 // to form PBLEND/PSIGN.
17943 // 2) To match ANDN packed intrinsics
17944 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17947 SDValue N0 = N->getOperand(0);
17948 SDValue N1 = N->getOperand(1);
17951 // Check LHS for vnot
17952 if (N0.getOpcode() == ISD::XOR &&
17953 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17954 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17955 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17957 // Check RHS for vnot
17958 if (N1.getOpcode() == ISD::XOR &&
17959 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17960 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17961 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17966 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17967 TargetLowering::DAGCombinerInfo &DCI,
17968 const X86Subtarget *Subtarget) {
17969 EVT VT = N->getValueType(0);
17970 if (DCI.isBeforeLegalizeOps())
17973 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17977 SDValue N0 = N->getOperand(0);
17978 SDValue N1 = N->getOperand(1);
17980 // look for psign/blend
17981 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17982 if (!Subtarget->hasSSSE3() ||
17983 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17986 // Canonicalize pandn to RHS
17987 if (N0.getOpcode() == X86ISD::ANDNP)
17989 // or (and (m, y), (pandn m, x))
17990 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17991 SDValue Mask = N1.getOperand(0);
17992 SDValue X = N1.getOperand(1);
17994 if (N0.getOperand(0) == Mask)
17995 Y = N0.getOperand(1);
17996 if (N0.getOperand(1) == Mask)
17997 Y = N0.getOperand(0);
17999 // Check to see if the mask appeared in both the AND and ANDNP and
18003 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
18004 // Look through mask bitcast.
18005 if (Mask.getOpcode() == ISD::BITCAST)
18006 Mask = Mask.getOperand(0);
18007 if (X.getOpcode() == ISD::BITCAST)
18008 X = X.getOperand(0);
18009 if (Y.getOpcode() == ISD::BITCAST)
18010 Y = Y.getOperand(0);
18012 EVT MaskVT = Mask.getValueType();
18014 // Validate that the Mask operand is a vector sra node.
18015 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
18016 // there is no psrai.b
18017 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
18018 unsigned SraAmt = ~0;
18019 if (Mask.getOpcode() == ISD::SRA) {
18020 SDValue Amt = Mask.getOperand(1);
18021 if (isSplatVector(Amt.getNode())) {
18022 SDValue SclrAmt = Amt->getOperand(0);
18023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
18024 SraAmt = C->getZExtValue();
18026 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
18027 SDValue SraC = Mask.getOperand(1);
18028 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
18030 if ((SraAmt + 1) != EltBits)
18035 // Now we know we at least have a plendvb with the mask val. See if
18036 // we can form a psignb/w/d.
18037 // psign = x.type == y.type == mask.type && y = sub(0, x);
18038 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
18039 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
18040 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
18041 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
18042 "Unsupported VT for PSIGN");
18043 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
18044 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18046 // PBLENDVB only available on SSE 4.1
18047 if (!Subtarget->hasSSE41())
18050 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
18052 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
18053 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
18054 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
18055 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
18056 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18060 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
18063 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
18064 MachineFunction &MF = DAG.getMachineFunction();
18065 bool OptForSize = MF.getFunction()->getAttributes().
18066 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
18068 // SHLD/SHRD instructions have lower register pressure, but on some
18069 // platforms they have higher latency than the equivalent
18070 // series of shifts/or that would otherwise be generated.
18071 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
18072 // have higher latencies and we are not optimizing for size.
18073 if (!OptForSize && Subtarget->isSHLDSlow())
18076 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
18078 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
18080 if (!N0.hasOneUse() || !N1.hasOneUse())
18083 SDValue ShAmt0 = N0.getOperand(1);
18084 if (ShAmt0.getValueType() != MVT::i8)
18086 SDValue ShAmt1 = N1.getOperand(1);
18087 if (ShAmt1.getValueType() != MVT::i8)
18089 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18090 ShAmt0 = ShAmt0.getOperand(0);
18091 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18092 ShAmt1 = ShAmt1.getOperand(0);
18095 unsigned Opc = X86ISD::SHLD;
18096 SDValue Op0 = N0.getOperand(0);
18097 SDValue Op1 = N1.getOperand(0);
18098 if (ShAmt0.getOpcode() == ISD::SUB) {
18099 Opc = X86ISD::SHRD;
18100 std::swap(Op0, Op1);
18101 std::swap(ShAmt0, ShAmt1);
18104 unsigned Bits = VT.getSizeInBits();
18105 if (ShAmt1.getOpcode() == ISD::SUB) {
18106 SDValue Sum = ShAmt1.getOperand(0);
18107 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18108 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18109 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18110 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18111 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18112 return DAG.getNode(Opc, DL, VT,
18114 DAG.getNode(ISD::TRUNCATE, DL,
18117 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18118 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18120 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18121 return DAG.getNode(Opc, DL, VT,
18122 N0.getOperand(0), N1.getOperand(0),
18123 DAG.getNode(ISD::TRUNCATE, DL,
18130 // Generate NEG and CMOV for integer abs.
18131 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18132 EVT VT = N->getValueType(0);
18134 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18135 // 8-bit integer abs to NEG and CMOV.
18136 if (VT.isInteger() && VT.getSizeInBits() == 8)
18139 SDValue N0 = N->getOperand(0);
18140 SDValue N1 = N->getOperand(1);
18143 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18144 // and change it to SUB and CMOV.
18145 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18146 N0.getOpcode() == ISD::ADD &&
18147 N0.getOperand(1) == N1 &&
18148 N1.getOpcode() == ISD::SRA &&
18149 N1.getOperand(0) == N0.getOperand(0))
18150 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18151 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18152 // Generate SUB & CMOV.
18153 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18154 DAG.getConstant(0, VT), N0.getOperand(0));
18156 SDValue Ops[] = { N0.getOperand(0), Neg,
18157 DAG.getConstant(X86::COND_GE, MVT::i8),
18158 SDValue(Neg.getNode(), 1) };
18159 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18160 Ops, array_lengthof(Ops));
18165 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18166 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18167 TargetLowering::DAGCombinerInfo &DCI,
18168 const X86Subtarget *Subtarget) {
18169 EVT VT = N->getValueType(0);
18170 if (DCI.isBeforeLegalizeOps())
18173 if (Subtarget->hasCMov()) {
18174 SDValue RV = performIntegerAbsCombine(N, DAG);
18179 // Try forming BMI if it is available.
18180 if (!Subtarget->hasBMI())
18183 if (VT != MVT::i32 && VT != MVT::i64)
18186 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
18188 // Create BLSMSK instructions by finding X ^ (X-1)
18189 SDValue N0 = N->getOperand(0);
18190 SDValue N1 = N->getOperand(1);
18193 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18194 isAllOnes(N0.getOperand(1)))
18195 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
18197 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18198 isAllOnes(N1.getOperand(1)))
18199 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
18204 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18205 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18206 TargetLowering::DAGCombinerInfo &DCI,
18207 const X86Subtarget *Subtarget) {
18208 LoadSDNode *Ld = cast<LoadSDNode>(N);
18209 EVT RegVT = Ld->getValueType(0);
18210 EVT MemVT = Ld->getMemoryVT();
18212 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18213 unsigned RegSz = RegVT.getSizeInBits();
18215 // On Sandybridge unaligned 256bit loads are inefficient.
18216 ISD::LoadExtType Ext = Ld->getExtensionType();
18217 unsigned Alignment = Ld->getAlignment();
18218 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18219 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18220 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18221 unsigned NumElems = RegVT.getVectorNumElements();
18225 SDValue Ptr = Ld->getBasePtr();
18226 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18228 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18230 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18231 Ld->getPointerInfo(), Ld->isVolatile(),
18232 Ld->isNonTemporal(), Ld->isInvariant(),
18234 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18235 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18236 Ld->getPointerInfo(), Ld->isVolatile(),
18237 Ld->isNonTemporal(), Ld->isInvariant(),
18238 std::min(16U, Alignment));
18239 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18241 Load2.getValue(1));
18243 SDValue NewVec = DAG.getUNDEF(RegVT);
18244 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18245 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18246 return DCI.CombineTo(N, NewVec, TF, true);
18249 // If this is a vector EXT Load then attempt to optimize it using a
18250 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18251 // expansion is still better than scalar code.
18252 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18253 // emit a shuffle and a arithmetic shift.
18254 // TODO: It is possible to support ZExt by zeroing the undef values
18255 // during the shuffle phase or after the shuffle.
18256 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18257 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18258 assert(MemVT != RegVT && "Cannot extend to the same type");
18259 assert(MemVT.isVector() && "Must load a vector from memory");
18261 unsigned NumElems = RegVT.getVectorNumElements();
18262 unsigned MemSz = MemVT.getSizeInBits();
18263 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18265 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18268 // All sizes must be a power of two.
18269 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18272 // Attempt to load the original value using scalar loads.
18273 // Find the largest scalar type that divides the total loaded size.
18274 MVT SclrLoadTy = MVT::i8;
18275 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18276 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18277 MVT Tp = (MVT::SimpleValueType)tp;
18278 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18283 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18284 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18286 SclrLoadTy = MVT::f64;
18288 // Calculate the number of scalar loads that we need to perform
18289 // in order to load our vector from memory.
18290 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18291 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18294 unsigned loadRegZize = RegSz;
18295 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18298 // Represent our vector as a sequence of elements which are the
18299 // largest scalar that we can load.
18300 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18301 loadRegZize/SclrLoadTy.getSizeInBits());
18303 // Represent the data using the same element type that is stored in
18304 // memory. In practice, we ''widen'' MemVT.
18306 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18307 loadRegZize/MemVT.getScalarType().getSizeInBits());
18309 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18310 "Invalid vector type");
18312 // We can't shuffle using an illegal type.
18313 if (!TLI.isTypeLegal(WideVecVT))
18316 SmallVector<SDValue, 8> Chains;
18317 SDValue Ptr = Ld->getBasePtr();
18318 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18319 TLI.getPointerTy());
18320 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18322 for (unsigned i = 0; i < NumLoads; ++i) {
18323 // Perform a single load.
18324 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18325 Ptr, Ld->getPointerInfo(),
18326 Ld->isVolatile(), Ld->isNonTemporal(),
18327 Ld->isInvariant(), Ld->getAlignment());
18328 Chains.push_back(ScalarLoad.getValue(1));
18329 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18330 // another round of DAGCombining.
18332 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18334 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18335 ScalarLoad, DAG.getIntPtrConstant(i));
18337 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18340 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18343 // Bitcast the loaded value to a vector of the original element type, in
18344 // the size of the target vector type.
18345 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18346 unsigned SizeRatio = RegSz/MemSz;
18348 if (Ext == ISD::SEXTLOAD) {
18349 // If we have SSE4.1 we can directly emit a VSEXT node.
18350 if (Subtarget->hasSSE41()) {
18351 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18352 return DCI.CombineTo(N, Sext, TF, true);
18355 // Otherwise we'll shuffle the small elements in the high bits of the
18356 // larger type and perform an arithmetic shift. If the shift is not legal
18357 // it's better to scalarize.
18358 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18361 // Redistribute the loaded elements into the different locations.
18362 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18363 for (unsigned i = 0; i != NumElems; ++i)
18364 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18366 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18367 DAG.getUNDEF(WideVecVT),
18370 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18372 // Build the arithmetic shift.
18373 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18374 MemVT.getVectorElementType().getSizeInBits();
18375 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18376 DAG.getConstant(Amt, RegVT));
18378 return DCI.CombineTo(N, Shuff, TF, true);
18381 // Redistribute the loaded elements into the different locations.
18382 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18383 for (unsigned i = 0; i != NumElems; ++i)
18384 ShuffleVec[i*SizeRatio] = i;
18386 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18387 DAG.getUNDEF(WideVecVT),
18390 // Bitcast to the requested type.
18391 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18392 // Replace the original load with the new sequence
18393 // and return the new chain.
18394 return DCI.CombineTo(N, Shuff, TF, true);
18400 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18401 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18402 const X86Subtarget *Subtarget) {
18403 StoreSDNode *St = cast<StoreSDNode>(N);
18404 EVT VT = St->getValue().getValueType();
18405 EVT StVT = St->getMemoryVT();
18407 SDValue StoredVal = St->getOperand(1);
18408 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18410 // If we are saving a concatenation of two XMM registers, perform two stores.
18411 // On Sandy Bridge, 256-bit memory operations are executed by two
18412 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18413 // memory operation.
18414 unsigned Alignment = St->getAlignment();
18415 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18416 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18417 StVT == VT && !IsAligned) {
18418 unsigned NumElems = VT.getVectorNumElements();
18422 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18423 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18425 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18426 SDValue Ptr0 = St->getBasePtr();
18427 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18429 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18430 St->getPointerInfo(), St->isVolatile(),
18431 St->isNonTemporal(), Alignment);
18432 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18433 St->getPointerInfo(), St->isVolatile(),
18434 St->isNonTemporal(),
18435 std::min(16U, Alignment));
18436 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18439 // Optimize trunc store (of multiple scalars) to shuffle and store.
18440 // First, pack all of the elements in one place. Next, store to memory
18441 // in fewer chunks.
18442 if (St->isTruncatingStore() && VT.isVector()) {
18443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18444 unsigned NumElems = VT.getVectorNumElements();
18445 assert(StVT != VT && "Cannot truncate to the same type");
18446 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18447 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18449 // From, To sizes and ElemCount must be pow of two
18450 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18451 // We are going to use the original vector elt for storing.
18452 // Accumulated smaller vector elements must be a multiple of the store size.
18453 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18455 unsigned SizeRatio = FromSz / ToSz;
18457 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18459 // Create a type on which we perform the shuffle
18460 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18461 StVT.getScalarType(), NumElems*SizeRatio);
18463 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18465 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18466 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18467 for (unsigned i = 0; i != NumElems; ++i)
18468 ShuffleVec[i] = i * SizeRatio;
18470 // Can't shuffle using an illegal type.
18471 if (!TLI.isTypeLegal(WideVecVT))
18474 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18475 DAG.getUNDEF(WideVecVT),
18477 // At this point all of the data is stored at the bottom of the
18478 // register. We now need to save it to mem.
18480 // Find the largest store unit
18481 MVT StoreType = MVT::i8;
18482 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18483 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18484 MVT Tp = (MVT::SimpleValueType)tp;
18485 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18489 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18490 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18491 (64 <= NumElems * ToSz))
18492 StoreType = MVT::f64;
18494 // Bitcast the original vector into a vector of store-size units
18495 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18496 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18497 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18498 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18499 SmallVector<SDValue, 8> Chains;
18500 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18501 TLI.getPointerTy());
18502 SDValue Ptr = St->getBasePtr();
18504 // Perform one or more big stores into memory.
18505 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18506 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18507 StoreType, ShuffWide,
18508 DAG.getIntPtrConstant(i));
18509 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18510 St->getPointerInfo(), St->isVolatile(),
18511 St->isNonTemporal(), St->getAlignment());
18512 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18513 Chains.push_back(Ch);
18516 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18520 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18521 // the FP state in cases where an emms may be missing.
18522 // A preferable solution to the general problem is to figure out the right
18523 // places to insert EMMS. This qualifies as a quick hack.
18525 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18526 if (VT.getSizeInBits() != 64)
18529 const Function *F = DAG.getMachineFunction().getFunction();
18530 bool NoImplicitFloatOps = F->getAttributes().
18531 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18532 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18533 && Subtarget->hasSSE2();
18534 if ((VT.isVector() ||
18535 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18536 isa<LoadSDNode>(St->getValue()) &&
18537 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18538 St->getChain().hasOneUse() && !St->isVolatile()) {
18539 SDNode* LdVal = St->getValue().getNode();
18540 LoadSDNode *Ld = 0;
18541 int TokenFactorIndex = -1;
18542 SmallVector<SDValue, 8> Ops;
18543 SDNode* ChainVal = St->getChain().getNode();
18544 // Must be a store of a load. We currently handle two cases: the load
18545 // is a direct child, and it's under an intervening TokenFactor. It is
18546 // possible to dig deeper under nested TokenFactors.
18547 if (ChainVal == LdVal)
18548 Ld = cast<LoadSDNode>(St->getChain());
18549 else if (St->getValue().hasOneUse() &&
18550 ChainVal->getOpcode() == ISD::TokenFactor) {
18551 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18552 if (ChainVal->getOperand(i).getNode() == LdVal) {
18553 TokenFactorIndex = i;
18554 Ld = cast<LoadSDNode>(St->getValue());
18556 Ops.push_back(ChainVal->getOperand(i));
18560 if (!Ld || !ISD::isNormalLoad(Ld))
18563 // If this is not the MMX case, i.e. we are just turning i64 load/store
18564 // into f64 load/store, avoid the transformation if there are multiple
18565 // uses of the loaded value.
18566 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18571 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18572 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18574 if (Subtarget->is64Bit() || F64IsLegal) {
18575 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18576 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18577 Ld->getPointerInfo(), Ld->isVolatile(),
18578 Ld->isNonTemporal(), Ld->isInvariant(),
18579 Ld->getAlignment());
18580 SDValue NewChain = NewLd.getValue(1);
18581 if (TokenFactorIndex != -1) {
18582 Ops.push_back(NewChain);
18583 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18586 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18587 St->getPointerInfo(),
18588 St->isVolatile(), St->isNonTemporal(),
18589 St->getAlignment());
18592 // Otherwise, lower to two pairs of 32-bit loads / stores.
18593 SDValue LoAddr = Ld->getBasePtr();
18594 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18595 DAG.getConstant(4, MVT::i32));
18597 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18598 Ld->getPointerInfo(),
18599 Ld->isVolatile(), Ld->isNonTemporal(),
18600 Ld->isInvariant(), Ld->getAlignment());
18601 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18602 Ld->getPointerInfo().getWithOffset(4),
18603 Ld->isVolatile(), Ld->isNonTemporal(),
18605 MinAlign(Ld->getAlignment(), 4));
18607 SDValue NewChain = LoLd.getValue(1);
18608 if (TokenFactorIndex != -1) {
18609 Ops.push_back(LoLd);
18610 Ops.push_back(HiLd);
18611 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18615 LoAddr = St->getBasePtr();
18616 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18617 DAG.getConstant(4, MVT::i32));
18619 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18620 St->getPointerInfo(),
18621 St->isVolatile(), St->isNonTemporal(),
18622 St->getAlignment());
18623 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18624 St->getPointerInfo().getWithOffset(4),
18626 St->isNonTemporal(),
18627 MinAlign(St->getAlignment(), 4));
18628 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18633 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18634 /// and return the operands for the horizontal operation in LHS and RHS. A
18635 /// horizontal operation performs the binary operation on successive elements
18636 /// of its first operand, then on successive elements of its second operand,
18637 /// returning the resulting values in a vector. For example, if
18638 /// A = < float a0, float a1, float a2, float a3 >
18640 /// B = < float b0, float b1, float b2, float b3 >
18641 /// then the result of doing a horizontal operation on A and B is
18642 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18643 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18644 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18645 /// set to A, RHS to B, and the routine returns 'true'.
18646 /// Note that the binary operation should have the property that if one of the
18647 /// operands is UNDEF then the result is UNDEF.
18648 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18649 // Look for the following pattern: if
18650 // A = < float a0, float a1, float a2, float a3 >
18651 // B = < float b0, float b1, float b2, float b3 >
18653 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18654 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18655 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18656 // which is A horizontal-op B.
18658 // At least one of the operands should be a vector shuffle.
18659 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18660 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18663 MVT VT = LHS.getSimpleValueType();
18665 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18666 "Unsupported vector type for horizontal add/sub");
18668 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18669 // operate independently on 128-bit lanes.
18670 unsigned NumElts = VT.getVectorNumElements();
18671 unsigned NumLanes = VT.getSizeInBits()/128;
18672 unsigned NumLaneElts = NumElts / NumLanes;
18673 assert((NumLaneElts % 2 == 0) &&
18674 "Vector type should have an even number of elements in each lane");
18675 unsigned HalfLaneElts = NumLaneElts/2;
18677 // View LHS in the form
18678 // LHS = VECTOR_SHUFFLE A, B, LMask
18679 // If LHS is not a shuffle then pretend it is the shuffle
18680 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18681 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18684 SmallVector<int, 16> LMask(NumElts);
18685 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18686 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18687 A = LHS.getOperand(0);
18688 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18689 B = LHS.getOperand(1);
18690 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18691 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18693 if (LHS.getOpcode() != ISD::UNDEF)
18695 for (unsigned i = 0; i != NumElts; ++i)
18699 // Likewise, view RHS in the form
18700 // RHS = VECTOR_SHUFFLE C, D, RMask
18702 SmallVector<int, 16> RMask(NumElts);
18703 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18704 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18705 C = RHS.getOperand(0);
18706 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18707 D = RHS.getOperand(1);
18708 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18709 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18711 if (RHS.getOpcode() != ISD::UNDEF)
18713 for (unsigned i = 0; i != NumElts; ++i)
18717 // Check that the shuffles are both shuffling the same vectors.
18718 if (!(A == C && B == D) && !(A == D && B == C))
18721 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18722 if (!A.getNode() && !B.getNode())
18725 // If A and B occur in reverse order in RHS, then "swap" them (which means
18726 // rewriting the mask).
18728 CommuteVectorShuffleMask(RMask, NumElts);
18730 // At this point LHS and RHS are equivalent to
18731 // LHS = VECTOR_SHUFFLE A, B, LMask
18732 // RHS = VECTOR_SHUFFLE A, B, RMask
18733 // Check that the masks correspond to performing a horizontal operation.
18734 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18735 for (unsigned i = 0; i != NumLaneElts; ++i) {
18736 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18738 // Ignore any UNDEF components.
18739 if (LIdx < 0 || RIdx < 0 ||
18740 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18741 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18744 // Check that successive elements are being operated on. If not, this is
18745 // not a horizontal operation.
18746 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18747 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18748 if (!(LIdx == Index && RIdx == Index + 1) &&
18749 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18754 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18755 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18759 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18760 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18761 const X86Subtarget *Subtarget) {
18762 EVT VT = N->getValueType(0);
18763 SDValue LHS = N->getOperand(0);
18764 SDValue RHS = N->getOperand(1);
18766 // Try to synthesize horizontal adds from adds of shuffles.
18767 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18768 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18769 isHorizontalBinOp(LHS, RHS, true))
18770 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18774 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18775 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18776 const X86Subtarget *Subtarget) {
18777 EVT VT = N->getValueType(0);
18778 SDValue LHS = N->getOperand(0);
18779 SDValue RHS = N->getOperand(1);
18781 // Try to synthesize horizontal subs from subs of shuffles.
18782 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18783 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18784 isHorizontalBinOp(LHS, RHS, false))
18785 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18789 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18790 /// X86ISD::FXOR nodes.
18791 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18792 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18793 // F[X]OR(0.0, x) -> x
18794 // F[X]OR(x, 0.0) -> x
18795 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18796 if (C->getValueAPF().isPosZero())
18797 return N->getOperand(1);
18798 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18799 if (C->getValueAPF().isPosZero())
18800 return N->getOperand(0);
18804 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18805 /// X86ISD::FMAX nodes.
18806 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18807 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18809 // Only perform optimizations if UnsafeMath is used.
18810 if (!DAG.getTarget().Options.UnsafeFPMath)
18813 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18814 // into FMINC and FMAXC, which are Commutative operations.
18815 unsigned NewOp = 0;
18816 switch (N->getOpcode()) {
18817 default: llvm_unreachable("unknown opcode");
18818 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18819 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18822 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18823 N->getOperand(0), N->getOperand(1));
18826 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18827 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18828 // FAND(0.0, x) -> 0.0
18829 // FAND(x, 0.0) -> 0.0
18830 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18831 if (C->getValueAPF().isPosZero())
18832 return N->getOperand(0);
18833 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18834 if (C->getValueAPF().isPosZero())
18835 return N->getOperand(1);
18839 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18840 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18841 // FANDN(x, 0.0) -> 0.0
18842 // FANDN(0.0, x) -> x
18843 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18844 if (C->getValueAPF().isPosZero())
18845 return N->getOperand(1);
18846 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18847 if (C->getValueAPF().isPosZero())
18848 return N->getOperand(1);
18852 static SDValue PerformBTCombine(SDNode *N,
18854 TargetLowering::DAGCombinerInfo &DCI) {
18855 // BT ignores high bits in the bit index operand.
18856 SDValue Op1 = N->getOperand(1);
18857 if (Op1.hasOneUse()) {
18858 unsigned BitWidth = Op1.getValueSizeInBits();
18859 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18860 APInt KnownZero, KnownOne;
18861 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18862 !DCI.isBeforeLegalizeOps());
18863 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18864 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18865 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18866 DCI.CommitTargetLoweringOpt(TLO);
18871 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18872 SDValue Op = N->getOperand(0);
18873 if (Op.getOpcode() == ISD::BITCAST)
18874 Op = Op.getOperand(0);
18875 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18876 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18877 VT.getVectorElementType().getSizeInBits() ==
18878 OpVT.getVectorElementType().getSizeInBits()) {
18879 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18884 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18885 const X86Subtarget *Subtarget) {
18886 EVT VT = N->getValueType(0);
18887 if (!VT.isVector())
18890 SDValue N0 = N->getOperand(0);
18891 SDValue N1 = N->getOperand(1);
18892 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18895 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18896 // both SSE and AVX2 since there is no sign-extended shift right
18897 // operation on a vector with 64-bit elements.
18898 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18899 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18900 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18901 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18902 SDValue N00 = N0.getOperand(0);
18904 // EXTLOAD has a better solution on AVX2,
18905 // it may be replaced with X86ISD::VSEXT node.
18906 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18907 if (!ISD::isNormalLoad(N00.getNode()))
18910 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18911 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18913 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18919 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18920 TargetLowering::DAGCombinerInfo &DCI,
18921 const X86Subtarget *Subtarget) {
18922 if (!DCI.isBeforeLegalizeOps())
18925 if (!Subtarget->hasFp256())
18928 EVT VT = N->getValueType(0);
18929 if (VT.isVector() && VT.getSizeInBits() == 256) {
18930 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18938 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18939 const X86Subtarget* Subtarget) {
18941 EVT VT = N->getValueType(0);
18943 // Let legalize expand this if it isn't a legal type yet.
18944 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18947 EVT ScalarVT = VT.getScalarType();
18948 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18949 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18952 SDValue A = N->getOperand(0);
18953 SDValue B = N->getOperand(1);
18954 SDValue C = N->getOperand(2);
18956 bool NegA = (A.getOpcode() == ISD::FNEG);
18957 bool NegB = (B.getOpcode() == ISD::FNEG);
18958 bool NegC = (C.getOpcode() == ISD::FNEG);
18960 // Negative multiplication when NegA xor NegB
18961 bool NegMul = (NegA != NegB);
18963 A = A.getOperand(0);
18965 B = B.getOperand(0);
18967 C = C.getOperand(0);
18971 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18973 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18975 return DAG.getNode(Opcode, dl, VT, A, B, C);
18978 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18979 TargetLowering::DAGCombinerInfo &DCI,
18980 const X86Subtarget *Subtarget) {
18981 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18982 // (and (i32 x86isd::setcc_carry), 1)
18983 // This eliminates the zext. This transformation is necessary because
18984 // ISD::SETCC is always legalized to i8.
18986 SDValue N0 = N->getOperand(0);
18987 EVT VT = N->getValueType(0);
18989 if (N0.getOpcode() == ISD::AND &&
18991 N0.getOperand(0).hasOneUse()) {
18992 SDValue N00 = N0.getOperand(0);
18993 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18994 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18995 if (!C || C->getZExtValue() != 1)
18997 return DAG.getNode(ISD::AND, dl, VT,
18998 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18999 N00.getOperand(0), N00.getOperand(1)),
19000 DAG.getConstant(1, VT));
19004 if (N0.getOpcode() == ISD::TRUNCATE &&
19006 N0.getOperand(0).hasOneUse()) {
19007 SDValue N00 = N0.getOperand(0);
19008 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19009 return DAG.getNode(ISD::AND, dl, VT,
19010 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19011 N00.getOperand(0), N00.getOperand(1)),
19012 DAG.getConstant(1, VT));
19015 if (VT.is256BitVector()) {
19016 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19024 // Optimize x == -y --> x+y == 0
19025 // x != -y --> x+y != 0
19026 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
19027 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
19028 SDValue LHS = N->getOperand(0);
19029 SDValue RHS = N->getOperand(1);
19031 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
19032 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
19033 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
19034 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19035 LHS.getValueType(), RHS, LHS.getOperand(1));
19036 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19037 addV, DAG.getConstant(0, addV.getValueType()), CC);
19039 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
19040 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
19041 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
19042 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19043 RHS.getValueType(), LHS, RHS.getOperand(1));
19044 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19045 addV, DAG.getConstant(0, addV.getValueType()), CC);
19050 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
19051 // as "sbb reg,reg", since it can be extended without zext and produces
19052 // an all-ones bit which is more useful than 0/1 in some cases.
19053 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
19056 return DAG.getNode(ISD::AND, DL, VT,
19057 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19058 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
19059 DAG.getConstant(1, VT));
19060 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
19061 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
19062 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19063 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
19066 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
19067 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
19068 TargetLowering::DAGCombinerInfo &DCI,
19069 const X86Subtarget *Subtarget) {
19071 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
19072 SDValue EFLAGS = N->getOperand(1);
19074 if (CC == X86::COND_A) {
19075 // Try to convert COND_A into COND_B in an attempt to facilitate
19076 // materializing "setb reg".
19078 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
19079 // cannot take an immediate as its first operand.
19081 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
19082 EFLAGS.getValueType().isInteger() &&
19083 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
19084 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
19085 EFLAGS.getNode()->getVTList(),
19086 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
19087 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
19088 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
19092 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
19093 // a zext and produces an all-ones bit which is more useful than 0/1 in some
19095 if (CC == X86::COND_B)
19096 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
19100 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19101 if (Flags.getNode()) {
19102 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19103 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19109 // Optimize branch condition evaluation.
19111 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19112 TargetLowering::DAGCombinerInfo &DCI,
19113 const X86Subtarget *Subtarget) {
19115 SDValue Chain = N->getOperand(0);
19116 SDValue Dest = N->getOperand(1);
19117 SDValue EFLAGS = N->getOperand(3);
19118 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19122 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19123 if (Flags.getNode()) {
19124 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19125 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19132 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19133 const X86TargetLowering *XTLI) {
19134 SDValue Op0 = N->getOperand(0);
19135 EVT InVT = Op0->getValueType(0);
19137 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19138 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19140 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19141 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19142 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19145 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19146 // a 32-bit target where SSE doesn't support i64->FP operations.
19147 if (Op0.getOpcode() == ISD::LOAD) {
19148 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19149 EVT VT = Ld->getValueType(0);
19150 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19151 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19152 !XTLI->getSubtarget()->is64Bit() &&
19154 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19155 Ld->getChain(), Op0, DAG);
19156 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19163 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19164 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19165 X86TargetLowering::DAGCombinerInfo &DCI) {
19166 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19167 // the result is either zero or one (depending on the input carry bit).
19168 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19169 if (X86::isZeroNode(N->getOperand(0)) &&
19170 X86::isZeroNode(N->getOperand(1)) &&
19171 // We don't have a good way to replace an EFLAGS use, so only do this when
19173 SDValue(N, 1).use_empty()) {
19175 EVT VT = N->getValueType(0);
19176 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19177 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19178 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19179 DAG.getConstant(X86::COND_B,MVT::i8),
19181 DAG.getConstant(1, VT));
19182 return DCI.CombineTo(N, Res1, CarryOut);
19188 // fold (add Y, (sete X, 0)) -> adc 0, Y
19189 // (add Y, (setne X, 0)) -> sbb -1, Y
19190 // (sub (sete X, 0), Y) -> sbb 0, Y
19191 // (sub (setne X, 0), Y) -> adc -1, Y
19192 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19195 // Look through ZExts.
19196 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19197 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19200 SDValue SetCC = Ext.getOperand(0);
19201 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19204 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19205 if (CC != X86::COND_E && CC != X86::COND_NE)
19208 SDValue Cmp = SetCC.getOperand(1);
19209 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19210 !X86::isZeroNode(Cmp.getOperand(1)) ||
19211 !Cmp.getOperand(0).getValueType().isInteger())
19214 SDValue CmpOp0 = Cmp.getOperand(0);
19215 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19216 DAG.getConstant(1, CmpOp0.getValueType()));
19218 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19219 if (CC == X86::COND_NE)
19220 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19221 DL, OtherVal.getValueType(), OtherVal,
19222 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19223 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19224 DL, OtherVal.getValueType(), OtherVal,
19225 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19228 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19229 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19230 const X86Subtarget *Subtarget) {
19231 EVT VT = N->getValueType(0);
19232 SDValue Op0 = N->getOperand(0);
19233 SDValue Op1 = N->getOperand(1);
19235 // Try to synthesize horizontal adds from adds of shuffles.
19236 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19237 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19238 isHorizontalBinOp(Op0, Op1, true))
19239 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19241 return OptimizeConditionalInDecrement(N, DAG);
19244 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19245 const X86Subtarget *Subtarget) {
19246 SDValue Op0 = N->getOperand(0);
19247 SDValue Op1 = N->getOperand(1);
19249 // X86 can't encode an immediate LHS of a sub. See if we can push the
19250 // negation into a preceding instruction.
19251 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19252 // If the RHS of the sub is a XOR with one use and a constant, invert the
19253 // immediate. Then add one to the LHS of the sub so we can turn
19254 // X-Y -> X+~Y+1, saving one register.
19255 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19256 isa<ConstantSDNode>(Op1.getOperand(1))) {
19257 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19258 EVT VT = Op0.getValueType();
19259 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19261 DAG.getConstant(~XorC, VT));
19262 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19263 DAG.getConstant(C->getAPIntValue()+1, VT));
19267 // Try to synthesize horizontal adds from adds of shuffles.
19268 EVT VT = N->getValueType(0);
19269 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19270 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19271 isHorizontalBinOp(Op0, Op1, true))
19272 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19274 return OptimizeConditionalInDecrement(N, DAG);
19277 /// performVZEXTCombine - Performs build vector combines
19278 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19279 TargetLowering::DAGCombinerInfo &DCI,
19280 const X86Subtarget *Subtarget) {
19281 // (vzext (bitcast (vzext (x)) -> (vzext x)
19282 SDValue In = N->getOperand(0);
19283 while (In.getOpcode() == ISD::BITCAST)
19284 In = In.getOperand(0);
19286 if (In.getOpcode() != X86ISD::VZEXT)
19289 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19293 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19294 DAGCombinerInfo &DCI) const {
19295 SelectionDAG &DAG = DCI.DAG;
19296 switch (N->getOpcode()) {
19298 case ISD::EXTRACT_VECTOR_ELT:
19299 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19301 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19302 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19303 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19304 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19305 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19306 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19309 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19310 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19311 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19312 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19313 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19314 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19315 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19316 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19317 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19319 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19321 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19322 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19323 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19324 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19325 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19326 case ISD::ANY_EXTEND:
19327 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19328 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19329 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19330 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19331 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19332 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19333 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19334 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19335 case X86ISD::SHUFP: // Handle all target specific shuffles
19336 case X86ISD::PALIGNR:
19337 case X86ISD::UNPCKH:
19338 case X86ISD::UNPCKL:
19339 case X86ISD::MOVHLPS:
19340 case X86ISD::MOVLHPS:
19341 case X86ISD::PSHUFD:
19342 case X86ISD::PSHUFHW:
19343 case X86ISD::PSHUFLW:
19344 case X86ISD::MOVSS:
19345 case X86ISD::MOVSD:
19346 case X86ISD::VPERMILP:
19347 case X86ISD::VPERM2X128:
19348 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19349 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19355 /// isTypeDesirableForOp - Return true if the target has native support for
19356 /// the specified value type and it is 'desirable' to use the type for the
19357 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19358 /// instruction encodings are longer and some i16 instructions are slow.
19359 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19360 if (!isTypeLegal(VT))
19362 if (VT != MVT::i16)
19369 case ISD::SIGN_EXTEND:
19370 case ISD::ZERO_EXTEND:
19371 case ISD::ANY_EXTEND:
19384 /// IsDesirableToPromoteOp - This method query the target whether it is
19385 /// beneficial for dag combiner to promote the specified node. If true, it
19386 /// should return the desired promotion type by reference.
19387 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19388 EVT VT = Op.getValueType();
19389 if (VT != MVT::i16)
19392 bool Promote = false;
19393 bool Commute = false;
19394 switch (Op.getOpcode()) {
19397 LoadSDNode *LD = cast<LoadSDNode>(Op);
19398 // If the non-extending load has a single use and it's not live out, then it
19399 // might be folded.
19400 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19401 Op.hasOneUse()*/) {
19402 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19403 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19404 // The only case where we'd want to promote LOAD (rather then it being
19405 // promoted as an operand is when it's only use is liveout.
19406 if (UI->getOpcode() != ISD::CopyToReg)
19413 case ISD::SIGN_EXTEND:
19414 case ISD::ZERO_EXTEND:
19415 case ISD::ANY_EXTEND:
19420 SDValue N0 = Op.getOperand(0);
19421 // Look out for (store (shl (load), x)).
19422 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19435 SDValue N0 = Op.getOperand(0);
19436 SDValue N1 = Op.getOperand(1);
19437 if (!Commute && MayFoldLoad(N1))
19439 // Avoid disabling potential load folding opportunities.
19440 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19442 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19452 //===----------------------------------------------------------------------===//
19453 // X86 Inline Assembly Support
19454 //===----------------------------------------------------------------------===//
19457 // Helper to match a string separated by whitespace.
19458 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19459 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19461 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19462 StringRef piece(*args[i]);
19463 if (!s.startswith(piece)) // Check if the piece matches.
19466 s = s.substr(piece.size());
19467 StringRef::size_type pos = s.find_first_not_of(" \t");
19468 if (pos == 0) // We matched a prefix.
19476 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19479 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19481 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19482 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19483 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19484 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19486 if (AsmPieces.size() == 3)
19488 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19495 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19496 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19498 std::string AsmStr = IA->getAsmString();
19500 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19501 if (!Ty || Ty->getBitWidth() % 16 != 0)
19504 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19505 SmallVector<StringRef, 4> AsmPieces;
19506 SplitString(AsmStr, AsmPieces, ";\n");
19508 switch (AsmPieces.size()) {
19509 default: return false;
19511 // FIXME: this should verify that we are targeting a 486 or better. If not,
19512 // we will turn this bswap into something that will be lowered to logical
19513 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19514 // lower so don't worry about this.
19516 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19517 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19518 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19519 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19520 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19521 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19522 // No need to check constraints, nothing other than the equivalent of
19523 // "=r,0" would be valid here.
19524 return IntrinsicLowering::LowerToByteSwap(CI);
19527 // rorw $$8, ${0:w} --> llvm.bswap.i16
19528 if (CI->getType()->isIntegerTy(16) &&
19529 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19530 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19531 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19533 const std::string &ConstraintsStr = IA->getConstraintString();
19534 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19535 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19536 if (clobbersFlagRegisters(AsmPieces))
19537 return IntrinsicLowering::LowerToByteSwap(CI);
19541 if (CI->getType()->isIntegerTy(32) &&
19542 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19543 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19544 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19545 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19547 const std::string &ConstraintsStr = IA->getConstraintString();
19548 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19549 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19550 if (clobbersFlagRegisters(AsmPieces))
19551 return IntrinsicLowering::LowerToByteSwap(CI);
19554 if (CI->getType()->isIntegerTy(64)) {
19555 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19556 if (Constraints.size() >= 2 &&
19557 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19558 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19559 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19560 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19561 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19562 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19563 return IntrinsicLowering::LowerToByteSwap(CI);
19571 /// getConstraintType - Given a constraint letter, return the type of
19572 /// constraint it is for this target.
19573 X86TargetLowering::ConstraintType
19574 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19575 if (Constraint.size() == 1) {
19576 switch (Constraint[0]) {
19587 return C_RegisterClass;
19611 return TargetLowering::getConstraintType(Constraint);
19614 /// Examine constraint type and operand type and determine a weight value.
19615 /// This object must already have been set up with the operand type
19616 /// and the current alternative constraint selected.
19617 TargetLowering::ConstraintWeight
19618 X86TargetLowering::getSingleConstraintMatchWeight(
19619 AsmOperandInfo &info, const char *constraint) const {
19620 ConstraintWeight weight = CW_Invalid;
19621 Value *CallOperandVal = info.CallOperandVal;
19622 // If we don't have a value, we can't do a match,
19623 // but allow it at the lowest weight.
19624 if (CallOperandVal == NULL)
19626 Type *type = CallOperandVal->getType();
19627 // Look at the constraint type.
19628 switch (*constraint) {
19630 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19641 if (CallOperandVal->getType()->isIntegerTy())
19642 weight = CW_SpecificReg;
19647 if (type->isFloatingPointTy())
19648 weight = CW_SpecificReg;
19651 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19652 weight = CW_SpecificReg;
19656 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19657 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19658 weight = CW_Register;
19661 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19662 if (C->getZExtValue() <= 31)
19663 weight = CW_Constant;
19667 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19668 if (C->getZExtValue() <= 63)
19669 weight = CW_Constant;
19673 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19674 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19675 weight = CW_Constant;
19679 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19680 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19681 weight = CW_Constant;
19685 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19686 if (C->getZExtValue() <= 3)
19687 weight = CW_Constant;
19691 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19692 if (C->getZExtValue() <= 0xff)
19693 weight = CW_Constant;
19698 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19699 weight = CW_Constant;
19703 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19704 if ((C->getSExtValue() >= -0x80000000LL) &&
19705 (C->getSExtValue() <= 0x7fffffffLL))
19706 weight = CW_Constant;
19710 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19711 if (C->getZExtValue() <= 0xffffffff)
19712 weight = CW_Constant;
19719 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19720 /// with another that has more specific requirements based on the type of the
19721 /// corresponding operand.
19722 const char *X86TargetLowering::
19723 LowerXConstraint(EVT ConstraintVT) const {
19724 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19725 // 'f' like normal targets.
19726 if (ConstraintVT.isFloatingPoint()) {
19727 if (Subtarget->hasSSE2())
19729 if (Subtarget->hasSSE1())
19733 return TargetLowering::LowerXConstraint(ConstraintVT);
19736 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19737 /// vector. If it is invalid, don't add anything to Ops.
19738 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19739 std::string &Constraint,
19740 std::vector<SDValue>&Ops,
19741 SelectionDAG &DAG) const {
19742 SDValue Result(0, 0);
19744 // Only support length 1 constraints for now.
19745 if (Constraint.length() > 1) return;
19747 char ConstraintLetter = Constraint[0];
19748 switch (ConstraintLetter) {
19751 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19752 if (C->getZExtValue() <= 31) {
19753 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19759 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19760 if (C->getZExtValue() <= 63) {
19761 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19767 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19768 if (isInt<8>(C->getSExtValue())) {
19769 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19775 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19776 if (C->getZExtValue() <= 255) {
19777 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19783 // 32-bit signed value
19784 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19785 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19786 C->getSExtValue())) {
19787 // Widen to 64 bits here to get it sign extended.
19788 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19791 // FIXME gcc accepts some relocatable values here too, but only in certain
19792 // memory models; it's complicated.
19797 // 32-bit unsigned value
19798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19799 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19800 C->getZExtValue())) {
19801 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19805 // FIXME gcc accepts some relocatable values here too, but only in certain
19806 // memory models; it's complicated.
19810 // Literal immediates are always ok.
19811 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19812 // Widen to 64 bits here to get it sign extended.
19813 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19817 // In any sort of PIC mode addresses need to be computed at runtime by
19818 // adding in a register or some sort of table lookup. These can't
19819 // be used as immediates.
19820 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19823 // If we are in non-pic codegen mode, we allow the address of a global (with
19824 // an optional displacement) to be used with 'i'.
19825 GlobalAddressSDNode *GA = 0;
19826 int64_t Offset = 0;
19828 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19830 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19831 Offset += GA->getOffset();
19833 } else if (Op.getOpcode() == ISD::ADD) {
19834 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19835 Offset += C->getZExtValue();
19836 Op = Op.getOperand(0);
19839 } else if (Op.getOpcode() == ISD::SUB) {
19840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19841 Offset += -C->getZExtValue();
19842 Op = Op.getOperand(0);
19847 // Otherwise, this isn't something we can handle, reject it.
19851 const GlobalValue *GV = GA->getGlobal();
19852 // If we require an extra load to get this address, as in PIC mode, we
19853 // can't accept it.
19854 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19855 getTargetMachine())))
19858 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19859 GA->getValueType(0), Offset);
19864 if (Result.getNode()) {
19865 Ops.push_back(Result);
19868 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19871 std::pair<unsigned, const TargetRegisterClass*>
19872 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19874 // First, see if this is a constraint that directly corresponds to an LLVM
19876 if (Constraint.size() == 1) {
19877 // GCC Constraint Letters
19878 switch (Constraint[0]) {
19880 // TODO: Slight differences here in allocation order and leaving
19881 // RIP in the class. Do they matter any more here than they do
19882 // in the normal allocation?
19883 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19884 if (Subtarget->is64Bit()) {
19885 if (VT == MVT::i32 || VT == MVT::f32)
19886 return std::make_pair(0U, &X86::GR32RegClass);
19887 if (VT == MVT::i16)
19888 return std::make_pair(0U, &X86::GR16RegClass);
19889 if (VT == MVT::i8 || VT == MVT::i1)
19890 return std::make_pair(0U, &X86::GR8RegClass);
19891 if (VT == MVT::i64 || VT == MVT::f64)
19892 return std::make_pair(0U, &X86::GR64RegClass);
19895 // 32-bit fallthrough
19896 case 'Q': // Q_REGS
19897 if (VT == MVT::i32 || VT == MVT::f32)
19898 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19899 if (VT == MVT::i16)
19900 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19901 if (VT == MVT::i8 || VT == MVT::i1)
19902 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19903 if (VT == MVT::i64)
19904 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19906 case 'r': // GENERAL_REGS
19907 case 'l': // INDEX_REGS
19908 if (VT == MVT::i8 || VT == MVT::i1)
19909 return std::make_pair(0U, &X86::GR8RegClass);
19910 if (VT == MVT::i16)
19911 return std::make_pair(0U, &X86::GR16RegClass);
19912 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19913 return std::make_pair(0U, &X86::GR32RegClass);
19914 return std::make_pair(0U, &X86::GR64RegClass);
19915 case 'R': // LEGACY_REGS
19916 if (VT == MVT::i8 || VT == MVT::i1)
19917 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19918 if (VT == MVT::i16)
19919 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19920 if (VT == MVT::i32 || !Subtarget->is64Bit())
19921 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19922 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19923 case 'f': // FP Stack registers.
19924 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19925 // value to the correct fpstack register class.
19926 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19927 return std::make_pair(0U, &X86::RFP32RegClass);
19928 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19929 return std::make_pair(0U, &X86::RFP64RegClass);
19930 return std::make_pair(0U, &X86::RFP80RegClass);
19931 case 'y': // MMX_REGS if MMX allowed.
19932 if (!Subtarget->hasMMX()) break;
19933 return std::make_pair(0U, &X86::VR64RegClass);
19934 case 'Y': // SSE_REGS if SSE2 allowed
19935 if (!Subtarget->hasSSE2()) break;
19937 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19938 if (!Subtarget->hasSSE1()) break;
19940 switch (VT.SimpleTy) {
19942 // Scalar SSE types.
19945 return std::make_pair(0U, &X86::FR32RegClass);
19948 return std::make_pair(0U, &X86::FR64RegClass);
19956 return std::make_pair(0U, &X86::VR128RegClass);
19964 return std::make_pair(0U, &X86::VR256RegClass);
19969 return std::make_pair(0U, &X86::VR512RegClass);
19975 // Use the default implementation in TargetLowering to convert the register
19976 // constraint into a member of a register class.
19977 std::pair<unsigned, const TargetRegisterClass*> Res;
19978 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19980 // Not found as a standard register?
19981 if (Res.second == 0) {
19982 // Map st(0) -> st(7) -> ST0
19983 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19984 tolower(Constraint[1]) == 's' &&
19985 tolower(Constraint[2]) == 't' &&
19986 Constraint[3] == '(' &&
19987 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19988 Constraint[5] == ')' &&
19989 Constraint[6] == '}') {
19991 Res.first = X86::ST0+Constraint[4]-'0';
19992 Res.second = &X86::RFP80RegClass;
19996 // GCC allows "st(0)" to be called just plain "st".
19997 if (StringRef("{st}").equals_lower(Constraint)) {
19998 Res.first = X86::ST0;
19999 Res.second = &X86::RFP80RegClass;
20004 if (StringRef("{flags}").equals_lower(Constraint)) {
20005 Res.first = X86::EFLAGS;
20006 Res.second = &X86::CCRRegClass;
20010 // 'A' means EAX + EDX.
20011 if (Constraint == "A") {
20012 Res.first = X86::EAX;
20013 Res.second = &X86::GR32_ADRegClass;
20019 // Otherwise, check to see if this is a register class of the wrong value
20020 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
20021 // turn into {ax},{dx}.
20022 if (Res.second->hasType(VT))
20023 return Res; // Correct type already, nothing to do.
20025 // All of the single-register GCC register classes map their values onto
20026 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
20027 // really want an 8-bit or 32-bit register, map to the appropriate register
20028 // class and return the appropriate register.
20029 if (Res.second == &X86::GR16RegClass) {
20030 if (VT == MVT::i8 || VT == MVT::i1) {
20031 unsigned DestReg = 0;
20032 switch (Res.first) {
20034 case X86::AX: DestReg = X86::AL; break;
20035 case X86::DX: DestReg = X86::DL; break;
20036 case X86::CX: DestReg = X86::CL; break;
20037 case X86::BX: DestReg = X86::BL; break;
20040 Res.first = DestReg;
20041 Res.second = &X86::GR8RegClass;
20043 } else if (VT == MVT::i32 || VT == MVT::f32) {
20044 unsigned DestReg = 0;
20045 switch (Res.first) {
20047 case X86::AX: DestReg = X86::EAX; break;
20048 case X86::DX: DestReg = X86::EDX; break;
20049 case X86::CX: DestReg = X86::ECX; break;
20050 case X86::BX: DestReg = X86::EBX; break;
20051 case X86::SI: DestReg = X86::ESI; break;
20052 case X86::DI: DestReg = X86::EDI; break;
20053 case X86::BP: DestReg = X86::EBP; break;
20054 case X86::SP: DestReg = X86::ESP; break;
20057 Res.first = DestReg;
20058 Res.second = &X86::GR32RegClass;
20060 } else if (VT == MVT::i64 || VT == MVT::f64) {
20061 unsigned DestReg = 0;
20062 switch (Res.first) {
20064 case X86::AX: DestReg = X86::RAX; break;
20065 case X86::DX: DestReg = X86::RDX; break;
20066 case X86::CX: DestReg = X86::RCX; break;
20067 case X86::BX: DestReg = X86::RBX; break;
20068 case X86::SI: DestReg = X86::RSI; break;
20069 case X86::DI: DestReg = X86::RDI; break;
20070 case X86::BP: DestReg = X86::RBP; break;
20071 case X86::SP: DestReg = X86::RSP; break;
20074 Res.first = DestReg;
20075 Res.second = &X86::GR64RegClass;
20078 } else if (Res.second == &X86::FR32RegClass ||
20079 Res.second == &X86::FR64RegClass ||
20080 Res.second == &X86::VR128RegClass ||
20081 Res.second == &X86::VR256RegClass ||
20082 Res.second == &X86::FR32XRegClass ||
20083 Res.second == &X86::FR64XRegClass ||
20084 Res.second == &X86::VR128XRegClass ||
20085 Res.second == &X86::VR256XRegClass ||
20086 Res.second == &X86::VR512RegClass) {
20087 // Handle references to XMM physical registers that got mapped into the
20088 // wrong class. This can happen with constraints like {xmm0} where the
20089 // target independent register mapper will just pick the first match it can
20090 // find, ignoring the required type.
20092 if (VT == MVT::f32 || VT == MVT::i32)
20093 Res.second = &X86::FR32RegClass;
20094 else if (VT == MVT::f64 || VT == MVT::i64)
20095 Res.second = &X86::FR64RegClass;
20096 else if (X86::VR128RegClass.hasType(VT))
20097 Res.second = &X86::VR128RegClass;
20098 else if (X86::VR256RegClass.hasType(VT))
20099 Res.second = &X86::VR256RegClass;
20100 else if (X86::VR512RegClass.hasType(VT))
20101 Res.second = &X86::VR512RegClass;