1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
168 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
169 } else if (!Subtarget->useSoftFloat()) {
170 // We have an algorithm for SSE2->double, and we turn this into a
171 // 64-bit FILD followed by conditional FADD for other targets.
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 // We have an algorithm for SSE2, and we turn this into a 64-bit
174 // FILD for other targets.
175 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
178 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
180 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
183 if (!Subtarget->useSoftFloat()) {
184 // SSE has no i16 to fp conversion, only i32
185 if (X86ScalarSSEf32) {
186 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
187 // f32 and f64 cases are Legal, f80 case is not
188 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
191 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
198 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
199 // are Legal, f80 is custom lowered.
200 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
203 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
205 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
206 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
208 if (X86ScalarSSEf32) {
209 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
210 // f32 and f64 cases are Legal, f80 case is not
211 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
214 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 // Handle FP_TO_UINT by promoting the destination to a larger signed
219 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
220 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
221 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
223 if (Subtarget->is64Bit()) {
224 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
225 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
226 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
227 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
229 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
232 } else if (!Subtarget->useSoftFloat()) {
233 // Since AVX is a superset of SSE3, only check for SSE here.
234 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
235 // Expand FP_TO_UINT into a select.
236 // FIXME: We would like to use a Custom expander here eventually to do
237 // the optimal thing for SSE vs. the default expansion in the legalizer.
238 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
240 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
241 // With SSE3 we can use fisttpll to convert to a signed i64; without
242 // SSE, we're stuck with a fistpll.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
245 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
248 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
249 if (!X86ScalarSSEf64) {
250 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
251 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
252 if (Subtarget->is64Bit()) {
253 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
254 // Without SSE, i64->f64 goes through memory.
255 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
259 // Scalar integer divide and remainder are lowered to use operations that
260 // produce two results, to match the available instructions. This exposes
261 // the two-result form to trivial CSE, which is able to combine x/y and x%y
262 // into a single instruction.
264 // Scalar integer multiply-high is also lowered to use two-result
265 // operations, to match the available instructions. However, plain multiply
266 // (low) operations are left as Legal, as there are single-result
267 // instructions for this in x86. Using the two-result multiply instructions
268 // when both high and low results are needed must be arranged by dagcombine.
269 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
271 setOperationAction(ISD::MULHS, VT, Expand);
272 setOperationAction(ISD::MULHU, VT, Expand);
273 setOperationAction(ISD::SDIV, VT, Expand);
274 setOperationAction(ISD::UDIV, VT, Expand);
275 setOperationAction(ISD::SREM, VT, Expand);
276 setOperationAction(ISD::UREM, VT, Expand);
278 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
279 setOperationAction(ISD::ADDC, VT, Custom);
280 setOperationAction(ISD::ADDE, VT, Custom);
281 setOperationAction(ISD::SUBC, VT, Custom);
282 setOperationAction(ISD::SUBE, VT, Custom);
285 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
286 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
287 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
288 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
289 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
290 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
291 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
292 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
293 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
294 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
295 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
296 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
297 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
301 if (Subtarget->is64Bit())
302 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
303 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
304 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
305 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
306 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
308 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
309 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
310 // is. We should promote the value to 64-bits to solve this.
311 // This is what the CRT headers do - `fmodf` is an inline header
312 // function casting to f64 and calling `fmod`.
313 setOperationAction(ISD::FREM , MVT::f32 , Promote);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
318 setOperationAction(ISD::FREM , MVT::f64 , Expand);
319 setOperationAction(ISD::FREM , MVT::f80 , Expand);
320 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
322 // Promote the i8 variants and force them on up to i32 which has a shorter
324 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
326 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
327 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
328 if (Subtarget->hasBMI()) {
329 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
331 if (Subtarget->is64Bit())
332 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
334 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
335 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
336 if (Subtarget->is64Bit())
337 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
340 if (Subtarget->hasLZCNT()) {
341 // When promoting the i8 variants, force them to i32 for a shorter
343 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
346 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
347 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
349 if (Subtarget->is64Bit())
350 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
352 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
353 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
354 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
358 if (Subtarget->is64Bit()) {
359 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
364 // Special handling for half-precision floating point conversions.
365 // If we don't have F16C support, then lower half float conversions
366 // into library calls.
367 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
368 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
369 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
372 // There's never any support for operations beyond MVT::f32.
373 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
374 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
375 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
376 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
379 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
380 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
382 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
383 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
385 if (Subtarget->hasPOPCNT()) {
386 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
388 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
389 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
390 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
391 if (Subtarget->is64Bit())
392 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
395 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
397 if (!Subtarget->hasMOVBE())
398 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
400 // These should be promoted to a larger select which is supported.
401 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
402 // X86 wants to expand cmov itself.
403 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
404 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
405 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
407 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
410 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
413 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
417 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
419 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
420 setOperationAction(ISD::CATCHRET , MVT::Other, Custom);
421 setOperationAction(ISD::CLEANUPRET , MVT::Other, Custom);
422 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
423 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
424 // support continuation, user-level threading, and etc.. As a result, no
425 // other SjLj exception interfaces are implemented and please don't build
426 // your own exception handling based on them.
427 // LLVM/Clang supports zero-cost DWARF exception handling.
428 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
429 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
432 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
433 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
434 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
435 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
436 if (Subtarget->is64Bit())
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
438 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
439 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
440 if (Subtarget->is64Bit()) {
441 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
442 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
443 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
444 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
445 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
447 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
448 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
453 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
454 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
457 if (Subtarget->hasSSE1())
458 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
460 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
462 // Expand certain atomics
463 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
467 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
470 if (Subtarget->hasCmpxchg16b()) {
471 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
474 // FIXME - use subtarget debug flags
475 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
476 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
477 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
480 if (Subtarget->isTarget64BitLP64()) {
481 setExceptionPointerRegister(X86::RAX);
482 setExceptionSelectorRegister(X86::RDX);
484 setExceptionPointerRegister(X86::EAX);
485 setExceptionSelectorRegister(X86::EDX);
487 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
488 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
490 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
491 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::TRAP, MVT::Other, Legal);
494 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
496 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
497 setOperationAction(ISD::VASTART , MVT::Other, Custom);
498 setOperationAction(ISD::VAEND , MVT::Other, Expand);
499 if (Subtarget->is64Bit()) {
500 setOperationAction(ISD::VAARG , MVT::Other, Custom);
501 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
503 // TargetInfo::CharPtrBuiltinVaList
504 setOperationAction(ISD::VAARG , MVT::Other, Expand);
505 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
508 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
509 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
511 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
513 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
514 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
515 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
517 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
518 // f32 and f64 use SSE.
519 // Set up the FP register classes.
520 addRegisterClass(MVT::f32, &X86::FR32RegClass);
521 addRegisterClass(MVT::f64, &X86::FR64RegClass);
523 // Use ANDPD to simulate FABS.
524 setOperationAction(ISD::FABS , MVT::f64, Custom);
525 setOperationAction(ISD::FABS , MVT::f32, Custom);
527 // Use XORP to simulate FNEG.
528 setOperationAction(ISD::FNEG , MVT::f64, Custom);
529 setOperationAction(ISD::FNEG , MVT::f32, Custom);
531 // Use ANDPD and ORPD to simulate FCOPYSIGN.
532 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
533 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
535 // Lower this to FGETSIGNx86 plus an AND.
536 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
537 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
539 // We don't support sin/cos/fmod
540 setOperationAction(ISD::FSIN , MVT::f64, Expand);
541 setOperationAction(ISD::FCOS , MVT::f64, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
543 setOperationAction(ISD::FSIN , MVT::f32, Expand);
544 setOperationAction(ISD::FCOS , MVT::f32, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
547 // Expand FP immediates into loads from the stack, except for the special
549 addLegalFPImmediate(APFloat(+0.0)); // xorpd
550 addLegalFPImmediate(APFloat(+0.0f)); // xorps
551 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
552 // Use SSE for f32, x87 for f64.
553 // Set up the FP register classes.
554 addRegisterClass(MVT::f32, &X86::FR32RegClass);
555 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
557 // Use ANDPS to simulate FABS.
558 setOperationAction(ISD::FABS , MVT::f32, Custom);
560 // Use XORP to simulate FNEG.
561 setOperationAction(ISD::FNEG , MVT::f32, Custom);
563 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
565 // Use ANDPS and ORPS to simulate FCOPYSIGN.
566 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
567 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
569 // We don't support sin/cos/fmod
570 setOperationAction(ISD::FSIN , MVT::f32, Expand);
571 setOperationAction(ISD::FCOS , MVT::f32, Expand);
572 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
574 // Special cases we handle for FP constants.
575 addLegalFPImmediate(APFloat(+0.0f)); // xorps
576 addLegalFPImmediate(APFloat(+0.0)); // FLD0
577 addLegalFPImmediate(APFloat(+1.0)); // FLD1
578 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
579 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
581 if (!TM.Options.UnsafeFPMath) {
582 setOperationAction(ISD::FSIN , MVT::f64, Expand);
583 setOperationAction(ISD::FCOS , MVT::f64, Expand);
584 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
586 } else if (!Subtarget->useSoftFloat()) {
587 // f32 and f64 in x87.
588 // Set up the FP register classes.
589 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
590 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
592 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
593 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
595 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
597 if (!TM.Options.UnsafeFPMath) {
598 setOperationAction(ISD::FSIN , MVT::f64, Expand);
599 setOperationAction(ISD::FSIN , MVT::f32, Expand);
600 setOperationAction(ISD::FCOS , MVT::f64, Expand);
601 setOperationAction(ISD::FCOS , MVT::f32, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
603 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
605 addLegalFPImmediate(APFloat(+0.0)); // FLD0
606 addLegalFPImmediate(APFloat(+1.0)); // FLD1
607 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
608 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
609 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
610 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
611 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
612 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
615 // We don't support FMA.
616 setOperationAction(ISD::FMA, MVT::f64, Expand);
617 setOperationAction(ISD::FMA, MVT::f32, Expand);
619 // Long double always uses X87.
620 if (!Subtarget->useSoftFloat()) {
621 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
622 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
623 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
625 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
626 addLegalFPImmediate(TmpFlt); // FLD0
628 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
631 APFloat TmpFlt2(+1.0);
632 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
634 addLegalFPImmediate(TmpFlt2); // FLD1
635 TmpFlt2.changeSign();
636 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f80, Expand);
641 setOperationAction(ISD::FCOS , MVT::f80, Expand);
642 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
645 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
646 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
647 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
648 setOperationAction(ISD::FRINT, MVT::f80, Expand);
649 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
650 setOperationAction(ISD::FMA, MVT::f80, Expand);
653 // Always use a library call for pow.
654 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
656 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
658 setOperationAction(ISD::FLOG, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
660 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP, MVT::f80, Expand);
662 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
663 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
664 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
666 // First set operation action for all vector types to either promote
667 // (for widening) or expand (for scalarization). Then we will selectively
668 // turn on ones that can be effectively codegen'd.
669 for (MVT VT : MVT::vector_valuetypes()) {
670 setOperationAction(ISD::ADD , VT, Expand);
671 setOperationAction(ISD::SUB , VT, Expand);
672 setOperationAction(ISD::FADD, VT, Expand);
673 setOperationAction(ISD::FNEG, VT, Expand);
674 setOperationAction(ISD::FSUB, VT, Expand);
675 setOperationAction(ISD::MUL , VT, Expand);
676 setOperationAction(ISD::FMUL, VT, Expand);
677 setOperationAction(ISD::SDIV, VT, Expand);
678 setOperationAction(ISD::UDIV, VT, Expand);
679 setOperationAction(ISD::FDIV, VT, Expand);
680 setOperationAction(ISD::SREM, VT, Expand);
681 setOperationAction(ISD::UREM, VT, Expand);
682 setOperationAction(ISD::LOAD, VT, Expand);
683 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
684 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
685 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
686 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
688 setOperationAction(ISD::FABS, VT, Expand);
689 setOperationAction(ISD::FSIN, VT, Expand);
690 setOperationAction(ISD::FSINCOS, VT, Expand);
691 setOperationAction(ISD::FCOS, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FREM, VT, Expand);
694 setOperationAction(ISD::FMA, VT, Expand);
695 setOperationAction(ISD::FPOWI, VT, Expand);
696 setOperationAction(ISD::FSQRT, VT, Expand);
697 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
698 setOperationAction(ISD::FFLOOR, VT, Expand);
699 setOperationAction(ISD::FCEIL, VT, Expand);
700 setOperationAction(ISD::FTRUNC, VT, Expand);
701 setOperationAction(ISD::FRINT, VT, Expand);
702 setOperationAction(ISD::FNEARBYINT, VT, Expand);
703 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
704 setOperationAction(ISD::MULHS, VT, Expand);
705 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHU, VT, Expand);
707 setOperationAction(ISD::SDIVREM, VT, Expand);
708 setOperationAction(ISD::UDIVREM, VT, Expand);
709 setOperationAction(ISD::FPOW, VT, Expand);
710 setOperationAction(ISD::CTPOP, VT, Expand);
711 setOperationAction(ISD::CTTZ, VT, Expand);
712 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
713 setOperationAction(ISD::CTLZ, VT, Expand);
714 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::SHL, VT, Expand);
716 setOperationAction(ISD::SRA, VT, Expand);
717 setOperationAction(ISD::SRL, VT, Expand);
718 setOperationAction(ISD::ROTL, VT, Expand);
719 setOperationAction(ISD::ROTR, VT, Expand);
720 setOperationAction(ISD::BSWAP, VT, Expand);
721 setOperationAction(ISD::SETCC, VT, Expand);
722 setOperationAction(ISD::FLOG, VT, Expand);
723 setOperationAction(ISD::FLOG2, VT, Expand);
724 setOperationAction(ISD::FLOG10, VT, Expand);
725 setOperationAction(ISD::FEXP, VT, Expand);
726 setOperationAction(ISD::FEXP2, VT, Expand);
727 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
728 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
729 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
731 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
732 setOperationAction(ISD::TRUNCATE, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
734 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
735 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
736 setOperationAction(ISD::VSELECT, VT, Expand);
737 setOperationAction(ISD::SELECT_CC, VT, Expand);
738 for (MVT InnerVT : MVT::vector_valuetypes()) {
739 setTruncStoreAction(InnerVT, VT, Expand);
741 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
742 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
744 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
745 // types, we have to deal with them whether we ask for Expansion or not.
746 // Setting Expand causes its own optimisation problems though, so leave
748 if (VT.getVectorElementType() == MVT::i1)
749 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
751 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
752 // split/scalarized right now.
753 if (VT.getVectorElementType() == MVT::f16)
754 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
758 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
759 // with -msoft-float, disable use of MMX as well.
760 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
761 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
762 // No operations on x86mmx supported, everything uses intrinsics.
765 // MMX-sized vectors (other than x86mmx) are expected to be expanded
766 // into smaller operations.
767 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
768 setOperationAction(ISD::MULHS, MMXTy, Expand);
769 setOperationAction(ISD::AND, MMXTy, Expand);
770 setOperationAction(ISD::OR, MMXTy, Expand);
771 setOperationAction(ISD::XOR, MMXTy, Expand);
772 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
773 setOperationAction(ISD::SELECT, MMXTy, Expand);
774 setOperationAction(ISD::BITCAST, MMXTy, Expand);
776 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
778 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
779 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
781 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
783 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
784 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
786 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
787 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
788 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
789 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
790 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
791 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
792 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
793 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
797 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
798 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
800 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
801 // registers cannot be used even for integer operations.
802 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
803 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
804 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
805 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
807 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
808 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
809 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
810 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
811 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
812 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
813 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
814 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
815 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
816 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
817 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
818 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
819 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
821 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
822 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
823 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
825 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
826 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
828 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
829 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
831 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
832 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
833 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
836 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
837 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
838 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
839 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
841 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
842 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
848 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
852 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
853 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
854 MVT VT = (MVT::SimpleValueType)i;
855 // Do not attempt to custom lower non-power-of-2 vectors
856 if (!isPowerOf2_32(VT.getVectorNumElements()))
858 // Do not attempt to custom lower non-128-bit vectors
859 if (!VT.is128BitVector())
861 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
862 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
863 setOperationAction(ISD::VSELECT, VT, Custom);
864 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
867 // We support custom legalizing of sext and anyext loads for specific
868 // memory vector types which we can load as a scalar (or sequence of
869 // scalars) and extend in-register to a legal 128-bit vector type. For sext
870 // loads these must work with a single scalar load.
871 for (MVT VT : MVT::integer_vector_valuetypes()) {
872 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
883 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
885 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
887 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
889 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
892 if (Subtarget->is64Bit()) {
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
897 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
898 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
899 MVT VT = (MVT::SimpleValueType)i;
901 // Do not attempt to promote non-128-bit vectors
902 if (!VT.is128BitVector())
905 setOperationAction(ISD::AND, VT, Promote);
906 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
907 setOperationAction(ISD::OR, VT, Promote);
908 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
909 setOperationAction(ISD::XOR, VT, Promote);
910 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
911 setOperationAction(ISD::LOAD, VT, Promote);
912 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
913 setOperationAction(ISD::SELECT, VT, Promote);
914 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
917 // Custom lower v2i64 and v2f64 selects.
918 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
919 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
920 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
921 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
923 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
924 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
926 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
929 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
930 // As there is no 64-bit GPR available, we need build a special custom
931 // sequence to convert from v2i32 to v2f32.
932 if (!Subtarget->is64Bit())
933 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
936 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
938 for (MVT VT : MVT::fp_vector_valuetypes())
939 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
941 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
943 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
946 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
947 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
948 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
949 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
950 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
951 setOperationAction(ISD::FRINT, RoundedTy, Legal);
952 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
955 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
956 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
957 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
958 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
959 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
960 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
961 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
962 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
964 // FIXME: Do we need to handle scalar-to-vector here?
965 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
967 // We directly match byte blends in the backend as they match the VSELECT
969 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
971 // SSE41 brings specific instructions for doing vector sign extend even in
972 // cases where we don't have SRA.
973 for (MVT VT : MVT::integer_vector_valuetypes()) {
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
976 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
979 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
985 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
992 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
994 // i8 and i16 vectors are custom because the source register and source
995 // source memory operand types are not the same width. f32 vectors are
996 // custom since the immediate controlling the insert encodes additional
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1006 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1008 // FIXME: these should be Legal, but that's only for the case where
1009 // the index is constant. For now custom expand to deal with that.
1010 if (Subtarget->is64Bit()) {
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1012 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1016 if (Subtarget->hasSSE2()) {
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1019 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1022 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1024 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1025 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1027 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1028 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1030 // In the customized shift lowering, the legal cases in AVX2 will be
1032 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1033 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1035 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1036 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1038 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1039 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1042 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1043 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1044 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1045 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1046 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1047 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1048 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1050 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1051 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1052 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1054 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1056 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1057 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1058 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1059 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1060 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1062 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1063 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1064 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1065 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1067 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1069 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1070 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1071 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1072 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1073 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1075 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1076 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1077 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1078 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1080 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1081 // even though v8i16 is a legal type.
1082 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1083 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1084 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1086 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1087 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1088 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1090 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1091 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1093 for (MVT VT : MVT::fp_vector_valuetypes())
1094 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1097 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1099 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1100 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1102 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1106 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1108 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1110 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1111 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1112 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1114 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1115 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1117 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1118 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1119 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1120 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1121 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1122 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1123 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1124 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1125 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1127 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1128 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1129 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1130 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1132 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1133 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1135 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1136 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1137 setOperationAction(ISD::FMA, MVT::f32, Legal);
1138 setOperationAction(ISD::FMA, MVT::f64, Legal);
1141 if (Subtarget->hasInt256()) {
1142 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1143 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1144 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1145 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1147 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1148 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1149 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1150 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1152 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1153 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1154 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1155 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1157 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1158 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1159 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1160 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1162 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1163 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1164 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1165 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1166 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1167 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1169 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1171 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1172 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1173 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1175 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1176 // when we have a 256bit-wide blend with immediate.
1177 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1179 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1180 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1181 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1182 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1183 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1184 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1185 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1187 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1188 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1189 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1190 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1191 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1192 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1194 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1195 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1197 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1199 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1200 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1201 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1202 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1204 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1205 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1206 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1207 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1209 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1210 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1211 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1212 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1213 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1214 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1215 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1216 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1218 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1219 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1220 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1223 // In the customized shift lowering, the legal cases in AVX2 will be
1225 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1226 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1228 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1229 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1231 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1234 // Custom lower several nodes for 256-bit types.
1235 for (MVT VT : MVT::vector_valuetypes()) {
1236 if (VT.getScalarSizeInBits() >= 32) {
1237 setOperationAction(ISD::MLOAD, VT, Legal);
1238 setOperationAction(ISD::MSTORE, VT, Legal);
1240 // Extract subvector is special because the value type
1241 // (result) is 128-bit but the source is 256-bit wide.
1242 if (VT.is128BitVector()) {
1243 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1245 // Do not attempt to custom lower other non-256-bit vectors
1246 if (!VT.is256BitVector())
1249 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1250 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1251 setOperationAction(ISD::VSELECT, VT, Custom);
1252 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1253 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1254 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1255 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1256 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1259 if (Subtarget->hasInt256())
1260 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1263 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1264 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1265 MVT VT = (MVT::SimpleValueType)i;
1267 // Do not attempt to promote non-256-bit vectors
1268 if (!VT.is256BitVector())
1271 setOperationAction(ISD::AND, VT, Promote);
1272 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1273 setOperationAction(ISD::OR, VT, Promote);
1274 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1275 setOperationAction(ISD::XOR, VT, Promote);
1276 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1277 setOperationAction(ISD::LOAD, VT, Promote);
1278 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1279 setOperationAction(ISD::SELECT, VT, Promote);
1280 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1284 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1285 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1286 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1287 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1288 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1290 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1291 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1292 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1294 for (MVT VT : MVT::fp_vector_valuetypes())
1295 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1297 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1298 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1299 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1300 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1301 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1302 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1303 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1304 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1305 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1306 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1307 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1308 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1310 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1311 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1312 setOperationAction(ISD::XOR, MVT::i1, Legal);
1313 setOperationAction(ISD::OR, MVT::i1, Legal);
1314 setOperationAction(ISD::AND, MVT::i1, Legal);
1315 setOperationAction(ISD::SUB, MVT::i1, Custom);
1316 setOperationAction(ISD::ADD, MVT::i1, Custom);
1317 setOperationAction(ISD::MUL, MVT::i1, Custom);
1318 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1319 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1322 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1324 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1326 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1331 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1332 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1337 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1338 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1340 // FIXME: [US]INT_TO_FP are not legal for f80.
1341 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1342 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1343 if (Subtarget->is64Bit()) {
1344 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1345 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1347 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1348 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1349 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1350 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1351 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1352 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1354 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1355 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1356 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1359 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1360 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1361 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1362 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1364 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1365 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1366 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1367 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1368 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1369 if (Subtarget->hasVLX()){
1370 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1371 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1372 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1373 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1374 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1376 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1377 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1378 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1379 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1380 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1382 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1383 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1384 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1385 if (Subtarget->hasDQI()) {
1386 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1387 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1389 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1390 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1391 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1392 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1393 if (Subtarget->hasVLX()) {
1394 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1395 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1396 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1397 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1401 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1404 if (Subtarget->hasVLX()) {
1405 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1414 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1415 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1416 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1417 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1418 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1419 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1420 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1421 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1422 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1423 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1424 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1425 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1426 if (Subtarget->hasDQI()) {
1427 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1428 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1430 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1431 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1432 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1433 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1434 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1435 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1436 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1437 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1438 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1447 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1448 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1450 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1460 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1461 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1464 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1465 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1466 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1467 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1468 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1470 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1471 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1473 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1474 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1476 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1477 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1479 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1481 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1482 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1484 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1485 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1487 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1488 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1490 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1491 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1492 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1493 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1494 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1495 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1497 if (Subtarget->hasCDI()) {
1498 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1499 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1503 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1504 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1505 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1506 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1513 if (Subtarget->hasDQI()) {
1514 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1515 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1516 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1518 // Custom lower several nodes.
1519 for (MVT VT : MVT::vector_valuetypes()) {
1520 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1522 setOperationAction(ISD::AND, VT, Legal);
1523 setOperationAction(ISD::OR, VT, Legal);
1524 setOperationAction(ISD::XOR, VT, Legal);
1526 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1527 setOperationAction(ISD::MGATHER, VT, Custom);
1528 setOperationAction(ISD::MSCATTER, VT, Custom);
1530 // Extract subvector is special because the value type
1531 // (result) is 256/128-bit but the source is 512-bit wide.
1532 if (VT.is128BitVector() || VT.is256BitVector()) {
1533 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1535 if (VT.getVectorElementType() == MVT::i1)
1536 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1538 // Do not attempt to custom lower other non-512-bit vectors
1539 if (!VT.is512BitVector())
1542 if (EltSize >= 32) {
1543 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1544 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1545 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1546 setOperationAction(ISD::VSELECT, VT, Legal);
1547 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1548 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1549 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1550 setOperationAction(ISD::MLOAD, VT, Legal);
1551 setOperationAction(ISD::MSTORE, VT, Legal);
1554 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1555 MVT VT = (MVT::SimpleValueType)i;
1557 // Do not attempt to promote non-512-bit vectors.
1558 if (!VT.is512BitVector())
1561 setOperationAction(ISD::SELECT, VT, Promote);
1562 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1566 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1567 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1568 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1570 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1571 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1573 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1574 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1575 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1576 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1577 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1578 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1579 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1580 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1581 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1582 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1583 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1584 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1585 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1586 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1587 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1588 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1589 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1590 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1591 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1592 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1593 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1594 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1595 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1596 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1597 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1598 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1599 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1600 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1601 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1602 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1603 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1605 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1606 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1607 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1608 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1609 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1610 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1611 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1612 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1614 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1615 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1616 if (Subtarget->hasVLX())
1617 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1619 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1620 const MVT VT = (MVT::SimpleValueType)i;
1622 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1624 // Do not attempt to promote non-512-bit vectors.
1625 if (!VT.is512BitVector())
1629 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1630 setOperationAction(ISD::VSELECT, VT, Legal);
1635 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1636 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1637 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1639 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1640 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1641 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1642 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1644 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1645 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1646 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1647 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1648 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1650 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1651 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1652 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1653 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1654 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1655 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1656 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1657 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1659 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1660 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1661 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1662 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1663 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1664 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1665 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1666 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1669 // We want to custom lower some of our intrinsics.
1670 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1671 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1672 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1673 if (!Subtarget->is64Bit())
1674 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1676 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1677 // handle type legalization for these operations here.
1679 // FIXME: We really should do custom legalization for addition and
1680 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1681 // than generic legalization for 64-bit multiplication-with-overflow, though.
1682 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1683 // Add/Sub/Mul with overflow operations are custom lowered.
1685 setOperationAction(ISD::SADDO, VT, Custom);
1686 setOperationAction(ISD::UADDO, VT, Custom);
1687 setOperationAction(ISD::SSUBO, VT, Custom);
1688 setOperationAction(ISD::USUBO, VT, Custom);
1689 setOperationAction(ISD::SMULO, VT, Custom);
1690 setOperationAction(ISD::UMULO, VT, Custom);
1694 if (!Subtarget->is64Bit()) {
1695 // These libcalls are not available in 32-bit.
1696 setLibcallName(RTLIB::SHL_I128, nullptr);
1697 setLibcallName(RTLIB::SRL_I128, nullptr);
1698 setLibcallName(RTLIB::SRA_I128, nullptr);
1701 // Combine sin / cos into one node or libcall if possible.
1702 if (Subtarget->hasSinCos()) {
1703 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1704 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1705 if (Subtarget->isTargetDarwin()) {
1706 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1707 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1708 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1709 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1713 if (Subtarget->isTargetWin64()) {
1714 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1715 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1716 setOperationAction(ISD::SREM, MVT::i128, Custom);
1717 setOperationAction(ISD::UREM, MVT::i128, Custom);
1718 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1719 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1722 // We have target-specific dag combine patterns for the following nodes:
1723 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1724 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1725 setTargetDAGCombine(ISD::BITCAST);
1726 setTargetDAGCombine(ISD::VSELECT);
1727 setTargetDAGCombine(ISD::SELECT);
1728 setTargetDAGCombine(ISD::SHL);
1729 setTargetDAGCombine(ISD::SRA);
1730 setTargetDAGCombine(ISD::SRL);
1731 setTargetDAGCombine(ISD::OR);
1732 setTargetDAGCombine(ISD::AND);
1733 setTargetDAGCombine(ISD::ADD);
1734 setTargetDAGCombine(ISD::FADD);
1735 setTargetDAGCombine(ISD::FSUB);
1736 setTargetDAGCombine(ISD::FMA);
1737 setTargetDAGCombine(ISD::SUB);
1738 setTargetDAGCombine(ISD::LOAD);
1739 setTargetDAGCombine(ISD::MLOAD);
1740 setTargetDAGCombine(ISD::STORE);
1741 setTargetDAGCombine(ISD::MSTORE);
1742 setTargetDAGCombine(ISD::ZERO_EXTEND);
1743 setTargetDAGCombine(ISD::ANY_EXTEND);
1744 setTargetDAGCombine(ISD::SIGN_EXTEND);
1745 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1746 setTargetDAGCombine(ISD::SINT_TO_FP);
1747 setTargetDAGCombine(ISD::UINT_TO_FP);
1748 setTargetDAGCombine(ISD::SETCC);
1749 setTargetDAGCombine(ISD::BUILD_VECTOR);
1750 setTargetDAGCombine(ISD::MUL);
1751 setTargetDAGCombine(ISD::XOR);
1753 computeRegisterProperties(Subtarget->getRegisterInfo());
1755 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1756 MaxStoresPerMemsetOptSize = 8;
1757 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1758 MaxStoresPerMemcpyOptSize = 4;
1759 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1760 MaxStoresPerMemmoveOptSize = 4;
1761 setPrefLoopAlignment(4); // 2^4 bytes.
1763 // Predictable cmov don't hurt on atom because it's in-order.
1764 PredictableSelectIsExpensive = !Subtarget->isAtom();
1765 EnableExtLdPromotion = true;
1766 setPrefFunctionAlignment(4); // 2^4 bytes.
1768 verifyIntrinsicTables();
1771 // This has so far only been implemented for 64-bit MachO.
1772 bool X86TargetLowering::useLoadStackGuardNode() const {
1773 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1776 TargetLoweringBase::LegalizeTypeAction
1777 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1778 if (ExperimentalVectorWideningLegalization &&
1779 VT.getVectorNumElements() != 1 &&
1780 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1781 return TypeWidenVector;
1783 return TargetLoweringBase::getPreferredVectorAction(VT);
1786 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1789 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1791 const unsigned NumElts = VT.getVectorNumElements();
1792 const EVT EltVT = VT.getVectorElementType();
1793 if (VT.is512BitVector()) {
1794 if (Subtarget->hasAVX512())
1795 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1796 EltVT == MVT::f32 || EltVT == MVT::f64)
1798 case 8: return MVT::v8i1;
1799 case 16: return MVT::v16i1;
1801 if (Subtarget->hasBWI())
1802 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1804 case 32: return MVT::v32i1;
1805 case 64: return MVT::v64i1;
1809 if (VT.is256BitVector() || VT.is128BitVector()) {
1810 if (Subtarget->hasVLX())
1811 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1812 EltVT == MVT::f32 || EltVT == MVT::f64)
1814 case 2: return MVT::v2i1;
1815 case 4: return MVT::v4i1;
1816 case 8: return MVT::v8i1;
1818 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1819 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1821 case 8: return MVT::v8i1;
1822 case 16: return MVT::v16i1;
1823 case 32: return MVT::v32i1;
1827 return VT.changeVectorElementTypeToInteger();
1830 /// Helper for getByValTypeAlignment to determine
1831 /// the desired ByVal argument alignment.
1832 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1835 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1836 if (VTy->getBitWidth() == 128)
1838 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1839 unsigned EltAlign = 0;
1840 getMaxByValAlign(ATy->getElementType(), EltAlign);
1841 if (EltAlign > MaxAlign)
1842 MaxAlign = EltAlign;
1843 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1844 for (auto *EltTy : STy->elements()) {
1845 unsigned EltAlign = 0;
1846 getMaxByValAlign(EltTy, EltAlign);
1847 if (EltAlign > MaxAlign)
1848 MaxAlign = EltAlign;
1855 /// Return the desired alignment for ByVal aggregate
1856 /// function arguments in the caller parameter area. For X86, aggregates
1857 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1858 /// are at 4-byte boundaries.
1859 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1860 const DataLayout &DL) const {
1861 if (Subtarget->is64Bit()) {
1862 // Max of 8 and alignment of type.
1863 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1870 if (Subtarget->hasSSE1())
1871 getMaxByValAlign(Ty, Align);
1875 /// Returns the target specific optimal type for load
1876 /// and store operations as a result of memset, memcpy, and memmove
1877 /// lowering. If DstAlign is zero that means it's safe to destination
1878 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1879 /// means there isn't a need to check it against alignment requirement,
1880 /// probably because the source does not need to be loaded. If 'IsMemset' is
1881 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1882 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1883 /// source is constant so it does not need to be loaded.
1884 /// It returns EVT::Other if the type should be determined using generic
1885 /// target-independent logic.
1887 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1888 unsigned DstAlign, unsigned SrcAlign,
1889 bool IsMemset, bool ZeroMemset,
1891 MachineFunction &MF) const {
1892 const Function *F = MF.getFunction();
1893 if ((!IsMemset || ZeroMemset) &&
1894 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1896 (!Subtarget->isUnalignedMem16Slow() ||
1897 ((DstAlign == 0 || DstAlign >= 16) &&
1898 (SrcAlign == 0 || SrcAlign >= 16)))) {
1900 // FIXME: Check if unaligned 32-byte accesses are slow.
1901 if (Subtarget->hasInt256())
1903 if (Subtarget->hasFp256())
1906 if (Subtarget->hasSSE2())
1908 if (Subtarget->hasSSE1())
1910 } else if (!MemcpyStrSrc && Size >= 8 &&
1911 !Subtarget->is64Bit() &&
1912 Subtarget->hasSSE2()) {
1913 // Do not use f64 to lower memcpy if source is string constant. It's
1914 // better to use i32 to avoid the loads.
1918 // This is a compromise. If we reach here, unaligned accesses may be slow on
1919 // this target. However, creating smaller, aligned accesses could be even
1920 // slower and would certainly be a lot more code.
1921 if (Subtarget->is64Bit() && Size >= 8)
1926 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1928 return X86ScalarSSEf32;
1929 else if (VT == MVT::f64)
1930 return X86ScalarSSEf64;
1935 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1940 switch (VT.getSizeInBits()) {
1942 // 8-byte and under are always assumed to be fast.
1946 *Fast = !Subtarget->isUnalignedMem16Slow();
1949 *Fast = !Subtarget->isUnalignedMem32Slow();
1951 // TODO: What about AVX-512 (512-bit) accesses?
1954 // Misaligned accesses of any size are always allowed.
1958 /// Return the entry encoding for a jump table in the
1959 /// current function. The returned value is a member of the
1960 /// MachineJumpTableInfo::JTEntryKind enum.
1961 unsigned X86TargetLowering::getJumpTableEncoding() const {
1962 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1964 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1965 Subtarget->isPICStyleGOT())
1966 return MachineJumpTableInfo::EK_Custom32;
1968 // Otherwise, use the normal jump table encoding heuristics.
1969 return TargetLowering::getJumpTableEncoding();
1972 bool X86TargetLowering::useSoftFloat() const {
1973 return Subtarget->useSoftFloat();
1977 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1978 const MachineBasicBlock *MBB,
1979 unsigned uid,MCContext &Ctx) const{
1980 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1981 Subtarget->isPICStyleGOT());
1982 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1984 return MCSymbolRefExpr::create(MBB->getSymbol(),
1985 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1988 /// Returns relocation base for the given PIC jumptable.
1989 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1990 SelectionDAG &DAG) const {
1991 if (!Subtarget->is64Bit())
1992 // This doesn't have SDLoc associated with it, but is not really the
1993 // same as a Register.
1994 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
1995 getPointerTy(DAG.getDataLayout()));
1999 /// This returns the relocation base for the given PIC jumptable,
2000 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2001 const MCExpr *X86TargetLowering::
2002 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2003 MCContext &Ctx) const {
2004 // X86-64 uses RIP relative addressing based on the jump table label.
2005 if (Subtarget->isPICStyleRIPRel())
2006 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2008 // Otherwise, the reference is relative to the PIC base.
2009 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2012 std::pair<const TargetRegisterClass *, uint8_t>
2013 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2015 const TargetRegisterClass *RRC = nullptr;
2017 switch (VT.SimpleTy) {
2019 return TargetLowering::findRepresentativeClass(TRI, VT);
2020 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2021 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2024 RRC = &X86::VR64RegClass;
2026 case MVT::f32: case MVT::f64:
2027 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2028 case MVT::v4f32: case MVT::v2f64:
2029 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2031 RRC = &X86::VR128RegClass;
2034 return std::make_pair(RRC, Cost);
2037 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2038 unsigned &Offset) const {
2039 if (!Subtarget->isTargetLinux())
2042 if (Subtarget->is64Bit()) {
2043 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2045 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2057 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2058 unsigned DestAS) const {
2059 assert(SrcAS != DestAS && "Expected different address spaces!");
2061 return SrcAS < 256 && DestAS < 256;
2064 //===----------------------------------------------------------------------===//
2065 // Return Value Calling Convention Implementation
2066 //===----------------------------------------------------------------------===//
2068 #include "X86GenCallingConv.inc"
2071 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2072 MachineFunction &MF, bool isVarArg,
2073 const SmallVectorImpl<ISD::OutputArg> &Outs,
2074 LLVMContext &Context) const {
2075 SmallVector<CCValAssign, 16> RVLocs;
2076 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2077 return CCInfo.CheckReturn(Outs, RetCC_X86);
2080 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2081 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2086 X86TargetLowering::LowerReturn(SDValue Chain,
2087 CallingConv::ID CallConv, bool isVarArg,
2088 const SmallVectorImpl<ISD::OutputArg> &Outs,
2089 const SmallVectorImpl<SDValue> &OutVals,
2090 SDLoc dl, SelectionDAG &DAG) const {
2091 MachineFunction &MF = DAG.getMachineFunction();
2092 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2094 SmallVector<CCValAssign, 16> RVLocs;
2095 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2096 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2099 SmallVector<SDValue, 6> RetOps;
2100 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2101 // Operand #1 = Bytes To Pop
2102 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2105 // Copy the result values into the output registers.
2106 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2107 CCValAssign &VA = RVLocs[i];
2108 assert(VA.isRegLoc() && "Can only return in registers!");
2109 SDValue ValToCopy = OutVals[i];
2110 EVT ValVT = ValToCopy.getValueType();
2112 // Promote values to the appropriate types.
2113 if (VA.getLocInfo() == CCValAssign::SExt)
2114 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2115 else if (VA.getLocInfo() == CCValAssign::ZExt)
2116 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2117 else if (VA.getLocInfo() == CCValAssign::AExt) {
2118 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2119 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2121 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2123 else if (VA.getLocInfo() == CCValAssign::BCvt)
2124 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2126 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2127 "Unexpected FP-extend for return value.");
2129 // If this is x86-64, and we disabled SSE, we can't return FP values,
2130 // or SSE or MMX vectors.
2131 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2132 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2133 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2134 report_fatal_error("SSE register return with SSE disabled");
2136 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2137 // llvm-gcc has never done it right and no one has noticed, so this
2138 // should be OK for now.
2139 if (ValVT == MVT::f64 &&
2140 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2141 report_fatal_error("SSE2 register return with SSE2 disabled");
2143 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2144 // the RET instruction and handled by the FP Stackifier.
2145 if (VA.getLocReg() == X86::FP0 ||
2146 VA.getLocReg() == X86::FP1) {
2147 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2148 // change the value to the FP stack register class.
2149 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2150 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2151 RetOps.push_back(ValToCopy);
2152 // Don't emit a copytoreg.
2156 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2157 // which is returned in RAX / RDX.
2158 if (Subtarget->is64Bit()) {
2159 if (ValVT == MVT::x86mmx) {
2160 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2161 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2162 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2164 // If we don't have SSE2 available, convert to v4f32 so the generated
2165 // register is legal.
2166 if (!Subtarget->hasSSE2())
2167 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2172 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2173 Flag = Chain.getValue(1);
2174 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2177 // All x86 ABIs require that for returning structs by value we copy
2178 // the sret argument into %rax/%eax (depending on ABI) for the return.
2179 // We saved the argument into a virtual register in the entry block,
2180 // so now we copy the value out and into %rax/%eax.
2182 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2183 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2184 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2185 // either case FuncInfo->setSRetReturnReg() will have been called.
2186 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2187 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2188 getPointerTy(MF.getDataLayout()));
2191 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2192 X86::RAX : X86::EAX;
2193 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2194 Flag = Chain.getValue(1);
2196 // RAX/EAX now acts like a return value.
2198 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2201 RetOps[0] = Chain; // Update chain.
2203 // Add the flag if we have it.
2205 RetOps.push_back(Flag);
2207 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2210 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2211 if (N->getNumValues() != 1)
2213 if (!N->hasNUsesOfValue(1, 0))
2216 SDValue TCChain = Chain;
2217 SDNode *Copy = *N->use_begin();
2218 if (Copy->getOpcode() == ISD::CopyToReg) {
2219 // If the copy has a glue operand, we conservatively assume it isn't safe to
2220 // perform a tail call.
2221 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2223 TCChain = Copy->getOperand(0);
2224 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2227 bool HasRet = false;
2228 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2230 if (UI->getOpcode() != X86ISD::RET_FLAG)
2232 // If we are returning more than one value, we can definitely
2233 // not make a tail call see PR19530
2234 if (UI->getNumOperands() > 4)
2236 if (UI->getNumOperands() == 4 &&
2237 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2250 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2251 ISD::NodeType ExtendKind) const {
2253 // TODO: Is this also valid on 32-bit?
2254 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2255 ReturnMVT = MVT::i8;
2257 ReturnMVT = MVT::i32;
2259 EVT MinVT = getRegisterType(Context, ReturnMVT);
2260 return VT.bitsLT(MinVT) ? MinVT : VT;
2263 /// Lower the result values of a call into the
2264 /// appropriate copies out of appropriate physical registers.
2267 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2268 CallingConv::ID CallConv, bool isVarArg,
2269 const SmallVectorImpl<ISD::InputArg> &Ins,
2270 SDLoc dl, SelectionDAG &DAG,
2271 SmallVectorImpl<SDValue> &InVals) const {
2273 // Assign locations to each value returned by this call.
2274 SmallVector<CCValAssign, 16> RVLocs;
2275 bool Is64Bit = Subtarget->is64Bit();
2276 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2278 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2280 // Copy all of the result registers out of their specified physreg.
2281 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2282 CCValAssign &VA = RVLocs[i];
2283 EVT CopyVT = VA.getLocVT();
2285 // If this is x86-64, and we disabled SSE, we can't return FP values
2286 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2287 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2288 report_fatal_error("SSE register return with SSE disabled");
2291 // If we prefer to use the value in xmm registers, copy it out as f80 and
2292 // use a truncate to move it from fp stack reg to xmm reg.
2293 bool RoundAfterCopy = false;
2294 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2295 isScalarFPTypeInSSEReg(VA.getValVT())) {
2297 RoundAfterCopy = (CopyVT != VA.getLocVT());
2300 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2301 CopyVT, InFlag).getValue(1);
2302 SDValue Val = Chain.getValue(0);
2305 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2306 // This truncation won't change the value.
2307 DAG.getIntPtrConstant(1, dl));
2309 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2310 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2312 InFlag = Chain.getValue(2);
2313 InVals.push_back(Val);
2319 //===----------------------------------------------------------------------===//
2320 // C & StdCall & Fast Calling Convention implementation
2321 //===----------------------------------------------------------------------===//
2322 // StdCall calling convention seems to be standard for many Windows' API
2323 // routines and around. It differs from C calling convention just a little:
2324 // callee should clean up the stack, not caller. Symbols should be also
2325 // decorated in some fancy way :) It doesn't support any vector arguments.
2326 // For info on fast calling convention see Fast Calling Convention (tail call)
2327 // implementation LowerX86_32FastCCCallTo.
2329 /// CallIsStructReturn - Determines whether a call uses struct return
2331 enum StructReturnType {
2336 static StructReturnType
2337 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2339 return NotStructReturn;
2341 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2342 if (!Flags.isSRet())
2343 return NotStructReturn;
2344 if (Flags.isInReg())
2345 return RegStructReturn;
2346 return StackStructReturn;
2349 /// Determines whether a function uses struct return semantics.
2350 static StructReturnType
2351 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2353 return NotStructReturn;
2355 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2356 if (!Flags.isSRet())
2357 return NotStructReturn;
2358 if (Flags.isInReg())
2359 return RegStructReturn;
2360 return StackStructReturn;
2363 /// Make a copy of an aggregate at address specified by "Src" to address
2364 /// "Dst" with size and alignment information specified by the specific
2365 /// parameter attribute. The copy will be passed as a byval function parameter.
2367 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2368 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2370 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2372 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2373 /*isVolatile*/false, /*AlwaysInline=*/true,
2374 /*isTailCall*/false,
2375 MachinePointerInfo(), MachinePointerInfo());
2378 /// Return true if the calling convention is one that
2379 /// supports tail call optimization.
2380 static bool IsTailCallConvention(CallingConv::ID CC) {
2381 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2382 CC == CallingConv::HiPE);
2385 /// \brief Return true if the calling convention is a C calling convention.
2386 static bool IsCCallConvention(CallingConv::ID CC) {
2387 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2388 CC == CallingConv::X86_64_SysV);
2391 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2393 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2394 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2398 CallingConv::ID CalleeCC = CS.getCallingConv();
2399 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2405 /// Return true if the function is being made into
2406 /// a tailcall target by changing its ABI.
2407 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2408 bool GuaranteedTailCallOpt) {
2409 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2413 X86TargetLowering::LowerMemArgument(SDValue Chain,
2414 CallingConv::ID CallConv,
2415 const SmallVectorImpl<ISD::InputArg> &Ins,
2416 SDLoc dl, SelectionDAG &DAG,
2417 const CCValAssign &VA,
2418 MachineFrameInfo *MFI,
2420 // Create the nodes corresponding to a load from this parameter slot.
2421 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2422 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2423 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2424 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2427 // If value is passed by pointer we have address passed instead of the value
2429 bool ExtendedInMem = VA.isExtInLoc() &&
2430 VA.getValVT().getScalarType() == MVT::i1;
2432 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2433 ValVT = VA.getLocVT();
2435 ValVT = VA.getValVT();
2437 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2438 // changed with more analysis.
2439 // In case of tail call optimization mark all arguments mutable. Since they
2440 // could be overwritten by lowering of arguments in case of a tail call.
2441 if (Flags.isByVal()) {
2442 unsigned Bytes = Flags.getByValSize();
2443 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2444 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2445 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2447 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2448 VA.getLocMemOffset(), isImmutable);
2449 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2450 SDValue Val = DAG.getLoad(
2451 ValVT, dl, Chain, FIN,
2452 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2454 return ExtendedInMem ?
2455 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2459 // FIXME: Get this from tablegen.
2460 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2461 const X86Subtarget *Subtarget) {
2462 assert(Subtarget->is64Bit());
2464 if (Subtarget->isCallingConvWin64(CallConv)) {
2465 static const MCPhysReg GPR64ArgRegsWin64[] = {
2466 X86::RCX, X86::RDX, X86::R8, X86::R9
2468 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2471 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2472 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2474 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2477 // FIXME: Get this from tablegen.
2478 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2479 CallingConv::ID CallConv,
2480 const X86Subtarget *Subtarget) {
2481 assert(Subtarget->is64Bit());
2482 if (Subtarget->isCallingConvWin64(CallConv)) {
2483 // The XMM registers which might contain var arg parameters are shadowed
2484 // in their paired GPR. So we only need to save the GPR to their home
2486 // TODO: __vectorcall will change this.
2490 const Function *Fn = MF.getFunction();
2491 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2492 bool isSoftFloat = Subtarget->useSoftFloat();
2493 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2494 "SSE register cannot be used when SSE is disabled!");
2495 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2496 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2500 static const MCPhysReg XMMArgRegs64Bit[] = {
2501 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2502 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2504 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2508 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2509 CallingConv::ID CallConv,
2511 const SmallVectorImpl<ISD::InputArg> &Ins,
2514 SmallVectorImpl<SDValue> &InVals)
2516 MachineFunction &MF = DAG.getMachineFunction();
2517 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2518 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2520 const Function* Fn = MF.getFunction();
2521 if (Fn->hasExternalLinkage() &&
2522 Subtarget->isTargetCygMing() &&
2523 Fn->getName() == "main")
2524 FuncInfo->setForceFramePointer(true);
2526 MachineFrameInfo *MFI = MF.getFrameInfo();
2527 bool Is64Bit = Subtarget->is64Bit();
2528 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2530 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2531 "Var args not supported with calling convention fastcc, ghc or hipe");
2533 // Assign locations to all of the incoming arguments.
2534 SmallVector<CCValAssign, 16> ArgLocs;
2535 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2537 // Allocate shadow area for Win64
2539 CCInfo.AllocateStack(32, 8);
2541 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2543 unsigned LastVal = ~0U;
2545 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2546 CCValAssign &VA = ArgLocs[i];
2547 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2549 assert(VA.getValNo() != LastVal &&
2550 "Don't support value assigned to multiple locs yet");
2552 LastVal = VA.getValNo();
2554 if (VA.isRegLoc()) {
2555 EVT RegVT = VA.getLocVT();
2556 const TargetRegisterClass *RC;
2557 if (RegVT == MVT::i32)
2558 RC = &X86::GR32RegClass;
2559 else if (Is64Bit && RegVT == MVT::i64)
2560 RC = &X86::GR64RegClass;
2561 else if (RegVT == MVT::f32)
2562 RC = &X86::FR32RegClass;
2563 else if (RegVT == MVT::f64)
2564 RC = &X86::FR64RegClass;
2565 else if (RegVT.is512BitVector())
2566 RC = &X86::VR512RegClass;
2567 else if (RegVT.is256BitVector())
2568 RC = &X86::VR256RegClass;
2569 else if (RegVT.is128BitVector())
2570 RC = &X86::VR128RegClass;
2571 else if (RegVT == MVT::x86mmx)
2572 RC = &X86::VR64RegClass;
2573 else if (RegVT == MVT::i1)
2574 RC = &X86::VK1RegClass;
2575 else if (RegVT == MVT::v8i1)
2576 RC = &X86::VK8RegClass;
2577 else if (RegVT == MVT::v16i1)
2578 RC = &X86::VK16RegClass;
2579 else if (RegVT == MVT::v32i1)
2580 RC = &X86::VK32RegClass;
2581 else if (RegVT == MVT::v64i1)
2582 RC = &X86::VK64RegClass;
2584 llvm_unreachable("Unknown argument type!");
2586 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2587 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2589 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2590 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2592 if (VA.getLocInfo() == CCValAssign::SExt)
2593 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2594 DAG.getValueType(VA.getValVT()));
2595 else if (VA.getLocInfo() == CCValAssign::ZExt)
2596 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2597 DAG.getValueType(VA.getValVT()));
2598 else if (VA.getLocInfo() == CCValAssign::BCvt)
2599 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2601 if (VA.isExtInLoc()) {
2602 // Handle MMX values passed in XMM regs.
2603 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2604 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2606 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2609 assert(VA.isMemLoc());
2610 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2613 // If value is passed via pointer - do a load.
2614 if (VA.getLocInfo() == CCValAssign::Indirect)
2615 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2616 MachinePointerInfo(), false, false, false, 0);
2618 InVals.push_back(ArgValue);
2621 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2622 // All x86 ABIs require that for returning structs by value we copy the
2623 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2624 // the argument into a virtual register so that we can access it from the
2626 if (Ins[i].Flags.isSRet()) {
2627 unsigned Reg = FuncInfo->getSRetReturnReg();
2629 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2630 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2631 FuncInfo->setSRetReturnReg(Reg);
2633 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2634 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2639 unsigned StackSize = CCInfo.getNextStackOffset();
2640 // Align stack specially for tail calls.
2641 if (FuncIsMadeTailCallSafe(CallConv,
2642 MF.getTarget().Options.GuaranteedTailCallOpt))
2643 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2645 // If the function takes variable number of arguments, make a frame index for
2646 // the start of the first vararg value... for expansion of llvm.va_start. We
2647 // can skip this if there are no va_start calls.
2648 if (MFI->hasVAStart() &&
2649 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2650 CallConv != CallingConv::X86_ThisCall))) {
2651 FuncInfo->setVarArgsFrameIndex(
2652 MFI->CreateFixedObject(1, StackSize, true));
2655 MachineModuleInfo &MMI = MF.getMMI();
2656 const Function *WinEHParent = nullptr;
2657 if (MMI.hasWinEHFuncInfo(Fn))
2658 WinEHParent = MMI.getWinEHParent(Fn);
2659 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2660 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2662 // Figure out if XMM registers are in use.
2663 assert(!(Subtarget->useSoftFloat() &&
2664 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2665 "SSE register cannot be used when SSE is disabled!");
2667 // 64-bit calling conventions support varargs and register parameters, so we
2668 // have to do extra work to spill them in the prologue.
2669 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2670 // Find the first unallocated argument registers.
2671 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2672 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2673 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2674 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2675 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2676 "SSE register cannot be used when SSE is disabled!");
2678 // Gather all the live in physical registers.
2679 SmallVector<SDValue, 6> LiveGPRs;
2680 SmallVector<SDValue, 8> LiveXMMRegs;
2682 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2683 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2685 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2687 if (!ArgXMMs.empty()) {
2688 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2689 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2690 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2691 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2692 LiveXMMRegs.push_back(
2693 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2698 // Get to the caller-allocated home save location. Add 8 to account
2699 // for the return address.
2700 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2701 FuncInfo->setRegSaveFrameIndex(
2702 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2703 // Fixup to set vararg frame on shadow area (4 x i64).
2705 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2707 // For X86-64, if there are vararg parameters that are passed via
2708 // registers, then we must store them to their spots on the stack so
2709 // they may be loaded by deferencing the result of va_next.
2710 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2711 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2712 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2713 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2716 // Store the integer parameter registers.
2717 SmallVector<SDValue, 8> MemOps;
2718 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2719 getPointerTy(DAG.getDataLayout()));
2720 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2721 for (SDValue Val : LiveGPRs) {
2722 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2723 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2725 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2726 MachinePointerInfo::getFixedStack(
2727 DAG.getMachineFunction(),
2728 FuncInfo->getRegSaveFrameIndex(), Offset),
2730 MemOps.push_back(Store);
2734 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2735 // Now store the XMM (fp + vector) parameter registers.
2736 SmallVector<SDValue, 12> SaveXMMOps;
2737 SaveXMMOps.push_back(Chain);
2738 SaveXMMOps.push_back(ALVal);
2739 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2740 FuncInfo->getRegSaveFrameIndex(), dl));
2741 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2742 FuncInfo->getVarArgsFPOffset(), dl));
2743 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2745 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2746 MVT::Other, SaveXMMOps));
2749 if (!MemOps.empty())
2750 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2751 } else if (IsWin64 && IsWinEHOutlined) {
2752 // Get to the caller-allocated home save location. Add 8 to account
2753 // for the return address.
2754 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2755 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2756 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2758 MMI.getWinEHFuncInfo(Fn)
2759 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2760 FuncInfo->getRegSaveFrameIndex();
2762 // Store the second integer parameter (rdx) into rsp+16 relative to the
2763 // stack pointer at the entry of the function.
2764 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2765 getPointerTy(DAG.getDataLayout()));
2766 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2767 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2768 Chain = DAG.getStore(
2769 Val.getValue(1), dl, Val, RSFIN,
2770 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(),
2771 FuncInfo->getRegSaveFrameIndex()),
2772 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2775 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2776 // Find the largest legal vector type.
2777 MVT VecVT = MVT::Other;
2778 // FIXME: Only some x86_32 calling conventions support AVX512.
2779 if (Subtarget->hasAVX512() &&
2780 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2781 CallConv == CallingConv::Intel_OCL_BI)))
2782 VecVT = MVT::v16f32;
2783 else if (Subtarget->hasAVX())
2785 else if (Subtarget->hasSSE2())
2788 // We forward some GPRs and some vector types.
2789 SmallVector<MVT, 2> RegParmTypes;
2790 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2791 RegParmTypes.push_back(IntVT);
2792 if (VecVT != MVT::Other)
2793 RegParmTypes.push_back(VecVT);
2795 // Compute the set of forwarded registers. The rest are scratch.
2796 SmallVectorImpl<ForwardedRegister> &Forwards =
2797 FuncInfo->getForwardedMustTailRegParms();
2798 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2800 // Conservatively forward AL on x86_64, since it might be used for varargs.
2801 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2802 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2803 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2806 // Copy all forwards from physical to virtual registers.
2807 for (ForwardedRegister &F : Forwards) {
2808 // FIXME: Can we use a less constrained schedule?
2809 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2810 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2811 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2815 // Some CCs need callee pop.
2816 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2817 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2818 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2820 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2821 // If this is an sret function, the return should pop the hidden pointer.
2822 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2823 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2824 argsAreStructReturn(Ins) == StackStructReturn)
2825 FuncInfo->setBytesToPopOnReturn(4);
2829 // RegSaveFrameIndex is X86-64 only.
2830 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2831 if (CallConv == CallingConv::X86_FastCall ||
2832 CallConv == CallingConv::X86_ThisCall)
2833 // fastcc functions can't have varargs.
2834 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2837 FuncInfo->setArgumentStackSize(StackSize);
2839 if (IsWinEHParent) {
2841 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2842 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2843 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2844 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2845 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2846 MachinePointerInfo::getFixedStack(
2847 DAG.getMachineFunction(), UnwindHelpFI),
2848 /*isVolatile=*/true,
2849 /*isNonTemporal=*/false, /*Alignment=*/0);
2851 // Functions using Win32 EH are considered to have opaque SP adjustments
2852 // to force local variables to be addressed from the frame or base
2854 MFI->setHasOpaqueSPAdjustment(true);
2862 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2863 SDValue StackPtr, SDValue Arg,
2864 SDLoc dl, SelectionDAG &DAG,
2865 const CCValAssign &VA,
2866 ISD::ArgFlagsTy Flags) const {
2867 unsigned LocMemOffset = VA.getLocMemOffset();
2868 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2869 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2871 if (Flags.isByVal())
2872 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2874 return DAG.getStore(
2875 Chain, dl, Arg, PtrOff,
2876 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2880 /// Emit a load of return address if tail call
2881 /// optimization is performed and it is required.
2883 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2884 SDValue &OutRetAddr, SDValue Chain,
2885 bool IsTailCall, bool Is64Bit,
2886 int FPDiff, SDLoc dl) const {
2887 // Adjust the Return address stack slot.
2888 EVT VT = getPointerTy(DAG.getDataLayout());
2889 OutRetAddr = getReturnAddressFrameIndex(DAG);
2891 // Load the "old" Return address.
2892 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2893 false, false, false, 0);
2894 return SDValue(OutRetAddr.getNode(), 1);
2897 /// Emit a store of the return address if tail call
2898 /// optimization is performed and it is required (FPDiff!=0).
2899 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2900 SDValue Chain, SDValue RetAddrFrIdx,
2901 EVT PtrVT, unsigned SlotSize,
2902 int FPDiff, SDLoc dl) {
2903 // Store the return address to the appropriate stack slot.
2904 if (!FPDiff) return Chain;
2905 // Calculate the new stack slot for the return address.
2906 int NewReturnAddrFI =
2907 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2909 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2910 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2911 MachinePointerInfo::getFixedStack(
2912 DAG.getMachineFunction(), NewReturnAddrFI),
2917 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2918 /// operation of specified width.
2919 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2921 unsigned NumElems = VT.getVectorNumElements();
2922 SmallVector<int, 8> Mask;
2923 Mask.push_back(NumElems);
2924 for (unsigned i = 1; i != NumElems; ++i)
2926 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2930 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2931 SmallVectorImpl<SDValue> &InVals) const {
2932 SelectionDAG &DAG = CLI.DAG;
2934 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2935 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2936 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2937 SDValue Chain = CLI.Chain;
2938 SDValue Callee = CLI.Callee;
2939 CallingConv::ID CallConv = CLI.CallConv;
2940 bool &isTailCall = CLI.IsTailCall;
2941 bool isVarArg = CLI.IsVarArg;
2943 MachineFunction &MF = DAG.getMachineFunction();
2944 bool Is64Bit = Subtarget->is64Bit();
2945 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2946 StructReturnType SR = callIsStructReturn(Outs);
2947 bool IsSibcall = false;
2948 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2949 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2951 if (Attr.getValueAsString() == "true")
2954 if (Subtarget->isPICStyleGOT() &&
2955 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2956 // If we are using a GOT, disable tail calls to external symbols with
2957 // default visibility. Tail calling such a symbol requires using a GOT
2958 // relocation, which forces early binding of the symbol. This breaks code
2959 // that require lazy function symbol resolution. Using musttail or
2960 // GuaranteedTailCallOpt will override this.
2961 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2962 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2963 G->getGlobal()->hasDefaultVisibility()))
2967 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2969 // Force this to be a tail call. The verifier rules are enough to ensure
2970 // that we can lower this successfully without moving the return address
2973 } else if (isTailCall) {
2974 // Check if it's really possible to do a tail call.
2975 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2976 isVarArg, SR != NotStructReturn,
2977 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2978 Outs, OutVals, Ins, DAG);
2980 // Sibcalls are automatically detected tailcalls which do not require
2982 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2989 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2990 "Var args not supported with calling convention fastcc, ghc or hipe");
2992 // Analyze operands of the call, assigning locations to each operand.
2993 SmallVector<CCValAssign, 16> ArgLocs;
2994 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2996 // Allocate shadow area for Win64
2998 CCInfo.AllocateStack(32, 8);
3000 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3002 // Get a count of how many bytes are to be pushed on the stack.
3003 unsigned NumBytes = CCInfo.getNextStackOffset();
3005 // This is a sibcall. The memory operands are available in caller's
3006 // own caller's stack.
3008 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3009 IsTailCallConvention(CallConv))
3010 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3013 if (isTailCall && !IsSibcall && !IsMustTail) {
3014 // Lower arguments at fp - stackoffset + fpdiff.
3015 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3017 FPDiff = NumBytesCallerPushed - NumBytes;
3019 // Set the delta of movement of the returnaddr stackslot.
3020 // But only set if delta is greater than previous delta.
3021 if (FPDiff < X86Info->getTCReturnAddrDelta())
3022 X86Info->setTCReturnAddrDelta(FPDiff);
3025 unsigned NumBytesToPush = NumBytes;
3026 unsigned NumBytesToPop = NumBytes;
3028 // If we have an inalloca argument, all stack space has already been allocated
3029 // for us and be right at the top of the stack. We don't support multiple
3030 // arguments passed in memory when using inalloca.
3031 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3033 if (!ArgLocs.back().isMemLoc())
3034 report_fatal_error("cannot use inalloca attribute on a register "
3036 if (ArgLocs.back().getLocMemOffset() != 0)
3037 report_fatal_error("any parameter with the inalloca attribute must be "
3038 "the only memory argument");
3042 Chain = DAG.getCALLSEQ_START(
3043 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3045 SDValue RetAddrFrIdx;
3046 // Load return address for tail calls.
3047 if (isTailCall && FPDiff)
3048 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3049 Is64Bit, FPDiff, dl);
3051 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3052 SmallVector<SDValue, 8> MemOpChains;
3055 // Walk the register/memloc assignments, inserting copies/loads. In the case
3056 // of tail call optimization arguments are handle later.
3057 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3058 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3059 // Skip inalloca arguments, they have already been written.
3060 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3061 if (Flags.isInAlloca())
3064 CCValAssign &VA = ArgLocs[i];
3065 EVT RegVT = VA.getLocVT();
3066 SDValue Arg = OutVals[i];
3067 bool isByVal = Flags.isByVal();
3069 // Promote the value if needed.
3070 switch (VA.getLocInfo()) {
3071 default: llvm_unreachable("Unknown loc info!");
3072 case CCValAssign::Full: break;
3073 case CCValAssign::SExt:
3074 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3076 case CCValAssign::ZExt:
3077 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3079 case CCValAssign::AExt:
3080 if (Arg.getValueType().isVector() &&
3081 Arg.getValueType().getScalarType() == MVT::i1)
3082 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3083 else if (RegVT.is128BitVector()) {
3084 // Special case: passing MMX values in XMM registers.
3085 Arg = DAG.getBitcast(MVT::i64, Arg);
3086 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3087 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3089 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3091 case CCValAssign::BCvt:
3092 Arg = DAG.getBitcast(RegVT, Arg);
3094 case CCValAssign::Indirect: {
3095 // Store the argument.
3096 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3097 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3098 Chain = DAG.getStore(
3099 Chain, dl, Arg, SpillSlot,
3100 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3107 if (VA.isRegLoc()) {
3108 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3109 if (isVarArg && IsWin64) {
3110 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3111 // shadow reg if callee is a varargs function.
3112 unsigned ShadowReg = 0;
3113 switch (VA.getLocReg()) {
3114 case X86::XMM0: ShadowReg = X86::RCX; break;
3115 case X86::XMM1: ShadowReg = X86::RDX; break;
3116 case X86::XMM2: ShadowReg = X86::R8; break;
3117 case X86::XMM3: ShadowReg = X86::R9; break;
3120 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3122 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3123 assert(VA.isMemLoc());
3124 if (!StackPtr.getNode())
3125 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3126 getPointerTy(DAG.getDataLayout()));
3127 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3128 dl, DAG, VA, Flags));
3132 if (!MemOpChains.empty())
3133 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3135 if (Subtarget->isPICStyleGOT()) {
3136 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3139 RegsToPass.push_back(std::make_pair(
3140 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3141 getPointerTy(DAG.getDataLayout()))));
3143 // If we are tail calling and generating PIC/GOT style code load the
3144 // address of the callee into ECX. The value in ecx is used as target of
3145 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3146 // for tail calls on PIC/GOT architectures. Normally we would just put the
3147 // address of GOT into ebx and then call target@PLT. But for tail calls
3148 // ebx would be restored (since ebx is callee saved) before jumping to the
3151 // Note: The actual moving to ECX is done further down.
3152 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3153 if (G && !G->getGlobal()->hasLocalLinkage() &&
3154 G->getGlobal()->hasDefaultVisibility())
3155 Callee = LowerGlobalAddress(Callee, DAG);
3156 else if (isa<ExternalSymbolSDNode>(Callee))
3157 Callee = LowerExternalSymbol(Callee, DAG);
3161 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3162 // From AMD64 ABI document:
3163 // For calls that may call functions that use varargs or stdargs
3164 // (prototype-less calls or calls to functions containing ellipsis (...) in
3165 // the declaration) %al is used as hidden argument to specify the number
3166 // of SSE registers used. The contents of %al do not need to match exactly
3167 // the number of registers, but must be an ubound on the number of SSE
3168 // registers used and is in the range 0 - 8 inclusive.
3170 // Count the number of XMM registers allocated.
3171 static const MCPhysReg XMMArgRegs[] = {
3172 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3173 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3175 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3176 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3177 && "SSE registers cannot be used when SSE is disabled");
3179 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3180 DAG.getConstant(NumXMMRegs, dl,
3184 if (isVarArg && IsMustTail) {
3185 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3186 for (const auto &F : Forwards) {
3187 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3188 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3192 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3193 // don't need this because the eligibility check rejects calls that require
3194 // shuffling arguments passed in memory.
3195 if (!IsSibcall && isTailCall) {
3196 // Force all the incoming stack arguments to be loaded from the stack
3197 // before any new outgoing arguments are stored to the stack, because the
3198 // outgoing stack slots may alias the incoming argument stack slots, and
3199 // the alias isn't otherwise explicit. This is slightly more conservative
3200 // than necessary, because it means that each store effectively depends
3201 // on every argument instead of just those arguments it would clobber.
3202 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3204 SmallVector<SDValue, 8> MemOpChains2;
3207 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3208 CCValAssign &VA = ArgLocs[i];
3211 assert(VA.isMemLoc());
3212 SDValue Arg = OutVals[i];
3213 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3214 // Skip inalloca arguments. They don't require any work.
3215 if (Flags.isInAlloca())
3217 // Create frame index.
3218 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3219 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3220 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3221 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3223 if (Flags.isByVal()) {
3224 // Copy relative to framepointer.
3225 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3226 if (!StackPtr.getNode())
3227 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3228 getPointerTy(DAG.getDataLayout()));
3229 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3232 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3236 // Store relative to framepointer.
3237 MemOpChains2.push_back(DAG.getStore(
3238 ArgChain, dl, Arg, FIN,
3239 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3244 if (!MemOpChains2.empty())
3245 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3247 // Store the return address to the appropriate stack slot.
3248 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3249 getPointerTy(DAG.getDataLayout()),
3250 RegInfo->getSlotSize(), FPDiff, dl);
3253 // Build a sequence of copy-to-reg nodes chained together with token chain
3254 // and flag operands which copy the outgoing args into registers.
3256 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3257 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3258 RegsToPass[i].second, InFlag);
3259 InFlag = Chain.getValue(1);
3262 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3263 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3264 // In the 64-bit large code model, we have to make all calls
3265 // through a register, since the call instruction's 32-bit
3266 // pc-relative offset may not be large enough to hold the whole
3268 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3269 // If the callee is a GlobalAddress node (quite common, every direct call
3270 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3272 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3274 // We should use extra load for direct calls to dllimported functions in
3276 const GlobalValue *GV = G->getGlobal();
3277 if (!GV->hasDLLImportStorageClass()) {
3278 unsigned char OpFlags = 0;
3279 bool ExtraLoad = false;
3280 unsigned WrapperKind = ISD::DELETED_NODE;
3282 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3283 // external symbols most go through the PLT in PIC mode. If the symbol
3284 // has hidden or protected visibility, or if it is static or local, then
3285 // we don't need to use the PLT - we can directly call it.
3286 if (Subtarget->isTargetELF() &&
3287 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3288 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3289 OpFlags = X86II::MO_PLT;
3290 } else if (Subtarget->isPICStyleStubAny() &&
3291 !GV->isStrongDefinitionForLinker() &&
3292 (!Subtarget->getTargetTriple().isMacOSX() ||
3293 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3294 // PC-relative references to external symbols should go through $stub,
3295 // unless we're building with the leopard linker or later, which
3296 // automatically synthesizes these stubs.
3297 OpFlags = X86II::MO_DARWIN_STUB;
3298 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3299 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3300 // If the function is marked as non-lazy, generate an indirect call
3301 // which loads from the GOT directly. This avoids runtime overhead
3302 // at the cost of eager binding (and one extra byte of encoding).
3303 OpFlags = X86II::MO_GOTPCREL;
3304 WrapperKind = X86ISD::WrapperRIP;
3308 Callee = DAG.getTargetGlobalAddress(
3309 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3311 // Add a wrapper if needed.
3312 if (WrapperKind != ISD::DELETED_NODE)
3313 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3314 getPointerTy(DAG.getDataLayout()), Callee);
3315 // Add extra indirection if needed.
3317 Callee = DAG.getLoad(
3318 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3319 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3322 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3323 unsigned char OpFlags = 0;
3325 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3326 // external symbols should go through the PLT.
3327 if (Subtarget->isTargetELF() &&
3328 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3329 OpFlags = X86II::MO_PLT;
3330 } else if (Subtarget->isPICStyleStubAny() &&
3331 (!Subtarget->getTargetTriple().isMacOSX() ||
3332 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3333 // PC-relative references to external symbols should go through $stub,
3334 // unless we're building with the leopard linker or later, which
3335 // automatically synthesizes these stubs.
3336 OpFlags = X86II::MO_DARWIN_STUB;
3339 Callee = DAG.getTargetExternalSymbol(
3340 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3341 } else if (Subtarget->isTarget64BitILP32() &&
3342 Callee->getValueType(0) == MVT::i32) {
3343 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3344 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3347 // Returns a chain & a flag for retval copy to use.
3348 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3349 SmallVector<SDValue, 8> Ops;
3351 if (!IsSibcall && isTailCall) {
3352 Chain = DAG.getCALLSEQ_END(Chain,
3353 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3354 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3355 InFlag = Chain.getValue(1);
3358 Ops.push_back(Chain);
3359 Ops.push_back(Callee);
3362 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3364 // Add argument registers to the end of the list so that they are known live
3366 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3367 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3368 RegsToPass[i].second.getValueType()));
3370 // Add a register mask operand representing the call-preserved registers.
3371 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3372 assert(Mask && "Missing call preserved mask for calling convention");
3374 // If this is an invoke in a 32-bit function using an MSVC personality, assume
3375 // the function clobbers all registers. If an exception is thrown, the runtime
3376 // will not restore CSRs.
3377 // FIXME: Model this more precisely so that we can register allocate across
3378 // the normal edge and spill and fill across the exceptional edge.
3379 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3380 const Function *CallerFn = MF.getFunction();
3381 EHPersonality Pers =
3382 CallerFn->hasPersonalityFn()
3383 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3384 : EHPersonality::Unknown;
3385 if (isMSVCEHPersonality(Pers))
3386 Mask = RegInfo->getNoPreservedMask();
3389 Ops.push_back(DAG.getRegisterMask(Mask));
3391 if (InFlag.getNode())
3392 Ops.push_back(InFlag);
3396 //// If this is the first return lowered for this function, add the regs
3397 //// to the liveout set for the function.
3398 // This isn't right, although it's probably harmless on x86; liveouts
3399 // should be computed from returns not tail calls. Consider a void
3400 // function making a tail call to a function returning int.
3401 MF.getFrameInfo()->setHasTailCall();
3402 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3405 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3406 InFlag = Chain.getValue(1);
3408 // Create the CALLSEQ_END node.
3409 unsigned NumBytesForCalleeToPop;
3410 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3411 DAG.getTarget().Options.GuaranteedTailCallOpt))
3412 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3413 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3414 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3415 SR == StackStructReturn)
3416 // If this is a call to a struct-return function, the callee
3417 // pops the hidden struct pointer, so we have to push it back.
3418 // This is common for Darwin/X86, Linux & Mingw32 targets.
3419 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3420 NumBytesForCalleeToPop = 4;
3422 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3424 // Returns a flag for retval copy to use.
3426 Chain = DAG.getCALLSEQ_END(Chain,
3427 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3428 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3431 InFlag = Chain.getValue(1);
3434 // Handle result values, copying them out of physregs into vregs that we
3436 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3437 Ins, dl, DAG, InVals);
3440 //===----------------------------------------------------------------------===//
3441 // Fast Calling Convention (tail call) implementation
3442 //===----------------------------------------------------------------------===//
3444 // Like std call, callee cleans arguments, convention except that ECX is
3445 // reserved for storing the tail called function address. Only 2 registers are
3446 // free for argument passing (inreg). Tail call optimization is performed
3448 // * tailcallopt is enabled
3449 // * caller/callee are fastcc
3450 // On X86_64 architecture with GOT-style position independent code only local
3451 // (within module) calls are supported at the moment.
3452 // To keep the stack aligned according to platform abi the function
3453 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3454 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3455 // If a tail called function callee has more arguments than the caller the
3456 // caller needs to make sure that there is room to move the RETADDR to. This is
3457 // achieved by reserving an area the size of the argument delta right after the
3458 // original RETADDR, but before the saved framepointer or the spilled registers
3459 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3471 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3474 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3475 SelectionDAG& DAG) const {
3476 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3477 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3478 unsigned StackAlignment = TFI.getStackAlignment();
3479 uint64_t AlignMask = StackAlignment - 1;
3480 int64_t Offset = StackSize;
3481 unsigned SlotSize = RegInfo->getSlotSize();
3482 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3483 // Number smaller than 12 so just add the difference.
3484 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3486 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3487 Offset = ((~AlignMask) & Offset) + StackAlignment +
3488 (StackAlignment-SlotSize);
3493 /// Return true if the given stack call argument is already available in the
3494 /// same position (relatively) of the caller's incoming argument stack.
3496 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3497 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3498 const X86InstrInfo *TII) {
3499 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3501 if (Arg.getOpcode() == ISD::CopyFromReg) {
3502 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3503 if (!TargetRegisterInfo::isVirtualRegister(VR))
3505 MachineInstr *Def = MRI->getVRegDef(VR);
3508 if (!Flags.isByVal()) {
3509 if (!TII->isLoadFromStackSlot(Def, FI))
3512 unsigned Opcode = Def->getOpcode();
3513 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3514 Opcode == X86::LEA64_32r) &&
3515 Def->getOperand(1).isFI()) {
3516 FI = Def->getOperand(1).getIndex();
3517 Bytes = Flags.getByValSize();
3521 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3522 if (Flags.isByVal())
3523 // ByVal argument is passed in as a pointer but it's now being
3524 // dereferenced. e.g.
3525 // define @foo(%struct.X* %A) {
3526 // tail call @bar(%struct.X* byval %A)
3529 SDValue Ptr = Ld->getBasePtr();
3530 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3533 FI = FINode->getIndex();
3534 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3535 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3536 FI = FINode->getIndex();
3537 Bytes = Flags.getByValSize();
3541 assert(FI != INT_MAX);
3542 if (!MFI->isFixedObjectIndex(FI))
3544 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3547 /// Check whether the call is eligible for tail call optimization. Targets
3548 /// that want to do tail call optimization should implement this function.
3550 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3551 CallingConv::ID CalleeCC,
3553 bool isCalleeStructRet,
3554 bool isCallerStructRet,
3556 const SmallVectorImpl<ISD::OutputArg> &Outs,
3557 const SmallVectorImpl<SDValue> &OutVals,
3558 const SmallVectorImpl<ISD::InputArg> &Ins,
3559 SelectionDAG &DAG) const {
3560 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3563 // If -tailcallopt is specified, make fastcc functions tail-callable.
3564 const MachineFunction &MF = DAG.getMachineFunction();
3565 const Function *CallerF = MF.getFunction();
3567 // If the function return type is x86_fp80 and the callee return type is not,
3568 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3569 // perform a tailcall optimization here.
3570 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3573 CallingConv::ID CallerCC = CallerF->getCallingConv();
3574 bool CCMatch = CallerCC == CalleeCC;
3575 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3576 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3578 // Win64 functions have extra shadow space for argument homing. Don't do the
3579 // sibcall if the caller and callee have mismatched expectations for this
3581 if (IsCalleeWin64 != IsCallerWin64)
3584 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3585 if (IsTailCallConvention(CalleeCC) && CCMatch)
3590 // Look for obvious safe cases to perform tail call optimization that do not
3591 // require ABI changes. This is what gcc calls sibcall.
3593 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3594 // emit a special epilogue.
3595 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3596 if (RegInfo->needsStackRealignment(MF))
3599 // Also avoid sibcall optimization if either caller or callee uses struct
3600 // return semantics.
3601 if (isCalleeStructRet || isCallerStructRet)
3604 // An stdcall/thiscall caller is expected to clean up its arguments; the
3605 // callee isn't going to do that.
3606 // FIXME: this is more restrictive than needed. We could produce a tailcall
3607 // when the stack adjustment matches. For example, with a thiscall that takes
3608 // only one argument.
3609 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3610 CallerCC == CallingConv::X86_ThisCall))
3613 // Do not sibcall optimize vararg calls unless all arguments are passed via
3615 if (isVarArg && !Outs.empty()) {
3617 // Optimizing for varargs on Win64 is unlikely to be safe without
3618 // additional testing.
3619 if (IsCalleeWin64 || IsCallerWin64)
3622 SmallVector<CCValAssign, 16> ArgLocs;
3623 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3626 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3627 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3628 if (!ArgLocs[i].isRegLoc())
3632 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3633 // stack. Therefore, if it's not used by the call it is not safe to optimize
3634 // this into a sibcall.
3635 bool Unused = false;
3636 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3643 SmallVector<CCValAssign, 16> RVLocs;
3644 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3646 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3647 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3648 CCValAssign &VA = RVLocs[i];
3649 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3654 // If the calling conventions do not match, then we'd better make sure the
3655 // results are returned in the same way as what the caller expects.
3657 SmallVector<CCValAssign, 16> RVLocs1;
3658 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3660 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3662 SmallVector<CCValAssign, 16> RVLocs2;
3663 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3665 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3667 if (RVLocs1.size() != RVLocs2.size())
3669 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3670 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3672 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3674 if (RVLocs1[i].isRegLoc()) {
3675 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3678 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3684 // If the callee takes no arguments then go on to check the results of the
3686 if (!Outs.empty()) {
3687 // Check if stack adjustment is needed. For now, do not do this if any
3688 // argument is passed on the stack.
3689 SmallVector<CCValAssign, 16> ArgLocs;
3690 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3693 // Allocate shadow area for Win64
3695 CCInfo.AllocateStack(32, 8);
3697 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3698 if (CCInfo.getNextStackOffset()) {
3699 MachineFunction &MF = DAG.getMachineFunction();
3700 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3703 // Check if the arguments are already laid out in the right way as
3704 // the caller's fixed stack objects.
3705 MachineFrameInfo *MFI = MF.getFrameInfo();
3706 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3707 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3708 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3709 CCValAssign &VA = ArgLocs[i];
3710 SDValue Arg = OutVals[i];
3711 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3712 if (VA.getLocInfo() == CCValAssign::Indirect)
3714 if (!VA.isRegLoc()) {
3715 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3722 // If the tailcall address may be in a register, then make sure it's
3723 // possible to register allocate for it. In 32-bit, the call address can
3724 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3725 // callee-saved registers are restored. These happen to be the same
3726 // registers used to pass 'inreg' arguments so watch out for those.
3727 if (!Subtarget->is64Bit() &&
3728 ((!isa<GlobalAddressSDNode>(Callee) &&
3729 !isa<ExternalSymbolSDNode>(Callee)) ||
3730 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3731 unsigned NumInRegs = 0;
3732 // In PIC we need an extra register to formulate the address computation
3734 unsigned MaxInRegs =
3735 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3737 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3738 CCValAssign &VA = ArgLocs[i];
3741 unsigned Reg = VA.getLocReg();
3744 case X86::EAX: case X86::EDX: case X86::ECX:
3745 if (++NumInRegs == MaxInRegs)
3757 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3758 const TargetLibraryInfo *libInfo) const {
3759 return X86::createFastISel(funcInfo, libInfo);
3762 //===----------------------------------------------------------------------===//
3763 // Other Lowering Hooks
3764 //===----------------------------------------------------------------------===//
3766 static bool MayFoldLoad(SDValue Op) {
3767 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3770 static bool MayFoldIntoStore(SDValue Op) {
3771 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3774 static bool isTargetShuffle(unsigned Opcode) {
3776 default: return false;
3777 case X86ISD::BLENDI:
3778 case X86ISD::PSHUFB:
3779 case X86ISD::PSHUFD:
3780 case X86ISD::PSHUFHW:
3781 case X86ISD::PSHUFLW:
3783 case X86ISD::PALIGNR:
3784 case X86ISD::MOVLHPS:
3785 case X86ISD::MOVLHPD:
3786 case X86ISD::MOVHLPS:
3787 case X86ISD::MOVLPS:
3788 case X86ISD::MOVLPD:
3789 case X86ISD::MOVSHDUP:
3790 case X86ISD::MOVSLDUP:
3791 case X86ISD::MOVDDUP:
3794 case X86ISD::UNPCKL:
3795 case X86ISD::UNPCKH:
3796 case X86ISD::VPERMILPI:
3797 case X86ISD::VPERM2X128:
3798 case X86ISD::VPERMI:
3799 case X86ISD::VPERMV:
3800 case X86ISD::VPERMV3:
3805 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3806 SDValue V1, unsigned TargetMask,
3807 SelectionDAG &DAG) {
3809 default: llvm_unreachable("Unknown x86 shuffle node");
3810 case X86ISD::PSHUFD:
3811 case X86ISD::PSHUFHW:
3812 case X86ISD::PSHUFLW:
3813 case X86ISD::VPERMILPI:
3814 case X86ISD::VPERMI:
3815 return DAG.getNode(Opc, dl, VT, V1,
3816 DAG.getConstant(TargetMask, dl, MVT::i8));
3820 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3821 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3823 default: llvm_unreachable("Unknown x86 shuffle node");
3824 case X86ISD::MOVLHPS:
3825 case X86ISD::MOVLHPD:
3826 case X86ISD::MOVHLPS:
3827 case X86ISD::MOVLPS:
3828 case X86ISD::MOVLPD:
3831 case X86ISD::UNPCKL:
3832 case X86ISD::UNPCKH:
3833 return DAG.getNode(Opc, dl, VT, V1, V2);
3837 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3838 MachineFunction &MF = DAG.getMachineFunction();
3839 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3840 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3841 int ReturnAddrIndex = FuncInfo->getRAIndex();
3843 if (ReturnAddrIndex == 0) {
3844 // Set up a frame object for the return address.
3845 unsigned SlotSize = RegInfo->getSlotSize();
3846 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3849 FuncInfo->setRAIndex(ReturnAddrIndex);
3852 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3855 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3856 bool hasSymbolicDisplacement) {
3857 // Offset should fit into 32 bit immediate field.
3858 if (!isInt<32>(Offset))
3861 // If we don't have a symbolic displacement - we don't have any extra
3863 if (!hasSymbolicDisplacement)
3866 // FIXME: Some tweaks might be needed for medium code model.
3867 if (M != CodeModel::Small && M != CodeModel::Kernel)
3870 // For small code model we assume that latest object is 16MB before end of 31
3871 // bits boundary. We may also accept pretty large negative constants knowing
3872 // that all objects are in the positive half of address space.
3873 if (M == CodeModel::Small && Offset < 16*1024*1024)
3876 // For kernel code model we know that all object resist in the negative half
3877 // of 32bits address space. We may not accept negative offsets, since they may
3878 // be just off and we may accept pretty large positive ones.
3879 if (M == CodeModel::Kernel && Offset >= 0)
3885 /// Determines whether the callee is required to pop its own arguments.
3886 /// Callee pop is necessary to support tail calls.
3887 bool X86::isCalleePop(CallingConv::ID CallingConv,
3888 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3889 switch (CallingConv) {
3892 case CallingConv::X86_StdCall:
3893 case CallingConv::X86_FastCall:
3894 case CallingConv::X86_ThisCall:
3896 case CallingConv::Fast:
3897 case CallingConv::GHC:
3898 case CallingConv::HiPE:
3905 /// \brief Return true if the condition is an unsigned comparison operation.
3906 static bool isX86CCUnsigned(unsigned X86CC) {
3908 default: llvm_unreachable("Invalid integer condition!");
3909 case X86::COND_E: return true;
3910 case X86::COND_G: return false;
3911 case X86::COND_GE: return false;
3912 case X86::COND_L: return false;
3913 case X86::COND_LE: return false;
3914 case X86::COND_NE: return true;
3915 case X86::COND_B: return true;
3916 case X86::COND_A: return true;
3917 case X86::COND_BE: return true;
3918 case X86::COND_AE: return true;
3920 llvm_unreachable("covered switch fell through?!");
3923 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3924 /// condition code, returning the condition code and the LHS/RHS of the
3925 /// comparison to make.
3926 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3927 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3929 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3930 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3931 // X > -1 -> X == 0, jump !sign.
3932 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3933 return X86::COND_NS;
3935 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3936 // X < 0 -> X == 0, jump on sign.
3939 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3941 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3942 return X86::COND_LE;
3946 switch (SetCCOpcode) {
3947 default: llvm_unreachable("Invalid integer condition!");
3948 case ISD::SETEQ: return X86::COND_E;
3949 case ISD::SETGT: return X86::COND_G;
3950 case ISD::SETGE: return X86::COND_GE;
3951 case ISD::SETLT: return X86::COND_L;
3952 case ISD::SETLE: return X86::COND_LE;
3953 case ISD::SETNE: return X86::COND_NE;
3954 case ISD::SETULT: return X86::COND_B;
3955 case ISD::SETUGT: return X86::COND_A;
3956 case ISD::SETULE: return X86::COND_BE;
3957 case ISD::SETUGE: return X86::COND_AE;
3961 // First determine if it is required or is profitable to flip the operands.
3963 // If LHS is a foldable load, but RHS is not, flip the condition.
3964 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3965 !ISD::isNON_EXTLoad(RHS.getNode())) {
3966 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3967 std::swap(LHS, RHS);
3970 switch (SetCCOpcode) {
3976 std::swap(LHS, RHS);
3980 // On a floating point condition, the flags are set as follows:
3982 // 0 | 0 | 0 | X > Y
3983 // 0 | 0 | 1 | X < Y
3984 // 1 | 0 | 0 | X == Y
3985 // 1 | 1 | 1 | unordered
3986 switch (SetCCOpcode) {
3987 default: llvm_unreachable("Condcode should be pre-legalized away");
3989 case ISD::SETEQ: return X86::COND_E;
3990 case ISD::SETOLT: // flipped
3992 case ISD::SETGT: return X86::COND_A;
3993 case ISD::SETOLE: // flipped
3995 case ISD::SETGE: return X86::COND_AE;
3996 case ISD::SETUGT: // flipped
3998 case ISD::SETLT: return X86::COND_B;
3999 case ISD::SETUGE: // flipped
4001 case ISD::SETLE: return X86::COND_BE;
4003 case ISD::SETNE: return X86::COND_NE;
4004 case ISD::SETUO: return X86::COND_P;
4005 case ISD::SETO: return X86::COND_NP;
4007 case ISD::SETUNE: return X86::COND_INVALID;
4011 /// Is there a floating point cmov for the specific X86 condition code?
4012 /// Current x86 isa includes the following FP cmov instructions:
4013 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4014 static bool hasFPCMov(unsigned X86CC) {
4030 /// Returns true if the target can instruction select the
4031 /// specified FP immediate natively. If false, the legalizer will
4032 /// materialize the FP immediate as a load from a constant pool.
4033 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4034 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4035 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4041 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4042 ISD::LoadExtType ExtTy,
4044 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4045 // relocation target a movq or addq instruction: don't let the load shrink.
4046 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4047 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4048 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4049 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4053 /// \brief Returns true if it is beneficial to convert a load of a constant
4054 /// to just the constant itself.
4055 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4057 assert(Ty->isIntegerTy());
4059 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4060 if (BitSize == 0 || BitSize > 64)
4065 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4066 unsigned Index) const {
4067 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4070 return (Index == 0 || Index == ResVT.getVectorNumElements());
4073 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4074 // Speculate cttz only if we can directly use TZCNT.
4075 return Subtarget->hasBMI();
4078 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4079 // Speculate ctlz only if we can directly use LZCNT.
4080 return Subtarget->hasLZCNT();
4083 /// Return true if every element in Mask, beginning
4084 /// from position Pos and ending in Pos+Size is undef.
4085 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4086 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4092 /// Return true if Val is undef or if its value falls within the
4093 /// specified range (L, H].
4094 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4095 return (Val < 0) || (Val >= Low && Val < Hi);
4098 /// Val is either less than zero (undef) or equal to the specified value.
4099 static bool isUndefOrEqual(int Val, int CmpVal) {
4100 return (Val < 0 || Val == CmpVal);
4103 /// Return true if every element in Mask, beginning
4104 /// from position Pos and ending in Pos+Size, falls within the specified
4105 /// sequential range (Low, Low+Size]. or is undef.
4106 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4107 unsigned Pos, unsigned Size, int Low) {
4108 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4109 if (!isUndefOrEqual(Mask[i], Low))
4114 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4115 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4116 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4117 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4118 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4121 // The index should be aligned on a vecWidth-bit boundary.
4123 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4125 MVT VT = N->getSimpleValueType(0);
4126 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4127 bool Result = (Index * ElSize) % vecWidth == 0;
4132 /// Return true if the specified INSERT_SUBVECTOR
4133 /// operand specifies a subvector insert that is suitable for input to
4134 /// insertion of 128 or 256-bit subvectors
4135 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4136 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4137 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4139 // The index should be aligned on a vecWidth-bit boundary.
4141 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4143 MVT VT = N->getSimpleValueType(0);
4144 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4145 bool Result = (Index * ElSize) % vecWidth == 0;
4150 bool X86::isVINSERT128Index(SDNode *N) {
4151 return isVINSERTIndex(N, 128);
4154 bool X86::isVINSERT256Index(SDNode *N) {
4155 return isVINSERTIndex(N, 256);
4158 bool X86::isVEXTRACT128Index(SDNode *N) {
4159 return isVEXTRACTIndex(N, 128);
4162 bool X86::isVEXTRACT256Index(SDNode *N) {
4163 return isVEXTRACTIndex(N, 256);
4166 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4167 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4168 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4169 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4172 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4174 MVT VecVT = N->getOperand(0).getSimpleValueType();
4175 MVT ElVT = VecVT.getVectorElementType();
4177 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4178 return Index / NumElemsPerChunk;
4181 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4182 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4183 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4184 llvm_unreachable("Illegal insert subvector for VINSERT");
4187 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4189 MVT VecVT = N->getSimpleValueType(0);
4190 MVT ElVT = VecVT.getVectorElementType();
4192 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4193 return Index / NumElemsPerChunk;
4196 /// Return the appropriate immediate to extract the specified
4197 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4198 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4199 return getExtractVEXTRACTImmediate(N, 128);
4202 /// Return the appropriate immediate to extract the specified
4203 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4204 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4205 return getExtractVEXTRACTImmediate(N, 256);
4208 /// Return the appropriate immediate to insert at the specified
4209 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4210 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4211 return getInsertVINSERTImmediate(N, 128);
4214 /// Return the appropriate immediate to insert at the specified
4215 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4216 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4217 return getInsertVINSERTImmediate(N, 256);
4220 /// Returns true if Elt is a constant integer zero
4221 static bool isZero(SDValue V) {
4222 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4223 return C && C->isNullValue();
4226 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4227 bool X86::isZeroNode(SDValue Elt) {
4230 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4231 return CFP->getValueAPF().isPosZero();
4235 /// Returns a vector of specified type with all zero elements.
4236 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4237 SelectionDAG &DAG, SDLoc dl) {
4238 assert(VT.isVector() && "Expected a vector type");
4240 // Always build SSE zero vectors as <4 x i32> bitcasted
4241 // to their dest type. This ensures they get CSE'd.
4243 if (VT.is128BitVector()) { // SSE
4244 if (Subtarget->hasSSE2()) { // SSE2
4245 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4246 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4248 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4249 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4251 } else if (VT.is256BitVector()) { // AVX
4252 if (Subtarget->hasInt256()) { // AVX2
4253 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4254 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4255 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4257 // 256-bit logic and arithmetic instructions in AVX are all
4258 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4259 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4260 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4263 } else if (VT.is512BitVector()) { // AVX-512
4264 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4265 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4266 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4267 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4268 } else if (VT.getScalarType() == MVT::i1) {
4270 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4271 && "Unexpected vector type");
4272 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4273 && "Unexpected vector type");
4274 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4275 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4276 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4278 llvm_unreachable("Unexpected vector type");
4280 return DAG.getBitcast(VT, Vec);
4283 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4284 SelectionDAG &DAG, SDLoc dl,
4285 unsigned vectorWidth) {
4286 assert((vectorWidth == 128 || vectorWidth == 256) &&
4287 "Unsupported vector width");
4288 EVT VT = Vec.getValueType();
4289 EVT ElVT = VT.getVectorElementType();
4290 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4291 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4292 VT.getVectorNumElements()/Factor);
4294 // Extract from UNDEF is UNDEF.
4295 if (Vec.getOpcode() == ISD::UNDEF)
4296 return DAG.getUNDEF(ResultVT);
4298 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4299 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4301 // This is the index of the first element of the vectorWidth-bit chunk
4303 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4306 // If the input is a buildvector just emit a smaller one.
4307 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4308 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4309 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4312 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4313 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4316 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4317 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4318 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4319 /// instructions or a simple subregister reference. Idx is an index in the
4320 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4321 /// lowering EXTRACT_VECTOR_ELT operations easier.
4322 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4323 SelectionDAG &DAG, SDLoc dl) {
4324 assert((Vec.getValueType().is256BitVector() ||
4325 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4326 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4329 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4330 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4331 SelectionDAG &DAG, SDLoc dl) {
4332 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4333 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4336 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4337 unsigned IdxVal, SelectionDAG &DAG,
4338 SDLoc dl, unsigned vectorWidth) {
4339 assert((vectorWidth == 128 || vectorWidth == 256) &&
4340 "Unsupported vector width");
4341 // Inserting UNDEF is Result
4342 if (Vec.getOpcode() == ISD::UNDEF)
4344 EVT VT = Vec.getValueType();
4345 EVT ElVT = VT.getVectorElementType();
4346 EVT ResultVT = Result.getValueType();
4348 // Insert the relevant vectorWidth bits.
4349 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4351 // This is the index of the first element of the vectorWidth-bit chunk
4353 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4356 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4357 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4360 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4361 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4362 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4363 /// simple superregister reference. Idx is an index in the 128 bits
4364 /// we want. It need not be aligned to a 128-bit boundary. That makes
4365 /// lowering INSERT_VECTOR_ELT operations easier.
4366 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4367 SelectionDAG &DAG, SDLoc dl) {
4368 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4370 // For insertion into the zero index (low half) of a 256-bit vector, it is
4371 // more efficient to generate a blend with immediate instead of an insert*128.
4372 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4373 // extend the subvector to the size of the result vector. Make sure that
4374 // we are not recursing on that node by checking for undef here.
4375 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4376 Result.getOpcode() != ISD::UNDEF) {
4377 EVT ResultVT = Result.getValueType();
4378 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4379 SDValue Undef = DAG.getUNDEF(ResultVT);
4380 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4383 // The blend instruction, and therefore its mask, depend on the data type.
4384 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4385 if (ScalarType.isFloatingPoint()) {
4386 // Choose either vblendps (float) or vblendpd (double).
4387 unsigned ScalarSize = ScalarType.getSizeInBits();
4388 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4389 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4390 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4391 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4394 const X86Subtarget &Subtarget =
4395 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4397 // AVX2 is needed for 256-bit integer blend support.
4398 // Integers must be cast to 32-bit because there is only vpblendd;
4399 // vpblendw can't be used for this because it has a handicapped mask.
4401 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4402 // is still more efficient than using the wrong domain vinsertf128 that
4403 // will be created by InsertSubVector().
4404 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4406 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4407 Vec256 = DAG.getBitcast(CastVT, Vec256);
4408 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4409 return DAG.getBitcast(ResultVT, Vec256);
4412 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4415 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4416 SelectionDAG &DAG, SDLoc dl) {
4417 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4418 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4421 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4422 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4423 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4424 /// large BUILD_VECTORS.
4425 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4426 unsigned NumElems, SelectionDAG &DAG,
4428 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4429 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4432 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4433 unsigned NumElems, SelectionDAG &DAG,
4435 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4436 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4439 /// Returns a vector of specified type with all bits set.
4440 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4441 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4442 /// Then bitcast to their original type, ensuring they get CSE'd.
4443 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4445 assert(VT.isVector() && "Expected a vector type");
4447 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4449 if (VT.is256BitVector()) {
4450 if (HasInt256) { // AVX2
4451 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4452 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4454 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4455 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4457 } else if (VT.is128BitVector()) {
4458 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4460 llvm_unreachable("Unexpected vector type");
4462 return DAG.getBitcast(VT, Vec);
4465 /// Returns a vector_shuffle node for an unpackl operation.
4466 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4468 unsigned NumElems = VT.getVectorNumElements();
4469 SmallVector<int, 8> Mask;
4470 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4472 Mask.push_back(i + NumElems);
4474 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4477 /// Returns a vector_shuffle node for an unpackh operation.
4478 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4480 unsigned NumElems = VT.getVectorNumElements();
4481 SmallVector<int, 8> Mask;
4482 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4483 Mask.push_back(i + Half);
4484 Mask.push_back(i + NumElems + Half);
4486 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4489 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4490 /// This produces a shuffle where the low element of V2 is swizzled into the
4491 /// zero/undef vector, landing at element Idx.
4492 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4493 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4495 const X86Subtarget *Subtarget,
4496 SelectionDAG &DAG) {
4497 MVT VT = V2.getSimpleValueType();
4499 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4500 unsigned NumElems = VT.getVectorNumElements();
4501 SmallVector<int, 16> MaskVec;
4502 for (unsigned i = 0; i != NumElems; ++i)
4503 // If this is the insertion idx, put the low elt of V2 here.
4504 MaskVec.push_back(i == Idx ? NumElems : i);
4505 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4508 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4509 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4510 /// uses one source. Note that this will set IsUnary for shuffles which use a
4511 /// single input multiple times, and in those cases it will
4512 /// adjust the mask to only have indices within that single input.
4513 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4514 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4515 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4516 unsigned NumElems = VT.getVectorNumElements();
4520 bool IsFakeUnary = false;
4521 switch(N->getOpcode()) {
4522 case X86ISD::BLENDI:
4523 ImmN = N->getOperand(N->getNumOperands()-1);
4524 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4527 ImmN = N->getOperand(N->getNumOperands()-1);
4528 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4529 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4531 case X86ISD::UNPCKH:
4532 DecodeUNPCKHMask(VT, Mask);
4533 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4535 case X86ISD::UNPCKL:
4536 DecodeUNPCKLMask(VT, Mask);
4537 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4539 case X86ISD::MOVHLPS:
4540 DecodeMOVHLPSMask(NumElems, Mask);
4541 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4543 case X86ISD::MOVLHPS:
4544 DecodeMOVLHPSMask(NumElems, Mask);
4545 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4547 case X86ISD::PALIGNR:
4548 ImmN = N->getOperand(N->getNumOperands()-1);
4549 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4551 case X86ISD::PSHUFD:
4552 case X86ISD::VPERMILPI:
4553 ImmN = N->getOperand(N->getNumOperands()-1);
4554 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4557 case X86ISD::PSHUFHW:
4558 ImmN = N->getOperand(N->getNumOperands()-1);
4559 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4562 case X86ISD::PSHUFLW:
4563 ImmN = N->getOperand(N->getNumOperands()-1);
4564 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4567 case X86ISD::PSHUFB: {
4569 SDValue MaskNode = N->getOperand(1);
4570 while (MaskNode->getOpcode() == ISD::BITCAST)
4571 MaskNode = MaskNode->getOperand(0);
4573 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4574 // If we have a build-vector, then things are easy.
4575 EVT VT = MaskNode.getValueType();
4576 assert(VT.isVector() &&
4577 "Can't produce a non-vector with a build_vector!");
4578 if (!VT.isInteger())
4581 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4583 SmallVector<uint64_t, 32> RawMask;
4584 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4585 SDValue Op = MaskNode->getOperand(i);
4586 if (Op->getOpcode() == ISD::UNDEF) {
4587 RawMask.push_back((uint64_t)SM_SentinelUndef);
4590 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4593 APInt MaskElement = CN->getAPIntValue();
4595 // We now have to decode the element which could be any integer size and
4596 // extract each byte of it.
4597 for (int j = 0; j < NumBytesPerElement; ++j) {
4598 // Note that this is x86 and so always little endian: the low byte is
4599 // the first byte of the mask.
4600 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4601 MaskElement = MaskElement.lshr(8);
4604 DecodePSHUFBMask(RawMask, Mask);
4608 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4612 SDValue Ptr = MaskLoad->getBasePtr();
4613 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4614 Ptr->getOpcode() == X86ISD::WrapperRIP)
4615 Ptr = Ptr->getOperand(0);
4617 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4618 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4621 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4622 DecodePSHUFBMask(C, Mask);
4630 case X86ISD::VPERMI:
4631 ImmN = N->getOperand(N->getNumOperands()-1);
4632 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4637 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4639 case X86ISD::VPERM2X128:
4640 ImmN = N->getOperand(N->getNumOperands()-1);
4641 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4642 if (Mask.empty()) return false;
4643 // Mask only contains negative index if an element is zero.
4644 if (std::any_of(Mask.begin(), Mask.end(),
4645 [](int M){ return M == SM_SentinelZero; }))
4648 case X86ISD::MOVSLDUP:
4649 DecodeMOVSLDUPMask(VT, Mask);
4652 case X86ISD::MOVSHDUP:
4653 DecodeMOVSHDUPMask(VT, Mask);
4656 case X86ISD::MOVDDUP:
4657 DecodeMOVDDUPMask(VT, Mask);
4660 case X86ISD::MOVLHPD:
4661 case X86ISD::MOVLPD:
4662 case X86ISD::MOVLPS:
4663 // Not yet implemented
4665 case X86ISD::VPERMV: {
4667 SDValue MaskNode = N->getOperand(0);
4668 while (MaskNode->getOpcode() == ISD::BITCAST)
4669 MaskNode = MaskNode->getOperand(0);
4671 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4672 SmallVector<uint64_t, 32> RawMask;
4673 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4674 // If we have a build-vector, then things are easy.
4675 assert(MaskNode.getValueType().isInteger() &&
4676 MaskNode.getValueType().getVectorNumElements() ==
4677 VT.getVectorNumElements());
4679 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4680 SDValue Op = MaskNode->getOperand(i);
4681 if (Op->getOpcode() == ISD::UNDEF)
4682 RawMask.push_back((uint64_t)SM_SentinelUndef);
4683 else if (isa<ConstantSDNode>(Op)) {
4684 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4685 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4689 DecodeVPERMVMask(RawMask, Mask);
4692 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4693 unsigned NumEltsInMask = MaskNode->getNumOperands();
4694 MaskNode = MaskNode->getOperand(0);
4695 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4697 APInt MaskEltValue = CN->getAPIntValue();
4698 for (unsigned i = 0; i < NumEltsInMask; ++i)
4699 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4700 DecodeVPERMVMask(RawMask, Mask);
4703 // It may be a scalar load
4706 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4710 SDValue Ptr = MaskLoad->getBasePtr();
4711 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4712 Ptr->getOpcode() == X86ISD::WrapperRIP)
4713 Ptr = Ptr->getOperand(0);
4715 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4716 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4719 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4721 DecodeVPERMVMask(C, VT, Mask);
4728 case X86ISD::VPERMV3: {
4730 SDValue MaskNode = N->getOperand(1);
4731 while (MaskNode->getOpcode() == ISD::BITCAST)
4732 MaskNode = MaskNode->getOperand(1);
4734 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4735 // If we have a build-vector, then things are easy.
4736 assert(MaskNode.getValueType().isInteger() &&
4737 MaskNode.getValueType().getVectorNumElements() ==
4738 VT.getVectorNumElements());
4740 SmallVector<uint64_t, 32> RawMask;
4741 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4743 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4744 SDValue Op = MaskNode->getOperand(i);
4745 if (Op->getOpcode() == ISD::UNDEF)
4746 RawMask.push_back((uint64_t)SM_SentinelUndef);
4748 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4751 APInt MaskElement = CN->getAPIntValue();
4752 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4755 DecodeVPERMV3Mask(RawMask, Mask);
4759 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4763 SDValue Ptr = MaskLoad->getBasePtr();
4764 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4765 Ptr->getOpcode() == X86ISD::WrapperRIP)
4766 Ptr = Ptr->getOperand(0);
4768 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4769 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4772 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4774 DecodeVPERMV3Mask(C, VT, Mask);
4781 default: llvm_unreachable("unknown target shuffle node");
4784 // If we have a fake unary shuffle, the shuffle mask is spread across two
4785 // inputs that are actually the same node. Re-map the mask to always point
4786 // into the first input.
4789 if (M >= (int)Mask.size())
4795 /// Returns the scalar element that will make up the ith
4796 /// element of the result of the vector shuffle.
4797 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4800 return SDValue(); // Limit search depth.
4802 SDValue V = SDValue(N, 0);
4803 EVT VT = V.getValueType();
4804 unsigned Opcode = V.getOpcode();
4806 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4807 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4808 int Elt = SV->getMaskElt(Index);
4811 return DAG.getUNDEF(VT.getVectorElementType());
4813 unsigned NumElems = VT.getVectorNumElements();
4814 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4815 : SV->getOperand(1);
4816 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4819 // Recurse into target specific vector shuffles to find scalars.
4820 if (isTargetShuffle(Opcode)) {
4821 MVT ShufVT = V.getSimpleValueType();
4822 unsigned NumElems = ShufVT.getVectorNumElements();
4823 SmallVector<int, 16> ShuffleMask;
4826 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4829 int Elt = ShuffleMask[Index];
4831 return DAG.getUNDEF(ShufVT.getVectorElementType());
4833 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4835 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4839 // Actual nodes that may contain scalar elements
4840 if (Opcode == ISD::BITCAST) {
4841 V = V.getOperand(0);
4842 EVT SrcVT = V.getValueType();
4843 unsigned NumElems = VT.getVectorNumElements();
4845 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4849 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4850 return (Index == 0) ? V.getOperand(0)
4851 : DAG.getUNDEF(VT.getVectorElementType());
4853 if (V.getOpcode() == ISD::BUILD_VECTOR)
4854 return V.getOperand(Index);
4859 /// Custom lower build_vector of v16i8.
4860 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4861 unsigned NumNonZero, unsigned NumZero,
4863 const X86Subtarget* Subtarget,
4864 const TargetLowering &TLI) {
4872 // SSE4.1 - use PINSRB to insert each byte directly.
4873 if (Subtarget->hasSSE41()) {
4874 for (unsigned i = 0; i < 16; ++i) {
4875 bool isNonZero = (NonZeros & (1 << i)) != 0;
4879 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4881 V = DAG.getUNDEF(MVT::v16i8);
4884 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4885 MVT::v16i8, V, Op.getOperand(i),
4886 DAG.getIntPtrConstant(i, dl));
4893 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4894 for (unsigned i = 0; i < 16; ++i) {
4895 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4896 if (ThisIsNonZero && First) {
4898 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4900 V = DAG.getUNDEF(MVT::v8i16);
4905 SDValue ThisElt, LastElt;
4906 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4907 if (LastIsNonZero) {
4908 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4909 MVT::i16, Op.getOperand(i-1));
4911 if (ThisIsNonZero) {
4912 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4913 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4914 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4916 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4920 if (ThisElt.getNode())
4921 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4922 DAG.getIntPtrConstant(i/2, dl));
4926 return DAG.getBitcast(MVT::v16i8, V);
4929 /// Custom lower build_vector of v8i16.
4930 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4931 unsigned NumNonZero, unsigned NumZero,
4933 const X86Subtarget* Subtarget,
4934 const TargetLowering &TLI) {
4941 for (unsigned i = 0; i < 8; ++i) {
4942 bool isNonZero = (NonZeros & (1 << i)) != 0;
4946 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4948 V = DAG.getUNDEF(MVT::v8i16);
4951 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4952 MVT::v8i16, V, Op.getOperand(i),
4953 DAG.getIntPtrConstant(i, dl));
4960 /// Custom lower build_vector of v4i32 or v4f32.
4961 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4962 const X86Subtarget *Subtarget,
4963 const TargetLowering &TLI) {
4964 // Find all zeroable elements.
4965 std::bitset<4> Zeroable;
4966 for (int i=0; i < 4; ++i) {
4967 SDValue Elt = Op->getOperand(i);
4968 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4970 assert(Zeroable.size() - Zeroable.count() > 1 &&
4971 "We expect at least two non-zero elements!");
4973 // We only know how to deal with build_vector nodes where elements are either
4974 // zeroable or extract_vector_elt with constant index.
4975 SDValue FirstNonZero;
4976 unsigned FirstNonZeroIdx;
4977 for (unsigned i=0; i < 4; ++i) {
4980 SDValue Elt = Op->getOperand(i);
4981 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4982 !isa<ConstantSDNode>(Elt.getOperand(1)))
4984 // Make sure that this node is extracting from a 128-bit vector.
4985 MVT VT = Elt.getOperand(0).getSimpleValueType();
4986 if (!VT.is128BitVector())
4988 if (!FirstNonZero.getNode()) {
4990 FirstNonZeroIdx = i;
4994 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4995 SDValue V1 = FirstNonZero.getOperand(0);
4996 MVT VT = V1.getSimpleValueType();
4998 // See if this build_vector can be lowered as a blend with zero.
5000 unsigned EltMaskIdx, EltIdx;
5002 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5003 if (Zeroable[EltIdx]) {
5004 // The zero vector will be on the right hand side.
5005 Mask[EltIdx] = EltIdx+4;
5009 Elt = Op->getOperand(EltIdx);
5010 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5011 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5012 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5014 Mask[EltIdx] = EltIdx;
5018 // Let the shuffle legalizer deal with blend operations.
5019 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5020 if (V1.getSimpleValueType() != VT)
5021 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5022 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5025 // See if we can lower this build_vector to a INSERTPS.
5026 if (!Subtarget->hasSSE41())
5029 SDValue V2 = Elt.getOperand(0);
5030 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5033 bool CanFold = true;
5034 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5038 SDValue Current = Op->getOperand(i);
5039 SDValue SrcVector = Current->getOperand(0);
5042 CanFold = SrcVector == V1 &&
5043 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5049 assert(V1.getNode() && "Expected at least two non-zero elements!");
5050 if (V1.getSimpleValueType() != MVT::v4f32)
5051 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5052 if (V2.getSimpleValueType() != MVT::v4f32)
5053 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5055 // Ok, we can emit an INSERTPS instruction.
5056 unsigned ZMask = Zeroable.to_ulong();
5058 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5059 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5061 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5062 DAG.getIntPtrConstant(InsertPSMask, DL));
5063 return DAG.getBitcast(VT, Result);
5066 /// Return a vector logical shift node.
5067 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5068 unsigned NumBits, SelectionDAG &DAG,
5069 const TargetLowering &TLI, SDLoc dl) {
5070 assert(VT.is128BitVector() && "Unknown type for VShift");
5071 MVT ShVT = MVT::v2i64;
5072 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5073 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5074 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5075 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5076 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5077 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5081 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5083 // Check if the scalar load can be widened into a vector load. And if
5084 // the address is "base + cst" see if the cst can be "absorbed" into
5085 // the shuffle mask.
5086 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5087 SDValue Ptr = LD->getBasePtr();
5088 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5090 EVT PVT = LD->getValueType(0);
5091 if (PVT != MVT::i32 && PVT != MVT::f32)
5096 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5097 FI = FINode->getIndex();
5099 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5100 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5101 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5102 Offset = Ptr.getConstantOperandVal(1);
5103 Ptr = Ptr.getOperand(0);
5108 // FIXME: 256-bit vector instructions don't require a strict alignment,
5109 // improve this code to support it better.
5110 unsigned RequiredAlign = VT.getSizeInBits()/8;
5111 SDValue Chain = LD->getChain();
5112 // Make sure the stack object alignment is at least 16 or 32.
5113 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5114 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5115 if (MFI->isFixedObjectIndex(FI)) {
5116 // Can't change the alignment. FIXME: It's possible to compute
5117 // the exact stack offset and reference FI + adjust offset instead.
5118 // If someone *really* cares about this. That's the way to implement it.
5121 MFI->setObjectAlignment(FI, RequiredAlign);
5125 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5126 // Ptr + (Offset & ~15).
5129 if ((Offset % RequiredAlign) & 3)
5131 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5134 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5135 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5138 int EltNo = (Offset - StartOffset) >> 2;
5139 unsigned NumElems = VT.getVectorNumElements();
5141 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5142 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5143 LD->getPointerInfo().getWithOffset(StartOffset),
5144 false, false, false, 0);
5146 SmallVector<int, 8> Mask(NumElems, EltNo);
5148 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5154 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5155 /// elements can be replaced by a single large load which has the same value as
5156 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5158 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5160 /// FIXME: we'd also like to handle the case where the last elements are zero
5161 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5162 /// There's even a handy isZeroNode for that purpose.
5163 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5164 SDLoc &DL, SelectionDAG &DAG,
5165 bool isAfterLegalize) {
5166 unsigned NumElems = Elts.size();
5168 LoadSDNode *LDBase = nullptr;
5169 unsigned LastLoadedElt = -1U;
5171 // For each element in the initializer, see if we've found a load or an undef.
5172 // If we don't find an initial load element, or later load elements are
5173 // non-consecutive, bail out.
5174 for (unsigned i = 0; i < NumElems; ++i) {
5175 SDValue Elt = Elts[i];
5176 // Look through a bitcast.
5177 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5178 Elt = Elt.getOperand(0);
5179 if (!Elt.getNode() ||
5180 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5183 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5185 LDBase = cast<LoadSDNode>(Elt.getNode());
5189 if (Elt.getOpcode() == ISD::UNDEF)
5192 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5193 EVT LdVT = Elt.getValueType();
5194 // Each loaded element must be the correct fractional portion of the
5195 // requested vector load.
5196 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5198 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5203 // If we have found an entire vector of loads and undefs, then return a large
5204 // load of the entire vector width starting at the base pointer. If we found
5205 // consecutive loads for the low half, generate a vzext_load node.
5206 if (LastLoadedElt == NumElems - 1) {
5207 assert(LDBase && "Did not find base load for merging consecutive loads");
5208 EVT EltVT = LDBase->getValueType(0);
5209 // Ensure that the input vector size for the merged loads matches the
5210 // cumulative size of the input elements.
5211 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5214 if (isAfterLegalize &&
5215 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5218 SDValue NewLd = SDValue();
5220 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5221 LDBase->getPointerInfo(), LDBase->isVolatile(),
5222 LDBase->isNonTemporal(), LDBase->isInvariant(),
5223 LDBase->getAlignment());
5225 if (LDBase->hasAnyUseOfValue(1)) {
5226 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5228 SDValue(NewLd.getNode(), 1));
5229 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5230 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5231 SDValue(NewLd.getNode(), 1));
5237 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5238 //of a v4i32 / v4f32. It's probably worth generalizing.
5239 EVT EltVT = VT.getVectorElementType();
5240 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5241 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5242 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5243 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5245 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5246 LDBase->getPointerInfo(),
5247 LDBase->getAlignment(),
5248 false/*isVolatile*/, true/*ReadMem*/,
5251 // Make sure the newly-created LOAD is in the same position as LDBase in
5252 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5253 // update uses of LDBase's output chain to use the TokenFactor.
5254 if (LDBase->hasAnyUseOfValue(1)) {
5255 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5256 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5257 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5258 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5259 SDValue(ResNode.getNode(), 1));
5262 return DAG.getBitcast(VT, ResNode);
5267 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5268 /// to generate a splat value for the following cases:
5269 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5270 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5271 /// a scalar load, or a constant.
5272 /// The VBROADCAST node is returned when a pattern is found,
5273 /// or SDValue() otherwise.
5274 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5275 SelectionDAG &DAG) {
5276 // VBROADCAST requires AVX.
5277 // TODO: Splats could be generated for non-AVX CPUs using SSE
5278 // instructions, but there's less potential gain for only 128-bit vectors.
5279 if (!Subtarget->hasAVX())
5282 MVT VT = Op.getSimpleValueType();
5285 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5286 "Unsupported vector type for broadcast.");
5291 switch (Op.getOpcode()) {
5293 // Unknown pattern found.
5296 case ISD::BUILD_VECTOR: {
5297 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5298 BitVector UndefElements;
5299 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5301 // We need a splat of a single value to use broadcast, and it doesn't
5302 // make any sense if the value is only in one element of the vector.
5303 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5307 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5308 Ld.getOpcode() == ISD::ConstantFP);
5310 // Make sure that all of the users of a non-constant load are from the
5311 // BUILD_VECTOR node.
5312 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5317 case ISD::VECTOR_SHUFFLE: {
5318 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5320 // Shuffles must have a splat mask where the first element is
5322 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5325 SDValue Sc = Op.getOperand(0);
5326 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5327 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5329 if (!Subtarget->hasInt256())
5332 // Use the register form of the broadcast instruction available on AVX2.
5333 if (VT.getSizeInBits() >= 256)
5334 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5335 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5338 Ld = Sc.getOperand(0);
5339 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5340 Ld.getOpcode() == ISD::ConstantFP);
5342 // The scalar_to_vector node and the suspected
5343 // load node must have exactly one user.
5344 // Constants may have multiple users.
5346 // AVX-512 has register version of the broadcast
5347 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5348 Ld.getValueType().getSizeInBits() >= 32;
5349 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5356 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5357 bool IsGE256 = (VT.getSizeInBits() >= 256);
5359 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5360 // instruction to save 8 or more bytes of constant pool data.
5361 // TODO: If multiple splats are generated to load the same constant,
5362 // it may be detrimental to overall size. There needs to be a way to detect
5363 // that condition to know if this is truly a size win.
5364 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5366 // Handle broadcasting a single constant scalar from the constant pool
5368 // On Sandybridge (no AVX2), it is still better to load a constant vector
5369 // from the constant pool and not to broadcast it from a scalar.
5370 // But override that restriction when optimizing for size.
5371 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5372 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5373 EVT CVT = Ld.getValueType();
5374 assert(!CVT.isVector() && "Must not broadcast a vector type");
5376 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5377 // For size optimization, also splat v2f64 and v2i64, and for size opt
5378 // with AVX2, also splat i8 and i16.
5379 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5380 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5381 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5382 const Constant *C = nullptr;
5383 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5384 C = CI->getConstantIntValue();
5385 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5386 C = CF->getConstantFPValue();
5388 assert(C && "Invalid constant type");
5390 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5392 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5393 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5395 CVT, dl, DAG.getEntryNode(), CP,
5396 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5397 false, false, Alignment);
5399 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5403 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5405 // Handle AVX2 in-register broadcasts.
5406 if (!IsLoad && Subtarget->hasInt256() &&
5407 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5408 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5410 // The scalar source must be a normal load.
5414 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5415 (Subtarget->hasVLX() && ScalarSize == 64))
5416 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5418 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5419 // double since there is no vbroadcastsd xmm
5420 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5421 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5422 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5425 // Unsupported broadcast.
5429 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5430 /// underlying vector and index.
5432 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5434 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5436 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5437 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5440 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5442 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5444 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5445 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5448 // In this case the vector is the extract_subvector expression and the index
5449 // is 2, as specified by the shuffle.
5450 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5451 SDValue ShuffleVec = SVOp->getOperand(0);
5452 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5453 assert(ShuffleVecVT.getVectorElementType() ==
5454 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5456 int ShuffleIdx = SVOp->getMaskElt(Idx);
5457 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5458 ExtractedFromVec = ShuffleVec;
5464 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5465 MVT VT = Op.getSimpleValueType();
5467 // Skip if insert_vec_elt is not supported.
5468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5469 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5473 unsigned NumElems = Op.getNumOperands();
5477 SmallVector<unsigned, 4> InsertIndices;
5478 SmallVector<int, 8> Mask(NumElems, -1);
5480 for (unsigned i = 0; i != NumElems; ++i) {
5481 unsigned Opc = Op.getOperand(i).getOpcode();
5483 if (Opc == ISD::UNDEF)
5486 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5487 // Quit if more than 1 elements need inserting.
5488 if (InsertIndices.size() > 1)
5491 InsertIndices.push_back(i);
5495 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5496 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5497 // Quit if non-constant index.
5498 if (!isa<ConstantSDNode>(ExtIdx))
5500 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5502 // Quit if extracted from vector of different type.
5503 if (ExtractedFromVec.getValueType() != VT)
5506 if (!VecIn1.getNode())
5507 VecIn1 = ExtractedFromVec;
5508 else if (VecIn1 != ExtractedFromVec) {
5509 if (!VecIn2.getNode())
5510 VecIn2 = ExtractedFromVec;
5511 else if (VecIn2 != ExtractedFromVec)
5512 // Quit if more than 2 vectors to shuffle
5516 if (ExtractedFromVec == VecIn1)
5518 else if (ExtractedFromVec == VecIn2)
5519 Mask[i] = Idx + NumElems;
5522 if (!VecIn1.getNode())
5525 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5526 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5527 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5528 unsigned Idx = InsertIndices[i];
5529 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5530 DAG.getIntPtrConstant(Idx, DL));
5536 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5537 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5538 Op.getScalarValueSizeInBits() == 1 &&
5539 "Can not convert non-constant vector");
5540 uint64_t Immediate = 0;
5541 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5542 SDValue In = Op.getOperand(idx);
5543 if (In.getOpcode() != ISD::UNDEF)
5544 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5548 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5549 return DAG.getConstant(Immediate, dl, VT);
5551 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5553 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5555 MVT VT = Op.getSimpleValueType();
5556 assert((VT.getVectorElementType() == MVT::i1) &&
5557 "Unexpected type in LowerBUILD_VECTORvXi1!");
5560 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5561 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5562 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5563 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5566 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5567 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5568 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5569 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5572 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5573 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5574 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5575 return DAG.getBitcast(VT, Imm);
5576 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5577 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5578 DAG.getIntPtrConstant(0, dl));
5581 // Vector has one or more non-const elements
5582 uint64_t Immediate = 0;
5583 SmallVector<unsigned, 16> NonConstIdx;
5584 bool IsSplat = true;
5585 bool HasConstElts = false;
5587 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5588 SDValue In = Op.getOperand(idx);
5589 if (In.getOpcode() == ISD::UNDEF)
5591 if (!isa<ConstantSDNode>(In))
5592 NonConstIdx.push_back(idx);
5594 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5595 HasConstElts = true;
5599 else if (In != Op.getOperand(SplatIdx))
5603 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5605 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5606 DAG.getConstant(1, dl, VT),
5607 DAG.getConstant(0, dl, VT));
5609 // insert elements one by one
5613 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5614 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5616 else if (HasConstElts)
5617 Imm = DAG.getConstant(0, dl, VT);
5619 Imm = DAG.getUNDEF(VT);
5620 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5621 DstVec = DAG.getBitcast(VT, Imm);
5623 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5624 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5625 DAG.getIntPtrConstant(0, dl));
5628 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5629 unsigned InsertIdx = NonConstIdx[i];
5630 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5631 Op.getOperand(InsertIdx),
5632 DAG.getIntPtrConstant(InsertIdx, dl));
5637 /// \brief Return true if \p N implements a horizontal binop and return the
5638 /// operands for the horizontal binop into V0 and V1.
5640 /// This is a helper function of LowerToHorizontalOp().
5641 /// This function checks that the build_vector \p N in input implements a
5642 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5643 /// operation to match.
5644 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5645 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5646 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5649 /// This function only analyzes elements of \p N whose indices are
5650 /// in range [BaseIdx, LastIdx).
5651 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5653 unsigned BaseIdx, unsigned LastIdx,
5654 SDValue &V0, SDValue &V1) {
5655 EVT VT = N->getValueType(0);
5657 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5658 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5659 "Invalid Vector in input!");
5661 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5662 bool CanFold = true;
5663 unsigned ExpectedVExtractIdx = BaseIdx;
5664 unsigned NumElts = LastIdx - BaseIdx;
5665 V0 = DAG.getUNDEF(VT);
5666 V1 = DAG.getUNDEF(VT);
5668 // Check if N implements a horizontal binop.
5669 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5670 SDValue Op = N->getOperand(i + BaseIdx);
5673 if (Op->getOpcode() == ISD::UNDEF) {
5674 // Update the expected vector extract index.
5675 if (i * 2 == NumElts)
5676 ExpectedVExtractIdx = BaseIdx;
5677 ExpectedVExtractIdx += 2;
5681 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5686 SDValue Op0 = Op.getOperand(0);
5687 SDValue Op1 = Op.getOperand(1);
5689 // Try to match the following pattern:
5690 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5691 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5692 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5693 Op0.getOperand(0) == Op1.getOperand(0) &&
5694 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5695 isa<ConstantSDNode>(Op1.getOperand(1)));
5699 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5700 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5702 if (i * 2 < NumElts) {
5703 if (V0.getOpcode() == ISD::UNDEF) {
5704 V0 = Op0.getOperand(0);
5705 if (V0.getValueType() != VT)
5709 if (V1.getOpcode() == ISD::UNDEF) {
5710 V1 = Op0.getOperand(0);
5711 if (V1.getValueType() != VT)
5714 if (i * 2 == NumElts)
5715 ExpectedVExtractIdx = BaseIdx;
5718 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5719 if (I0 == ExpectedVExtractIdx)
5720 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5721 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5722 // Try to match the following dag sequence:
5723 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5724 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5728 ExpectedVExtractIdx += 2;
5734 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5735 /// a concat_vector.
5737 /// This is a helper function of LowerToHorizontalOp().
5738 /// This function expects two 256-bit vectors called V0 and V1.
5739 /// At first, each vector is split into two separate 128-bit vectors.
5740 /// Then, the resulting 128-bit vectors are used to implement two
5741 /// horizontal binary operations.
5743 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5745 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5746 /// the two new horizontal binop.
5747 /// When Mode is set, the first horizontal binop dag node would take as input
5748 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5749 /// horizontal binop dag node would take as input the lower 128-bit of V1
5750 /// and the upper 128-bit of V1.
5752 /// HADD V0_LO, V0_HI
5753 /// HADD V1_LO, V1_HI
5755 /// Otherwise, the first horizontal binop dag node takes as input the lower
5756 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5757 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5759 /// HADD V0_LO, V1_LO
5760 /// HADD V0_HI, V1_HI
5762 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5763 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5764 /// the upper 128-bits of the result.
5765 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5766 SDLoc DL, SelectionDAG &DAG,
5767 unsigned X86Opcode, bool Mode,
5768 bool isUndefLO, bool isUndefHI) {
5769 EVT VT = V0.getValueType();
5770 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5771 "Invalid nodes in input!");
5773 unsigned NumElts = VT.getVectorNumElements();
5774 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5775 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5776 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5777 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5778 EVT NewVT = V0_LO.getValueType();
5780 SDValue LO = DAG.getUNDEF(NewVT);
5781 SDValue HI = DAG.getUNDEF(NewVT);
5784 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5785 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5786 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5787 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5788 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5790 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5791 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5792 V1_LO->getOpcode() != ISD::UNDEF))
5793 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5795 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5796 V1_HI->getOpcode() != ISD::UNDEF))
5797 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5800 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5803 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5805 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5806 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5807 EVT VT = BV->getValueType(0);
5808 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5809 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5813 unsigned NumElts = VT.getVectorNumElements();
5814 SDValue InVec0 = DAG.getUNDEF(VT);
5815 SDValue InVec1 = DAG.getUNDEF(VT);
5817 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5818 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5820 // Odd-numbered elements in the input build vector are obtained from
5821 // adding two integer/float elements.
5822 // Even-numbered elements in the input build vector are obtained from
5823 // subtracting two integer/float elements.
5824 unsigned ExpectedOpcode = ISD::FSUB;
5825 unsigned NextExpectedOpcode = ISD::FADD;
5826 bool AddFound = false;
5827 bool SubFound = false;
5829 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5830 SDValue Op = BV->getOperand(i);
5832 // Skip 'undef' values.
5833 unsigned Opcode = Op.getOpcode();
5834 if (Opcode == ISD::UNDEF) {
5835 std::swap(ExpectedOpcode, NextExpectedOpcode);
5839 // Early exit if we found an unexpected opcode.
5840 if (Opcode != ExpectedOpcode)
5843 SDValue Op0 = Op.getOperand(0);
5844 SDValue Op1 = Op.getOperand(1);
5846 // Try to match the following pattern:
5847 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5848 // Early exit if we cannot match that sequence.
5849 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5850 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5851 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5852 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5853 Op0.getOperand(1) != Op1.getOperand(1))
5856 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5860 // We found a valid add/sub node. Update the information accordingly.
5866 // Update InVec0 and InVec1.
5867 if (InVec0.getOpcode() == ISD::UNDEF) {
5868 InVec0 = Op0.getOperand(0);
5869 if (InVec0.getValueType() != VT)
5872 if (InVec1.getOpcode() == ISD::UNDEF) {
5873 InVec1 = Op1.getOperand(0);
5874 if (InVec1.getValueType() != VT)
5878 // Make sure that operands in input to each add/sub node always
5879 // come from a same pair of vectors.
5880 if (InVec0 != Op0.getOperand(0)) {
5881 if (ExpectedOpcode == ISD::FSUB)
5884 // FADD is commutable. Try to commute the operands
5885 // and then test again.
5886 std::swap(Op0, Op1);
5887 if (InVec0 != Op0.getOperand(0))
5891 if (InVec1 != Op1.getOperand(0))
5894 // Update the pair of expected opcodes.
5895 std::swap(ExpectedOpcode, NextExpectedOpcode);
5898 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5899 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5900 InVec1.getOpcode() != ISD::UNDEF)
5901 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5906 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5907 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5908 const X86Subtarget *Subtarget,
5909 SelectionDAG &DAG) {
5910 EVT VT = BV->getValueType(0);
5911 unsigned NumElts = VT.getVectorNumElements();
5912 unsigned NumUndefsLO = 0;
5913 unsigned NumUndefsHI = 0;
5914 unsigned Half = NumElts/2;
5916 // Count the number of UNDEF operands in the build_vector in input.
5917 for (unsigned i = 0, e = Half; i != e; ++i)
5918 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5921 for (unsigned i = Half, e = NumElts; i != e; ++i)
5922 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5925 // Early exit if this is either a build_vector of all UNDEFs or all the
5926 // operands but one are UNDEF.
5927 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5931 SDValue InVec0, InVec1;
5932 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5933 // Try to match an SSE3 float HADD/HSUB.
5934 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5935 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5937 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5938 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5939 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5940 // Try to match an SSSE3 integer HADD/HSUB.
5941 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5942 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5944 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5945 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5948 if (!Subtarget->hasAVX())
5951 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5952 // Try to match an AVX horizontal add/sub of packed single/double
5953 // precision floating point values from 256-bit vectors.
5954 SDValue InVec2, InVec3;
5955 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5956 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5957 ((InVec0.getOpcode() == ISD::UNDEF ||
5958 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5959 ((InVec1.getOpcode() == ISD::UNDEF ||
5960 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5961 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5963 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5964 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5965 ((InVec0.getOpcode() == ISD::UNDEF ||
5966 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5967 ((InVec1.getOpcode() == ISD::UNDEF ||
5968 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5969 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5970 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5971 // Try to match an AVX2 horizontal add/sub of signed integers.
5972 SDValue InVec2, InVec3;
5974 bool CanFold = true;
5976 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5977 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5978 ((InVec0.getOpcode() == ISD::UNDEF ||
5979 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5980 ((InVec1.getOpcode() == ISD::UNDEF ||
5981 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5982 X86Opcode = X86ISD::HADD;
5983 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5984 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5985 ((InVec0.getOpcode() == ISD::UNDEF ||
5986 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5987 ((InVec1.getOpcode() == ISD::UNDEF ||
5988 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5989 X86Opcode = X86ISD::HSUB;
5994 // Fold this build_vector into a single horizontal add/sub.
5995 // Do this only if the target has AVX2.
5996 if (Subtarget->hasAVX2())
5997 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5999 // Do not try to expand this build_vector into a pair of horizontal
6000 // add/sub if we can emit a pair of scalar add/sub.
6001 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6004 // Convert this build_vector into a pair of horizontal binop followed by
6006 bool isUndefLO = NumUndefsLO == Half;
6007 bool isUndefHI = NumUndefsHI == Half;
6008 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6009 isUndefLO, isUndefHI);
6013 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6014 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6016 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6017 X86Opcode = X86ISD::HADD;
6018 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6019 X86Opcode = X86ISD::HSUB;
6020 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6021 X86Opcode = X86ISD::FHADD;
6022 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6023 X86Opcode = X86ISD::FHSUB;
6027 // Don't try to expand this build_vector into a pair of horizontal add/sub
6028 // if we can simply emit a pair of scalar add/sub.
6029 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6032 // Convert this build_vector into two horizontal add/sub followed by
6034 bool isUndefLO = NumUndefsLO == Half;
6035 bool isUndefHI = NumUndefsHI == Half;
6036 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6037 isUndefLO, isUndefHI);
6044 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6047 MVT VT = Op.getSimpleValueType();
6048 MVT ExtVT = VT.getVectorElementType();
6049 unsigned NumElems = Op.getNumOperands();
6051 // Generate vectors for predicate vectors.
6052 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6053 return LowerBUILD_VECTORvXi1(Op, DAG);
6055 // Vectors containing all zeros can be matched by pxor and xorps later
6056 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6057 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6058 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6059 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6062 return getZeroVector(VT, Subtarget, DAG, dl);
6065 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6066 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6067 // vpcmpeqd on 256-bit vectors.
6068 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6069 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6072 if (!VT.is512BitVector())
6073 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6076 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6077 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6079 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6080 return HorizontalOp;
6081 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6084 unsigned EVTBits = ExtVT.getSizeInBits();
6086 unsigned NumZero = 0;
6087 unsigned NumNonZero = 0;
6088 unsigned NonZeros = 0;
6089 bool IsAllConstants = true;
6090 SmallSet<SDValue, 8> Values;
6091 for (unsigned i = 0; i < NumElems; ++i) {
6092 SDValue Elt = Op.getOperand(i);
6093 if (Elt.getOpcode() == ISD::UNDEF)
6096 if (Elt.getOpcode() != ISD::Constant &&
6097 Elt.getOpcode() != ISD::ConstantFP)
6098 IsAllConstants = false;
6099 if (X86::isZeroNode(Elt))
6102 NonZeros |= (1 << i);
6107 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6108 if (NumNonZero == 0)
6109 return DAG.getUNDEF(VT);
6111 // Special case for single non-zero, non-undef, element.
6112 if (NumNonZero == 1) {
6113 unsigned Idx = countTrailingZeros(NonZeros);
6114 SDValue Item = Op.getOperand(Idx);
6116 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6117 // the value are obviously zero, truncate the value to i32 and do the
6118 // insertion that way. Only do this if the value is non-constant or if the
6119 // value is a constant being inserted into element 0. It is cheaper to do
6120 // a constant pool load than it is to do a movd + shuffle.
6121 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6122 (!IsAllConstants || Idx == 0)) {
6123 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6125 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6126 EVT VecVT = MVT::v4i32;
6128 // Truncate the value (which may itself be a constant) to i32, and
6129 // convert it to a vector with movd (S2V+shuffle to zero extend).
6130 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6131 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6132 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6133 Item, Idx * 2, true, Subtarget, DAG));
6137 // If we have a constant or non-constant insertion into the low element of
6138 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6139 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6140 // depending on what the source datatype is.
6143 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6145 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6146 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6147 if (VT.is512BitVector()) {
6148 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6149 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6150 Item, DAG.getIntPtrConstant(0, dl));
6152 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6153 "Expected an SSE value type!");
6154 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6155 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6156 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6159 // We can't directly insert an i8 or i16 into a vector, so zero extend
6161 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6162 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6163 if (VT.is256BitVector()) {
6164 if (Subtarget->hasAVX()) {
6165 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6166 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6168 // Without AVX, we need to extend to a 128-bit vector and then
6169 // insert into the 256-bit vector.
6170 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6171 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6172 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6175 assert(VT.is128BitVector() && "Expected an SSE value type!");
6176 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6177 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6179 return DAG.getBitcast(VT, Item);
6183 // Is it a vector logical left shift?
6184 if (NumElems == 2 && Idx == 1 &&
6185 X86::isZeroNode(Op.getOperand(0)) &&
6186 !X86::isZeroNode(Op.getOperand(1))) {
6187 unsigned NumBits = VT.getSizeInBits();
6188 return getVShift(true, VT,
6189 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6190 VT, Op.getOperand(1)),
6191 NumBits/2, DAG, *this, dl);
6194 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6197 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6198 // is a non-constant being inserted into an element other than the low one,
6199 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6200 // movd/movss) to move this into the low element, then shuffle it into
6202 if (EVTBits == 32) {
6203 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6204 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6208 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6209 if (Values.size() == 1) {
6210 if (EVTBits == 32) {
6211 // Instead of a shuffle like this:
6212 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6213 // Check if it's possible to issue this instead.
6214 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6215 unsigned Idx = countTrailingZeros(NonZeros);
6216 SDValue Item = Op.getOperand(Idx);
6217 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6218 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6223 // A vector full of immediates; various special cases are already
6224 // handled, so this is best done with a single constant-pool load.
6228 // For AVX-length vectors, see if we can use a vector load to get all of the
6229 // elements, otherwise build the individual 128-bit pieces and use
6230 // shuffles to put them in place.
6231 if (VT.is256BitVector() || VT.is512BitVector()) {
6232 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6234 // Check for a build vector of consecutive loads.
6235 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6238 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6240 // Build both the lower and upper subvector.
6241 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6242 makeArrayRef(&V[0], NumElems/2));
6243 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6244 makeArrayRef(&V[NumElems / 2], NumElems/2));
6246 // Recreate the wider vector with the lower and upper part.
6247 if (VT.is256BitVector())
6248 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6249 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6252 // Let legalizer expand 2-wide build_vectors.
6253 if (EVTBits == 64) {
6254 if (NumNonZero == 1) {
6255 // One half is zero or undef.
6256 unsigned Idx = countTrailingZeros(NonZeros);
6257 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6258 Op.getOperand(Idx));
6259 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6264 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6265 if (EVTBits == 8 && NumElems == 16)
6266 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6270 if (EVTBits == 16 && NumElems == 8)
6271 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6275 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6276 if (EVTBits == 32 && NumElems == 4)
6277 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6280 // If element VT is == 32 bits, turn it into a number of shuffles.
6281 SmallVector<SDValue, 8> V(NumElems);
6282 if (NumElems == 4 && NumZero > 0) {
6283 for (unsigned i = 0; i < 4; ++i) {
6284 bool isZero = !(NonZeros & (1 << i));
6286 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6288 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6291 for (unsigned i = 0; i < 2; ++i) {
6292 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6295 V[i] = V[i*2]; // Must be a zero vector.
6298 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6301 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6304 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6309 bool Reverse1 = (NonZeros & 0x3) == 2;
6310 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6314 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6315 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6317 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6320 if (Values.size() > 1 && VT.is128BitVector()) {
6321 // Check for a build vector of consecutive loads.
6322 for (unsigned i = 0; i < NumElems; ++i)
6323 V[i] = Op.getOperand(i);
6325 // Check for elements which are consecutive loads.
6326 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6329 // Check for a build vector from mostly shuffle plus few inserting.
6330 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6333 // For SSE 4.1, use insertps to put the high elements into the low element.
6334 if (Subtarget->hasSSE41()) {
6336 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6337 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6339 Result = DAG.getUNDEF(VT);
6341 for (unsigned i = 1; i < NumElems; ++i) {
6342 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6343 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6344 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6349 // Otherwise, expand into a number of unpckl*, start by extending each of
6350 // our (non-undef) elements to the full vector width with the element in the
6351 // bottom slot of the vector (which generates no code for SSE).
6352 for (unsigned i = 0; i < NumElems; ++i) {
6353 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6354 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6356 V[i] = DAG.getUNDEF(VT);
6359 // Next, we iteratively mix elements, e.g. for v4f32:
6360 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6361 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6362 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6363 unsigned EltStride = NumElems >> 1;
6364 while (EltStride != 0) {
6365 for (unsigned i = 0; i < EltStride; ++i) {
6366 // If V[i+EltStride] is undef and this is the first round of mixing,
6367 // then it is safe to just drop this shuffle: V[i] is already in the
6368 // right place, the one element (since it's the first round) being
6369 // inserted as undef can be dropped. This isn't safe for successive
6370 // rounds because they will permute elements within both vectors.
6371 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6372 EltStride == NumElems/2)
6375 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6384 // 256-bit AVX can use the vinsertf128 instruction
6385 // to create 256-bit vectors from two other 128-bit ones.
6386 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6388 MVT ResVT = Op.getSimpleValueType();
6390 assert((ResVT.is256BitVector() ||
6391 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6393 SDValue V1 = Op.getOperand(0);
6394 SDValue V2 = Op.getOperand(1);
6395 unsigned NumElems = ResVT.getVectorNumElements();
6396 if (ResVT.is256BitVector())
6397 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6399 if (Op.getNumOperands() == 4) {
6400 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6401 ResVT.getVectorNumElements()/2);
6402 SDValue V3 = Op.getOperand(2);
6403 SDValue V4 = Op.getOperand(3);
6404 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6405 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6407 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6410 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6411 const X86Subtarget *Subtarget,
6412 SelectionDAG & DAG) {
6414 MVT ResVT = Op.getSimpleValueType();
6415 unsigned NumOfOperands = Op.getNumOperands();
6417 assert(isPowerOf2_32(NumOfOperands) &&
6418 "Unexpected number of operands in CONCAT_VECTORS");
6420 if (NumOfOperands > 2) {
6421 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6422 ResVT.getVectorNumElements()/2);
6423 SmallVector<SDValue, 2> Ops;
6424 for (unsigned i = 0; i < NumOfOperands/2; i++)
6425 Ops.push_back(Op.getOperand(i));
6426 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6428 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6429 Ops.push_back(Op.getOperand(i));
6430 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6431 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6434 SDValue V1 = Op.getOperand(0);
6435 SDValue V2 = Op.getOperand(1);
6436 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6437 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6439 if (IsZeroV1 && IsZeroV2)
6440 return getZeroVector(ResVT, Subtarget, DAG, dl);
6442 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6443 SDValue Undef = DAG.getUNDEF(ResVT);
6444 unsigned NumElems = ResVT.getVectorNumElements();
6445 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6447 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6448 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6452 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6453 // Zero the upper bits of V1
6454 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6455 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6458 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6461 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6462 const X86Subtarget *Subtarget,
6463 SelectionDAG &DAG) {
6464 MVT VT = Op.getSimpleValueType();
6465 if (VT.getVectorElementType() == MVT::i1)
6466 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6468 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6469 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6470 Op.getNumOperands() == 4)));
6472 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6473 // from two other 128-bit ones.
6475 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6476 return LowerAVXCONCAT_VECTORS(Op, DAG);
6480 //===----------------------------------------------------------------------===//
6481 // Vector shuffle lowering
6483 // This is an experimental code path for lowering vector shuffles on x86. It is
6484 // designed to handle arbitrary vector shuffles and blends, gracefully
6485 // degrading performance as necessary. It works hard to recognize idiomatic
6486 // shuffles and lower them to optimal instruction patterns without leaving
6487 // a framework that allows reasonably efficient handling of all vector shuffle
6489 //===----------------------------------------------------------------------===//
6491 /// \brief Tiny helper function to identify a no-op mask.
6493 /// This is a somewhat boring predicate function. It checks whether the mask
6494 /// array input, which is assumed to be a single-input shuffle mask of the kind
6495 /// used by the X86 shuffle instructions (not a fully general
6496 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6497 /// in-place shuffle are 'no-op's.
6498 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6499 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6500 if (Mask[i] != -1 && Mask[i] != i)
6505 /// \brief Helper function to classify a mask as a single-input mask.
6507 /// This isn't a generic single-input test because in the vector shuffle
6508 /// lowering we canonicalize single inputs to be the first input operand. This
6509 /// means we can more quickly test for a single input by only checking whether
6510 /// an input from the second operand exists. We also assume that the size of
6511 /// mask corresponds to the size of the input vectors which isn't true in the
6512 /// fully general case.
6513 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6515 if (M >= (int)Mask.size())
6520 /// \brief Test whether there are elements crossing 128-bit lanes in this
6523 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6524 /// and we routinely test for these.
6525 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6526 int LaneSize = 128 / VT.getScalarSizeInBits();
6527 int Size = Mask.size();
6528 for (int i = 0; i < Size; ++i)
6529 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6534 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6536 /// This checks a shuffle mask to see if it is performing the same
6537 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6538 /// that it is also not lane-crossing. It may however involve a blend from the
6539 /// same lane of a second vector.
6541 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6542 /// non-trivial to compute in the face of undef lanes. The representation is
6543 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6544 /// entries from both V1 and V2 inputs to the wider mask.
6546 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6547 SmallVectorImpl<int> &RepeatedMask) {
6548 int LaneSize = 128 / VT.getScalarSizeInBits();
6549 RepeatedMask.resize(LaneSize, -1);
6550 int Size = Mask.size();
6551 for (int i = 0; i < Size; ++i) {
6554 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6555 // This entry crosses lanes, so there is no way to model this shuffle.
6558 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6559 if (RepeatedMask[i % LaneSize] == -1)
6560 // This is the first non-undef entry in this slot of a 128-bit lane.
6561 RepeatedMask[i % LaneSize] =
6562 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6563 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6564 // Found a mismatch with the repeated mask.
6570 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6573 /// This is a fast way to test a shuffle mask against a fixed pattern:
6575 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6577 /// It returns true if the mask is exactly as wide as the argument list, and
6578 /// each element of the mask is either -1 (signifying undef) or the value given
6579 /// in the argument.
6580 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6581 ArrayRef<int> ExpectedMask) {
6582 if (Mask.size() != ExpectedMask.size())
6585 int Size = Mask.size();
6587 // If the values are build vectors, we can look through them to find
6588 // equivalent inputs that make the shuffles equivalent.
6589 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6590 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6592 for (int i = 0; i < Size; ++i)
6593 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6594 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6595 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6596 if (!MaskBV || !ExpectedBV ||
6597 MaskBV->getOperand(Mask[i] % Size) !=
6598 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6605 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6607 /// This helper function produces an 8-bit shuffle immediate corresponding to
6608 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6609 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6612 /// NB: We rely heavily on "undef" masks preserving the input lane.
6613 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6614 SelectionDAG &DAG) {
6615 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6616 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6617 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6618 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6619 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6622 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6623 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6624 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6625 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6626 return DAG.getConstant(Imm, DL, MVT::i8);
6629 /// \brief Compute whether each element of a shuffle is zeroable.
6631 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6632 /// Either it is an undef element in the shuffle mask, the element of the input
6633 /// referenced is undef, or the element of the input referenced is known to be
6634 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6635 /// as many lanes with this technique as possible to simplify the remaining
6637 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6638 SDValue V1, SDValue V2) {
6639 SmallBitVector Zeroable(Mask.size(), false);
6641 while (V1.getOpcode() == ISD::BITCAST)
6642 V1 = V1->getOperand(0);
6643 while (V2.getOpcode() == ISD::BITCAST)
6644 V2 = V2->getOperand(0);
6646 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6647 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6649 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6651 // Handle the easy cases.
6652 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6657 // If this is an index into a build_vector node (which has the same number
6658 // of elements), dig out the input value and use it.
6659 SDValue V = M < Size ? V1 : V2;
6660 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6663 SDValue Input = V.getOperand(M % Size);
6664 // The UNDEF opcode check really should be dead code here, but not quite
6665 // worth asserting on (it isn't invalid, just unexpected).
6666 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6673 // X86 has dedicated unpack instructions that can handle specific blend
6674 // operations: UNPCKH and UNPCKL.
6675 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6676 SDValue V1, SDValue V2,
6677 SelectionDAG &DAG) {
6678 int NumElts = VT.getVectorNumElements();
6681 bool UnpcklSwapped = true;
6682 bool UnpckhSwapped = true;
6683 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6685 for (int i = 0; i < NumElts; ++i) {
6686 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6688 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6689 int HiPos = LoPos + NumEltsInLane / 2;
6690 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6691 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6695 if (Mask[i] != LoPos)
6697 if (Mask[i] != HiPos)
6699 if (Mask[i] != LoPosSwapped)
6700 UnpcklSwapped = false;
6701 if (Mask[i] != HiPosSwapped)
6702 UnpckhSwapped = false;
6703 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6707 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6709 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6711 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6713 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6715 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6719 /// \brief Try to emit a bitmask instruction for a shuffle.
6721 /// This handles cases where we can model a blend exactly as a bitmask due to
6722 /// one of the inputs being zeroable.
6723 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6724 SDValue V2, ArrayRef<int> Mask,
6725 SelectionDAG &DAG) {
6726 MVT EltVT = VT.getScalarType();
6727 int NumEltBits = EltVT.getSizeInBits();
6728 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6729 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6730 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6732 if (EltVT.isFloatingPoint()) {
6733 Zero = DAG.getBitcast(EltVT, Zero);
6734 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6736 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6737 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6739 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6742 if (Mask[i] % Size != i)
6743 return SDValue(); // Not a blend.
6745 V = Mask[i] < Size ? V1 : V2;
6746 else if (V != (Mask[i] < Size ? V1 : V2))
6747 return SDValue(); // Can only let one input through the mask.
6749 VMaskOps[i] = AllOnes;
6752 return SDValue(); // No non-zeroable elements!
6754 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6755 V = DAG.getNode(VT.isFloatingPoint()
6756 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6761 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6763 /// This is used as a fallback approach when first class blend instructions are
6764 /// unavailable. Currently it is only suitable for integer vectors, but could
6765 /// be generalized for floating point vectors if desirable.
6766 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6767 SDValue V2, ArrayRef<int> Mask,
6768 SelectionDAG &DAG) {
6769 assert(VT.isInteger() && "Only supports integer vector types!");
6770 MVT EltVT = VT.getScalarType();
6771 int NumEltBits = EltVT.getSizeInBits();
6772 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6773 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6775 SmallVector<SDValue, 16> MaskOps;
6776 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6777 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6778 return SDValue(); // Shuffled input!
6779 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6782 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6783 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6784 // We have to cast V2 around.
6785 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6786 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6787 DAG.getBitcast(MaskVT, V1Mask),
6788 DAG.getBitcast(MaskVT, V2)));
6789 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6792 /// \brief Try to emit a blend instruction for a shuffle.
6794 /// This doesn't do any checks for the availability of instructions for blending
6795 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6796 /// be matched in the backend with the type given. What it does check for is
6797 /// that the shuffle mask is in fact a blend.
6798 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6799 SDValue V2, ArrayRef<int> Mask,
6800 const X86Subtarget *Subtarget,
6801 SelectionDAG &DAG) {
6802 unsigned BlendMask = 0;
6803 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6804 if (Mask[i] >= Size) {
6805 if (Mask[i] != i + Size)
6806 return SDValue(); // Shuffled V2 input!
6807 BlendMask |= 1u << i;
6810 if (Mask[i] >= 0 && Mask[i] != i)
6811 return SDValue(); // Shuffled V1 input!
6813 switch (VT.SimpleTy) {
6818 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6819 DAG.getConstant(BlendMask, DL, MVT::i8));
6823 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6827 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6828 // that instruction.
6829 if (Subtarget->hasAVX2()) {
6830 // Scale the blend by the number of 32-bit dwords per element.
6831 int Scale = VT.getScalarSizeInBits() / 32;
6833 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6834 if (Mask[i] >= Size)
6835 for (int j = 0; j < Scale; ++j)
6836 BlendMask |= 1u << (i * Scale + j);
6838 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6839 V1 = DAG.getBitcast(BlendVT, V1);
6840 V2 = DAG.getBitcast(BlendVT, V2);
6841 return DAG.getBitcast(
6842 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6843 DAG.getConstant(BlendMask, DL, MVT::i8)));
6847 // For integer shuffles we need to expand the mask and cast the inputs to
6848 // v8i16s prior to blending.
6849 int Scale = 8 / VT.getVectorNumElements();
6851 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6852 if (Mask[i] >= Size)
6853 for (int j = 0; j < Scale; ++j)
6854 BlendMask |= 1u << (i * Scale + j);
6856 V1 = DAG.getBitcast(MVT::v8i16, V1);
6857 V2 = DAG.getBitcast(MVT::v8i16, V2);
6858 return DAG.getBitcast(VT,
6859 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6860 DAG.getConstant(BlendMask, DL, MVT::i8)));
6864 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6865 SmallVector<int, 8> RepeatedMask;
6866 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6867 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6868 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6870 for (int i = 0; i < 8; ++i)
6871 if (RepeatedMask[i] >= 16)
6872 BlendMask |= 1u << i;
6873 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6874 DAG.getConstant(BlendMask, DL, MVT::i8));
6880 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6881 "256-bit byte-blends require AVX2 support!");
6883 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6884 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6887 // Scale the blend by the number of bytes per element.
6888 int Scale = VT.getScalarSizeInBits() / 8;
6890 // This form of blend is always done on bytes. Compute the byte vector
6892 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6894 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6895 // mix of LLVM's code generator and the x86 backend. We tell the code
6896 // generator that boolean values in the elements of an x86 vector register
6897 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6898 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6899 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6900 // of the element (the remaining are ignored) and 0 in that high bit would
6901 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6902 // the LLVM model for boolean values in vector elements gets the relevant
6903 // bit set, it is set backwards and over constrained relative to x86's
6905 SmallVector<SDValue, 32> VSELECTMask;
6906 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6907 for (int j = 0; j < Scale; ++j)
6908 VSELECTMask.push_back(
6909 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6910 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6913 V1 = DAG.getBitcast(BlendVT, V1);
6914 V2 = DAG.getBitcast(BlendVT, V2);
6915 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6916 DAG.getNode(ISD::BUILD_VECTOR, DL,
6917 BlendVT, VSELECTMask),
6922 llvm_unreachable("Not a supported integer vector type!");
6926 /// \brief Try to lower as a blend of elements from two inputs followed by
6927 /// a single-input permutation.
6929 /// This matches the pattern where we can blend elements from two inputs and
6930 /// then reduce the shuffle to a single-input permutation.
6931 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6934 SelectionDAG &DAG) {
6935 // We build up the blend mask while checking whether a blend is a viable way
6936 // to reduce the shuffle.
6937 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6938 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6940 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6944 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6946 if (BlendMask[Mask[i] % Size] == -1)
6947 BlendMask[Mask[i] % Size] = Mask[i];
6948 else if (BlendMask[Mask[i] % Size] != Mask[i])
6949 return SDValue(); // Can't blend in the needed input!
6951 PermuteMask[i] = Mask[i] % Size;
6954 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6955 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6958 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6959 /// blends and permutes.
6961 /// This matches the extremely common pattern for handling combined
6962 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6963 /// operations. It will try to pick the best arrangement of shuffles and
6965 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6969 SelectionDAG &DAG) {
6970 // Shuffle the input elements into the desired positions in V1 and V2 and
6971 // blend them together.
6972 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6973 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6974 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6975 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6976 if (Mask[i] >= 0 && Mask[i] < Size) {
6977 V1Mask[i] = Mask[i];
6979 } else if (Mask[i] >= Size) {
6980 V2Mask[i] = Mask[i] - Size;
6981 BlendMask[i] = i + Size;
6984 // Try to lower with the simpler initial blend strategy unless one of the
6985 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6986 // shuffle may be able to fold with a load or other benefit. However, when
6987 // we'll have to do 2x as many shuffles in order to achieve this, blending
6988 // first is a better strategy.
6989 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6990 if (SDValue BlendPerm =
6991 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6994 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6995 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6996 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6999 /// \brief Try to lower a vector shuffle as a byte rotation.
7001 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7002 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7003 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7004 /// try to generically lower a vector shuffle through such an pattern. It
7005 /// does not check for the profitability of lowering either as PALIGNR or
7006 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7007 /// This matches shuffle vectors that look like:
7009 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7011 /// Essentially it concatenates V1 and V2, shifts right by some number of
7012 /// elements, and takes the low elements as the result. Note that while this is
7013 /// specified as a *right shift* because x86 is little-endian, it is a *left
7014 /// rotate* of the vector lanes.
7015 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7018 const X86Subtarget *Subtarget,
7019 SelectionDAG &DAG) {
7020 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7022 int NumElts = Mask.size();
7023 int NumLanes = VT.getSizeInBits() / 128;
7024 int NumLaneElts = NumElts / NumLanes;
7026 // We need to detect various ways of spelling a rotation:
7027 // [11, 12, 13, 14, 15, 0, 1, 2]
7028 // [-1, 12, 13, 14, -1, -1, 1, -1]
7029 // [-1, -1, -1, -1, -1, -1, 1, 2]
7030 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7031 // [-1, 4, 5, 6, -1, -1, 9, -1]
7032 // [-1, 4, 5, 6, -1, -1, -1, -1]
7035 for (int l = 0; l < NumElts; l += NumLaneElts) {
7036 for (int i = 0; i < NumLaneElts; ++i) {
7037 if (Mask[l + i] == -1)
7039 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7041 // Get the mod-Size index and lane correct it.
7042 int LaneIdx = (Mask[l + i] % NumElts) - l;
7043 // Make sure it was in this lane.
7044 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7047 // Determine where a rotated vector would have started.
7048 int StartIdx = i - LaneIdx;
7050 // The identity rotation isn't interesting, stop.
7053 // If we found the tail of a vector the rotation must be the missing
7054 // front. If we found the head of a vector, it must be how much of the
7056 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7059 Rotation = CandidateRotation;
7060 else if (Rotation != CandidateRotation)
7061 // The rotations don't match, so we can't match this mask.
7064 // Compute which value this mask is pointing at.
7065 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7067 // Compute which of the two target values this index should be assigned
7068 // to. This reflects whether the high elements are remaining or the low
7069 // elements are remaining.
7070 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7072 // Either set up this value if we've not encountered it before, or check
7073 // that it remains consistent.
7076 else if (TargetV != MaskV)
7077 // This may be a rotation, but it pulls from the inputs in some
7078 // unsupported interleaving.
7083 // Check that we successfully analyzed the mask, and normalize the results.
7084 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7085 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7091 // The actual rotate instruction rotates bytes, so we need to scale the
7092 // rotation based on how many bytes are in the vector lane.
7093 int Scale = 16 / NumLaneElts;
7095 // SSSE3 targets can use the palignr instruction.
7096 if (Subtarget->hasSSSE3()) {
7097 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7098 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7099 Lo = DAG.getBitcast(AlignVT, Lo);
7100 Hi = DAG.getBitcast(AlignVT, Hi);
7102 return DAG.getBitcast(
7103 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7104 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7107 assert(VT.getSizeInBits() == 128 &&
7108 "Rotate-based lowering only supports 128-bit lowering!");
7109 assert(Mask.size() <= 16 &&
7110 "Can shuffle at most 16 bytes in a 128-bit vector!");
7112 // Default SSE2 implementation
7113 int LoByteShift = 16 - Rotation * Scale;
7114 int HiByteShift = Rotation * Scale;
7116 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7117 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7118 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7120 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7121 DAG.getConstant(LoByteShift, DL, MVT::i8));
7122 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7123 DAG.getConstant(HiByteShift, DL, MVT::i8));
7124 return DAG.getBitcast(VT,
7125 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7128 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7130 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7131 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7132 /// matches elements from one of the input vectors shuffled to the left or
7133 /// right with zeroable elements 'shifted in'. It handles both the strictly
7134 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7137 /// PSHL : (little-endian) left bit shift.
7138 /// [ zz, 0, zz, 2 ]
7139 /// [ -1, 4, zz, -1 ]
7140 /// PSRL : (little-endian) right bit shift.
7142 /// [ -1, -1, 7, zz]
7143 /// PSLLDQ : (little-endian) left byte shift
7144 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7145 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7146 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7147 /// PSRLDQ : (little-endian) right byte shift
7148 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7149 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7150 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7151 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7152 SDValue V2, ArrayRef<int> Mask,
7153 SelectionDAG &DAG) {
7154 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7156 int Size = Mask.size();
7157 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7159 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7160 for (int i = 0; i < Size; i += Scale)
7161 for (int j = 0; j < Shift; ++j)
7162 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7168 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7169 for (int i = 0; i != Size; i += Scale) {
7170 unsigned Pos = Left ? i + Shift : i;
7171 unsigned Low = Left ? i : i + Shift;
7172 unsigned Len = Scale - Shift;
7173 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7174 Low + (V == V1 ? 0 : Size)))
7178 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7179 bool ByteShift = ShiftEltBits > 64;
7180 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7181 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7182 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7184 // Normalize the scale for byte shifts to still produce an i64 element
7186 Scale = ByteShift ? Scale / 2 : Scale;
7188 // We need to round trip through the appropriate type for the shift.
7189 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7190 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7191 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7192 "Illegal integer vector type");
7193 V = DAG.getBitcast(ShiftVT, V);
7195 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7196 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7197 return DAG.getBitcast(VT, V);
7200 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7201 // keep doubling the size of the integer elements up to that. We can
7202 // then shift the elements of the integer vector by whole multiples of
7203 // their width within the elements of the larger integer vector. Test each
7204 // multiple to see if we can find a match with the moved element indices
7205 // and that the shifted in elements are all zeroable.
7206 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7207 for (int Shift = 1; Shift != Scale; ++Shift)
7208 for (bool Left : {true, false})
7209 if (CheckZeros(Shift, Scale, Left))
7210 for (SDValue V : {V1, V2})
7211 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7218 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7219 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7220 SDValue V2, ArrayRef<int> Mask,
7221 SelectionDAG &DAG) {
7222 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7223 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7225 int Size = Mask.size();
7226 int HalfSize = Size / 2;
7227 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7229 // Upper half must be undefined.
7230 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7233 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7234 // Remainder of lower half result is zero and upper half is all undef.
7235 auto LowerAsEXTRQ = [&]() {
7236 // Determine the extraction length from the part of the
7237 // lower half that isn't zeroable.
7239 for (; Len >= 0; --Len)
7240 if (!Zeroable[Len - 1])
7242 assert(Len > 0 && "Zeroable shuffle mask");
7244 // Attempt to match first Len sequential elements from the lower half.
7247 for (int i = 0; i != Len; ++i) {
7251 SDValue &V = (M < Size ? V1 : V2);
7254 // All mask elements must be in the lower half.
7258 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7269 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7270 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7271 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7272 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7273 DAG.getConstant(BitLen, DL, MVT::i8),
7274 DAG.getConstant(BitIdx, DL, MVT::i8));
7277 if (SDValue ExtrQ = LowerAsEXTRQ())
7280 // INSERTQ: Extract lowest Len elements from lower half of second source and
7281 // insert over first source, starting at Idx.
7282 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7283 auto LowerAsInsertQ = [&]() {
7284 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7287 // Attempt to match first source from mask before insertion point.
7288 if (isUndefInRange(Mask, 0, Idx)) {
7290 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7292 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7298 // Extend the extraction length looking to match both the insertion of
7299 // the second source and the remaining elements of the first.
7300 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7305 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7307 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7313 // Match the remaining elements of the lower half.
7314 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7316 } else if ((!Base || (Base == V1)) &&
7317 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7319 } else if ((!Base || (Base == V2)) &&
7320 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7327 // We may not have a base (first source) - this can safely be undefined.
7329 Base = DAG.getUNDEF(VT);
7331 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7332 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7333 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7334 DAG.getConstant(BitLen, DL, MVT::i8),
7335 DAG.getConstant(BitIdx, DL, MVT::i8));
7342 if (SDValue InsertQ = LowerAsInsertQ())
7348 /// \brief Lower a vector shuffle as a zero or any extension.
7350 /// Given a specific number of elements, element bit width, and extension
7351 /// stride, produce either a zero or any extension based on the available
7352 /// features of the subtarget.
7353 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7354 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
7355 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7356 assert(Scale > 1 && "Need a scale to extend.");
7357 int NumElements = VT.getVectorNumElements();
7358 int EltBits = VT.getScalarSizeInBits();
7359 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7360 "Only 8, 16, and 32 bit elements can be extended.");
7361 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7363 // Found a valid zext mask! Try various lowering strategies based on the
7364 // input type and available ISA extensions.
7365 if (Subtarget->hasSSE41()) {
7366 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7367 NumElements / Scale);
7368 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7371 // For any extends we can cheat for larger element sizes and use shuffle
7372 // instructions that can fold with a load and/or copy.
7373 if (AnyExt && EltBits == 32) {
7374 int PSHUFDMask[4] = {0, -1, 1, -1};
7375 return DAG.getBitcast(
7376 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7377 DAG.getBitcast(MVT::v4i32, InputV),
7378 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7380 if (AnyExt && EltBits == 16 && Scale > 2) {
7381 int PSHUFDMask[4] = {0, -1, 0, -1};
7382 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7383 DAG.getBitcast(MVT::v4i32, InputV),
7384 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7385 int PSHUFHWMask[4] = {1, -1, -1, -1};
7386 return DAG.getBitcast(
7387 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7388 DAG.getBitcast(MVT::v8i16, InputV),
7389 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
7392 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7394 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7395 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7396 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7398 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7399 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7400 DAG.getConstant(EltBits, DL, MVT::i8),
7401 DAG.getConstant(0, DL, MVT::i8)));
7402 if (isUndefInRange(Mask, NumElements/2, NumElements/2))
7403 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7406 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7407 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7408 DAG.getConstant(EltBits, DL, MVT::i8),
7409 DAG.getConstant(EltBits, DL, MVT::i8)));
7410 return DAG.getNode(ISD::BITCAST, DL, VT,
7411 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7414 // If this would require more than 2 unpack instructions to expand, use
7415 // pshufb when available. We can only use more than 2 unpack instructions
7416 // when zero extending i8 elements which also makes it easier to use pshufb.
7417 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7418 assert(NumElements == 16 && "Unexpected byte vector width!");
7419 SDValue PSHUFBMask[16];
7420 for (int i = 0; i < 16; ++i)
7422 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
7423 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7424 return DAG.getBitcast(VT,
7425 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7426 DAG.getNode(ISD::BUILD_VECTOR, DL,
7427 MVT::v16i8, PSHUFBMask)));
7430 // Otherwise emit a sequence of unpacks.
7432 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7433 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7434 : getZeroVector(InputVT, Subtarget, DAG, DL);
7435 InputV = DAG.getBitcast(InputVT, InputV);
7436 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7440 } while (Scale > 1);
7441 return DAG.getBitcast(VT, InputV);
7444 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7446 /// This routine will try to do everything in its power to cleverly lower
7447 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7448 /// check for the profitability of this lowering, it tries to aggressively
7449 /// match this pattern. It will use all of the micro-architectural details it
7450 /// can to emit an efficient lowering. It handles both blends with all-zero
7451 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7452 /// masking out later).
7454 /// The reason we have dedicated lowering for zext-style shuffles is that they
7455 /// are both incredibly common and often quite performance sensitive.
7456 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7457 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7458 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7459 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7461 int Bits = VT.getSizeInBits();
7462 int NumElements = VT.getVectorNumElements();
7463 assert(VT.getScalarSizeInBits() <= 32 &&
7464 "Exceeds 32-bit integer zero extension limit");
7465 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7467 // Define a helper function to check a particular ext-scale and lower to it if
7469 auto Lower = [&](int Scale) -> SDValue {
7472 for (int i = 0; i < NumElements; ++i) {
7474 continue; // Valid anywhere but doesn't tell us anything.
7475 if (i % Scale != 0) {
7476 // Each of the extended elements need to be zeroable.
7480 // We no longer are in the anyext case.
7485 // Each of the base elements needs to be consecutive indices into the
7486 // same input vector.
7487 SDValue V = Mask[i] < NumElements ? V1 : V2;
7490 else if (InputV != V)
7491 return SDValue(); // Flip-flopping inputs.
7493 if (Mask[i] % NumElements != i / Scale)
7494 return SDValue(); // Non-consecutive strided elements.
7497 // If we fail to find an input, we have a zero-shuffle which should always
7498 // have already been handled.
7499 // FIXME: Maybe handle this here in case during blending we end up with one?
7503 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7504 DL, VT, Scale, AnyExt, InputV, Mask, Subtarget, DAG);
7507 // The widest scale possible for extending is to a 64-bit integer.
7508 assert(Bits % 64 == 0 &&
7509 "The number of bits in a vector must be divisible by 64 on x86!");
7510 int NumExtElements = Bits / 64;
7512 // Each iteration, try extending the elements half as much, but into twice as
7514 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7515 assert(NumElements % NumExtElements == 0 &&
7516 "The input vector size must be divisible by the extended size.");
7517 if (SDValue V = Lower(NumElements / NumExtElements))
7521 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7525 // Returns one of the source operands if the shuffle can be reduced to a
7526 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7527 auto CanZExtLowHalf = [&]() {
7528 for (int i = NumElements / 2; i != NumElements; ++i)
7531 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7533 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7538 if (SDValue V = CanZExtLowHalf()) {
7539 V = DAG.getBitcast(MVT::v2i64, V);
7540 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7541 return DAG.getBitcast(VT, V);
7544 // No viable ext lowering found.
7548 /// \brief Try to get a scalar value for a specific element of a vector.
7550 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7551 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7552 SelectionDAG &DAG) {
7553 MVT VT = V.getSimpleValueType();
7554 MVT EltVT = VT.getVectorElementType();
7555 while (V.getOpcode() == ISD::BITCAST)
7556 V = V.getOperand(0);
7557 // If the bitcasts shift the element size, we can't extract an equivalent
7559 MVT NewVT = V.getSimpleValueType();
7560 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7563 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7564 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7565 // Ensure the scalar operand is the same size as the destination.
7566 // FIXME: Add support for scalar truncation where possible.
7567 SDValue S = V.getOperand(Idx);
7568 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7569 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7575 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7577 /// This is particularly important because the set of instructions varies
7578 /// significantly based on whether the operand is a load or not.
7579 static bool isShuffleFoldableLoad(SDValue V) {
7580 while (V.getOpcode() == ISD::BITCAST)
7581 V = V.getOperand(0);
7583 return ISD::isNON_EXTLoad(V.getNode());
7586 /// \brief Try to lower insertion of a single element into a zero vector.
7588 /// This is a common pattern that we have especially efficient patterns to lower
7589 /// across all subtarget feature sets.
7590 static SDValue lowerVectorShuffleAsElementInsertion(
7591 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7593 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7595 MVT EltVT = VT.getVectorElementType();
7597 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7598 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7600 bool IsV1Zeroable = true;
7601 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7602 if (i != V2Index && !Zeroable[i]) {
7603 IsV1Zeroable = false;
7607 // Check for a single input from a SCALAR_TO_VECTOR node.
7608 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7609 // all the smarts here sunk into that routine. However, the current
7610 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7611 // vector shuffle lowering is dead.
7612 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7614 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7615 // We need to zext the scalar if it is smaller than an i32.
7616 V2S = DAG.getBitcast(EltVT, V2S);
7617 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7618 // Using zext to expand a narrow element won't work for non-zero
7623 // Zero-extend directly to i32.
7625 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7627 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7628 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7629 EltVT == MVT::i16) {
7630 // Either not inserting from the low element of the input or the input
7631 // element size is too small to use VZEXT_MOVL to clear the high bits.
7635 if (!IsV1Zeroable) {
7636 // If V1 can't be treated as a zero vector we have fewer options to lower
7637 // this. We can't support integer vectors or non-zero targets cheaply, and
7638 // the V1 elements can't be permuted in any way.
7639 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7640 if (!VT.isFloatingPoint() || V2Index != 0)
7642 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7643 V1Mask[V2Index] = -1;
7644 if (!isNoopShuffleMask(V1Mask))
7646 // This is essentially a special case blend operation, but if we have
7647 // general purpose blend operations, they are always faster. Bail and let
7648 // the rest of the lowering handle these as blends.
7649 if (Subtarget->hasSSE41())
7652 // Otherwise, use MOVSD or MOVSS.
7653 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7654 "Only two types of floating point element types to handle!");
7655 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7659 // This lowering only works for the low element with floating point vectors.
7660 if (VT.isFloatingPoint() && V2Index != 0)
7663 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7665 V2 = DAG.getBitcast(VT, V2);
7668 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7669 // the desired position. Otherwise it is more efficient to do a vector
7670 // shift left. We know that we can do a vector shift left because all
7671 // the inputs are zero.
7672 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7673 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7674 V2Shuffle[V2Index] = 0;
7675 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7677 V2 = DAG.getBitcast(MVT::v2i64, V2);
7679 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7680 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7681 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7682 DAG.getDataLayout(), VT)));
7683 V2 = DAG.getBitcast(VT, V2);
7689 /// \brief Try to lower broadcast of a single element.
7691 /// For convenience, this code also bundles all of the subtarget feature set
7692 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7693 /// a convenient way to factor it out.
7694 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7696 const X86Subtarget *Subtarget,
7697 SelectionDAG &DAG) {
7698 if (!Subtarget->hasAVX())
7700 if (VT.isInteger() && !Subtarget->hasAVX2())
7703 // Check that the mask is a broadcast.
7704 int BroadcastIdx = -1;
7706 if (M >= 0 && BroadcastIdx == -1)
7708 else if (M >= 0 && M != BroadcastIdx)
7711 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7712 "a sorted mask where the broadcast "
7715 // Go up the chain of (vector) values to find a scalar load that we can
7716 // combine with the broadcast.
7718 switch (V.getOpcode()) {
7719 case ISD::CONCAT_VECTORS: {
7720 int OperandSize = Mask.size() / V.getNumOperands();
7721 V = V.getOperand(BroadcastIdx / OperandSize);
7722 BroadcastIdx %= OperandSize;
7726 case ISD::INSERT_SUBVECTOR: {
7727 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7728 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7732 int BeginIdx = (int)ConstantIdx->getZExtValue();
7734 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7735 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7736 BroadcastIdx -= BeginIdx;
7747 // Check if this is a broadcast of a scalar. We special case lowering
7748 // for scalars so that we can more effectively fold with loads.
7749 // First, look through bitcast: if the original value has a larger element
7750 // type than the shuffle, the broadcast element is in essence truncated.
7751 // Make that explicit to ease folding.
7752 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7753 EVT EltVT = VT.getVectorElementType();
7754 SDValue V0 = V.getOperand(0);
7755 EVT V0VT = V0.getValueType();
7757 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7758 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7759 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7760 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7765 // Also check the simpler case, where we can directly reuse the scalar.
7766 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7767 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7768 V = V.getOperand(BroadcastIdx);
7770 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7771 // Only AVX2 has register broadcasts.
7772 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7774 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7775 // We can't broadcast from a vector register without AVX2, and we can only
7776 // broadcast from the zero-element of a vector register.
7780 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7783 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7784 // INSERTPS when the V1 elements are already in the correct locations
7785 // because otherwise we can just always use two SHUFPS instructions which
7786 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7787 // perform INSERTPS if a single V1 element is out of place and all V2
7788 // elements are zeroable.
7789 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7791 SelectionDAG &DAG) {
7792 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7793 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7794 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7795 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7797 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7800 int V1DstIndex = -1;
7801 int V2DstIndex = -1;
7802 bool V1UsedInPlace = false;
7804 for (int i = 0; i < 4; ++i) {
7805 // Synthesize a zero mask from the zeroable elements (includes undefs).
7811 // Flag if we use any V1 inputs in place.
7813 V1UsedInPlace = true;
7817 // We can only insert a single non-zeroable element.
7818 if (V1DstIndex != -1 || V2DstIndex != -1)
7822 // V1 input out of place for insertion.
7825 // V2 input for insertion.
7830 // Don't bother if we have no (non-zeroable) element for insertion.
7831 if (V1DstIndex == -1 && V2DstIndex == -1)
7834 // Determine element insertion src/dst indices. The src index is from the
7835 // start of the inserted vector, not the start of the concatenated vector.
7836 unsigned V2SrcIndex = 0;
7837 if (V1DstIndex != -1) {
7838 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7839 // and don't use the original V2 at all.
7840 V2SrcIndex = Mask[V1DstIndex];
7841 V2DstIndex = V1DstIndex;
7844 V2SrcIndex = Mask[V2DstIndex] - 4;
7847 // If no V1 inputs are used in place, then the result is created only from
7848 // the zero mask and the V2 insertion - so remove V1 dependency.
7850 V1 = DAG.getUNDEF(MVT::v4f32);
7852 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7853 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7855 // Insert the V2 element into the desired position.
7857 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7858 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7861 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7862 /// UNPCK instruction.
7864 /// This specifically targets cases where we end up with alternating between
7865 /// the two inputs, and so can permute them into something that feeds a single
7866 /// UNPCK instruction. Note that this routine only targets integer vectors
7867 /// because for floating point vectors we have a generalized SHUFPS lowering
7868 /// strategy that handles everything that doesn't *exactly* match an unpack,
7869 /// making this clever lowering unnecessary.
7870 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
7871 SDValue V1, SDValue V2,
7873 SelectionDAG &DAG) {
7874 assert(!VT.isFloatingPoint() &&
7875 "This routine only supports integer vectors.");
7876 assert(!isSingleInputShuffleMask(Mask) &&
7877 "This routine should only be used when blending two inputs.");
7878 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7880 int Size = Mask.size();
7882 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7883 return M >= 0 && M % Size < Size / 2;
7885 int NumHiInputs = std::count_if(
7886 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7888 bool UnpackLo = NumLoInputs >= NumHiInputs;
7890 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7891 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7892 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7894 for (int i = 0; i < Size; ++i) {
7898 // Each element of the unpack contains Scale elements from this mask.
7899 int UnpackIdx = i / Scale;
7901 // We only handle the case where V1 feeds the first slots of the unpack.
7902 // We rely on canonicalization to ensure this is the case.
7903 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7906 // Setup the mask for this input. The indexing is tricky as we have to
7907 // handle the unpack stride.
7908 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7909 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7913 // If we will have to shuffle both inputs to use the unpack, check whether
7914 // we can just unpack first and shuffle the result. If so, skip this unpack.
7915 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7916 !isNoopShuffleMask(V2Mask))
7919 // Shuffle the inputs into place.
7920 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7921 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7923 // Cast the inputs to the type we will use to unpack them.
7924 V1 = DAG.getBitcast(UnpackVT, V1);
7925 V2 = DAG.getBitcast(UnpackVT, V2);
7927 // Unpack the inputs and cast the result back to the desired type.
7928 return DAG.getBitcast(
7929 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7933 // We try each unpack from the largest to the smallest to try and find one
7934 // that fits this mask.
7935 int OrigNumElements = VT.getVectorNumElements();
7936 int OrigScalarSize = VT.getScalarSizeInBits();
7937 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7938 int Scale = ScalarSize / OrigScalarSize;
7939 int NumElements = OrigNumElements / Scale;
7940 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7941 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7945 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7947 if (NumLoInputs == 0 || NumHiInputs == 0) {
7948 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7949 "We have to have *some* inputs!");
7950 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7952 // FIXME: We could consider the total complexity of the permute of each
7953 // possible unpacking. Or at the least we should consider how many
7954 // half-crossings are created.
7955 // FIXME: We could consider commuting the unpacks.
7957 SmallVector<int, 32> PermMask;
7958 PermMask.assign(Size, -1);
7959 for (int i = 0; i < Size; ++i) {
7963 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7966 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7968 return DAG.getVectorShuffle(
7969 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7971 DAG.getUNDEF(VT), PermMask);
7977 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7979 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7980 /// support for floating point shuffles but not integer shuffles. These
7981 /// instructions will incur a domain crossing penalty on some chips though so
7982 /// it is better to avoid lowering through this for integer vectors where
7984 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7985 const X86Subtarget *Subtarget,
7986 SelectionDAG &DAG) {
7988 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7989 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7990 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7991 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7992 ArrayRef<int> Mask = SVOp->getMask();
7993 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7995 if (isSingleInputShuffleMask(Mask)) {
7996 // Use low duplicate instructions for masks that match their pattern.
7997 if (Subtarget->hasSSE3())
7998 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7999 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8001 // Straight shuffle of a single input vector. Simulate this by using the
8002 // single input as both of the "inputs" to this instruction..
8003 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8005 if (Subtarget->hasAVX()) {
8006 // If we have AVX, we can use VPERMILPS which will allow folding a load
8007 // into the shuffle.
8008 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8009 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8012 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8013 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8015 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8016 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8018 // If we have a single input, insert that into V1 if we can do so cheaply.
8019 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8020 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8021 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8023 // Try inverting the insertion since for v2 masks it is easy to do and we
8024 // can't reliably sort the mask one way or the other.
8025 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8026 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8027 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8028 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8032 // Try to use one of the special instruction patterns to handle two common
8033 // blend patterns if a zero-blend above didn't work.
8034 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8035 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8036 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8037 // We can either use a special instruction to load over the low double or
8038 // to move just the low double.
8040 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8042 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8044 if (Subtarget->hasSSE41())
8045 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8049 // Use dedicated unpack instructions for masks that match their pattern.
8050 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8051 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8052 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8053 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8055 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8056 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8057 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8060 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8062 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8063 /// the integer unit to minimize domain crossing penalties. However, for blends
8064 /// it falls back to the floating point shuffle operation with appropriate bit
8066 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8067 const X86Subtarget *Subtarget,
8068 SelectionDAG &DAG) {
8070 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8071 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8072 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8073 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8074 ArrayRef<int> Mask = SVOp->getMask();
8075 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8077 if (isSingleInputShuffleMask(Mask)) {
8078 // Check for being able to broadcast a single element.
8079 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8080 Mask, Subtarget, DAG))
8083 // Straight shuffle of a single input vector. For everything from SSE2
8084 // onward this has a single fast instruction with no scary immediates.
8085 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8086 V1 = DAG.getBitcast(MVT::v4i32, V1);
8087 int WidenedMask[4] = {
8088 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8089 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8090 return DAG.getBitcast(
8092 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8093 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8095 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8096 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8097 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8098 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8100 // If we have a blend of two PACKUS operations an the blend aligns with the
8101 // low and half halves, we can just merge the PACKUS operations. This is
8102 // particularly important as it lets us merge shuffles that this routine itself
8104 auto GetPackNode = [](SDValue V) {
8105 while (V.getOpcode() == ISD::BITCAST)
8106 V = V.getOperand(0);
8108 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8110 if (SDValue V1Pack = GetPackNode(V1))
8111 if (SDValue V2Pack = GetPackNode(V2))
8112 return DAG.getBitcast(MVT::v2i64,
8113 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8114 Mask[0] == 0 ? V1Pack.getOperand(0)
8115 : V1Pack.getOperand(1),
8116 Mask[1] == 2 ? V2Pack.getOperand(0)
8117 : V2Pack.getOperand(1)));
8119 // Try to use shift instructions.
8121 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8124 // When loading a scalar and then shuffling it into a vector we can often do
8125 // the insertion cheaply.
8126 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8127 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8129 // Try inverting the insertion since for v2 masks it is easy to do and we
8130 // can't reliably sort the mask one way or the other.
8131 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8132 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8133 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8136 // We have different paths for blend lowering, but they all must use the
8137 // *exact* same predicate.
8138 bool IsBlendSupported = Subtarget->hasSSE41();
8139 if (IsBlendSupported)
8140 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8144 // Use dedicated unpack instructions for masks that match their pattern.
8145 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8146 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8147 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8148 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8150 // Try to use byte rotation instructions.
8151 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8152 if (Subtarget->hasSSSE3())
8153 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8154 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8157 // If we have direct support for blends, we should lower by decomposing into
8158 // a permute. That will be faster than the domain cross.
8159 if (IsBlendSupported)
8160 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8163 // We implement this with SHUFPD which is pretty lame because it will likely
8164 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8165 // However, all the alternatives are still more cycles and newer chips don't
8166 // have this problem. It would be really nice if x86 had better shuffles here.
8167 V1 = DAG.getBitcast(MVT::v2f64, V1);
8168 V2 = DAG.getBitcast(MVT::v2f64, V2);
8169 return DAG.getBitcast(MVT::v2i64,
8170 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8173 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8175 /// This is used to disable more specialized lowerings when the shufps lowering
8176 /// will happen to be efficient.
8177 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8178 // This routine only handles 128-bit shufps.
8179 assert(Mask.size() == 4 && "Unsupported mask size!");
8181 // To lower with a single SHUFPS we need to have the low half and high half
8182 // each requiring a single input.
8183 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8185 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8191 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8193 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8194 /// It makes no assumptions about whether this is the *best* lowering, it simply
8196 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8197 ArrayRef<int> Mask, SDValue V1,
8198 SDValue V2, SelectionDAG &DAG) {
8199 SDValue LowV = V1, HighV = V2;
8200 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8203 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8205 if (NumV2Elements == 1) {
8207 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8210 // Compute the index adjacent to V2Index and in the same half by toggling
8212 int V2AdjIndex = V2Index ^ 1;
8214 if (Mask[V2AdjIndex] == -1) {
8215 // Handles all the cases where we have a single V2 element and an undef.
8216 // This will only ever happen in the high lanes because we commute the
8217 // vector otherwise.
8219 std::swap(LowV, HighV);
8220 NewMask[V2Index] -= 4;
8222 // Handle the case where the V2 element ends up adjacent to a V1 element.
8223 // To make this work, blend them together as the first step.
8224 int V1Index = V2AdjIndex;
8225 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8226 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8227 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8229 // Now proceed to reconstruct the final blend as we have the necessary
8230 // high or low half formed.
8237 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8238 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8240 } else if (NumV2Elements == 2) {
8241 if (Mask[0] < 4 && Mask[1] < 4) {
8242 // Handle the easy case where we have V1 in the low lanes and V2 in the
8246 } else if (Mask[2] < 4 && Mask[3] < 4) {
8247 // We also handle the reversed case because this utility may get called
8248 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8249 // arrange things in the right direction.
8255 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8256 // trying to place elements directly, just blend them and set up the final
8257 // shuffle to place them.
8259 // The first two blend mask elements are for V1, the second two are for
8261 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8262 Mask[2] < 4 ? Mask[2] : Mask[3],
8263 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8264 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8265 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8266 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8268 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8271 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8272 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8273 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8274 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8277 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8278 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8281 /// \brief Lower 4-lane 32-bit floating point shuffles.
8283 /// Uses instructions exclusively from the floating point unit to minimize
8284 /// domain crossing penalties, as these are sufficient to implement all v4f32
8286 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8287 const X86Subtarget *Subtarget,
8288 SelectionDAG &DAG) {
8290 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8291 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8292 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8293 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8294 ArrayRef<int> Mask = SVOp->getMask();
8295 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8298 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8300 if (NumV2Elements == 0) {
8301 // Check for being able to broadcast a single element.
8302 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8303 Mask, Subtarget, DAG))
8306 // Use even/odd duplicate instructions for masks that match their pattern.
8307 if (Subtarget->hasSSE3()) {
8308 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8309 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8310 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8311 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8314 if (Subtarget->hasAVX()) {
8315 // If we have AVX, we can use VPERMILPS which will allow folding a load
8316 // into the shuffle.
8317 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8318 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8321 // Otherwise, use a straight shuffle of a single input vector. We pass the
8322 // input vector to both operands to simulate this with a SHUFPS.
8323 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8324 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8327 // There are special ways we can lower some single-element blends. However, we
8328 // have custom ways we can lower more complex single-element blends below that
8329 // we defer to if both this and BLENDPS fail to match, so restrict this to
8330 // when the V2 input is targeting element 0 of the mask -- that is the fast
8332 if (NumV2Elements == 1 && Mask[0] >= 4)
8333 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8334 Mask, Subtarget, DAG))
8337 if (Subtarget->hasSSE41()) {
8338 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8342 // Use INSERTPS if we can complete the shuffle efficiently.
8343 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8346 if (!isSingleSHUFPSMask(Mask))
8347 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8348 DL, MVT::v4f32, V1, V2, Mask, DAG))
8352 // Use dedicated unpack instructions for masks that match their pattern.
8353 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8354 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8355 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8356 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8357 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8358 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8359 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8360 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8362 // Otherwise fall back to a SHUFPS lowering strategy.
8363 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8366 /// \brief Lower 4-lane i32 vector shuffles.
8368 /// We try to handle these with integer-domain shuffles where we can, but for
8369 /// blends we use the floating point domain blend instructions.
8370 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8371 const X86Subtarget *Subtarget,
8372 SelectionDAG &DAG) {
8374 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8375 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8376 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8377 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8378 ArrayRef<int> Mask = SVOp->getMask();
8379 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8381 // Whenever we can lower this as a zext, that instruction is strictly faster
8382 // than any alternative. It also allows us to fold memory operands into the
8383 // shuffle in many cases.
8384 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8385 Mask, Subtarget, DAG))
8389 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8391 if (NumV2Elements == 0) {
8392 // Check for being able to broadcast a single element.
8393 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8394 Mask, Subtarget, DAG))
8397 // Straight shuffle of a single input vector. For everything from SSE2
8398 // onward this has a single fast instruction with no scary immediates.
8399 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8400 // but we aren't actually going to use the UNPCK instruction because doing
8401 // so prevents folding a load into this instruction or making a copy.
8402 const int UnpackLoMask[] = {0, 0, 1, 1};
8403 const int UnpackHiMask[] = {2, 2, 3, 3};
8404 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8405 Mask = UnpackLoMask;
8406 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8407 Mask = UnpackHiMask;
8409 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8410 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8413 // Try to use shift instructions.
8415 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8418 // There are special ways we can lower some single-element blends.
8419 if (NumV2Elements == 1)
8420 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8421 Mask, Subtarget, DAG))
8424 // We have different paths for blend lowering, but they all must use the
8425 // *exact* same predicate.
8426 bool IsBlendSupported = Subtarget->hasSSE41();
8427 if (IsBlendSupported)
8428 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8432 if (SDValue Masked =
8433 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8436 // Use dedicated unpack instructions for masks that match their pattern.
8437 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8438 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8439 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8440 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8441 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8442 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8443 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8444 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8446 // Try to use byte rotation instructions.
8447 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8448 if (Subtarget->hasSSSE3())
8449 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8450 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8453 // If we have direct support for blends, we should lower by decomposing into
8454 // a permute. That will be faster than the domain cross.
8455 if (IsBlendSupported)
8456 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8459 // Try to lower by permuting the inputs into an unpack instruction.
8460 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8464 // We implement this with SHUFPS because it can blend from two vectors.
8465 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8466 // up the inputs, bypassing domain shift penalties that we would encur if we
8467 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8469 return DAG.getBitcast(
8471 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8472 DAG.getBitcast(MVT::v4f32, V2), Mask));
8475 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8476 /// shuffle lowering, and the most complex part.
8478 /// The lowering strategy is to try to form pairs of input lanes which are
8479 /// targeted at the same half of the final vector, and then use a dword shuffle
8480 /// to place them onto the right half, and finally unpack the paired lanes into
8481 /// their final position.
8483 /// The exact breakdown of how to form these dword pairs and align them on the
8484 /// correct sides is really tricky. See the comments within the function for
8485 /// more of the details.
8487 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8488 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8489 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8490 /// vector, form the analogous 128-bit 8-element Mask.
8491 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8492 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8493 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8494 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8495 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8497 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8498 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8499 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8501 SmallVector<int, 4> LoInputs;
8502 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8503 [](int M) { return M >= 0; });
8504 std::sort(LoInputs.begin(), LoInputs.end());
8505 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8506 SmallVector<int, 4> HiInputs;
8507 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8508 [](int M) { return M >= 0; });
8509 std::sort(HiInputs.begin(), HiInputs.end());
8510 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8512 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8513 int NumHToL = LoInputs.size() - NumLToL;
8515 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8516 int NumHToH = HiInputs.size() - NumLToH;
8517 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8518 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8519 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8520 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8522 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8523 // such inputs we can swap two of the dwords across the half mark and end up
8524 // with <=2 inputs to each half in each half. Once there, we can fall through
8525 // to the generic code below. For example:
8527 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8528 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8530 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8531 // and an existing 2-into-2 on the other half. In this case we may have to
8532 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8533 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8534 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8535 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8536 // half than the one we target for fixing) will be fixed when we re-enter this
8537 // path. We will also combine away any sequence of PSHUFD instructions that
8538 // result into a single instruction. Here is an example of the tricky case:
8540 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8541 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8543 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8545 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8546 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8548 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8549 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8551 // The result is fine to be handled by the generic logic.
8552 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8553 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8554 int AOffset, int BOffset) {
8555 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8556 "Must call this with A having 3 or 1 inputs from the A half.");
8557 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8558 "Must call this with B having 1 or 3 inputs from the B half.");
8559 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8560 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8562 bool ThreeAInputs = AToAInputs.size() == 3;
8564 // Compute the index of dword with only one word among the three inputs in
8565 // a half by taking the sum of the half with three inputs and subtracting
8566 // the sum of the actual three inputs. The difference is the remaining
8569 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8570 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8571 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8572 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8573 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8574 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8575 int TripleNonInputIdx =
8576 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8577 TripleDWord = TripleNonInputIdx / 2;
8579 // We use xor with one to compute the adjacent DWord to whichever one the
8581 OneInputDWord = (OneInput / 2) ^ 1;
8583 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8584 // and BToA inputs. If there is also such a problem with the BToB and AToB
8585 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8586 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8587 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8588 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8589 // Compute how many inputs will be flipped by swapping these DWords. We
8591 // to balance this to ensure we don't form a 3-1 shuffle in the other
8593 int NumFlippedAToBInputs =
8594 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8595 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8596 int NumFlippedBToBInputs =
8597 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8598 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8599 if ((NumFlippedAToBInputs == 1 &&
8600 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8601 (NumFlippedBToBInputs == 1 &&
8602 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8603 // We choose whether to fix the A half or B half based on whether that
8604 // half has zero flipped inputs. At zero, we may not be able to fix it
8605 // with that half. We also bias towards fixing the B half because that
8606 // will more commonly be the high half, and we have to bias one way.
8607 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8608 ArrayRef<int> Inputs) {
8609 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8610 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8611 PinnedIdx ^ 1) != Inputs.end();
8612 // Determine whether the free index is in the flipped dword or the
8613 // unflipped dword based on where the pinned index is. We use this bit
8614 // in an xor to conditionally select the adjacent dword.
8615 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8616 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8617 FixFreeIdx) != Inputs.end();
8618 if (IsFixIdxInput == IsFixFreeIdxInput)
8620 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8621 FixFreeIdx) != Inputs.end();
8622 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8623 "We need to be changing the number of flipped inputs!");
8624 int PSHUFHalfMask[] = {0, 1, 2, 3};
8625 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8626 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8628 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8631 if (M != -1 && M == FixIdx)
8633 else if (M != -1 && M == FixFreeIdx)
8636 if (NumFlippedBToBInputs != 0) {
8638 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8639 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8641 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8642 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8643 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8648 int PSHUFDMask[] = {0, 1, 2, 3};
8649 PSHUFDMask[ADWord] = BDWord;
8650 PSHUFDMask[BDWord] = ADWord;
8653 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8654 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8656 // Adjust the mask to match the new locations of A and B.
8658 if (M != -1 && M/2 == ADWord)
8659 M = 2 * BDWord + M % 2;
8660 else if (M != -1 && M/2 == BDWord)
8661 M = 2 * ADWord + M % 2;
8663 // Recurse back into this routine to re-compute state now that this isn't
8664 // a 3 and 1 problem.
8665 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8668 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8669 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8670 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8671 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8673 // At this point there are at most two inputs to the low and high halves from
8674 // each half. That means the inputs can always be grouped into dwords and
8675 // those dwords can then be moved to the correct half with a dword shuffle.
8676 // We use at most one low and one high word shuffle to collect these paired
8677 // inputs into dwords, and finally a dword shuffle to place them.
8678 int PSHUFLMask[4] = {-1, -1, -1, -1};
8679 int PSHUFHMask[4] = {-1, -1, -1, -1};
8680 int PSHUFDMask[4] = {-1, -1, -1, -1};
8682 // First fix the masks for all the inputs that are staying in their
8683 // original halves. This will then dictate the targets of the cross-half
8685 auto fixInPlaceInputs =
8686 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8687 MutableArrayRef<int> SourceHalfMask,
8688 MutableArrayRef<int> HalfMask, int HalfOffset) {
8689 if (InPlaceInputs.empty())
8691 if (InPlaceInputs.size() == 1) {
8692 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8693 InPlaceInputs[0] - HalfOffset;
8694 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8697 if (IncomingInputs.empty()) {
8698 // Just fix all of the in place inputs.
8699 for (int Input : InPlaceInputs) {
8700 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8701 PSHUFDMask[Input / 2] = Input / 2;
8706 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8707 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8708 InPlaceInputs[0] - HalfOffset;
8709 // Put the second input next to the first so that they are packed into
8710 // a dword. We find the adjacent index by toggling the low bit.
8711 int AdjIndex = InPlaceInputs[0] ^ 1;
8712 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8713 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8714 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8716 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8717 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8719 // Now gather the cross-half inputs and place them into a free dword of
8720 // their target half.
8721 // FIXME: This operation could almost certainly be simplified dramatically to
8722 // look more like the 3-1 fixing operation.
8723 auto moveInputsToRightHalf = [&PSHUFDMask](
8724 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8725 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8726 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8728 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8729 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8731 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8733 int LowWord = Word & ~1;
8734 int HighWord = Word | 1;
8735 return isWordClobbered(SourceHalfMask, LowWord) ||
8736 isWordClobbered(SourceHalfMask, HighWord);
8739 if (IncomingInputs.empty())
8742 if (ExistingInputs.empty()) {
8743 // Map any dwords with inputs from them into the right half.
8744 for (int Input : IncomingInputs) {
8745 // If the source half mask maps over the inputs, turn those into
8746 // swaps and use the swapped lane.
8747 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8748 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8749 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8750 Input - SourceOffset;
8751 // We have to swap the uses in our half mask in one sweep.
8752 for (int &M : HalfMask)
8753 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8755 else if (M == Input)
8756 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8758 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8759 Input - SourceOffset &&
8760 "Previous placement doesn't match!");
8762 // Note that this correctly re-maps both when we do a swap and when
8763 // we observe the other side of the swap above. We rely on that to
8764 // avoid swapping the members of the input list directly.
8765 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8768 // Map the input's dword into the correct half.
8769 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8770 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8772 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8774 "Previous placement doesn't match!");
8777 // And just directly shift any other-half mask elements to be same-half
8778 // as we will have mirrored the dword containing the element into the
8779 // same position within that half.
8780 for (int &M : HalfMask)
8781 if (M >= SourceOffset && M < SourceOffset + 4) {
8782 M = M - SourceOffset + DestOffset;
8783 assert(M >= 0 && "This should never wrap below zero!");
8788 // Ensure we have the input in a viable dword of its current half. This
8789 // is particularly tricky because the original position may be clobbered
8790 // by inputs being moved and *staying* in that half.
8791 if (IncomingInputs.size() == 1) {
8792 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8793 int InputFixed = std::find(std::begin(SourceHalfMask),
8794 std::end(SourceHalfMask), -1) -
8795 std::begin(SourceHalfMask) + SourceOffset;
8796 SourceHalfMask[InputFixed - SourceOffset] =
8797 IncomingInputs[0] - SourceOffset;
8798 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8800 IncomingInputs[0] = InputFixed;
8802 } else if (IncomingInputs.size() == 2) {
8803 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8804 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8805 // We have two non-adjacent or clobbered inputs we need to extract from
8806 // the source half. To do this, we need to map them into some adjacent
8807 // dword slot in the source mask.
8808 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8809 IncomingInputs[1] - SourceOffset};
8811 // If there is a free slot in the source half mask adjacent to one of
8812 // the inputs, place the other input in it. We use (Index XOR 1) to
8813 // compute an adjacent index.
8814 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8815 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8816 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8817 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8818 InputsFixed[1] = InputsFixed[0] ^ 1;
8819 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8820 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8821 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8822 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8823 InputsFixed[0] = InputsFixed[1] ^ 1;
8824 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8825 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8826 // The two inputs are in the same DWord but it is clobbered and the
8827 // adjacent DWord isn't used at all. Move both inputs to the free
8829 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8830 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8831 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8832 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8834 // The only way we hit this point is if there is no clobbering
8835 // (because there are no off-half inputs to this half) and there is no
8836 // free slot adjacent to one of the inputs. In this case, we have to
8837 // swap an input with a non-input.
8838 for (int i = 0; i < 4; ++i)
8839 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8840 "We can't handle any clobbers here!");
8841 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8842 "Cannot have adjacent inputs here!");
8844 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8845 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8847 // We also have to update the final source mask in this case because
8848 // it may need to undo the above swap.
8849 for (int &M : FinalSourceHalfMask)
8850 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8851 M = InputsFixed[1] + SourceOffset;
8852 else if (M == InputsFixed[1] + SourceOffset)
8853 M = (InputsFixed[0] ^ 1) + SourceOffset;
8855 InputsFixed[1] = InputsFixed[0] ^ 1;
8858 // Point everything at the fixed inputs.
8859 for (int &M : HalfMask)
8860 if (M == IncomingInputs[0])
8861 M = InputsFixed[0] + SourceOffset;
8862 else if (M == IncomingInputs[1])
8863 M = InputsFixed[1] + SourceOffset;
8865 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8866 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8869 llvm_unreachable("Unhandled input size!");
8872 // Now hoist the DWord down to the right half.
8873 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8874 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8875 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8876 for (int &M : HalfMask)
8877 for (int Input : IncomingInputs)
8879 M = FreeDWord * 2 + Input % 2;
8881 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8882 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8883 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8884 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8886 // Now enact all the shuffles we've computed to move the inputs into their
8888 if (!isNoopShuffleMask(PSHUFLMask))
8889 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8890 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8891 if (!isNoopShuffleMask(PSHUFHMask))
8892 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8893 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8894 if (!isNoopShuffleMask(PSHUFDMask))
8897 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8898 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8900 // At this point, each half should contain all its inputs, and we can then
8901 // just shuffle them into their final position.
8902 assert(std::count_if(LoMask.begin(), LoMask.end(),
8903 [](int M) { return M >= 4; }) == 0 &&
8904 "Failed to lift all the high half inputs to the low mask!");
8905 assert(std::count_if(HiMask.begin(), HiMask.end(),
8906 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8907 "Failed to lift all the low half inputs to the high mask!");
8909 // Do a half shuffle for the low mask.
8910 if (!isNoopShuffleMask(LoMask))
8911 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8912 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8914 // Do a half shuffle with the high mask after shifting its values down.
8915 for (int &M : HiMask)
8918 if (!isNoopShuffleMask(HiMask))
8919 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8920 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8925 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8926 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8927 SDValue V2, ArrayRef<int> Mask,
8928 SelectionDAG &DAG, bool &V1InUse,
8930 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8936 int Size = Mask.size();
8937 int Scale = 16 / Size;
8938 for (int i = 0; i < 16; ++i) {
8939 if (Mask[i / Scale] == -1) {
8940 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8942 const int ZeroMask = 0x80;
8943 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8945 int V2Idx = Mask[i / Scale] < Size
8947 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8948 if (Zeroable[i / Scale])
8949 V1Idx = V2Idx = ZeroMask;
8950 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8951 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8952 V1InUse |= (ZeroMask != V1Idx);
8953 V2InUse |= (ZeroMask != V2Idx);
8958 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8959 DAG.getBitcast(MVT::v16i8, V1),
8960 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8962 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8963 DAG.getBitcast(MVT::v16i8, V2),
8964 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8966 // If we need shuffled inputs from both, blend the two.
8968 if (V1InUse && V2InUse)
8969 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8971 V = V1InUse ? V1 : V2;
8973 // Cast the result back to the correct type.
8974 return DAG.getBitcast(VT, V);
8977 /// \brief Generic lowering of 8-lane i16 shuffles.
8979 /// This handles both single-input shuffles and combined shuffle/blends with
8980 /// two inputs. The single input shuffles are immediately delegated to
8981 /// a dedicated lowering routine.
8983 /// The blends are lowered in one of three fundamental ways. If there are few
8984 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8985 /// of the input is significantly cheaper when lowered as an interleaving of
8986 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8987 /// halves of the inputs separately (making them have relatively few inputs)
8988 /// and then concatenate them.
8989 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8990 const X86Subtarget *Subtarget,
8991 SelectionDAG &DAG) {
8993 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8994 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8995 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8997 ArrayRef<int> OrigMask = SVOp->getMask();
8998 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8999 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9000 MutableArrayRef<int> Mask(MaskStorage);
9002 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9004 // Whenever we can lower this as a zext, that instruction is strictly faster
9005 // than any alternative.
9006 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9007 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9010 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9012 auto isV2 = [](int M) { return M >= 8; };
9014 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9016 if (NumV2Inputs == 0) {
9017 // Check for being able to broadcast a single element.
9018 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9019 Mask, Subtarget, DAG))
9022 // Try to use shift instructions.
9024 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9027 // Use dedicated unpack instructions for masks that match their pattern.
9028 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9029 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9030 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9031 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9033 // Try to use byte rotation instructions.
9034 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9035 Mask, Subtarget, DAG))
9038 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9042 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9043 "All single-input shuffles should be canonicalized to be V1-input "
9046 // Try to use shift instructions.
9048 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9051 // See if we can use SSE4A Extraction / Insertion.
9052 if (Subtarget->hasSSE4A())
9053 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9056 // There are special ways we can lower some single-element blends.
9057 if (NumV2Inputs == 1)
9058 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9059 Mask, Subtarget, DAG))
9062 // We have different paths for blend lowering, but they all must use the
9063 // *exact* same predicate.
9064 bool IsBlendSupported = Subtarget->hasSSE41();
9065 if (IsBlendSupported)
9066 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9070 if (SDValue Masked =
9071 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9074 // Use dedicated unpack instructions for masks that match their pattern.
9075 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9076 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9077 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9078 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9080 // Try to use byte rotation instructions.
9081 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9082 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9085 if (SDValue BitBlend =
9086 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9089 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9093 // If we can't directly blend but can use PSHUFB, that will be better as it
9094 // can both shuffle and set up the inefficient blend.
9095 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9096 bool V1InUse, V2InUse;
9097 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9101 // We can always bit-blend if we have to so the fallback strategy is to
9102 // decompose into single-input permutes and blends.
9103 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9107 /// \brief Check whether a compaction lowering can be done by dropping even
9108 /// elements and compute how many times even elements must be dropped.
9110 /// This handles shuffles which take every Nth element where N is a power of
9111 /// two. Example shuffle masks:
9113 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9114 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9115 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9116 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9117 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9118 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9120 /// Any of these lanes can of course be undef.
9122 /// This routine only supports N <= 3.
9123 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9126 /// \returns N above, or the number of times even elements must be dropped if
9127 /// there is such a number. Otherwise returns zero.
9128 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9129 // Figure out whether we're looping over two inputs or just one.
9130 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9132 // The modulus for the shuffle vector entries is based on whether this is
9133 // a single input or not.
9134 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9135 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9136 "We should only be called with masks with a power-of-2 size!");
9138 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9140 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9141 // and 2^3 simultaneously. This is because we may have ambiguity with
9142 // partially undef inputs.
9143 bool ViableForN[3] = {true, true, true};
9145 for (int i = 0, e = Mask.size(); i < e; ++i) {
9146 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9151 bool IsAnyViable = false;
9152 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9153 if (ViableForN[j]) {
9156 // The shuffle mask must be equal to (i * 2^N) % M.
9157 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9160 ViableForN[j] = false;
9162 // Early exit if we exhaust the possible powers of two.
9167 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9171 // Return 0 as there is no viable power of two.
9175 /// \brief Generic lowering of v16i8 shuffles.
9177 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9178 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9179 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9180 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9182 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9183 const X86Subtarget *Subtarget,
9184 SelectionDAG &DAG) {
9186 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9187 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9188 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9189 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9190 ArrayRef<int> Mask = SVOp->getMask();
9191 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9193 // Try to use shift instructions.
9195 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9198 // Try to use byte rotation instructions.
9199 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9200 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9203 // Try to use a zext lowering.
9204 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9205 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9208 // See if we can use SSE4A Extraction / Insertion.
9209 if (Subtarget->hasSSE4A())
9210 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9214 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9216 // For single-input shuffles, there are some nicer lowering tricks we can use.
9217 if (NumV2Elements == 0) {
9218 // Check for being able to broadcast a single element.
9219 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9220 Mask, Subtarget, DAG))
9223 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9224 // Notably, this handles splat and partial-splat shuffles more efficiently.
9225 // However, it only makes sense if the pre-duplication shuffle simplifies
9226 // things significantly. Currently, this means we need to be able to
9227 // express the pre-duplication shuffle as an i16 shuffle.
9229 // FIXME: We should check for other patterns which can be widened into an
9230 // i16 shuffle as well.
9231 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9232 for (int i = 0; i < 16; i += 2)
9233 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9238 auto tryToWidenViaDuplication = [&]() -> SDValue {
9239 if (!canWidenViaDuplication(Mask))
9241 SmallVector<int, 4> LoInputs;
9242 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9243 [](int M) { return M >= 0 && M < 8; });
9244 std::sort(LoInputs.begin(), LoInputs.end());
9245 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9247 SmallVector<int, 4> HiInputs;
9248 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9249 [](int M) { return M >= 8; });
9250 std::sort(HiInputs.begin(), HiInputs.end());
9251 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9254 bool TargetLo = LoInputs.size() >= HiInputs.size();
9255 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9256 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9258 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9259 SmallDenseMap<int, int, 8> LaneMap;
9260 for (int I : InPlaceInputs) {
9261 PreDupI16Shuffle[I/2] = I/2;
9264 int j = TargetLo ? 0 : 4, je = j + 4;
9265 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9266 // Check if j is already a shuffle of this input. This happens when
9267 // there are two adjacent bytes after we move the low one.
9268 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9269 // If we haven't yet mapped the input, search for a slot into which
9271 while (j < je && PreDupI16Shuffle[j] != -1)
9275 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9278 // Map this input with the i16 shuffle.
9279 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9282 // Update the lane map based on the mapping we ended up with.
9283 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9285 V1 = DAG.getBitcast(
9287 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9288 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9290 // Unpack the bytes to form the i16s that will be shuffled into place.
9291 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9292 MVT::v16i8, V1, V1);
9294 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9295 for (int i = 0; i < 16; ++i)
9296 if (Mask[i] != -1) {
9297 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9298 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9299 if (PostDupI16Shuffle[i / 2] == -1)
9300 PostDupI16Shuffle[i / 2] = MappedMask;
9302 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9303 "Conflicting entrties in the original shuffle!");
9305 return DAG.getBitcast(
9307 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9308 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9310 if (SDValue V = tryToWidenViaDuplication())
9314 if (SDValue Masked =
9315 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9318 // Use dedicated unpack instructions for masks that match their pattern.
9319 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9320 0, 16, 1, 17, 2, 18, 3, 19,
9322 4, 20, 5, 21, 6, 22, 7, 23}))
9323 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9324 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9325 8, 24, 9, 25, 10, 26, 11, 27,
9327 12, 28, 13, 29, 14, 30, 15, 31}))
9328 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9330 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9331 // with PSHUFB. It is important to do this before we attempt to generate any
9332 // blends but after all of the single-input lowerings. If the single input
9333 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9334 // want to preserve that and we can DAG combine any longer sequences into
9335 // a PSHUFB in the end. But once we start blending from multiple inputs,
9336 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9337 // and there are *very* few patterns that would actually be faster than the
9338 // PSHUFB approach because of its ability to zero lanes.
9340 // FIXME: The only exceptions to the above are blends which are exact
9341 // interleavings with direct instructions supporting them. We currently don't
9342 // handle those well here.
9343 if (Subtarget->hasSSSE3()) {
9344 bool V1InUse = false;
9345 bool V2InUse = false;
9347 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9348 DAG, V1InUse, V2InUse);
9350 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9351 // do so. This avoids using them to handle blends-with-zero which is
9352 // important as a single pshufb is significantly faster for that.
9353 if (V1InUse && V2InUse) {
9354 if (Subtarget->hasSSE41())
9355 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9356 Mask, Subtarget, DAG))
9359 // We can use an unpack to do the blending rather than an or in some
9360 // cases. Even though the or may be (very minorly) more efficient, we
9361 // preference this lowering because there are common cases where part of
9362 // the complexity of the shuffles goes away when we do the final blend as
9364 // FIXME: It might be worth trying to detect if the unpack-feeding
9365 // shuffles will both be pshufb, in which case we shouldn't bother with
9367 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9368 DL, MVT::v16i8, V1, V2, Mask, DAG))
9375 // There are special ways we can lower some single-element blends.
9376 if (NumV2Elements == 1)
9377 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9378 Mask, Subtarget, DAG))
9381 if (SDValue BitBlend =
9382 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9385 // Check whether a compaction lowering can be done. This handles shuffles
9386 // which take every Nth element for some even N. See the helper function for
9389 // We special case these as they can be particularly efficiently handled with
9390 // the PACKUSB instruction on x86 and they show up in common patterns of
9391 // rearranging bytes to truncate wide elements.
9392 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9393 // NumEvenDrops is the power of two stride of the elements. Another way of
9394 // thinking about it is that we need to drop the even elements this many
9395 // times to get the original input.
9396 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9398 // First we need to zero all the dropped bytes.
9399 assert(NumEvenDrops <= 3 &&
9400 "No support for dropping even elements more than 3 times.");
9401 // We use the mask type to pick which bytes are preserved based on how many
9402 // elements are dropped.
9403 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9404 SDValue ByteClearMask = DAG.getBitcast(
9405 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9406 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9408 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9410 // Now pack things back together.
9411 V1 = DAG.getBitcast(MVT::v8i16, V1);
9412 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9413 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9414 for (int i = 1; i < NumEvenDrops; ++i) {
9415 Result = DAG.getBitcast(MVT::v8i16, Result);
9416 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9422 // Handle multi-input cases by blending single-input shuffles.
9423 if (NumV2Elements > 0)
9424 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9427 // The fallback path for single-input shuffles widens this into two v8i16
9428 // vectors with unpacks, shuffles those, and then pulls them back together
9432 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9433 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9434 for (int i = 0; i < 16; ++i)
9436 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9438 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9440 SDValue VLoHalf, VHiHalf;
9441 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9442 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9444 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9445 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9446 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9447 [](int M) { return M >= 0 && M % 2 == 1; })) {
9448 // Use a mask to drop the high bytes.
9449 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9450 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9451 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9453 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9454 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9456 // Squash the masks to point directly into VLoHalf.
9457 for (int &M : LoBlendMask)
9460 for (int &M : HiBlendMask)
9464 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9465 // VHiHalf so that we can blend them as i16s.
9466 VLoHalf = DAG.getBitcast(
9467 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9468 VHiHalf = DAG.getBitcast(
9469 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9472 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9473 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9475 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9478 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9480 /// This routine breaks down the specific type of 128-bit shuffle and
9481 /// dispatches to the lowering routines accordingly.
9482 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9483 MVT VT, const X86Subtarget *Subtarget,
9484 SelectionDAG &DAG) {
9485 switch (VT.SimpleTy) {
9487 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9489 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9491 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9493 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9495 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9497 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9500 llvm_unreachable("Unimplemented!");
9504 /// \brief Helper function to test whether a shuffle mask could be
9505 /// simplified by widening the elements being shuffled.
9507 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9508 /// leaves it in an unspecified state.
9510 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9511 /// shuffle masks. The latter have the special property of a '-2' representing
9512 /// a zero-ed lane of a vector.
9513 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9514 SmallVectorImpl<int> &WidenedMask) {
9515 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9516 // If both elements are undef, its trivial.
9517 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9518 WidenedMask.push_back(SM_SentinelUndef);
9522 // Check for an undef mask and a mask value properly aligned to fit with
9523 // a pair of values. If we find such a case, use the non-undef mask's value.
9524 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9525 WidenedMask.push_back(Mask[i + 1] / 2);
9528 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9529 WidenedMask.push_back(Mask[i] / 2);
9533 // When zeroing, we need to spread the zeroing across both lanes to widen.
9534 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9535 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9536 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9537 WidenedMask.push_back(SM_SentinelZero);
9543 // Finally check if the two mask values are adjacent and aligned with
9545 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9546 WidenedMask.push_back(Mask[i] / 2);
9550 // Otherwise we can't safely widen the elements used in this shuffle.
9553 assert(WidenedMask.size() == Mask.size() / 2 &&
9554 "Incorrect size of mask after widening the elements!");
9559 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9561 /// This routine just extracts two subvectors, shuffles them independently, and
9562 /// then concatenates them back together. This should work effectively with all
9563 /// AVX vector shuffle types.
9564 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9565 SDValue V2, ArrayRef<int> Mask,
9566 SelectionDAG &DAG) {
9567 assert(VT.getSizeInBits() >= 256 &&
9568 "Only for 256-bit or wider vector shuffles!");
9569 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9570 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9572 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9573 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9575 int NumElements = VT.getVectorNumElements();
9576 int SplitNumElements = NumElements / 2;
9577 MVT ScalarVT = VT.getScalarType();
9578 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9580 // Rather than splitting build-vectors, just build two narrower build
9581 // vectors. This helps shuffling with splats and zeros.
9582 auto SplitVector = [&](SDValue V) {
9583 while (V.getOpcode() == ISD::BITCAST)
9584 V = V->getOperand(0);
9586 MVT OrigVT = V.getSimpleValueType();
9587 int OrigNumElements = OrigVT.getVectorNumElements();
9588 int OrigSplitNumElements = OrigNumElements / 2;
9589 MVT OrigScalarVT = OrigVT.getScalarType();
9590 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9594 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9596 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9597 DAG.getIntPtrConstant(0, DL));
9598 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9599 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9602 SmallVector<SDValue, 16> LoOps, HiOps;
9603 for (int i = 0; i < OrigSplitNumElements; ++i) {
9604 LoOps.push_back(BV->getOperand(i));
9605 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9607 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9608 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9610 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9611 DAG.getBitcast(SplitVT, HiV));
9614 SDValue LoV1, HiV1, LoV2, HiV2;
9615 std::tie(LoV1, HiV1) = SplitVector(V1);
9616 std::tie(LoV2, HiV2) = SplitVector(V2);
9618 // Now create two 4-way blends of these half-width vectors.
9619 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9620 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9621 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9622 for (int i = 0; i < SplitNumElements; ++i) {
9623 int M = HalfMask[i];
9624 if (M >= NumElements) {
9625 if (M >= NumElements + SplitNumElements)
9629 V2BlendMask.push_back(M - NumElements);
9630 V1BlendMask.push_back(-1);
9631 BlendMask.push_back(SplitNumElements + i);
9632 } else if (M >= 0) {
9633 if (M >= SplitNumElements)
9637 V2BlendMask.push_back(-1);
9638 V1BlendMask.push_back(M);
9639 BlendMask.push_back(i);
9641 V2BlendMask.push_back(-1);
9642 V1BlendMask.push_back(-1);
9643 BlendMask.push_back(-1);
9647 // Because the lowering happens after all combining takes place, we need to
9648 // manually combine these blend masks as much as possible so that we create
9649 // a minimal number of high-level vector shuffle nodes.
9651 // First try just blending the halves of V1 or V2.
9652 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9653 return DAG.getUNDEF(SplitVT);
9654 if (!UseLoV2 && !UseHiV2)
9655 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9656 if (!UseLoV1 && !UseHiV1)
9657 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9659 SDValue V1Blend, V2Blend;
9660 if (UseLoV1 && UseHiV1) {
9662 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9664 // We only use half of V1 so map the usage down into the final blend mask.
9665 V1Blend = UseLoV1 ? LoV1 : HiV1;
9666 for (int i = 0; i < SplitNumElements; ++i)
9667 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9668 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9670 if (UseLoV2 && UseHiV2) {
9672 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9674 // We only use half of V2 so map the usage down into the final blend mask.
9675 V2Blend = UseLoV2 ? LoV2 : HiV2;
9676 for (int i = 0; i < SplitNumElements; ++i)
9677 if (BlendMask[i] >= SplitNumElements)
9678 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9680 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9682 SDValue Lo = HalfBlend(LoMask);
9683 SDValue Hi = HalfBlend(HiMask);
9684 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9687 /// \brief Either split a vector in halves or decompose the shuffles and the
9690 /// This is provided as a good fallback for many lowerings of non-single-input
9691 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9692 /// between splitting the shuffle into 128-bit components and stitching those
9693 /// back together vs. extracting the single-input shuffles and blending those
9695 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9696 SDValue V2, ArrayRef<int> Mask,
9697 SelectionDAG &DAG) {
9698 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9699 "lower single-input shuffles as it "
9700 "could then recurse on itself.");
9701 int Size = Mask.size();
9703 // If this can be modeled as a broadcast of two elements followed by a blend,
9704 // prefer that lowering. This is especially important because broadcasts can
9705 // often fold with memory operands.
9706 auto DoBothBroadcast = [&] {
9707 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9710 if (V2BroadcastIdx == -1)
9711 V2BroadcastIdx = M - Size;
9712 else if (M - Size != V2BroadcastIdx)
9714 } else if (M >= 0) {
9715 if (V1BroadcastIdx == -1)
9717 else if (M != V1BroadcastIdx)
9722 if (DoBothBroadcast())
9723 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9726 // If the inputs all stem from a single 128-bit lane of each input, then we
9727 // split them rather than blending because the split will decompose to
9728 // unusually few instructions.
9729 int LaneCount = VT.getSizeInBits() / 128;
9730 int LaneSize = Size / LaneCount;
9731 SmallBitVector LaneInputs[2];
9732 LaneInputs[0].resize(LaneCount, false);
9733 LaneInputs[1].resize(LaneCount, false);
9734 for (int i = 0; i < Size; ++i)
9736 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9737 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9738 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9740 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9741 // that the decomposed single-input shuffles don't end up here.
9742 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9745 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9746 /// a permutation and blend of those lanes.
9748 /// This essentially blends the out-of-lane inputs to each lane into the lane
9749 /// from a permuted copy of the vector. This lowering strategy results in four
9750 /// instructions in the worst case for a single-input cross lane shuffle which
9751 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9752 /// of. Special cases for each particular shuffle pattern should be handled
9753 /// prior to trying this lowering.
9754 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9755 SDValue V1, SDValue V2,
9757 SelectionDAG &DAG) {
9758 // FIXME: This should probably be generalized for 512-bit vectors as well.
9759 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9760 int LaneSize = Mask.size() / 2;
9762 // If there are only inputs from one 128-bit lane, splitting will in fact be
9763 // less expensive. The flags track whether the given lane contains an element
9764 // that crosses to another lane.
9765 bool LaneCrossing[2] = {false, false};
9766 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9767 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9768 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9769 if (!LaneCrossing[0] || !LaneCrossing[1])
9770 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9772 if (isSingleInputShuffleMask(Mask)) {
9773 SmallVector<int, 32> FlippedBlendMask;
9774 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9775 FlippedBlendMask.push_back(
9776 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9778 : Mask[i] % LaneSize +
9779 (i / LaneSize) * LaneSize + Size));
9781 // Flip the vector, and blend the results which should now be in-lane. The
9782 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9783 // 5 for the high source. The value 3 selects the high half of source 2 and
9784 // the value 2 selects the low half of source 2. We only use source 2 to
9785 // allow folding it into a memory operand.
9786 unsigned PERMMask = 3 | 2 << 4;
9787 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9788 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9789 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9792 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9793 // will be handled by the above logic and a blend of the results, much like
9794 // other patterns in AVX.
9795 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9798 /// \brief Handle lowering 2-lane 128-bit shuffles.
9799 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9800 SDValue V2, ArrayRef<int> Mask,
9801 const X86Subtarget *Subtarget,
9802 SelectionDAG &DAG) {
9803 // TODO: If minimizing size and one of the inputs is a zero vector and the
9804 // the zero vector has only one use, we could use a VPERM2X128 to save the
9805 // instruction bytes needed to explicitly generate the zero vector.
9807 // Blends are faster and handle all the non-lane-crossing cases.
9808 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9812 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9813 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9815 // If either input operand is a zero vector, use VPERM2X128 because its mask
9816 // allows us to replace the zero input with an implicit zero.
9817 if (!IsV1Zero && !IsV2Zero) {
9818 // Check for patterns which can be matched with a single insert of a 128-bit
9820 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9821 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9822 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9823 VT.getVectorNumElements() / 2);
9824 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9825 DAG.getIntPtrConstant(0, DL));
9826 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9827 OnlyUsesV1 ? V1 : V2,
9828 DAG.getIntPtrConstant(0, DL));
9829 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9833 // Otherwise form a 128-bit permutation. After accounting for undefs,
9834 // convert the 64-bit shuffle mask selection values into 128-bit
9835 // selection bits by dividing the indexes by 2 and shifting into positions
9836 // defined by a vperm2*128 instruction's immediate control byte.
9838 // The immediate permute control byte looks like this:
9839 // [1:0] - select 128 bits from sources for low half of destination
9841 // [3] - zero low half of destination
9842 // [5:4] - select 128 bits from sources for high half of destination
9844 // [7] - zero high half of destination
9846 int MaskLO = Mask[0];
9847 if (MaskLO == SM_SentinelUndef)
9848 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9850 int MaskHI = Mask[2];
9851 if (MaskHI == SM_SentinelUndef)
9852 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9854 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9856 // If either input is a zero vector, replace it with an undef input.
9857 // Shuffle mask values < 4 are selecting elements of V1.
9858 // Shuffle mask values >= 4 are selecting elements of V2.
9859 // Adjust each half of the permute mask by clearing the half that was
9860 // selecting the zero vector and setting the zero mask bit.
9862 V1 = DAG.getUNDEF(VT);
9864 PermMask = (PermMask & 0xf0) | 0x08;
9866 PermMask = (PermMask & 0x0f) | 0x80;
9869 V2 = DAG.getUNDEF(VT);
9871 PermMask = (PermMask & 0xf0) | 0x08;
9873 PermMask = (PermMask & 0x0f) | 0x80;
9876 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9877 DAG.getConstant(PermMask, DL, MVT::i8));
9880 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9881 /// shuffling each lane.
9883 /// This will only succeed when the result of fixing the 128-bit lanes results
9884 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9885 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9886 /// the lane crosses early and then use simpler shuffles within each lane.
9888 /// FIXME: It might be worthwhile at some point to support this without
9889 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9890 /// in x86 only floating point has interesting non-repeating shuffles, and even
9891 /// those are still *marginally* more expensive.
9892 static SDValue lowerVectorShuffleByMerging128BitLanes(
9893 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9894 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9895 assert(!isSingleInputShuffleMask(Mask) &&
9896 "This is only useful with multiple inputs.");
9898 int Size = Mask.size();
9899 int LaneSize = 128 / VT.getScalarSizeInBits();
9900 int NumLanes = Size / LaneSize;
9901 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9903 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9904 // check whether the in-128-bit lane shuffles share a repeating pattern.
9905 SmallVector<int, 4> Lanes;
9906 Lanes.resize(NumLanes, -1);
9907 SmallVector<int, 4> InLaneMask;
9908 InLaneMask.resize(LaneSize, -1);
9909 for (int i = 0; i < Size; ++i) {
9913 int j = i / LaneSize;
9916 // First entry we've seen for this lane.
9917 Lanes[j] = Mask[i] / LaneSize;
9918 } else if (Lanes[j] != Mask[i] / LaneSize) {
9919 // This doesn't match the lane selected previously!
9923 // Check that within each lane we have a consistent shuffle mask.
9924 int k = i % LaneSize;
9925 if (InLaneMask[k] < 0) {
9926 InLaneMask[k] = Mask[i] % LaneSize;
9927 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9928 // This doesn't fit a repeating in-lane mask.
9933 // First shuffle the lanes into place.
9934 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9935 VT.getSizeInBits() / 64);
9936 SmallVector<int, 8> LaneMask;
9937 LaneMask.resize(NumLanes * 2, -1);
9938 for (int i = 0; i < NumLanes; ++i)
9939 if (Lanes[i] >= 0) {
9940 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9941 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9944 V1 = DAG.getBitcast(LaneVT, V1);
9945 V2 = DAG.getBitcast(LaneVT, V2);
9946 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9948 // Cast it back to the type we actually want.
9949 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9951 // Now do a simple shuffle that isn't lane crossing.
9952 SmallVector<int, 8> NewMask;
9953 NewMask.resize(Size, -1);
9954 for (int i = 0; i < Size; ++i)
9956 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9957 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9958 "Must not introduce lane crosses at this point!");
9960 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9963 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9966 /// This returns true if the elements from a particular input are already in the
9967 /// slot required by the given mask and require no permutation.
9968 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9969 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9970 int Size = Mask.size();
9971 for (int i = 0; i < Size; ++i)
9972 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9978 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9979 ArrayRef<int> Mask, SDValue V1,
9980 SDValue V2, SelectionDAG &DAG) {
9982 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9983 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9984 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9985 int NumElts = VT.getVectorNumElements();
9986 bool ShufpdMask = true;
9987 bool CommutableMask = true;
9988 unsigned Immediate = 0;
9989 for (int i = 0; i < NumElts; ++i) {
9992 int Val = (i & 6) + NumElts * (i & 1);
9993 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9994 if (Mask[i] < Val || Mask[i] > Val + 1)
9996 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9997 CommutableMask = false;
9998 Immediate |= (Mask[i] % 2) << i;
10001 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10002 DAG.getConstant(Immediate, DL, MVT::i8));
10003 if (CommutableMask)
10004 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10005 DAG.getConstant(Immediate, DL, MVT::i8));
10009 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10011 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10012 /// isn't available.
10013 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10014 const X86Subtarget *Subtarget,
10015 SelectionDAG &DAG) {
10017 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10018 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10019 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10020 ArrayRef<int> Mask = SVOp->getMask();
10021 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10023 SmallVector<int, 4> WidenedMask;
10024 if (canWidenShuffleElements(Mask, WidenedMask))
10025 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10028 if (isSingleInputShuffleMask(Mask)) {
10029 // Check for being able to broadcast a single element.
10030 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10031 Mask, Subtarget, DAG))
10034 // Use low duplicate instructions for masks that match their pattern.
10035 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10036 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10038 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10039 // Non-half-crossing single input shuffles can be lowerid with an
10040 // interleaved permutation.
10041 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10042 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10043 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10044 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10047 // With AVX2 we have direct support for this permutation.
10048 if (Subtarget->hasAVX2())
10049 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10050 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10052 // Otherwise, fall back.
10053 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10057 // X86 has dedicated unpack instructions that can handle specific blend
10058 // operations: UNPCKH and UNPCKL.
10059 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10060 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10061 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10062 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10063 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10064 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10065 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10066 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10068 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10072 // Check if the blend happens to exactly fit that of SHUFPD.
10074 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10077 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10078 // shuffle. However, if we have AVX2 and either inputs are already in place,
10079 // we will be able to shuffle even across lanes the other input in a single
10080 // instruction so skip this pattern.
10081 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10082 isShuffleMaskInputInPlace(1, Mask))))
10083 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10084 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10087 // If we have AVX2 then we always want to lower with a blend because an v4 we
10088 // can fully permute the elements.
10089 if (Subtarget->hasAVX2())
10090 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10093 // Otherwise fall back on generic lowering.
10094 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10097 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10099 /// This routine is only called when we have AVX2 and thus a reasonable
10100 /// instruction set for v4i64 shuffling..
10101 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10102 const X86Subtarget *Subtarget,
10103 SelectionDAG &DAG) {
10105 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10106 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10107 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10108 ArrayRef<int> Mask = SVOp->getMask();
10109 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10110 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10112 SmallVector<int, 4> WidenedMask;
10113 if (canWidenShuffleElements(Mask, WidenedMask))
10114 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10117 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10121 // Check for being able to broadcast a single element.
10122 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10123 Mask, Subtarget, DAG))
10126 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10127 // use lower latency instructions that will operate on both 128-bit lanes.
10128 SmallVector<int, 2> RepeatedMask;
10129 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10130 if (isSingleInputShuffleMask(Mask)) {
10131 int PSHUFDMask[] = {-1, -1, -1, -1};
10132 for (int i = 0; i < 2; ++i)
10133 if (RepeatedMask[i] >= 0) {
10134 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10135 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10137 return DAG.getBitcast(
10139 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10140 DAG.getBitcast(MVT::v8i32, V1),
10141 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10145 // AVX2 provides a direct instruction for permuting a single input across
10147 if (isSingleInputShuffleMask(Mask))
10148 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10149 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10151 // Try to use shift instructions.
10152 if (SDValue Shift =
10153 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10156 // Use dedicated unpack instructions for masks that match their pattern.
10157 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10158 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10159 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10160 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10161 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10162 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10163 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10164 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10166 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10167 // shuffle. However, if we have AVX2 and either inputs are already in place,
10168 // we will be able to shuffle even across lanes the other input in a single
10169 // instruction so skip this pattern.
10170 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10171 isShuffleMaskInputInPlace(1, Mask))))
10172 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10173 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10176 // Otherwise fall back on generic blend lowering.
10177 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10181 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10183 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10184 /// isn't available.
10185 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10186 const X86Subtarget *Subtarget,
10187 SelectionDAG &DAG) {
10189 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10190 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10191 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10192 ArrayRef<int> Mask = SVOp->getMask();
10193 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10195 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10199 // Check for being able to broadcast a single element.
10200 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10201 Mask, Subtarget, DAG))
10204 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10205 // options to efficiently lower the shuffle.
10206 SmallVector<int, 4> RepeatedMask;
10207 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10208 assert(RepeatedMask.size() == 4 &&
10209 "Repeated masks must be half the mask width!");
10211 // Use even/odd duplicate instructions for masks that match their pattern.
10212 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10213 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10214 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10215 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10217 if (isSingleInputShuffleMask(Mask))
10218 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10219 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10221 // Use dedicated unpack instructions for masks that match their pattern.
10222 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10223 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10224 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10225 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10226 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10227 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10228 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10229 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10231 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10232 // have already handled any direct blends. We also need to squash the
10233 // repeated mask into a simulated v4f32 mask.
10234 for (int i = 0; i < 4; ++i)
10235 if (RepeatedMask[i] >= 8)
10236 RepeatedMask[i] -= 4;
10237 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10240 // If we have a single input shuffle with different shuffle patterns in the
10241 // two 128-bit lanes use the variable mask to VPERMILPS.
10242 if (isSingleInputShuffleMask(Mask)) {
10243 SDValue VPermMask[8];
10244 for (int i = 0; i < 8; ++i)
10245 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10246 : DAG.getConstant(Mask[i], DL, MVT::i32);
10247 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10248 return DAG.getNode(
10249 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10250 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10252 if (Subtarget->hasAVX2())
10253 return DAG.getNode(
10254 X86ISD::VPERMV, DL, MVT::v8f32,
10255 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10256 MVT::v8i32, VPermMask)),
10259 // Otherwise, fall back.
10260 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10264 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10266 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10267 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10270 // If we have AVX2 then we always want to lower with a blend because at v8 we
10271 // can fully permute the elements.
10272 if (Subtarget->hasAVX2())
10273 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10276 // Otherwise fall back on generic lowering.
10277 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10280 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10282 /// This routine is only called when we have AVX2 and thus a reasonable
10283 /// instruction set for v8i32 shuffling..
10284 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10285 const X86Subtarget *Subtarget,
10286 SelectionDAG &DAG) {
10288 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10289 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10290 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10291 ArrayRef<int> Mask = SVOp->getMask();
10292 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10293 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10295 // Whenever we can lower this as a zext, that instruction is strictly faster
10296 // than any alternative. It also allows us to fold memory operands into the
10297 // shuffle in many cases.
10298 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10299 Mask, Subtarget, DAG))
10302 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10306 // Check for being able to broadcast a single element.
10307 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10308 Mask, Subtarget, DAG))
10311 // If the shuffle mask is repeated in each 128-bit lane we can use more
10312 // efficient instructions that mirror the shuffles across the two 128-bit
10314 SmallVector<int, 4> RepeatedMask;
10315 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10316 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10317 if (isSingleInputShuffleMask(Mask))
10318 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10319 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10321 // Use dedicated unpack instructions for masks that match their pattern.
10322 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10323 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10324 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10325 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10326 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10327 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10328 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10329 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10332 // Try to use shift instructions.
10333 if (SDValue Shift =
10334 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10337 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10338 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10341 // If the shuffle patterns aren't repeated but it is a single input, directly
10342 // generate a cross-lane VPERMD instruction.
10343 if (isSingleInputShuffleMask(Mask)) {
10344 SDValue VPermMask[8];
10345 for (int i = 0; i < 8; ++i)
10346 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10347 : DAG.getConstant(Mask[i], DL, MVT::i32);
10348 return DAG.getNode(
10349 X86ISD::VPERMV, DL, MVT::v8i32,
10350 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10353 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10355 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10356 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10359 // Otherwise fall back on generic blend lowering.
10360 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10364 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10366 /// This routine is only called when we have AVX2 and thus a reasonable
10367 /// instruction set for v16i16 shuffling..
10368 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10369 const X86Subtarget *Subtarget,
10370 SelectionDAG &DAG) {
10372 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10373 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10375 ArrayRef<int> Mask = SVOp->getMask();
10376 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10377 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10379 // Whenever we can lower this as a zext, that instruction is strictly faster
10380 // than any alternative. It also allows us to fold memory operands into the
10381 // shuffle in many cases.
10382 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10383 Mask, Subtarget, DAG))
10386 // Check for being able to broadcast a single element.
10387 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10388 Mask, Subtarget, DAG))
10391 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10395 // Use dedicated unpack instructions for masks that match their pattern.
10396 if (isShuffleEquivalent(V1, V2, Mask,
10397 {// First 128-bit lane:
10398 0, 16, 1, 17, 2, 18, 3, 19,
10399 // Second 128-bit lane:
10400 8, 24, 9, 25, 10, 26, 11, 27}))
10401 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10402 if (isShuffleEquivalent(V1, V2, Mask,
10403 {// First 128-bit lane:
10404 4, 20, 5, 21, 6, 22, 7, 23,
10405 // Second 128-bit lane:
10406 12, 28, 13, 29, 14, 30, 15, 31}))
10407 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10409 // Try to use shift instructions.
10410 if (SDValue Shift =
10411 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10414 // Try to use byte rotation instructions.
10415 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10416 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10419 if (isSingleInputShuffleMask(Mask)) {
10420 // There are no generalized cross-lane shuffle operations available on i16
10422 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10423 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10426 SmallVector<int, 8> RepeatedMask;
10427 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10428 // As this is a single-input shuffle, the repeated mask should be
10429 // a strictly valid v8i16 mask that we can pass through to the v8i16
10430 // lowering to handle even the v16 case.
10431 return lowerV8I16GeneralSingleInputVectorShuffle(
10432 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10435 SDValue PSHUFBMask[32];
10436 for (int i = 0; i < 16; ++i) {
10437 if (Mask[i] == -1) {
10438 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10442 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10443 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10444 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10445 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10447 return DAG.getBitcast(MVT::v16i16,
10448 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10449 DAG.getBitcast(MVT::v32i8, V1),
10450 DAG.getNode(ISD::BUILD_VECTOR, DL,
10451 MVT::v32i8, PSHUFBMask)));
10454 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10456 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10457 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10460 // Otherwise fall back on generic lowering.
10461 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10464 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10466 /// This routine is only called when we have AVX2 and thus a reasonable
10467 /// instruction set for v32i8 shuffling..
10468 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10469 const X86Subtarget *Subtarget,
10470 SelectionDAG &DAG) {
10472 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10473 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10474 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10475 ArrayRef<int> Mask = SVOp->getMask();
10476 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10477 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10479 // Whenever we can lower this as a zext, that instruction is strictly faster
10480 // than any alternative. It also allows us to fold memory operands into the
10481 // shuffle in many cases.
10482 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10483 Mask, Subtarget, DAG))
10486 // Check for being able to broadcast a single element.
10487 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10488 Mask, Subtarget, DAG))
10491 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10495 // Use dedicated unpack instructions for masks that match their pattern.
10496 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10498 if (isShuffleEquivalent(
10500 {// First 128-bit lane:
10501 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10502 // Second 128-bit lane:
10503 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10504 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10505 if (isShuffleEquivalent(
10507 {// First 128-bit lane:
10508 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10509 // Second 128-bit lane:
10510 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10511 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10513 // Try to use shift instructions.
10514 if (SDValue Shift =
10515 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10518 // Try to use byte rotation instructions.
10519 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10520 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10523 if (isSingleInputShuffleMask(Mask)) {
10524 // There are no generalized cross-lane shuffle operations available on i8
10526 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10527 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10530 SDValue PSHUFBMask[32];
10531 for (int i = 0; i < 32; ++i)
10534 ? DAG.getUNDEF(MVT::i8)
10535 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10538 return DAG.getNode(
10539 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10540 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10543 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10545 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10546 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10549 // Otherwise fall back on generic lowering.
10550 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10553 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10555 /// This routine either breaks down the specific type of a 256-bit x86 vector
10556 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10557 /// together based on the available instructions.
10558 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10559 MVT VT, const X86Subtarget *Subtarget,
10560 SelectionDAG &DAG) {
10562 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10563 ArrayRef<int> Mask = SVOp->getMask();
10565 // If we have a single input to the zero element, insert that into V1 if we
10566 // can do so cheaply.
10567 int NumElts = VT.getVectorNumElements();
10568 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10569 return M >= NumElts;
10572 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10573 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10574 DL, VT, V1, V2, Mask, Subtarget, DAG))
10577 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10578 // check for those subtargets here and avoid much of the subtarget querying in
10579 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10580 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10581 // floating point types there eventually, just immediately cast everything to
10582 // a float and operate entirely in that domain.
10583 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10584 int ElementBits = VT.getScalarSizeInBits();
10585 if (ElementBits < 32)
10586 // No floating point type available, decompose into 128-bit vectors.
10587 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10589 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10590 VT.getVectorNumElements());
10591 V1 = DAG.getBitcast(FpVT, V1);
10592 V2 = DAG.getBitcast(FpVT, V2);
10593 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10596 switch (VT.SimpleTy) {
10598 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10600 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10602 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10604 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10606 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10608 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10611 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10615 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10616 ArrayRef<int> Mask, SDValue V1,
10617 SDValue V2, SelectionDAG &DAG) {
10619 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10621 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10622 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10624 SmallVector<SDValue, 32> VPermMask;
10625 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10626 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10627 DAG.getConstant(Mask[i], DL, MaskEltVT));
10628 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10630 if (isSingleInputShuffleMask(Mask))
10631 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10633 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10636 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10637 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10638 const X86Subtarget *Subtarget,
10639 SelectionDAG &DAG) {
10641 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10642 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10643 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10644 ArrayRef<int> Mask = SVOp->getMask();
10645 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10647 if (SDValue Unpck =
10648 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10651 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10654 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10655 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10656 const X86Subtarget *Subtarget,
10657 SelectionDAG &DAG) {
10659 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10660 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10661 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10662 ArrayRef<int> Mask = SVOp->getMask();
10663 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10665 if (SDValue Unpck =
10666 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10669 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10672 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10673 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10674 const X86Subtarget *Subtarget,
10675 SelectionDAG &DAG) {
10677 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10678 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10679 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10680 ArrayRef<int> Mask = SVOp->getMask();
10681 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10683 if (SDValue Unpck =
10684 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10687 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10690 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10691 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10692 const X86Subtarget *Subtarget,
10693 SelectionDAG &DAG) {
10695 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10696 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10697 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10698 ArrayRef<int> Mask = SVOp->getMask();
10699 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10701 if (SDValue Unpck =
10702 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10705 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10708 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10709 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10710 const X86Subtarget *Subtarget,
10711 SelectionDAG &DAG) {
10713 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10714 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10715 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10716 ArrayRef<int> Mask = SVOp->getMask();
10717 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10718 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10720 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10723 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10724 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10725 const X86Subtarget *Subtarget,
10726 SelectionDAG &DAG) {
10728 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10729 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10730 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10731 ArrayRef<int> Mask = SVOp->getMask();
10732 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10733 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10735 // FIXME: Implement direct support for this type!
10736 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10739 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10741 /// This routine either breaks down the specific type of a 512-bit x86 vector
10742 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10743 /// together based on the available instructions.
10744 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10745 MVT VT, const X86Subtarget *Subtarget,
10746 SelectionDAG &DAG) {
10748 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10749 ArrayRef<int> Mask = SVOp->getMask();
10750 assert(Subtarget->hasAVX512() &&
10751 "Cannot lower 512-bit vectors w/ basic ISA!");
10753 // Check for being able to broadcast a single element.
10754 if (SDValue Broadcast =
10755 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10758 // Dispatch to each element type for lowering. If we don't have supprot for
10759 // specific element type shuffles at 512 bits, immediately split them and
10760 // lower them. Each lowering routine of a given type is allowed to assume that
10761 // the requisite ISA extensions for that element type are available.
10762 switch (VT.SimpleTy) {
10764 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10766 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10768 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10770 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10772 if (Subtarget->hasBWI())
10773 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10776 if (Subtarget->hasBWI())
10777 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10781 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10784 // Otherwise fall back on splitting.
10785 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10788 /// \brief Top-level lowering for x86 vector shuffles.
10790 /// This handles decomposition, canonicalization, and lowering of all x86
10791 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10792 /// above in helper routines. The canonicalization attempts to widen shuffles
10793 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10794 /// s.t. only one of the two inputs needs to be tested, etc.
10795 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10796 SelectionDAG &DAG) {
10797 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10798 ArrayRef<int> Mask = SVOp->getMask();
10799 SDValue V1 = Op.getOperand(0);
10800 SDValue V2 = Op.getOperand(1);
10801 MVT VT = Op.getSimpleValueType();
10802 int NumElements = VT.getVectorNumElements();
10805 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10807 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10808 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10809 if (V1IsUndef && V2IsUndef)
10810 return DAG.getUNDEF(VT);
10812 // When we create a shuffle node we put the UNDEF node to second operand,
10813 // but in some cases the first operand may be transformed to UNDEF.
10814 // In this case we should just commute the node.
10816 return DAG.getCommutedVectorShuffle(*SVOp);
10818 // Check for non-undef masks pointing at an undef vector and make the masks
10819 // undef as well. This makes it easier to match the shuffle based solely on
10823 if (M >= NumElements) {
10824 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10825 for (int &M : NewMask)
10826 if (M >= NumElements)
10828 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10831 // We actually see shuffles that are entirely re-arrangements of a set of
10832 // zero inputs. This mostly happens while decomposing complex shuffles into
10833 // simple ones. Directly lower these as a buildvector of zeros.
10834 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10835 if (Zeroable.all())
10836 return getZeroVector(VT, Subtarget, DAG, dl);
10838 // Try to collapse shuffles into using a vector type with fewer elements but
10839 // wider element types. We cap this to not form integers or floating point
10840 // elements wider than 64 bits, but it might be interesting to form i128
10841 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10842 SmallVector<int, 16> WidenedMask;
10843 if (VT.getScalarSizeInBits() < 64 &&
10844 canWidenShuffleElements(Mask, WidenedMask)) {
10845 MVT NewEltVT = VT.isFloatingPoint()
10846 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10847 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10848 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10849 // Make sure that the new vector type is legal. For example, v2f64 isn't
10851 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10852 V1 = DAG.getBitcast(NewVT, V1);
10853 V2 = DAG.getBitcast(NewVT, V2);
10854 return DAG.getBitcast(
10855 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10859 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10860 for (int M : SVOp->getMask())
10862 ++NumUndefElements;
10863 else if (M < NumElements)
10868 // Commute the shuffle as needed such that more elements come from V1 than
10869 // V2. This allows us to match the shuffle pattern strictly on how many
10870 // elements come from V1 without handling the symmetric cases.
10871 if (NumV2Elements > NumV1Elements)
10872 return DAG.getCommutedVectorShuffle(*SVOp);
10874 // When the number of V1 and V2 elements are the same, try to minimize the
10875 // number of uses of V2 in the low half of the vector. When that is tied,
10876 // ensure that the sum of indices for V1 is equal to or lower than the sum
10877 // indices for V2. When those are equal, try to ensure that the number of odd
10878 // indices for V1 is lower than the number of odd indices for V2.
10879 if (NumV1Elements == NumV2Elements) {
10880 int LowV1Elements = 0, LowV2Elements = 0;
10881 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10882 if (M >= NumElements)
10886 if (LowV2Elements > LowV1Elements) {
10887 return DAG.getCommutedVectorShuffle(*SVOp);
10888 } else if (LowV2Elements == LowV1Elements) {
10889 int SumV1Indices = 0, SumV2Indices = 0;
10890 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10891 if (SVOp->getMask()[i] >= NumElements)
10893 else if (SVOp->getMask()[i] >= 0)
10895 if (SumV2Indices < SumV1Indices) {
10896 return DAG.getCommutedVectorShuffle(*SVOp);
10897 } else if (SumV2Indices == SumV1Indices) {
10898 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10899 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10900 if (SVOp->getMask()[i] >= NumElements)
10901 NumV2OddIndices += i % 2;
10902 else if (SVOp->getMask()[i] >= 0)
10903 NumV1OddIndices += i % 2;
10904 if (NumV2OddIndices < NumV1OddIndices)
10905 return DAG.getCommutedVectorShuffle(*SVOp);
10910 // For each vector width, delegate to a specialized lowering routine.
10911 if (VT.getSizeInBits() == 128)
10912 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10914 if (VT.getSizeInBits() == 256)
10915 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10917 if (VT.getSizeInBits() == 512)
10918 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10920 llvm_unreachable("Unimplemented!");
10923 // This function assumes its argument is a BUILD_VECTOR of constants or
10924 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10926 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10927 unsigned &MaskValue) {
10929 unsigned NumElems = BuildVector->getNumOperands();
10930 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10931 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10932 unsigned NumElemsInLane = NumElems / NumLanes;
10934 // Blend for v16i16 should be symmetric for the both lanes.
10935 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10936 SDValue EltCond = BuildVector->getOperand(i);
10937 SDValue SndLaneEltCond =
10938 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10940 int Lane1Cond = -1, Lane2Cond = -1;
10941 if (isa<ConstantSDNode>(EltCond))
10942 Lane1Cond = !isZero(EltCond);
10943 if (isa<ConstantSDNode>(SndLaneEltCond))
10944 Lane2Cond = !isZero(SndLaneEltCond);
10946 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10947 // Lane1Cond != 0, means we want the first argument.
10948 // Lane1Cond == 0, means we want the second argument.
10949 // The encoding of this argument is 0 for the first argument, 1
10950 // for the second. Therefore, invert the condition.
10951 MaskValue |= !Lane1Cond << i;
10952 else if (Lane1Cond < 0)
10953 MaskValue |= !Lane2Cond << i;
10960 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10961 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10962 const X86Subtarget *Subtarget,
10963 SelectionDAG &DAG) {
10964 SDValue Cond = Op.getOperand(0);
10965 SDValue LHS = Op.getOperand(1);
10966 SDValue RHS = Op.getOperand(2);
10968 MVT VT = Op.getSimpleValueType();
10970 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10972 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10974 // Only non-legal VSELECTs reach this lowering, convert those into generic
10975 // shuffles and re-use the shuffle lowering path for blends.
10976 SmallVector<int, 32> Mask;
10977 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10978 SDValue CondElt = CondBV->getOperand(i);
10980 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10982 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10985 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10986 // A vselect where all conditions and data are constants can be optimized into
10987 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10988 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10989 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10990 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10993 // Try to lower this to a blend-style vector shuffle. This can handle all
10994 // constant condition cases.
10995 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10998 // Variable blends are only legal from SSE4.1 onward.
10999 if (!Subtarget->hasSSE41())
11002 // Only some types will be legal on some subtargets. If we can emit a legal
11003 // VSELECT-matching blend, return Op, and but if we need to expand, return
11005 switch (Op.getSimpleValueType().SimpleTy) {
11007 // Most of the vector types have blends past SSE4.1.
11011 // The byte blends for AVX vectors were introduced only in AVX2.
11012 if (Subtarget->hasAVX2())
11019 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11020 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11023 // FIXME: We should custom lower this by fixing the condition and using i8
11029 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11030 MVT VT = Op.getSimpleValueType();
11033 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11036 if (VT.getSizeInBits() == 8) {
11037 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11038 Op.getOperand(0), Op.getOperand(1));
11039 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11040 DAG.getValueType(VT));
11041 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11044 if (VT.getSizeInBits() == 16) {
11045 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11046 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11048 return DAG.getNode(
11049 ISD::TRUNCATE, dl, MVT::i16,
11050 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11051 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11052 Op.getOperand(1)));
11053 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11054 Op.getOperand(0), Op.getOperand(1));
11055 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11056 DAG.getValueType(VT));
11057 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11060 if (VT == MVT::f32) {
11061 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11062 // the result back to FR32 register. It's only worth matching if the
11063 // result has a single use which is a store or a bitcast to i32. And in
11064 // the case of a store, it's not worth it if the index is a constant 0,
11065 // because a MOVSSmr can be used instead, which is smaller and faster.
11066 if (!Op.hasOneUse())
11068 SDNode *User = *Op.getNode()->use_begin();
11069 if ((User->getOpcode() != ISD::STORE ||
11070 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11071 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11072 (User->getOpcode() != ISD::BITCAST ||
11073 User->getValueType(0) != MVT::i32))
11075 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11076 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11078 return DAG.getBitcast(MVT::f32, Extract);
11081 if (VT == MVT::i32 || VT == MVT::i64) {
11082 // ExtractPS/pextrq works with constant index.
11083 if (isa<ConstantSDNode>(Op.getOperand(1)))
11089 /// Extract one bit from mask vector, like v16i1 or v8i1.
11090 /// AVX-512 feature.
11092 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11093 SDValue Vec = Op.getOperand(0);
11095 MVT VecVT = Vec.getSimpleValueType();
11096 SDValue Idx = Op.getOperand(1);
11097 MVT EltVT = Op.getSimpleValueType();
11099 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11100 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11101 "Unexpected vector type in ExtractBitFromMaskVector");
11103 // variable index can't be handled in mask registers,
11104 // extend vector to VR512
11105 if (!isa<ConstantSDNode>(Idx)) {
11106 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11107 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11108 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11109 ExtVT.getVectorElementType(), Ext, Idx);
11110 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11113 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11114 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11115 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11116 rc = getRegClassFor(MVT::v16i1);
11117 unsigned MaxSift = rc->getSize()*8 - 1;
11118 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11119 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11120 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11121 DAG.getConstant(MaxSift, dl, MVT::i8));
11122 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11123 DAG.getIntPtrConstant(0, dl));
11127 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11128 SelectionDAG &DAG) const {
11130 SDValue Vec = Op.getOperand(0);
11131 MVT VecVT = Vec.getSimpleValueType();
11132 SDValue Idx = Op.getOperand(1);
11134 if (Op.getSimpleValueType() == MVT::i1)
11135 return ExtractBitFromMaskVector(Op, DAG);
11137 if (!isa<ConstantSDNode>(Idx)) {
11138 if (VecVT.is512BitVector() ||
11139 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11140 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11143 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11144 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11145 MaskEltVT.getSizeInBits());
11147 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11148 auto PtrVT = getPointerTy(DAG.getDataLayout());
11149 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11150 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11151 DAG.getConstant(0, dl, PtrVT));
11152 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11153 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11154 DAG.getConstant(0, dl, PtrVT));
11159 // If this is a 256-bit vector result, first extract the 128-bit vector and
11160 // then extract the element from the 128-bit vector.
11161 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11163 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11164 // Get the 128-bit vector.
11165 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11166 MVT EltVT = VecVT.getVectorElementType();
11168 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11170 //if (IdxVal >= NumElems/2)
11171 // IdxVal -= NumElems/2;
11172 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11173 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11174 DAG.getConstant(IdxVal, dl, MVT::i32));
11177 assert(VecVT.is128BitVector() && "Unexpected vector length");
11179 if (Subtarget->hasSSE41())
11180 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11183 MVT VT = Op.getSimpleValueType();
11184 // TODO: handle v16i8.
11185 if (VT.getSizeInBits() == 16) {
11186 SDValue Vec = Op.getOperand(0);
11187 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11189 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11190 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11191 DAG.getBitcast(MVT::v4i32, Vec),
11192 Op.getOperand(1)));
11193 // Transform it so it match pextrw which produces a 32-bit result.
11194 MVT EltVT = MVT::i32;
11195 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11196 Op.getOperand(0), Op.getOperand(1));
11197 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11198 DAG.getValueType(VT));
11199 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11202 if (VT.getSizeInBits() == 32) {
11203 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11207 // SHUFPS the element to the lowest double word, then movss.
11208 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11209 MVT VVT = Op.getOperand(0).getSimpleValueType();
11210 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11211 DAG.getUNDEF(VVT), Mask);
11212 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11213 DAG.getIntPtrConstant(0, dl));
11216 if (VT.getSizeInBits() == 64) {
11217 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11218 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11219 // to match extract_elt for f64.
11220 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11224 // UNPCKHPD the element to the lowest double word, then movsd.
11225 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11226 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11227 int Mask[2] = { 1, -1 };
11228 MVT VVT = Op.getOperand(0).getSimpleValueType();
11229 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11230 DAG.getUNDEF(VVT), Mask);
11231 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11232 DAG.getIntPtrConstant(0, dl));
11238 /// Insert one bit to mask vector, like v16i1 or v8i1.
11239 /// AVX-512 feature.
11241 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11243 SDValue Vec = Op.getOperand(0);
11244 SDValue Elt = Op.getOperand(1);
11245 SDValue Idx = Op.getOperand(2);
11246 MVT VecVT = Vec.getSimpleValueType();
11248 if (!isa<ConstantSDNode>(Idx)) {
11249 // Non constant index. Extend source and destination,
11250 // insert element and then truncate the result.
11251 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11252 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11253 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11254 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11255 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11256 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11259 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11260 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11262 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11263 DAG.getConstant(IdxVal, dl, MVT::i8));
11264 if (Vec.getOpcode() == ISD::UNDEF)
11266 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11269 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11270 SelectionDAG &DAG) const {
11271 MVT VT = Op.getSimpleValueType();
11272 MVT EltVT = VT.getVectorElementType();
11274 if (EltVT == MVT::i1)
11275 return InsertBitToMaskVector(Op, DAG);
11278 SDValue N0 = Op.getOperand(0);
11279 SDValue N1 = Op.getOperand(1);
11280 SDValue N2 = Op.getOperand(2);
11281 if (!isa<ConstantSDNode>(N2))
11283 auto *N2C = cast<ConstantSDNode>(N2);
11284 unsigned IdxVal = N2C->getZExtValue();
11286 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11287 // into that, and then insert the subvector back into the result.
11288 if (VT.is256BitVector() || VT.is512BitVector()) {
11289 // With a 256-bit vector, we can insert into the zero element efficiently
11290 // using a blend if we have AVX or AVX2 and the right data type.
11291 if (VT.is256BitVector() && IdxVal == 0) {
11292 // TODO: It is worthwhile to cast integer to floating point and back
11293 // and incur a domain crossing penalty if that's what we'll end up
11294 // doing anyway after extracting to a 128-bit vector.
11295 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11296 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11297 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11298 N2 = DAG.getIntPtrConstant(1, dl);
11299 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11303 // Get the desired 128-bit vector chunk.
11304 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11306 // Insert the element into the desired chunk.
11307 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11308 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11310 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11311 DAG.getConstant(IdxIn128, dl, MVT::i32));
11313 // Insert the changed part back into the bigger vector
11314 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11316 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11318 if (Subtarget->hasSSE41()) {
11319 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11321 if (VT == MVT::v8i16) {
11322 Opc = X86ISD::PINSRW;
11324 assert(VT == MVT::v16i8);
11325 Opc = X86ISD::PINSRB;
11328 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11330 if (N1.getValueType() != MVT::i32)
11331 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11332 if (N2.getValueType() != MVT::i32)
11333 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11334 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11337 if (EltVT == MVT::f32) {
11338 // Bits [7:6] of the constant are the source select. This will always be
11339 // zero here. The DAG Combiner may combine an extract_elt index into
11340 // these bits. For example (insert (extract, 3), 2) could be matched by
11341 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11342 // Bits [5:4] of the constant are the destination select. This is the
11343 // value of the incoming immediate.
11344 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11345 // combine either bitwise AND or insert of float 0.0 to set these bits.
11347 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11348 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11349 // If this is an insertion of 32-bits into the low 32-bits of
11350 // a vector, we prefer to generate a blend with immediate rather
11351 // than an insertps. Blends are simpler operations in hardware and so
11352 // will always have equal or better performance than insertps.
11353 // But if optimizing for size and there's a load folding opportunity,
11354 // generate insertps because blendps does not have a 32-bit memory
11356 N2 = DAG.getIntPtrConstant(1, dl);
11357 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11358 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11360 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11361 // Create this as a scalar to vector..
11362 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11363 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11366 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11367 // PINSR* works with constant index.
11372 if (EltVT == MVT::i8)
11375 if (EltVT.getSizeInBits() == 16) {
11376 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11377 // as its second argument.
11378 if (N1.getValueType() != MVT::i32)
11379 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11380 if (N2.getValueType() != MVT::i32)
11381 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11382 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11387 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11389 MVT OpVT = Op.getSimpleValueType();
11391 // If this is a 256-bit vector result, first insert into a 128-bit
11392 // vector and then insert into the 256-bit vector.
11393 if (!OpVT.is128BitVector()) {
11394 // Insert into a 128-bit vector.
11395 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11396 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11397 OpVT.getVectorNumElements() / SizeFactor);
11399 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11401 // Insert the 128-bit vector.
11402 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11405 if (OpVT == MVT::v1i64 &&
11406 Op.getOperand(0).getValueType() == MVT::i64)
11407 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11409 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11410 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11411 return DAG.getBitcast(
11412 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11415 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11416 // a simple subregister reference or explicit instructions to grab
11417 // upper bits of a vector.
11418 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11419 SelectionDAG &DAG) {
11421 SDValue In = Op.getOperand(0);
11422 SDValue Idx = Op.getOperand(1);
11423 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11424 MVT ResVT = Op.getSimpleValueType();
11425 MVT InVT = In.getSimpleValueType();
11427 if (Subtarget->hasFp256()) {
11428 if (ResVT.is128BitVector() &&
11429 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11430 isa<ConstantSDNode>(Idx)) {
11431 return Extract128BitVector(In, IdxVal, DAG, dl);
11433 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11434 isa<ConstantSDNode>(Idx)) {
11435 return Extract256BitVector(In, IdxVal, DAG, dl);
11441 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11442 // simple superregister reference or explicit instructions to insert
11443 // the upper bits of a vector.
11444 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11445 SelectionDAG &DAG) {
11446 if (!Subtarget->hasAVX())
11450 SDValue Vec = Op.getOperand(0);
11451 SDValue SubVec = Op.getOperand(1);
11452 SDValue Idx = Op.getOperand(2);
11454 if (!isa<ConstantSDNode>(Idx))
11457 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11458 MVT OpVT = Op.getSimpleValueType();
11459 MVT SubVecVT = SubVec.getSimpleValueType();
11461 // Fold two 16-byte subvector loads into one 32-byte load:
11462 // (insert_subvector (insert_subvector undef, (load addr), 0),
11463 // (load addr + 16), Elts/2)
11465 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11466 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11467 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11468 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11469 if (Idx2 && Idx2->getZExtValue() == 0) {
11470 SDValue SubVec2 = Vec.getOperand(1);
11471 // If needed, look through a bitcast to get to the load.
11472 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11473 SubVec2 = SubVec2.getOperand(0);
11475 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11477 unsigned Alignment = FirstLd->getAlignment();
11478 unsigned AS = FirstLd->getAddressSpace();
11479 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11480 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11481 OpVT, AS, Alignment, &Fast) && Fast) {
11482 SDValue Ops[] = { SubVec2, SubVec };
11483 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11490 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11491 SubVecVT.is128BitVector())
11492 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11494 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11495 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11497 if (OpVT.getVectorElementType() == MVT::i1) {
11498 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11500 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11501 SDValue Undef = DAG.getUNDEF(OpVT);
11502 unsigned NumElems = OpVT.getVectorNumElements();
11503 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11505 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11506 // Zero upper bits of the Vec
11507 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11508 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11510 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11512 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11513 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11516 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11518 // Zero upper bits of the Vec2
11519 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11520 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11521 // Zero lower bits of the Vec
11522 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11523 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11524 // Merge them together
11525 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11531 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11532 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11533 // one of the above mentioned nodes. It has to be wrapped because otherwise
11534 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11535 // be used to form addressing mode. These wrapped nodes will be selected
11538 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11539 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11541 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11542 // global base reg.
11543 unsigned char OpFlag = 0;
11544 unsigned WrapperKind = X86ISD::Wrapper;
11545 CodeModel::Model M = DAG.getTarget().getCodeModel();
11547 if (Subtarget->isPICStyleRIPRel() &&
11548 (M == CodeModel::Small || M == CodeModel::Kernel))
11549 WrapperKind = X86ISD::WrapperRIP;
11550 else if (Subtarget->isPICStyleGOT())
11551 OpFlag = X86II::MO_GOTOFF;
11552 else if (Subtarget->isPICStyleStubPIC())
11553 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11555 auto PtrVT = getPointerTy(DAG.getDataLayout());
11556 SDValue Result = DAG.getTargetConstantPool(
11557 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11559 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11560 // With PIC, the address is actually $g + Offset.
11563 DAG.getNode(ISD::ADD, DL, PtrVT,
11564 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11570 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11571 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11573 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11574 // global base reg.
11575 unsigned char OpFlag = 0;
11576 unsigned WrapperKind = X86ISD::Wrapper;
11577 CodeModel::Model M = DAG.getTarget().getCodeModel();
11579 if (Subtarget->isPICStyleRIPRel() &&
11580 (M == CodeModel::Small || M == CodeModel::Kernel))
11581 WrapperKind = X86ISD::WrapperRIP;
11582 else if (Subtarget->isPICStyleGOT())
11583 OpFlag = X86II::MO_GOTOFF;
11584 else if (Subtarget->isPICStyleStubPIC())
11585 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11587 auto PtrVT = getPointerTy(DAG.getDataLayout());
11588 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11590 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11592 // With PIC, the address is actually $g + Offset.
11595 DAG.getNode(ISD::ADD, DL, PtrVT,
11596 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11602 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11603 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11605 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11606 // global base reg.
11607 unsigned char OpFlag = 0;
11608 unsigned WrapperKind = X86ISD::Wrapper;
11609 CodeModel::Model M = DAG.getTarget().getCodeModel();
11611 if (Subtarget->isPICStyleRIPRel() &&
11612 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11613 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11614 OpFlag = X86II::MO_GOTPCREL;
11615 WrapperKind = X86ISD::WrapperRIP;
11616 } else if (Subtarget->isPICStyleGOT()) {
11617 OpFlag = X86II::MO_GOT;
11618 } else if (Subtarget->isPICStyleStubPIC()) {
11619 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11620 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11621 OpFlag = X86II::MO_DARWIN_NONLAZY;
11624 auto PtrVT = getPointerTy(DAG.getDataLayout());
11625 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11628 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11630 // With PIC, the address is actually $g + Offset.
11631 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11632 !Subtarget->is64Bit()) {
11634 DAG.getNode(ISD::ADD, DL, PtrVT,
11635 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11638 // For symbols that require a load from a stub to get the address, emit the
11640 if (isGlobalStubReference(OpFlag))
11641 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11642 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11643 false, false, false, 0);
11649 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11650 // Create the TargetBlockAddressAddress node.
11651 unsigned char OpFlags =
11652 Subtarget->ClassifyBlockAddressReference();
11653 CodeModel::Model M = DAG.getTarget().getCodeModel();
11654 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11655 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11657 auto PtrVT = getPointerTy(DAG.getDataLayout());
11658 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11660 if (Subtarget->isPICStyleRIPRel() &&
11661 (M == CodeModel::Small || M == CodeModel::Kernel))
11662 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11664 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11666 // With PIC, the address is actually $g + Offset.
11667 if (isGlobalRelativeToPICBase(OpFlags)) {
11668 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11669 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11676 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11677 int64_t Offset, SelectionDAG &DAG) const {
11678 // Create the TargetGlobalAddress node, folding in the constant
11679 // offset if it is legal.
11680 unsigned char OpFlags =
11681 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11682 CodeModel::Model M = DAG.getTarget().getCodeModel();
11683 auto PtrVT = getPointerTy(DAG.getDataLayout());
11685 if (OpFlags == X86II::MO_NO_FLAG &&
11686 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11687 // A direct static reference to a global.
11688 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11691 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11694 if (Subtarget->isPICStyleRIPRel() &&
11695 (M == CodeModel::Small || M == CodeModel::Kernel))
11696 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11698 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11700 // With PIC, the address is actually $g + Offset.
11701 if (isGlobalRelativeToPICBase(OpFlags)) {
11702 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11703 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11706 // For globals that require a load from a stub to get the address, emit the
11708 if (isGlobalStubReference(OpFlags))
11709 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11710 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11711 false, false, false, 0);
11713 // If there was a non-zero offset that we didn't fold, create an explicit
11714 // addition for it.
11716 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11717 DAG.getConstant(Offset, dl, PtrVT));
11723 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11724 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11725 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11726 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11730 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11731 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11732 unsigned char OperandFlags, bool LocalDynamic = false) {
11733 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11734 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11736 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11737 GA->getValueType(0),
11741 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11745 SDValue Ops[] = { Chain, TGA, *InFlag };
11746 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11748 SDValue Ops[] = { Chain, TGA };
11749 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11752 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11753 MFI->setAdjustsStack(true);
11754 MFI->setHasCalls(true);
11756 SDValue Flag = Chain.getValue(1);
11757 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11760 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11762 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11765 SDLoc dl(GA); // ? function entry point might be better
11766 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11767 DAG.getNode(X86ISD::GlobalBaseReg,
11768 SDLoc(), PtrVT), InFlag);
11769 InFlag = Chain.getValue(1);
11771 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11774 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11776 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11778 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11779 X86::RAX, X86II::MO_TLSGD);
11782 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11788 // Get the start address of the TLS block for this module.
11789 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11790 .getInfo<X86MachineFunctionInfo>();
11791 MFI->incNumLocalDynamicTLSAccesses();
11795 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11796 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11799 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11800 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11801 InFlag = Chain.getValue(1);
11802 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11803 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11806 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11810 unsigned char OperandFlags = X86II::MO_DTPOFF;
11811 unsigned WrapperKind = X86ISD::Wrapper;
11812 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11813 GA->getValueType(0),
11814 GA->getOffset(), OperandFlags);
11815 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11817 // Add x@dtpoff with the base.
11818 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11821 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11822 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11823 const EVT PtrVT, TLSModel::Model model,
11824 bool is64Bit, bool isPIC) {
11827 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11828 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11829 is64Bit ? 257 : 256));
11831 SDValue ThreadPointer =
11832 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11833 MachinePointerInfo(Ptr), false, false, false, 0);
11835 unsigned char OperandFlags = 0;
11836 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11838 unsigned WrapperKind = X86ISD::Wrapper;
11839 if (model == TLSModel::LocalExec) {
11840 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11841 } else if (model == TLSModel::InitialExec) {
11843 OperandFlags = X86II::MO_GOTTPOFF;
11844 WrapperKind = X86ISD::WrapperRIP;
11846 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11849 llvm_unreachable("Unexpected model");
11852 // emit "addl x@ntpoff,%eax" (local exec)
11853 // or "addl x@indntpoff,%eax" (initial exec)
11854 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11856 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11857 GA->getOffset(), OperandFlags);
11858 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11860 if (model == TLSModel::InitialExec) {
11861 if (isPIC && !is64Bit) {
11862 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11863 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11867 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11868 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11869 false, false, false, 0);
11872 // The address of the thread local variable is the add of the thread
11873 // pointer with the offset of the variable.
11874 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11878 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11880 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11881 const GlobalValue *GV = GA->getGlobal();
11882 auto PtrVT = getPointerTy(DAG.getDataLayout());
11884 if (Subtarget->isTargetELF()) {
11885 if (DAG.getTarget().Options.EmulatedTLS)
11886 return LowerToTLSEmulatedModel(GA, DAG);
11887 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11889 case TLSModel::GeneralDynamic:
11890 if (Subtarget->is64Bit())
11891 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
11892 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
11893 case TLSModel::LocalDynamic:
11894 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
11895 Subtarget->is64Bit());
11896 case TLSModel::InitialExec:
11897 case TLSModel::LocalExec:
11898 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
11899 DAG.getTarget().getRelocationModel() ==
11902 llvm_unreachable("Unknown TLS model.");
11905 if (Subtarget->isTargetDarwin()) {
11906 // Darwin only has one model of TLS. Lower to that.
11907 unsigned char OpFlag = 0;
11908 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11909 X86ISD::WrapperRIP : X86ISD::Wrapper;
11911 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11912 // global base reg.
11913 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11914 !Subtarget->is64Bit();
11916 OpFlag = X86II::MO_TLVP_PIC_BASE;
11918 OpFlag = X86II::MO_TLVP;
11920 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11921 GA->getValueType(0),
11922 GA->getOffset(), OpFlag);
11923 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11925 // With PIC32, the address is actually $g + Offset.
11927 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
11928 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11931 // Lowering the machine isd will make sure everything is in the right
11933 SDValue Chain = DAG.getEntryNode();
11934 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11935 SDValue Args[] = { Chain, Offset };
11936 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11938 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11939 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11940 MFI->setAdjustsStack(true);
11942 // And our return value (tls address) is in the standard call return value
11944 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11945 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
11948 if (Subtarget->isTargetKnownWindowsMSVC() ||
11949 Subtarget->isTargetWindowsGNU()) {
11950 // Just use the implicit TLS architecture
11951 // Need to generate someting similar to:
11952 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11954 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11955 // mov rcx, qword [rdx+rcx*8]
11956 // mov eax, .tls$:tlsvar
11957 // [rax+rcx] contains the address
11958 // Windows 64bit: gs:0x58
11959 // Windows 32bit: fs:__tls_array
11962 SDValue Chain = DAG.getEntryNode();
11964 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11965 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11966 // use its literal value of 0x2C.
11967 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11968 ? Type::getInt8PtrTy(*DAG.getContext(),
11970 : Type::getInt32PtrTy(*DAG.getContext(),
11973 SDValue TlsArray = Subtarget->is64Bit()
11974 ? DAG.getIntPtrConstant(0x58, dl)
11975 : (Subtarget->isTargetWindowsGNU()
11976 ? DAG.getIntPtrConstant(0x2C, dl)
11977 : DAG.getExternalSymbol("_tls_array", PtrVT));
11979 SDValue ThreadPointer =
11980 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
11984 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11985 res = ThreadPointer;
11987 // Load the _tls_index variable
11988 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
11989 if (Subtarget->is64Bit())
11990 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
11991 MachinePointerInfo(), MVT::i32, false, false,
11994 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
11997 auto &DL = DAG.getDataLayout();
11999 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12000 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12002 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12005 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12008 // Get the offset of start of .tls section
12009 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12010 GA->getValueType(0),
12011 GA->getOffset(), X86II::MO_SECREL);
12012 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12014 // The address of the thread local variable is the add of the thread
12015 // pointer with the offset of the variable.
12016 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12019 llvm_unreachable("TLS not implemented for this target.");
12022 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12023 /// and take a 2 x i32 value to shift plus a shift amount.
12024 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12025 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12026 MVT VT = Op.getSimpleValueType();
12027 unsigned VTBits = VT.getSizeInBits();
12029 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12030 SDValue ShOpLo = Op.getOperand(0);
12031 SDValue ShOpHi = Op.getOperand(1);
12032 SDValue ShAmt = Op.getOperand(2);
12033 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12034 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12036 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12037 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12038 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12039 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12040 : DAG.getConstant(0, dl, VT);
12042 SDValue Tmp2, Tmp3;
12043 if (Op.getOpcode() == ISD::SHL_PARTS) {
12044 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12045 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12047 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12048 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12051 // If the shift amount is larger or equal than the width of a part we can't
12052 // rely on the results of shld/shrd. Insert a test and select the appropriate
12053 // values for large shift amounts.
12054 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12055 DAG.getConstant(VTBits, dl, MVT::i8));
12056 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12057 AndNode, DAG.getConstant(0, dl, MVT::i8));
12060 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12061 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12062 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12064 if (Op.getOpcode() == ISD::SHL_PARTS) {
12065 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12066 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12068 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12069 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12072 SDValue Ops[2] = { Lo, Hi };
12073 return DAG.getMergeValues(Ops, dl);
12076 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12077 SelectionDAG &DAG) const {
12078 SDValue Src = Op.getOperand(0);
12079 MVT SrcVT = Src.getSimpleValueType();
12080 MVT VT = Op.getSimpleValueType();
12083 if (SrcVT.isVector()) {
12084 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12085 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12086 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12087 DAG.getUNDEF(SrcVT)));
12089 if (SrcVT.getVectorElementType() == MVT::i1) {
12090 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12091 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12092 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12097 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12098 "Unknown SINT_TO_FP to lower!");
12100 // These are really Legal; return the operand so the caller accepts it as
12102 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12104 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12105 Subtarget->is64Bit()) {
12109 unsigned Size = SrcVT.getSizeInBits()/8;
12110 MachineFunction &MF = DAG.getMachineFunction();
12111 auto PtrVT = getPointerTy(MF.getDataLayout());
12112 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12113 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12114 SDValue Chain = DAG.getStore(
12115 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12116 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12118 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12121 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12123 SelectionDAG &DAG) const {
12127 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12129 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12131 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12133 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12135 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12136 MachineMemOperand *MMO;
12138 int SSFI = FI->getIndex();
12139 MMO = DAG.getMachineFunction().getMachineMemOperand(
12140 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12141 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12143 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12144 StackSlot = StackSlot.getOperand(1);
12146 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12147 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12149 Tys, Ops, SrcVT, MMO);
12152 Chain = Result.getValue(1);
12153 SDValue InFlag = Result.getValue(2);
12155 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12156 // shouldn't be necessary except that RFP cannot be live across
12157 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12158 MachineFunction &MF = DAG.getMachineFunction();
12159 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12160 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12161 auto PtrVT = getPointerTy(MF.getDataLayout());
12162 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12163 Tys = DAG.getVTList(MVT::Other);
12165 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12167 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12168 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12169 MachineMemOperand::MOStore, SSFISize, SSFISize);
12171 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12172 Ops, Op.getValueType(), MMO);
12173 Result = DAG.getLoad(
12174 Op.getValueType(), DL, Chain, StackSlot,
12175 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12176 false, false, false, 0);
12182 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12183 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12184 SelectionDAG &DAG) const {
12185 // This algorithm is not obvious. Here it is what we're trying to output:
12188 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12189 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12191 haddpd %xmm0, %xmm0
12193 pshufd $0x4e, %xmm0, %xmm1
12199 LLVMContext *Context = DAG.getContext();
12201 // Build some magic constants.
12202 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12203 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12204 auto PtrVT = getPointerTy(DAG.getDataLayout());
12205 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12207 SmallVector<Constant*,2> CV1;
12209 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12210 APInt(64, 0x4330000000000000ULL))));
12212 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12213 APInt(64, 0x4530000000000000ULL))));
12214 Constant *C1 = ConstantVector::get(CV1);
12215 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12217 // Load the 64-bit value into an XMM register.
12218 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12221 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12222 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12223 false, false, false, 16);
12225 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12228 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12229 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12230 false, false, false, 16);
12231 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12232 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12235 if (Subtarget->hasSSE3()) {
12236 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12237 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12239 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12240 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12242 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12243 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12246 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12247 DAG.getIntPtrConstant(0, dl));
12250 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12251 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12252 SelectionDAG &DAG) const {
12254 // FP constant to bias correct the final result.
12255 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12258 // Load the 32-bit value into an XMM register.
12259 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12262 // Zero out the upper parts of the register.
12263 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12265 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12266 DAG.getBitcast(MVT::v2f64, Load),
12267 DAG.getIntPtrConstant(0, dl));
12269 // Or the load with the bias.
12270 SDValue Or = DAG.getNode(
12271 ISD::OR, dl, MVT::v2i64,
12272 DAG.getBitcast(MVT::v2i64,
12273 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12274 DAG.getBitcast(MVT::v2i64,
12275 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12277 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12278 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12280 // Subtract the bias.
12281 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12283 // Handle final rounding.
12284 EVT DestVT = Op.getValueType();
12286 if (DestVT.bitsLT(MVT::f64))
12287 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12288 DAG.getIntPtrConstant(0, dl));
12289 if (DestVT.bitsGT(MVT::f64))
12290 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12292 // Handle final rounding.
12296 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12297 const X86Subtarget &Subtarget) {
12298 // The algorithm is the following:
12299 // #ifdef __SSE4_1__
12300 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12301 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12302 // (uint4) 0x53000000, 0xaa);
12304 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12305 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12307 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12308 // return (float4) lo + fhi;
12311 SDValue V = Op->getOperand(0);
12312 EVT VecIntVT = V.getValueType();
12313 bool Is128 = VecIntVT == MVT::v4i32;
12314 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12315 // If we convert to something else than the supported type, e.g., to v4f64,
12317 if (VecFloatVT != Op->getValueType(0))
12320 unsigned NumElts = VecIntVT.getVectorNumElements();
12321 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12322 "Unsupported custom type");
12323 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12325 // In the #idef/#else code, we have in common:
12326 // - The vector of constants:
12332 // Create the splat vector for 0x4b000000.
12333 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12334 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12335 CstLow, CstLow, CstLow, CstLow};
12336 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12337 makeArrayRef(&CstLowArray[0], NumElts));
12338 // Create the splat vector for 0x53000000.
12339 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12340 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12341 CstHigh, CstHigh, CstHigh, CstHigh};
12342 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12343 makeArrayRef(&CstHighArray[0], NumElts));
12345 // Create the right shift.
12346 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12347 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12348 CstShift, CstShift, CstShift, CstShift};
12349 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12350 makeArrayRef(&CstShiftArray[0], NumElts));
12351 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12354 if (Subtarget.hasSSE41()) {
12355 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12356 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12357 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12358 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12359 // Low will be bitcasted right away, so do not bother bitcasting back to its
12361 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12362 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12363 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12364 // (uint4) 0x53000000, 0xaa);
12365 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12366 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12367 // High will be bitcasted right away, so do not bother bitcasting back to
12368 // its original type.
12369 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12370 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12372 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12373 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12374 CstMask, CstMask, CstMask);
12375 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12376 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12377 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12379 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12380 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12383 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12384 SDValue CstFAdd = DAG.getConstantFP(
12385 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12386 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12387 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12388 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12389 makeArrayRef(&CstFAddArray[0], NumElts));
12391 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12392 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12394 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12395 // return (float4) lo + fhi;
12396 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12397 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12400 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12401 SelectionDAG &DAG) const {
12402 SDValue N0 = Op.getOperand(0);
12403 MVT SVT = N0.getSimpleValueType();
12406 switch (SVT.SimpleTy) {
12408 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12413 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12414 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12415 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12419 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12422 if (Subtarget->hasAVX512())
12423 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12424 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12426 llvm_unreachable(nullptr);
12429 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12430 SelectionDAG &DAG) const {
12431 SDValue N0 = Op.getOperand(0);
12433 auto PtrVT = getPointerTy(DAG.getDataLayout());
12435 if (Op.getValueType().isVector())
12436 return lowerUINT_TO_FP_vec(Op, DAG);
12438 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12439 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12440 // the optimization here.
12441 if (DAG.SignBitIsZero(N0))
12442 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12444 MVT SrcVT = N0.getSimpleValueType();
12445 MVT DstVT = Op.getSimpleValueType();
12446 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12447 return LowerUINT_TO_FP_i64(Op, DAG);
12448 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12449 return LowerUINT_TO_FP_i32(Op, DAG);
12450 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12453 // Make a 64-bit buffer, and use it to build an FILD.
12454 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12455 if (SrcVT == MVT::i32) {
12456 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12457 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12458 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12459 StackSlot, MachinePointerInfo(),
12461 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12462 OffsetSlot, MachinePointerInfo(),
12464 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12468 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12469 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12470 StackSlot, MachinePointerInfo(),
12472 // For i64 source, we need to add the appropriate power of 2 if the input
12473 // was negative. This is the same as the optimization in
12474 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12475 // we must be careful to do the computation in x87 extended precision, not
12476 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12477 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12478 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12479 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12480 MachineMemOperand::MOLoad, 8, 8);
12482 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12483 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12484 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12487 APInt FF(32, 0x5F800000ULL);
12489 // Check whether the sign bit is set.
12490 SDValue SignSet = DAG.getSetCC(
12491 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12492 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12494 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12495 SDValue FudgePtr = DAG.getConstantPool(
12496 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12498 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12499 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12500 SDValue Four = DAG.getIntPtrConstant(4, dl);
12501 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12503 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12505 // Load the value out, extending it from f32 to f80.
12506 // FIXME: Avoid the extend by constructing the right constant pool?
12507 SDValue Fudge = DAG.getExtLoad(
12508 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12509 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12510 false, false, false, 4);
12511 // Extend everything to 80 bits to force it to be done on x87.
12512 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12513 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12514 DAG.getIntPtrConstant(0, dl));
12517 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12518 // is legal, or has an f16 source (which needs to be promoted to f32),
12519 // just return an <SDValue(), SDValue()> pair.
12520 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12521 // to i16, i32 or i64, and we lower it to a legal sequence.
12522 // If lowered to the final integer result we return a <result, SDValue()> pair.
12523 // Otherwise we lower it to a sequence ending with a FIST, return a
12524 // <FIST, StackSlot> pair, and the caller is responsible for loading
12525 // the final integer result from StackSlot.
12526 std::pair<SDValue,SDValue>
12527 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12528 bool IsSigned, bool IsReplace) const {
12531 EVT DstTy = Op.getValueType();
12532 EVT TheVT = Op.getOperand(0).getValueType();
12533 auto PtrVT = getPointerTy(DAG.getDataLayout());
12535 if (TheVT == MVT::f16)
12536 // We need to promote the f16 to f32 before using the lowering
12537 // in this routine.
12538 return std::make_pair(SDValue(), SDValue());
12540 assert((TheVT == MVT::f32 ||
12541 TheVT == MVT::f64 ||
12542 TheVT == MVT::f80) &&
12543 "Unexpected FP operand type in FP_TO_INTHelper");
12545 // If using FIST to compute an unsigned i64, we'll need some fixup
12546 // to handle values above the maximum signed i64. A FIST is always
12547 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12548 bool UnsignedFixup = !IsSigned &&
12549 DstTy == MVT::i64 &&
12550 (!Subtarget->is64Bit() ||
12551 !isScalarFPTypeInSSEReg(TheVT));
12553 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12554 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12555 // The low 32 bits of the fist result will have the correct uint32 result.
12556 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12560 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12561 DstTy.getSimpleVT() >= MVT::i16 &&
12562 "Unknown FP_TO_INT to lower!");
12564 // These are really Legal.
12565 if (DstTy == MVT::i32 &&
12566 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12567 return std::make_pair(SDValue(), SDValue());
12568 if (Subtarget->is64Bit() &&
12569 DstTy == MVT::i64 &&
12570 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12571 return std::make_pair(SDValue(), SDValue());
12573 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12575 MachineFunction &MF = DAG.getMachineFunction();
12576 unsigned MemSize = DstTy.getSizeInBits()/8;
12577 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12578 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12581 switch (DstTy.getSimpleVT().SimpleTy) {
12582 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12583 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12584 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12585 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12588 SDValue Chain = DAG.getEntryNode();
12589 SDValue Value = Op.getOperand(0);
12590 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12592 if (UnsignedFixup) {
12594 // Conversion to unsigned i64 is implemented with a select,
12595 // depending on whether the source value fits in the range
12596 // of a signed i64. Let Thresh be the FP equivalent of
12597 // 0x8000000000000000ULL.
12599 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12600 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12601 // Fist-to-mem64 FistSrc
12602 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12603 // to XOR'ing the high 32 bits with Adjust.
12605 // Being a power of 2, Thresh is exactly representable in all FP formats.
12606 // For X87 we'd like to use the smallest FP type for this constant, but
12607 // for DAG type consistency we have to match the FP operand type.
12609 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12610 APFloat::opStatus Status = APFloat::opOK;
12611 bool LosesInfo = false;
12612 if (TheVT == MVT::f64)
12613 // The rounding mode is irrelevant as the conversion should be exact.
12614 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12616 else if (TheVT == MVT::f80)
12617 Status = Thresh.convert(APFloat::x87DoubleExtended,
12618 APFloat::rmNearestTiesToEven, &LosesInfo);
12620 assert(Status == APFloat::opOK && !LosesInfo &&
12621 "FP conversion should have been exact");
12623 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12625 SDValue Cmp = DAG.getSetCC(DL,
12626 getSetCCResultType(DAG.getDataLayout(),
12627 *DAG.getContext(), TheVT),
12628 Value, ThreshVal, ISD::SETLT);
12629 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12630 DAG.getConstant(0, DL, MVT::i32),
12631 DAG.getConstant(0x80000000, DL, MVT::i32));
12632 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12633 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12634 *DAG.getContext(), TheVT),
12635 Value, ThreshVal, ISD::SETLT);
12636 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12639 // FIXME This causes a redundant load/store if the SSE-class value is already
12640 // in memory, such as if it is on the callstack.
12641 if (isScalarFPTypeInSSEReg(TheVT)) {
12642 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12643 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12644 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12646 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12648 Chain, StackSlot, DAG.getValueType(TheVT)
12651 MachineMemOperand *MMO =
12652 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12653 MachineMemOperand::MOLoad, MemSize, MemSize);
12654 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12655 Chain = Value.getValue(1);
12656 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12657 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12660 MachineMemOperand *MMO =
12661 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12662 MachineMemOperand::MOStore, MemSize, MemSize);
12664 if (UnsignedFixup) {
12666 // Insert the FIST, load its result as two i32's,
12667 // and XOR the high i32 with Adjust.
12669 SDValue FistOps[] = { Chain, Value, StackSlot };
12670 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12671 FistOps, DstTy, MMO);
12673 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12674 MachinePointerInfo(),
12675 false, false, false, 0);
12676 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12677 DAG.getConstant(4, DL, PtrVT));
12679 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12680 MachinePointerInfo(),
12681 false, false, false, 0);
12682 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12684 if (Subtarget->is64Bit()) {
12685 // Join High32 and Low32 into a 64-bit result.
12686 // (High32 << 32) | Low32
12687 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12688 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12689 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12690 DAG.getConstant(32, DL, MVT::i8));
12691 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12692 return std::make_pair(Result, SDValue());
12695 SDValue ResultOps[] = { Low32, High32 };
12697 SDValue pair = IsReplace
12698 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12699 : DAG.getMergeValues(ResultOps, DL);
12700 return std::make_pair(pair, SDValue());
12702 // Build the FP_TO_INT*_IN_MEM
12703 SDValue Ops[] = { Chain, Value, StackSlot };
12704 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12706 return std::make_pair(FIST, StackSlot);
12710 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12711 const X86Subtarget *Subtarget) {
12712 MVT VT = Op->getSimpleValueType(0);
12713 SDValue In = Op->getOperand(0);
12714 MVT InVT = In.getSimpleValueType();
12717 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12718 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12720 // Optimize vectors in AVX mode:
12723 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12724 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12725 // Concat upper and lower parts.
12728 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12729 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12730 // Concat upper and lower parts.
12733 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12734 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12735 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12738 if (Subtarget->hasInt256())
12739 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12741 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12742 SDValue Undef = DAG.getUNDEF(InVT);
12743 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12744 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12745 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12747 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12748 VT.getVectorNumElements()/2);
12750 OpLo = DAG.getBitcast(HVT, OpLo);
12751 OpHi = DAG.getBitcast(HVT, OpHi);
12753 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12756 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12757 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12758 MVT VT = Op->getSimpleValueType(0);
12759 SDValue In = Op->getOperand(0);
12760 MVT InVT = In.getSimpleValueType();
12762 unsigned int NumElts = VT.getVectorNumElements();
12763 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12766 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12767 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12769 assert(InVT.getVectorElementType() == MVT::i1);
12770 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12772 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12774 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12776 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12777 if (VT.is512BitVector())
12779 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12782 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12783 SelectionDAG &DAG) {
12784 if (Subtarget->hasFp256())
12785 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12791 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12792 SelectionDAG &DAG) {
12794 MVT VT = Op.getSimpleValueType();
12795 SDValue In = Op.getOperand(0);
12796 MVT SVT = In.getSimpleValueType();
12798 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12799 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12801 if (Subtarget->hasFp256())
12802 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12805 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12806 VT.getVectorNumElements() != SVT.getVectorNumElements());
12810 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12812 MVT VT = Op.getSimpleValueType();
12813 SDValue In = Op.getOperand(0);
12814 MVT InVT = In.getSimpleValueType();
12816 if (VT == MVT::i1) {
12817 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12818 "Invalid scalar TRUNCATE operation");
12819 if (InVT.getSizeInBits() >= 32)
12821 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12822 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12824 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12825 "Invalid TRUNCATE operation");
12827 // move vector to mask - truncate solution for SKX
12828 if (VT.getVectorElementType() == MVT::i1) {
12829 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12830 Subtarget->hasBWI())
12831 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12832 if ((InVT.is256BitVector() || InVT.is128BitVector())
12833 && InVT.getScalarSizeInBits() <= 16 &&
12834 Subtarget->hasBWI() && Subtarget->hasVLX())
12835 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12836 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12837 Subtarget->hasDQI())
12838 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12839 if ((InVT.is256BitVector() || InVT.is128BitVector())
12840 && InVT.getScalarSizeInBits() >= 32 &&
12841 Subtarget->hasDQI() && Subtarget->hasVLX())
12842 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12845 if (VT.getVectorElementType() == MVT::i1) {
12846 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12847 unsigned NumElts = InVT.getVectorNumElements();
12848 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12849 if (InVT.getSizeInBits() < 512) {
12850 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12851 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12856 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12857 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12858 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12861 // vpmovqb/w/d, vpmovdb/w, vpmovwb
12862 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
12863 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
12864 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12866 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12867 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12868 if (Subtarget->hasInt256()) {
12869 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12870 In = DAG.getBitcast(MVT::v8i32, In);
12871 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12873 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12874 DAG.getIntPtrConstant(0, DL));
12877 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12878 DAG.getIntPtrConstant(0, DL));
12879 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12880 DAG.getIntPtrConstant(2, DL));
12881 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12882 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12883 static const int ShufMask[] = {0, 2, 4, 6};
12884 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12887 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12888 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12889 if (Subtarget->hasInt256()) {
12890 In = DAG.getBitcast(MVT::v32i8, In);
12892 SmallVector<SDValue,32> pshufbMask;
12893 for (unsigned i = 0; i < 2; ++i) {
12894 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12895 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12896 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12897 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12898 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12899 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12900 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12901 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12902 for (unsigned j = 0; j < 8; ++j)
12903 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12905 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12906 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12907 In = DAG.getBitcast(MVT::v4i64, In);
12909 static const int ShufMask[] = {0, 2, -1, -1};
12910 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12912 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12913 DAG.getIntPtrConstant(0, DL));
12914 return DAG.getBitcast(VT, In);
12917 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12918 DAG.getIntPtrConstant(0, DL));
12920 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12921 DAG.getIntPtrConstant(4, DL));
12923 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12924 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12926 // The PSHUFB mask:
12927 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12928 -1, -1, -1, -1, -1, -1, -1, -1};
12930 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12931 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12932 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12934 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12935 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12937 // The MOVLHPS Mask:
12938 static const int ShufMask2[] = {0, 1, 4, 5};
12939 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12940 return DAG.getBitcast(MVT::v8i16, res);
12943 // Handle truncation of V256 to V128 using shuffles.
12944 if (!VT.is128BitVector() || !InVT.is256BitVector())
12947 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12949 unsigned NumElems = VT.getVectorNumElements();
12950 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12952 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12953 // Prepare truncation shuffle mask
12954 for (unsigned i = 0; i != NumElems; ++i)
12955 MaskVec[i] = i * 2;
12956 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12957 DAG.getUNDEF(NVT), &MaskVec[0]);
12958 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12959 DAG.getIntPtrConstant(0, DL));
12962 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12963 SelectionDAG &DAG) const {
12964 assert(!Op.getSimpleValueType().isVector());
12966 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12967 /*IsSigned=*/ true, /*IsReplace=*/ false);
12968 SDValue FIST = Vals.first, StackSlot = Vals.second;
12969 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12970 if (!FIST.getNode())
12973 if (StackSlot.getNode())
12974 // Load the result.
12975 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12976 FIST, StackSlot, MachinePointerInfo(),
12977 false, false, false, 0);
12979 // The node is the result.
12983 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12984 SelectionDAG &DAG) const {
12985 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12986 /*IsSigned=*/ false, /*IsReplace=*/ false);
12987 SDValue FIST = Vals.first, StackSlot = Vals.second;
12988 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12989 if (!FIST.getNode())
12992 if (StackSlot.getNode())
12993 // Load the result.
12994 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12995 FIST, StackSlot, MachinePointerInfo(),
12996 false, false, false, 0);
12998 // The node is the result.
13002 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13004 MVT VT = Op.getSimpleValueType();
13005 SDValue In = Op.getOperand(0);
13006 MVT SVT = In.getSimpleValueType();
13008 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13010 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13011 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13012 In, DAG.getUNDEF(SVT)));
13015 /// The only differences between FABS and FNEG are the mask and the logic op.
13016 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13017 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13018 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13019 "Wrong opcode for lowering FABS or FNEG.");
13021 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13023 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13024 // into an FNABS. We'll lower the FABS after that if it is still in use.
13026 for (SDNode *User : Op->uses())
13027 if (User->getOpcode() == ISD::FNEG)
13031 MVT VT = Op.getSimpleValueType();
13033 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13034 // decide if we should generate a 16-byte constant mask when we only need 4 or
13035 // 8 bytes for the scalar case.
13041 if (VT.isVector()) {
13043 EltVT = VT.getVectorElementType();
13044 NumElts = VT.getVectorNumElements();
13046 // There are no scalar bitwise logical SSE/AVX instructions, so we
13047 // generate a 16-byte vector constant and logic op even for the scalar case.
13048 // Using a 16-byte mask allows folding the load of the mask with
13049 // the logic op, so it can save (~4 bytes) on code size.
13050 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13052 NumElts = (VT == MVT::f64) ? 2 : 4;
13055 unsigned EltBits = EltVT.getSizeInBits();
13056 LLVMContext *Context = DAG.getContext();
13057 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13059 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13060 Constant *C = ConstantInt::get(*Context, MaskElt);
13061 C = ConstantVector::getSplat(NumElts, C);
13062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13063 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13064 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13066 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13067 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13068 false, false, false, Alignment);
13070 SDValue Op0 = Op.getOperand(0);
13071 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13073 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13074 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13077 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13079 // For the scalar case extend to a 128-bit vector, perform the logic op,
13080 // and extract the scalar result back out.
13081 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13082 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13083 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13084 DAG.getIntPtrConstant(0, dl));
13087 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13088 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13089 LLVMContext *Context = DAG.getContext();
13090 SDValue Op0 = Op.getOperand(0);
13091 SDValue Op1 = Op.getOperand(1);
13093 MVT VT = Op.getSimpleValueType();
13094 MVT SrcVT = Op1.getSimpleValueType();
13096 // If second operand is smaller, extend it first.
13097 if (SrcVT.bitsLT(VT)) {
13098 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13101 // And if it is bigger, shrink it first.
13102 if (SrcVT.bitsGT(VT)) {
13103 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13107 // At this point the operands and the result should have the same
13108 // type, and that won't be f80 since that is not custom lowered.
13110 const fltSemantics &Sem =
13111 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13112 const unsigned SizeInBits = VT.getSizeInBits();
13114 SmallVector<Constant *, 4> CV(
13115 VT == MVT::f64 ? 2 : 4,
13116 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13118 // First, clear all bits but the sign bit from the second operand (sign).
13119 CV[0] = ConstantFP::get(*Context,
13120 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13121 Constant *C = ConstantVector::get(CV);
13122 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13123 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13125 // Perform all logic operations as 16-byte vectors because there are no
13126 // scalar FP logic instructions in SSE. This allows load folding of the
13127 // constants into the logic instructions.
13128 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13130 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13131 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13132 false, false, false, 16);
13133 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13134 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13136 // Next, clear the sign bit from the first operand (magnitude).
13137 // If it's a constant, we can clear it here.
13138 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13139 APFloat APF = Op0CN->getValueAPF();
13140 // If the magnitude is a positive zero, the sign bit alone is enough.
13141 if (APF.isPosZero())
13142 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13143 DAG.getIntPtrConstant(0, dl));
13145 CV[0] = ConstantFP::get(*Context, APF);
13147 CV[0] = ConstantFP::get(
13149 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13151 C = ConstantVector::get(CV);
13152 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13154 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13155 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13156 false, false, false, 16);
13157 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13158 if (!isa<ConstantFPSDNode>(Op0)) {
13159 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13160 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13162 // OR the magnitude value with the sign bit.
13163 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13164 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13165 DAG.getIntPtrConstant(0, dl));
13168 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13169 SDValue N0 = Op.getOperand(0);
13171 MVT VT = Op.getSimpleValueType();
13173 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13174 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13175 DAG.getConstant(1, dl, VT));
13176 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13179 // Check whether an OR'd tree is PTEST-able.
13180 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13181 SelectionDAG &DAG) {
13182 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13184 if (!Subtarget->hasSSE41())
13187 if (!Op->hasOneUse())
13190 SDNode *N = Op.getNode();
13193 SmallVector<SDValue, 8> Opnds;
13194 DenseMap<SDValue, unsigned> VecInMap;
13195 SmallVector<SDValue, 8> VecIns;
13196 EVT VT = MVT::Other;
13198 // Recognize a special case where a vector is casted into wide integer to
13200 Opnds.push_back(N->getOperand(0));
13201 Opnds.push_back(N->getOperand(1));
13203 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13204 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13205 // BFS traverse all OR'd operands.
13206 if (I->getOpcode() == ISD::OR) {
13207 Opnds.push_back(I->getOperand(0));
13208 Opnds.push_back(I->getOperand(1));
13209 // Re-evaluate the number of nodes to be traversed.
13210 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13214 // Quit if a non-EXTRACT_VECTOR_ELT
13215 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13218 // Quit if without a constant index.
13219 SDValue Idx = I->getOperand(1);
13220 if (!isa<ConstantSDNode>(Idx))
13223 SDValue ExtractedFromVec = I->getOperand(0);
13224 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13225 if (M == VecInMap.end()) {
13226 VT = ExtractedFromVec.getValueType();
13227 // Quit if not 128/256-bit vector.
13228 if (!VT.is128BitVector() && !VT.is256BitVector())
13230 // Quit if not the same type.
13231 if (VecInMap.begin() != VecInMap.end() &&
13232 VT != VecInMap.begin()->first.getValueType())
13234 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13235 VecIns.push_back(ExtractedFromVec);
13237 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13240 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13241 "Not extracted from 128-/256-bit vector.");
13243 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13245 for (DenseMap<SDValue, unsigned>::const_iterator
13246 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13247 // Quit if not all elements are used.
13248 if (I->second != FullMask)
13252 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13254 // Cast all vectors into TestVT for PTEST.
13255 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13256 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13258 // If more than one full vectors are evaluated, OR them first before PTEST.
13259 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13260 // Each iteration will OR 2 nodes and append the result until there is only
13261 // 1 node left, i.e. the final OR'd value of all vectors.
13262 SDValue LHS = VecIns[Slot];
13263 SDValue RHS = VecIns[Slot + 1];
13264 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13267 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13268 VecIns.back(), VecIns.back());
13271 /// \brief return true if \c Op has a use that doesn't just read flags.
13272 static bool hasNonFlagsUse(SDValue Op) {
13273 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13275 SDNode *User = *UI;
13276 unsigned UOpNo = UI.getOperandNo();
13277 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13278 // Look pass truncate.
13279 UOpNo = User->use_begin().getOperandNo();
13280 User = *User->use_begin();
13283 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13284 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13290 /// Emit nodes that will be selected as "test Op0,Op0", or something
13292 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13293 SelectionDAG &DAG) const {
13294 if (Op.getValueType() == MVT::i1) {
13295 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13296 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13297 DAG.getConstant(0, dl, MVT::i8));
13299 // CF and OF aren't always set the way we want. Determine which
13300 // of these we need.
13301 bool NeedCF = false;
13302 bool NeedOF = false;
13305 case X86::COND_A: case X86::COND_AE:
13306 case X86::COND_B: case X86::COND_BE:
13309 case X86::COND_G: case X86::COND_GE:
13310 case X86::COND_L: case X86::COND_LE:
13311 case X86::COND_O: case X86::COND_NO: {
13312 // Check if we really need to set the
13313 // Overflow flag. If NoSignedWrap is present
13314 // that is not actually needed.
13315 switch (Op->getOpcode()) {
13320 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13321 if (BinNode->Flags.hasNoSignedWrap())
13331 // See if we can use the EFLAGS value from the operand instead of
13332 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13333 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13334 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13335 // Emit a CMP with 0, which is the TEST pattern.
13336 //if (Op.getValueType() == MVT::i1)
13337 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13338 // DAG.getConstant(0, MVT::i1));
13339 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13340 DAG.getConstant(0, dl, Op.getValueType()));
13342 unsigned Opcode = 0;
13343 unsigned NumOperands = 0;
13345 // Truncate operations may prevent the merge of the SETCC instruction
13346 // and the arithmetic instruction before it. Attempt to truncate the operands
13347 // of the arithmetic instruction and use a reduced bit-width instruction.
13348 bool NeedTruncation = false;
13349 SDValue ArithOp = Op;
13350 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13351 SDValue Arith = Op->getOperand(0);
13352 // Both the trunc and the arithmetic op need to have one user each.
13353 if (Arith->hasOneUse())
13354 switch (Arith.getOpcode()) {
13361 NeedTruncation = true;
13367 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13368 // which may be the result of a CAST. We use the variable 'Op', which is the
13369 // non-casted variable when we check for possible users.
13370 switch (ArithOp.getOpcode()) {
13372 // Due to an isel shortcoming, be conservative if this add is likely to be
13373 // selected as part of a load-modify-store instruction. When the root node
13374 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13375 // uses of other nodes in the match, such as the ADD in this case. This
13376 // leads to the ADD being left around and reselected, with the result being
13377 // two adds in the output. Alas, even if none our users are stores, that
13378 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13379 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13380 // climbing the DAG back to the root, and it doesn't seem to be worth the
13382 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13383 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13384 if (UI->getOpcode() != ISD::CopyToReg &&
13385 UI->getOpcode() != ISD::SETCC &&
13386 UI->getOpcode() != ISD::STORE)
13389 if (ConstantSDNode *C =
13390 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13391 // An add of one will be selected as an INC.
13392 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13393 Opcode = X86ISD::INC;
13398 // An add of negative one (subtract of one) will be selected as a DEC.
13399 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13400 Opcode = X86ISD::DEC;
13406 // Otherwise use a regular EFLAGS-setting add.
13407 Opcode = X86ISD::ADD;
13412 // If we have a constant logical shift that's only used in a comparison
13413 // against zero turn it into an equivalent AND. This allows turning it into
13414 // a TEST instruction later.
13415 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13416 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13417 EVT VT = Op.getValueType();
13418 unsigned BitWidth = VT.getSizeInBits();
13419 unsigned ShAmt = Op->getConstantOperandVal(1);
13420 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13422 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13423 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13424 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13425 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13427 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13428 DAG.getConstant(Mask, dl, VT));
13429 DAG.ReplaceAllUsesWith(Op, New);
13435 // If the primary and result isn't used, don't bother using X86ISD::AND,
13436 // because a TEST instruction will be better.
13437 if (!hasNonFlagsUse(Op))
13443 // Due to the ISEL shortcoming noted above, be conservative if this op is
13444 // likely to be selected as part of a load-modify-store instruction.
13445 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13446 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13447 if (UI->getOpcode() == ISD::STORE)
13450 // Otherwise use a regular EFLAGS-setting instruction.
13451 switch (ArithOp.getOpcode()) {
13452 default: llvm_unreachable("unexpected operator!");
13453 case ISD::SUB: Opcode = X86ISD::SUB; break;
13454 case ISD::XOR: Opcode = X86ISD::XOR; break;
13455 case ISD::AND: Opcode = X86ISD::AND; break;
13457 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13458 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13459 if (EFLAGS.getNode())
13462 Opcode = X86ISD::OR;
13476 return SDValue(Op.getNode(), 1);
13482 // If we found that truncation is beneficial, perform the truncation and
13484 if (NeedTruncation) {
13485 EVT VT = Op.getValueType();
13486 SDValue WideVal = Op->getOperand(0);
13487 EVT WideVT = WideVal.getValueType();
13488 unsigned ConvertedOp = 0;
13489 // Use a target machine opcode to prevent further DAGCombine
13490 // optimizations that may separate the arithmetic operations
13491 // from the setcc node.
13492 switch (WideVal.getOpcode()) {
13494 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13495 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13496 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13497 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13498 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13502 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13503 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13504 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13505 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13506 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13512 // Emit a CMP with 0, which is the TEST pattern.
13513 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13514 DAG.getConstant(0, dl, Op.getValueType()));
13516 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13517 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13519 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13520 DAG.ReplaceAllUsesWith(Op, New);
13521 return SDValue(New.getNode(), 1);
13524 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13526 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13527 SDLoc dl, SelectionDAG &DAG) const {
13528 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13529 if (C->getAPIntValue() == 0)
13530 return EmitTest(Op0, X86CC, dl, DAG);
13532 if (Op0.getValueType() == MVT::i1)
13533 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13536 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13537 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13538 // Do the comparison at i32 if it's smaller, besides the Atom case.
13539 // This avoids subregister aliasing issues. Keep the smaller reference
13540 // if we're optimizing for size, however, as that'll allow better folding
13541 // of memory operations.
13542 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13543 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13544 !Subtarget->isAtom()) {
13545 unsigned ExtendOp =
13546 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13547 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13548 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13550 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13551 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13552 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13554 return SDValue(Sub.getNode(), 1);
13556 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13559 /// Convert a comparison if required by the subtarget.
13560 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13561 SelectionDAG &DAG) const {
13562 // If the subtarget does not support the FUCOMI instruction, floating-point
13563 // comparisons have to be converted.
13564 if (Subtarget->hasCMov() ||
13565 Cmp.getOpcode() != X86ISD::CMP ||
13566 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13567 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13570 // The instruction selector will select an FUCOM instruction instead of
13571 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13572 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13573 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13575 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13576 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13577 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13578 DAG.getConstant(8, dl, MVT::i8));
13579 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13580 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13583 /// The minimum architected relative accuracy is 2^-12. We need one
13584 /// Newton-Raphson step to have a good float result (24 bits of precision).
13585 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13586 DAGCombinerInfo &DCI,
13587 unsigned &RefinementSteps,
13588 bool &UseOneConstNR) const {
13589 EVT VT = Op.getValueType();
13590 const char *RecipOp;
13592 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13593 // TODO: Add support for AVX512 (v16f32).
13594 // It is likely not profitable to do this for f64 because a double-precision
13595 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13596 // instructions: convert to single, rsqrtss, convert back to double, refine
13597 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13598 // along with FMA, this could be a throughput win.
13599 if (VT == MVT::f32 && Subtarget->hasSSE1())
13601 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13602 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13603 RecipOp = "vec-sqrtf";
13607 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13608 if (!Recips.isEnabled(RecipOp))
13611 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13612 UseOneConstNR = false;
13613 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13616 /// The minimum architected relative accuracy is 2^-12. We need one
13617 /// Newton-Raphson step to have a good float result (24 bits of precision).
13618 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13619 DAGCombinerInfo &DCI,
13620 unsigned &RefinementSteps) const {
13621 EVT VT = Op.getValueType();
13622 const char *RecipOp;
13624 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13625 // TODO: Add support for AVX512 (v16f32).
13626 // It is likely not profitable to do this for f64 because a double-precision
13627 // reciprocal estimate with refinement on x86 prior to FMA requires
13628 // 15 instructions: convert to single, rcpss, convert back to double, refine
13629 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13630 // along with FMA, this could be a throughput win.
13631 if (VT == MVT::f32 && Subtarget->hasSSE1())
13633 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13634 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13635 RecipOp = "vec-divf";
13639 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13640 if (!Recips.isEnabled(RecipOp))
13643 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13644 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13647 /// If we have at least two divisions that use the same divisor, convert to
13648 /// multplication by a reciprocal. This may need to be adjusted for a given
13649 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13650 /// This is because we still need one division to calculate the reciprocal and
13651 /// then we need two multiplies by that reciprocal as replacements for the
13652 /// original divisions.
13653 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13657 static bool isAllOnes(SDValue V) {
13658 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13659 return C && C->isAllOnesValue();
13662 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13663 /// if it's possible.
13664 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13665 SDLoc dl, SelectionDAG &DAG) const {
13666 SDValue Op0 = And.getOperand(0);
13667 SDValue Op1 = And.getOperand(1);
13668 if (Op0.getOpcode() == ISD::TRUNCATE)
13669 Op0 = Op0.getOperand(0);
13670 if (Op1.getOpcode() == ISD::TRUNCATE)
13671 Op1 = Op1.getOperand(0);
13674 if (Op1.getOpcode() == ISD::SHL)
13675 std::swap(Op0, Op1);
13676 if (Op0.getOpcode() == ISD::SHL) {
13677 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13678 if (And00C->getZExtValue() == 1) {
13679 // If we looked past a truncate, check that it's only truncating away
13681 unsigned BitWidth = Op0.getValueSizeInBits();
13682 unsigned AndBitWidth = And.getValueSizeInBits();
13683 if (BitWidth > AndBitWidth) {
13685 DAG.computeKnownBits(Op0, Zeros, Ones);
13686 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13690 RHS = Op0.getOperand(1);
13692 } else if (Op1.getOpcode() == ISD::Constant) {
13693 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13694 uint64_t AndRHSVal = AndRHS->getZExtValue();
13695 SDValue AndLHS = Op0;
13697 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13698 LHS = AndLHS.getOperand(0);
13699 RHS = AndLHS.getOperand(1);
13702 // Use BT if the immediate can't be encoded in a TEST instruction.
13703 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13705 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13709 if (LHS.getNode()) {
13710 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13711 // instruction. Since the shift amount is in-range-or-undefined, we know
13712 // that doing a bittest on the i32 value is ok. We extend to i32 because
13713 // the encoding for the i16 version is larger than the i32 version.
13714 // Also promote i16 to i32 for performance / code size reason.
13715 if (LHS.getValueType() == MVT::i8 ||
13716 LHS.getValueType() == MVT::i16)
13717 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13719 // If the operand types disagree, extend the shift amount to match. Since
13720 // BT ignores high bits (like shifts) we can use anyextend.
13721 if (LHS.getValueType() != RHS.getValueType())
13722 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13724 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13725 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13726 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13727 DAG.getConstant(Cond, dl, MVT::i8), BT);
13733 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13735 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13740 // SSE Condition code mapping:
13749 switch (SetCCOpcode) {
13750 default: llvm_unreachable("Unexpected SETCC condition");
13752 case ISD::SETEQ: SSECC = 0; break;
13754 case ISD::SETGT: Swap = true; // Fallthrough
13756 case ISD::SETOLT: SSECC = 1; break;
13758 case ISD::SETGE: Swap = true; // Fallthrough
13760 case ISD::SETOLE: SSECC = 2; break;
13761 case ISD::SETUO: SSECC = 3; break;
13763 case ISD::SETNE: SSECC = 4; break;
13764 case ISD::SETULE: Swap = true; // Fallthrough
13765 case ISD::SETUGE: SSECC = 5; break;
13766 case ISD::SETULT: Swap = true; // Fallthrough
13767 case ISD::SETUGT: SSECC = 6; break;
13768 case ISD::SETO: SSECC = 7; break;
13770 case ISD::SETONE: SSECC = 8; break;
13773 std::swap(Op0, Op1);
13778 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13779 // ones, and then concatenate the result back.
13780 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13781 MVT VT = Op.getSimpleValueType();
13783 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13784 "Unsupported value type for operation");
13786 unsigned NumElems = VT.getVectorNumElements();
13788 SDValue CC = Op.getOperand(2);
13790 // Extract the LHS vectors
13791 SDValue LHS = Op.getOperand(0);
13792 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13793 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13795 // Extract the RHS vectors
13796 SDValue RHS = Op.getOperand(1);
13797 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13798 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13800 // Issue the operation on the smaller types and concatenate the result back
13801 MVT EltVT = VT.getVectorElementType();
13802 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13803 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13804 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13805 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13808 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13809 SDValue Op0 = Op.getOperand(0);
13810 SDValue Op1 = Op.getOperand(1);
13811 SDValue CC = Op.getOperand(2);
13812 MVT VT = Op.getSimpleValueType();
13815 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13816 "Unexpected type for boolean compare operation");
13817 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13818 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13819 DAG.getConstant(-1, dl, VT));
13820 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13821 DAG.getConstant(-1, dl, VT));
13822 switch (SetCCOpcode) {
13823 default: llvm_unreachable("Unexpected SETCC condition");
13825 // (x == y) -> ~(x ^ y)
13826 return DAG.getNode(ISD::XOR, dl, VT,
13827 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13828 DAG.getConstant(-1, dl, VT));
13830 // (x != y) -> (x ^ y)
13831 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13834 // (x > y) -> (x & ~y)
13835 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13838 // (x < y) -> (~x & y)
13839 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13842 // (x <= y) -> (~x | y)
13843 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13846 // (x >=y) -> (x | ~y)
13847 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13851 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13852 const X86Subtarget *Subtarget) {
13853 SDValue Op0 = Op.getOperand(0);
13854 SDValue Op1 = Op.getOperand(1);
13855 SDValue CC = Op.getOperand(2);
13856 MVT VT = Op.getSimpleValueType();
13859 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13860 Op.getValueType().getScalarType() == MVT::i1 &&
13861 "Cannot set masked compare for this operation");
13863 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13865 bool Unsigned = false;
13868 switch (SetCCOpcode) {
13869 default: llvm_unreachable("Unexpected SETCC condition");
13870 case ISD::SETNE: SSECC = 4; break;
13871 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13872 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13873 case ISD::SETLT: Swap = true; //fall-through
13874 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13875 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13876 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13877 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13878 case ISD::SETULE: Unsigned = true; //fall-through
13879 case ISD::SETLE: SSECC = 2; break;
13883 std::swap(Op0, Op1);
13885 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13886 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13887 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13888 DAG.getConstant(SSECC, dl, MVT::i8));
13891 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13892 /// operand \p Op1. If non-trivial (for example because it's not constant)
13893 /// return an empty value.
13894 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13896 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13900 MVT VT = Op1.getSimpleValueType();
13901 MVT EVT = VT.getVectorElementType();
13902 unsigned n = VT.getVectorNumElements();
13903 SmallVector<SDValue, 8> ULTOp1;
13905 for (unsigned i = 0; i < n; ++i) {
13906 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13907 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13910 // Avoid underflow.
13911 APInt Val = Elt->getAPIntValue();
13915 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13918 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13921 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13922 SelectionDAG &DAG) {
13923 SDValue Op0 = Op.getOperand(0);
13924 SDValue Op1 = Op.getOperand(1);
13925 SDValue CC = Op.getOperand(2);
13926 MVT VT = Op.getSimpleValueType();
13927 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13928 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13933 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13934 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13937 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13938 unsigned Opc = X86ISD::CMPP;
13939 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13940 assert(VT.getVectorNumElements() <= 16);
13941 Opc = X86ISD::CMPM;
13943 // In the two special cases we can't handle, emit two comparisons.
13946 unsigned CombineOpc;
13947 if (SetCCOpcode == ISD::SETUEQ) {
13948 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13950 assert(SetCCOpcode == ISD::SETONE);
13951 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13954 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13955 DAG.getConstant(CC0, dl, MVT::i8));
13956 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13957 DAG.getConstant(CC1, dl, MVT::i8));
13958 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13960 // Handle all other FP comparisons here.
13961 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13962 DAG.getConstant(SSECC, dl, MVT::i8));
13965 // Break 256-bit integer vector compare into smaller ones.
13966 if (VT.is256BitVector() && !Subtarget->hasInt256())
13967 return Lower256IntVSETCC(Op, DAG);
13969 EVT OpVT = Op1.getValueType();
13970 if (OpVT.getVectorElementType() == MVT::i1)
13971 return LowerBoolVSETCC_AVX512(Op, DAG);
13973 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13974 if (Subtarget->hasAVX512()) {
13975 if (Op1.getValueType().is512BitVector() ||
13976 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13977 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13978 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13980 // In AVX-512 architecture setcc returns mask with i1 elements,
13981 // But there is no compare instruction for i8 and i16 elements in KNL.
13982 // We are not talking about 512-bit operands in this case, these
13983 // types are illegal.
13985 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13986 OpVT.getVectorElementType().getSizeInBits() >= 8))
13987 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13988 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13991 // We are handling one of the integer comparisons here. Since SSE only has
13992 // GT and EQ comparisons for integer, swapping operands and multiple
13993 // operations may be required for some comparisons.
13995 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13996 bool Subus = false;
13998 switch (SetCCOpcode) {
13999 default: llvm_unreachable("Unexpected SETCC condition");
14000 case ISD::SETNE: Invert = true;
14001 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14002 case ISD::SETLT: Swap = true;
14003 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14004 case ISD::SETGE: Swap = true;
14005 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14006 Invert = true; break;
14007 case ISD::SETULT: Swap = true;
14008 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14009 FlipSigns = true; break;
14010 case ISD::SETUGE: Swap = true;
14011 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14012 FlipSigns = true; Invert = true; break;
14015 // Special case: Use min/max operations for SETULE/SETUGE
14016 MVT VET = VT.getVectorElementType();
14018 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14019 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14022 switch (SetCCOpcode) {
14024 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14025 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14028 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14031 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14032 if (!MinMax && hasSubus) {
14033 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14035 // t = psubus Op0, Op1
14036 // pcmpeq t, <0..0>
14037 switch (SetCCOpcode) {
14039 case ISD::SETULT: {
14040 // If the comparison is against a constant we can turn this into a
14041 // setule. With psubus, setule does not require a swap. This is
14042 // beneficial because the constant in the register is no longer
14043 // destructed as the destination so it can be hoisted out of a loop.
14044 // Only do this pre-AVX since vpcmp* is no longer destructive.
14045 if (Subtarget->hasAVX())
14047 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14048 if (ULEOp1.getNode()) {
14050 Subus = true; Invert = false; Swap = false;
14054 // Psubus is better than flip-sign because it requires no inversion.
14055 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14056 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14060 Opc = X86ISD::SUBUS;
14066 std::swap(Op0, Op1);
14068 // Check that the operation in question is available (most are plain SSE2,
14069 // but PCMPGTQ and PCMPEQQ have different requirements).
14070 if (VT == MVT::v2i64) {
14071 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14072 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14074 // First cast everything to the right type.
14075 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14076 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14078 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14079 // bits of the inputs before performing those operations. The lower
14080 // compare is always unsigned.
14083 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14085 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14086 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14087 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14088 Sign, Zero, Sign, Zero);
14090 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14091 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14093 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14094 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14095 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14097 // Create masks for only the low parts/high parts of the 64 bit integers.
14098 static const int MaskHi[] = { 1, 1, 3, 3 };
14099 static const int MaskLo[] = { 0, 0, 2, 2 };
14100 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14101 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14102 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14104 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14105 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14108 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14110 return DAG.getBitcast(VT, Result);
14113 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14114 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14115 // pcmpeqd + pshufd + pand.
14116 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14118 // First cast everything to the right type.
14119 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14120 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14123 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14125 // Make sure the lower and upper halves are both all-ones.
14126 static const int Mask[] = { 1, 0, 3, 2 };
14127 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14128 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14131 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14133 return DAG.getBitcast(VT, Result);
14137 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14138 // bits of the inputs before performing those operations.
14140 EVT EltVT = VT.getVectorElementType();
14141 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14143 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14144 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14147 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14149 // If the logical-not of the result is required, perform that now.
14151 Result = DAG.getNOT(dl, Result, VT);
14154 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14157 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14158 getZeroVector(VT, Subtarget, DAG, dl));
14163 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14165 MVT VT = Op.getSimpleValueType();
14167 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14169 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14170 && "SetCC type must be 8-bit or 1-bit integer");
14171 SDValue Op0 = Op.getOperand(0);
14172 SDValue Op1 = Op.getOperand(1);
14174 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14176 // Optimize to BT if possible.
14177 // Lower (X & (1 << N)) == 0 to BT(X, N).
14178 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14179 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14180 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14181 Op1.getOpcode() == ISD::Constant &&
14182 cast<ConstantSDNode>(Op1)->isNullValue() &&
14183 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14184 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14185 if (NewSetCC.getNode()) {
14187 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14192 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14194 if (Op1.getOpcode() == ISD::Constant &&
14195 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14196 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14197 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14199 // If the input is a setcc, then reuse the input setcc or use a new one with
14200 // the inverted condition.
14201 if (Op0.getOpcode() == X86ISD::SETCC) {
14202 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14203 bool Invert = (CC == ISD::SETNE) ^
14204 cast<ConstantSDNode>(Op1)->isNullValue();
14208 CCode = X86::GetOppositeBranchCondition(CCode);
14209 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14210 DAG.getConstant(CCode, dl, MVT::i8),
14211 Op0.getOperand(1));
14213 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14217 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14218 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14219 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14221 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14222 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14225 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14226 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14227 if (X86CC == X86::COND_INVALID)
14230 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14231 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14232 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14233 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14235 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14239 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14240 static bool isX86LogicalCmp(SDValue Op) {
14241 unsigned Opc = Op.getNode()->getOpcode();
14242 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14243 Opc == X86ISD::SAHF)
14245 if (Op.getResNo() == 1 &&
14246 (Opc == X86ISD::ADD ||
14247 Opc == X86ISD::SUB ||
14248 Opc == X86ISD::ADC ||
14249 Opc == X86ISD::SBB ||
14250 Opc == X86ISD::SMUL ||
14251 Opc == X86ISD::UMUL ||
14252 Opc == X86ISD::INC ||
14253 Opc == X86ISD::DEC ||
14254 Opc == X86ISD::OR ||
14255 Opc == X86ISD::XOR ||
14256 Opc == X86ISD::AND))
14259 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14265 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14266 if (V.getOpcode() != ISD::TRUNCATE)
14269 SDValue VOp0 = V.getOperand(0);
14270 unsigned InBits = VOp0.getValueSizeInBits();
14271 unsigned Bits = V.getValueSizeInBits();
14272 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14275 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14276 bool addTest = true;
14277 SDValue Cond = Op.getOperand(0);
14278 SDValue Op1 = Op.getOperand(1);
14279 SDValue Op2 = Op.getOperand(2);
14281 EVT VT = Op1.getValueType();
14284 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14285 // are available or VBLENDV if AVX is available.
14286 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14287 if (Cond.getOpcode() == ISD::SETCC &&
14288 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14289 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14290 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14291 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14292 int SSECC = translateX86FSETCC(
14293 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14296 if (Subtarget->hasAVX512()) {
14297 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14298 DAG.getConstant(SSECC, DL, MVT::i8));
14299 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14302 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14303 DAG.getConstant(SSECC, DL, MVT::i8));
14305 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14306 // of 3 logic instructions for size savings and potentially speed.
14307 // Unfortunately, there is no scalar form of VBLENDV.
14309 // If either operand is a constant, don't try this. We can expect to
14310 // optimize away at least one of the logic instructions later in that
14311 // case, so that sequence would be faster than a variable blend.
14313 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14314 // uses XMM0 as the selection register. That may need just as many
14315 // instructions as the AND/ANDN/OR sequence due to register moves, so
14318 if (Subtarget->hasAVX() &&
14319 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14321 // Convert to vectors, do a VSELECT, and convert back to scalar.
14322 // All of the conversions should be optimized away.
14324 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14325 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14326 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14327 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14329 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14330 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14332 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14334 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14335 VSel, DAG.getIntPtrConstant(0, DL));
14337 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14338 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14339 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14343 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14345 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14346 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14347 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14348 Op1Scalar = Op1.getOperand(0);
14350 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14351 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14352 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14353 Op2Scalar = Op2.getOperand(0);
14354 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14355 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14356 Op1Scalar.getValueType(),
14357 Cond, Op1Scalar, Op2Scalar);
14358 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14359 return DAG.getBitcast(VT, newSelect);
14360 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14361 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14362 DAG.getIntPtrConstant(0, DL));
14366 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14367 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14368 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14369 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14370 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14371 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14372 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14374 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14377 if (Cond.getOpcode() == ISD::SETCC) {
14378 SDValue NewCond = LowerSETCC(Cond, DAG);
14379 if (NewCond.getNode())
14383 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14384 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14385 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14386 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14387 if (Cond.getOpcode() == X86ISD::SETCC &&
14388 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14389 isZero(Cond.getOperand(1).getOperand(1))) {
14390 SDValue Cmp = Cond.getOperand(1);
14392 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14394 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14395 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14396 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14398 SDValue CmpOp0 = Cmp.getOperand(0);
14399 // Apply further optimizations for special cases
14400 // (select (x != 0), -1, 0) -> neg & sbb
14401 // (select (x == 0), 0, -1) -> neg & sbb
14402 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14403 if (YC->isNullValue() &&
14404 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14405 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14406 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14407 DAG.getConstant(0, DL,
14408 CmpOp0.getValueType()),
14410 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14411 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14412 SDValue(Neg.getNode(), 1));
14416 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14417 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14418 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14420 SDValue Res = // Res = 0 or -1.
14421 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14422 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14424 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14425 Res = DAG.getNOT(DL, Res, Res.getValueType());
14427 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14428 if (!N2C || !N2C->isNullValue())
14429 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14434 // Look past (and (setcc_carry (cmp ...)), 1).
14435 if (Cond.getOpcode() == ISD::AND &&
14436 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14437 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14438 if (C && C->getAPIntValue() == 1)
14439 Cond = Cond.getOperand(0);
14442 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14443 // setting operand in place of the X86ISD::SETCC.
14444 unsigned CondOpcode = Cond.getOpcode();
14445 if (CondOpcode == X86ISD::SETCC ||
14446 CondOpcode == X86ISD::SETCC_CARRY) {
14447 CC = Cond.getOperand(0);
14449 SDValue Cmp = Cond.getOperand(1);
14450 unsigned Opc = Cmp.getOpcode();
14451 MVT VT = Op.getSimpleValueType();
14453 bool IllegalFPCMov = false;
14454 if (VT.isFloatingPoint() && !VT.isVector() &&
14455 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14456 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14458 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14459 Opc == X86ISD::BT) { // FIXME
14463 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14464 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14465 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14466 Cond.getOperand(0).getValueType() != MVT::i8)) {
14467 SDValue LHS = Cond.getOperand(0);
14468 SDValue RHS = Cond.getOperand(1);
14469 unsigned X86Opcode;
14472 switch (CondOpcode) {
14473 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14474 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14475 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14476 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14477 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14478 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14479 default: llvm_unreachable("unexpected overflowing operator");
14481 if (CondOpcode == ISD::UMULO)
14482 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14485 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14487 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14489 if (CondOpcode == ISD::UMULO)
14490 Cond = X86Op.getValue(2);
14492 Cond = X86Op.getValue(1);
14494 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14499 // Look past the truncate if the high bits are known zero.
14500 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14501 Cond = Cond.getOperand(0);
14503 // We know the result of AND is compared against zero. Try to match
14505 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14506 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14507 if (NewSetCC.getNode()) {
14508 CC = NewSetCC.getOperand(0);
14509 Cond = NewSetCC.getOperand(1);
14516 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14517 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14520 // a < b ? -1 : 0 -> RES = ~setcc_carry
14521 // a < b ? 0 : -1 -> RES = setcc_carry
14522 // a >= b ? -1 : 0 -> RES = setcc_carry
14523 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14524 if (Cond.getOpcode() == X86ISD::SUB) {
14525 Cond = ConvertCmpIfNecessary(Cond, DAG);
14526 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14528 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14529 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14530 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14531 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14533 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14534 return DAG.getNOT(DL, Res, Res.getValueType());
14539 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14540 // widen the cmov and push the truncate through. This avoids introducing a new
14541 // branch during isel and doesn't add any extensions.
14542 if (Op.getValueType() == MVT::i8 &&
14543 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14544 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14545 if (T1.getValueType() == T2.getValueType() &&
14546 // Blacklist CopyFromReg to avoid partial register stalls.
14547 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14548 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14549 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14550 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14554 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14555 // condition is true.
14556 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14557 SDValue Ops[] = { Op2, Op1, CC, Cond };
14558 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14561 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14562 const X86Subtarget *Subtarget,
14563 SelectionDAG &DAG) {
14564 MVT VT = Op->getSimpleValueType(0);
14565 SDValue In = Op->getOperand(0);
14566 MVT InVT = In.getSimpleValueType();
14567 MVT VTElt = VT.getVectorElementType();
14568 MVT InVTElt = InVT.getVectorElementType();
14572 if ((InVTElt == MVT::i1) &&
14573 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14574 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14576 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14577 VTElt.getSizeInBits() <= 16)) ||
14579 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14580 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14582 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14583 VTElt.getSizeInBits() >= 32))))
14584 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14586 unsigned int NumElts = VT.getVectorNumElements();
14588 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14591 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14592 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14593 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14594 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14597 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14598 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14600 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14603 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14605 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14606 if (VT.is512BitVector())
14608 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14611 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14612 const X86Subtarget *Subtarget,
14613 SelectionDAG &DAG) {
14614 SDValue In = Op->getOperand(0);
14615 MVT VT = Op->getSimpleValueType(0);
14616 MVT InVT = In.getSimpleValueType();
14617 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14619 MVT InSVT = InVT.getScalarType();
14620 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14622 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14624 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14629 // SSE41 targets can use the pmovsx* instructions directly.
14630 if (Subtarget->hasSSE41())
14631 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14633 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14637 // As SRAI is only available on i16/i32 types, we expand only up to i32
14638 // and handle i64 separately.
14639 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14640 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14641 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14642 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14643 Curr = DAG.getBitcast(CurrVT, Curr);
14646 SDValue SignExt = Curr;
14647 if (CurrVT != InVT) {
14648 unsigned SignExtShift =
14649 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14650 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14651 DAG.getConstant(SignExtShift, dl, MVT::i8));
14657 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14658 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14659 DAG.getConstant(31, dl, MVT::i8));
14660 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14661 return DAG.getBitcast(VT, Ext);
14667 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14668 SelectionDAG &DAG) {
14669 MVT VT = Op->getSimpleValueType(0);
14670 SDValue In = Op->getOperand(0);
14671 MVT InVT = In.getSimpleValueType();
14674 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14675 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14677 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14678 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14679 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14682 if (Subtarget->hasInt256())
14683 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14685 // Optimize vectors in AVX mode
14686 // Sign extend v8i16 to v8i32 and
14689 // Divide input vector into two parts
14690 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14691 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14692 // concat the vectors to original VT
14694 unsigned NumElems = InVT.getVectorNumElements();
14695 SDValue Undef = DAG.getUNDEF(InVT);
14697 SmallVector<int,8> ShufMask1(NumElems, -1);
14698 for (unsigned i = 0; i != NumElems/2; ++i)
14701 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14703 SmallVector<int,8> ShufMask2(NumElems, -1);
14704 for (unsigned i = 0; i != NumElems/2; ++i)
14705 ShufMask2[i] = i + NumElems/2;
14707 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14709 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14710 VT.getVectorNumElements()/2);
14712 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14713 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14715 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14718 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14719 // may emit an illegal shuffle but the expansion is still better than scalar
14720 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14721 // we'll emit a shuffle and a arithmetic shift.
14722 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14723 // TODO: It is possible to support ZExt by zeroing the undef values during
14724 // the shuffle phase or after the shuffle.
14725 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14726 SelectionDAG &DAG) {
14727 MVT RegVT = Op.getSimpleValueType();
14728 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14729 assert(RegVT.isInteger() &&
14730 "We only custom lower integer vector sext loads.");
14732 // Nothing useful we can do without SSE2 shuffles.
14733 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14735 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14737 EVT MemVT = Ld->getMemoryVT();
14738 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14739 unsigned RegSz = RegVT.getSizeInBits();
14741 ISD::LoadExtType Ext = Ld->getExtensionType();
14743 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14744 && "Only anyext and sext are currently implemented.");
14745 assert(MemVT != RegVT && "Cannot extend to the same type");
14746 assert(MemVT.isVector() && "Must load a vector from memory");
14748 unsigned NumElems = RegVT.getVectorNumElements();
14749 unsigned MemSz = MemVT.getSizeInBits();
14750 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14752 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14753 // The only way in which we have a legal 256-bit vector result but not the
14754 // integer 256-bit operations needed to directly lower a sextload is if we
14755 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14756 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14757 // correctly legalized. We do this late to allow the canonical form of
14758 // sextload to persist throughout the rest of the DAG combiner -- it wants
14759 // to fold together any extensions it can, and so will fuse a sign_extend
14760 // of an sextload into a sextload targeting a wider value.
14762 if (MemSz == 128) {
14763 // Just switch this to a normal load.
14764 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14765 "it must be a legal 128-bit vector "
14767 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14768 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14769 Ld->isInvariant(), Ld->getAlignment());
14771 assert(MemSz < 128 &&
14772 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14773 // Do an sext load to a 128-bit vector type. We want to use the same
14774 // number of elements, but elements half as wide. This will end up being
14775 // recursively lowered by this routine, but will succeed as we definitely
14776 // have all the necessary features if we're using AVX1.
14778 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14779 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14781 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14782 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14783 Ld->isNonTemporal(), Ld->isInvariant(),
14784 Ld->getAlignment());
14787 // Replace chain users with the new chain.
14788 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14789 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14791 // Finally, do a normal sign-extend to the desired register.
14792 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14795 // All sizes must be a power of two.
14796 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14797 "Non-power-of-two elements are not custom lowered!");
14799 // Attempt to load the original value using scalar loads.
14800 // Find the largest scalar type that divides the total loaded size.
14801 MVT SclrLoadTy = MVT::i8;
14802 for (MVT Tp : MVT::integer_valuetypes()) {
14803 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14808 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14809 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14811 SclrLoadTy = MVT::f64;
14813 // Calculate the number of scalar loads that we need to perform
14814 // in order to load our vector from memory.
14815 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14817 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14818 "Can only lower sext loads with a single scalar load!");
14820 unsigned loadRegZize = RegSz;
14821 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14824 // Represent our vector as a sequence of elements which are the
14825 // largest scalar that we can load.
14826 EVT LoadUnitVecVT = EVT::getVectorVT(
14827 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14829 // Represent the data using the same element type that is stored in
14830 // memory. In practice, we ''widen'' MemVT.
14832 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14833 loadRegZize / MemVT.getScalarType().getSizeInBits());
14835 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14836 "Invalid vector type");
14838 // We can't shuffle using an illegal type.
14839 assert(TLI.isTypeLegal(WideVecVT) &&
14840 "We only lower types that form legal widened vector types");
14842 SmallVector<SDValue, 8> Chains;
14843 SDValue Ptr = Ld->getBasePtr();
14844 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
14845 TLI.getPointerTy(DAG.getDataLayout()));
14846 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14848 for (unsigned i = 0; i < NumLoads; ++i) {
14849 // Perform a single load.
14850 SDValue ScalarLoad =
14851 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14852 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14853 Ld->getAlignment());
14854 Chains.push_back(ScalarLoad.getValue(1));
14855 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14856 // another round of DAGCombining.
14858 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14860 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14861 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14863 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14866 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14868 // Bitcast the loaded value to a vector of the original element type, in
14869 // the size of the target vector type.
14870 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14871 unsigned SizeRatio = RegSz / MemSz;
14873 if (Ext == ISD::SEXTLOAD) {
14874 // If we have SSE4.1, we can directly emit a VSEXT node.
14875 if (Subtarget->hasSSE41()) {
14876 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14877 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14881 // Otherwise we'll shuffle the small elements in the high bits of the
14882 // larger type and perform an arithmetic shift. If the shift is not legal
14883 // it's better to scalarize.
14884 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14885 "We can't implement a sext load without an arithmetic right shift!");
14887 // Redistribute the loaded elements into the different locations.
14888 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14889 for (unsigned i = 0; i != NumElems; ++i)
14890 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14892 SDValue Shuff = DAG.getVectorShuffle(
14893 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14895 Shuff = DAG.getBitcast(RegVT, Shuff);
14897 // Build the arithmetic shift.
14898 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14899 MemVT.getVectorElementType().getSizeInBits();
14901 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14902 DAG.getConstant(Amt, dl, RegVT));
14904 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14908 // Redistribute the loaded elements into the different locations.
14909 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14910 for (unsigned i = 0; i != NumElems; ++i)
14911 ShuffleVec[i * SizeRatio] = i;
14913 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14914 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14916 // Bitcast to the requested type.
14917 Shuff = DAG.getBitcast(RegVT, Shuff);
14918 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14922 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14923 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14924 // from the AND / OR.
14925 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14926 Opc = Op.getOpcode();
14927 if (Opc != ISD::OR && Opc != ISD::AND)
14929 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14930 Op.getOperand(0).hasOneUse() &&
14931 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14932 Op.getOperand(1).hasOneUse());
14935 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14936 // 1 and that the SETCC node has a single use.
14937 static bool isXor1OfSetCC(SDValue Op) {
14938 if (Op.getOpcode() != ISD::XOR)
14940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14941 if (N1C && N1C->getAPIntValue() == 1) {
14942 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14943 Op.getOperand(0).hasOneUse();
14948 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14949 bool addTest = true;
14950 SDValue Chain = Op.getOperand(0);
14951 SDValue Cond = Op.getOperand(1);
14952 SDValue Dest = Op.getOperand(2);
14955 bool Inverted = false;
14957 if (Cond.getOpcode() == ISD::SETCC) {
14958 // Check for setcc([su]{add,sub,mul}o == 0).
14959 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14960 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14961 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14962 Cond.getOperand(0).getResNo() == 1 &&
14963 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14964 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14965 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14966 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14967 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14968 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14970 Cond = Cond.getOperand(0);
14972 SDValue NewCond = LowerSETCC(Cond, DAG);
14973 if (NewCond.getNode())
14978 // FIXME: LowerXALUO doesn't handle these!!
14979 else if (Cond.getOpcode() == X86ISD::ADD ||
14980 Cond.getOpcode() == X86ISD::SUB ||
14981 Cond.getOpcode() == X86ISD::SMUL ||
14982 Cond.getOpcode() == X86ISD::UMUL)
14983 Cond = LowerXALUO(Cond, DAG);
14986 // Look pass (and (setcc_carry (cmp ...)), 1).
14987 if (Cond.getOpcode() == ISD::AND &&
14988 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14989 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14990 if (C && C->getAPIntValue() == 1)
14991 Cond = Cond.getOperand(0);
14994 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14995 // setting operand in place of the X86ISD::SETCC.
14996 unsigned CondOpcode = Cond.getOpcode();
14997 if (CondOpcode == X86ISD::SETCC ||
14998 CondOpcode == X86ISD::SETCC_CARRY) {
14999 CC = Cond.getOperand(0);
15001 SDValue Cmp = Cond.getOperand(1);
15002 unsigned Opc = Cmp.getOpcode();
15003 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15004 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15008 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15012 // These can only come from an arithmetic instruction with overflow,
15013 // e.g. SADDO, UADDO.
15014 Cond = Cond.getNode()->getOperand(1);
15020 CondOpcode = Cond.getOpcode();
15021 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15022 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15023 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15024 Cond.getOperand(0).getValueType() != MVT::i8)) {
15025 SDValue LHS = Cond.getOperand(0);
15026 SDValue RHS = Cond.getOperand(1);
15027 unsigned X86Opcode;
15030 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15031 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15033 switch (CondOpcode) {
15034 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15038 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15041 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15042 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15046 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15049 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15050 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15051 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15052 default: llvm_unreachable("unexpected overflowing operator");
15055 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15056 if (CondOpcode == ISD::UMULO)
15057 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15060 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15062 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15064 if (CondOpcode == ISD::UMULO)
15065 Cond = X86Op.getValue(2);
15067 Cond = X86Op.getValue(1);
15069 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15073 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15074 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15075 if (CondOpc == ISD::OR) {
15076 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15077 // two branches instead of an explicit OR instruction with a
15079 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15080 isX86LogicalCmp(Cmp)) {
15081 CC = Cond.getOperand(0).getOperand(0);
15082 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15083 Chain, Dest, CC, Cmp);
15084 CC = Cond.getOperand(1).getOperand(0);
15088 } else { // ISD::AND
15089 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15090 // two branches instead of an explicit AND instruction with a
15091 // separate test. However, we only do this if this block doesn't
15092 // have a fall-through edge, because this requires an explicit
15093 // jmp when the condition is false.
15094 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15095 isX86LogicalCmp(Cmp) &&
15096 Op.getNode()->hasOneUse()) {
15097 X86::CondCode CCode =
15098 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15099 CCode = X86::GetOppositeBranchCondition(CCode);
15100 CC = DAG.getConstant(CCode, dl, MVT::i8);
15101 SDNode *User = *Op.getNode()->use_begin();
15102 // Look for an unconditional branch following this conditional branch.
15103 // We need this because we need to reverse the successors in order
15104 // to implement FCMP_OEQ.
15105 if (User->getOpcode() == ISD::BR) {
15106 SDValue FalseBB = User->getOperand(1);
15108 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15109 assert(NewBR == User);
15113 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15114 Chain, Dest, CC, Cmp);
15115 X86::CondCode CCode =
15116 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15117 CCode = X86::GetOppositeBranchCondition(CCode);
15118 CC = DAG.getConstant(CCode, dl, MVT::i8);
15124 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15125 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15126 // It should be transformed during dag combiner except when the condition
15127 // is set by a arithmetics with overflow node.
15128 X86::CondCode CCode =
15129 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15130 CCode = X86::GetOppositeBranchCondition(CCode);
15131 CC = DAG.getConstant(CCode, dl, MVT::i8);
15132 Cond = Cond.getOperand(0).getOperand(1);
15134 } else if (Cond.getOpcode() == ISD::SETCC &&
15135 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15136 // For FCMP_OEQ, we can emit
15137 // two branches instead of an explicit AND instruction with a
15138 // separate test. However, we only do this if this block doesn't
15139 // have a fall-through edge, because this requires an explicit
15140 // jmp when the condition is false.
15141 if (Op.getNode()->hasOneUse()) {
15142 SDNode *User = *Op.getNode()->use_begin();
15143 // Look for an unconditional branch following this conditional branch.
15144 // We need this because we need to reverse the successors in order
15145 // to implement FCMP_OEQ.
15146 if (User->getOpcode() == ISD::BR) {
15147 SDValue FalseBB = User->getOperand(1);
15149 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15150 assert(NewBR == User);
15154 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15155 Cond.getOperand(0), Cond.getOperand(1));
15156 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15157 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15158 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15159 Chain, Dest, CC, Cmp);
15160 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15165 } else if (Cond.getOpcode() == ISD::SETCC &&
15166 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15167 // For FCMP_UNE, we can emit
15168 // two branches instead of an explicit AND instruction with a
15169 // separate test. However, we only do this if this block doesn't
15170 // have a fall-through edge, because this requires an explicit
15171 // jmp when the condition is false.
15172 if (Op.getNode()->hasOneUse()) {
15173 SDNode *User = *Op.getNode()->use_begin();
15174 // Look for an unconditional branch following this conditional branch.
15175 // We need this because we need to reverse the successors in order
15176 // to implement FCMP_UNE.
15177 if (User->getOpcode() == ISD::BR) {
15178 SDValue FalseBB = User->getOperand(1);
15180 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15181 assert(NewBR == User);
15184 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15185 Cond.getOperand(0), Cond.getOperand(1));
15186 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15187 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15188 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15189 Chain, Dest, CC, Cmp);
15190 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15200 // Look pass the truncate if the high bits are known zero.
15201 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15202 Cond = Cond.getOperand(0);
15204 // We know the result of AND is compared against zero. Try to match
15206 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15207 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15208 if (NewSetCC.getNode()) {
15209 CC = NewSetCC.getOperand(0);
15210 Cond = NewSetCC.getOperand(1);
15217 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15218 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15219 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15221 Cond = ConvertCmpIfNecessary(Cond, DAG);
15222 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15223 Chain, Dest, CC, Cond);
15226 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15227 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15228 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15229 // that the guard pages used by the OS virtual memory manager are allocated in
15230 // correct sequence.
15232 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15233 SelectionDAG &DAG) const {
15234 MachineFunction &MF = DAG.getMachineFunction();
15235 bool SplitStack = MF.shouldSplitStack();
15236 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15241 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15242 SDNode* Node = Op.getNode();
15244 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15245 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15246 " not tell us which reg is the stack pointer!");
15247 EVT VT = Node->getValueType(0);
15248 SDValue Tmp1 = SDValue(Node, 0);
15249 SDValue Tmp2 = SDValue(Node, 1);
15250 SDValue Tmp3 = Node->getOperand(2);
15251 SDValue Chain = Tmp1.getOperand(0);
15253 // Chain the dynamic stack allocation so that it doesn't modify the stack
15254 // pointer when other instructions are using the stack.
15255 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15258 SDValue Size = Tmp2.getOperand(1);
15259 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15260 Chain = SP.getValue(1);
15261 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15262 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15263 unsigned StackAlign = TFI.getStackAlignment();
15264 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15265 if (Align > StackAlign)
15266 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15267 DAG.getConstant(-(uint64_t)Align, dl, VT));
15268 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15270 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15271 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15274 SDValue Ops[2] = { Tmp1, Tmp2 };
15275 return DAG.getMergeValues(Ops, dl);
15279 SDValue Chain = Op.getOperand(0);
15280 SDValue Size = Op.getOperand(1);
15281 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15282 EVT VT = Op.getNode()->getValueType(0);
15284 bool Is64Bit = Subtarget->is64Bit();
15285 MVT SPTy = getPointerTy(DAG.getDataLayout());
15288 MachineRegisterInfo &MRI = MF.getRegInfo();
15291 // The 64 bit implementation of segmented stacks needs to clobber both r10
15292 // r11. This makes it impossible to use it along with nested parameters.
15293 const Function *F = MF.getFunction();
15295 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15297 if (I->hasNestAttr())
15298 report_fatal_error("Cannot use segmented stacks with functions that "
15299 "have nested arguments.");
15302 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15303 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15304 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15305 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15306 DAG.getRegister(Vreg, SPTy));
15307 SDValue Ops1[2] = { Value, Chain };
15308 return DAG.getMergeValues(Ops1, dl);
15311 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15313 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15314 Flag = Chain.getValue(1);
15315 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15317 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15319 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15320 unsigned SPReg = RegInfo->getStackRegister();
15321 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15322 Chain = SP.getValue(1);
15325 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15326 DAG.getConstant(-(uint64_t)Align, dl, VT));
15327 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15330 SDValue Ops1[2] = { SP, Chain };
15331 return DAG.getMergeValues(Ops1, dl);
15335 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15336 MachineFunction &MF = DAG.getMachineFunction();
15337 auto PtrVT = getPointerTy(MF.getDataLayout());
15338 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15340 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15343 if (!Subtarget->is64Bit() ||
15344 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15345 // vastart just stores the address of the VarArgsFrameIndex slot into the
15346 // memory location argument.
15347 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15348 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15349 MachinePointerInfo(SV), false, false, 0);
15353 // gp_offset (0 - 6 * 8)
15354 // fp_offset (48 - 48 + 8 * 16)
15355 // overflow_arg_area (point to parameters coming in memory).
15357 SmallVector<SDValue, 8> MemOps;
15358 SDValue FIN = Op.getOperand(1);
15360 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15361 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15363 FIN, MachinePointerInfo(SV), false, false, 0);
15364 MemOps.push_back(Store);
15367 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15368 Store = DAG.getStore(Op.getOperand(0), DL,
15369 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15371 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15372 MemOps.push_back(Store);
15374 // Store ptr to overflow_arg_area
15375 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15376 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15377 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15378 MachinePointerInfo(SV, 8),
15380 MemOps.push_back(Store);
15382 // Store ptr to reg_save_area.
15383 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15384 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15385 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15386 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15387 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15388 MemOps.push_back(Store);
15389 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15392 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15393 assert(Subtarget->is64Bit() &&
15394 "LowerVAARG only handles 64-bit va_arg!");
15395 assert(Op.getNode()->getNumOperands() == 4);
15397 MachineFunction &MF = DAG.getMachineFunction();
15398 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15399 // The Win64 ABI uses char* instead of a structure.
15400 return DAG.expandVAArg(Op.getNode());
15402 SDValue Chain = Op.getOperand(0);
15403 SDValue SrcPtr = Op.getOperand(1);
15404 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15405 unsigned Align = Op.getConstantOperandVal(3);
15408 EVT ArgVT = Op.getNode()->getValueType(0);
15409 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15410 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15413 // Decide which area this value should be read from.
15414 // TODO: Implement the AMD64 ABI in its entirety. This simple
15415 // selection mechanism works only for the basic types.
15416 if (ArgVT == MVT::f80) {
15417 llvm_unreachable("va_arg for f80 not yet implemented");
15418 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15419 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15420 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15421 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15423 llvm_unreachable("Unhandled argument type in LowerVAARG");
15426 if (ArgMode == 2) {
15427 // Sanity Check: Make sure using fp_offset makes sense.
15428 assert(!Subtarget->useSoftFloat() &&
15429 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15430 Subtarget->hasSSE1());
15433 // Insert VAARG_64 node into the DAG
15434 // VAARG_64 returns two values: Variable Argument Address, Chain
15435 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15436 DAG.getConstant(ArgMode, dl, MVT::i8),
15437 DAG.getConstant(Align, dl, MVT::i32)};
15438 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15439 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15440 VTs, InstOps, MVT::i64,
15441 MachinePointerInfo(SV),
15443 /*Volatile=*/false,
15445 /*WriteMem=*/true);
15446 Chain = VAARG.getValue(1);
15448 // Load the next argument and return it
15449 return DAG.getLoad(ArgVT, dl,
15452 MachinePointerInfo(),
15453 false, false, false, 0);
15456 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15457 SelectionDAG &DAG) {
15458 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15459 // where a va_list is still an i8*.
15460 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15461 if (Subtarget->isCallingConvWin64(
15462 DAG.getMachineFunction().getFunction()->getCallingConv()))
15463 // Probably a Win64 va_copy.
15464 return DAG.expandVACopy(Op.getNode());
15466 SDValue Chain = Op.getOperand(0);
15467 SDValue DstPtr = Op.getOperand(1);
15468 SDValue SrcPtr = Op.getOperand(2);
15469 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15470 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15473 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15474 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15476 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15479 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15480 // amount is a constant. Takes immediate version of shift as input.
15481 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15482 SDValue SrcOp, uint64_t ShiftAmt,
15483 SelectionDAG &DAG) {
15484 MVT ElementType = VT.getVectorElementType();
15486 // Fold this packed shift into its first operand if ShiftAmt is 0.
15490 // Check for ShiftAmt >= element width
15491 if (ShiftAmt >= ElementType.getSizeInBits()) {
15492 if (Opc == X86ISD::VSRAI)
15493 ShiftAmt = ElementType.getSizeInBits() - 1;
15495 return DAG.getConstant(0, dl, VT);
15498 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15499 && "Unknown target vector shift-by-constant node");
15501 // Fold this packed vector shift into a build vector if SrcOp is a
15502 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15503 if (VT == SrcOp.getSimpleValueType() &&
15504 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15505 SmallVector<SDValue, 8> Elts;
15506 unsigned NumElts = SrcOp->getNumOperands();
15507 ConstantSDNode *ND;
15510 default: llvm_unreachable(nullptr);
15511 case X86ISD::VSHLI:
15512 for (unsigned i=0; i!=NumElts; ++i) {
15513 SDValue CurrentOp = SrcOp->getOperand(i);
15514 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15515 Elts.push_back(CurrentOp);
15518 ND = cast<ConstantSDNode>(CurrentOp);
15519 const APInt &C = ND->getAPIntValue();
15520 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15523 case X86ISD::VSRLI:
15524 for (unsigned i=0; i!=NumElts; ++i) {
15525 SDValue CurrentOp = SrcOp->getOperand(i);
15526 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15527 Elts.push_back(CurrentOp);
15530 ND = cast<ConstantSDNode>(CurrentOp);
15531 const APInt &C = ND->getAPIntValue();
15532 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15535 case X86ISD::VSRAI:
15536 for (unsigned i=0; i!=NumElts; ++i) {
15537 SDValue CurrentOp = SrcOp->getOperand(i);
15538 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15539 Elts.push_back(CurrentOp);
15542 ND = cast<ConstantSDNode>(CurrentOp);
15543 const APInt &C = ND->getAPIntValue();
15544 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15549 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15552 return DAG.getNode(Opc, dl, VT, SrcOp,
15553 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15556 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15557 // may or may not be a constant. Takes immediate version of shift as input.
15558 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15559 SDValue SrcOp, SDValue ShAmt,
15560 SelectionDAG &DAG) {
15561 MVT SVT = ShAmt.getSimpleValueType();
15562 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15564 // Catch shift-by-constant.
15565 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15566 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15567 CShAmt->getZExtValue(), DAG);
15569 // Change opcode to non-immediate version
15571 default: llvm_unreachable("Unknown target vector shift node");
15572 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15573 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15574 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15577 const X86Subtarget &Subtarget =
15578 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15579 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15580 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15581 // Let the shuffle legalizer expand this shift amount node.
15582 SDValue Op0 = ShAmt.getOperand(0);
15583 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15584 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15586 // Need to build a vector containing shift amount.
15587 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15588 SmallVector<SDValue, 4> ShOps;
15589 ShOps.push_back(ShAmt);
15590 if (SVT == MVT::i32) {
15591 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15592 ShOps.push_back(DAG.getUNDEF(SVT));
15594 ShOps.push_back(DAG.getUNDEF(SVT));
15596 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15597 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15600 // The return type has to be a 128-bit type with the same element
15601 // type as the input type.
15602 MVT EltVT = VT.getVectorElementType();
15603 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15605 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15606 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15609 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15610 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15611 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15612 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15613 SDValue PreservedSrc,
15614 const X86Subtarget *Subtarget,
15615 SelectionDAG &DAG) {
15616 EVT VT = Op.getValueType();
15617 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15618 MVT::i1, VT.getVectorNumElements());
15619 SDValue VMask = SDValue();
15620 unsigned OpcodeSelect = ISD::VSELECT;
15623 assert(MaskVT.isSimple() && "invalid mask type");
15625 if (isAllOnes(Mask))
15628 if (MaskVT.bitsGT(Mask.getValueType())) {
15629 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15630 MaskVT.getSizeInBits());
15631 VMask = DAG.getBitcast(MaskVT,
15632 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15634 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15635 Mask.getValueType().getSizeInBits());
15636 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15637 // are extracted by EXTRACT_SUBVECTOR.
15638 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15639 DAG.getBitcast(BitcastVT, Mask),
15640 DAG.getIntPtrConstant(0, dl));
15643 switch (Op.getOpcode()) {
15645 case X86ISD::PCMPEQM:
15646 case X86ISD::PCMPGTM:
15648 case X86ISD::CMPMU:
15649 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15650 case X86ISD::VTRUNC:
15651 case X86ISD::VTRUNCS:
15652 case X86ISD::VTRUNCUS:
15653 // We can't use ISD::VSELECT here because it is not always "Legal"
15654 // for the destination type. For example vpmovqb require only AVX512
15655 // and vselect that can operate on byte element type require BWI
15656 OpcodeSelect = X86ISD::SELECT;
15659 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15660 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15661 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15664 /// \brief Creates an SDNode for a predicated scalar operation.
15665 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15666 /// The mask is coming as MVT::i8 and it should be truncated
15667 /// to MVT::i1 while lowering masking intrinsics.
15668 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15669 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15670 /// for a scalar instruction.
15671 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15672 SDValue PreservedSrc,
15673 const X86Subtarget *Subtarget,
15674 SelectionDAG &DAG) {
15675 if (isAllOnes(Mask))
15678 EVT VT = Op.getValueType();
15680 // The mask should be of type MVT::i1
15681 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15683 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15684 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15685 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15688 static int getSEHRegistrationNodeSize(const Function *Fn) {
15689 if (!Fn->hasPersonalityFn())
15690 report_fatal_error(
15691 "querying registration node size for function without personality");
15692 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15693 // WinEHStatePass for the full struct definition.
15694 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15695 case EHPersonality::MSVC_X86SEH: return 24;
15696 case EHPersonality::MSVC_CXX: return 16;
15699 report_fatal_error("can only recover FP for MSVC EH personality functions");
15702 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15703 /// function or when returning to a parent frame after catching an exception, we
15704 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15705 /// Here's the math:
15706 /// RegNodeBase = EntryEBP - RegNodeSize
15707 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15708 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15709 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15710 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15711 SDValue EntryEBP) {
15712 MachineFunction &MF = DAG.getMachineFunction();
15715 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15716 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15718 // It's possible that the parent function no longer has a personality function
15719 // if the exceptional code was optimized away, in which case we just return
15720 // the incoming EBP.
15721 if (!Fn->hasPersonalityFn())
15724 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15726 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15728 MCSymbol *OffsetSym =
15729 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15730 GlobalValue::getRealLinkageName(Fn->getName()));
15731 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15732 SDValue RegNodeFrameOffset =
15733 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15735 // RegNodeBase = EntryEBP - RegNodeSize
15736 // ParentFP = RegNodeBase - RegNodeFrameOffset
15737 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15738 DAG.getConstant(RegNodeSize, dl, PtrVT));
15739 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15742 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15743 SelectionDAG &DAG) {
15745 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15746 EVT VT = Op.getValueType();
15747 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15749 switch(IntrData->Type) {
15750 case INTR_TYPE_1OP:
15751 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15752 case INTR_TYPE_2OP:
15753 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15755 case INTR_TYPE_2OP_IMM8:
15756 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15757 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15758 case INTR_TYPE_3OP:
15759 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15760 Op.getOperand(2), Op.getOperand(3));
15761 case INTR_TYPE_4OP:
15762 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15763 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15764 case INTR_TYPE_1OP_MASK_RM: {
15765 SDValue Src = Op.getOperand(1);
15766 SDValue PassThru = Op.getOperand(2);
15767 SDValue Mask = Op.getOperand(3);
15768 SDValue RoundingMode;
15769 // We allways add rounding mode to the Node.
15770 // If the rounding mode is not specified, we add the
15771 // "current direction" mode.
15772 if (Op.getNumOperands() == 4)
15774 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15776 RoundingMode = Op.getOperand(4);
15777 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15778 if (IntrWithRoundingModeOpcode != 0)
15779 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15780 X86::STATIC_ROUNDING::CUR_DIRECTION)
15781 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15782 dl, Op.getValueType(), Src, RoundingMode),
15783 Mask, PassThru, Subtarget, DAG);
15784 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15786 Mask, PassThru, Subtarget, DAG);
15788 case INTR_TYPE_1OP_MASK: {
15789 SDValue Src = Op.getOperand(1);
15790 SDValue PassThru = Op.getOperand(2);
15791 SDValue Mask = Op.getOperand(3);
15792 // We add rounding mode to the Node when
15793 // - RM Opcode is specified and
15794 // - RM is not "current direction".
15795 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15796 if (IntrWithRoundingModeOpcode != 0) {
15797 SDValue Rnd = Op.getOperand(4);
15798 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15799 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15800 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15801 dl, Op.getValueType(),
15803 Mask, PassThru, Subtarget, DAG);
15806 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15807 Mask, PassThru, Subtarget, DAG);
15809 case INTR_TYPE_SCALAR_MASK_RM: {
15810 SDValue Src1 = Op.getOperand(1);
15811 SDValue Src2 = Op.getOperand(2);
15812 SDValue Src0 = Op.getOperand(3);
15813 SDValue Mask = Op.getOperand(4);
15814 // There are 2 kinds of intrinsics in this group:
15815 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
15816 // (2) With rounding mode and sae - 7 operands.
15817 if (Op.getNumOperands() == 6) {
15818 SDValue Sae = Op.getOperand(5);
15819 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15820 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15822 Mask, Src0, Subtarget, DAG);
15824 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15825 SDValue RoundingMode = Op.getOperand(5);
15826 SDValue Sae = Op.getOperand(6);
15827 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15828 RoundingMode, Sae),
15829 Mask, Src0, Subtarget, DAG);
15831 case INTR_TYPE_2OP_MASK: {
15832 SDValue Src1 = Op.getOperand(1);
15833 SDValue Src2 = Op.getOperand(2);
15834 SDValue PassThru = Op.getOperand(3);
15835 SDValue Mask = Op.getOperand(4);
15836 // We specify 2 possible opcodes for intrinsics with rounding modes.
15837 // First, we check if the intrinsic may have non-default rounding mode,
15838 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15839 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15840 if (IntrWithRoundingModeOpcode != 0) {
15841 SDValue Rnd = Op.getOperand(5);
15842 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15843 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15844 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15845 dl, Op.getValueType(),
15847 Mask, PassThru, Subtarget, DAG);
15850 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15852 Mask, PassThru, Subtarget, DAG);
15854 case INTR_TYPE_2OP_MASK_RM: {
15855 SDValue Src1 = Op.getOperand(1);
15856 SDValue Src2 = Op.getOperand(2);
15857 SDValue PassThru = Op.getOperand(3);
15858 SDValue Mask = Op.getOperand(4);
15859 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15860 // First, we check if the intrinsic have rounding mode (6 operands),
15861 // if not, we set rounding mode to "current".
15863 if (Op.getNumOperands() == 6)
15864 Rnd = Op.getOperand(5);
15866 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15867 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15869 Mask, PassThru, Subtarget, DAG);
15871 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
15872 SDValue Src1 = Op.getOperand(1);
15873 SDValue Src2 = Op.getOperand(2);
15874 SDValue Src3 = Op.getOperand(3);
15875 SDValue PassThru = Op.getOperand(4);
15876 SDValue Mask = Op.getOperand(5);
15877 SDValue Sae = Op.getOperand(6);
15879 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
15881 Mask, PassThru, Subtarget, DAG);
15883 case INTR_TYPE_3OP_MASK_RM: {
15884 SDValue Src1 = Op.getOperand(1);
15885 SDValue Src2 = Op.getOperand(2);
15886 SDValue Imm = Op.getOperand(3);
15887 SDValue PassThru = Op.getOperand(4);
15888 SDValue Mask = Op.getOperand(5);
15889 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15890 // First, we check if the intrinsic have rounding mode (7 operands),
15891 // if not, we set rounding mode to "current".
15893 if (Op.getNumOperands() == 7)
15894 Rnd = Op.getOperand(6);
15896 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15897 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15898 Src1, Src2, Imm, Rnd),
15899 Mask, PassThru, Subtarget, DAG);
15901 case INTR_TYPE_3OP_IMM8_MASK:
15902 case INTR_TYPE_3OP_MASK: {
15903 SDValue Src1 = Op.getOperand(1);
15904 SDValue Src2 = Op.getOperand(2);
15905 SDValue Src3 = Op.getOperand(3);
15906 SDValue PassThru = Op.getOperand(4);
15907 SDValue Mask = Op.getOperand(5);
15909 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
15910 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
15911 // We specify 2 possible opcodes for intrinsics with rounding modes.
15912 // First, we check if the intrinsic may have non-default rounding mode,
15913 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15914 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15915 if (IntrWithRoundingModeOpcode != 0) {
15916 SDValue Rnd = Op.getOperand(6);
15917 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15918 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15919 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15920 dl, Op.getValueType(),
15921 Src1, Src2, Src3, Rnd),
15922 Mask, PassThru, Subtarget, DAG);
15925 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15927 Mask, PassThru, Subtarget, DAG);
15929 case VPERM_3OP_MASKZ:
15930 case VPERM_3OP_MASK:
15933 case FMA_OP_MASK: {
15934 SDValue Src1 = Op.getOperand(1);
15935 SDValue Src2 = Op.getOperand(2);
15936 SDValue Src3 = Op.getOperand(3);
15937 SDValue Mask = Op.getOperand(4);
15938 EVT VT = Op.getValueType();
15939 SDValue PassThru = SDValue();
15941 // set PassThru element
15942 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15943 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15944 else if (IntrData->Type == FMA_OP_MASK3)
15949 // We specify 2 possible opcodes for intrinsics with rounding modes.
15950 // First, we check if the intrinsic may have non-default rounding mode,
15951 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15952 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15953 if (IntrWithRoundingModeOpcode != 0) {
15954 SDValue Rnd = Op.getOperand(5);
15955 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15956 X86::STATIC_ROUNDING::CUR_DIRECTION)
15957 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15958 dl, Op.getValueType(),
15959 Src1, Src2, Src3, Rnd),
15960 Mask, PassThru, Subtarget, DAG);
15962 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15963 dl, Op.getValueType(),
15965 Mask, PassThru, Subtarget, DAG);
15968 case CMP_MASK_CC: {
15969 // Comparison intrinsics with masks.
15970 // Example of transformation:
15971 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15972 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15974 // (v8i1 (insert_subvector undef,
15975 // (v2i1 (and (PCMPEQM %a, %b),
15976 // (extract_subvector
15977 // (v8i1 (bitcast %mask)), 0))), 0))))
15978 EVT VT = Op.getOperand(1).getValueType();
15979 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15980 VT.getVectorNumElements());
15981 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15982 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15983 Mask.getValueType().getSizeInBits());
15985 if (IntrData->Type == CMP_MASK_CC) {
15986 SDValue CC = Op.getOperand(3);
15987 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15988 // We specify 2 possible opcodes for intrinsics with rounding modes.
15989 // First, we check if the intrinsic may have non-default rounding mode,
15990 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15991 if (IntrData->Opc1 != 0) {
15992 SDValue Rnd = Op.getOperand(5);
15993 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15994 X86::STATIC_ROUNDING::CUR_DIRECTION)
15995 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15996 Op.getOperand(2), CC, Rnd);
15998 //default rounding mode
16000 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16001 Op.getOperand(2), CC);
16004 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16005 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16008 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16009 DAG.getTargetConstant(0, dl,
16012 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16013 DAG.getUNDEF(BitcastVT), CmpMask,
16014 DAG.getIntPtrConstant(0, dl));
16015 return DAG.getBitcast(Op.getValueType(), Res);
16017 case COMI: { // Comparison intrinsics
16018 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16019 SDValue LHS = Op.getOperand(1);
16020 SDValue RHS = Op.getOperand(2);
16021 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16022 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16023 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16024 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16025 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16026 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16029 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16030 Op.getOperand(1), Op.getOperand(2), DAG);
16032 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16033 Op.getSimpleValueType(),
16035 Op.getOperand(2), DAG),
16036 Op.getOperand(4), Op.getOperand(3), Subtarget,
16038 case COMPRESS_EXPAND_IN_REG: {
16039 SDValue Mask = Op.getOperand(3);
16040 SDValue DataToCompress = Op.getOperand(1);
16041 SDValue PassThru = Op.getOperand(2);
16042 if (isAllOnes(Mask)) // return data as is
16043 return Op.getOperand(1);
16045 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16047 Mask, PassThru, Subtarget, DAG);
16050 SDValue Mask = Op.getOperand(3);
16051 EVT VT = Op.getValueType();
16052 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16053 VT.getVectorNumElements());
16054 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16055 Mask.getValueType().getSizeInBits());
16057 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16058 DAG.getBitcast(BitcastVT, Mask),
16059 DAG.getIntPtrConstant(0, dl));
16060 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16069 default: return SDValue(); // Don't custom lower most intrinsics.
16071 case Intrinsic::x86_avx2_permd:
16072 case Intrinsic::x86_avx2_permps:
16073 // Operands intentionally swapped. Mask is last operand to intrinsic,
16074 // but second operand for node/instruction.
16075 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16076 Op.getOperand(2), Op.getOperand(1));
16078 // ptest and testp intrinsics. The intrinsic these come from are designed to
16079 // return an integer value, not just an instruction so lower it to the ptest
16080 // or testp pattern and a setcc for the result.
16081 case Intrinsic::x86_sse41_ptestz:
16082 case Intrinsic::x86_sse41_ptestc:
16083 case Intrinsic::x86_sse41_ptestnzc:
16084 case Intrinsic::x86_avx_ptestz_256:
16085 case Intrinsic::x86_avx_ptestc_256:
16086 case Intrinsic::x86_avx_ptestnzc_256:
16087 case Intrinsic::x86_avx_vtestz_ps:
16088 case Intrinsic::x86_avx_vtestc_ps:
16089 case Intrinsic::x86_avx_vtestnzc_ps:
16090 case Intrinsic::x86_avx_vtestz_pd:
16091 case Intrinsic::x86_avx_vtestc_pd:
16092 case Intrinsic::x86_avx_vtestnzc_pd:
16093 case Intrinsic::x86_avx_vtestz_ps_256:
16094 case Intrinsic::x86_avx_vtestc_ps_256:
16095 case Intrinsic::x86_avx_vtestnzc_ps_256:
16096 case Intrinsic::x86_avx_vtestz_pd_256:
16097 case Intrinsic::x86_avx_vtestc_pd_256:
16098 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16099 bool IsTestPacked = false;
16102 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16103 case Intrinsic::x86_avx_vtestz_ps:
16104 case Intrinsic::x86_avx_vtestz_pd:
16105 case Intrinsic::x86_avx_vtestz_ps_256:
16106 case Intrinsic::x86_avx_vtestz_pd_256:
16107 IsTestPacked = true; // Fallthrough
16108 case Intrinsic::x86_sse41_ptestz:
16109 case Intrinsic::x86_avx_ptestz_256:
16111 X86CC = X86::COND_E;
16113 case Intrinsic::x86_avx_vtestc_ps:
16114 case Intrinsic::x86_avx_vtestc_pd:
16115 case Intrinsic::x86_avx_vtestc_ps_256:
16116 case Intrinsic::x86_avx_vtestc_pd_256:
16117 IsTestPacked = true; // Fallthrough
16118 case Intrinsic::x86_sse41_ptestc:
16119 case Intrinsic::x86_avx_ptestc_256:
16121 X86CC = X86::COND_B;
16123 case Intrinsic::x86_avx_vtestnzc_ps:
16124 case Intrinsic::x86_avx_vtestnzc_pd:
16125 case Intrinsic::x86_avx_vtestnzc_ps_256:
16126 case Intrinsic::x86_avx_vtestnzc_pd_256:
16127 IsTestPacked = true; // Fallthrough
16128 case Intrinsic::x86_sse41_ptestnzc:
16129 case Intrinsic::x86_avx_ptestnzc_256:
16131 X86CC = X86::COND_A;
16135 SDValue LHS = Op.getOperand(1);
16136 SDValue RHS = Op.getOperand(2);
16137 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16138 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16139 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16140 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16141 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16143 case Intrinsic::x86_avx512_kortestz_w:
16144 case Intrinsic::x86_avx512_kortestc_w: {
16145 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16146 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16147 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16148 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16149 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16150 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16151 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16154 case Intrinsic::x86_sse42_pcmpistria128:
16155 case Intrinsic::x86_sse42_pcmpestria128:
16156 case Intrinsic::x86_sse42_pcmpistric128:
16157 case Intrinsic::x86_sse42_pcmpestric128:
16158 case Intrinsic::x86_sse42_pcmpistrio128:
16159 case Intrinsic::x86_sse42_pcmpestrio128:
16160 case Intrinsic::x86_sse42_pcmpistris128:
16161 case Intrinsic::x86_sse42_pcmpestris128:
16162 case Intrinsic::x86_sse42_pcmpistriz128:
16163 case Intrinsic::x86_sse42_pcmpestriz128: {
16167 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16168 case Intrinsic::x86_sse42_pcmpistria128:
16169 Opcode = X86ISD::PCMPISTRI;
16170 X86CC = X86::COND_A;
16172 case Intrinsic::x86_sse42_pcmpestria128:
16173 Opcode = X86ISD::PCMPESTRI;
16174 X86CC = X86::COND_A;
16176 case Intrinsic::x86_sse42_pcmpistric128:
16177 Opcode = X86ISD::PCMPISTRI;
16178 X86CC = X86::COND_B;
16180 case Intrinsic::x86_sse42_pcmpestric128:
16181 Opcode = X86ISD::PCMPESTRI;
16182 X86CC = X86::COND_B;
16184 case Intrinsic::x86_sse42_pcmpistrio128:
16185 Opcode = X86ISD::PCMPISTRI;
16186 X86CC = X86::COND_O;
16188 case Intrinsic::x86_sse42_pcmpestrio128:
16189 Opcode = X86ISD::PCMPESTRI;
16190 X86CC = X86::COND_O;
16192 case Intrinsic::x86_sse42_pcmpistris128:
16193 Opcode = X86ISD::PCMPISTRI;
16194 X86CC = X86::COND_S;
16196 case Intrinsic::x86_sse42_pcmpestris128:
16197 Opcode = X86ISD::PCMPESTRI;
16198 X86CC = X86::COND_S;
16200 case Intrinsic::x86_sse42_pcmpistriz128:
16201 Opcode = X86ISD::PCMPISTRI;
16202 X86CC = X86::COND_E;
16204 case Intrinsic::x86_sse42_pcmpestriz128:
16205 Opcode = X86ISD::PCMPESTRI;
16206 X86CC = X86::COND_E;
16209 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16210 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16211 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16212 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16213 DAG.getConstant(X86CC, dl, MVT::i8),
16214 SDValue(PCMP.getNode(), 1));
16215 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16218 case Intrinsic::x86_sse42_pcmpistri128:
16219 case Intrinsic::x86_sse42_pcmpestri128: {
16221 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16222 Opcode = X86ISD::PCMPISTRI;
16224 Opcode = X86ISD::PCMPESTRI;
16226 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16227 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16228 return DAG.getNode(Opcode, dl, VTs, NewOps);
16231 case Intrinsic::x86_seh_lsda: {
16232 // Compute the symbol for the LSDA. We know it'll get emitted later.
16233 MachineFunction &MF = DAG.getMachineFunction();
16234 SDValue Op1 = Op.getOperand(1);
16235 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16236 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16237 GlobalValue::getRealLinkageName(Fn->getName()));
16239 // Generate a simple absolute symbol reference. This intrinsic is only
16240 // supported on 32-bit Windows, which isn't PIC.
16241 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16242 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16245 case Intrinsic::x86_seh_recoverfp: {
16246 SDValue FnOp = Op.getOperand(1);
16247 SDValue IncomingFPOp = Op.getOperand(2);
16248 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16249 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16251 report_fatal_error(
16252 "llvm.x86.seh.recoverfp must take a function as the first argument");
16253 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16256 case Intrinsic::localaddress: {
16257 // Returns one of the stack, base, or frame pointer registers, depending on
16258 // which is used to reference local variables.
16259 MachineFunction &MF = DAG.getMachineFunction();
16260 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16262 if (RegInfo->hasBasePointer(MF))
16263 Reg = RegInfo->getBaseRegister();
16264 else // This function handles the SP or FP case.
16265 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16266 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16271 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16272 SDValue Src, SDValue Mask, SDValue Base,
16273 SDValue Index, SDValue ScaleOp, SDValue Chain,
16274 const X86Subtarget * Subtarget) {
16276 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16278 llvm_unreachable("Invalid scale type");
16279 unsigned ScaleVal = C->getZExtValue();
16280 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16281 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16283 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16284 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16285 Index.getSimpleValueType().getVectorNumElements());
16287 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16289 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16291 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16292 Mask.getValueType().getSizeInBits());
16294 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16295 // are extracted by EXTRACT_SUBVECTOR.
16296 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16297 DAG.getBitcast(BitcastVT, Mask),
16298 DAG.getIntPtrConstant(0, dl));
16300 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16301 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16302 SDValue Segment = DAG.getRegister(0, MVT::i32);
16303 if (Src.getOpcode() == ISD::UNDEF)
16304 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16305 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16306 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16307 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16308 return DAG.getMergeValues(RetOps, dl);
16311 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16312 SDValue Src, SDValue Mask, SDValue Base,
16313 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16315 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16317 llvm_unreachable("Invalid scale type");
16318 unsigned ScaleVal = C->getZExtValue();
16319 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16320 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16322 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16323 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16324 SDValue Segment = DAG.getRegister(0, MVT::i32);
16325 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16326 Index.getSimpleValueType().getVectorNumElements());
16328 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16330 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16332 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16333 Mask.getValueType().getSizeInBits());
16335 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16336 // are extracted by EXTRACT_SUBVECTOR.
16337 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16338 DAG.getBitcast(BitcastVT, Mask),
16339 DAG.getIntPtrConstant(0, dl));
16341 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16342 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16343 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16344 return SDValue(Res, 1);
16347 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16348 SDValue Mask, SDValue Base, SDValue Index,
16349 SDValue ScaleOp, SDValue Chain) {
16351 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16352 assert(C && "Invalid scale type");
16353 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16354 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16355 SDValue Segment = DAG.getRegister(0, MVT::i32);
16357 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16359 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16361 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16363 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16364 //SDVTList VTs = DAG.getVTList(MVT::Other);
16365 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16366 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16367 return SDValue(Res, 0);
16370 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16371 // read performance monitor counters (x86_rdpmc).
16372 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16373 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16374 SmallVectorImpl<SDValue> &Results) {
16375 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16376 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16379 // The ECX register is used to select the index of the performance counter
16381 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16383 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16385 // Reads the content of a 64-bit performance counter and returns it in the
16386 // registers EDX:EAX.
16387 if (Subtarget->is64Bit()) {
16388 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16389 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16392 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16393 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16396 Chain = HI.getValue(1);
16398 if (Subtarget->is64Bit()) {
16399 // The EAX register is loaded with the low-order 32 bits. The EDX register
16400 // is loaded with the supported high-order bits of the counter.
16401 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16402 DAG.getConstant(32, DL, MVT::i8));
16403 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16404 Results.push_back(Chain);
16408 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16409 SDValue Ops[] = { LO, HI };
16410 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16411 Results.push_back(Pair);
16412 Results.push_back(Chain);
16415 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16416 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16417 // also used to custom lower READCYCLECOUNTER nodes.
16418 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16419 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16420 SmallVectorImpl<SDValue> &Results) {
16421 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16422 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16425 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16426 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16427 // and the EAX register is loaded with the low-order 32 bits.
16428 if (Subtarget->is64Bit()) {
16429 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16430 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16433 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16434 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16437 SDValue Chain = HI.getValue(1);
16439 if (Opcode == X86ISD::RDTSCP_DAG) {
16440 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16442 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16443 // the ECX register. Add 'ecx' explicitly to the chain.
16444 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16446 // Explicitly store the content of ECX at the location passed in input
16447 // to the 'rdtscp' intrinsic.
16448 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16449 MachinePointerInfo(), false, false, 0);
16452 if (Subtarget->is64Bit()) {
16453 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16454 // the EAX register is loaded with the low-order 32 bits.
16455 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16456 DAG.getConstant(32, DL, MVT::i8));
16457 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16458 Results.push_back(Chain);
16462 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16463 SDValue Ops[] = { LO, HI };
16464 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16465 Results.push_back(Pair);
16466 Results.push_back(Chain);
16469 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16470 SelectionDAG &DAG) {
16471 SmallVector<SDValue, 2> Results;
16473 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16475 return DAG.getMergeValues(Results, DL);
16478 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16479 SelectionDAG &DAG) {
16480 MachineFunction &MF = DAG.getMachineFunction();
16481 const Function *Fn = MF.getFunction();
16483 SDValue Chain = Op.getOperand(0);
16485 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16486 "using llvm.x86.seh.restoreframe requires a frame pointer");
16488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16489 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16491 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16492 unsigned FrameReg =
16493 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16494 unsigned SPReg = RegInfo->getStackRegister();
16495 unsigned SlotSize = RegInfo->getSlotSize();
16497 // Get incoming EBP.
16498 SDValue IncomingEBP =
16499 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16501 // SP is saved in the first field of every registration node, so load
16502 // [EBP-RegNodeSize] into SP.
16503 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16504 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16505 DAG.getConstant(-RegNodeSize, dl, VT));
16507 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16508 false, VT.getScalarSizeInBits() / 8);
16509 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16511 if (!RegInfo->needsStackRealignment(MF)) {
16512 // Adjust EBP to point back to the original frame position.
16513 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16514 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16516 assert(RegInfo->hasBasePointer(MF) &&
16517 "functions with Win32 EH must use frame or base pointer register");
16519 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16520 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16521 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16523 // Reload the spilled EBP value, now that the stack and base pointers are
16525 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16526 X86FI->setHasSEHFramePtrSave(true);
16527 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16528 X86FI->setSEHFramePtrSaveIndex(FI);
16529 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16530 MachinePointerInfo(), false, false, false,
16531 VT.getScalarSizeInBits() / 8);
16532 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16538 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16539 /// return truncate Store/MaskedStore Node
16540 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16544 SDValue Mask = Op.getOperand(4);
16545 SDValue DataToTruncate = Op.getOperand(3);
16546 SDValue Addr = Op.getOperand(2);
16547 SDValue Chain = Op.getOperand(0);
16549 EVT VT = DataToTruncate.getValueType();
16550 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16551 ElementType, VT.getVectorNumElements());
16553 if (isAllOnes(Mask)) // return just a truncate store
16554 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16555 MachinePointerInfo(), SVT, false, false,
16556 SVT.getScalarSizeInBits()/8);
16558 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16559 MVT::i1, VT.getVectorNumElements());
16560 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16561 Mask.getValueType().getSizeInBits());
16562 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16563 // are extracted by EXTRACT_SUBVECTOR.
16564 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16565 DAG.getBitcast(BitcastVT, Mask),
16566 DAG.getIntPtrConstant(0, dl));
16568 MachineMemOperand *MMO = DAG.getMachineFunction().
16569 getMachineMemOperand(MachinePointerInfo(),
16570 MachineMemOperand::MOStore, SVT.getStoreSize(),
16571 SVT.getScalarSizeInBits()/8);
16573 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16574 VMask, SVT, MMO, true);
16577 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16578 SelectionDAG &DAG) {
16579 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16581 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16583 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16584 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16589 switch(IntrData->Type) {
16591 llvm_unreachable("Unknown Intrinsic Type");
16595 // Emit the node with the right value type.
16596 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16597 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16599 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16600 // Otherwise return the value from Rand, which is always 0, casted to i32.
16601 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16602 DAG.getConstant(1, dl, Op->getValueType(1)),
16603 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16604 SDValue(Result.getNode(), 1) };
16605 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16606 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16609 // Return { result, isValid, chain }.
16610 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16611 SDValue(Result.getNode(), 2));
16614 //gather(v1, mask, index, base, scale);
16615 SDValue Chain = Op.getOperand(0);
16616 SDValue Src = Op.getOperand(2);
16617 SDValue Base = Op.getOperand(3);
16618 SDValue Index = Op.getOperand(4);
16619 SDValue Mask = Op.getOperand(5);
16620 SDValue Scale = Op.getOperand(6);
16621 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16625 //scatter(base, mask, index, v1, scale);
16626 SDValue Chain = Op.getOperand(0);
16627 SDValue Base = Op.getOperand(2);
16628 SDValue Mask = Op.getOperand(3);
16629 SDValue Index = Op.getOperand(4);
16630 SDValue Src = Op.getOperand(5);
16631 SDValue Scale = Op.getOperand(6);
16632 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16636 SDValue Hint = Op.getOperand(6);
16637 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16638 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16639 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16640 SDValue Chain = Op.getOperand(0);
16641 SDValue Mask = Op.getOperand(2);
16642 SDValue Index = Op.getOperand(3);
16643 SDValue Base = Op.getOperand(4);
16644 SDValue Scale = Op.getOperand(5);
16645 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16647 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16649 SmallVector<SDValue, 2> Results;
16650 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16652 return DAG.getMergeValues(Results, dl);
16654 // Read Performance Monitoring Counters.
16656 SmallVector<SDValue, 2> Results;
16657 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16658 return DAG.getMergeValues(Results, dl);
16660 // XTEST intrinsics.
16662 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16663 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16664 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16665 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16667 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16668 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16669 Ret, SDValue(InTrans.getNode(), 1));
16673 SmallVector<SDValue, 2> Results;
16674 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16675 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16676 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16677 DAG.getConstant(-1, dl, MVT::i8));
16678 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16679 Op.getOperand(4), GenCF.getValue(1));
16680 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16681 Op.getOperand(5), MachinePointerInfo(),
16683 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16684 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16686 Results.push_back(SetCC);
16687 Results.push_back(Store);
16688 return DAG.getMergeValues(Results, dl);
16690 case COMPRESS_TO_MEM: {
16692 SDValue Mask = Op.getOperand(4);
16693 SDValue DataToCompress = Op.getOperand(3);
16694 SDValue Addr = Op.getOperand(2);
16695 SDValue Chain = Op.getOperand(0);
16697 EVT VT = DataToCompress.getValueType();
16698 if (isAllOnes(Mask)) // return just a store
16699 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16700 MachinePointerInfo(), false, false,
16701 VT.getScalarSizeInBits()/8);
16703 SDValue Compressed =
16704 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16705 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16706 return DAG.getStore(Chain, dl, Compressed, Addr,
16707 MachinePointerInfo(), false, false,
16708 VT.getScalarSizeInBits()/8);
16710 case TRUNCATE_TO_MEM_VI8:
16711 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16712 case TRUNCATE_TO_MEM_VI16:
16713 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16714 case TRUNCATE_TO_MEM_VI32:
16715 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16716 case EXPAND_FROM_MEM: {
16718 SDValue Mask = Op.getOperand(4);
16719 SDValue PassThru = Op.getOperand(3);
16720 SDValue Addr = Op.getOperand(2);
16721 SDValue Chain = Op.getOperand(0);
16722 EVT VT = Op.getValueType();
16724 if (isAllOnes(Mask)) // return just a load
16725 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16726 false, VT.getScalarSizeInBits()/8);
16728 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16729 false, false, false,
16730 VT.getScalarSizeInBits()/8);
16732 SDValue Results[] = {
16733 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16734 Mask, PassThru, Subtarget, DAG), Chain};
16735 return DAG.getMergeValues(Results, dl);
16740 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16741 SelectionDAG &DAG) const {
16742 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16743 MFI->setReturnAddressIsTaken(true);
16745 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16748 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16750 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16753 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16754 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16755 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16756 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16757 DAG.getNode(ISD::ADD, dl, PtrVT,
16758 FrameAddr, Offset),
16759 MachinePointerInfo(), false, false, false, 0);
16762 // Just load the return address.
16763 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16764 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16765 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16768 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16769 MachineFunction &MF = DAG.getMachineFunction();
16770 MachineFrameInfo *MFI = MF.getFrameInfo();
16771 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16772 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16773 EVT VT = Op.getValueType();
16775 MFI->setFrameAddressIsTaken(true);
16777 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
16778 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
16779 // is not possible to crawl up the stack without looking at the unwind codes
16781 int FrameAddrIndex = FuncInfo->getFAIndex();
16782 if (!FrameAddrIndex) {
16783 // Set up a frame object for the return address.
16784 unsigned SlotSize = RegInfo->getSlotSize();
16785 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
16786 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
16787 FuncInfo->setFAIndex(FrameAddrIndex);
16789 return DAG.getFrameIndex(FrameAddrIndex, VT);
16792 unsigned FrameReg =
16793 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16794 SDLoc dl(Op); // FIXME probably not meaningful
16795 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16796 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16797 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16798 "Invalid Frame Register!");
16799 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16801 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16802 MachinePointerInfo(),
16803 false, false, false, 0);
16807 // FIXME? Maybe this could be a TableGen attribute on some registers and
16808 // this table could be generated automatically from RegInfo.
16809 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
16810 SelectionDAG &DAG) const {
16811 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16812 const MachineFunction &MF = DAG.getMachineFunction();
16814 unsigned Reg = StringSwitch<unsigned>(RegName)
16815 .Case("esp", X86::ESP)
16816 .Case("rsp", X86::RSP)
16817 .Case("ebp", X86::EBP)
16818 .Case("rbp", X86::RBP)
16821 if (Reg == X86::EBP || Reg == X86::RBP) {
16822 if (!TFI.hasFP(MF))
16823 report_fatal_error("register " + StringRef(RegName) +
16824 " is allocatable: function has no frame pointer");
16827 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16828 unsigned FrameReg =
16829 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16830 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
16831 "Invalid Frame Register!");
16839 report_fatal_error("Invalid register name global variable");
16842 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16843 SelectionDAG &DAG) const {
16844 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16845 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16848 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16849 SDValue Chain = Op.getOperand(0);
16850 SDValue Offset = Op.getOperand(1);
16851 SDValue Handler = Op.getOperand(2);
16854 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16855 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16856 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16857 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16858 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16859 "Invalid Frame Register!");
16860 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16861 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16863 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16864 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16866 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16867 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16869 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16871 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16872 DAG.getRegister(StoreAddrReg, PtrVT));
16875 SDValue X86TargetLowering::LowerCATCHRET(SDValue Op, SelectionDAG &DAG) const {
16876 SDValue Chain = Op.getOperand(0);
16877 SDValue Dest = Op.getOperand(1);
16880 MVT PtrVT = getPointerTy(DAG.getDataLayout());
16882 MachineFunction &MF = DAG.getMachineFunction();
16883 if (isAsynchronousEHPersonality(
16884 classifyEHPersonality(MF.getFunction()->getPersonalityFn()))) {
16885 // For SEH, codegen catchret as a branch for now.
16886 // FIXME: Insert something to restore the frame.
16887 return DAG.getNode(ISD::BR, DL, MVT::Other, Chain, Dest);
16890 unsigned ReturnReg = (PtrVT == MVT::i64 ? X86::RAX : X86::EAX);
16892 // Load the address of the destination block.
16893 // FIXME: Do this without creating a BlockAddress.
16894 MachineBasicBlock *DestMBB = cast<BasicBlockSDNode>(Dest)->getBasicBlock();
16896 BlockAddress::get(const_cast<Function *>(MF.getFunction()),
16897 const_cast<BasicBlock *>(DestMBB->getBasicBlock()));
16898 DestMBB->setHasAddressTaken();
16899 SDValue BlockPtr = DAG.getBlockAddress(BA, PtrVT);
16900 Chain = DAG.getCopyToReg(Chain, DL, ReturnReg, BlockPtr);
16901 return DAG.getNode(X86ISD::CATCHRET, DL, MVT::Other, Chain,
16902 DAG.getRegister(ReturnReg, PtrVT));
16905 SDValue X86TargetLowering::LowerCLEANUPRET(SDValue Op, SelectionDAG &DAG) const {
16906 return DAG.getNode(X86ISD::CLEANUPRET, SDLoc(Op), MVT::Other,
16910 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16911 SelectionDAG &DAG) const {
16913 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16914 DAG.getVTList(MVT::i32, MVT::Other),
16915 Op.getOperand(0), Op.getOperand(1));
16918 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16919 SelectionDAG &DAG) const {
16921 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16922 Op.getOperand(0), Op.getOperand(1));
16925 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16926 return Op.getOperand(0);
16929 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16930 SelectionDAG &DAG) const {
16931 SDValue Root = Op.getOperand(0);
16932 SDValue Trmp = Op.getOperand(1); // trampoline
16933 SDValue FPtr = Op.getOperand(2); // nested function
16934 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16937 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16938 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16940 if (Subtarget->is64Bit()) {
16941 SDValue OutChains[6];
16943 // Large code-model.
16944 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16945 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16947 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16948 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16950 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16952 // Load the pointer to the nested function into R11.
16953 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16954 SDValue Addr = Trmp;
16955 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16956 Addr, MachinePointerInfo(TrmpAddr),
16959 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16960 DAG.getConstant(2, dl, MVT::i64));
16961 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16962 MachinePointerInfo(TrmpAddr, 2),
16965 // Load the 'nest' parameter value into R10.
16966 // R10 is specified in X86CallingConv.td
16967 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16968 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16969 DAG.getConstant(10, dl, MVT::i64));
16970 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16971 Addr, MachinePointerInfo(TrmpAddr, 10),
16974 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16975 DAG.getConstant(12, dl, MVT::i64));
16976 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16977 MachinePointerInfo(TrmpAddr, 12),
16980 // Jump to the nested function.
16981 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16982 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16983 DAG.getConstant(20, dl, MVT::i64));
16984 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16985 Addr, MachinePointerInfo(TrmpAddr, 20),
16988 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16989 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16990 DAG.getConstant(22, dl, MVT::i64));
16991 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16992 Addr, MachinePointerInfo(TrmpAddr, 22),
16995 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16997 const Function *Func =
16998 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16999 CallingConv::ID CC = Func->getCallingConv();
17004 llvm_unreachable("Unsupported calling convention");
17005 case CallingConv::C:
17006 case CallingConv::X86_StdCall: {
17007 // Pass 'nest' parameter in ECX.
17008 // Must be kept in sync with X86CallingConv.td
17009 NestReg = X86::ECX;
17011 // Check that ECX wasn't needed by an 'inreg' parameter.
17012 FunctionType *FTy = Func->getFunctionType();
17013 const AttributeSet &Attrs = Func->getAttributes();
17015 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17016 unsigned InRegCount = 0;
17019 for (FunctionType::param_iterator I = FTy->param_begin(),
17020 E = FTy->param_end(); I != E; ++I, ++Idx)
17021 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17022 auto &DL = DAG.getDataLayout();
17023 // FIXME: should only count parameters that are lowered to integers.
17024 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17027 if (InRegCount > 2) {
17028 report_fatal_error("Nest register in use - reduce number of inreg"
17034 case CallingConv::X86_FastCall:
17035 case CallingConv::X86_ThisCall:
17036 case CallingConv::Fast:
17037 // Pass 'nest' parameter in EAX.
17038 // Must be kept in sync with X86CallingConv.td
17039 NestReg = X86::EAX;
17043 SDValue OutChains[4];
17044 SDValue Addr, Disp;
17046 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17047 DAG.getConstant(10, dl, MVT::i32));
17048 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17050 // This is storing the opcode for MOV32ri.
17051 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17052 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17053 OutChains[0] = DAG.getStore(Root, dl,
17054 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17055 Trmp, MachinePointerInfo(TrmpAddr),
17058 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17059 DAG.getConstant(1, dl, MVT::i32));
17060 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17061 MachinePointerInfo(TrmpAddr, 1),
17064 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17065 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17066 DAG.getConstant(5, dl, MVT::i32));
17067 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17068 Addr, MachinePointerInfo(TrmpAddr, 5),
17071 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17072 DAG.getConstant(6, dl, MVT::i32));
17073 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17074 MachinePointerInfo(TrmpAddr, 6),
17077 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17081 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17082 SelectionDAG &DAG) const {
17084 The rounding mode is in bits 11:10 of FPSR, and has the following
17086 00 Round to nearest
17091 FLT_ROUNDS, on the other hand, expects the following:
17098 To perform the conversion, we do:
17099 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17102 MachineFunction &MF = DAG.getMachineFunction();
17103 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17104 unsigned StackAlignment = TFI.getStackAlignment();
17105 MVT VT = Op.getSimpleValueType();
17108 // Save FP Control Word to stack slot
17109 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17110 SDValue StackSlot =
17111 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17113 MachineMemOperand *MMO =
17114 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17115 MachineMemOperand::MOStore, 2, 2);
17117 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17118 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17119 DAG.getVTList(MVT::Other),
17120 Ops, MVT::i16, MMO);
17122 // Load FP Control Word from stack slot
17123 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17124 MachinePointerInfo(), false, false, false, 0);
17126 // Transform as necessary
17128 DAG.getNode(ISD::SRL, DL, MVT::i16,
17129 DAG.getNode(ISD::AND, DL, MVT::i16,
17130 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17131 DAG.getConstant(11, DL, MVT::i8));
17133 DAG.getNode(ISD::SRL, DL, MVT::i16,
17134 DAG.getNode(ISD::AND, DL, MVT::i16,
17135 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17136 DAG.getConstant(9, DL, MVT::i8));
17139 DAG.getNode(ISD::AND, DL, MVT::i16,
17140 DAG.getNode(ISD::ADD, DL, MVT::i16,
17141 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17142 DAG.getConstant(1, DL, MVT::i16)),
17143 DAG.getConstant(3, DL, MVT::i16));
17145 return DAG.getNode((VT.getSizeInBits() < 16 ?
17146 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17149 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17150 MVT VT = Op.getSimpleValueType();
17152 unsigned NumBits = VT.getSizeInBits();
17155 Op = Op.getOperand(0);
17156 if (VT == MVT::i8) {
17157 // Zero extend to i32 since there is not an i8 bsr.
17159 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17162 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17163 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17164 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17166 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17169 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17170 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17173 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17175 // Finally xor with NumBits-1.
17176 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17177 DAG.getConstant(NumBits - 1, dl, OpVT));
17180 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17184 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17185 MVT VT = Op.getSimpleValueType();
17187 unsigned NumBits = VT.getSizeInBits();
17190 Op = Op.getOperand(0);
17191 if (VT == MVT::i8) {
17192 // Zero extend to i32 since there is not an i8 bsr.
17194 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17197 // Issue a bsr (scan bits in reverse).
17198 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17199 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17201 // And xor with NumBits-1.
17202 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17203 DAG.getConstant(NumBits - 1, dl, OpVT));
17206 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17210 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17211 MVT VT = Op.getSimpleValueType();
17212 unsigned NumBits = VT.getSizeInBits();
17214 Op = Op.getOperand(0);
17216 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17217 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17218 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17220 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17223 DAG.getConstant(NumBits, dl, VT),
17224 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17227 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17230 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17231 // ones, and then concatenate the result back.
17232 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17233 MVT VT = Op.getSimpleValueType();
17235 assert(VT.is256BitVector() && VT.isInteger() &&
17236 "Unsupported value type for operation");
17238 unsigned NumElems = VT.getVectorNumElements();
17241 // Extract the LHS vectors
17242 SDValue LHS = Op.getOperand(0);
17243 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17244 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17246 // Extract the RHS vectors
17247 SDValue RHS = Op.getOperand(1);
17248 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17249 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17251 MVT EltVT = VT.getVectorElementType();
17252 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17254 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17255 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17256 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17259 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17260 if (Op.getValueType() == MVT::i1)
17261 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17262 Op.getOperand(0), Op.getOperand(1));
17263 assert(Op.getSimpleValueType().is256BitVector() &&
17264 Op.getSimpleValueType().isInteger() &&
17265 "Only handle AVX 256-bit vector integer operation");
17266 return Lower256IntArith(Op, DAG);
17269 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17270 if (Op.getValueType() == MVT::i1)
17271 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17272 Op.getOperand(0), Op.getOperand(1));
17273 assert(Op.getSimpleValueType().is256BitVector() &&
17274 Op.getSimpleValueType().isInteger() &&
17275 "Only handle AVX 256-bit vector integer operation");
17276 return Lower256IntArith(Op, DAG);
17279 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17280 assert(Op.getSimpleValueType().is256BitVector() &&
17281 Op.getSimpleValueType().isInteger() &&
17282 "Only handle AVX 256-bit vector integer operation");
17283 return Lower256IntArith(Op, DAG);
17286 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17287 SelectionDAG &DAG) {
17289 MVT VT = Op.getSimpleValueType();
17292 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17294 // Decompose 256-bit ops into smaller 128-bit ops.
17295 if (VT.is256BitVector() && !Subtarget->hasInt256())
17296 return Lower256IntArith(Op, DAG);
17298 SDValue A = Op.getOperand(0);
17299 SDValue B = Op.getOperand(1);
17301 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17302 // pairs, multiply and truncate.
17303 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17304 if (Subtarget->hasInt256()) {
17305 if (VT == MVT::v32i8) {
17306 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17307 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17308 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17309 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17310 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17311 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17312 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17313 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17314 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17315 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17318 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17319 return DAG.getNode(
17320 ISD::TRUNCATE, dl, VT,
17321 DAG.getNode(ISD::MUL, dl, ExVT,
17322 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17323 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17326 assert(VT == MVT::v16i8 &&
17327 "Pre-AVX2 support only supports v16i8 multiplication");
17328 MVT ExVT = MVT::v8i16;
17330 // Extract the lo parts and sign extend to i16
17332 if (Subtarget->hasSSE41()) {
17333 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17334 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17336 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17337 -1, 4, -1, 5, -1, 6, -1, 7};
17338 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17339 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17340 ALo = DAG.getBitcast(ExVT, ALo);
17341 BLo = DAG.getBitcast(ExVT, BLo);
17342 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17343 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17346 // Extract the hi parts and sign extend to i16
17348 if (Subtarget->hasSSE41()) {
17349 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17350 -1, -1, -1, -1, -1, -1, -1, -1};
17351 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17352 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17353 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17354 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17356 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17357 -1, 12, -1, 13, -1, 14, -1, 15};
17358 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17359 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17360 AHi = DAG.getBitcast(ExVT, AHi);
17361 BHi = DAG.getBitcast(ExVT, BHi);
17362 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17363 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17366 // Multiply, mask the lower 8bits of the lo/hi results and pack
17367 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17368 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17369 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17370 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17371 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17374 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17375 if (VT == MVT::v4i32) {
17376 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17377 "Should not custom lower when pmuldq is available!");
17379 // Extract the odd parts.
17380 static const int UnpackMask[] = { 1, -1, 3, -1 };
17381 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17382 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17384 // Multiply the even parts.
17385 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17386 // Now multiply odd parts.
17387 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17389 Evens = DAG.getBitcast(VT, Evens);
17390 Odds = DAG.getBitcast(VT, Odds);
17392 // Merge the two vectors back together with a shuffle. This expands into 2
17394 static const int ShufMask[] = { 0, 4, 2, 6 };
17395 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17398 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17399 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17401 // Ahi = psrlqi(a, 32);
17402 // Bhi = psrlqi(b, 32);
17404 // AloBlo = pmuludq(a, b);
17405 // AloBhi = pmuludq(a, Bhi);
17406 // AhiBlo = pmuludq(Ahi, b);
17408 // AloBhi = psllqi(AloBhi, 32);
17409 // AhiBlo = psllqi(AhiBlo, 32);
17410 // return AloBlo + AloBhi + AhiBlo;
17412 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17413 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17415 SDValue AhiBlo = Ahi;
17416 SDValue AloBhi = Bhi;
17417 // Bit cast to 32-bit vectors for MULUDQ
17418 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17419 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17420 A = DAG.getBitcast(MulVT, A);
17421 B = DAG.getBitcast(MulVT, B);
17422 Ahi = DAG.getBitcast(MulVT, Ahi);
17423 Bhi = DAG.getBitcast(MulVT, Bhi);
17425 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17426 // After shifting right const values the result may be all-zero.
17427 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17428 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17429 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17431 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17432 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17433 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17436 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17437 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17440 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17441 assert(Subtarget->isTargetWin64() && "Unexpected target");
17442 EVT VT = Op.getValueType();
17443 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17444 "Unexpected return type for lowering");
17448 switch (Op->getOpcode()) {
17449 default: llvm_unreachable("Unexpected request for libcall!");
17450 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17451 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17452 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17453 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17454 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17455 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17459 SDValue InChain = DAG.getEntryNode();
17461 TargetLowering::ArgListTy Args;
17462 TargetLowering::ArgListEntry Entry;
17463 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17464 EVT ArgVT = Op->getOperand(i).getValueType();
17465 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17466 "Unexpected argument type for lowering");
17467 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17468 Entry.Node = StackPtr;
17469 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17471 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17472 Entry.Ty = PointerType::get(ArgTy,0);
17473 Entry.isSExt = false;
17474 Entry.isZExt = false;
17475 Args.push_back(Entry);
17478 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17479 getPointerTy(DAG.getDataLayout()));
17481 TargetLowering::CallLoweringInfo CLI(DAG);
17482 CLI.setDebugLoc(dl).setChain(InChain)
17483 .setCallee(getLibcallCallingConv(LC),
17484 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17485 Callee, std::move(Args), 0)
17486 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17488 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17489 return DAG.getBitcast(VT, CallInfo.first);
17492 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17493 SelectionDAG &DAG) {
17494 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17495 EVT VT = Op0.getValueType();
17498 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17499 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17501 // PMULxD operations multiply each even value (starting at 0) of LHS with
17502 // the related value of RHS and produce a widen result.
17503 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17504 // => <2 x i64> <ae|cg>
17506 // In other word, to have all the results, we need to perform two PMULxD:
17507 // 1. one with the even values.
17508 // 2. one with the odd values.
17509 // To achieve #2, with need to place the odd values at an even position.
17511 // Place the odd value at an even position (basically, shift all values 1
17512 // step to the left):
17513 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17514 // <a|b|c|d> => <b|undef|d|undef>
17515 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17516 // <e|f|g|h> => <f|undef|h|undef>
17517 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17519 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17521 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17522 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17524 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17525 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17526 // => <2 x i64> <ae|cg>
17527 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17528 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17529 // => <2 x i64> <bf|dh>
17530 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17532 // Shuffle it back into the right order.
17533 SDValue Highs, Lows;
17534 if (VT == MVT::v8i32) {
17535 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17536 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17537 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17538 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17540 const int HighMask[] = {1, 5, 3, 7};
17541 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17542 const int LowMask[] = {0, 4, 2, 6};
17543 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17546 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17547 // unsigned multiply.
17548 if (IsSigned && !Subtarget->hasSSE41()) {
17549 SDValue ShAmt = DAG.getConstant(
17551 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17552 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17553 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17554 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17555 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17557 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17558 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17561 // The first result of MUL_LOHI is actually the low value, followed by the
17563 SDValue Ops[] = {Lows, Highs};
17564 return DAG.getMergeValues(Ops, dl);
17567 // Return true if the required (according to Opcode) shift-imm form is natively
17568 // supported by the Subtarget
17569 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17571 if (VT.getScalarSizeInBits() < 16)
17574 if (VT.is512BitVector() &&
17575 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17578 bool LShift = VT.is128BitVector() ||
17579 (VT.is256BitVector() && Subtarget->hasInt256());
17581 bool AShift = LShift && (Subtarget->hasVLX() ||
17582 (VT != MVT::v2i64 && VT != MVT::v4i64));
17583 return (Opcode == ISD::SRA) ? AShift : LShift;
17586 // The shift amount is a variable, but it is the same for all vector lanes.
17587 // These instructions are defined together with shift-immediate.
17589 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17591 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17594 // Return true if the required (according to Opcode) variable-shift form is
17595 // natively supported by the Subtarget
17596 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17599 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17602 // vXi16 supported only on AVX-512, BWI
17603 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17606 if (VT.is512BitVector() || Subtarget->hasVLX())
17609 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17610 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17611 return (Opcode == ISD::SRA) ? AShift : LShift;
17614 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17615 const X86Subtarget *Subtarget) {
17616 MVT VT = Op.getSimpleValueType();
17618 SDValue R = Op.getOperand(0);
17619 SDValue Amt = Op.getOperand(1);
17621 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17622 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17624 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17625 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17626 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17627 SDValue Ex = DAG.getBitcast(ExVT, R);
17629 if (ShiftAmt >= 32) {
17630 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17632 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17633 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17634 ShiftAmt - 32, DAG);
17635 if (VT == MVT::v2i64)
17636 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17637 if (VT == MVT::v4i64)
17638 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17639 {9, 1, 11, 3, 13, 5, 15, 7});
17641 // SRA upper i32, SHL whole i64 and select lower i32.
17642 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17645 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17646 Lower = DAG.getBitcast(ExVT, Lower);
17647 if (VT == MVT::v2i64)
17648 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17649 if (VT == MVT::v4i64)
17650 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17651 {8, 1, 10, 3, 12, 5, 14, 7});
17653 return DAG.getBitcast(VT, Ex);
17656 // Optimize shl/srl/sra with constant shift amount.
17657 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17658 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17659 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17661 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17662 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17664 // i64 SRA needs to be performed as partial shifts.
17665 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17666 Op.getOpcode() == ISD::SRA)
17667 return ArithmeticShiftRight64(ShiftAmt);
17669 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17670 unsigned NumElts = VT.getVectorNumElements();
17671 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17673 if (Op.getOpcode() == ISD::SHL) {
17674 // Simple i8 add case
17676 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17678 // Make a large shift.
17679 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17681 SHL = DAG.getBitcast(VT, SHL);
17682 // Zero out the rightmost bits.
17683 SmallVector<SDValue, 32> V(
17684 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17685 return DAG.getNode(ISD::AND, dl, VT, SHL,
17686 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17688 if (Op.getOpcode() == ISD::SRL) {
17689 // Make a large shift.
17690 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17692 SRL = DAG.getBitcast(VT, SRL);
17693 // Zero out the leftmost bits.
17694 SmallVector<SDValue, 32> V(
17695 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17696 return DAG.getNode(ISD::AND, dl, VT, SRL,
17697 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17699 if (Op.getOpcode() == ISD::SRA) {
17700 if (ShiftAmt == 7) {
17701 // ashr(R, 7) === cmp_slt(R, 0)
17702 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17703 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17706 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17707 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17708 SmallVector<SDValue, 32> V(NumElts,
17709 DAG.getConstant(128 >> ShiftAmt, dl,
17711 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17712 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17713 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17716 llvm_unreachable("Unknown shift opcode.");
17721 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17722 if (!Subtarget->is64Bit() &&
17723 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17725 // Peek through any splat that was introduced for i64 shift vectorization.
17726 int SplatIndex = -1;
17727 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17728 if (SVN->isSplat()) {
17729 SplatIndex = SVN->getSplatIndex();
17730 Amt = Amt.getOperand(0);
17731 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17732 "Splat shuffle referencing second operand");
17735 if (Amt.getOpcode() != ISD::BITCAST ||
17736 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17739 Amt = Amt.getOperand(0);
17740 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17741 VT.getVectorNumElements();
17742 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17743 uint64_t ShiftAmt = 0;
17744 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17745 for (unsigned i = 0; i != Ratio; ++i) {
17746 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17750 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17753 // Check remaining shift amounts (if not a splat).
17754 if (SplatIndex < 0) {
17755 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17756 uint64_t ShAmt = 0;
17757 for (unsigned j = 0; j != Ratio; ++j) {
17758 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17762 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17764 if (ShAmt != ShiftAmt)
17769 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17770 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17772 if (Op.getOpcode() == ISD::SRA)
17773 return ArithmeticShiftRight64(ShiftAmt);
17779 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17780 const X86Subtarget* Subtarget) {
17781 MVT VT = Op.getSimpleValueType();
17783 SDValue R = Op.getOperand(0);
17784 SDValue Amt = Op.getOperand(1);
17786 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17787 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17789 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
17790 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
17792 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
17794 EVT EltVT = VT.getVectorElementType();
17796 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
17797 // Check if this build_vector node is doing a splat.
17798 // If so, then set BaseShAmt equal to the splat value.
17799 BaseShAmt = BV->getSplatValue();
17800 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
17801 BaseShAmt = SDValue();
17803 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17804 Amt = Amt.getOperand(0);
17806 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
17807 if (SVN && SVN->isSplat()) {
17808 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
17809 SDValue InVec = Amt.getOperand(0);
17810 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17811 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
17812 "Unexpected shuffle index found!");
17813 BaseShAmt = InVec.getOperand(SplatIdx);
17814 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17815 if (ConstantSDNode *C =
17816 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17817 if (C->getZExtValue() == SplatIdx)
17818 BaseShAmt = InVec.getOperand(1);
17823 // Avoid introducing an extract element from a shuffle.
17824 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
17825 DAG.getIntPtrConstant(SplatIdx, dl));
17829 if (BaseShAmt.getNode()) {
17830 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
17831 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
17832 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
17833 else if (EltVT.bitsLT(MVT::i32))
17834 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17836 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
17840 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17841 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
17842 Amt.getOpcode() == ISD::BITCAST &&
17843 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17844 Amt = Amt.getOperand(0);
17845 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17846 VT.getVectorNumElements();
17847 std::vector<SDValue> Vals(Ratio);
17848 for (unsigned i = 0; i != Ratio; ++i)
17849 Vals[i] = Amt.getOperand(i);
17850 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17851 for (unsigned j = 0; j != Ratio; ++j)
17852 if (Vals[j] != Amt.getOperand(i + j))
17856 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
17857 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
17862 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17863 SelectionDAG &DAG) {
17864 MVT VT = Op.getSimpleValueType();
17866 SDValue R = Op.getOperand(0);
17867 SDValue Amt = Op.getOperand(1);
17869 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17870 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17872 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
17875 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
17878 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
17881 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
17882 // shifts per-lane and then shuffle the partial results back together.
17883 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
17884 // Splat the shift amounts so the scalar shifts above will catch it.
17885 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
17886 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
17887 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
17888 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
17889 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
17892 // i64 vector arithmetic shift can be emulated with the transform:
17893 // M = lshr(SIGN_BIT, Amt)
17894 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
17895 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
17896 Op.getOpcode() == ISD::SRA) {
17897 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
17898 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
17899 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17900 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
17901 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
17905 // If possible, lower this packed shift into a vector multiply instead of
17906 // expanding it into a sequence of scalar shifts.
17907 // Do this only if the vector shift count is a constant build_vector.
17908 if (Op.getOpcode() == ISD::SHL &&
17909 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17910 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17911 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17912 SmallVector<SDValue, 8> Elts;
17913 EVT SVT = VT.getScalarType();
17914 unsigned SVTBits = SVT.getSizeInBits();
17915 const APInt &One = APInt(SVTBits, 1);
17916 unsigned NumElems = VT.getVectorNumElements();
17918 for (unsigned i=0; i !=NumElems; ++i) {
17919 SDValue Op = Amt->getOperand(i);
17920 if (Op->getOpcode() == ISD::UNDEF) {
17921 Elts.push_back(Op);
17925 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17926 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17927 uint64_t ShAmt = C.getZExtValue();
17928 if (ShAmt >= SVTBits) {
17929 Elts.push_back(DAG.getUNDEF(SVT));
17932 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
17934 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17935 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17938 // Lower SHL with variable shift amount.
17939 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17940 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
17942 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
17943 DAG.getConstant(0x3f800000U, dl, VT));
17944 Op = DAG.getBitcast(MVT::v4f32, Op);
17945 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17946 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17949 // If possible, lower this shift as a sequence of two shifts by
17950 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17952 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17954 // Could be rewritten as:
17955 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17957 // The advantage is that the two shifts from the example would be
17958 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17959 // the vector shift into four scalar shifts plus four pairs of vector
17961 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17962 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17963 unsigned TargetOpcode = X86ISD::MOVSS;
17964 bool CanBeSimplified;
17965 // The splat value for the first packed shift (the 'X' from the example).
17966 SDValue Amt1 = Amt->getOperand(0);
17967 // The splat value for the second packed shift (the 'Y' from the example).
17968 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17969 Amt->getOperand(2);
17971 // See if it is possible to replace this node with a sequence of
17972 // two shifts followed by a MOVSS/MOVSD
17973 if (VT == MVT::v4i32) {
17974 // Check if it is legal to use a MOVSS.
17975 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17976 Amt2 == Amt->getOperand(3);
17977 if (!CanBeSimplified) {
17978 // Otherwise, check if we can still simplify this node using a MOVSD.
17979 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17980 Amt->getOperand(2) == Amt->getOperand(3);
17981 TargetOpcode = X86ISD::MOVSD;
17982 Amt2 = Amt->getOperand(2);
17985 // Do similar checks for the case where the machine value type
17987 CanBeSimplified = Amt1 == Amt->getOperand(1);
17988 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17989 CanBeSimplified = Amt2 == Amt->getOperand(i);
17991 if (!CanBeSimplified) {
17992 TargetOpcode = X86ISD::MOVSD;
17993 CanBeSimplified = true;
17994 Amt2 = Amt->getOperand(4);
17995 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17996 CanBeSimplified = Amt1 == Amt->getOperand(i);
17997 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17998 CanBeSimplified = Amt2 == Amt->getOperand(j);
18002 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18003 isa<ConstantSDNode>(Amt2)) {
18004 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18005 EVT CastVT = MVT::v4i32;
18007 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18008 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18010 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18011 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18012 if (TargetOpcode == X86ISD::MOVSD)
18013 CastVT = MVT::v2i64;
18014 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18015 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18016 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18018 return DAG.getBitcast(VT, Result);
18022 // v4i32 Non Uniform Shifts.
18023 // If the shift amount is constant we can shift each lane using the SSE2
18024 // immediate shifts, else we need to zero-extend each lane to the lower i64
18025 // and shift using the SSE2 variable shifts.
18026 // The separate results can then be blended together.
18027 if (VT == MVT::v4i32) {
18028 unsigned Opc = Op.getOpcode();
18029 SDValue Amt0, Amt1, Amt2, Amt3;
18030 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18031 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18032 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18033 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18034 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18036 // ISD::SHL is handled above but we include it here for completeness.
18039 llvm_unreachable("Unknown target vector shift node");
18041 Opc = X86ISD::VSHL;
18044 Opc = X86ISD::VSRL;
18047 Opc = X86ISD::VSRA;
18050 // The SSE2 shifts use the lower i64 as the same shift amount for
18051 // all lanes and the upper i64 is ignored. These shuffle masks
18052 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18053 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18054 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18055 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18056 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18057 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18060 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18061 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18062 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18063 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18064 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18065 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18066 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18069 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
18070 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18071 unsigned ShiftOpcode = Op->getOpcode();
18073 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18074 // On SSE41 targets we make use of the fact that VSELECT lowers
18075 // to PBLENDVB which selects bytes based just on the sign bit.
18076 if (Subtarget->hasSSE41()) {
18077 V0 = DAG.getBitcast(VT, V0);
18078 V1 = DAG.getBitcast(VT, V1);
18079 Sel = DAG.getBitcast(VT, Sel);
18080 return DAG.getBitcast(SelVT,
18081 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18083 // On pre-SSE41 targets we test for the sign bit by comparing to
18084 // zero - a negative value will set all bits of the lanes to true
18085 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18086 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18087 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18088 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18091 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18092 // We can safely do this using i16 shifts as we're only interested in
18093 // the 3 lower bits of each byte.
18094 Amt = DAG.getBitcast(ExtVT, Amt);
18095 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18096 Amt = DAG.getBitcast(VT, Amt);
18098 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18099 // r = VSELECT(r, shift(r, 4), a);
18101 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18102 R = SignBitSelect(VT, Amt, M, R);
18105 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18107 // r = VSELECT(r, shift(r, 2), a);
18108 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18109 R = SignBitSelect(VT, Amt, M, R);
18112 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18114 // return VSELECT(r, shift(r, 1), a);
18115 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18116 R = SignBitSelect(VT, Amt, M, R);
18120 if (Op->getOpcode() == ISD::SRA) {
18121 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18122 // so we can correctly sign extend. We don't care what happens to the
18124 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18125 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18126 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18127 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18128 ALo = DAG.getBitcast(ExtVT, ALo);
18129 AHi = DAG.getBitcast(ExtVT, AHi);
18130 RLo = DAG.getBitcast(ExtVT, RLo);
18131 RHi = DAG.getBitcast(ExtVT, RHi);
18133 // r = VSELECT(r, shift(r, 4), a);
18134 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18135 DAG.getConstant(4, dl, ExtVT));
18136 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18137 DAG.getConstant(4, dl, ExtVT));
18138 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18139 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18142 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18143 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18145 // r = VSELECT(r, shift(r, 2), a);
18146 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18147 DAG.getConstant(2, dl, ExtVT));
18148 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18149 DAG.getConstant(2, dl, ExtVT));
18150 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18151 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18154 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18155 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18157 // r = VSELECT(r, shift(r, 1), a);
18158 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18159 DAG.getConstant(1, dl, ExtVT));
18160 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18161 DAG.getConstant(1, dl, ExtVT));
18162 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18163 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18165 // Logical shift the result back to the lower byte, leaving a zero upper
18167 // meaning that we can safely pack with PACKUSWB.
18169 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18171 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18172 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18176 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18177 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18178 // solution better.
18179 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18180 MVT ExtVT = MVT::v8i32;
18182 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18183 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18184 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18185 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18186 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18189 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
18190 MVT ExtVT = MVT::v8i32;
18191 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18192 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18193 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18194 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18195 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18196 ALo = DAG.getBitcast(ExtVT, ALo);
18197 AHi = DAG.getBitcast(ExtVT, AHi);
18198 RLo = DAG.getBitcast(ExtVT, RLo);
18199 RHi = DAG.getBitcast(ExtVT, RHi);
18200 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18201 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18202 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18203 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18204 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18207 if (VT == MVT::v8i16) {
18208 unsigned ShiftOpcode = Op->getOpcode();
18210 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18211 // On SSE41 targets we make use of the fact that VSELECT lowers
18212 // to PBLENDVB which selects bytes based just on the sign bit.
18213 if (Subtarget->hasSSE41()) {
18214 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18215 V0 = DAG.getBitcast(ExtVT, V0);
18216 V1 = DAG.getBitcast(ExtVT, V1);
18217 Sel = DAG.getBitcast(ExtVT, Sel);
18218 return DAG.getBitcast(
18219 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18221 // On pre-SSE41 targets we splat the sign bit - a negative value will
18222 // set all bits of the lanes to true and VSELECT uses that in
18223 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18225 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18226 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18229 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18230 if (Subtarget->hasSSE41()) {
18231 // On SSE41 targets we need to replicate the shift mask in both
18232 // bytes for PBLENDVB.
18235 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18236 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18238 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18241 // r = VSELECT(r, shift(r, 8), a);
18242 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18243 R = SignBitSelect(Amt, M, R);
18246 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18248 // r = VSELECT(r, shift(r, 4), a);
18249 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18250 R = SignBitSelect(Amt, M, R);
18253 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18255 // r = VSELECT(r, shift(r, 2), a);
18256 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18257 R = SignBitSelect(Amt, M, R);
18260 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18262 // return VSELECT(r, shift(r, 1), a);
18263 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18264 R = SignBitSelect(Amt, M, R);
18268 // Decompose 256-bit shifts into smaller 128-bit shifts.
18269 if (VT.is256BitVector()) {
18270 unsigned NumElems = VT.getVectorNumElements();
18271 MVT EltVT = VT.getVectorElementType();
18272 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18274 // Extract the two vectors
18275 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18276 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18278 // Recreate the shift amount vectors
18279 SDValue Amt1, Amt2;
18280 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18281 // Constant shift amount
18282 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18283 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18284 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18286 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18287 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18289 // Variable shift amount
18290 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18291 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18294 // Issue new vector shifts for the smaller types
18295 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18296 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18298 // Concatenate the result back
18299 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18305 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18306 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18307 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18308 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18309 // has only one use.
18310 SDNode *N = Op.getNode();
18311 SDValue LHS = N->getOperand(0);
18312 SDValue RHS = N->getOperand(1);
18313 unsigned BaseOp = 0;
18316 switch (Op.getOpcode()) {
18317 default: llvm_unreachable("Unknown ovf instruction!");
18319 // A subtract of one will be selected as a INC. Note that INC doesn't
18320 // set CF, so we can't do this for UADDO.
18321 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18323 BaseOp = X86ISD::INC;
18324 Cond = X86::COND_O;
18327 BaseOp = X86ISD::ADD;
18328 Cond = X86::COND_O;
18331 BaseOp = X86ISD::ADD;
18332 Cond = X86::COND_B;
18335 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18336 // set CF, so we can't do this for USUBO.
18337 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18339 BaseOp = X86ISD::DEC;
18340 Cond = X86::COND_O;
18343 BaseOp = X86ISD::SUB;
18344 Cond = X86::COND_O;
18347 BaseOp = X86ISD::SUB;
18348 Cond = X86::COND_B;
18351 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18352 Cond = X86::COND_O;
18354 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18355 if (N->getValueType(0) == MVT::i8) {
18356 BaseOp = X86ISD::UMUL8;
18357 Cond = X86::COND_O;
18360 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18362 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18365 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18366 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18367 SDValue(Sum.getNode(), 2));
18369 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18373 // Also sets EFLAGS.
18374 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18375 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18378 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18379 DAG.getConstant(Cond, DL, MVT::i32),
18380 SDValue(Sum.getNode(), 1));
18382 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18385 /// Returns true if the operand type is exactly twice the native width, and
18386 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18387 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18388 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18389 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18390 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18393 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18394 else if (OpWidth == 128)
18395 return Subtarget->hasCmpxchg16b();
18400 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18401 return needsCmpXchgNb(SI->getValueOperand()->getType());
18404 // Note: this turns large loads into lock cmpxchg8b/16b.
18405 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18406 TargetLowering::AtomicExpansionKind
18407 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18408 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18409 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18410 : AtomicExpansionKind::None;
18413 TargetLowering::AtomicExpansionKind
18414 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18415 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18416 Type *MemType = AI->getType();
18418 // If the operand is too big, we must see if cmpxchg8/16b is available
18419 // and default to library calls otherwise.
18420 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18421 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18422 : AtomicExpansionKind::None;
18425 AtomicRMWInst::BinOp Op = AI->getOperation();
18428 llvm_unreachable("Unknown atomic operation");
18429 case AtomicRMWInst::Xchg:
18430 case AtomicRMWInst::Add:
18431 case AtomicRMWInst::Sub:
18432 // It's better to use xadd, xsub or xchg for these in all cases.
18433 return AtomicExpansionKind::None;
18434 case AtomicRMWInst::Or:
18435 case AtomicRMWInst::And:
18436 case AtomicRMWInst::Xor:
18437 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18438 // prefix to a normal instruction for these operations.
18439 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18440 : AtomicExpansionKind::None;
18441 case AtomicRMWInst::Nand:
18442 case AtomicRMWInst::Max:
18443 case AtomicRMWInst::Min:
18444 case AtomicRMWInst::UMax:
18445 case AtomicRMWInst::UMin:
18446 // These always require a non-trivial set of data operations on x86. We must
18447 // use a cmpxchg loop.
18448 return AtomicExpansionKind::CmpXChg;
18452 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18453 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18454 // no-sse2). There isn't any reason to disable it if the target processor
18456 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18460 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18461 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18462 Type *MemType = AI->getType();
18463 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18464 // there is no benefit in turning such RMWs into loads, and it is actually
18465 // harmful as it introduces a mfence.
18466 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18469 auto Builder = IRBuilder<>(AI);
18470 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18471 auto SynchScope = AI->getSynchScope();
18472 // We must restrict the ordering to avoid generating loads with Release or
18473 // ReleaseAcquire orderings.
18474 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18475 auto Ptr = AI->getPointerOperand();
18477 // Before the load we need a fence. Here is an example lifted from
18478 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18481 // x.store(1, relaxed);
18482 // r1 = y.fetch_add(0, release);
18484 // y.fetch_add(42, acquire);
18485 // r2 = x.load(relaxed);
18486 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18487 // lowered to just a load without a fence. A mfence flushes the store buffer,
18488 // making the optimization clearly correct.
18489 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18490 // otherwise, we might be able to be more aggressive on relaxed idempotent
18491 // rmw. In practice, they do not look useful, so we don't try to be
18492 // especially clever.
18493 if (SynchScope == SingleThread)
18494 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18495 // the IR level, so we must wrap it in an intrinsic.
18498 if (!hasMFENCE(*Subtarget))
18499 // FIXME: it might make sense to use a locked operation here but on a
18500 // different cache-line to prevent cache-line bouncing. In practice it
18501 // is probably a small win, and x86 processors without mfence are rare
18502 // enough that we do not bother.
18506 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18507 Builder.CreateCall(MFence, {});
18509 // Finally we can emit the atomic load.
18510 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18511 AI->getType()->getPrimitiveSizeInBits());
18512 Loaded->setAtomic(Order, SynchScope);
18513 AI->replaceAllUsesWith(Loaded);
18514 AI->eraseFromParent();
18518 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18519 SelectionDAG &DAG) {
18521 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18522 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18523 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18524 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18526 // The only fence that needs an instruction is a sequentially-consistent
18527 // cross-thread fence.
18528 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18529 if (hasMFENCE(*Subtarget))
18530 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18532 SDValue Chain = Op.getOperand(0);
18533 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18535 DAG.getRegister(X86::ESP, MVT::i32), // Base
18536 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18537 DAG.getRegister(0, MVT::i32), // Index
18538 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18539 DAG.getRegister(0, MVT::i32), // Segment.
18543 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18544 return SDValue(Res, 0);
18547 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18548 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18551 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18552 SelectionDAG &DAG) {
18553 MVT T = Op.getSimpleValueType();
18557 switch(T.SimpleTy) {
18558 default: llvm_unreachable("Invalid value type!");
18559 case MVT::i8: Reg = X86::AL; size = 1; break;
18560 case MVT::i16: Reg = X86::AX; size = 2; break;
18561 case MVT::i32: Reg = X86::EAX; size = 4; break;
18563 assert(Subtarget->is64Bit() && "Node not type legal!");
18564 Reg = X86::RAX; size = 8;
18567 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18568 Op.getOperand(2), SDValue());
18569 SDValue Ops[] = { cpIn.getValue(0),
18572 DAG.getTargetConstant(size, DL, MVT::i8),
18573 cpIn.getValue(1) };
18574 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18575 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18576 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18580 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18581 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18582 MVT::i32, cpOut.getValue(2));
18583 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18584 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18587 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18588 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18589 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18593 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18594 SelectionDAG &DAG) {
18595 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18596 MVT DstVT = Op.getSimpleValueType();
18598 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18599 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18600 if (DstVT != MVT::f64)
18601 // This conversion needs to be expanded.
18604 SDValue InVec = Op->getOperand(0);
18606 unsigned NumElts = SrcVT.getVectorNumElements();
18607 EVT SVT = SrcVT.getVectorElementType();
18609 // Widen the vector in input in the case of MVT::v2i32.
18610 // Example: from MVT::v2i32 to MVT::v4i32.
18611 SmallVector<SDValue, 16> Elts;
18612 for (unsigned i = 0, e = NumElts; i != e; ++i)
18613 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18614 DAG.getIntPtrConstant(i, dl)));
18616 // Explicitly mark the extra elements as Undef.
18617 Elts.append(NumElts, DAG.getUNDEF(SVT));
18619 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18620 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18621 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18622 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18623 DAG.getIntPtrConstant(0, dl));
18626 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18627 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18628 assert((DstVT == MVT::i64 ||
18629 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18630 "Unexpected custom BITCAST");
18631 // i64 <=> MMX conversions are Legal.
18632 if (SrcVT==MVT::i64 && DstVT.isVector())
18634 if (DstVT==MVT::i64 && SrcVT.isVector())
18636 // MMX <=> MMX conversions are Legal.
18637 if (SrcVT.isVector() && DstVT.isVector())
18639 // All other conversions need to be expanded.
18643 /// Compute the horizontal sum of bytes in V for the elements of VT.
18645 /// Requires V to be a byte vector and VT to be an integer vector type with
18646 /// wider elements than V's type. The width of the elements of VT determines
18647 /// how many bytes of V are summed horizontally to produce each element of the
18649 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18650 const X86Subtarget *Subtarget,
18651 SelectionDAG &DAG) {
18653 MVT ByteVecVT = V.getSimpleValueType();
18654 MVT EltVT = VT.getVectorElementType();
18655 int NumElts = VT.getVectorNumElements();
18656 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18657 "Expected value to have byte element type.");
18658 assert(EltVT != MVT::i8 &&
18659 "Horizontal byte sum only makes sense for wider elements!");
18660 unsigned VecSize = VT.getSizeInBits();
18661 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18663 // PSADBW instruction horizontally add all bytes and leave the result in i64
18664 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18665 if (EltVT == MVT::i64) {
18666 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18667 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18668 return DAG.getBitcast(VT, V);
18671 if (EltVT == MVT::i32) {
18672 // We unpack the low half and high half into i32s interleaved with zeros so
18673 // that we can use PSADBW to horizontally sum them. The most useful part of
18674 // this is that it lines up the results of two PSADBW instructions to be
18675 // two v2i64 vectors which concatenated are the 4 population counts. We can
18676 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18677 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18678 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18679 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18681 // Do the horizontal sums into two v2i64s.
18682 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18683 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18684 DAG.getBitcast(ByteVecVT, Low), Zeros);
18685 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18686 DAG.getBitcast(ByteVecVT, High), Zeros);
18688 // Merge them together.
18689 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18690 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18691 DAG.getBitcast(ShortVecVT, Low),
18692 DAG.getBitcast(ShortVecVT, High));
18694 return DAG.getBitcast(VT, V);
18697 // The only element type left is i16.
18698 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18700 // To obtain pop count for each i16 element starting from the pop count for
18701 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18702 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18703 // directly supported.
18704 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18705 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18706 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18707 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18708 DAG.getBitcast(ByteVecVT, V));
18709 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18712 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18713 const X86Subtarget *Subtarget,
18714 SelectionDAG &DAG) {
18715 MVT VT = Op.getSimpleValueType();
18716 MVT EltVT = VT.getVectorElementType();
18717 unsigned VecSize = VT.getSizeInBits();
18719 // Implement a lookup table in register by using an algorithm based on:
18720 // http://wm.ite.pl/articles/sse-popcount.html
18722 // The general idea is that every lower byte nibble in the input vector is an
18723 // index into a in-register pre-computed pop count table. We then split up the
18724 // input vector in two new ones: (1) a vector with only the shifted-right
18725 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18726 // masked out higher ones) for each byte. PSHUB is used separately with both
18727 // to index the in-register table. Next, both are added and the result is a
18728 // i8 vector where each element contains the pop count for input byte.
18730 // To obtain the pop count for elements != i8, we follow up with the same
18731 // approach and use additional tricks as described below.
18733 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18734 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18735 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18736 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18738 int NumByteElts = VecSize / 8;
18739 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18740 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18741 SmallVector<SDValue, 16> LUTVec;
18742 for (int i = 0; i < NumByteElts; ++i)
18743 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18744 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18745 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18746 DAG.getConstant(0x0F, DL, MVT::i8));
18747 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18750 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18751 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18752 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18755 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18757 // The input vector is used as the shuffle mask that index elements into the
18758 // LUT. After counting low and high nibbles, add the vector to obtain the
18759 // final pop count per i8 element.
18760 SDValue HighPopCnt =
18761 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18762 SDValue LowPopCnt =
18763 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18764 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18766 if (EltVT == MVT::i8)
18769 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
18772 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
18773 const X86Subtarget *Subtarget,
18774 SelectionDAG &DAG) {
18775 MVT VT = Op.getSimpleValueType();
18776 assert(VT.is128BitVector() &&
18777 "Only 128-bit vector bitmath lowering supported.");
18779 int VecSize = VT.getSizeInBits();
18780 MVT EltVT = VT.getVectorElementType();
18781 int Len = EltVT.getSizeInBits();
18783 // This is the vectorized version of the "best" algorithm from
18784 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
18785 // with a minor tweak to use a series of adds + shifts instead of vector
18786 // multiplications. Implemented for all integer vector types. We only use
18787 // this when we don't have SSSE3 which allows a LUT-based lowering that is
18788 // much faster, even faster than using native popcnt instructions.
18790 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
18791 MVT VT = V.getSimpleValueType();
18792 SmallVector<SDValue, 32> Shifters(
18793 VT.getVectorNumElements(),
18794 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
18795 return DAG.getNode(OpCode, DL, VT, V,
18796 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
18798 auto GetMask = [&](SDValue V, APInt Mask) {
18799 MVT VT = V.getSimpleValueType();
18800 SmallVector<SDValue, 32> Masks(
18801 VT.getVectorNumElements(),
18802 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
18803 return DAG.getNode(ISD::AND, DL, VT, V,
18804 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
18807 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
18808 // x86, so set the SRL type to have elements at least i16 wide. This is
18809 // correct because all of our SRLs are followed immediately by a mask anyways
18810 // that handles any bits that sneak into the high bits of the byte elements.
18811 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
18815 // v = v - ((v >> 1) & 0x55555555...)
18817 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
18818 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
18819 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
18821 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
18822 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
18823 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
18824 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
18825 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
18827 // v = (v + (v >> 4)) & 0x0F0F0F0F...
18828 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
18829 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
18830 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
18832 // At this point, V contains the byte-wise population count, and we are
18833 // merely doing a horizontal sum if necessary to get the wider element
18835 if (EltVT == MVT::i8)
18838 return LowerHorizontalByteSum(
18839 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
18843 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18844 SelectionDAG &DAG) {
18845 MVT VT = Op.getSimpleValueType();
18846 // FIXME: Need to add AVX-512 support here!
18847 assert((VT.is256BitVector() || VT.is128BitVector()) &&
18848 "Unknown CTPOP type to handle");
18849 SDLoc DL(Op.getNode());
18850 SDValue Op0 = Op.getOperand(0);
18852 if (!Subtarget->hasSSSE3()) {
18853 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
18854 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
18855 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
18858 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
18859 unsigned NumElems = VT.getVectorNumElements();
18861 // Extract each 128-bit vector, compute pop count and concat the result.
18862 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
18863 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
18865 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
18866 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
18867 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
18870 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
18873 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18874 SelectionDAG &DAG) {
18875 assert(Op.getValueType().isVector() &&
18876 "We only do custom lowering for vector population count.");
18877 return LowerVectorCTPOP(Op, Subtarget, DAG);
18880 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18881 SDNode *Node = Op.getNode();
18883 EVT T = Node->getValueType(0);
18884 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18885 DAG.getConstant(0, dl, T), Node->getOperand(2));
18886 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18887 cast<AtomicSDNode>(Node)->getMemoryVT(),
18888 Node->getOperand(0),
18889 Node->getOperand(1), negOp,
18890 cast<AtomicSDNode>(Node)->getMemOperand(),
18891 cast<AtomicSDNode>(Node)->getOrdering(),
18892 cast<AtomicSDNode>(Node)->getSynchScope());
18895 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18896 SDNode *Node = Op.getNode();
18898 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18900 // Convert seq_cst store -> xchg
18901 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18902 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18903 // (The only way to get a 16-byte store is cmpxchg16b)
18904 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18905 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18906 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18907 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18908 cast<AtomicSDNode>(Node)->getMemoryVT(),
18909 Node->getOperand(0),
18910 Node->getOperand(1), Node->getOperand(2),
18911 cast<AtomicSDNode>(Node)->getMemOperand(),
18912 cast<AtomicSDNode>(Node)->getOrdering(),
18913 cast<AtomicSDNode>(Node)->getSynchScope());
18914 return Swap.getValue(1);
18916 // Other atomic stores have a simple pattern.
18920 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18921 EVT VT = Op.getNode()->getSimpleValueType(0);
18923 // Let legalize expand this if it isn't a legal type yet.
18924 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18927 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18930 bool ExtraOp = false;
18931 switch (Op.getOpcode()) {
18932 default: llvm_unreachable("Invalid code");
18933 case ISD::ADDC: Opc = X86ISD::ADD; break;
18934 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18935 case ISD::SUBC: Opc = X86ISD::SUB; break;
18936 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18940 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18942 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18943 Op.getOperand(1), Op.getOperand(2));
18946 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18947 SelectionDAG &DAG) {
18948 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18950 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18951 // which returns the values as { float, float } (in XMM0) or
18952 // { double, double } (which is returned in XMM0, XMM1).
18954 SDValue Arg = Op.getOperand(0);
18955 EVT ArgVT = Arg.getValueType();
18956 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18958 TargetLowering::ArgListTy Args;
18959 TargetLowering::ArgListEntry Entry;
18963 Entry.isSExt = false;
18964 Entry.isZExt = false;
18965 Args.push_back(Entry);
18967 bool isF64 = ArgVT == MVT::f64;
18968 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18969 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18970 // the results are returned via SRet in memory.
18971 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18974 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
18976 Type *RetTy = isF64
18977 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
18978 : (Type*)VectorType::get(ArgTy, 4);
18980 TargetLowering::CallLoweringInfo CLI(DAG);
18981 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18982 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18984 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18987 // Returned in xmm0 and xmm1.
18988 return CallResult.first;
18990 // Returned in bits 0:31 and 32:64 xmm0.
18991 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18992 CallResult.first, DAG.getIntPtrConstant(0, dl));
18993 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18994 CallResult.first, DAG.getIntPtrConstant(1, dl));
18995 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18996 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18999 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19000 SelectionDAG &DAG) {
19001 assert(Subtarget->hasAVX512() &&
19002 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19004 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19005 EVT VT = N->getValue().getValueType();
19006 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19009 // X86 scatter kills mask register, so its type should be added to
19010 // the list of return values
19011 if (N->getNumValues() == 1) {
19012 SDValue Index = N->getIndex();
19013 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19014 !Index.getValueType().is512BitVector())
19015 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19017 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19018 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19019 N->getOperand(3), Index };
19021 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19022 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19023 return SDValue(NewScatter.getNode(), 0);
19028 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19029 SelectionDAG &DAG) {
19030 assert(Subtarget->hasAVX512() &&
19031 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19033 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19034 EVT VT = Op.getValueType();
19035 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19038 SDValue Index = N->getIndex();
19039 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19040 !Index.getValueType().is512BitVector()) {
19041 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19042 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19043 N->getOperand(3), Index };
19044 DAG.UpdateNodeOperands(N, Ops);
19049 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19050 SelectionDAG &DAG) const {
19051 // TODO: Eventually, the lowering of these nodes should be informed by or
19052 // deferred to the GC strategy for the function in which they appear. For
19053 // now, however, they must be lowered to something. Since they are logically
19054 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19055 // require special handling for these nodes), lower them as literal NOOPs for
19057 SmallVector<SDValue, 2> Ops;
19059 Ops.push_back(Op.getOperand(0));
19060 if (Op->getGluedNode())
19061 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19064 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19065 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19070 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19071 SelectionDAG &DAG) const {
19072 // TODO: Eventually, the lowering of these nodes should be informed by or
19073 // deferred to the GC strategy for the function in which they appear. For
19074 // now, however, they must be lowered to something. Since they are logically
19075 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19076 // require special handling for these nodes), lower them as literal NOOPs for
19078 SmallVector<SDValue, 2> Ops;
19080 Ops.push_back(Op.getOperand(0));
19081 if (Op->getGluedNode())
19082 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19085 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19086 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19091 /// LowerOperation - Provide custom lowering hooks for some operations.
19093 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19094 switch (Op.getOpcode()) {
19095 default: llvm_unreachable("Should not custom lower this!");
19096 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19097 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19098 return LowerCMP_SWAP(Op, Subtarget, DAG);
19099 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19100 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19101 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19102 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19103 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19104 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19105 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19106 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19107 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19108 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19109 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19110 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19111 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19112 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19113 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19114 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19115 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19116 case ISD::SHL_PARTS:
19117 case ISD::SRA_PARTS:
19118 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19119 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19120 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19121 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19122 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19123 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19124 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19125 case ISD::SIGN_EXTEND_VECTOR_INREG:
19126 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19127 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19128 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19129 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19130 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19132 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19133 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19134 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19135 case ISD::SETCC: return LowerSETCC(Op, DAG);
19136 case ISD::SELECT: return LowerSELECT(Op, DAG);
19137 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19138 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19139 case ISD::VASTART: return LowerVASTART(Op, DAG);
19140 case ISD::VAARG: return LowerVAARG(Op, DAG);
19141 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19142 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19143 case ISD::INTRINSIC_VOID:
19144 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19145 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19146 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19147 case ISD::FRAME_TO_ARGS_OFFSET:
19148 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19149 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19150 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19151 case ISD::CLEANUPRET: return LowerCLEANUPRET(Op, DAG);
19152 case ISD::CATCHRET: return LowerCATCHRET(Op, DAG);
19153 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19154 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19155 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19156 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19157 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19158 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19159 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19160 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19161 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19162 case ISD::UMUL_LOHI:
19163 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19166 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19172 case ISD::UMULO: return LowerXALUO(Op, DAG);
19173 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19174 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19178 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19179 case ISD::ADD: return LowerADD(Op, DAG);
19180 case ISD::SUB: return LowerSUB(Op, DAG);
19184 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19185 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19186 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19187 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19188 case ISD::GC_TRANSITION_START:
19189 return LowerGC_TRANSITION_START(Op, DAG);
19190 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19194 /// ReplaceNodeResults - Replace a node with an illegal result type
19195 /// with a new node built out of custom code.
19196 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19197 SmallVectorImpl<SDValue>&Results,
19198 SelectionDAG &DAG) const {
19200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19201 switch (N->getOpcode()) {
19203 llvm_unreachable("Do not know how to custom type legalize this operation!");
19204 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19205 case X86ISD::FMINC:
19207 case X86ISD::FMAXC:
19208 case X86ISD::FMAX: {
19209 EVT VT = N->getValueType(0);
19210 if (VT != MVT::v2f32)
19211 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19212 SDValue UNDEF = DAG.getUNDEF(VT);
19213 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19214 N->getOperand(0), UNDEF);
19215 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19216 N->getOperand(1), UNDEF);
19217 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19220 case ISD::SIGN_EXTEND_INREG:
19225 // We don't want to expand or promote these.
19232 case ISD::UDIVREM: {
19233 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19234 Results.push_back(V);
19237 case ISD::FP_TO_SINT:
19238 case ISD::FP_TO_UINT: {
19239 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19241 std::pair<SDValue,SDValue> Vals =
19242 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19243 SDValue FIST = Vals.first, StackSlot = Vals.second;
19244 if (FIST.getNode()) {
19245 EVT VT = N->getValueType(0);
19246 // Return a load from the stack slot.
19247 if (StackSlot.getNode())
19248 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19249 MachinePointerInfo(),
19250 false, false, false, 0));
19252 Results.push_back(FIST);
19256 case ISD::UINT_TO_FP: {
19257 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19258 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19259 N->getValueType(0) != MVT::v2f32)
19261 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19263 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19265 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19266 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19267 DAG.getBitcast(MVT::v2i64, VBias));
19268 Or = DAG.getBitcast(MVT::v2f64, Or);
19269 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19270 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19273 case ISD::FP_ROUND: {
19274 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19276 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19277 Results.push_back(V);
19280 case ISD::FP_EXTEND: {
19281 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19282 // No other ValueType for FP_EXTEND should reach this point.
19283 assert(N->getValueType(0) == MVT::v2f32 &&
19284 "Do not know how to legalize this Node");
19287 case ISD::INTRINSIC_W_CHAIN: {
19288 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19290 default : llvm_unreachable("Do not know how to custom type "
19291 "legalize this intrinsic operation!");
19292 case Intrinsic::x86_rdtsc:
19293 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19295 case Intrinsic::x86_rdtscp:
19296 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19298 case Intrinsic::x86_rdpmc:
19299 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19302 case ISD::READCYCLECOUNTER: {
19303 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19306 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19307 EVT T = N->getValueType(0);
19308 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19309 bool Regs64bit = T == MVT::i128;
19310 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19311 SDValue cpInL, cpInH;
19312 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19313 DAG.getConstant(0, dl, HalfT));
19314 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19315 DAG.getConstant(1, dl, HalfT));
19316 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19317 Regs64bit ? X86::RAX : X86::EAX,
19319 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19320 Regs64bit ? X86::RDX : X86::EDX,
19321 cpInH, cpInL.getValue(1));
19322 SDValue swapInL, swapInH;
19323 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19324 DAG.getConstant(0, dl, HalfT));
19325 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19326 DAG.getConstant(1, dl, HalfT));
19327 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19328 Regs64bit ? X86::RBX : X86::EBX,
19329 swapInL, cpInH.getValue(1));
19330 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19331 Regs64bit ? X86::RCX : X86::ECX,
19332 swapInH, swapInL.getValue(1));
19333 SDValue Ops[] = { swapInH.getValue(0),
19335 swapInH.getValue(1) };
19336 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19337 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19338 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19339 X86ISD::LCMPXCHG8_DAG;
19340 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19341 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19342 Regs64bit ? X86::RAX : X86::EAX,
19343 HalfT, Result.getValue(1));
19344 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19345 Regs64bit ? X86::RDX : X86::EDX,
19346 HalfT, cpOutL.getValue(2));
19347 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19349 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19350 MVT::i32, cpOutH.getValue(2));
19352 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19353 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19354 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19356 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19357 Results.push_back(Success);
19358 Results.push_back(EFLAGS.getValue(1));
19361 case ISD::ATOMIC_SWAP:
19362 case ISD::ATOMIC_LOAD_ADD:
19363 case ISD::ATOMIC_LOAD_SUB:
19364 case ISD::ATOMIC_LOAD_AND:
19365 case ISD::ATOMIC_LOAD_OR:
19366 case ISD::ATOMIC_LOAD_XOR:
19367 case ISD::ATOMIC_LOAD_NAND:
19368 case ISD::ATOMIC_LOAD_MIN:
19369 case ISD::ATOMIC_LOAD_MAX:
19370 case ISD::ATOMIC_LOAD_UMIN:
19371 case ISD::ATOMIC_LOAD_UMAX:
19372 case ISD::ATOMIC_LOAD: {
19373 // Delegate to generic TypeLegalization. Situations we can really handle
19374 // should have already been dealt with by AtomicExpandPass.cpp.
19377 case ISD::BITCAST: {
19378 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19379 EVT DstVT = N->getValueType(0);
19380 EVT SrcVT = N->getOperand(0)->getValueType(0);
19382 if (SrcVT != MVT::f64 ||
19383 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19386 unsigned NumElts = DstVT.getVectorNumElements();
19387 EVT SVT = DstVT.getVectorElementType();
19388 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19389 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19390 MVT::v2f64, N->getOperand(0));
19391 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19393 if (ExperimentalVectorWideningLegalization) {
19394 // If we are legalizing vectors by widening, we already have the desired
19395 // legal vector type, just return it.
19396 Results.push_back(ToVecInt);
19400 SmallVector<SDValue, 8> Elts;
19401 for (unsigned i = 0, e = NumElts; i != e; ++i)
19402 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19403 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19405 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19410 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19411 switch ((X86ISD::NodeType)Opcode) {
19412 case X86ISD::FIRST_NUMBER: break;
19413 case X86ISD::BSF: return "X86ISD::BSF";
19414 case X86ISD::BSR: return "X86ISD::BSR";
19415 case X86ISD::SHLD: return "X86ISD::SHLD";
19416 case X86ISD::SHRD: return "X86ISD::SHRD";
19417 case X86ISD::FAND: return "X86ISD::FAND";
19418 case X86ISD::FANDN: return "X86ISD::FANDN";
19419 case X86ISD::FOR: return "X86ISD::FOR";
19420 case X86ISD::FXOR: return "X86ISD::FXOR";
19421 case X86ISD::FILD: return "X86ISD::FILD";
19422 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19423 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19424 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19425 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19426 case X86ISD::FLD: return "X86ISD::FLD";
19427 case X86ISD::FST: return "X86ISD::FST";
19428 case X86ISD::CALL: return "X86ISD::CALL";
19429 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19430 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19431 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19432 case X86ISD::BT: return "X86ISD::BT";
19433 case X86ISD::CMP: return "X86ISD::CMP";
19434 case X86ISD::COMI: return "X86ISD::COMI";
19435 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19436 case X86ISD::CMPM: return "X86ISD::CMPM";
19437 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19438 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19439 case X86ISD::SETCC: return "X86ISD::SETCC";
19440 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19441 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19442 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19443 case X86ISD::CMOV: return "X86ISD::CMOV";
19444 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19445 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19446 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19447 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19448 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19449 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19450 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19451 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19452 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19453 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19454 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19455 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19456 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19457 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19458 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19459 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19460 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19461 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19462 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19463 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19464 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19465 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19466 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19467 case X86ISD::HADD: return "X86ISD::HADD";
19468 case X86ISD::HSUB: return "X86ISD::HSUB";
19469 case X86ISD::FHADD: return "X86ISD::FHADD";
19470 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19471 case X86ISD::ABS: return "X86ISD::ABS";
19472 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19473 case X86ISD::FMAX: return "X86ISD::FMAX";
19474 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19475 case X86ISD::FMIN: return "X86ISD::FMIN";
19476 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19477 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19478 case X86ISD::FMINC: return "X86ISD::FMINC";
19479 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19480 case X86ISD::FRCP: return "X86ISD::FRCP";
19481 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19482 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19483 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19484 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19485 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19486 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19487 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19488 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19489 case X86ISD::CATCHRET: return "X86ISD::CATCHRET";
19490 case X86ISD::CLEANUPRET: return "X86ISD::CLEANUPRET";
19491 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19492 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19493 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19494 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19495 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19496 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19497 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19498 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19499 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19500 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19501 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19502 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19503 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19504 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19505 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19506 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19507 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19508 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19509 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19510 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19511 case X86ISD::VSHL: return "X86ISD::VSHL";
19512 case X86ISD::VSRL: return "X86ISD::VSRL";
19513 case X86ISD::VSRA: return "X86ISD::VSRA";
19514 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19515 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19516 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19517 case X86ISD::CMPP: return "X86ISD::CMPP";
19518 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19519 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19520 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19521 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19522 case X86ISD::ADD: return "X86ISD::ADD";
19523 case X86ISD::SUB: return "X86ISD::SUB";
19524 case X86ISD::ADC: return "X86ISD::ADC";
19525 case X86ISD::SBB: return "X86ISD::SBB";
19526 case X86ISD::SMUL: return "X86ISD::SMUL";
19527 case X86ISD::UMUL: return "X86ISD::UMUL";
19528 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19529 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19530 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19531 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19532 case X86ISD::INC: return "X86ISD::INC";
19533 case X86ISD::DEC: return "X86ISD::DEC";
19534 case X86ISD::OR: return "X86ISD::OR";
19535 case X86ISD::XOR: return "X86ISD::XOR";
19536 case X86ISD::AND: return "X86ISD::AND";
19537 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19538 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19539 case X86ISD::PTEST: return "X86ISD::PTEST";
19540 case X86ISD::TESTP: return "X86ISD::TESTP";
19541 case X86ISD::TESTM: return "X86ISD::TESTM";
19542 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19543 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19544 case X86ISD::KTEST: return "X86ISD::KTEST";
19545 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19546 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19547 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19548 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19549 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19550 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19551 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19552 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19553 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19554 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19555 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19556 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19557 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19558 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19559 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19560 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19561 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19562 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19563 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19564 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19565 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19566 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19567 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19568 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19569 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19570 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19571 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19572 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19573 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19574 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19575 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19576 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19577 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19578 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19579 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19580 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19581 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19582 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19583 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19584 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19585 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19586 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19587 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19588 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19589 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19590 case X86ISD::SAHF: return "X86ISD::SAHF";
19591 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19592 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19593 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19594 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19595 case X86ISD::FMADD: return "X86ISD::FMADD";
19596 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19597 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19598 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19599 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19600 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19601 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19602 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19603 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19604 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19605 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19606 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19607 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19608 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19609 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19610 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19611 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19612 case X86ISD::XTEST: return "X86ISD::XTEST";
19613 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19614 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19615 case X86ISD::SELECT: return "X86ISD::SELECT";
19616 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19617 case X86ISD::RCP28: return "X86ISD::RCP28";
19618 case X86ISD::EXP2: return "X86ISD::EXP2";
19619 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19620 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19621 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19622 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19623 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19624 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19625 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19626 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19627 case X86ISD::ADDS: return "X86ISD::ADDS";
19628 case X86ISD::SUBS: return "X86ISD::SUBS";
19629 case X86ISD::AVG: return "X86ISD::AVG";
19630 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19631 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19632 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19633 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19634 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19639 // isLegalAddressingMode - Return true if the addressing mode represented
19640 // by AM is legal for this target, for a load/store of the specified type.
19641 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19642 const AddrMode &AM, Type *Ty,
19643 unsigned AS) const {
19644 // X86 supports extremely general addressing modes.
19645 CodeModel::Model M = getTargetMachine().getCodeModel();
19646 Reloc::Model R = getTargetMachine().getRelocationModel();
19648 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19649 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19654 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19656 // If a reference to this global requires an extra load, we can't fold it.
19657 if (isGlobalStubReference(GVFlags))
19660 // If BaseGV requires a register for the PIC base, we cannot also have a
19661 // BaseReg specified.
19662 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19665 // If lower 4G is not available, then we must use rip-relative addressing.
19666 if ((M != CodeModel::Small || R != Reloc::Static) &&
19667 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19671 switch (AM.Scale) {
19677 // These scales always work.
19682 // These scales are formed with basereg+scalereg. Only accept if there is
19687 default: // Other stuff never works.
19694 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19695 unsigned Bits = Ty->getScalarSizeInBits();
19697 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19698 // particularly cheaper than those without.
19702 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19703 // variable shifts just as cheap as scalar ones.
19704 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19707 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19708 // fully general vector.
19712 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19713 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19715 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19716 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19717 return NumBits1 > NumBits2;
19720 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19721 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19724 if (!isTypeLegal(EVT::getEVT(Ty1)))
19727 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19729 // Assuming the caller doesn't have a zeroext or signext return parameter,
19730 // truncation all the way down to i1 is valid.
19734 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19735 return isInt<32>(Imm);
19738 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19739 // Can also use sub to handle negated immediates.
19740 return isInt<32>(Imm);
19743 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19744 if (!VT1.isInteger() || !VT2.isInteger())
19746 unsigned NumBits1 = VT1.getSizeInBits();
19747 unsigned NumBits2 = VT2.getSizeInBits();
19748 return NumBits1 > NumBits2;
19751 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19752 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19753 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19756 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19757 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19758 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19761 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19762 EVT VT1 = Val.getValueType();
19763 if (isZExtFree(VT1, VT2))
19766 if (Val.getOpcode() != ISD::LOAD)
19769 if (!VT1.isSimple() || !VT1.isInteger() ||
19770 !VT2.isSimple() || !VT2.isInteger())
19773 switch (VT1.getSimpleVT().SimpleTy) {
19778 // X86 has 8, 16, and 32-bit zero-extending loads.
19785 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
19788 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19789 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
19792 VT = VT.getScalarType();
19794 if (!VT.isSimple())
19797 switch (VT.getSimpleVT().SimpleTy) {
19808 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19809 // i16 instructions are longer (0x66 prefix) and potentially slower.
19810 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19813 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19814 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19815 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19816 /// are assumed to be legal.
19818 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19820 if (!VT.isSimple())
19823 // Not for i1 vectors
19824 if (VT.getScalarType() == MVT::i1)
19827 // Very little shuffling can be done for 64-bit vectors right now.
19828 if (VT.getSizeInBits() == 64)
19831 // We only care that the types being shuffled are legal. The lowering can
19832 // handle any possible shuffle mask that results.
19833 return isTypeLegal(VT.getSimpleVT());
19837 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19839 // Just delegate to the generic legality, clear masks aren't special.
19840 return isShuffleMaskLegal(Mask, VT);
19843 //===----------------------------------------------------------------------===//
19844 // X86 Scheduler Hooks
19845 //===----------------------------------------------------------------------===//
19847 /// Utility function to emit xbegin specifying the start of an RTM region.
19848 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19849 const TargetInstrInfo *TII) {
19850 DebugLoc DL = MI->getDebugLoc();
19852 const BasicBlock *BB = MBB->getBasicBlock();
19853 MachineFunction::iterator I = MBB;
19856 // For the v = xbegin(), we generate
19867 MachineBasicBlock *thisMBB = MBB;
19868 MachineFunction *MF = MBB->getParent();
19869 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19870 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19871 MF->insert(I, mainMBB);
19872 MF->insert(I, sinkMBB);
19874 // Transfer the remainder of BB and its successor edges to sinkMBB.
19875 sinkMBB->splice(sinkMBB->begin(), MBB,
19876 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19877 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19881 // # fallthrough to mainMBB
19882 // # abortion to sinkMBB
19883 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19884 thisMBB->addSuccessor(mainMBB);
19885 thisMBB->addSuccessor(sinkMBB);
19889 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19890 mainMBB->addSuccessor(sinkMBB);
19893 // EAX is live into the sinkMBB
19894 sinkMBB->addLiveIn(X86::EAX);
19895 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19896 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19899 MI->eraseFromParent();
19903 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19904 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19905 // in the .td file.
19906 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19907 const TargetInstrInfo *TII) {
19909 switch (MI->getOpcode()) {
19910 default: llvm_unreachable("illegal opcode!");
19911 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19912 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19913 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19914 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19915 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19916 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19917 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19918 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19921 DebugLoc dl = MI->getDebugLoc();
19922 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19924 unsigned NumArgs = MI->getNumOperands();
19925 for (unsigned i = 1; i < NumArgs; ++i) {
19926 MachineOperand &Op = MI->getOperand(i);
19927 if (!(Op.isReg() && Op.isImplicit()))
19928 MIB.addOperand(Op);
19930 if (MI->hasOneMemOperand())
19931 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19933 BuildMI(*BB, MI, dl,
19934 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19935 .addReg(X86::XMM0);
19937 MI->eraseFromParent();
19941 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19942 // defs in an instruction pattern
19943 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19944 const TargetInstrInfo *TII) {
19946 switch (MI->getOpcode()) {
19947 default: llvm_unreachable("illegal opcode!");
19948 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19949 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19950 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19951 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19952 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19953 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19954 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19955 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19958 DebugLoc dl = MI->getDebugLoc();
19959 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19961 unsigned NumArgs = MI->getNumOperands(); // remove the results
19962 for (unsigned i = 1; i < NumArgs; ++i) {
19963 MachineOperand &Op = MI->getOperand(i);
19964 if (!(Op.isReg() && Op.isImplicit()))
19965 MIB.addOperand(Op);
19967 if (MI->hasOneMemOperand())
19968 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19970 BuildMI(*BB, MI, dl,
19971 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19974 MI->eraseFromParent();
19978 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19979 const X86Subtarget *Subtarget) {
19980 DebugLoc dl = MI->getDebugLoc();
19981 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19982 // Address into RAX/EAX, other two args into ECX, EDX.
19983 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19984 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19985 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19986 for (int i = 0; i < X86::AddrNumOperands; ++i)
19987 MIB.addOperand(MI->getOperand(i));
19989 unsigned ValOps = X86::AddrNumOperands;
19990 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19991 .addReg(MI->getOperand(ValOps).getReg());
19992 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19993 .addReg(MI->getOperand(ValOps+1).getReg());
19995 // The instruction doesn't actually take any operands though.
19996 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19998 MI->eraseFromParent(); // The pseudo is gone now.
20002 MachineBasicBlock *
20003 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20004 MachineBasicBlock *MBB) const {
20005 // Emit va_arg instruction on X86-64.
20007 // Operands to this pseudo-instruction:
20008 // 0 ) Output : destination address (reg)
20009 // 1-5) Input : va_list address (addr, i64mem)
20010 // 6 ) ArgSize : Size (in bytes) of vararg type
20011 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20012 // 8 ) Align : Alignment of type
20013 // 9 ) EFLAGS (implicit-def)
20015 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20016 static_assert(X86::AddrNumOperands == 5,
20017 "VAARG_64 assumes 5 address operands");
20019 unsigned DestReg = MI->getOperand(0).getReg();
20020 MachineOperand &Base = MI->getOperand(1);
20021 MachineOperand &Scale = MI->getOperand(2);
20022 MachineOperand &Index = MI->getOperand(3);
20023 MachineOperand &Disp = MI->getOperand(4);
20024 MachineOperand &Segment = MI->getOperand(5);
20025 unsigned ArgSize = MI->getOperand(6).getImm();
20026 unsigned ArgMode = MI->getOperand(7).getImm();
20027 unsigned Align = MI->getOperand(8).getImm();
20029 // Memory Reference
20030 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20031 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20032 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20034 // Machine Information
20035 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20036 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20037 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20038 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20039 DebugLoc DL = MI->getDebugLoc();
20041 // struct va_list {
20044 // i64 overflow_area (address)
20045 // i64 reg_save_area (address)
20047 // sizeof(va_list) = 24
20048 // alignment(va_list) = 8
20050 unsigned TotalNumIntRegs = 6;
20051 unsigned TotalNumXMMRegs = 8;
20052 bool UseGPOffset = (ArgMode == 1);
20053 bool UseFPOffset = (ArgMode == 2);
20054 unsigned MaxOffset = TotalNumIntRegs * 8 +
20055 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20057 /* Align ArgSize to a multiple of 8 */
20058 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20059 bool NeedsAlign = (Align > 8);
20061 MachineBasicBlock *thisMBB = MBB;
20062 MachineBasicBlock *overflowMBB;
20063 MachineBasicBlock *offsetMBB;
20064 MachineBasicBlock *endMBB;
20066 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20067 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20068 unsigned OffsetReg = 0;
20070 if (!UseGPOffset && !UseFPOffset) {
20071 // If we only pull from the overflow region, we don't create a branch.
20072 // We don't need to alter control flow.
20073 OffsetDestReg = 0; // unused
20074 OverflowDestReg = DestReg;
20076 offsetMBB = nullptr;
20077 overflowMBB = thisMBB;
20080 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20081 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20082 // If not, pull from overflow_area. (branch to overflowMBB)
20087 // offsetMBB overflowMBB
20092 // Registers for the PHI in endMBB
20093 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20094 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20096 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20097 MachineFunction *MF = MBB->getParent();
20098 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20099 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20100 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20102 MachineFunction::iterator MBBIter = MBB;
20105 // Insert the new basic blocks
20106 MF->insert(MBBIter, offsetMBB);
20107 MF->insert(MBBIter, overflowMBB);
20108 MF->insert(MBBIter, endMBB);
20110 // Transfer the remainder of MBB and its successor edges to endMBB.
20111 endMBB->splice(endMBB->begin(), thisMBB,
20112 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20113 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20115 // Make offsetMBB and overflowMBB successors of thisMBB
20116 thisMBB->addSuccessor(offsetMBB);
20117 thisMBB->addSuccessor(overflowMBB);
20119 // endMBB is a successor of both offsetMBB and overflowMBB
20120 offsetMBB->addSuccessor(endMBB);
20121 overflowMBB->addSuccessor(endMBB);
20123 // Load the offset value into a register
20124 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20125 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20129 .addDisp(Disp, UseFPOffset ? 4 : 0)
20130 .addOperand(Segment)
20131 .setMemRefs(MMOBegin, MMOEnd);
20133 // Check if there is enough room left to pull this argument.
20134 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20136 .addImm(MaxOffset + 8 - ArgSizeA8);
20138 // Branch to "overflowMBB" if offset >= max
20139 // Fall through to "offsetMBB" otherwise
20140 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20141 .addMBB(overflowMBB);
20144 // In offsetMBB, emit code to use the reg_save_area.
20146 assert(OffsetReg != 0);
20148 // Read the reg_save_area address.
20149 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20150 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20155 .addOperand(Segment)
20156 .setMemRefs(MMOBegin, MMOEnd);
20158 // Zero-extend the offset
20159 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20160 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20163 .addImm(X86::sub_32bit);
20165 // Add the offset to the reg_save_area to get the final address.
20166 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20167 .addReg(OffsetReg64)
20168 .addReg(RegSaveReg);
20170 // Compute the offset for the next argument
20171 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20172 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20174 .addImm(UseFPOffset ? 16 : 8);
20176 // Store it back into the va_list.
20177 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20181 .addDisp(Disp, UseFPOffset ? 4 : 0)
20182 .addOperand(Segment)
20183 .addReg(NextOffsetReg)
20184 .setMemRefs(MMOBegin, MMOEnd);
20187 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20192 // Emit code to use overflow area
20195 // Load the overflow_area address into a register.
20196 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20197 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20202 .addOperand(Segment)
20203 .setMemRefs(MMOBegin, MMOEnd);
20205 // If we need to align it, do so. Otherwise, just copy the address
20206 // to OverflowDestReg.
20208 // Align the overflow address
20209 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20210 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20212 // aligned_addr = (addr + (align-1)) & ~(align-1)
20213 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20214 .addReg(OverflowAddrReg)
20217 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20219 .addImm(~(uint64_t)(Align-1));
20221 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20222 .addReg(OverflowAddrReg);
20225 // Compute the next overflow address after this argument.
20226 // (the overflow address should be kept 8-byte aligned)
20227 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20228 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20229 .addReg(OverflowDestReg)
20230 .addImm(ArgSizeA8);
20232 // Store the new overflow address.
20233 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20238 .addOperand(Segment)
20239 .addReg(NextAddrReg)
20240 .setMemRefs(MMOBegin, MMOEnd);
20242 // If we branched, emit the PHI to the front of endMBB.
20244 BuildMI(*endMBB, endMBB->begin(), DL,
20245 TII->get(X86::PHI), DestReg)
20246 .addReg(OffsetDestReg).addMBB(offsetMBB)
20247 .addReg(OverflowDestReg).addMBB(overflowMBB);
20250 // Erase the pseudo instruction
20251 MI->eraseFromParent();
20256 MachineBasicBlock *
20257 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20259 MachineBasicBlock *MBB) const {
20260 // Emit code to save XMM registers to the stack. The ABI says that the
20261 // number of registers to save is given in %al, so it's theoretically
20262 // possible to do an indirect jump trick to avoid saving all of them,
20263 // however this code takes a simpler approach and just executes all
20264 // of the stores if %al is non-zero. It's less code, and it's probably
20265 // easier on the hardware branch predictor, and stores aren't all that
20266 // expensive anyway.
20268 // Create the new basic blocks. One block contains all the XMM stores,
20269 // and one block is the final destination regardless of whether any
20270 // stores were performed.
20271 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20272 MachineFunction *F = MBB->getParent();
20273 MachineFunction::iterator MBBIter = MBB;
20275 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20276 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20277 F->insert(MBBIter, XMMSaveMBB);
20278 F->insert(MBBIter, EndMBB);
20280 // Transfer the remainder of MBB and its successor edges to EndMBB.
20281 EndMBB->splice(EndMBB->begin(), MBB,
20282 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20283 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20285 // The original block will now fall through to the XMM save block.
20286 MBB->addSuccessor(XMMSaveMBB);
20287 // The XMMSaveMBB will fall through to the end block.
20288 XMMSaveMBB->addSuccessor(EndMBB);
20290 // Now add the instructions.
20291 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20292 DebugLoc DL = MI->getDebugLoc();
20294 unsigned CountReg = MI->getOperand(0).getReg();
20295 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20296 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20298 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20299 // If %al is 0, branch around the XMM save block.
20300 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20301 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20302 MBB->addSuccessor(EndMBB);
20305 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20306 // that was just emitted, but clearly shouldn't be "saved".
20307 assert((MI->getNumOperands() <= 3 ||
20308 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20309 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20310 && "Expected last argument to be EFLAGS");
20311 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20312 // In the XMM save block, save all the XMM argument registers.
20313 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20314 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20315 MachineMemOperand *MMO = F->getMachineMemOperand(
20316 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20317 MachineMemOperand::MOStore,
20318 /*Size=*/16, /*Align=*/16);
20319 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20320 .addFrameIndex(RegSaveFrameIndex)
20321 .addImm(/*Scale=*/1)
20322 .addReg(/*IndexReg=*/0)
20323 .addImm(/*Disp=*/Offset)
20324 .addReg(/*Segment=*/0)
20325 .addReg(MI->getOperand(i).getReg())
20326 .addMemOperand(MMO);
20329 MI->eraseFromParent(); // The pseudo instruction is gone now.
20334 // The EFLAGS operand of SelectItr might be missing a kill marker
20335 // because there were multiple uses of EFLAGS, and ISel didn't know
20336 // which to mark. Figure out whether SelectItr should have had a
20337 // kill marker, and set it if it should. Returns the correct kill
20339 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20340 MachineBasicBlock* BB,
20341 const TargetRegisterInfo* TRI) {
20342 // Scan forward through BB for a use/def of EFLAGS.
20343 MachineBasicBlock::iterator miI(std::next(SelectItr));
20344 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20345 const MachineInstr& mi = *miI;
20346 if (mi.readsRegister(X86::EFLAGS))
20348 if (mi.definesRegister(X86::EFLAGS))
20349 break; // Should have kill-flag - update below.
20352 // If we hit the end of the block, check whether EFLAGS is live into a
20354 if (miI == BB->end()) {
20355 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20356 sEnd = BB->succ_end();
20357 sItr != sEnd; ++sItr) {
20358 MachineBasicBlock* succ = *sItr;
20359 if (succ->isLiveIn(X86::EFLAGS))
20364 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20365 // out. SelectMI should have a kill flag on EFLAGS.
20366 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20370 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20371 // together with other CMOV pseudo-opcodes into a single basic-block with
20372 // conditional jump around it.
20373 static bool isCMOVPseudo(MachineInstr *MI) {
20374 switch (MI->getOpcode()) {
20375 case X86::CMOV_FR32:
20376 case X86::CMOV_FR64:
20377 case X86::CMOV_GR8:
20378 case X86::CMOV_GR16:
20379 case X86::CMOV_GR32:
20380 case X86::CMOV_RFP32:
20381 case X86::CMOV_RFP64:
20382 case X86::CMOV_RFP80:
20383 case X86::CMOV_V2F64:
20384 case X86::CMOV_V2I64:
20385 case X86::CMOV_V4F32:
20386 case X86::CMOV_V4F64:
20387 case X86::CMOV_V4I64:
20388 case X86::CMOV_V16F32:
20389 case X86::CMOV_V8F32:
20390 case X86::CMOV_V8F64:
20391 case X86::CMOV_V8I64:
20392 case X86::CMOV_V8I1:
20393 case X86::CMOV_V16I1:
20394 case X86::CMOV_V32I1:
20395 case X86::CMOV_V64I1:
20403 MachineBasicBlock *
20404 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20405 MachineBasicBlock *BB) const {
20406 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20407 DebugLoc DL = MI->getDebugLoc();
20409 // To "insert" a SELECT_CC instruction, we actually have to insert the
20410 // diamond control-flow pattern. The incoming instruction knows the
20411 // destination vreg to set, the condition code register to branch on, the
20412 // true/false values to select between, and a branch opcode to use.
20413 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20414 MachineFunction::iterator It = BB;
20420 // cmpTY ccX, r1, r2
20422 // fallthrough --> copy0MBB
20423 MachineBasicBlock *thisMBB = BB;
20424 MachineFunction *F = BB->getParent();
20426 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20427 // as described above, by inserting a BB, and then making a PHI at the join
20428 // point to select the true and false operands of the CMOV in the PHI.
20430 // The code also handles two different cases of multiple CMOV opcodes
20434 // In this case, there are multiple CMOVs in a row, all which are based on
20435 // the same condition setting (or the exact opposite condition setting).
20436 // In this case we can lower all the CMOVs using a single inserted BB, and
20437 // then make a number of PHIs at the join point to model the CMOVs. The only
20438 // trickiness here, is that in a case like:
20440 // t2 = CMOV cond1 t1, f1
20441 // t3 = CMOV cond1 t2, f2
20443 // when rewriting this into PHIs, we have to perform some renaming on the
20444 // temps since you cannot have a PHI operand refer to a PHI result earlier
20445 // in the same block. The "simple" but wrong lowering would be:
20447 // t2 = PHI t1(BB1), f1(BB2)
20448 // t3 = PHI t2(BB1), f2(BB2)
20450 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20451 // renaming is to note that on the path through BB1, t2 is really just a
20452 // copy of t1, and do that renaming, properly generating:
20454 // t2 = PHI t1(BB1), f1(BB2)
20455 // t3 = PHI t1(BB1), f2(BB2)
20457 // Case 2, we lower cascaded CMOVs such as
20459 // (CMOV (CMOV F, T, cc1), T, cc2)
20461 // to two successives branches. For that, we look for another CMOV as the
20462 // following instruction.
20464 // Without this, we would add a PHI between the two jumps, which ends up
20465 // creating a few copies all around. For instance, for
20467 // (sitofp (zext (fcmp une)))
20469 // we would generate:
20471 // ucomiss %xmm1, %xmm0
20472 // movss <1.0f>, %xmm0
20473 // movaps %xmm0, %xmm1
20475 // xorps %xmm1, %xmm1
20478 // movaps %xmm1, %xmm0
20482 // because this custom-inserter would have generated:
20494 // A: X = ...; Y = ...
20496 // C: Z = PHI [X, A], [Y, B]
20498 // E: PHI [X, C], [Z, D]
20500 // If we lower both CMOVs in a single step, we can instead generate:
20512 // A: X = ...; Y = ...
20514 // E: PHI [X, A], [X, C], [Y, D]
20516 // Which, in our sitofp/fcmp example, gives us something like:
20518 // ucomiss %xmm1, %xmm0
20519 // movss <1.0f>, %xmm0
20522 // xorps %xmm0, %xmm0
20526 MachineInstr *CascadedCMOV = nullptr;
20527 MachineInstr *LastCMOV = MI;
20528 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20529 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20530 MachineBasicBlock::iterator NextMIIt =
20531 std::next(MachineBasicBlock::iterator(MI));
20533 // Check for case 1, where there are multiple CMOVs with the same condition
20534 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20535 // number of jumps the most.
20537 if (isCMOVPseudo(MI)) {
20538 // See if we have a string of CMOVS with the same condition.
20539 while (NextMIIt != BB->end() &&
20540 isCMOVPseudo(NextMIIt) &&
20541 (NextMIIt->getOperand(3).getImm() == CC ||
20542 NextMIIt->getOperand(3).getImm() == OppCC)) {
20543 LastCMOV = &*NextMIIt;
20548 // This checks for case 2, but only do this if we didn't already find
20549 // case 1, as indicated by LastCMOV == MI.
20550 if (LastCMOV == MI &&
20551 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20552 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20553 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20554 CascadedCMOV = &*NextMIIt;
20557 MachineBasicBlock *jcc1MBB = nullptr;
20559 // If we have a cascaded CMOV, we lower it to two successive branches to
20560 // the same block. EFLAGS is used by both, so mark it as live in the second.
20561 if (CascadedCMOV) {
20562 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20563 F->insert(It, jcc1MBB);
20564 jcc1MBB->addLiveIn(X86::EFLAGS);
20567 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20568 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20569 F->insert(It, copy0MBB);
20570 F->insert(It, sinkMBB);
20572 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20573 // live into the sink and copy blocks.
20574 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20576 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20577 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20578 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20579 copy0MBB->addLiveIn(X86::EFLAGS);
20580 sinkMBB->addLiveIn(X86::EFLAGS);
20583 // Transfer the remainder of BB and its successor edges to sinkMBB.
20584 sinkMBB->splice(sinkMBB->begin(), BB,
20585 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20586 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20588 // Add the true and fallthrough blocks as its successors.
20589 if (CascadedCMOV) {
20590 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20591 BB->addSuccessor(jcc1MBB);
20593 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20594 // jump to the sinkMBB.
20595 jcc1MBB->addSuccessor(copy0MBB);
20596 jcc1MBB->addSuccessor(sinkMBB);
20598 BB->addSuccessor(copy0MBB);
20601 // The true block target of the first (or only) branch is always sinkMBB.
20602 BB->addSuccessor(sinkMBB);
20604 // Create the conditional branch instruction.
20605 unsigned Opc = X86::GetCondBranchFromCond(CC);
20606 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20608 if (CascadedCMOV) {
20609 unsigned Opc2 = X86::GetCondBranchFromCond(
20610 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20611 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20615 // %FalseValue = ...
20616 // # fallthrough to sinkMBB
20617 copy0MBB->addSuccessor(sinkMBB);
20620 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20622 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20623 MachineBasicBlock::iterator MIItEnd =
20624 std::next(MachineBasicBlock::iterator(LastCMOV));
20625 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20626 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20627 MachineInstrBuilder MIB;
20629 // As we are creating the PHIs, we have to be careful if there is more than
20630 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20631 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20632 // That also means that PHI construction must work forward from earlier to
20633 // later, and that the code must maintain a mapping from earlier PHI's
20634 // destination registers, and the registers that went into the PHI.
20636 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20637 unsigned DestReg = MIIt->getOperand(0).getReg();
20638 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20639 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20641 // If this CMOV we are generating is the opposite condition from
20642 // the jump we generated, then we have to swap the operands for the
20643 // PHI that is going to be generated.
20644 if (MIIt->getOperand(3).getImm() == OppCC)
20645 std::swap(Op1Reg, Op2Reg);
20647 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20648 Op1Reg = RegRewriteTable[Op1Reg].first;
20650 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20651 Op2Reg = RegRewriteTable[Op2Reg].second;
20653 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20654 TII->get(X86::PHI), DestReg)
20655 .addReg(Op1Reg).addMBB(copy0MBB)
20656 .addReg(Op2Reg).addMBB(thisMBB);
20658 // Add this PHI to the rewrite table.
20659 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20662 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20663 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20664 if (CascadedCMOV) {
20665 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20666 // Copy the PHI result to the register defined by the second CMOV.
20667 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20668 DL, TII->get(TargetOpcode::COPY),
20669 CascadedCMOV->getOperand(0).getReg())
20670 .addReg(MI->getOperand(0).getReg());
20671 CascadedCMOV->eraseFromParent();
20674 // Now remove the CMOV(s).
20675 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20676 (MIIt++)->eraseFromParent();
20681 MachineBasicBlock *
20682 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20683 MachineBasicBlock *BB) const {
20684 // Combine the following atomic floating-point modification pattern:
20685 // a.store(reg OP a.load(acquire), release)
20686 // Transform them into:
20687 // OPss (%gpr), %xmm
20688 // movss %xmm, (%gpr)
20689 // Or sd equivalent for 64-bit operations.
20691 switch (MI->getOpcode()) {
20692 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20693 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20694 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20696 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20697 DebugLoc DL = MI->getDebugLoc();
20698 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20699 unsigned MSrc = MI->getOperand(0).getReg();
20700 unsigned VSrc = MI->getOperand(5).getReg();
20701 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20702 .addReg(/*Base=*/MSrc)
20703 .addImm(/*Scale=*/1)
20704 .addReg(/*Index=*/0)
20707 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20708 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20710 .addReg(/*Base=*/MSrc)
20711 .addImm(/*Scale=*/1)
20712 .addReg(/*Index=*/0)
20713 .addImm(/*Disp=*/0)
20714 .addReg(/*Segment=*/0);
20715 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20716 MI->eraseFromParent(); // The pseudo instruction is gone now.
20720 MachineBasicBlock *
20721 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20722 MachineBasicBlock *BB) const {
20723 MachineFunction *MF = BB->getParent();
20724 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20725 DebugLoc DL = MI->getDebugLoc();
20726 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20728 assert(MF->shouldSplitStack());
20730 const bool Is64Bit = Subtarget->is64Bit();
20731 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20733 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20734 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20737 // ... [Till the alloca]
20738 // If stacklet is not large enough, jump to mallocMBB
20741 // Allocate by subtracting from RSP
20742 // Jump to continueMBB
20745 // Allocate by call to runtime
20749 // [rest of original BB]
20752 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20753 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20754 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20756 MachineRegisterInfo &MRI = MF->getRegInfo();
20757 const TargetRegisterClass *AddrRegClass =
20758 getRegClassFor(getPointerTy(MF->getDataLayout()));
20760 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20761 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20762 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20763 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20764 sizeVReg = MI->getOperand(1).getReg(),
20765 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20767 MachineFunction::iterator MBBIter = BB;
20770 MF->insert(MBBIter, bumpMBB);
20771 MF->insert(MBBIter, mallocMBB);
20772 MF->insert(MBBIter, continueMBB);
20774 continueMBB->splice(continueMBB->begin(), BB,
20775 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20776 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20778 // Add code to the main basic block to check if the stack limit has been hit,
20779 // and if so, jump to mallocMBB otherwise to bumpMBB.
20780 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20781 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20782 .addReg(tmpSPVReg).addReg(sizeVReg);
20783 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20784 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20785 .addReg(SPLimitVReg);
20786 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20788 // bumpMBB simply decreases the stack pointer, since we know the current
20789 // stacklet has enough space.
20790 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20791 .addReg(SPLimitVReg);
20792 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20793 .addReg(SPLimitVReg);
20794 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20796 // Calls into a routine in libgcc to allocate more space from the heap.
20797 const uint32_t *RegMask =
20798 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
20800 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20802 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20803 .addExternalSymbol("__morestack_allocate_stack_space")
20804 .addRegMask(RegMask)
20805 .addReg(X86::RDI, RegState::Implicit)
20806 .addReg(X86::RAX, RegState::ImplicitDefine);
20807 } else if (Is64Bit) {
20808 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20810 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20811 .addExternalSymbol("__morestack_allocate_stack_space")
20812 .addRegMask(RegMask)
20813 .addReg(X86::EDI, RegState::Implicit)
20814 .addReg(X86::EAX, RegState::ImplicitDefine);
20816 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20818 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20819 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20820 .addExternalSymbol("__morestack_allocate_stack_space")
20821 .addRegMask(RegMask)
20822 .addReg(X86::EAX, RegState::ImplicitDefine);
20826 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20829 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20830 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20831 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20833 // Set up the CFG correctly.
20834 BB->addSuccessor(bumpMBB);
20835 BB->addSuccessor(mallocMBB);
20836 mallocMBB->addSuccessor(continueMBB);
20837 bumpMBB->addSuccessor(continueMBB);
20839 // Take care of the PHI nodes.
20840 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20841 MI->getOperand(0).getReg())
20842 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20843 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20845 // Delete the original pseudo instruction.
20846 MI->eraseFromParent();
20849 return continueMBB;
20852 MachineBasicBlock *
20853 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20854 MachineBasicBlock *BB) const {
20855 DebugLoc DL = MI->getDebugLoc();
20857 assert(!Subtarget->isTargetMachO());
20859 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
20862 MI->eraseFromParent(); // The pseudo instruction is gone now.
20866 MachineBasicBlock *
20867 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20868 MachineBasicBlock *BB) const {
20869 // This is pretty easy. We're taking the value that we received from
20870 // our load from the relocation, sticking it in either RDI (x86-64)
20871 // or EAX and doing an indirect call. The return value will then
20872 // be in the normal return register.
20873 MachineFunction *F = BB->getParent();
20874 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20875 DebugLoc DL = MI->getDebugLoc();
20877 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20878 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20880 // Get a register mask for the lowered call.
20881 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20882 // proper register mask.
20883 const uint32_t *RegMask =
20884 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
20885 if (Subtarget->is64Bit()) {
20886 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20887 TII->get(X86::MOV64rm), X86::RDI)
20889 .addImm(0).addReg(0)
20890 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20891 MI->getOperand(3).getTargetFlags())
20893 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20894 addDirectMem(MIB, X86::RDI);
20895 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20896 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20897 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20898 TII->get(X86::MOV32rm), X86::EAX)
20900 .addImm(0).addReg(0)
20901 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20902 MI->getOperand(3).getTargetFlags())
20904 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20905 addDirectMem(MIB, X86::EAX);
20906 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20908 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20909 TII->get(X86::MOV32rm), X86::EAX)
20910 .addReg(TII->getGlobalBaseReg(F))
20911 .addImm(0).addReg(0)
20912 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20913 MI->getOperand(3).getTargetFlags())
20915 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20916 addDirectMem(MIB, X86::EAX);
20917 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20920 MI->eraseFromParent(); // The pseudo instruction is gone now.
20924 MachineBasicBlock *
20925 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20926 MachineBasicBlock *MBB) const {
20927 DebugLoc DL = MI->getDebugLoc();
20928 MachineFunction *MF = MBB->getParent();
20929 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20930 MachineRegisterInfo &MRI = MF->getRegInfo();
20932 const BasicBlock *BB = MBB->getBasicBlock();
20933 MachineFunction::iterator I = MBB;
20936 // Memory Reference
20937 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20938 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20941 unsigned MemOpndSlot = 0;
20943 unsigned CurOp = 0;
20945 DstReg = MI->getOperand(CurOp++).getReg();
20946 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20947 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20948 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20949 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20951 MemOpndSlot = CurOp;
20953 MVT PVT = getPointerTy(MF->getDataLayout());
20954 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20955 "Invalid Pointer Size!");
20957 // For v = setjmp(buf), we generate
20960 // buf[LabelOffset] = restoreMBB
20961 // SjLjSetup restoreMBB
20967 // v = phi(main, restore)
20970 // if base pointer being used, load it from frame
20973 MachineBasicBlock *thisMBB = MBB;
20974 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20975 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20976 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20977 MF->insert(I, mainMBB);
20978 MF->insert(I, sinkMBB);
20979 MF->push_back(restoreMBB);
20981 MachineInstrBuilder MIB;
20983 // Transfer the remainder of BB and its successor edges to sinkMBB.
20984 sinkMBB->splice(sinkMBB->begin(), MBB,
20985 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20986 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20989 unsigned PtrStoreOpc = 0;
20990 unsigned LabelReg = 0;
20991 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20992 Reloc::Model RM = MF->getTarget().getRelocationModel();
20993 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20994 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20996 // Prepare IP either in reg or imm.
20997 if (!UseImmLabel) {
20998 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20999 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21000 LabelReg = MRI.createVirtualRegister(PtrRC);
21001 if (Subtarget->is64Bit()) {
21002 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21006 .addMBB(restoreMBB)
21009 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21010 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21011 .addReg(XII->getGlobalBaseReg(MF))
21014 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21018 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21020 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21021 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21022 if (i == X86::AddrDisp)
21023 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21025 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21028 MIB.addReg(LabelReg);
21030 MIB.addMBB(restoreMBB);
21031 MIB.setMemRefs(MMOBegin, MMOEnd);
21033 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21034 .addMBB(restoreMBB);
21036 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21037 MIB.addRegMask(RegInfo->getNoPreservedMask());
21038 thisMBB->addSuccessor(mainMBB);
21039 thisMBB->addSuccessor(restoreMBB);
21043 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21044 mainMBB->addSuccessor(sinkMBB);
21047 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21048 TII->get(X86::PHI), DstReg)
21049 .addReg(mainDstReg).addMBB(mainMBB)
21050 .addReg(restoreDstReg).addMBB(restoreMBB);
21053 if (RegInfo->hasBasePointer(*MF)) {
21054 const bool Uses64BitFramePtr =
21055 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21056 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21057 X86FI->setRestoreBasePointer(MF);
21058 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21059 unsigned BasePtr = RegInfo->getBaseRegister();
21060 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21061 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21062 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21063 .setMIFlag(MachineInstr::FrameSetup);
21065 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21066 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21067 restoreMBB->addSuccessor(sinkMBB);
21069 MI->eraseFromParent();
21073 MachineBasicBlock *
21074 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21075 MachineBasicBlock *MBB) const {
21076 DebugLoc DL = MI->getDebugLoc();
21077 MachineFunction *MF = MBB->getParent();
21078 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21079 MachineRegisterInfo &MRI = MF->getRegInfo();
21081 // Memory Reference
21082 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21083 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21085 MVT PVT = getPointerTy(MF->getDataLayout());
21086 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21087 "Invalid Pointer Size!");
21089 const TargetRegisterClass *RC =
21090 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21091 unsigned Tmp = MRI.createVirtualRegister(RC);
21092 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21093 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21094 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21095 unsigned SP = RegInfo->getStackRegister();
21097 MachineInstrBuilder MIB;
21099 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21100 const int64_t SPOffset = 2 * PVT.getStoreSize();
21102 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21103 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21106 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21107 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21108 MIB.addOperand(MI->getOperand(i));
21109 MIB.setMemRefs(MMOBegin, MMOEnd);
21111 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21112 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21113 if (i == X86::AddrDisp)
21114 MIB.addDisp(MI->getOperand(i), LabelOffset);
21116 MIB.addOperand(MI->getOperand(i));
21118 MIB.setMemRefs(MMOBegin, MMOEnd);
21120 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21121 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21122 if (i == X86::AddrDisp)
21123 MIB.addDisp(MI->getOperand(i), SPOffset);
21125 MIB.addOperand(MI->getOperand(i));
21127 MIB.setMemRefs(MMOBegin, MMOEnd);
21129 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21131 MI->eraseFromParent();
21135 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21136 // accumulator loops. Writing back to the accumulator allows the coalescer
21137 // to remove extra copies in the loop.
21138 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21139 MachineBasicBlock *
21140 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21141 MachineBasicBlock *MBB) const {
21142 MachineOperand &AddendOp = MI->getOperand(3);
21144 // Bail out early if the addend isn't a register - we can't switch these.
21145 if (!AddendOp.isReg())
21148 MachineFunction &MF = *MBB->getParent();
21149 MachineRegisterInfo &MRI = MF.getRegInfo();
21151 // Check whether the addend is defined by a PHI:
21152 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21153 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21154 if (!AddendDef.isPHI())
21157 // Look for the following pattern:
21159 // %addend = phi [%entry, 0], [%loop, %result]
21161 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21165 // %addend = phi [%entry, 0], [%loop, %result]
21167 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21169 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21170 assert(AddendDef.getOperand(i).isReg());
21171 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21172 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21173 if (&PHISrcInst == MI) {
21174 // Found a matching instruction.
21175 unsigned NewFMAOpc = 0;
21176 switch (MI->getOpcode()) {
21177 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21178 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21179 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21180 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21181 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21182 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21183 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21184 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21185 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21186 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21187 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21188 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21189 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21190 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21191 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21192 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21193 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21194 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21195 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21196 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21198 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21199 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21200 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21201 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21202 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21203 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21204 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21205 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21206 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21207 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21208 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21209 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21210 default: llvm_unreachable("Unrecognized FMA variant.");
21213 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21214 MachineInstrBuilder MIB =
21215 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21216 .addOperand(MI->getOperand(0))
21217 .addOperand(MI->getOperand(3))
21218 .addOperand(MI->getOperand(2))
21219 .addOperand(MI->getOperand(1));
21220 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21221 MI->eraseFromParent();
21228 MachineBasicBlock *
21229 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21230 MachineBasicBlock *BB) const {
21231 switch (MI->getOpcode()) {
21232 default: llvm_unreachable("Unexpected instr type to insert");
21233 case X86::TAILJMPd64:
21234 case X86::TAILJMPr64:
21235 case X86::TAILJMPm64:
21236 case X86::TAILJMPd64_REX:
21237 case X86::TAILJMPr64_REX:
21238 case X86::TAILJMPm64_REX:
21239 llvm_unreachable("TAILJMP64 would not be touched here.");
21240 case X86::TCRETURNdi64:
21241 case X86::TCRETURNri64:
21242 case X86::TCRETURNmi64:
21244 case X86::WIN_ALLOCA:
21245 return EmitLoweredWinAlloca(MI, BB);
21246 case X86::SEG_ALLOCA_32:
21247 case X86::SEG_ALLOCA_64:
21248 return EmitLoweredSegAlloca(MI, BB);
21249 case X86::TLSCall_32:
21250 case X86::TLSCall_64:
21251 return EmitLoweredTLSCall(MI, BB);
21252 case X86::CMOV_FR32:
21253 case X86::CMOV_FR64:
21254 case X86::CMOV_GR8:
21255 case X86::CMOV_GR16:
21256 case X86::CMOV_GR32:
21257 case X86::CMOV_RFP32:
21258 case X86::CMOV_RFP64:
21259 case X86::CMOV_RFP80:
21260 case X86::CMOV_V2F64:
21261 case X86::CMOV_V2I64:
21262 case X86::CMOV_V4F32:
21263 case X86::CMOV_V4F64:
21264 case X86::CMOV_V4I64:
21265 case X86::CMOV_V16F32:
21266 case X86::CMOV_V8F32:
21267 case X86::CMOV_V8F64:
21268 case X86::CMOV_V8I64:
21269 case X86::CMOV_V8I1:
21270 case X86::CMOV_V16I1:
21271 case X86::CMOV_V32I1:
21272 case X86::CMOV_V64I1:
21273 return EmitLoweredSelect(MI, BB);
21275 case X86::RELEASE_FADD32mr:
21276 case X86::RELEASE_FADD64mr:
21277 return EmitLoweredAtomicFP(MI, BB);
21279 case X86::FP32_TO_INT16_IN_MEM:
21280 case X86::FP32_TO_INT32_IN_MEM:
21281 case X86::FP32_TO_INT64_IN_MEM:
21282 case X86::FP64_TO_INT16_IN_MEM:
21283 case X86::FP64_TO_INT32_IN_MEM:
21284 case X86::FP64_TO_INT64_IN_MEM:
21285 case X86::FP80_TO_INT16_IN_MEM:
21286 case X86::FP80_TO_INT32_IN_MEM:
21287 case X86::FP80_TO_INT64_IN_MEM: {
21288 MachineFunction *F = BB->getParent();
21289 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21290 DebugLoc DL = MI->getDebugLoc();
21292 // Change the floating point control register to use "round towards zero"
21293 // mode when truncating to an integer value.
21294 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21295 addFrameReference(BuildMI(*BB, MI, DL,
21296 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21298 // Load the old value of the high byte of the control word...
21300 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21301 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21304 // Set the high part to be round to zero...
21305 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21308 // Reload the modified control word now...
21309 addFrameReference(BuildMI(*BB, MI, DL,
21310 TII->get(X86::FLDCW16m)), CWFrameIdx);
21312 // Restore the memory image of control word to original value
21313 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21316 // Get the X86 opcode to use.
21318 switch (MI->getOpcode()) {
21319 default: llvm_unreachable("illegal opcode!");
21320 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21321 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21322 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21323 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21324 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21325 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21326 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21327 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21328 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21332 MachineOperand &Op = MI->getOperand(0);
21334 AM.BaseType = X86AddressMode::RegBase;
21335 AM.Base.Reg = Op.getReg();
21337 AM.BaseType = X86AddressMode::FrameIndexBase;
21338 AM.Base.FrameIndex = Op.getIndex();
21340 Op = MI->getOperand(1);
21342 AM.Scale = Op.getImm();
21343 Op = MI->getOperand(2);
21345 AM.IndexReg = Op.getImm();
21346 Op = MI->getOperand(3);
21347 if (Op.isGlobal()) {
21348 AM.GV = Op.getGlobal();
21350 AM.Disp = Op.getImm();
21352 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21353 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21355 // Reload the original control word now.
21356 addFrameReference(BuildMI(*BB, MI, DL,
21357 TII->get(X86::FLDCW16m)), CWFrameIdx);
21359 MI->eraseFromParent(); // The pseudo instruction is gone now.
21362 // String/text processing lowering.
21363 case X86::PCMPISTRM128REG:
21364 case X86::VPCMPISTRM128REG:
21365 case X86::PCMPISTRM128MEM:
21366 case X86::VPCMPISTRM128MEM:
21367 case X86::PCMPESTRM128REG:
21368 case X86::VPCMPESTRM128REG:
21369 case X86::PCMPESTRM128MEM:
21370 case X86::VPCMPESTRM128MEM:
21371 assert(Subtarget->hasSSE42() &&
21372 "Target must have SSE4.2 or AVX features enabled");
21373 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21375 // String/text processing lowering.
21376 case X86::PCMPISTRIREG:
21377 case X86::VPCMPISTRIREG:
21378 case X86::PCMPISTRIMEM:
21379 case X86::VPCMPISTRIMEM:
21380 case X86::PCMPESTRIREG:
21381 case X86::VPCMPESTRIREG:
21382 case X86::PCMPESTRIMEM:
21383 case X86::VPCMPESTRIMEM:
21384 assert(Subtarget->hasSSE42() &&
21385 "Target must have SSE4.2 or AVX features enabled");
21386 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21388 // Thread synchronization.
21390 return EmitMonitor(MI, BB, Subtarget);
21394 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21396 case X86::VASTART_SAVE_XMM_REGS:
21397 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21399 case X86::VAARG_64:
21400 return EmitVAARG64WithCustomInserter(MI, BB);
21402 case X86::EH_SjLj_SetJmp32:
21403 case X86::EH_SjLj_SetJmp64:
21404 return emitEHSjLjSetJmp(MI, BB);
21406 case X86::EH_SjLj_LongJmp32:
21407 case X86::EH_SjLj_LongJmp64:
21408 return emitEHSjLjLongJmp(MI, BB);
21410 case TargetOpcode::STATEPOINT:
21411 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21412 // this point in the process. We diverge later.
21413 return emitPatchPoint(MI, BB);
21415 case TargetOpcode::STACKMAP:
21416 case TargetOpcode::PATCHPOINT:
21417 return emitPatchPoint(MI, BB);
21419 case X86::VFMADDPDr213r:
21420 case X86::VFMADDPSr213r:
21421 case X86::VFMADDSDr213r:
21422 case X86::VFMADDSSr213r:
21423 case X86::VFMSUBPDr213r:
21424 case X86::VFMSUBPSr213r:
21425 case X86::VFMSUBSDr213r:
21426 case X86::VFMSUBSSr213r:
21427 case X86::VFNMADDPDr213r:
21428 case X86::VFNMADDPSr213r:
21429 case X86::VFNMADDSDr213r:
21430 case X86::VFNMADDSSr213r:
21431 case X86::VFNMSUBPDr213r:
21432 case X86::VFNMSUBPSr213r:
21433 case X86::VFNMSUBSDr213r:
21434 case X86::VFNMSUBSSr213r:
21435 case X86::VFMADDSUBPDr213r:
21436 case X86::VFMADDSUBPSr213r:
21437 case X86::VFMSUBADDPDr213r:
21438 case X86::VFMSUBADDPSr213r:
21439 case X86::VFMADDPDr213rY:
21440 case X86::VFMADDPSr213rY:
21441 case X86::VFMSUBPDr213rY:
21442 case X86::VFMSUBPSr213rY:
21443 case X86::VFNMADDPDr213rY:
21444 case X86::VFNMADDPSr213rY:
21445 case X86::VFNMSUBPDr213rY:
21446 case X86::VFNMSUBPSr213rY:
21447 case X86::VFMADDSUBPDr213rY:
21448 case X86::VFMADDSUBPSr213rY:
21449 case X86::VFMSUBADDPDr213rY:
21450 case X86::VFMSUBADDPSr213rY:
21451 return emitFMA3Instr(MI, BB);
21455 //===----------------------------------------------------------------------===//
21456 // X86 Optimization Hooks
21457 //===----------------------------------------------------------------------===//
21459 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21462 const SelectionDAG &DAG,
21463 unsigned Depth) const {
21464 unsigned BitWidth = KnownZero.getBitWidth();
21465 unsigned Opc = Op.getOpcode();
21466 assert((Opc >= ISD::BUILTIN_OP_END ||
21467 Opc == ISD::INTRINSIC_WO_CHAIN ||
21468 Opc == ISD::INTRINSIC_W_CHAIN ||
21469 Opc == ISD::INTRINSIC_VOID) &&
21470 "Should use MaskedValueIsZero if you don't know whether Op"
21471 " is a target node!");
21473 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21487 // These nodes' second result is a boolean.
21488 if (Op.getResNo() == 0)
21491 case X86ISD::SETCC:
21492 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21494 case ISD::INTRINSIC_WO_CHAIN: {
21495 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21496 unsigned NumLoBits = 0;
21499 case Intrinsic::x86_sse_movmsk_ps:
21500 case Intrinsic::x86_avx_movmsk_ps_256:
21501 case Intrinsic::x86_sse2_movmsk_pd:
21502 case Intrinsic::x86_avx_movmsk_pd_256:
21503 case Intrinsic::x86_mmx_pmovmskb:
21504 case Intrinsic::x86_sse2_pmovmskb_128:
21505 case Intrinsic::x86_avx2_pmovmskb: {
21506 // High bits of movmskp{s|d}, pmovmskb are known zero.
21508 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21509 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21510 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21511 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21512 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21513 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21514 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21515 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21517 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21526 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21528 const SelectionDAG &,
21529 unsigned Depth) const {
21530 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21531 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21532 return Op.getValueType().getScalarType().getSizeInBits();
21538 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21539 /// node is a GlobalAddress + offset.
21540 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21541 const GlobalValue* &GA,
21542 int64_t &Offset) const {
21543 if (N->getOpcode() == X86ISD::Wrapper) {
21544 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21545 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21546 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21550 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21553 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21554 /// same as extracting the high 128-bit part of 256-bit vector and then
21555 /// inserting the result into the low part of a new 256-bit vector
21556 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21557 EVT VT = SVOp->getValueType(0);
21558 unsigned NumElems = VT.getVectorNumElements();
21560 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21561 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21562 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21563 SVOp->getMaskElt(j) >= 0)
21569 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21570 /// same as extracting the low 128-bit part of 256-bit vector and then
21571 /// inserting the result into the high part of a new 256-bit vector
21572 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21573 EVT VT = SVOp->getValueType(0);
21574 unsigned NumElems = VT.getVectorNumElements();
21576 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21577 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21578 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21579 SVOp->getMaskElt(j) >= 0)
21585 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21586 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21587 TargetLowering::DAGCombinerInfo &DCI,
21588 const X86Subtarget* Subtarget) {
21590 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21591 SDValue V1 = SVOp->getOperand(0);
21592 SDValue V2 = SVOp->getOperand(1);
21593 EVT VT = SVOp->getValueType(0);
21594 unsigned NumElems = VT.getVectorNumElements();
21596 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21597 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21601 // V UNDEF BUILD_VECTOR UNDEF
21603 // CONCAT_VECTOR CONCAT_VECTOR
21606 // RESULT: V + zero extended
21608 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21609 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21610 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21613 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21616 // To match the shuffle mask, the first half of the mask should
21617 // be exactly the first vector, and all the rest a splat with the
21618 // first element of the second one.
21619 for (unsigned i = 0; i != NumElems/2; ++i)
21620 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21621 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21624 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21625 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21626 if (Ld->hasNUsesOfValue(1, 0)) {
21627 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21628 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21630 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21632 Ld->getPointerInfo(),
21633 Ld->getAlignment(),
21634 false/*isVolatile*/, true/*ReadMem*/,
21635 false/*WriteMem*/);
21637 // Make sure the newly-created LOAD is in the same position as Ld in
21638 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21639 // and update uses of Ld's output chain to use the TokenFactor.
21640 if (Ld->hasAnyUseOfValue(1)) {
21641 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21642 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21643 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21644 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21645 SDValue(ResNode.getNode(), 1));
21648 return DAG.getBitcast(VT, ResNode);
21652 // Emit a zeroed vector and insert the desired subvector on its
21654 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21655 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21656 return DCI.CombineTo(N, InsV);
21659 //===--------------------------------------------------------------------===//
21660 // Combine some shuffles into subvector extracts and inserts:
21663 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21664 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21665 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21666 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21667 return DCI.CombineTo(N, InsV);
21670 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21671 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21672 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21673 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21674 return DCI.CombineTo(N, InsV);
21680 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21683 /// This is the leaf of the recursive combinine below. When we have found some
21684 /// chain of single-use x86 shuffle instructions and accumulated the combined
21685 /// shuffle mask represented by them, this will try to pattern match that mask
21686 /// into either a single instruction if there is a special purpose instruction
21687 /// for this operation, or into a PSHUFB instruction which is a fully general
21688 /// instruction but should only be used to replace chains over a certain depth.
21689 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21690 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21691 TargetLowering::DAGCombinerInfo &DCI,
21692 const X86Subtarget *Subtarget) {
21693 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21695 // Find the operand that enters the chain. Note that multiple uses are OK
21696 // here, we're not going to remove the operand we find.
21697 SDValue Input = Op.getOperand(0);
21698 while (Input.getOpcode() == ISD::BITCAST)
21699 Input = Input.getOperand(0);
21701 MVT VT = Input.getSimpleValueType();
21702 MVT RootVT = Root.getSimpleValueType();
21705 // Just remove no-op shuffle masks.
21706 if (Mask.size() == 1) {
21707 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21712 // Use the float domain if the operand type is a floating point type.
21713 bool FloatDomain = VT.isFloatingPoint();
21715 // For floating point shuffles, we don't have free copies in the shuffle
21716 // instructions or the ability to load as part of the instruction, so
21717 // canonicalize their shuffles to UNPCK or MOV variants.
21719 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21720 // vectors because it can have a load folded into it that UNPCK cannot. This
21721 // doesn't preclude something switching to the shorter encoding post-RA.
21723 // FIXME: Should teach these routines about AVX vector widths.
21724 if (FloatDomain && VT.getSizeInBits() == 128) {
21725 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21726 bool Lo = Mask.equals({0, 0});
21729 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21730 // is no slower than UNPCKLPD but has the option to fold the input operand
21731 // into even an unaligned memory load.
21732 if (Lo && Subtarget->hasSSE3()) {
21733 Shuffle = X86ISD::MOVDDUP;
21734 ShuffleVT = MVT::v2f64;
21736 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21737 // than the UNPCK variants.
21738 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21739 ShuffleVT = MVT::v4f32;
21741 if (Depth == 1 && Root->getOpcode() == Shuffle)
21742 return false; // Nothing to do!
21743 Op = DAG.getBitcast(ShuffleVT, Input);
21744 DCI.AddToWorklist(Op.getNode());
21745 if (Shuffle == X86ISD::MOVDDUP)
21746 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21748 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21749 DCI.AddToWorklist(Op.getNode());
21750 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21754 if (Subtarget->hasSSE3() &&
21755 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
21756 bool Lo = Mask.equals({0, 0, 2, 2});
21757 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21758 MVT ShuffleVT = MVT::v4f32;
21759 if (Depth == 1 && Root->getOpcode() == Shuffle)
21760 return false; // Nothing to do!
21761 Op = DAG.getBitcast(ShuffleVT, Input);
21762 DCI.AddToWorklist(Op.getNode());
21763 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21764 DCI.AddToWorklist(Op.getNode());
21765 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21769 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
21770 bool Lo = Mask.equals({0, 0, 1, 1});
21771 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21772 MVT ShuffleVT = MVT::v4f32;
21773 if (Depth == 1 && Root->getOpcode() == Shuffle)
21774 return false; // Nothing to do!
21775 Op = DAG.getBitcast(ShuffleVT, Input);
21776 DCI.AddToWorklist(Op.getNode());
21777 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21778 DCI.AddToWorklist(Op.getNode());
21779 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21785 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21786 // variants as none of these have single-instruction variants that are
21787 // superior to the UNPCK formulation.
21788 if (!FloatDomain && VT.getSizeInBits() == 128 &&
21789 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21790 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
21791 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
21793 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
21794 bool Lo = Mask[0] == 0;
21795 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21796 if (Depth == 1 && Root->getOpcode() == Shuffle)
21797 return false; // Nothing to do!
21799 switch (Mask.size()) {
21801 ShuffleVT = MVT::v8i16;
21804 ShuffleVT = MVT::v16i8;
21807 llvm_unreachable("Impossible mask size!");
21809 Op = DAG.getBitcast(ShuffleVT, Input);
21810 DCI.AddToWorklist(Op.getNode());
21811 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21812 DCI.AddToWorklist(Op.getNode());
21813 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21818 // Don't try to re-form single instruction chains under any circumstances now
21819 // that we've done encoding canonicalization for them.
21823 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21824 // can replace them with a single PSHUFB instruction profitably. Intel's
21825 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21826 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21827 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21828 SmallVector<SDValue, 16> PSHUFBMask;
21829 int NumBytes = VT.getSizeInBits() / 8;
21830 int Ratio = NumBytes / Mask.size();
21831 for (int i = 0; i < NumBytes; ++i) {
21832 if (Mask[i / Ratio] == SM_SentinelUndef) {
21833 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21836 int M = Mask[i / Ratio] != SM_SentinelZero
21837 ? Ratio * Mask[i / Ratio] + i % Ratio
21839 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
21841 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
21842 Op = DAG.getBitcast(ByteVT, Input);
21843 DCI.AddToWorklist(Op.getNode());
21844 SDValue PSHUFBMaskOp =
21845 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
21846 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21847 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
21848 DCI.AddToWorklist(Op.getNode());
21849 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21854 // Failed to find any combines.
21858 /// \brief Fully generic combining of x86 shuffle instructions.
21860 /// This should be the last combine run over the x86 shuffle instructions. Once
21861 /// they have been fully optimized, this will recursively consider all chains
21862 /// of single-use shuffle instructions, build a generic model of the cumulative
21863 /// shuffle operation, and check for simpler instructions which implement this
21864 /// operation. We use this primarily for two purposes:
21866 /// 1) Collapse generic shuffles to specialized single instructions when
21867 /// equivalent. In most cases, this is just an encoding size win, but
21868 /// sometimes we will collapse multiple generic shuffles into a single
21869 /// special-purpose shuffle.
21870 /// 2) Look for sequences of shuffle instructions with 3 or more total
21871 /// instructions, and replace them with the slightly more expensive SSSE3
21872 /// PSHUFB instruction if available. We do this as the last combining step
21873 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21874 /// a suitable short sequence of other instructions. The PHUFB will either
21875 /// use a register or have to read from memory and so is slightly (but only
21876 /// slightly) more expensive than the other shuffle instructions.
21878 /// Because this is inherently a quadratic operation (for each shuffle in
21879 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21880 /// This should never be an issue in practice as the shuffle lowering doesn't
21881 /// produce sequences of more than 8 instructions.
21883 /// FIXME: We will currently miss some cases where the redundant shuffling
21884 /// would simplify under the threshold for PSHUFB formation because of
21885 /// combine-ordering. To fix this, we should do the redundant instruction
21886 /// combining in this recursive walk.
21887 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21888 ArrayRef<int> RootMask,
21889 int Depth, bool HasPSHUFB,
21891 TargetLowering::DAGCombinerInfo &DCI,
21892 const X86Subtarget *Subtarget) {
21893 // Bound the depth of our recursive combine because this is ultimately
21894 // quadratic in nature.
21898 // Directly rip through bitcasts to find the underlying operand.
21899 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21900 Op = Op.getOperand(0);
21902 MVT VT = Op.getSimpleValueType();
21903 if (!VT.isVector())
21904 return false; // Bail if we hit a non-vector.
21906 assert(Root.getSimpleValueType().isVector() &&
21907 "Shuffles operate on vector types!");
21908 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21909 "Can only combine shuffles of the same vector register size.");
21911 if (!isTargetShuffle(Op.getOpcode()))
21913 SmallVector<int, 16> OpMask;
21915 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21916 // We only can combine unary shuffles which we can decode the mask for.
21917 if (!HaveMask || !IsUnary)
21920 assert(VT.getVectorNumElements() == OpMask.size() &&
21921 "Different mask size from vector size!");
21922 assert(((RootMask.size() > OpMask.size() &&
21923 RootMask.size() % OpMask.size() == 0) ||
21924 (OpMask.size() > RootMask.size() &&
21925 OpMask.size() % RootMask.size() == 0) ||
21926 OpMask.size() == RootMask.size()) &&
21927 "The smaller number of elements must divide the larger.");
21928 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21929 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21930 assert(((RootRatio == 1 && OpRatio == 1) ||
21931 (RootRatio == 1) != (OpRatio == 1)) &&
21932 "Must not have a ratio for both incoming and op masks!");
21934 SmallVector<int, 16> Mask;
21935 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21937 // Merge this shuffle operation's mask into our accumulated mask. Note that
21938 // this shuffle's mask will be the first applied to the input, followed by the
21939 // root mask to get us all the way to the root value arrangement. The reason
21940 // for this order is that we are recursing up the operation chain.
21941 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21942 int RootIdx = i / RootRatio;
21943 if (RootMask[RootIdx] < 0) {
21944 // This is a zero or undef lane, we're done.
21945 Mask.push_back(RootMask[RootIdx]);
21949 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21950 int OpIdx = RootMaskedIdx / OpRatio;
21951 if (OpMask[OpIdx] < 0) {
21952 // The incoming lanes are zero or undef, it doesn't matter which ones we
21954 Mask.push_back(OpMask[OpIdx]);
21958 // Ok, we have non-zero lanes, map them through.
21959 Mask.push_back(OpMask[OpIdx] * OpRatio +
21960 RootMaskedIdx % OpRatio);
21963 // See if we can recurse into the operand to combine more things.
21964 switch (Op.getOpcode()) {
21965 case X86ISD::PSHUFB:
21967 case X86ISD::PSHUFD:
21968 case X86ISD::PSHUFHW:
21969 case X86ISD::PSHUFLW:
21970 if (Op.getOperand(0).hasOneUse() &&
21971 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21972 HasPSHUFB, DAG, DCI, Subtarget))
21976 case X86ISD::UNPCKL:
21977 case X86ISD::UNPCKH:
21978 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21979 // We can't check for single use, we have to check that this shuffle is the only user.
21980 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21981 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21982 HasPSHUFB, DAG, DCI, Subtarget))
21987 // Minor canonicalization of the accumulated shuffle mask to make it easier
21988 // to match below. All this does is detect masks with squential pairs of
21989 // elements, and shrink them to the half-width mask. It does this in a loop
21990 // so it will reduce the size of the mask to the minimal width mask which
21991 // performs an equivalent shuffle.
21992 SmallVector<int, 16> WidenedMask;
21993 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21994 Mask = std::move(WidenedMask);
21995 WidenedMask.clear();
21998 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22002 /// \brief Get the PSHUF-style mask from PSHUF node.
22004 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22005 /// PSHUF-style masks that can be reused with such instructions.
22006 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22007 MVT VT = N.getSimpleValueType();
22008 SmallVector<int, 4> Mask;
22010 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22014 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22015 // matter. Check that the upper masks are repeats and remove them.
22016 if (VT.getSizeInBits() > 128) {
22017 int LaneElts = 128 / VT.getScalarSizeInBits();
22019 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22020 for (int j = 0; j < LaneElts; ++j)
22021 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22022 "Mask doesn't repeat in high 128-bit lanes!");
22024 Mask.resize(LaneElts);
22027 switch (N.getOpcode()) {
22028 case X86ISD::PSHUFD:
22030 case X86ISD::PSHUFLW:
22033 case X86ISD::PSHUFHW:
22034 Mask.erase(Mask.begin(), Mask.begin() + 4);
22035 for (int &M : Mask)
22039 llvm_unreachable("No valid shuffle instruction found!");
22043 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22045 /// We walk up the chain and look for a combinable shuffle, skipping over
22046 /// shuffles that we could hoist this shuffle's transformation past without
22047 /// altering anything.
22049 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22051 TargetLowering::DAGCombinerInfo &DCI) {
22052 assert(N.getOpcode() == X86ISD::PSHUFD &&
22053 "Called with something other than an x86 128-bit half shuffle!");
22056 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22057 // of the shuffles in the chain so that we can form a fresh chain to replace
22059 SmallVector<SDValue, 8> Chain;
22060 SDValue V = N.getOperand(0);
22061 for (; V.hasOneUse(); V = V.getOperand(0)) {
22062 switch (V.getOpcode()) {
22064 return SDValue(); // Nothing combined!
22067 // Skip bitcasts as we always know the type for the target specific
22071 case X86ISD::PSHUFD:
22072 // Found another dword shuffle.
22075 case X86ISD::PSHUFLW:
22076 // Check that the low words (being shuffled) are the identity in the
22077 // dword shuffle, and the high words are self-contained.
22078 if (Mask[0] != 0 || Mask[1] != 1 ||
22079 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22082 Chain.push_back(V);
22085 case X86ISD::PSHUFHW:
22086 // Check that the high words (being shuffled) are the identity in the
22087 // dword shuffle, and the low words are self-contained.
22088 if (Mask[2] != 2 || Mask[3] != 3 ||
22089 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22092 Chain.push_back(V);
22095 case X86ISD::UNPCKL:
22096 case X86ISD::UNPCKH:
22097 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22098 // shuffle into a preceding word shuffle.
22099 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22100 V.getSimpleValueType().getScalarType() != MVT::i16)
22103 // Search for a half-shuffle which we can combine with.
22104 unsigned CombineOp =
22105 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22106 if (V.getOperand(0) != V.getOperand(1) ||
22107 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22109 Chain.push_back(V);
22110 V = V.getOperand(0);
22112 switch (V.getOpcode()) {
22114 return SDValue(); // Nothing to combine.
22116 case X86ISD::PSHUFLW:
22117 case X86ISD::PSHUFHW:
22118 if (V.getOpcode() == CombineOp)
22121 Chain.push_back(V);
22125 V = V.getOperand(0);
22129 } while (V.hasOneUse());
22132 // Break out of the loop if we break out of the switch.
22136 if (!V.hasOneUse())
22137 // We fell out of the loop without finding a viable combining instruction.
22140 // Merge this node's mask and our incoming mask.
22141 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22142 for (int &M : Mask)
22144 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22145 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22147 // Rebuild the chain around this new shuffle.
22148 while (!Chain.empty()) {
22149 SDValue W = Chain.pop_back_val();
22151 if (V.getValueType() != W.getOperand(0).getValueType())
22152 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22154 switch (W.getOpcode()) {
22156 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22158 case X86ISD::UNPCKL:
22159 case X86ISD::UNPCKH:
22160 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22163 case X86ISD::PSHUFD:
22164 case X86ISD::PSHUFLW:
22165 case X86ISD::PSHUFHW:
22166 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22170 if (V.getValueType() != N.getValueType())
22171 V = DAG.getBitcast(N.getValueType(), V);
22173 // Return the new chain to replace N.
22177 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22179 /// We walk up the chain, skipping shuffles of the other half and looking
22180 /// through shuffles which switch halves trying to find a shuffle of the same
22181 /// pair of dwords.
22182 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22184 TargetLowering::DAGCombinerInfo &DCI) {
22186 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22187 "Called with something other than an x86 128-bit half shuffle!");
22189 unsigned CombineOpcode = N.getOpcode();
22191 // Walk up a single-use chain looking for a combinable shuffle.
22192 SDValue V = N.getOperand(0);
22193 for (; V.hasOneUse(); V = V.getOperand(0)) {
22194 switch (V.getOpcode()) {
22196 return false; // Nothing combined!
22199 // Skip bitcasts as we always know the type for the target specific
22203 case X86ISD::PSHUFLW:
22204 case X86ISD::PSHUFHW:
22205 if (V.getOpcode() == CombineOpcode)
22208 // Other-half shuffles are no-ops.
22211 // Break out of the loop if we break out of the switch.
22215 if (!V.hasOneUse())
22216 // We fell out of the loop without finding a viable combining instruction.
22219 // Combine away the bottom node as its shuffle will be accumulated into
22220 // a preceding shuffle.
22221 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22223 // Record the old value.
22226 // Merge this node's mask and our incoming mask (adjusted to account for all
22227 // the pshufd instructions encountered).
22228 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22229 for (int &M : Mask)
22231 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22232 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22234 // Check that the shuffles didn't cancel each other out. If not, we need to
22235 // combine to the new one.
22237 // Replace the combinable shuffle with the combined one, updating all users
22238 // so that we re-evaluate the chain here.
22239 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22244 /// \brief Try to combine x86 target specific shuffles.
22245 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22246 TargetLowering::DAGCombinerInfo &DCI,
22247 const X86Subtarget *Subtarget) {
22249 MVT VT = N.getSimpleValueType();
22250 SmallVector<int, 4> Mask;
22252 switch (N.getOpcode()) {
22253 case X86ISD::PSHUFD:
22254 case X86ISD::PSHUFLW:
22255 case X86ISD::PSHUFHW:
22256 Mask = getPSHUFShuffleMask(N);
22257 assert(Mask.size() == 4);
22263 // Nuke no-op shuffles that show up after combining.
22264 if (isNoopShuffleMask(Mask))
22265 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22267 // Look for simplifications involving one or two shuffle instructions.
22268 SDValue V = N.getOperand(0);
22269 switch (N.getOpcode()) {
22272 case X86ISD::PSHUFLW:
22273 case X86ISD::PSHUFHW:
22274 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22276 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22277 return SDValue(); // We combined away this shuffle, so we're done.
22279 // See if this reduces to a PSHUFD which is no more expensive and can
22280 // combine with more operations. Note that it has to at least flip the
22281 // dwords as otherwise it would have been removed as a no-op.
22282 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22283 int DMask[] = {0, 1, 2, 3};
22284 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22285 DMask[DOffset + 0] = DOffset + 1;
22286 DMask[DOffset + 1] = DOffset + 0;
22287 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22288 V = DAG.getBitcast(DVT, V);
22289 DCI.AddToWorklist(V.getNode());
22290 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22291 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22292 DCI.AddToWorklist(V.getNode());
22293 return DAG.getBitcast(VT, V);
22296 // Look for shuffle patterns which can be implemented as a single unpack.
22297 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22298 // only works when we have a PSHUFD followed by two half-shuffles.
22299 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22300 (V.getOpcode() == X86ISD::PSHUFLW ||
22301 V.getOpcode() == X86ISD::PSHUFHW) &&
22302 V.getOpcode() != N.getOpcode() &&
22304 SDValue D = V.getOperand(0);
22305 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22306 D = D.getOperand(0);
22307 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22308 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22309 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22310 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22311 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22313 for (int i = 0; i < 4; ++i) {
22314 WordMask[i + NOffset] = Mask[i] + NOffset;
22315 WordMask[i + VOffset] = VMask[i] + VOffset;
22317 // Map the word mask through the DWord mask.
22319 for (int i = 0; i < 8; ++i)
22320 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22321 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22322 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22323 // We can replace all three shuffles with an unpack.
22324 V = DAG.getBitcast(VT, D.getOperand(0));
22325 DCI.AddToWorklist(V.getNode());
22326 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22335 case X86ISD::PSHUFD:
22336 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22345 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22347 /// We combine this directly on the abstract vector shuffle nodes so it is
22348 /// easier to generically match. We also insert dummy vector shuffle nodes for
22349 /// the operands which explicitly discard the lanes which are unused by this
22350 /// operation to try to flow through the rest of the combiner the fact that
22351 /// they're unused.
22352 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22354 EVT VT = N->getValueType(0);
22356 // We only handle target-independent shuffles.
22357 // FIXME: It would be easy and harmless to use the target shuffle mask
22358 // extraction tool to support more.
22359 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22362 auto *SVN = cast<ShuffleVectorSDNode>(N);
22363 ArrayRef<int> Mask = SVN->getMask();
22364 SDValue V1 = N->getOperand(0);
22365 SDValue V2 = N->getOperand(1);
22367 // We require the first shuffle operand to be the SUB node, and the second to
22368 // be the ADD node.
22369 // FIXME: We should support the commuted patterns.
22370 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22373 // If there are other uses of these operations we can't fold them.
22374 if (!V1->hasOneUse() || !V2->hasOneUse())
22377 // Ensure that both operations have the same operands. Note that we can
22378 // commute the FADD operands.
22379 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22380 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22381 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22384 // We're looking for blends between FADD and FSUB nodes. We insist on these
22385 // nodes being lined up in a specific expected pattern.
22386 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22387 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22388 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22391 // Only specific types are legal at this point, assert so we notice if and
22392 // when these change.
22393 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22394 VT == MVT::v4f64) &&
22395 "Unknown vector type encountered!");
22397 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22400 /// PerformShuffleCombine - Performs several different shuffle combines.
22401 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22402 TargetLowering::DAGCombinerInfo &DCI,
22403 const X86Subtarget *Subtarget) {
22405 SDValue N0 = N->getOperand(0);
22406 SDValue N1 = N->getOperand(1);
22407 EVT VT = N->getValueType(0);
22409 // Don't create instructions with illegal types after legalize types has run.
22410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22411 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22414 // If we have legalized the vector types, look for blends of FADD and FSUB
22415 // nodes that we can fuse into an ADDSUB node.
22416 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22417 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22420 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22421 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22422 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22423 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22425 // During Type Legalization, when promoting illegal vector types,
22426 // the backend might introduce new shuffle dag nodes and bitcasts.
22428 // This code performs the following transformation:
22429 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22430 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22432 // We do this only if both the bitcast and the BINOP dag nodes have
22433 // one use. Also, perform this transformation only if the new binary
22434 // operation is legal. This is to avoid introducing dag nodes that
22435 // potentially need to be further expanded (or custom lowered) into a
22436 // less optimal sequence of dag nodes.
22437 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22438 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22439 N0.getOpcode() == ISD::BITCAST) {
22440 SDValue BC0 = N0.getOperand(0);
22441 EVT SVT = BC0.getValueType();
22442 unsigned Opcode = BC0.getOpcode();
22443 unsigned NumElts = VT.getVectorNumElements();
22445 if (BC0.hasOneUse() && SVT.isVector() &&
22446 SVT.getVectorNumElements() * 2 == NumElts &&
22447 TLI.isOperationLegal(Opcode, VT)) {
22448 bool CanFold = false;
22460 unsigned SVTNumElts = SVT.getVectorNumElements();
22461 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22462 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22463 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22464 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22465 CanFold = SVOp->getMaskElt(i) < 0;
22468 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22469 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22470 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22471 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22476 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22477 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22478 // consecutive, non-overlapping, and in the right order.
22479 SmallVector<SDValue, 16> Elts;
22480 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22481 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22483 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22486 if (isTargetShuffle(N->getOpcode())) {
22488 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22489 if (Shuffle.getNode())
22492 // Try recursively combining arbitrary sequences of x86 shuffle
22493 // instructions into higher-order shuffles. We do this after combining
22494 // specific PSHUF instruction sequences into their minimal form so that we
22495 // can evaluate how many specialized shuffle instructions are involved in
22496 // a particular chain.
22497 SmallVector<int, 1> NonceMask; // Just a placeholder.
22498 NonceMask.push_back(0);
22499 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22500 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22502 return SDValue(); // This routine will use CombineTo to replace N.
22508 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22509 /// specific shuffle of a load can be folded into a single element load.
22510 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22511 /// shuffles have been custom lowered so we need to handle those here.
22512 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22513 TargetLowering::DAGCombinerInfo &DCI) {
22514 if (DCI.isBeforeLegalizeOps())
22517 SDValue InVec = N->getOperand(0);
22518 SDValue EltNo = N->getOperand(1);
22520 if (!isa<ConstantSDNode>(EltNo))
22523 EVT OriginalVT = InVec.getValueType();
22525 if (InVec.getOpcode() == ISD::BITCAST) {
22526 // Don't duplicate a load with other uses.
22527 if (!InVec.hasOneUse())
22529 EVT BCVT = InVec.getOperand(0).getValueType();
22530 if (!BCVT.isVector() ||
22531 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22533 InVec = InVec.getOperand(0);
22536 EVT CurrentVT = InVec.getValueType();
22538 if (!isTargetShuffle(InVec.getOpcode()))
22541 // Don't duplicate a load with other uses.
22542 if (!InVec.hasOneUse())
22545 SmallVector<int, 16> ShuffleMask;
22547 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22548 ShuffleMask, UnaryShuffle))
22551 // Select the input vector, guarding against out of range extract vector.
22552 unsigned NumElems = CurrentVT.getVectorNumElements();
22553 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22554 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22555 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22556 : InVec.getOperand(1);
22558 // If inputs to shuffle are the same for both ops, then allow 2 uses
22559 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22560 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22562 if (LdNode.getOpcode() == ISD::BITCAST) {
22563 // Don't duplicate a load with other uses.
22564 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22567 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22568 LdNode = LdNode.getOperand(0);
22571 if (!ISD::isNormalLoad(LdNode.getNode()))
22574 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22576 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22579 EVT EltVT = N->getValueType(0);
22580 // If there's a bitcast before the shuffle, check if the load type and
22581 // alignment is valid.
22582 unsigned Align = LN0->getAlignment();
22583 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22584 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22585 EltVT.getTypeForEVT(*DAG.getContext()));
22587 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22590 // All checks match so transform back to vector_shuffle so that DAG combiner
22591 // can finish the job
22594 // Create shuffle node taking into account the case that its a unary shuffle
22595 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22596 : InVec.getOperand(1);
22597 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22598 InVec.getOperand(0), Shuffle,
22600 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22601 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22605 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22606 /// special and don't usually play with other vector types, it's better to
22607 /// handle them early to be sure we emit efficient code by avoiding
22608 /// store-load conversions.
22609 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22610 if (N->getValueType(0) != MVT::x86mmx ||
22611 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22612 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22615 SDValue V = N->getOperand(0);
22616 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22617 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22618 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22619 N->getValueType(0), V.getOperand(0));
22624 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22625 /// generation and convert it from being a bunch of shuffles and extracts
22626 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22627 /// storing the value and loading scalars back, while for x64 we should
22628 /// use 64-bit extracts and shifts.
22629 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22630 TargetLowering::DAGCombinerInfo &DCI) {
22631 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22634 SDValue InputVector = N->getOperand(0);
22635 SDLoc dl(InputVector);
22636 // Detect mmx to i32 conversion through a v2i32 elt extract.
22637 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22638 N->getValueType(0) == MVT::i32 &&
22639 InputVector.getValueType() == MVT::v2i32) {
22641 // The bitcast source is a direct mmx result.
22642 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22643 if (MMXSrc.getValueType() == MVT::x86mmx)
22644 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22645 N->getValueType(0),
22646 InputVector.getNode()->getOperand(0));
22648 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22649 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22650 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22651 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22652 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22653 MMXSrcOp.getValueType() == MVT::v1i64 &&
22654 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22655 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22656 N->getValueType(0),
22657 MMXSrcOp.getOperand(0));
22660 EVT VT = N->getValueType(0);
22662 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22663 InputVector.getOpcode() == ISD::BITCAST &&
22664 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22665 uint64_t ExtractedElt =
22666 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22667 uint64_t InputValue =
22668 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22669 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22670 return DAG.getConstant(Res, dl, MVT::i1);
22672 // Only operate on vectors of 4 elements, where the alternative shuffling
22673 // gets to be more expensive.
22674 if (InputVector.getValueType() != MVT::v4i32)
22677 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22678 // single use which is a sign-extend or zero-extend, and all elements are
22680 SmallVector<SDNode *, 4> Uses;
22681 unsigned ExtractedElements = 0;
22682 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22683 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22684 if (UI.getUse().getResNo() != InputVector.getResNo())
22687 SDNode *Extract = *UI;
22688 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22691 if (Extract->getValueType(0) != MVT::i32)
22693 if (!Extract->hasOneUse())
22695 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22696 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22698 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22701 // Record which element was extracted.
22702 ExtractedElements |=
22703 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22705 Uses.push_back(Extract);
22708 // If not all the elements were used, this may not be worthwhile.
22709 if (ExtractedElements != 15)
22712 // Ok, we've now decided to do the transformation.
22713 // If 64-bit shifts are legal, use the extract-shift sequence,
22714 // otherwise bounce the vector off the cache.
22715 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22718 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22719 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22720 auto &DL = DAG.getDataLayout();
22721 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22722 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22723 DAG.getConstant(0, dl, VecIdxTy));
22724 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22725 DAG.getConstant(1, dl, VecIdxTy));
22727 SDValue ShAmt = DAG.getConstant(
22728 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22729 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22730 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22731 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22732 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22733 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22734 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22736 // Store the value to a temporary stack slot.
22737 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22738 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22739 MachinePointerInfo(), false, false, 0);
22741 EVT ElementType = InputVector.getValueType().getVectorElementType();
22742 unsigned EltSize = ElementType.getSizeInBits() / 8;
22744 // Replace each use (extract) with a load of the appropriate element.
22745 for (unsigned i = 0; i < 4; ++i) {
22746 uint64_t Offset = EltSize * i;
22747 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
22748 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
22750 SDValue ScalarAddr =
22751 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
22753 // Load the scalar.
22754 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22755 ScalarAddr, MachinePointerInfo(),
22756 false, false, false, 0);
22761 // Replace the extracts
22762 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22763 UE = Uses.end(); UI != UE; ++UI) {
22764 SDNode *Extract = *UI;
22766 SDValue Idx = Extract->getOperand(1);
22767 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22768 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22771 // The replacement was made in place; don't return anything.
22776 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22777 const X86Subtarget *Subtarget) {
22779 SDValue Cond = N->getOperand(0);
22780 SDValue LHS = N->getOperand(1);
22781 SDValue RHS = N->getOperand(2);
22783 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22784 SDValue CondSrc = Cond->getOperand(0);
22785 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22786 Cond = CondSrc->getOperand(0);
22789 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22792 // A vselect where all conditions and data are constants can be optimized into
22793 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22794 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22795 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22798 unsigned MaskValue = 0;
22799 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22802 MVT VT = N->getSimpleValueType(0);
22803 unsigned NumElems = VT.getVectorNumElements();
22804 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22805 for (unsigned i = 0; i < NumElems; ++i) {
22806 // Be sure we emit undef where we can.
22807 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22808 ShuffleMask[i] = -1;
22810 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22814 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22816 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22819 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22821 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22822 TargetLowering::DAGCombinerInfo &DCI,
22823 const X86Subtarget *Subtarget) {
22825 SDValue Cond = N->getOperand(0);
22826 // Get the LHS/RHS of the select.
22827 SDValue LHS = N->getOperand(1);
22828 SDValue RHS = N->getOperand(2);
22829 EVT VT = LHS.getValueType();
22830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22832 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22833 // instructions match the semantics of the common C idiom x<y?x:y but not
22834 // x<=y?x:y, because of how they handle negative zero (which can be
22835 // ignored in unsafe-math mode).
22836 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
22837 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22838 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
22839 (Subtarget->hasSSE2() ||
22840 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22841 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22843 unsigned Opcode = 0;
22844 // Check for x CC y ? x : y.
22845 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22846 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22850 // Converting this to a min would handle NaNs incorrectly, and swapping
22851 // the operands would cause it to handle comparisons between positive
22852 // and negative zero incorrectly.
22853 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22854 if (!DAG.getTarget().Options.UnsafeFPMath &&
22855 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22857 std::swap(LHS, RHS);
22859 Opcode = X86ISD::FMIN;
22862 // Converting this to a min would handle comparisons between positive
22863 // and negative zero incorrectly.
22864 if (!DAG.getTarget().Options.UnsafeFPMath &&
22865 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22867 Opcode = X86ISD::FMIN;
22870 // Converting this to a min would handle both negative zeros and NaNs
22871 // incorrectly, but we can swap the operands to fix both.
22872 std::swap(LHS, RHS);
22876 Opcode = X86ISD::FMIN;
22880 // Converting this to a max would handle comparisons between positive
22881 // and negative zero incorrectly.
22882 if (!DAG.getTarget().Options.UnsafeFPMath &&
22883 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22885 Opcode = X86ISD::FMAX;
22888 // Converting this to a max would handle NaNs incorrectly, and swapping
22889 // the operands would cause it to handle comparisons between positive
22890 // and negative zero incorrectly.
22891 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22892 if (!DAG.getTarget().Options.UnsafeFPMath &&
22893 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22895 std::swap(LHS, RHS);
22897 Opcode = X86ISD::FMAX;
22900 // Converting this to a max would handle both negative zeros and NaNs
22901 // incorrectly, but we can swap the operands to fix both.
22902 std::swap(LHS, RHS);
22906 Opcode = X86ISD::FMAX;
22909 // Check for x CC y ? y : x -- a min/max with reversed arms.
22910 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22911 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22915 // Converting this to a min would handle comparisons between positive
22916 // and negative zero incorrectly, and swapping the operands would
22917 // cause it to handle NaNs incorrectly.
22918 if (!DAG.getTarget().Options.UnsafeFPMath &&
22919 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22920 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22922 std::swap(LHS, RHS);
22924 Opcode = X86ISD::FMIN;
22927 // Converting this to a min would handle NaNs incorrectly.
22928 if (!DAG.getTarget().Options.UnsafeFPMath &&
22929 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22931 Opcode = X86ISD::FMIN;
22934 // Converting this to a min would handle both negative zeros and NaNs
22935 // incorrectly, but we can swap the operands to fix both.
22936 std::swap(LHS, RHS);
22940 Opcode = X86ISD::FMIN;
22944 // Converting this to a max would handle NaNs incorrectly.
22945 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22947 Opcode = X86ISD::FMAX;
22950 // Converting this to a max would handle comparisons between positive
22951 // and negative zero incorrectly, and swapping the operands would
22952 // cause it to handle NaNs incorrectly.
22953 if (!DAG.getTarget().Options.UnsafeFPMath &&
22954 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22955 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22957 std::swap(LHS, RHS);
22959 Opcode = X86ISD::FMAX;
22962 // Converting this to a max would handle both negative zeros and NaNs
22963 // incorrectly, but we can swap the operands to fix both.
22964 std::swap(LHS, RHS);
22968 Opcode = X86ISD::FMAX;
22974 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22977 EVT CondVT = Cond.getValueType();
22978 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22979 CondVT.getVectorElementType() == MVT::i1) {
22980 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22981 // lowering on KNL. In this case we convert it to
22982 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22983 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22984 // Since SKX these selects have a proper lowering.
22985 EVT OpVT = LHS.getValueType();
22986 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22987 (OpVT.getVectorElementType() == MVT::i8 ||
22988 OpVT.getVectorElementType() == MVT::i16) &&
22989 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22990 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22991 DCI.AddToWorklist(Cond.getNode());
22992 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22995 // If this is a select between two integer constants, try to do some
22997 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22998 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22999 // Don't do this for crazy integer types.
23000 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23001 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23002 // so that TrueC (the true value) is larger than FalseC.
23003 bool NeedsCondInvert = false;
23005 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23006 // Efficiently invertible.
23007 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23008 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23009 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23010 NeedsCondInvert = true;
23011 std::swap(TrueC, FalseC);
23014 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23015 if (FalseC->getAPIntValue() == 0 &&
23016 TrueC->getAPIntValue().isPowerOf2()) {
23017 if (NeedsCondInvert) // Invert the condition if needed.
23018 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23019 DAG.getConstant(1, DL, Cond.getValueType()));
23021 // Zero extend the condition if needed.
23022 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23024 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23025 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23026 DAG.getConstant(ShAmt, DL, MVT::i8));
23029 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23030 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23031 if (NeedsCondInvert) // Invert the condition if needed.
23032 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23033 DAG.getConstant(1, DL, Cond.getValueType()));
23035 // Zero extend the condition if needed.
23036 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23037 FalseC->getValueType(0), Cond);
23038 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23039 SDValue(FalseC, 0));
23042 // Optimize cases that will turn into an LEA instruction. This requires
23043 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23044 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23045 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23046 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23048 bool isFastMultiplier = false;
23050 switch ((unsigned char)Diff) {
23052 case 1: // result = add base, cond
23053 case 2: // result = lea base( , cond*2)
23054 case 3: // result = lea base(cond, cond*2)
23055 case 4: // result = lea base( , cond*4)
23056 case 5: // result = lea base(cond, cond*4)
23057 case 8: // result = lea base( , cond*8)
23058 case 9: // result = lea base(cond, cond*8)
23059 isFastMultiplier = true;
23064 if (isFastMultiplier) {
23065 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23066 if (NeedsCondInvert) // Invert the condition if needed.
23067 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23068 DAG.getConstant(1, DL, Cond.getValueType()));
23070 // Zero extend the condition if needed.
23071 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23073 // Scale the condition by the difference.
23075 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23076 DAG.getConstant(Diff, DL,
23077 Cond.getValueType()));
23079 // Add the base if non-zero.
23080 if (FalseC->getAPIntValue() != 0)
23081 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23082 SDValue(FalseC, 0));
23089 // Canonicalize max and min:
23090 // (x > y) ? x : y -> (x >= y) ? x : y
23091 // (x < y) ? x : y -> (x <= y) ? x : y
23092 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23093 // the need for an extra compare
23094 // against zero. e.g.
23095 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23097 // testl %edi, %edi
23099 // cmovgl %edi, %eax
23103 // cmovsl %eax, %edi
23104 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23105 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23106 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23107 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23112 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23113 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23114 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23115 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23120 // Early exit check
23121 if (!TLI.isTypeLegal(VT))
23124 // Match VSELECTs into subs with unsigned saturation.
23125 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23126 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23127 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23128 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23129 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23131 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23132 // left side invert the predicate to simplify logic below.
23134 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23136 CC = ISD::getSetCCInverse(CC, true);
23137 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23141 if (Other.getNode() && Other->getNumOperands() == 2 &&
23142 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23143 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23144 SDValue CondRHS = Cond->getOperand(1);
23146 // Look for a general sub with unsigned saturation first.
23147 // x >= y ? x-y : 0 --> subus x, y
23148 // x > y ? x-y : 0 --> subus x, y
23149 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23150 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23151 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23153 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23154 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23155 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23156 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23157 // If the RHS is a constant we have to reverse the const
23158 // canonicalization.
23159 // x > C-1 ? x+-C : 0 --> subus x, C
23160 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23161 CondRHSConst->getAPIntValue() ==
23162 (-OpRHSConst->getAPIntValue() - 1))
23163 return DAG.getNode(
23164 X86ISD::SUBUS, DL, VT, OpLHS,
23165 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23167 // Another special case: If C was a sign bit, the sub has been
23168 // canonicalized into a xor.
23169 // FIXME: Would it be better to use computeKnownBits to determine
23170 // whether it's safe to decanonicalize the xor?
23171 // x s< 0 ? x^C : 0 --> subus x, C
23172 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23173 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23174 OpRHSConst->getAPIntValue().isSignBit())
23175 // Note that we have to rebuild the RHS constant here to ensure we
23176 // don't rely on particular values of undef lanes.
23177 return DAG.getNode(
23178 X86ISD::SUBUS, DL, VT, OpLHS,
23179 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23184 // Simplify vector selection if condition value type matches vselect
23186 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23187 assert(Cond.getValueType().isVector() &&
23188 "vector select expects a vector selector!");
23190 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23191 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23193 // Try invert the condition if true value is not all 1s and false value
23195 if (!TValIsAllOnes && !FValIsAllZeros &&
23196 // Check if the selector will be produced by CMPP*/PCMP*
23197 Cond.getOpcode() == ISD::SETCC &&
23198 // Check if SETCC has already been promoted
23199 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23201 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23202 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23204 if (TValIsAllZeros || FValIsAllOnes) {
23205 SDValue CC = Cond.getOperand(2);
23206 ISD::CondCode NewCC =
23207 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23208 Cond.getOperand(0).getValueType().isInteger());
23209 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23210 std::swap(LHS, RHS);
23211 TValIsAllOnes = FValIsAllOnes;
23212 FValIsAllZeros = TValIsAllZeros;
23216 if (TValIsAllOnes || FValIsAllZeros) {
23219 if (TValIsAllOnes && FValIsAllZeros)
23221 else if (TValIsAllOnes)
23223 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23224 else if (FValIsAllZeros)
23225 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23226 DAG.getBitcast(CondVT, LHS));
23228 return DAG.getBitcast(VT, Ret);
23232 // We should generate an X86ISD::BLENDI from a vselect if its argument
23233 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23234 // constants. This specific pattern gets generated when we split a
23235 // selector for a 512 bit vector in a machine without AVX512 (but with
23236 // 256-bit vectors), during legalization:
23238 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23240 // Iff we find this pattern and the build_vectors are built from
23241 // constants, we translate the vselect into a shuffle_vector that we
23242 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23243 if ((N->getOpcode() == ISD::VSELECT ||
23244 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23245 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23246 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23247 if (Shuffle.getNode())
23251 // If this is a *dynamic* select (non-constant condition) and we can match
23252 // this node with one of the variable blend instructions, restructure the
23253 // condition so that the blends can use the high bit of each element and use
23254 // SimplifyDemandedBits to simplify the condition operand.
23255 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23256 !DCI.isBeforeLegalize() &&
23257 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23258 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23260 // Don't optimize vector selects that map to mask-registers.
23264 // We can only handle the cases where VSELECT is directly legal on the
23265 // subtarget. We custom lower VSELECT nodes with constant conditions and
23266 // this makes it hard to see whether a dynamic VSELECT will correctly
23267 // lower, so we both check the operation's status and explicitly handle the
23268 // cases where a *dynamic* blend will fail even though a constant-condition
23269 // blend could be custom lowered.
23270 // FIXME: We should find a better way to handle this class of problems.
23271 // Potentially, we should combine constant-condition vselect nodes
23272 // pre-legalization into shuffles and not mark as many types as custom
23274 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23276 // FIXME: We don't support i16-element blends currently. We could and
23277 // should support them by making *all* the bits in the condition be set
23278 // rather than just the high bit and using an i8-element blend.
23279 if (VT.getScalarType() == MVT::i16)
23281 // Dynamic blending was only available from SSE4.1 onward.
23282 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23284 // Byte blends are only available in AVX2
23285 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23286 !Subtarget->hasAVX2())
23289 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23290 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23292 APInt KnownZero, KnownOne;
23293 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23294 DCI.isBeforeLegalizeOps());
23295 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23296 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23298 // If we changed the computation somewhere in the DAG, this change
23299 // will affect all users of Cond.
23300 // Make sure it is fine and update all the nodes so that we do not
23301 // use the generic VSELECT anymore. Otherwise, we may perform
23302 // wrong optimizations as we messed up with the actual expectation
23303 // for the vector boolean values.
23304 if (Cond != TLO.Old) {
23305 // Check all uses of that condition operand to check whether it will be
23306 // consumed by non-BLEND instructions, which may depend on all bits are
23308 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23310 if (I->getOpcode() != ISD::VSELECT)
23311 // TODO: Add other opcodes eventually lowered into BLEND.
23314 // Update all the users of the condition, before committing the change,
23315 // so that the VSELECT optimizations that expect the correct vector
23316 // boolean value will not be triggered.
23317 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23319 DAG.ReplaceAllUsesOfValueWith(
23321 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23322 Cond, I->getOperand(1), I->getOperand(2)));
23323 DCI.CommitTargetLoweringOpt(TLO);
23326 // At this point, only Cond is changed. Change the condition
23327 // just for N to keep the opportunity to optimize all other
23328 // users their own way.
23329 DAG.ReplaceAllUsesOfValueWith(
23331 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23332 TLO.New, N->getOperand(1), N->getOperand(2)));
23340 // Check whether a boolean test is testing a boolean value generated by
23341 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23344 // Simplify the following patterns:
23345 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23346 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23347 // to (Op EFLAGS Cond)
23349 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23350 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23351 // to (Op EFLAGS !Cond)
23353 // where Op could be BRCOND or CMOV.
23355 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23356 // Quit if not CMP and SUB with its value result used.
23357 if (Cmp.getOpcode() != X86ISD::CMP &&
23358 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23361 // Quit if not used as a boolean value.
23362 if (CC != X86::COND_E && CC != X86::COND_NE)
23365 // Check CMP operands. One of them should be 0 or 1 and the other should be
23366 // an SetCC or extended from it.
23367 SDValue Op1 = Cmp.getOperand(0);
23368 SDValue Op2 = Cmp.getOperand(1);
23371 const ConstantSDNode* C = nullptr;
23372 bool needOppositeCond = (CC == X86::COND_E);
23373 bool checkAgainstTrue = false; // Is it a comparison against 1?
23375 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23377 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23379 else // Quit if all operands are not constants.
23382 if (C->getZExtValue() == 1) {
23383 needOppositeCond = !needOppositeCond;
23384 checkAgainstTrue = true;
23385 } else if (C->getZExtValue() != 0)
23386 // Quit if the constant is neither 0 or 1.
23389 bool truncatedToBoolWithAnd = false;
23390 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23391 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23392 SetCC.getOpcode() == ISD::TRUNCATE ||
23393 SetCC.getOpcode() == ISD::AND) {
23394 if (SetCC.getOpcode() == ISD::AND) {
23396 ConstantSDNode *CS;
23397 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23398 CS->getZExtValue() == 1)
23400 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23401 CS->getZExtValue() == 1)
23405 SetCC = SetCC.getOperand(OpIdx);
23406 truncatedToBoolWithAnd = true;
23408 SetCC = SetCC.getOperand(0);
23411 switch (SetCC.getOpcode()) {
23412 case X86ISD::SETCC_CARRY:
23413 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23414 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23415 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23416 // truncated to i1 using 'and'.
23417 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23419 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23420 "Invalid use of SETCC_CARRY!");
23422 case X86ISD::SETCC:
23423 // Set the condition code or opposite one if necessary.
23424 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23425 if (needOppositeCond)
23426 CC = X86::GetOppositeBranchCondition(CC);
23427 return SetCC.getOperand(1);
23428 case X86ISD::CMOV: {
23429 // Check whether false/true value has canonical one, i.e. 0 or 1.
23430 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23431 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23432 // Quit if true value is not a constant.
23435 // Quit if false value is not a constant.
23437 SDValue Op = SetCC.getOperand(0);
23438 // Skip 'zext' or 'trunc' node.
23439 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23440 Op.getOpcode() == ISD::TRUNCATE)
23441 Op = Op.getOperand(0);
23442 // A special case for rdrand/rdseed, where 0 is set if false cond is
23444 if ((Op.getOpcode() != X86ISD::RDRAND &&
23445 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23448 // Quit if false value is not the constant 0 or 1.
23449 bool FValIsFalse = true;
23450 if (FVal && FVal->getZExtValue() != 0) {
23451 if (FVal->getZExtValue() != 1)
23453 // If FVal is 1, opposite cond is needed.
23454 needOppositeCond = !needOppositeCond;
23455 FValIsFalse = false;
23457 // Quit if TVal is not the constant opposite of FVal.
23458 if (FValIsFalse && TVal->getZExtValue() != 1)
23460 if (!FValIsFalse && TVal->getZExtValue() != 0)
23462 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23463 if (needOppositeCond)
23464 CC = X86::GetOppositeBranchCondition(CC);
23465 return SetCC.getOperand(3);
23472 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23474 /// (X86or (X86setcc) (X86setcc))
23475 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23476 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23477 X86::CondCode &CC1, SDValue &Flags,
23479 if (Cond->getOpcode() == X86ISD::CMP) {
23480 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23481 if (!CondOp1C || !CondOp1C->isNullValue())
23484 Cond = Cond->getOperand(0);
23489 SDValue SetCC0, SetCC1;
23490 switch (Cond->getOpcode()) {
23491 default: return false;
23498 SetCC0 = Cond->getOperand(0);
23499 SetCC1 = Cond->getOperand(1);
23503 // Make sure we have SETCC nodes, using the same flags value.
23504 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23505 SetCC1.getOpcode() != X86ISD::SETCC ||
23506 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23509 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23510 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23511 Flags = SetCC0->getOperand(1);
23515 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23516 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23517 TargetLowering::DAGCombinerInfo &DCI,
23518 const X86Subtarget *Subtarget) {
23521 // If the flag operand isn't dead, don't touch this CMOV.
23522 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23525 SDValue FalseOp = N->getOperand(0);
23526 SDValue TrueOp = N->getOperand(1);
23527 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23528 SDValue Cond = N->getOperand(3);
23530 if (CC == X86::COND_E || CC == X86::COND_NE) {
23531 switch (Cond.getOpcode()) {
23535 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23536 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23537 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23543 Flags = checkBoolTestSetCCCombine(Cond, CC);
23544 if (Flags.getNode() &&
23545 // Extra check as FCMOV only supports a subset of X86 cond.
23546 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23547 SDValue Ops[] = { FalseOp, TrueOp,
23548 DAG.getConstant(CC, DL, MVT::i8), Flags };
23549 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23552 // If this is a select between two integer constants, try to do some
23553 // optimizations. Note that the operands are ordered the opposite of SELECT
23555 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23556 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23557 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23558 // larger than FalseC (the false value).
23559 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23560 CC = X86::GetOppositeBranchCondition(CC);
23561 std::swap(TrueC, FalseC);
23562 std::swap(TrueOp, FalseOp);
23565 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23566 // This is efficient for any integer data type (including i8/i16) and
23568 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23569 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23570 DAG.getConstant(CC, DL, MVT::i8), Cond);
23572 // Zero extend the condition if needed.
23573 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23575 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23576 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23577 DAG.getConstant(ShAmt, DL, MVT::i8));
23578 if (N->getNumValues() == 2) // Dead flag value?
23579 return DCI.CombineTo(N, Cond, SDValue());
23583 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23584 // for any integer data type, including i8/i16.
23585 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23586 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23587 DAG.getConstant(CC, DL, MVT::i8), Cond);
23589 // Zero extend the condition if needed.
23590 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23591 FalseC->getValueType(0), Cond);
23592 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23593 SDValue(FalseC, 0));
23595 if (N->getNumValues() == 2) // Dead flag value?
23596 return DCI.CombineTo(N, Cond, SDValue());
23600 // Optimize cases that will turn into an LEA instruction. This requires
23601 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23602 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23603 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23604 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23606 bool isFastMultiplier = false;
23608 switch ((unsigned char)Diff) {
23610 case 1: // result = add base, cond
23611 case 2: // result = lea base( , cond*2)
23612 case 3: // result = lea base(cond, cond*2)
23613 case 4: // result = lea base( , cond*4)
23614 case 5: // result = lea base(cond, cond*4)
23615 case 8: // result = lea base( , cond*8)
23616 case 9: // result = lea base(cond, cond*8)
23617 isFastMultiplier = true;
23622 if (isFastMultiplier) {
23623 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23624 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23625 DAG.getConstant(CC, DL, MVT::i8), Cond);
23626 // Zero extend the condition if needed.
23627 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23629 // Scale the condition by the difference.
23631 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23632 DAG.getConstant(Diff, DL, Cond.getValueType()));
23634 // Add the base if non-zero.
23635 if (FalseC->getAPIntValue() != 0)
23636 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23637 SDValue(FalseC, 0));
23638 if (N->getNumValues() == 2) // Dead flag value?
23639 return DCI.CombineTo(N, Cond, SDValue());
23646 // Handle these cases:
23647 // (select (x != c), e, c) -> select (x != c), e, x),
23648 // (select (x == c), c, e) -> select (x == c), x, e)
23649 // where the c is an integer constant, and the "select" is the combination
23650 // of CMOV and CMP.
23652 // The rationale for this change is that the conditional-move from a constant
23653 // needs two instructions, however, conditional-move from a register needs
23654 // only one instruction.
23656 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23657 // some instruction-combining opportunities. This opt needs to be
23658 // postponed as late as possible.
23660 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23661 // the DCI.xxxx conditions are provided to postpone the optimization as
23662 // late as possible.
23664 ConstantSDNode *CmpAgainst = nullptr;
23665 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23666 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23667 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23669 if (CC == X86::COND_NE &&
23670 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23671 CC = X86::GetOppositeBranchCondition(CC);
23672 std::swap(TrueOp, FalseOp);
23675 if (CC == X86::COND_E &&
23676 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23677 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23678 DAG.getConstant(CC, DL, MVT::i8), Cond };
23679 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23684 // Fold and/or of setcc's to double CMOV:
23685 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23686 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23688 // This combine lets us generate:
23689 // cmovcc1 (jcc1 if we don't have CMOV)
23695 // cmovne (jne if we don't have CMOV)
23696 // When we can't use the CMOV instruction, it might increase branch
23698 // When we can use CMOV, or when there is no mispredict, this improves
23699 // throughput and reduces register pressure.
23701 if (CC == X86::COND_NE) {
23703 X86::CondCode CC0, CC1;
23705 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23707 std::swap(FalseOp, TrueOp);
23708 CC0 = X86::GetOppositeBranchCondition(CC0);
23709 CC1 = X86::GetOppositeBranchCondition(CC1);
23712 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23714 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23715 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23716 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23717 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23725 /// PerformMulCombine - Optimize a single multiply with constant into two
23726 /// in order to implement it with two cheaper instructions, e.g.
23727 /// LEA + SHL, LEA + LEA.
23728 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23729 TargetLowering::DAGCombinerInfo &DCI) {
23730 // An imul is usually smaller than the alternative sequence.
23731 if (DAG.getMachineFunction().getFunction()->optForMinSize())
23734 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23737 EVT VT = N->getValueType(0);
23738 if (VT != MVT::i64 && VT != MVT::i32)
23741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23744 uint64_t MulAmt = C->getZExtValue();
23745 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23748 uint64_t MulAmt1 = 0;
23749 uint64_t MulAmt2 = 0;
23750 if ((MulAmt % 9) == 0) {
23752 MulAmt2 = MulAmt / 9;
23753 } else if ((MulAmt % 5) == 0) {
23755 MulAmt2 = MulAmt / 5;
23756 } else if ((MulAmt % 3) == 0) {
23758 MulAmt2 = MulAmt / 3;
23761 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23764 if (isPowerOf2_64(MulAmt2) &&
23765 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23766 // If second multiplifer is pow2, issue it first. We want the multiply by
23767 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23769 std::swap(MulAmt1, MulAmt2);
23772 if (isPowerOf2_64(MulAmt1))
23773 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23774 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
23776 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23777 DAG.getConstant(MulAmt1, DL, VT));
23779 if (isPowerOf2_64(MulAmt2))
23780 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23781 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
23783 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23784 DAG.getConstant(MulAmt2, DL, VT));
23786 // Do not add new nodes to DAG combiner worklist.
23787 DCI.CombineTo(N, NewMul, false);
23792 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23793 SDValue N0 = N->getOperand(0);
23794 SDValue N1 = N->getOperand(1);
23795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23796 EVT VT = N0.getValueType();
23798 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23799 // since the result of setcc_c is all zero's or all ones.
23800 if (VT.isInteger() && !VT.isVector() &&
23801 N1C && N0.getOpcode() == ISD::AND &&
23802 N0.getOperand(1).getOpcode() == ISD::Constant) {
23803 SDValue N00 = N0.getOperand(0);
23804 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23805 APInt ShAmt = N1C->getAPIntValue();
23806 Mask = Mask.shl(ShAmt);
23807 bool MaskOK = false;
23808 // We can handle cases concerning bit-widening nodes containing setcc_c if
23809 // we carefully interrogate the mask to make sure we are semantics
23811 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
23812 // of the underlying setcc_c operation if the setcc_c was zero extended.
23813 // Consider the following example:
23814 // zext(setcc_c) -> i32 0x0000FFFF
23815 // c1 -> i32 0x0000FFFF
23816 // c2 -> i32 0x00000001
23817 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
23818 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
23819 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23821 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
23822 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
23824 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
23825 N00.getOpcode() == ISD::ANY_EXTEND) &&
23826 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
23827 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
23829 if (MaskOK && Mask != 0) {
23831 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
23835 // Hardware support for vector shifts is sparse which makes us scalarize the
23836 // vector operations in many cases. Also, on sandybridge ADD is faster than
23838 // (shl V, 1) -> add V,V
23839 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23840 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23841 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23842 // We shift all of the values by one. In many cases we do not have
23843 // hardware support for this operation. This is better expressed as an ADD
23845 if (N1SplatC->getAPIntValue() == 1)
23846 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23852 /// \brief Returns a vector of 0s if the node in input is a vector logical
23853 /// shift by a constant amount which is known to be bigger than or equal
23854 /// to the vector element size in bits.
23855 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23856 const X86Subtarget *Subtarget) {
23857 EVT VT = N->getValueType(0);
23859 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23860 (!Subtarget->hasInt256() ||
23861 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23864 SDValue Amt = N->getOperand(1);
23866 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23867 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23868 APInt ShiftAmt = AmtSplat->getAPIntValue();
23869 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23871 // SSE2/AVX2 logical shifts always return a vector of 0s
23872 // if the shift amount is bigger than or equal to
23873 // the element size. The constant shift amount will be
23874 // encoded as a 8-bit immediate.
23875 if (ShiftAmt.trunc(8).uge(MaxAmount))
23876 return getZeroVector(VT, Subtarget, DAG, DL);
23882 /// PerformShiftCombine - Combine shifts.
23883 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23884 TargetLowering::DAGCombinerInfo &DCI,
23885 const X86Subtarget *Subtarget) {
23886 if (N->getOpcode() == ISD::SHL)
23887 if (SDValue V = PerformSHLCombine(N, DAG))
23890 // Try to fold this logical shift into a zero vector.
23891 if (N->getOpcode() != ISD::SRA)
23892 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
23898 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23899 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23900 // and friends. Likewise for OR -> CMPNEQSS.
23901 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23902 TargetLowering::DAGCombinerInfo &DCI,
23903 const X86Subtarget *Subtarget) {
23906 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23907 // we're requiring SSE2 for both.
23908 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23909 SDValue N0 = N->getOperand(0);
23910 SDValue N1 = N->getOperand(1);
23911 SDValue CMP0 = N0->getOperand(1);
23912 SDValue CMP1 = N1->getOperand(1);
23915 // The SETCCs should both refer to the same CMP.
23916 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23919 SDValue CMP00 = CMP0->getOperand(0);
23920 SDValue CMP01 = CMP0->getOperand(1);
23921 EVT VT = CMP00.getValueType();
23923 if (VT == MVT::f32 || VT == MVT::f64) {
23924 bool ExpectingFlags = false;
23925 // Check for any users that want flags:
23926 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23927 !ExpectingFlags && UI != UE; ++UI)
23928 switch (UI->getOpcode()) {
23933 ExpectingFlags = true;
23935 case ISD::CopyToReg:
23936 case ISD::SIGN_EXTEND:
23937 case ISD::ZERO_EXTEND:
23938 case ISD::ANY_EXTEND:
23942 if (!ExpectingFlags) {
23943 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23944 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23946 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23947 X86::CondCode tmp = cc0;
23952 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23953 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23954 // FIXME: need symbolic constants for these magic numbers.
23955 // See X86ATTInstPrinter.cpp:printSSECC().
23956 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23957 if (Subtarget->hasAVX512()) {
23958 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23960 DAG.getConstant(x86cc, DL, MVT::i8));
23961 if (N->getValueType(0) != MVT::i1)
23962 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23966 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23967 CMP00.getValueType(), CMP00, CMP01,
23968 DAG.getConstant(x86cc, DL,
23971 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23972 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23974 if (is64BitFP && !Subtarget->is64Bit()) {
23975 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23976 // 64-bit integer, since that's not a legal type. Since
23977 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23978 // bits, but can do this little dance to extract the lowest 32 bits
23979 // and work with those going forward.
23980 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23982 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
23983 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23984 Vector32, DAG.getIntPtrConstant(0, DL));
23988 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23989 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23990 DAG.getConstant(1, DL, IntVT));
23991 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
23993 return OneBitOfTruth;
24001 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24002 /// so it can be folded inside ANDNP.
24003 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24004 EVT VT = N->getValueType(0);
24006 // Match direct AllOnes for 128 and 256-bit vectors
24007 if (ISD::isBuildVectorAllOnes(N))
24010 // Look through a bit convert.
24011 if (N->getOpcode() == ISD::BITCAST)
24012 N = N->getOperand(0).getNode();
24014 // Sometimes the operand may come from a insert_subvector building a 256-bit
24016 if (VT.is256BitVector() &&
24017 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24018 SDValue V1 = N->getOperand(0);
24019 SDValue V2 = N->getOperand(1);
24021 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24022 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24023 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24024 ISD::isBuildVectorAllOnes(V2.getNode()))
24031 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24032 // register. In most cases we actually compare or select YMM-sized registers
24033 // and mixing the two types creates horrible code. This method optimizes
24034 // some of the transition sequences.
24035 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24036 TargetLowering::DAGCombinerInfo &DCI,
24037 const X86Subtarget *Subtarget) {
24038 EVT VT = N->getValueType(0);
24039 if (!VT.is256BitVector())
24042 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24043 N->getOpcode() == ISD::ZERO_EXTEND ||
24044 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24046 SDValue Narrow = N->getOperand(0);
24047 EVT NarrowVT = Narrow->getValueType(0);
24048 if (!NarrowVT.is128BitVector())
24051 if (Narrow->getOpcode() != ISD::XOR &&
24052 Narrow->getOpcode() != ISD::AND &&
24053 Narrow->getOpcode() != ISD::OR)
24056 SDValue N0 = Narrow->getOperand(0);
24057 SDValue N1 = Narrow->getOperand(1);
24060 // The Left side has to be a trunc.
24061 if (N0.getOpcode() != ISD::TRUNCATE)
24064 // The type of the truncated inputs.
24065 EVT WideVT = N0->getOperand(0)->getValueType(0);
24069 // The right side has to be a 'trunc' or a constant vector.
24070 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24071 ConstantSDNode *RHSConstSplat = nullptr;
24072 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24073 RHSConstSplat = RHSBV->getConstantSplatNode();
24074 if (!RHSTrunc && !RHSConstSplat)
24077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24079 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24082 // Set N0 and N1 to hold the inputs to the new wide operation.
24083 N0 = N0->getOperand(0);
24084 if (RHSConstSplat) {
24085 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24086 SDValue(RHSConstSplat, 0));
24087 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24088 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24089 } else if (RHSTrunc) {
24090 N1 = N1->getOperand(0);
24093 // Generate the wide operation.
24094 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24095 unsigned Opcode = N->getOpcode();
24097 case ISD::ANY_EXTEND:
24099 case ISD::ZERO_EXTEND: {
24100 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24101 APInt Mask = APInt::getAllOnesValue(InBits);
24102 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24103 return DAG.getNode(ISD::AND, DL, VT,
24104 Op, DAG.getConstant(Mask, DL, VT));
24106 case ISD::SIGN_EXTEND:
24107 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24108 Op, DAG.getValueType(NarrowVT));
24110 llvm_unreachable("Unexpected opcode");
24114 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24115 TargetLowering::DAGCombinerInfo &DCI,
24116 const X86Subtarget *Subtarget) {
24117 SDValue N0 = N->getOperand(0);
24118 SDValue N1 = N->getOperand(1);
24121 // A vector zext_in_reg may be represented as a shuffle,
24122 // feeding into a bitcast (this represents anyext) feeding into
24123 // an and with a mask.
24124 // We'd like to try to combine that into a shuffle with zero
24125 // plus a bitcast, removing the and.
24126 if (N0.getOpcode() != ISD::BITCAST ||
24127 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24130 // The other side of the AND should be a splat of 2^C, where C
24131 // is the number of bits in the source type.
24132 if (N1.getOpcode() == ISD::BITCAST)
24133 N1 = N1.getOperand(0);
24134 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24136 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24138 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24139 EVT SrcType = Shuffle->getValueType(0);
24141 // We expect a single-source shuffle
24142 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24145 unsigned SrcSize = SrcType.getScalarSizeInBits();
24147 APInt SplatValue, SplatUndef;
24148 unsigned SplatBitSize;
24150 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24151 SplatBitSize, HasAnyUndefs))
24154 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24155 // Make sure the splat matches the mask we expect
24156 if (SplatBitSize > ResSize ||
24157 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24160 // Make sure the input and output size make sense
24161 if (SrcSize >= ResSize || ResSize % SrcSize)
24164 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24165 // The number of u's between each two values depends on the ratio between
24166 // the source and dest type.
24167 unsigned ZextRatio = ResSize / SrcSize;
24168 bool IsZext = true;
24169 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24170 if (i % ZextRatio) {
24171 if (Shuffle->getMaskElt(i) > 0) {
24177 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24178 // Expected element number
24188 // Ok, perform the transformation - replace the shuffle with
24189 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24190 // (instead of undef) where the k elements come from the zero vector.
24191 SmallVector<int, 8> Mask;
24192 unsigned NumElems = SrcType.getVectorNumElements();
24193 for (unsigned i = 0; i < NumElems; ++i)
24195 Mask.push_back(NumElems);
24197 Mask.push_back(i / ZextRatio);
24199 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24200 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24201 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24204 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24205 TargetLowering::DAGCombinerInfo &DCI,
24206 const X86Subtarget *Subtarget) {
24207 if (DCI.isBeforeLegalizeOps())
24210 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24213 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24216 EVT VT = N->getValueType(0);
24217 SDValue N0 = N->getOperand(0);
24218 SDValue N1 = N->getOperand(1);
24221 // Create BEXTR instructions
24222 // BEXTR is ((X >> imm) & (2**size-1))
24223 if (VT == MVT::i32 || VT == MVT::i64) {
24224 // Check for BEXTR.
24225 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24226 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24227 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24228 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24229 if (MaskNode && ShiftNode) {
24230 uint64_t Mask = MaskNode->getZExtValue();
24231 uint64_t Shift = ShiftNode->getZExtValue();
24232 if (isMask_64(Mask)) {
24233 uint64_t MaskSize = countPopulation(Mask);
24234 if (Shift + MaskSize <= VT.getSizeInBits())
24235 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24236 DAG.getConstant(Shift | (MaskSize << 8), DL,
24245 // Want to form ANDNP nodes:
24246 // 1) In the hopes of then easily combining them with OR and AND nodes
24247 // to form PBLEND/PSIGN.
24248 // 2) To match ANDN packed intrinsics
24249 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24252 // Check LHS for vnot
24253 if (N0.getOpcode() == ISD::XOR &&
24254 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24255 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24256 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24258 // Check RHS for vnot
24259 if (N1.getOpcode() == ISD::XOR &&
24260 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24261 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24262 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24267 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24268 TargetLowering::DAGCombinerInfo &DCI,
24269 const X86Subtarget *Subtarget) {
24270 if (DCI.isBeforeLegalizeOps())
24273 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24276 SDValue N0 = N->getOperand(0);
24277 SDValue N1 = N->getOperand(1);
24278 EVT VT = N->getValueType(0);
24280 // look for psign/blend
24281 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24282 if (!Subtarget->hasSSSE3() ||
24283 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24286 // Canonicalize pandn to RHS
24287 if (N0.getOpcode() == X86ISD::ANDNP)
24289 // or (and (m, y), (pandn m, x))
24290 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24291 SDValue Mask = N1.getOperand(0);
24292 SDValue X = N1.getOperand(1);
24294 if (N0.getOperand(0) == Mask)
24295 Y = N0.getOperand(1);
24296 if (N0.getOperand(1) == Mask)
24297 Y = N0.getOperand(0);
24299 // Check to see if the mask appeared in both the AND and ANDNP and
24303 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24304 // Look through mask bitcast.
24305 if (Mask.getOpcode() == ISD::BITCAST)
24306 Mask = Mask.getOperand(0);
24307 if (X.getOpcode() == ISD::BITCAST)
24308 X = X.getOperand(0);
24309 if (Y.getOpcode() == ISD::BITCAST)
24310 Y = Y.getOperand(0);
24312 EVT MaskVT = Mask.getValueType();
24314 // Validate that the Mask operand is a vector sra node.
24315 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24316 // there is no psrai.b
24317 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24318 unsigned SraAmt = ~0;
24319 if (Mask.getOpcode() == ISD::SRA) {
24320 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24321 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24322 SraAmt = AmtConst->getZExtValue();
24323 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24324 SDValue SraC = Mask.getOperand(1);
24325 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24327 if ((SraAmt + 1) != EltBits)
24332 // Now we know we at least have a plendvb with the mask val. See if
24333 // we can form a psignb/w/d.
24334 // psign = x.type == y.type == mask.type && y = sub(0, x);
24335 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24336 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24337 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24338 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24339 "Unsupported VT for PSIGN");
24340 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24341 return DAG.getBitcast(VT, Mask);
24343 // PBLENDVB only available on SSE 4.1
24344 if (!Subtarget->hasSSE41())
24347 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24349 X = DAG.getBitcast(BlendVT, X);
24350 Y = DAG.getBitcast(BlendVT, Y);
24351 Mask = DAG.getBitcast(BlendVT, Mask);
24352 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24353 return DAG.getBitcast(VT, Mask);
24357 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24360 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24361 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24363 // SHLD/SHRD instructions have lower register pressure, but on some
24364 // platforms they have higher latency than the equivalent
24365 // series of shifts/or that would otherwise be generated.
24366 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24367 // have higher latencies and we are not optimizing for size.
24368 if (!OptForSize && Subtarget->isSHLDSlow())
24371 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24373 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24375 if (!N0.hasOneUse() || !N1.hasOneUse())
24378 SDValue ShAmt0 = N0.getOperand(1);
24379 if (ShAmt0.getValueType() != MVT::i8)
24381 SDValue ShAmt1 = N1.getOperand(1);
24382 if (ShAmt1.getValueType() != MVT::i8)
24384 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24385 ShAmt0 = ShAmt0.getOperand(0);
24386 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24387 ShAmt1 = ShAmt1.getOperand(0);
24390 unsigned Opc = X86ISD::SHLD;
24391 SDValue Op0 = N0.getOperand(0);
24392 SDValue Op1 = N1.getOperand(0);
24393 if (ShAmt0.getOpcode() == ISD::SUB) {
24394 Opc = X86ISD::SHRD;
24395 std::swap(Op0, Op1);
24396 std::swap(ShAmt0, ShAmt1);
24399 unsigned Bits = VT.getSizeInBits();
24400 if (ShAmt1.getOpcode() == ISD::SUB) {
24401 SDValue Sum = ShAmt1.getOperand(0);
24402 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24403 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24404 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24405 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24406 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24407 return DAG.getNode(Opc, DL, VT,
24409 DAG.getNode(ISD::TRUNCATE, DL,
24412 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24413 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24415 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24416 return DAG.getNode(Opc, DL, VT,
24417 N0.getOperand(0), N1.getOperand(0),
24418 DAG.getNode(ISD::TRUNCATE, DL,
24425 // Generate NEG and CMOV for integer abs.
24426 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24427 EVT VT = N->getValueType(0);
24429 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24430 // 8-bit integer abs to NEG and CMOV.
24431 if (VT.isInteger() && VT.getSizeInBits() == 8)
24434 SDValue N0 = N->getOperand(0);
24435 SDValue N1 = N->getOperand(1);
24438 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24439 // and change it to SUB and CMOV.
24440 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24441 N0.getOpcode() == ISD::ADD &&
24442 N0.getOperand(1) == N1 &&
24443 N1.getOpcode() == ISD::SRA &&
24444 N1.getOperand(0) == N0.getOperand(0))
24445 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24446 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24447 // Generate SUB & CMOV.
24448 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24449 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24451 SDValue Ops[] = { N0.getOperand(0), Neg,
24452 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24453 SDValue(Neg.getNode(), 1) };
24454 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24459 // Try to turn tests against the signbit in the form of:
24460 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24463 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24464 // This is only worth doing if the output type is i8.
24465 if (N->getValueType(0) != MVT::i8)
24468 SDValue N0 = N->getOperand(0);
24469 SDValue N1 = N->getOperand(1);
24471 // We should be performing an xor against a truncated shift.
24472 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24475 // Make sure we are performing an xor against one.
24476 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24479 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24480 SDValue Shift = N0.getOperand(0);
24481 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24484 // Make sure we are truncating from one of i16, i32 or i64.
24485 EVT ShiftTy = Shift.getValueType();
24486 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24489 // Make sure the shift amount extracts the sign bit.
24490 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24491 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24494 // Create a greater-than comparison against -1.
24495 // N.B. Using SETGE against 0 works but we want a canonical looking
24496 // comparison, using SETGT matches up with what TranslateX86CC.
24498 SDValue ShiftOp = Shift.getOperand(0);
24499 EVT ShiftOpTy = ShiftOp.getValueType();
24500 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24501 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24505 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24506 TargetLowering::DAGCombinerInfo &DCI,
24507 const X86Subtarget *Subtarget) {
24508 if (DCI.isBeforeLegalizeOps())
24511 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24514 if (Subtarget->hasCMov())
24515 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24521 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24522 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24523 TargetLowering::DAGCombinerInfo &DCI,
24524 const X86Subtarget *Subtarget) {
24525 LoadSDNode *Ld = cast<LoadSDNode>(N);
24526 EVT RegVT = Ld->getValueType(0);
24527 EVT MemVT = Ld->getMemoryVT();
24529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24531 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24532 // into two 16-byte operations.
24533 ISD::LoadExtType Ext = Ld->getExtensionType();
24535 unsigned AddressSpace = Ld->getAddressSpace();
24536 unsigned Alignment = Ld->getAlignment();
24537 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24538 Ext == ISD::NON_EXTLOAD &&
24539 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24540 AddressSpace, Alignment, &Fast) && !Fast) {
24541 unsigned NumElems = RegVT.getVectorNumElements();
24545 SDValue Ptr = Ld->getBasePtr();
24546 SDValue Increment =
24547 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24549 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24551 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24552 Ld->getPointerInfo(), Ld->isVolatile(),
24553 Ld->isNonTemporal(), Ld->isInvariant(),
24555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24556 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24557 Ld->getPointerInfo(), Ld->isVolatile(),
24558 Ld->isNonTemporal(), Ld->isInvariant(),
24559 std::min(16U, Alignment));
24560 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24562 Load2.getValue(1));
24564 SDValue NewVec = DAG.getUNDEF(RegVT);
24565 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24566 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24567 return DCI.CombineTo(N, NewVec, TF, true);
24573 /// PerformMLOADCombine - Resolve extending loads
24574 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24575 TargetLowering::DAGCombinerInfo &DCI,
24576 const X86Subtarget *Subtarget) {
24577 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24578 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24581 EVT VT = Mld->getValueType(0);
24582 unsigned NumElems = VT.getVectorNumElements();
24583 EVT LdVT = Mld->getMemoryVT();
24586 assert(LdVT != VT && "Cannot extend to the same type");
24587 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24588 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24589 // From, To sizes and ElemCount must be pow of two
24590 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24591 "Unexpected size for extending masked load");
24593 unsigned SizeRatio = ToSz / FromSz;
24594 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24596 // Create a type on which we perform the shuffle
24597 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24598 LdVT.getScalarType(), NumElems*SizeRatio);
24599 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24601 // Convert Src0 value
24602 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24603 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24604 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24605 for (unsigned i = 0; i != NumElems; ++i)
24606 ShuffleVec[i] = i * SizeRatio;
24608 // Can't shuffle using an illegal type.
24609 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24610 && "WideVecVT should be legal");
24611 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24612 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24614 // Prepare the new mask
24616 SDValue Mask = Mld->getMask();
24617 if (Mask.getValueType() == VT) {
24618 // Mask and original value have the same type
24619 NewMask = DAG.getBitcast(WideVecVT, Mask);
24620 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24621 for (unsigned i = 0; i != NumElems; ++i)
24622 ShuffleVec[i] = i * SizeRatio;
24623 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24624 ShuffleVec[i] = NumElems*SizeRatio;
24625 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24626 DAG.getConstant(0, dl, WideVecVT),
24630 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24631 unsigned WidenNumElts = NumElems*SizeRatio;
24632 unsigned MaskNumElts = VT.getVectorNumElements();
24633 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24636 unsigned NumConcat = WidenNumElts / MaskNumElts;
24637 SmallVector<SDValue, 16> Ops(NumConcat);
24638 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24640 for (unsigned i = 1; i != NumConcat; ++i)
24643 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24646 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24647 Mld->getBasePtr(), NewMask, WideSrc0,
24648 Mld->getMemoryVT(), Mld->getMemOperand(),
24650 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24651 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24654 /// PerformMSTORECombine - Resolve truncating stores
24655 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24656 const X86Subtarget *Subtarget) {
24657 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24658 if (!Mst->isTruncatingStore())
24661 EVT VT = Mst->getValue().getValueType();
24662 unsigned NumElems = VT.getVectorNumElements();
24663 EVT StVT = Mst->getMemoryVT();
24666 assert(StVT != VT && "Cannot truncate to the same type");
24667 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24668 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24670 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24672 // The truncating store is legal in some cases. For example
24673 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24674 // are designated for truncate store.
24675 // In this case we don't need any further transformations.
24676 if (TLI.isTruncStoreLegal(VT, StVT))
24679 // From, To sizes and ElemCount must be pow of two
24680 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24681 "Unexpected size for truncating masked store");
24682 // We are going to use the original vector elt for storing.
24683 // Accumulated smaller vector elements must be a multiple of the store size.
24684 assert (((NumElems * FromSz) % ToSz) == 0 &&
24685 "Unexpected ratio for truncating masked store");
24687 unsigned SizeRatio = FromSz / ToSz;
24688 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24690 // Create a type on which we perform the shuffle
24691 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24692 StVT.getScalarType(), NumElems*SizeRatio);
24694 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24696 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
24697 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24698 for (unsigned i = 0; i != NumElems; ++i)
24699 ShuffleVec[i] = i * SizeRatio;
24701 // Can't shuffle using an illegal type.
24702 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24703 && "WideVecVT should be legal");
24705 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24706 DAG.getUNDEF(WideVecVT),
24710 SDValue Mask = Mst->getMask();
24711 if (Mask.getValueType() == VT) {
24712 // Mask and original value have the same type
24713 NewMask = DAG.getBitcast(WideVecVT, Mask);
24714 for (unsigned i = 0; i != NumElems; ++i)
24715 ShuffleVec[i] = i * SizeRatio;
24716 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24717 ShuffleVec[i] = NumElems*SizeRatio;
24718 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24719 DAG.getConstant(0, dl, WideVecVT),
24723 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24724 unsigned WidenNumElts = NumElems*SizeRatio;
24725 unsigned MaskNumElts = VT.getVectorNumElements();
24726 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24729 unsigned NumConcat = WidenNumElts / MaskNumElts;
24730 SmallVector<SDValue, 16> Ops(NumConcat);
24731 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24733 for (unsigned i = 1; i != NumConcat; ++i)
24736 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24739 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
24740 NewMask, StVT, Mst->getMemOperand(), false);
24742 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24743 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24744 const X86Subtarget *Subtarget) {
24745 StoreSDNode *St = cast<StoreSDNode>(N);
24746 EVT VT = St->getValue().getValueType();
24747 EVT StVT = St->getMemoryVT();
24749 SDValue StoredVal = St->getOperand(1);
24750 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24752 // If we are saving a concatenation of two XMM registers and 32-byte stores
24753 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24755 unsigned AddressSpace = St->getAddressSpace();
24756 unsigned Alignment = St->getAlignment();
24757 if (VT.is256BitVector() && StVT == VT &&
24758 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
24759 AddressSpace, Alignment, &Fast) && !Fast) {
24760 unsigned NumElems = VT.getVectorNumElements();
24764 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24765 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24768 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24769 SDValue Ptr0 = St->getBasePtr();
24770 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24772 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24773 St->getPointerInfo(), St->isVolatile(),
24774 St->isNonTemporal(), Alignment);
24775 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24776 St->getPointerInfo(), St->isVolatile(),
24777 St->isNonTemporal(),
24778 std::min(16U, Alignment));
24779 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24782 // Optimize trunc store (of multiple scalars) to shuffle and store.
24783 // First, pack all of the elements in one place. Next, store to memory
24784 // in fewer chunks.
24785 if (St->isTruncatingStore() && VT.isVector()) {
24786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24787 unsigned NumElems = VT.getVectorNumElements();
24788 assert(StVT != VT && "Cannot truncate to the same type");
24789 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24790 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24792 // The truncating store is legal in some cases. For example
24793 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24794 // are designated for truncate store.
24795 // In this case we don't need any further transformations.
24796 if (TLI.isTruncStoreLegal(VT, StVT))
24799 // From, To sizes and ElemCount must be pow of two
24800 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24801 // We are going to use the original vector elt for storing.
24802 // Accumulated smaller vector elements must be a multiple of the store size.
24803 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24805 unsigned SizeRatio = FromSz / ToSz;
24807 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24809 // Create a type on which we perform the shuffle
24810 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24811 StVT.getScalarType(), NumElems*SizeRatio);
24813 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24815 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
24816 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24817 for (unsigned i = 0; i != NumElems; ++i)
24818 ShuffleVec[i] = i * SizeRatio;
24820 // Can't shuffle using an illegal type.
24821 if (!TLI.isTypeLegal(WideVecVT))
24824 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24825 DAG.getUNDEF(WideVecVT),
24827 // At this point all of the data is stored at the bottom of the
24828 // register. We now need to save it to mem.
24830 // Find the largest store unit
24831 MVT StoreType = MVT::i8;
24832 for (MVT Tp : MVT::integer_valuetypes()) {
24833 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24837 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24838 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24839 (64 <= NumElems * ToSz))
24840 StoreType = MVT::f64;
24842 // Bitcast the original vector into a vector of store-size units
24843 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24844 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24845 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24846 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
24847 SmallVector<SDValue, 8> Chains;
24848 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
24849 TLI.getPointerTy(DAG.getDataLayout()));
24850 SDValue Ptr = St->getBasePtr();
24852 // Perform one or more big stores into memory.
24853 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24854 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24855 StoreType, ShuffWide,
24856 DAG.getIntPtrConstant(i, dl));
24857 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24858 St->getPointerInfo(), St->isVolatile(),
24859 St->isNonTemporal(), St->getAlignment());
24860 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24861 Chains.push_back(Ch);
24864 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24867 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24868 // the FP state in cases where an emms may be missing.
24869 // A preferable solution to the general problem is to figure out the right
24870 // places to insert EMMS. This qualifies as a quick hack.
24872 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24873 if (VT.getSizeInBits() != 64)
24876 const Function *F = DAG.getMachineFunction().getFunction();
24877 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
24879 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
24880 if ((VT.isVector() ||
24881 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24882 isa<LoadSDNode>(St->getValue()) &&
24883 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24884 St->getChain().hasOneUse() && !St->isVolatile()) {
24885 SDNode* LdVal = St->getValue().getNode();
24886 LoadSDNode *Ld = nullptr;
24887 int TokenFactorIndex = -1;
24888 SmallVector<SDValue, 8> Ops;
24889 SDNode* ChainVal = St->getChain().getNode();
24890 // Must be a store of a load. We currently handle two cases: the load
24891 // is a direct child, and it's under an intervening TokenFactor. It is
24892 // possible to dig deeper under nested TokenFactors.
24893 if (ChainVal == LdVal)
24894 Ld = cast<LoadSDNode>(St->getChain());
24895 else if (St->getValue().hasOneUse() &&
24896 ChainVal->getOpcode() == ISD::TokenFactor) {
24897 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24898 if (ChainVal->getOperand(i).getNode() == LdVal) {
24899 TokenFactorIndex = i;
24900 Ld = cast<LoadSDNode>(St->getValue());
24902 Ops.push_back(ChainVal->getOperand(i));
24906 if (!Ld || !ISD::isNormalLoad(Ld))
24909 // If this is not the MMX case, i.e. we are just turning i64 load/store
24910 // into f64 load/store, avoid the transformation if there are multiple
24911 // uses of the loaded value.
24912 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24917 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24918 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24920 if (Subtarget->is64Bit() || F64IsLegal) {
24921 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24922 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24923 Ld->getPointerInfo(), Ld->isVolatile(),
24924 Ld->isNonTemporal(), Ld->isInvariant(),
24925 Ld->getAlignment());
24926 SDValue NewChain = NewLd.getValue(1);
24927 if (TokenFactorIndex != -1) {
24928 Ops.push_back(NewChain);
24929 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24931 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24932 St->getPointerInfo(),
24933 St->isVolatile(), St->isNonTemporal(),
24934 St->getAlignment());
24937 // Otherwise, lower to two pairs of 32-bit loads / stores.
24938 SDValue LoAddr = Ld->getBasePtr();
24939 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24940 DAG.getConstant(4, LdDL, MVT::i32));
24942 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24943 Ld->getPointerInfo(),
24944 Ld->isVolatile(), Ld->isNonTemporal(),
24945 Ld->isInvariant(), Ld->getAlignment());
24946 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24947 Ld->getPointerInfo().getWithOffset(4),
24948 Ld->isVolatile(), Ld->isNonTemporal(),
24950 MinAlign(Ld->getAlignment(), 4));
24952 SDValue NewChain = LoLd.getValue(1);
24953 if (TokenFactorIndex != -1) {
24954 Ops.push_back(LoLd);
24955 Ops.push_back(HiLd);
24956 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24959 LoAddr = St->getBasePtr();
24960 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24961 DAG.getConstant(4, StDL, MVT::i32));
24963 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24964 St->getPointerInfo(),
24965 St->isVolatile(), St->isNonTemporal(),
24966 St->getAlignment());
24967 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24968 St->getPointerInfo().getWithOffset(4),
24970 St->isNonTemporal(),
24971 MinAlign(St->getAlignment(), 4));
24972 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24975 // This is similar to the above case, but here we handle a scalar 64-bit
24976 // integer store that is extracted from a vector on a 32-bit target.
24977 // If we have SSE2, then we can treat it like a floating-point double
24978 // to get past legalization. The execution dependencies fixup pass will
24979 // choose the optimal machine instruction for the store if this really is
24980 // an integer or v2f32 rather than an f64.
24981 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
24982 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
24983 SDValue OldExtract = St->getOperand(1);
24984 SDValue ExtOp0 = OldExtract.getOperand(0);
24985 unsigned VecSize = ExtOp0.getValueSizeInBits();
24986 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
24987 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
24988 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
24989 BitCast, OldExtract.getOperand(1));
24990 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
24991 St->getPointerInfo(), St->isVolatile(),
24992 St->isNonTemporal(), St->getAlignment());
24998 /// Return 'true' if this vector operation is "horizontal"
24999 /// and return the operands for the horizontal operation in LHS and RHS. A
25000 /// horizontal operation performs the binary operation on successive elements
25001 /// of its first operand, then on successive elements of its second operand,
25002 /// returning the resulting values in a vector. For example, if
25003 /// A = < float a0, float a1, float a2, float a3 >
25005 /// B = < float b0, float b1, float b2, float b3 >
25006 /// then the result of doing a horizontal operation on A and B is
25007 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25008 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25009 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25010 /// set to A, RHS to B, and the routine returns 'true'.
25011 /// Note that the binary operation should have the property that if one of the
25012 /// operands is UNDEF then the result is UNDEF.
25013 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25014 // Look for the following pattern: if
25015 // A = < float a0, float a1, float a2, float a3 >
25016 // B = < float b0, float b1, float b2, float b3 >
25018 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25019 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25020 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25021 // which is A horizontal-op B.
25023 // At least one of the operands should be a vector shuffle.
25024 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25025 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25028 MVT VT = LHS.getSimpleValueType();
25030 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25031 "Unsupported vector type for horizontal add/sub");
25033 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25034 // operate independently on 128-bit lanes.
25035 unsigned NumElts = VT.getVectorNumElements();
25036 unsigned NumLanes = VT.getSizeInBits()/128;
25037 unsigned NumLaneElts = NumElts / NumLanes;
25038 assert((NumLaneElts % 2 == 0) &&
25039 "Vector type should have an even number of elements in each lane");
25040 unsigned HalfLaneElts = NumLaneElts/2;
25042 // View LHS in the form
25043 // LHS = VECTOR_SHUFFLE A, B, LMask
25044 // If LHS is not a shuffle then pretend it is the shuffle
25045 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25046 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25049 SmallVector<int, 16> LMask(NumElts);
25050 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25051 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25052 A = LHS.getOperand(0);
25053 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25054 B = LHS.getOperand(1);
25055 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25056 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25058 if (LHS.getOpcode() != ISD::UNDEF)
25060 for (unsigned i = 0; i != NumElts; ++i)
25064 // Likewise, view RHS in the form
25065 // RHS = VECTOR_SHUFFLE C, D, RMask
25067 SmallVector<int, 16> RMask(NumElts);
25068 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25069 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25070 C = RHS.getOperand(0);
25071 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25072 D = RHS.getOperand(1);
25073 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25074 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25076 if (RHS.getOpcode() != ISD::UNDEF)
25078 for (unsigned i = 0; i != NumElts; ++i)
25082 // Check that the shuffles are both shuffling the same vectors.
25083 if (!(A == C && B == D) && !(A == D && B == C))
25086 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25087 if (!A.getNode() && !B.getNode())
25090 // If A and B occur in reverse order in RHS, then "swap" them (which means
25091 // rewriting the mask).
25093 ShuffleVectorSDNode::commuteMask(RMask);
25095 // At this point LHS and RHS are equivalent to
25096 // LHS = VECTOR_SHUFFLE A, B, LMask
25097 // RHS = VECTOR_SHUFFLE A, B, RMask
25098 // Check that the masks correspond to performing a horizontal operation.
25099 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25100 for (unsigned i = 0; i != NumLaneElts; ++i) {
25101 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25103 // Ignore any UNDEF components.
25104 if (LIdx < 0 || RIdx < 0 ||
25105 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25106 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25109 // Check that successive elements are being operated on. If not, this is
25110 // not a horizontal operation.
25111 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25112 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25113 if (!(LIdx == Index && RIdx == Index + 1) &&
25114 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25119 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25120 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25124 /// Do target-specific dag combines on floating point adds.
25125 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25126 const X86Subtarget *Subtarget) {
25127 EVT VT = N->getValueType(0);
25128 SDValue LHS = N->getOperand(0);
25129 SDValue RHS = N->getOperand(1);
25131 // Try to synthesize horizontal adds from adds of shuffles.
25132 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25133 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25134 isHorizontalBinOp(LHS, RHS, true))
25135 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25139 /// Do target-specific dag combines on floating point subs.
25140 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25141 const X86Subtarget *Subtarget) {
25142 EVT VT = N->getValueType(0);
25143 SDValue LHS = N->getOperand(0);
25144 SDValue RHS = N->getOperand(1);
25146 // Try to synthesize horizontal subs from subs of shuffles.
25147 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25148 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25149 isHorizontalBinOp(LHS, RHS, false))
25150 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25154 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25155 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
25156 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25158 // F[X]OR(0.0, x) -> x
25159 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25160 if (C->getValueAPF().isPosZero())
25161 return N->getOperand(1);
25163 // F[X]OR(x, 0.0) -> x
25164 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25165 if (C->getValueAPF().isPosZero())
25166 return N->getOperand(0);
25170 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25171 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25172 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25174 // Only perform optimizations if UnsafeMath is used.
25175 if (!DAG.getTarget().Options.UnsafeFPMath)
25178 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25179 // into FMINC and FMAXC, which are Commutative operations.
25180 unsigned NewOp = 0;
25181 switch (N->getOpcode()) {
25182 default: llvm_unreachable("unknown opcode");
25183 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25184 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25187 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25188 N->getOperand(0), N->getOperand(1));
25191 /// Do target-specific dag combines on X86ISD::FAND nodes.
25192 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25193 // FAND(0.0, x) -> 0.0
25194 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25195 if (C->getValueAPF().isPosZero())
25196 return N->getOperand(0);
25198 // FAND(x, 0.0) -> 0.0
25199 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25200 if (C->getValueAPF().isPosZero())
25201 return N->getOperand(1);
25206 /// Do target-specific dag combines on X86ISD::FANDN nodes
25207 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25208 // FANDN(0.0, x) -> x
25209 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25210 if (C->getValueAPF().isPosZero())
25211 return N->getOperand(1);
25213 // FANDN(x, 0.0) -> 0.0
25214 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25215 if (C->getValueAPF().isPosZero())
25216 return N->getOperand(1);
25221 static SDValue PerformBTCombine(SDNode *N,
25223 TargetLowering::DAGCombinerInfo &DCI) {
25224 // BT ignores high bits in the bit index operand.
25225 SDValue Op1 = N->getOperand(1);
25226 if (Op1.hasOneUse()) {
25227 unsigned BitWidth = Op1.getValueSizeInBits();
25228 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25229 APInt KnownZero, KnownOne;
25230 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25231 !DCI.isBeforeLegalizeOps());
25232 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25233 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25234 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25235 DCI.CommitTargetLoweringOpt(TLO);
25240 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25241 SDValue Op = N->getOperand(0);
25242 if (Op.getOpcode() == ISD::BITCAST)
25243 Op = Op.getOperand(0);
25244 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25245 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25246 VT.getVectorElementType().getSizeInBits() ==
25247 OpVT.getVectorElementType().getSizeInBits()) {
25248 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25253 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25254 const X86Subtarget *Subtarget) {
25255 EVT VT = N->getValueType(0);
25256 if (!VT.isVector())
25259 SDValue N0 = N->getOperand(0);
25260 SDValue N1 = N->getOperand(1);
25261 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25264 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25265 // both SSE and AVX2 since there is no sign-extended shift right
25266 // operation on a vector with 64-bit elements.
25267 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25268 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25269 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25270 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25271 SDValue N00 = N0.getOperand(0);
25273 // EXTLOAD has a better solution on AVX2,
25274 // it may be replaced with X86ISD::VSEXT node.
25275 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25276 if (!ISD::isNormalLoad(N00.getNode()))
25279 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25280 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25282 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25288 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25289 TargetLowering::DAGCombinerInfo &DCI,
25290 const X86Subtarget *Subtarget) {
25291 SDValue N0 = N->getOperand(0);
25292 EVT VT = N->getValueType(0);
25293 EVT SVT = VT.getScalarType();
25294 EVT InVT = N0.getValueType();
25295 EVT InSVT = InVT.getScalarType();
25298 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25299 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25300 // This exposes the sext to the sdivrem lowering, so that it directly extends
25301 // from AH (which we otherwise need to do contortions to access).
25302 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25303 InVT == MVT::i8 && VT == MVT::i32) {
25304 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25305 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25306 N0.getOperand(0), N0.getOperand(1));
25307 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25308 return R.getValue(1);
25311 if (!DCI.isBeforeLegalizeOps()) {
25312 if (InVT == MVT::i1) {
25313 SDValue Zero = DAG.getConstant(0, DL, VT);
25315 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25316 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25321 if (VT.isVector() && Subtarget->hasSSE2()) {
25322 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25323 EVT InVT = N.getValueType();
25324 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25325 Size / InVT.getScalarSizeInBits());
25326 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25327 DAG.getUNDEF(InVT));
25329 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25332 // If target-size is less than 128-bits, extend to a type that would extend
25333 // to 128 bits, extend that and extract the original target vector.
25334 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25335 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25336 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25337 unsigned Scale = 128 / VT.getSizeInBits();
25339 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25340 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25341 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25342 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25343 DAG.getIntPtrConstant(0, DL));
25346 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25347 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25348 if (VT.getSizeInBits() == 128 &&
25349 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25350 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25351 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25352 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25355 // On pre-AVX2 targets, split into 128-bit nodes of
25356 // ISD::SIGN_EXTEND_VECTOR_INREG.
25357 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25358 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25359 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25360 unsigned NumVecs = VT.getSizeInBits() / 128;
25361 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25362 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25363 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25365 SmallVector<SDValue, 8> Opnds;
25366 for (unsigned i = 0, Offset = 0; i != NumVecs;
25367 ++i, Offset += NumSubElts) {
25368 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25369 DAG.getIntPtrConstant(Offset, DL));
25370 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25371 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25372 Opnds.push_back(SrcVec);
25374 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25378 if (!Subtarget->hasFp256())
25381 if (VT.isVector() && VT.getSizeInBits() == 256)
25382 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25388 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25389 const X86Subtarget* Subtarget) {
25391 EVT VT = N->getValueType(0);
25393 // Let legalize expand this if it isn't a legal type yet.
25394 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25397 EVT ScalarVT = VT.getScalarType();
25398 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25399 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25400 !Subtarget->hasAVX512()))
25403 SDValue A = N->getOperand(0);
25404 SDValue B = N->getOperand(1);
25405 SDValue C = N->getOperand(2);
25407 bool NegA = (A.getOpcode() == ISD::FNEG);
25408 bool NegB = (B.getOpcode() == ISD::FNEG);
25409 bool NegC = (C.getOpcode() == ISD::FNEG);
25411 // Negative multiplication when NegA xor NegB
25412 bool NegMul = (NegA != NegB);
25414 A = A.getOperand(0);
25416 B = B.getOperand(0);
25418 C = C.getOperand(0);
25422 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25424 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25426 return DAG.getNode(Opcode, dl, VT, A, B, C);
25429 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25430 TargetLowering::DAGCombinerInfo &DCI,
25431 const X86Subtarget *Subtarget) {
25432 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25433 // (and (i32 x86isd::setcc_carry), 1)
25434 // This eliminates the zext. This transformation is necessary because
25435 // ISD::SETCC is always legalized to i8.
25437 SDValue N0 = N->getOperand(0);
25438 EVT VT = N->getValueType(0);
25440 if (N0.getOpcode() == ISD::AND &&
25442 N0.getOperand(0).hasOneUse()) {
25443 SDValue N00 = N0.getOperand(0);
25444 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25445 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25446 if (!C || C->getZExtValue() != 1)
25448 return DAG.getNode(ISD::AND, dl, VT,
25449 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25450 N00.getOperand(0), N00.getOperand(1)),
25451 DAG.getConstant(1, dl, VT));
25455 if (N0.getOpcode() == ISD::TRUNCATE &&
25457 N0.getOperand(0).hasOneUse()) {
25458 SDValue N00 = N0.getOperand(0);
25459 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25460 return DAG.getNode(ISD::AND, dl, VT,
25461 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25462 N00.getOperand(0), N00.getOperand(1)),
25463 DAG.getConstant(1, dl, VT));
25467 if (VT.is256BitVector())
25468 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25471 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25472 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25473 // This exposes the zext to the udivrem lowering, so that it directly extends
25474 // from AH (which we otherwise need to do contortions to access).
25475 if (N0.getOpcode() == ISD::UDIVREM &&
25476 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25477 (VT == MVT::i32 || VT == MVT::i64)) {
25478 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25479 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25480 N0.getOperand(0), N0.getOperand(1));
25481 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25482 return R.getValue(1);
25488 // Optimize x == -y --> x+y == 0
25489 // x != -y --> x+y != 0
25490 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25491 const X86Subtarget* Subtarget) {
25492 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25493 SDValue LHS = N->getOperand(0);
25494 SDValue RHS = N->getOperand(1);
25495 EVT VT = N->getValueType(0);
25498 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25500 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25501 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25502 LHS.getOperand(1));
25503 return DAG.getSetCC(DL, N->getValueType(0), addV,
25504 DAG.getConstant(0, DL, addV.getValueType()), CC);
25506 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25508 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25509 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25510 RHS.getOperand(1));
25511 return DAG.getSetCC(DL, N->getValueType(0), addV,
25512 DAG.getConstant(0, DL, addV.getValueType()), CC);
25515 if (VT.getScalarType() == MVT::i1 &&
25516 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25518 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25519 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25520 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25522 if (!IsSEXT0 || !IsVZero1) {
25523 // Swap the operands and update the condition code.
25524 std::swap(LHS, RHS);
25525 CC = ISD::getSetCCSwappedOperands(CC);
25527 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25528 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25529 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25532 if (IsSEXT0 && IsVZero1) {
25533 assert(VT == LHS.getOperand(0).getValueType() &&
25534 "Uexpected operand type");
25535 if (CC == ISD::SETGT)
25536 return DAG.getConstant(0, DL, VT);
25537 if (CC == ISD::SETLE)
25538 return DAG.getConstant(1, DL, VT);
25539 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25540 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25542 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25543 "Unexpected condition code!");
25544 return LHS.getOperand(0);
25551 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25552 SelectionDAG &DAG) {
25554 MVT VT = Load->getSimpleValueType(0);
25555 MVT EVT = VT.getVectorElementType();
25556 SDValue Addr = Load->getOperand(1);
25557 SDValue NewAddr = DAG.getNode(
25558 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25559 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25560 Addr.getSimpleValueType()));
25563 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25564 DAG.getMachineFunction().getMachineMemOperand(
25565 Load->getMemOperand(), 0, EVT.getStoreSize()));
25569 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25570 const X86Subtarget *Subtarget) {
25572 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25573 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25574 "X86insertps is only defined for v4x32");
25576 SDValue Ld = N->getOperand(1);
25577 if (MayFoldLoad(Ld)) {
25578 // Extract the countS bits from the immediate so we can get the proper
25579 // address when narrowing the vector load to a specific element.
25580 // When the second source op is a memory address, insertps doesn't use
25581 // countS and just gets an f32 from that address.
25582 unsigned DestIndex =
25583 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25585 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25587 // Create this as a scalar to vector to match the instruction pattern.
25588 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25589 // countS bits are ignored when loading from memory on insertps, which
25590 // means we don't need to explicitly set them to 0.
25591 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25592 LoadScalarToVector, N->getOperand(2));
25597 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25598 SDValue V0 = N->getOperand(0);
25599 SDValue V1 = N->getOperand(1);
25601 EVT VT = N->getValueType(0);
25603 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25604 // operands and changing the mask to 1. This saves us a bunch of
25605 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25606 // x86InstrInfo knows how to commute this back after instruction selection
25607 // if it would help register allocation.
25609 // TODO: If optimizing for size or a processor that doesn't suffer from
25610 // partial register update stalls, this should be transformed into a MOVSD
25611 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25613 if (VT == MVT::v2f64)
25614 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25615 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25616 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25617 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25623 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25624 // as "sbb reg,reg", since it can be extended without zext and produces
25625 // an all-ones bit which is more useful than 0/1 in some cases.
25626 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25629 return DAG.getNode(ISD::AND, DL, VT,
25630 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25631 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25633 DAG.getConstant(1, DL, VT));
25634 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25635 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25636 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25637 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25641 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25642 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25643 TargetLowering::DAGCombinerInfo &DCI,
25644 const X86Subtarget *Subtarget) {
25646 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25647 SDValue EFLAGS = N->getOperand(1);
25649 if (CC == X86::COND_A) {
25650 // Try to convert COND_A into COND_B in an attempt to facilitate
25651 // materializing "setb reg".
25653 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25654 // cannot take an immediate as its first operand.
25656 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25657 EFLAGS.getValueType().isInteger() &&
25658 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25659 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25660 EFLAGS.getNode()->getVTList(),
25661 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25662 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25663 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25667 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25668 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25670 if (CC == X86::COND_B)
25671 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25673 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25674 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25675 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25681 // Optimize branch condition evaluation.
25683 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25684 TargetLowering::DAGCombinerInfo &DCI,
25685 const X86Subtarget *Subtarget) {
25687 SDValue Chain = N->getOperand(0);
25688 SDValue Dest = N->getOperand(1);
25689 SDValue EFLAGS = N->getOperand(3);
25690 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25692 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25693 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25694 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25701 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25702 SelectionDAG &DAG) {
25703 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25704 // optimize away operation when it's from a constant.
25706 // The general transformation is:
25707 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25708 // AND(VECTOR_CMP(x,y), constant2)
25709 // constant2 = UNARYOP(constant)
25711 // Early exit if this isn't a vector operation, the operand of the
25712 // unary operation isn't a bitwise AND, or if the sizes of the operations
25713 // aren't the same.
25714 EVT VT = N->getValueType(0);
25715 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25716 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25717 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25720 // Now check that the other operand of the AND is a constant. We could
25721 // make the transformation for non-constant splats as well, but it's unclear
25722 // that would be a benefit as it would not eliminate any operations, just
25723 // perform one more step in scalar code before moving to the vector unit.
25724 if (BuildVectorSDNode *BV =
25725 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25726 // Bail out if the vector isn't a constant.
25727 if (!BV->isConstant())
25730 // Everything checks out. Build up the new and improved node.
25732 EVT IntVT = BV->getValueType(0);
25733 // Create a new constant of the appropriate type for the transformed
25735 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25736 // The AND node needs bitcasts to/from an integer vector type around it.
25737 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
25738 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25739 N->getOperand(0)->getOperand(0), MaskConst);
25740 SDValue Res = DAG.getBitcast(VT, NewAnd);
25747 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25748 const X86Subtarget *Subtarget) {
25749 SDValue Op0 = N->getOperand(0);
25750 EVT VT = N->getValueType(0);
25751 EVT InVT = Op0.getValueType();
25752 EVT InSVT = InVT.getScalarType();
25753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25755 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
25756 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
25757 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25759 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25760 InVT.getVectorNumElements());
25761 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
25763 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
25764 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
25766 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25772 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25773 const X86Subtarget *Subtarget) {
25774 // First try to optimize away the conversion entirely when it's
25775 // conditionally from a constant. Vectors only.
25776 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
25779 // Now move on to more general possibilities.
25780 SDValue Op0 = N->getOperand(0);
25781 EVT VT = N->getValueType(0);
25782 EVT InVT = Op0.getValueType();
25783 EVT InSVT = InVT.getScalarType();
25785 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
25786 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
25787 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25789 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25790 InVT.getVectorNumElements());
25791 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25792 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25795 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25796 // a 32-bit target where SSE doesn't support i64->FP operations.
25797 if (Op0.getOpcode() == ISD::LOAD) {
25798 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25799 EVT LdVT = Ld->getValueType(0);
25801 // This transformation is not supported if the result type is f16
25802 if (VT == MVT::f16)
25805 if (!Ld->isVolatile() && !VT.isVector() &&
25806 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25807 !Subtarget->is64Bit() && LdVT == MVT::i64) {
25808 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
25809 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
25810 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25817 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25818 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25819 X86TargetLowering::DAGCombinerInfo &DCI) {
25820 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25821 // the result is either zero or one (depending on the input carry bit).
25822 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25823 if (X86::isZeroNode(N->getOperand(0)) &&
25824 X86::isZeroNode(N->getOperand(1)) &&
25825 // We don't have a good way to replace an EFLAGS use, so only do this when
25827 SDValue(N, 1).use_empty()) {
25829 EVT VT = N->getValueType(0);
25830 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
25831 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25832 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25833 DAG.getConstant(X86::COND_B, DL,
25836 DAG.getConstant(1, DL, VT));
25837 return DCI.CombineTo(N, Res1, CarryOut);
25843 // fold (add Y, (sete X, 0)) -> adc 0, Y
25844 // (add Y, (setne X, 0)) -> sbb -1, Y
25845 // (sub (sete X, 0), Y) -> sbb 0, Y
25846 // (sub (setne X, 0), Y) -> adc -1, Y
25847 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25850 // Look through ZExts.
25851 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25852 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25855 SDValue SetCC = Ext.getOperand(0);
25856 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25859 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25860 if (CC != X86::COND_E && CC != X86::COND_NE)
25863 SDValue Cmp = SetCC.getOperand(1);
25864 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25865 !X86::isZeroNode(Cmp.getOperand(1)) ||
25866 !Cmp.getOperand(0).getValueType().isInteger())
25869 SDValue CmpOp0 = Cmp.getOperand(0);
25870 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25871 DAG.getConstant(1, DL, CmpOp0.getValueType()));
25873 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25874 if (CC == X86::COND_NE)
25875 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25876 DL, OtherVal.getValueType(), OtherVal,
25877 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
25879 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25880 DL, OtherVal.getValueType(), OtherVal,
25881 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
25884 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25885 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25886 const X86Subtarget *Subtarget) {
25887 EVT VT = N->getValueType(0);
25888 SDValue Op0 = N->getOperand(0);
25889 SDValue Op1 = N->getOperand(1);
25891 // Try to synthesize horizontal adds from adds of shuffles.
25892 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25893 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25894 isHorizontalBinOp(Op0, Op1, true))
25895 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25897 return OptimizeConditionalInDecrement(N, DAG);
25900 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25901 const X86Subtarget *Subtarget) {
25902 SDValue Op0 = N->getOperand(0);
25903 SDValue Op1 = N->getOperand(1);
25905 // X86 can't encode an immediate LHS of a sub. See if we can push the
25906 // negation into a preceding instruction.
25907 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25908 // If the RHS of the sub is a XOR with one use and a constant, invert the
25909 // immediate. Then add one to the LHS of the sub so we can turn
25910 // X-Y -> X+~Y+1, saving one register.
25911 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25912 isa<ConstantSDNode>(Op1.getOperand(1))) {
25913 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25914 EVT VT = Op0.getValueType();
25915 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25917 DAG.getConstant(~XorC, SDLoc(Op1), VT));
25918 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25919 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
25923 // Try to synthesize horizontal adds from adds of shuffles.
25924 EVT VT = N->getValueType(0);
25925 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25926 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25927 isHorizontalBinOp(Op0, Op1, true))
25928 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25930 return OptimizeConditionalInDecrement(N, DAG);
25933 /// performVZEXTCombine - Performs build vector combines
25934 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25935 TargetLowering::DAGCombinerInfo &DCI,
25936 const X86Subtarget *Subtarget) {
25938 MVT VT = N->getSimpleValueType(0);
25939 SDValue Op = N->getOperand(0);
25940 MVT OpVT = Op.getSimpleValueType();
25941 MVT OpEltVT = OpVT.getVectorElementType();
25942 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25944 // (vzext (bitcast (vzext (x)) -> (vzext x)
25946 while (V.getOpcode() == ISD::BITCAST)
25947 V = V.getOperand(0);
25949 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25950 MVT InnerVT = V.getSimpleValueType();
25951 MVT InnerEltVT = InnerVT.getVectorElementType();
25953 // If the element sizes match exactly, we can just do one larger vzext. This
25954 // is always an exact type match as vzext operates on integer types.
25955 if (OpEltVT == InnerEltVT) {
25956 assert(OpVT == InnerVT && "Types must match for vzext!");
25957 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25960 // The only other way we can combine them is if only a single element of the
25961 // inner vzext is used in the input to the outer vzext.
25962 if (InnerEltVT.getSizeInBits() < InputBits)
25965 // In this case, the inner vzext is completely dead because we're going to
25966 // only look at bits inside of the low element. Just do the outer vzext on
25967 // a bitcast of the input to the inner.
25968 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
25971 // Check if we can bypass extracting and re-inserting an element of an input
25972 // vector. Essentially:
25973 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25974 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25975 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25976 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25977 SDValue ExtractedV = V.getOperand(0);
25978 SDValue OrigV = ExtractedV.getOperand(0);
25979 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25980 if (ExtractIdx->getZExtValue() == 0) {
25981 MVT OrigVT = OrigV.getSimpleValueType();
25982 // Extract a subvector if necessary...
25983 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25984 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25985 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25986 OrigVT.getVectorNumElements() / Ratio);
25987 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25988 DAG.getIntPtrConstant(0, DL));
25990 Op = DAG.getBitcast(OpVT, OrigV);
25991 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25998 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25999 DAGCombinerInfo &DCI) const {
26000 SelectionDAG &DAG = DCI.DAG;
26001 switch (N->getOpcode()) {
26003 case ISD::EXTRACT_VECTOR_ELT:
26004 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26007 case X86ISD::SHRUNKBLEND:
26008 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26009 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26010 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26011 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26012 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26013 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26014 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26017 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26018 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26019 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26020 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26021 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26022 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26023 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26024 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26025 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26026 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26027 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26028 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26030 case X86ISD::FOR: return PerformFORCombine(N, DAG);
26032 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26033 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26034 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26035 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26036 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26037 case ISD::ANY_EXTEND:
26038 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26039 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26040 case ISD::SIGN_EXTEND_INREG:
26041 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26042 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26043 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26044 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26045 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26046 case X86ISD::SHUFP: // Handle all target specific shuffles
26047 case X86ISD::PALIGNR:
26048 case X86ISD::UNPCKH:
26049 case X86ISD::UNPCKL:
26050 case X86ISD::MOVHLPS:
26051 case X86ISD::MOVLHPS:
26052 case X86ISD::PSHUFB:
26053 case X86ISD::PSHUFD:
26054 case X86ISD::PSHUFHW:
26055 case X86ISD::PSHUFLW:
26056 case X86ISD::MOVSS:
26057 case X86ISD::MOVSD:
26058 case X86ISD::VPERMILPI:
26059 case X86ISD::VPERM2X128:
26060 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26061 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26062 case X86ISD::INSERTPS: {
26063 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26064 return PerformINSERTPSCombine(N, DAG, Subtarget);
26067 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26073 /// isTypeDesirableForOp - Return true if the target has native support for
26074 /// the specified value type and it is 'desirable' to use the type for the
26075 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26076 /// instruction encodings are longer and some i16 instructions are slow.
26077 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26078 if (!isTypeLegal(VT))
26080 if (VT != MVT::i16)
26087 case ISD::SIGN_EXTEND:
26088 case ISD::ZERO_EXTEND:
26089 case ISD::ANY_EXTEND:
26102 /// IsDesirableToPromoteOp - This method query the target whether it is
26103 /// beneficial for dag combiner to promote the specified node. If true, it
26104 /// should return the desired promotion type by reference.
26105 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26106 EVT VT = Op.getValueType();
26107 if (VT != MVT::i16)
26110 bool Promote = false;
26111 bool Commute = false;
26112 switch (Op.getOpcode()) {
26115 LoadSDNode *LD = cast<LoadSDNode>(Op);
26116 // If the non-extending load has a single use and it's not live out, then it
26117 // might be folded.
26118 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26119 Op.hasOneUse()*/) {
26120 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26121 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26122 // The only case where we'd want to promote LOAD (rather then it being
26123 // promoted as an operand is when it's only use is liveout.
26124 if (UI->getOpcode() != ISD::CopyToReg)
26131 case ISD::SIGN_EXTEND:
26132 case ISD::ZERO_EXTEND:
26133 case ISD::ANY_EXTEND:
26138 SDValue N0 = Op.getOperand(0);
26139 // Look out for (store (shl (load), x)).
26140 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26153 SDValue N0 = Op.getOperand(0);
26154 SDValue N1 = Op.getOperand(1);
26155 if (!Commute && MayFoldLoad(N1))
26157 // Avoid disabling potential load folding opportunities.
26158 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26160 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26170 //===----------------------------------------------------------------------===//
26171 // X86 Inline Assembly Support
26172 //===----------------------------------------------------------------------===//
26174 // Helper to match a string separated by whitespace.
26175 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26176 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26178 for (StringRef Piece : Pieces) {
26179 if (!S.startswith(Piece)) // Check if the piece matches.
26182 S = S.substr(Piece.size());
26183 StringRef::size_type Pos = S.find_first_not_of(" \t");
26184 if (Pos == 0) // We matched a prefix.
26193 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26195 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26196 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26197 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26198 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26200 if (AsmPieces.size() == 3)
26202 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26209 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26210 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26212 std::string AsmStr = IA->getAsmString();
26214 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26215 if (!Ty || Ty->getBitWidth() % 16 != 0)
26218 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26219 SmallVector<StringRef, 4> AsmPieces;
26220 SplitString(AsmStr, AsmPieces, ";\n");
26222 switch (AsmPieces.size()) {
26223 default: return false;
26225 // FIXME: this should verify that we are targeting a 486 or better. If not,
26226 // we will turn this bswap into something that will be lowered to logical
26227 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26228 // lower so don't worry about this.
26230 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26231 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26232 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26233 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26234 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26235 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26236 // No need to check constraints, nothing other than the equivalent of
26237 // "=r,0" would be valid here.
26238 return IntrinsicLowering::LowerToByteSwap(CI);
26241 // rorw $$8, ${0:w} --> llvm.bswap.i16
26242 if (CI->getType()->isIntegerTy(16) &&
26243 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26244 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26245 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26247 StringRef ConstraintsStr = IA->getConstraintString();
26248 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26249 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26250 if (clobbersFlagRegisters(AsmPieces))
26251 return IntrinsicLowering::LowerToByteSwap(CI);
26255 if (CI->getType()->isIntegerTy(32) &&
26256 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26257 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26258 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26259 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26261 StringRef ConstraintsStr = IA->getConstraintString();
26262 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26263 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26264 if (clobbersFlagRegisters(AsmPieces))
26265 return IntrinsicLowering::LowerToByteSwap(CI);
26268 if (CI->getType()->isIntegerTy(64)) {
26269 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26270 if (Constraints.size() >= 2 &&
26271 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26272 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26273 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26274 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26275 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26276 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26277 return IntrinsicLowering::LowerToByteSwap(CI);
26285 /// getConstraintType - Given a constraint letter, return the type of
26286 /// constraint it is for this target.
26287 X86TargetLowering::ConstraintType
26288 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26289 if (Constraint.size() == 1) {
26290 switch (Constraint[0]) {
26301 return C_RegisterClass;
26325 return TargetLowering::getConstraintType(Constraint);
26328 /// Examine constraint type and operand type and determine a weight value.
26329 /// This object must already have been set up with the operand type
26330 /// and the current alternative constraint selected.
26331 TargetLowering::ConstraintWeight
26332 X86TargetLowering::getSingleConstraintMatchWeight(
26333 AsmOperandInfo &info, const char *constraint) const {
26334 ConstraintWeight weight = CW_Invalid;
26335 Value *CallOperandVal = info.CallOperandVal;
26336 // If we don't have a value, we can't do a match,
26337 // but allow it at the lowest weight.
26338 if (!CallOperandVal)
26340 Type *type = CallOperandVal->getType();
26341 // Look at the constraint type.
26342 switch (*constraint) {
26344 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26355 if (CallOperandVal->getType()->isIntegerTy())
26356 weight = CW_SpecificReg;
26361 if (type->isFloatingPointTy())
26362 weight = CW_SpecificReg;
26365 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26366 weight = CW_SpecificReg;
26370 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26371 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26372 weight = CW_Register;
26375 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26376 if (C->getZExtValue() <= 31)
26377 weight = CW_Constant;
26381 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26382 if (C->getZExtValue() <= 63)
26383 weight = CW_Constant;
26387 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26388 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26389 weight = CW_Constant;
26393 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26394 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26395 weight = CW_Constant;
26399 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26400 if (C->getZExtValue() <= 3)
26401 weight = CW_Constant;
26405 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26406 if (C->getZExtValue() <= 0xff)
26407 weight = CW_Constant;
26412 if (isa<ConstantFP>(CallOperandVal)) {
26413 weight = CW_Constant;
26417 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26418 if ((C->getSExtValue() >= -0x80000000LL) &&
26419 (C->getSExtValue() <= 0x7fffffffLL))
26420 weight = CW_Constant;
26424 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26425 if (C->getZExtValue() <= 0xffffffff)
26426 weight = CW_Constant;
26433 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26434 /// with another that has more specific requirements based on the type of the
26435 /// corresponding operand.
26436 const char *X86TargetLowering::
26437 LowerXConstraint(EVT ConstraintVT) const {
26438 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26439 // 'f' like normal targets.
26440 if (ConstraintVT.isFloatingPoint()) {
26441 if (Subtarget->hasSSE2())
26443 if (Subtarget->hasSSE1())
26447 return TargetLowering::LowerXConstraint(ConstraintVT);
26450 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26451 /// vector. If it is invalid, don't add anything to Ops.
26452 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26453 std::string &Constraint,
26454 std::vector<SDValue>&Ops,
26455 SelectionDAG &DAG) const {
26458 // Only support length 1 constraints for now.
26459 if (Constraint.length() > 1) return;
26461 char ConstraintLetter = Constraint[0];
26462 switch (ConstraintLetter) {
26465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26466 if (C->getZExtValue() <= 31) {
26467 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26468 Op.getValueType());
26474 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26475 if (C->getZExtValue() <= 63) {
26476 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26477 Op.getValueType());
26483 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26484 if (isInt<8>(C->getSExtValue())) {
26485 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26486 Op.getValueType());
26492 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26493 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26494 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26495 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26496 Op.getValueType());
26502 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26503 if (C->getZExtValue() <= 3) {
26504 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26505 Op.getValueType());
26511 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26512 if (C->getZExtValue() <= 255) {
26513 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26514 Op.getValueType());
26520 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26521 if (C->getZExtValue() <= 127) {
26522 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26523 Op.getValueType());
26529 // 32-bit signed value
26530 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26531 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26532 C->getSExtValue())) {
26533 // Widen to 64 bits here to get it sign extended.
26534 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26537 // FIXME gcc accepts some relocatable values here too, but only in certain
26538 // memory models; it's complicated.
26543 // 32-bit unsigned value
26544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26545 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26546 C->getZExtValue())) {
26547 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26548 Op.getValueType());
26552 // FIXME gcc accepts some relocatable values here too, but only in certain
26553 // memory models; it's complicated.
26557 // Literal immediates are always ok.
26558 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26559 // Widen to 64 bits here to get it sign extended.
26560 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26564 // In any sort of PIC mode addresses need to be computed at runtime by
26565 // adding in a register or some sort of table lookup. These can't
26566 // be used as immediates.
26567 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26570 // If we are in non-pic codegen mode, we allow the address of a global (with
26571 // an optional displacement) to be used with 'i'.
26572 GlobalAddressSDNode *GA = nullptr;
26573 int64_t Offset = 0;
26575 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26577 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26578 Offset += GA->getOffset();
26580 } else if (Op.getOpcode() == ISD::ADD) {
26581 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26582 Offset += C->getZExtValue();
26583 Op = Op.getOperand(0);
26586 } else if (Op.getOpcode() == ISD::SUB) {
26587 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26588 Offset += -C->getZExtValue();
26589 Op = Op.getOperand(0);
26594 // Otherwise, this isn't something we can handle, reject it.
26598 const GlobalValue *GV = GA->getGlobal();
26599 // If we require an extra load to get this address, as in PIC mode, we
26600 // can't accept it.
26601 if (isGlobalStubReference(
26602 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26605 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26606 GA->getValueType(0), Offset);
26611 if (Result.getNode()) {
26612 Ops.push_back(Result);
26615 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26618 std::pair<unsigned, const TargetRegisterClass *>
26619 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26620 StringRef Constraint,
26622 // First, see if this is a constraint that directly corresponds to an LLVM
26624 if (Constraint.size() == 1) {
26625 // GCC Constraint Letters
26626 switch (Constraint[0]) {
26628 // TODO: Slight differences here in allocation order and leaving
26629 // RIP in the class. Do they matter any more here than they do
26630 // in the normal allocation?
26631 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26632 if (Subtarget->is64Bit()) {
26633 if (VT == MVT::i32 || VT == MVT::f32)
26634 return std::make_pair(0U, &X86::GR32RegClass);
26635 if (VT == MVT::i16)
26636 return std::make_pair(0U, &X86::GR16RegClass);
26637 if (VT == MVT::i8 || VT == MVT::i1)
26638 return std::make_pair(0U, &X86::GR8RegClass);
26639 if (VT == MVT::i64 || VT == MVT::f64)
26640 return std::make_pair(0U, &X86::GR64RegClass);
26643 // 32-bit fallthrough
26644 case 'Q': // Q_REGS
26645 if (VT == MVT::i32 || VT == MVT::f32)
26646 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26647 if (VT == MVT::i16)
26648 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26649 if (VT == MVT::i8 || VT == MVT::i1)
26650 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26651 if (VT == MVT::i64)
26652 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26654 case 'r': // GENERAL_REGS
26655 case 'l': // INDEX_REGS
26656 if (VT == MVT::i8 || VT == MVT::i1)
26657 return std::make_pair(0U, &X86::GR8RegClass);
26658 if (VT == MVT::i16)
26659 return std::make_pair(0U, &X86::GR16RegClass);
26660 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26661 return std::make_pair(0U, &X86::GR32RegClass);
26662 return std::make_pair(0U, &X86::GR64RegClass);
26663 case 'R': // LEGACY_REGS
26664 if (VT == MVT::i8 || VT == MVT::i1)
26665 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26666 if (VT == MVT::i16)
26667 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26668 if (VT == MVT::i32 || !Subtarget->is64Bit())
26669 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26670 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26671 case 'f': // FP Stack registers.
26672 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26673 // value to the correct fpstack register class.
26674 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26675 return std::make_pair(0U, &X86::RFP32RegClass);
26676 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26677 return std::make_pair(0U, &X86::RFP64RegClass);
26678 return std::make_pair(0U, &X86::RFP80RegClass);
26679 case 'y': // MMX_REGS if MMX allowed.
26680 if (!Subtarget->hasMMX()) break;
26681 return std::make_pair(0U, &X86::VR64RegClass);
26682 case 'Y': // SSE_REGS if SSE2 allowed
26683 if (!Subtarget->hasSSE2()) break;
26685 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26686 if (!Subtarget->hasSSE1()) break;
26688 switch (VT.SimpleTy) {
26690 // Scalar SSE types.
26693 return std::make_pair(0U, &X86::FR32RegClass);
26696 return std::make_pair(0U, &X86::FR64RegClass);
26704 return std::make_pair(0U, &X86::VR128RegClass);
26712 return std::make_pair(0U, &X86::VR256RegClass);
26717 return std::make_pair(0U, &X86::VR512RegClass);
26723 // Use the default implementation in TargetLowering to convert the register
26724 // constraint into a member of a register class.
26725 std::pair<unsigned, const TargetRegisterClass*> Res;
26726 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
26728 // Not found as a standard register?
26730 // Map st(0) -> st(7) -> ST0
26731 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26732 tolower(Constraint[1]) == 's' &&
26733 tolower(Constraint[2]) == 't' &&
26734 Constraint[3] == '(' &&
26735 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26736 Constraint[5] == ')' &&
26737 Constraint[6] == '}') {
26739 Res.first = X86::FP0+Constraint[4]-'0';
26740 Res.second = &X86::RFP80RegClass;
26744 // GCC allows "st(0)" to be called just plain "st".
26745 if (StringRef("{st}").equals_lower(Constraint)) {
26746 Res.first = X86::FP0;
26747 Res.second = &X86::RFP80RegClass;
26752 if (StringRef("{flags}").equals_lower(Constraint)) {
26753 Res.first = X86::EFLAGS;
26754 Res.second = &X86::CCRRegClass;
26758 // 'A' means EAX + EDX.
26759 if (Constraint == "A") {
26760 Res.first = X86::EAX;
26761 Res.second = &X86::GR32_ADRegClass;
26767 // Otherwise, check to see if this is a register class of the wrong value
26768 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26769 // turn into {ax},{dx}.
26770 // MVT::Other is used to specify clobber names.
26771 if (Res.second->hasType(VT) || VT == MVT::Other)
26772 return Res; // Correct type already, nothing to do.
26774 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
26775 // return "eax". This should even work for things like getting 64bit integer
26776 // registers when given an f64 type.
26777 const TargetRegisterClass *Class = Res.second;
26778 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
26779 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
26780 unsigned Size = VT.getSizeInBits();
26781 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
26782 : Size == 16 ? MVT::i16
26783 : Size == 32 ? MVT::i32
26784 : Size == 64 ? MVT::i64
26786 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
26788 Res.first = DestReg;
26789 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
26790 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
26791 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
26792 : &X86::GR64RegClass;
26793 assert(Res.second->contains(Res.first) && "Register in register class");
26795 // No register found/type mismatch.
26797 Res.second = nullptr;
26799 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
26800 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
26801 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
26802 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
26803 Class == &X86::VR512RegClass) {
26804 // Handle references to XMM physical registers that got mapped into the
26805 // wrong class. This can happen with constraints like {xmm0} where the
26806 // target independent register mapper will just pick the first match it can
26807 // find, ignoring the required type.
26809 if (VT == MVT::f32 || VT == MVT::i32)
26810 Res.second = &X86::FR32RegClass;
26811 else if (VT == MVT::f64 || VT == MVT::i64)
26812 Res.second = &X86::FR64RegClass;
26813 else if (X86::VR128RegClass.hasType(VT))
26814 Res.second = &X86::VR128RegClass;
26815 else if (X86::VR256RegClass.hasType(VT))
26816 Res.second = &X86::VR256RegClass;
26817 else if (X86::VR512RegClass.hasType(VT))
26818 Res.second = &X86::VR512RegClass;
26820 // Type mismatch and not a clobber: Return an error;
26822 Res.second = nullptr;
26829 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
26830 const AddrMode &AM, Type *Ty,
26831 unsigned AS) const {
26832 // Scaling factors are not free at all.
26833 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26834 // will take 2 allocations in the out of order engine instead of 1
26835 // for plain addressing mode, i.e. inst (reg1).
26837 // vaddps (%rsi,%drx), %ymm0, %ymm1
26838 // Requires two allocations (one for the load, one for the computation)
26840 // vaddps (%rsi), %ymm0, %ymm1
26841 // Requires just 1 allocation, i.e., freeing allocations for other operations
26842 // and having less micro operations to execute.
26844 // For some X86 architectures, this is even worse because for instance for
26845 // stores, the complex addressing mode forces the instruction to use the
26846 // "load" ports instead of the dedicated "store" port.
26847 // E.g., on Haswell:
26848 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26849 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26850 if (isLegalAddressingMode(DL, AM, Ty, AS))
26851 // Scale represents reg2 * scale, thus account for 1
26852 // as soon as we use a second register.
26853 return AM.Scale != 0;
26857 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
26858 // Integer division on x86 is expensive. However, when aggressively optimizing
26859 // for code size, we prefer to use a div instruction, as it is usually smaller
26860 // than the alternative sequence.
26861 // The exception to this is vector division. Since x86 doesn't have vector
26862 // integer division, leaving the division as-is is a loss even in terms of
26863 // size, because it will have to be scalarized, while the alternative code
26864 // sequence can be performed in vector form.
26865 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
26866 Attribute::MinSize);
26867 return OptSize && !VT.isVector();